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TARGET_NUCLEO_L011K4/TOOLCHAIN_ARM_MICRO/stm32l0xx_ll_lpuart.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_NUCLEO_L011K4/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_lpuart.h@167:84c0a372a020

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	157:e7ca05fa8600	1	/**
AnnaBridge	157:e7ca05fa8600	2	******************************************************************************
AnnaBridge	157:e7ca05fa8600	3	* @file stm32l0xx_ll_lpuart.h
AnnaBridge	157:e7ca05fa8600	4	* @author MCD Application Team
AnnaBridge	157:e7ca05fa8600	5	* @brief Header file of LPUART LL module.
AnnaBridge	157:e7ca05fa8600	6	******************************************************************************
AnnaBridge	157:e7ca05fa8600	7	* @attention
AnnaBridge	157:e7ca05fa8600	8	*
AnnaBridge	157:e7ca05fa8600	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	157:e7ca05fa8600	10	*
AnnaBridge	157:e7ca05fa8600	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	157:e7ca05fa8600	12	* are permitted provided that the following conditions are met:
AnnaBridge	157:e7ca05fa8600	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	157:e7ca05fa8600	14	* this list of conditions and the following disclaimer.
AnnaBridge	157:e7ca05fa8600	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	157:e7ca05fa8600	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	157:e7ca05fa8600	17	* and/or other materials provided with the distribution.
AnnaBridge	157:e7ca05fa8600	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	157:e7ca05fa8600	19	* may be used to endorse or promote products derived from this software
AnnaBridge	157:e7ca05fa8600	20	* without specific prior written permission.
AnnaBridge	157:e7ca05fa8600	21	*
AnnaBridge	157:e7ca05fa8600	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	157:e7ca05fa8600	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	157:e7ca05fa8600	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	157:e7ca05fa8600	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	157:e7ca05fa8600	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	157:e7ca05fa8600	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	157:e7ca05fa8600	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	157:e7ca05fa8600	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	157:e7ca05fa8600	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	157:e7ca05fa8600	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	157:e7ca05fa8600	32	*
AnnaBridge	157:e7ca05fa8600	33	******************************************************************************
AnnaBridge	157:e7ca05fa8600	34	*/
AnnaBridge	157:e7ca05fa8600	35
AnnaBridge	157:e7ca05fa8600	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	157:e7ca05fa8600	37	#ifndef __STM32L0xx_LL_LPUART_H
AnnaBridge	157:e7ca05fa8600	38	#define __STM32L0xx_LL_LPUART_H
AnnaBridge	157:e7ca05fa8600	39
AnnaBridge	157:e7ca05fa8600	40	#ifdef __cplusplus
AnnaBridge	157:e7ca05fa8600	41	extern "C" {
AnnaBridge	157:e7ca05fa8600	42	#endif
AnnaBridge	157:e7ca05fa8600	43
AnnaBridge	157:e7ca05fa8600	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	157:e7ca05fa8600	45	#include "stm32l0xx.h"
AnnaBridge	157:e7ca05fa8600	46
AnnaBridge	157:e7ca05fa8600	47	/** @addtogroup STM32L0xx_LL_Driver
AnnaBridge	157:e7ca05fa8600	48	* @{
AnnaBridge	157:e7ca05fa8600	49	*/
AnnaBridge	157:e7ca05fa8600	50
AnnaBridge	157:e7ca05fa8600	51	#if defined (LPUART1)
AnnaBridge	157:e7ca05fa8600	52
AnnaBridge	157:e7ca05fa8600	53	/** @defgroup LPUART_LL LPUART
AnnaBridge	157:e7ca05fa8600	54	* @{
AnnaBridge	157:e7ca05fa8600	55	*/
AnnaBridge	157:e7ca05fa8600	56
AnnaBridge	157:e7ca05fa8600	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	157:e7ca05fa8600	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	157:e7ca05fa8600	59
AnnaBridge	157:e7ca05fa8600	60	/* Private constants ---------------------------------------------------------*/
AnnaBridge	157:e7ca05fa8600	61	/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
AnnaBridge	157:e7ca05fa8600	62	* @{
AnnaBridge	157:e7ca05fa8600	63	*/
AnnaBridge	157:e7ca05fa8600	64
AnnaBridge	157:e7ca05fa8600	65	/* Defines used for the bit position in the register and perform offsets*/
AnnaBridge	157:e7ca05fa8600	66	#define LPUART_POSITION_CR1_DEDT (uint32_t)16U
AnnaBridge	157:e7ca05fa8600	67	#define LPUART_POSITION_CR1_DEAT (uint32_t)21U
AnnaBridge	157:e7ca05fa8600	68	#define LPUART_POSITION_CR2_ADD (uint32_t)24U
AnnaBridge	157:e7ca05fa8600	69
AnnaBridge	157:e7ca05fa8600	70	/* Defines used in Baud Rate related macros and corresponding register setting computation */
AnnaBridge	157:e7ca05fa8600	71	#define LPUART_LPUARTDIV_FREQ_MUL (uint32_t)(256U)
AnnaBridge	157:e7ca05fa8600	72	#define LPUART_BRR_MASK (uint32_t)(0x000FFFFFU)
AnnaBridge	157:e7ca05fa8600	73	#define LPUART_BRR_MIN_VALUE (uint32_t)(0x00000300U)
AnnaBridge	157:e7ca05fa8600	74	/**
AnnaBridge	157:e7ca05fa8600	75	* @}
AnnaBridge	157:e7ca05fa8600	76	*/
AnnaBridge	157:e7ca05fa8600	77
AnnaBridge	157:e7ca05fa8600	78
AnnaBridge	157:e7ca05fa8600	79	/* Private macros ------------------------------------------------------------*/
AnnaBridge	157:e7ca05fa8600	80	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	157:e7ca05fa8600	81	/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
AnnaBridge	157:e7ca05fa8600	82	* @{
AnnaBridge	157:e7ca05fa8600	83	*/
AnnaBridge	157:e7ca05fa8600	84	/**
AnnaBridge	157:e7ca05fa8600	85	* @}
AnnaBridge	157:e7ca05fa8600	86	*/
AnnaBridge	157:e7ca05fa8600	87	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	157:e7ca05fa8600	88
AnnaBridge	157:e7ca05fa8600	89	/* Exported types ------------------------------------------------------------*/
AnnaBridge	157:e7ca05fa8600	90	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	157:e7ca05fa8600	91	/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
AnnaBridge	157:e7ca05fa8600	92	* @{
AnnaBridge	157:e7ca05fa8600	93	*/
AnnaBridge	157:e7ca05fa8600	94
AnnaBridge	157:e7ca05fa8600	95	/**
AnnaBridge	157:e7ca05fa8600	96	* @brief LL LPUART Init Structure definition
AnnaBridge	157:e7ca05fa8600	97	*/
AnnaBridge	157:e7ca05fa8600	98	typedef struct
AnnaBridge	157:e7ca05fa8600	99	{
AnnaBridge	157:e7ca05fa8600	100	uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate.
AnnaBridge	157:e7ca05fa8600	101
AnnaBridge	157:e7ca05fa8600	102	This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/
AnnaBridge	157:e7ca05fa8600	103
AnnaBridge	157:e7ca05fa8600	104	uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
AnnaBridge	157:e7ca05fa8600	105	This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
AnnaBridge	157:e7ca05fa8600	106
AnnaBridge	157:e7ca05fa8600	107	This feature can be modified afterwards using unitary function @ref LL_LPUART_SetDataWidth().*/
AnnaBridge	157:e7ca05fa8600	108
AnnaBridge	157:e7ca05fa8600	109	uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
AnnaBridge	157:e7ca05fa8600	110	This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
AnnaBridge	157:e7ca05fa8600	111
AnnaBridge	157:e7ca05fa8600	112	This feature can be modified afterwards using unitary function @ref LL_LPUART_SetStopBitsLength().*/
AnnaBridge	157:e7ca05fa8600	113
AnnaBridge	157:e7ca05fa8600	114	uint32_t Parity; /*!< Specifies the parity mode.
AnnaBridge	157:e7ca05fa8600	115	This parameter can be a value of @ref LPUART_LL_EC_PARITY.
AnnaBridge	157:e7ca05fa8600	116
AnnaBridge	157:e7ca05fa8600	117	This feature can be modified afterwards using unitary function @ref LL_LPUART_SetParity().*/
AnnaBridge	157:e7ca05fa8600	118
AnnaBridge	157:e7ca05fa8600	119	uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
AnnaBridge	157:e7ca05fa8600	120	This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
AnnaBridge	157:e7ca05fa8600	121
AnnaBridge	157:e7ca05fa8600	122	This feature can be modified afterwards using unitary function @ref LL_LPUART_SetTransferDirection().*/
AnnaBridge	157:e7ca05fa8600	123
AnnaBridge	157:e7ca05fa8600	124	uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
AnnaBridge	157:e7ca05fa8600	125	This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
AnnaBridge	157:e7ca05fa8600	126
AnnaBridge	157:e7ca05fa8600	127	This feature can be modified afterwards using unitary function @ref LL_LPUART_SetHWFlowCtrl().*/
AnnaBridge	157:e7ca05fa8600	128
AnnaBridge	157:e7ca05fa8600	129	} LL_LPUART_InitTypeDef;
AnnaBridge	157:e7ca05fa8600	130
AnnaBridge	157:e7ca05fa8600	131	/**
AnnaBridge	157:e7ca05fa8600	132	* @}
AnnaBridge	157:e7ca05fa8600	133	*/
AnnaBridge	157:e7ca05fa8600	134	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	157:e7ca05fa8600	135
AnnaBridge	157:e7ca05fa8600	136	/* Exported constants --------------------------------------------------------*/
AnnaBridge	157:e7ca05fa8600	137	/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
AnnaBridge	157:e7ca05fa8600	138	* @{
AnnaBridge	157:e7ca05fa8600	139	*/
AnnaBridge	157:e7ca05fa8600	140
AnnaBridge	157:e7ca05fa8600	141	/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge	157:e7ca05fa8600	142	* @brief Flags defines which can be used with LL_LPUART_WriteReg function
AnnaBridge	157:e7ca05fa8600	143	* @{
AnnaBridge	157:e7ca05fa8600	144	*/
AnnaBridge	157:e7ca05fa8600	145	#define LL_LPUART_ICR_PECF USART_ICR_PECF /!< Parity error flag /
AnnaBridge	157:e7ca05fa8600	146	#define LL_LPUART_ICR_FECF USART_ICR_FECF /!< Framing error flag /
AnnaBridge	157:e7ca05fa8600	147	#define LL_LPUART_ICR_NCF USART_ICR_NCF /!< Noise detected flag /
AnnaBridge	157:e7ca05fa8600	148	#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /!< Overrun error flag /
AnnaBridge	157:e7ca05fa8600	149	#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /!< Idle line detected flag /
AnnaBridge	157:e7ca05fa8600	150	#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /!< Transmission complete flag /
AnnaBridge	157:e7ca05fa8600	151	#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /!< CTS flag /
AnnaBridge	157:e7ca05fa8600	152	#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /!< Character match flag /
AnnaBridge	157:e7ca05fa8600	153	#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /!< Wakeup from Stop mode flag /
AnnaBridge	157:e7ca05fa8600	154	/**
AnnaBridge	157:e7ca05fa8600	155	* @}
AnnaBridge	157:e7ca05fa8600	156	*/
AnnaBridge	157:e7ca05fa8600	157
AnnaBridge	157:e7ca05fa8600	158	/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	157:e7ca05fa8600	159	* @brief Flags defines which can be used with LL_LPUART_ReadReg function
AnnaBridge	157:e7ca05fa8600	160	* @{
AnnaBridge	157:e7ca05fa8600	161	*/
AnnaBridge	157:e7ca05fa8600	162	#define LL_LPUART_ISR_PE USART_ISR_PE /!< Parity error flag /
AnnaBridge	157:e7ca05fa8600	163	#define LL_LPUART_ISR_FE USART_ISR_FE /!< Framing error flag /
AnnaBridge	157:e7ca05fa8600	164	#define LL_LPUART_ISR_NE USART_ISR_NE /!< Noise detected flag /
AnnaBridge	157:e7ca05fa8600	165	#define LL_LPUART_ISR_ORE USART_ISR_ORE /!< Overrun error flag /
AnnaBridge	157:e7ca05fa8600	166	#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /!< Idle line detected flag /
AnnaBridge	157:e7ca05fa8600	167	#define LL_LPUART_ISR_RXNE USART_ISR_RXNE /!< Read data register not empty flag /
AnnaBridge	157:e7ca05fa8600	168	#define LL_LPUART_ISR_TC USART_ISR_TC /!< Transmission complete flag /
AnnaBridge	157:e7ca05fa8600	169	#define LL_LPUART_ISR_TXE USART_ISR_TXE /!< Transmit data register empty flag /
AnnaBridge	157:e7ca05fa8600	170	#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /!< CTS interrupt flag /
AnnaBridge	157:e7ca05fa8600	171	#define LL_LPUART_ISR_CTS USART_ISR_CTS /!< CTS flag /
AnnaBridge	157:e7ca05fa8600	172	#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /!< Busy flag /
AnnaBridge	157:e7ca05fa8600	173	#define LL_LPUART_ISR_CMF USART_ISR_CMF /!< Character match flag /
AnnaBridge	157:e7ca05fa8600	174	#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /!< Send break flag /
AnnaBridge	157:e7ca05fa8600	175	#define LL_LPUART_ISR_RWU USART_ISR_RWU /!< Receiver wakeup from Mute mode flag /
AnnaBridge	157:e7ca05fa8600	176	#define LL_LPUART_ISR_WUF USART_ISR_WUF /!< Wakeup from Stop mode flag /
AnnaBridge	157:e7ca05fa8600	177	#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /!< Transmit enable acknowledge flag /
AnnaBridge	157:e7ca05fa8600	178	#define LL_LPUART_ISR_REACK USART_ISR_REACK /!< Receive enable acknowledge flag /
AnnaBridge	157:e7ca05fa8600	179	/**
AnnaBridge	157:e7ca05fa8600	180	* @}
AnnaBridge	157:e7ca05fa8600	181	*/
AnnaBridge	157:e7ca05fa8600	182
AnnaBridge	157:e7ca05fa8600	183	/** @defgroup LPUART_LL_EC_IT IT Defines
AnnaBridge	157:e7ca05fa8600	184	* @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions
AnnaBridge	157:e7ca05fa8600	185	* @{
AnnaBridge	157:e7ca05fa8600	186	*/
AnnaBridge	157:e7ca05fa8600	187	#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /!< IDLE interrupt enable /
AnnaBridge	157:e7ca05fa8600	188	#define LL_LPUART_CR1_RXNEIE USART_CR1_RXNEIE /!< Read data register not empty interrupt enable /
AnnaBridge	157:e7ca05fa8600	189	#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /!< Transmission complete interrupt enable /
AnnaBridge	157:e7ca05fa8600	190	#define LL_LPUART_CR1_TXEIE USART_CR1_TXEIE /!< Transmit data register empty interrupt enable /
AnnaBridge	157:e7ca05fa8600	191	#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /!< Parity error /
AnnaBridge	157:e7ca05fa8600	192	#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /!< Character match interrupt enable /
AnnaBridge	157:e7ca05fa8600	193	#define LL_LPUART_CR3_EIE USART_CR3_EIE /!< Error interrupt enable /
AnnaBridge	157:e7ca05fa8600	194	#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /!< CTS interrupt enable /
AnnaBridge	157:e7ca05fa8600	195	#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /!< Wakeup from Stop mode interrupt enable /
AnnaBridge	157:e7ca05fa8600	196	/**
AnnaBridge	157:e7ca05fa8600	197	* @}
AnnaBridge	157:e7ca05fa8600	198	*/
AnnaBridge	157:e7ca05fa8600	199
AnnaBridge	157:e7ca05fa8600	200	/** @defgroup LPUART_LL_EC_DIRECTION Direction
AnnaBridge	157:e7ca05fa8600	201	* @{
AnnaBridge	157:e7ca05fa8600	202	*/
AnnaBridge	157:e7ca05fa8600	203	#define LL_LPUART_DIRECTION_NONE (uint32_t)0x00000000U /!< Transmitter and Receiver are disabled /
AnnaBridge	157:e7ca05fa8600	204	#define LL_LPUART_DIRECTION_RX USART_CR1_RE /!< Transmitter is disabled and Receiver is enabled /
AnnaBridge	157:e7ca05fa8600	205	#define LL_LPUART_DIRECTION_TX USART_CR1_TE /!< Transmitter is enabled and Receiver is disabled /
AnnaBridge	157:e7ca05fa8600	206	#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE \|USART_CR1_RE) /!< Transmitter and Receiver are enabled /
AnnaBridge	157:e7ca05fa8600	207	/**
AnnaBridge	157:e7ca05fa8600	208	* @}
AnnaBridge	157:e7ca05fa8600	209	*/
AnnaBridge	157:e7ca05fa8600	210
AnnaBridge	157:e7ca05fa8600	211	/** @defgroup LPUART_LL_EC_PARITY Parity Control
AnnaBridge	157:e7ca05fa8600	212	* @{
AnnaBridge	157:e7ca05fa8600	213	*/
AnnaBridge	157:e7ca05fa8600	214	#define LL_LPUART_PARITY_NONE (uint32_t)0x00000000U /!< Parity control disabled /
AnnaBridge	157:e7ca05fa8600	215	#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /!< Parity control enabled and Even Parity is selected /
AnnaBridge	157:e7ca05fa8600	216	#define LL_LPUART_PARITY_ODD (USART_CR1_PCE \| USART_CR1_PS) /!< Parity control enabled and Odd Parity is selected /
AnnaBridge	157:e7ca05fa8600	217	/**
AnnaBridge	157:e7ca05fa8600	218	* @}
AnnaBridge	157:e7ca05fa8600	219	*/
AnnaBridge	157:e7ca05fa8600	220
AnnaBridge	157:e7ca05fa8600	221	/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
AnnaBridge	157:e7ca05fa8600	222	* @{
AnnaBridge	157:e7ca05fa8600	223	*/
AnnaBridge	157:e7ca05fa8600	224	#define LL_LPUART_WAKEUP_IDLELINE (uint32_t)0x00000000U /!< LPUART wake up from Mute mode on Idle Line /
AnnaBridge	157:e7ca05fa8600	225	#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /!< LPUART wake up from Mute mode on Address Mark /
AnnaBridge	157:e7ca05fa8600	226	/**
AnnaBridge	157:e7ca05fa8600	227	* @}
AnnaBridge	157:e7ca05fa8600	228	*/
AnnaBridge	157:e7ca05fa8600	229
AnnaBridge	157:e7ca05fa8600	230	/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
AnnaBridge	157:e7ca05fa8600	231	* @{
AnnaBridge	157:e7ca05fa8600	232	*/
AnnaBridge	157:e7ca05fa8600	233	#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /!< 7 bits word length : Start bit, 7 data bits, n stop bits /
AnnaBridge	157:e7ca05fa8600	234	#define LL_LPUART_DATAWIDTH_8B (uint32_t)0x00000000U /!< 8 bits word length : Start bit, 8 data bits, n stop bits /
AnnaBridge	157:e7ca05fa8600	235	#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /!< 9 bits word length : Start bit, 9 data bits, n stop bits /
AnnaBridge	157:e7ca05fa8600	236	/**
AnnaBridge	157:e7ca05fa8600	237	* @}
AnnaBridge	157:e7ca05fa8600	238	*/
AnnaBridge	157:e7ca05fa8600	239
AnnaBridge	157:e7ca05fa8600	240	/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
AnnaBridge	157:e7ca05fa8600	241	* @{
AnnaBridge	157:e7ca05fa8600	242	*/
AnnaBridge	157:e7ca05fa8600	243	#define LL_LPUART_STOPBITS_1 (uint32_t)0x00000000U /!< 1 stop bit /
AnnaBridge	157:e7ca05fa8600	244	#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /!< 2 stop bits /
AnnaBridge	157:e7ca05fa8600	245	/**
AnnaBridge	157:e7ca05fa8600	246	* @}
AnnaBridge	157:e7ca05fa8600	247	*/
AnnaBridge	157:e7ca05fa8600	248
AnnaBridge	157:e7ca05fa8600	249	/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
AnnaBridge	157:e7ca05fa8600	250	* @{
AnnaBridge	157:e7ca05fa8600	251	*/
AnnaBridge	157:e7ca05fa8600	252	#define LL_LPUART_TXRX_STANDARD (uint32_t)0x00000000U /!< TX/RX pins are used as defined in standard pinout /
AnnaBridge	157:e7ca05fa8600	253	#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /!< TX and RX pins functions are swapped. /
AnnaBridge	157:e7ca05fa8600	254	/**
AnnaBridge	157:e7ca05fa8600	255	* @}
AnnaBridge	157:e7ca05fa8600	256	*/
AnnaBridge	157:e7ca05fa8600	257
AnnaBridge	157:e7ca05fa8600	258	/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
AnnaBridge	157:e7ca05fa8600	259	* @{
AnnaBridge	157:e7ca05fa8600	260	*/
AnnaBridge	157:e7ca05fa8600	261	#define LL_LPUART_RXPIN_LEVEL_STANDARD (uint32_t)0x00000000U /!< RX pin signal works using the standard logic levels /
AnnaBridge	157:e7ca05fa8600	262	#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /!< RX pin signal values are inverted. /
AnnaBridge	157:e7ca05fa8600	263	/**
AnnaBridge	157:e7ca05fa8600	264	* @}
AnnaBridge	157:e7ca05fa8600	265	*/
AnnaBridge	157:e7ca05fa8600	266
AnnaBridge	157:e7ca05fa8600	267	/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
AnnaBridge	157:e7ca05fa8600	268	* @{
AnnaBridge	157:e7ca05fa8600	269	*/
AnnaBridge	157:e7ca05fa8600	270	#define LL_LPUART_TXPIN_LEVEL_STANDARD (uint32_t)0x00000000U /!< TX pin signal works using the standard logic levels /
AnnaBridge	157:e7ca05fa8600	271	#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /!< TX pin signal values are inverted. /
AnnaBridge	157:e7ca05fa8600	272	/**
AnnaBridge	157:e7ca05fa8600	273	* @}
AnnaBridge	157:e7ca05fa8600	274	*/
AnnaBridge	157:e7ca05fa8600	275
AnnaBridge	157:e7ca05fa8600	276	/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
AnnaBridge	157:e7ca05fa8600	277	* @{
AnnaBridge	157:e7ca05fa8600	278	*/
AnnaBridge	157:e7ca05fa8600	279	#define LL_LPUART_BINARY_LOGIC_POSITIVE (uint32_t)0x00000000U /!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) /
AnnaBridge	157:e7ca05fa8600	280	#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. /
AnnaBridge	157:e7ca05fa8600	281	/**
AnnaBridge	157:e7ca05fa8600	282	* @}
AnnaBridge	157:e7ca05fa8600	283	*/
AnnaBridge	157:e7ca05fa8600	284
AnnaBridge	157:e7ca05fa8600	285	/** @defgroup LPUART_LL_EC_BITORDER Bit Order
AnnaBridge	157:e7ca05fa8600	286	* @{
AnnaBridge	157:e7ca05fa8600	287	*/
AnnaBridge	157:e7ca05fa8600	288	#define LL_LPUART_BITORDER_LSBFIRST (uint32_t)0x00000000U /!< data is transmitted/received with data bit 0 first, following the start bit /
AnnaBridge	157:e7ca05fa8600	289	#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /!< data is transmitted/received with the MSB first, following the start bit /
AnnaBridge	157:e7ca05fa8600	290	/**
AnnaBridge	157:e7ca05fa8600	291	* @}
AnnaBridge	157:e7ca05fa8600	292	*/
AnnaBridge	157:e7ca05fa8600	293
AnnaBridge	157:e7ca05fa8600	294	/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
AnnaBridge	157:e7ca05fa8600	295	* @{
AnnaBridge	157:e7ca05fa8600	296	*/
AnnaBridge	157:e7ca05fa8600	297	#define LL_LPUART_ADDRESS_DETECT_4B (uint32_t)0x00000000U /!< 4-bit address detection method selected /
AnnaBridge	157:e7ca05fa8600	298	#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /!< 7-bit address detection (in 8-bit data mode) method selected /
AnnaBridge	157:e7ca05fa8600	299	/**
AnnaBridge	157:e7ca05fa8600	300	* @}
AnnaBridge	157:e7ca05fa8600	301	*/
AnnaBridge	157:e7ca05fa8600	302
AnnaBridge	157:e7ca05fa8600	303	/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
AnnaBridge	157:e7ca05fa8600	304	* @{
AnnaBridge	157:e7ca05fa8600	305	*/
AnnaBridge	157:e7ca05fa8600	306	#define LL_LPUART_HWCONTROL_NONE (uint32_t)0x00000000U /!< CTS and RTS hardware flow control disabled /
AnnaBridge	157:e7ca05fa8600	307	#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /!< RTS output enabled, data is only requested when there is space in the receive buffer /
AnnaBridge	157:e7ca05fa8600	308	#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) /
AnnaBridge	157:e7ca05fa8600	309	#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE \| USART_CR3_CTSE) /!< CTS and RTS hardware flow control enabled /
AnnaBridge	157:e7ca05fa8600	310	/**
AnnaBridge	157:e7ca05fa8600	311	* @}
AnnaBridge	157:e7ca05fa8600	312	*/
AnnaBridge	157:e7ca05fa8600	313
AnnaBridge	157:e7ca05fa8600	314	/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
AnnaBridge	157:e7ca05fa8600	315	* @{
AnnaBridge	157:e7ca05fa8600	316	*/
AnnaBridge	157:e7ca05fa8600	317	#define LL_LPUART_WAKEUP_ON_ADDRESS (uint32_t)0x00000000U /!< Wake up active on address match /
AnnaBridge	157:e7ca05fa8600	318	#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /!< Wake up active on Start bit detection /
AnnaBridge	157:e7ca05fa8600	319	#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 \| USART_CR3_WUS_1) /!< Wake up active on RXNE /
AnnaBridge	157:e7ca05fa8600	320	/**
AnnaBridge	157:e7ca05fa8600	321	* @}
AnnaBridge	157:e7ca05fa8600	322	*/
AnnaBridge	157:e7ca05fa8600	323
AnnaBridge	157:e7ca05fa8600	324	/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
AnnaBridge	157:e7ca05fa8600	325	* @{
AnnaBridge	157:e7ca05fa8600	326	*/
AnnaBridge	157:e7ca05fa8600	327	#define LL_LPUART_DE_POLARITY_HIGH (uint32_t)0x00000000U /!< DE signal is active high /
AnnaBridge	157:e7ca05fa8600	328	#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /!< DE signal is active low /
AnnaBridge	157:e7ca05fa8600	329	/**
AnnaBridge	157:e7ca05fa8600	330	* @}
AnnaBridge	157:e7ca05fa8600	331	*/
AnnaBridge	157:e7ca05fa8600	332
AnnaBridge	157:e7ca05fa8600	333	/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
AnnaBridge	157:e7ca05fa8600	334	* @{
AnnaBridge	157:e7ca05fa8600	335	*/
AnnaBridge	157:e7ca05fa8600	336	#define LL_LPUART_DMA_REG_DATA_TRANSMIT (uint32_t)0U /!< Get address of data register used for transmission /
AnnaBridge	157:e7ca05fa8600	337	#define LL_LPUART_DMA_REG_DATA_RECEIVE (uint32_t)1U /!< Get address of data register used for reception /
AnnaBridge	157:e7ca05fa8600	338	/**
AnnaBridge	157:e7ca05fa8600	339	* @}
AnnaBridge	157:e7ca05fa8600	340	*/
AnnaBridge	157:e7ca05fa8600	341
AnnaBridge	157:e7ca05fa8600	342	/**
AnnaBridge	157:e7ca05fa8600	343	* @}
AnnaBridge	157:e7ca05fa8600	344	*/
AnnaBridge	157:e7ca05fa8600	345
AnnaBridge	157:e7ca05fa8600	346	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	157:e7ca05fa8600	347	/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
AnnaBridge	157:e7ca05fa8600	348	* @{
AnnaBridge	157:e7ca05fa8600	349	*/
AnnaBridge	157:e7ca05fa8600	350
AnnaBridge	157:e7ca05fa8600	351	/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	157:e7ca05fa8600	352	* @{
AnnaBridge	157:e7ca05fa8600	353	*/
AnnaBridge	157:e7ca05fa8600	354
AnnaBridge	157:e7ca05fa8600	355	/**
AnnaBridge	157:e7ca05fa8600	356	* @brief Write a value in LPUART register
AnnaBridge	157:e7ca05fa8600	357	* @param __INSTANCE__ LPUART Instance
AnnaBridge	157:e7ca05fa8600	358	* @param __REG__ Register to be written
AnnaBridge	157:e7ca05fa8600	359	* @param __VALUE__ Value to be written in the register
AnnaBridge	157:e7ca05fa8600	360	* @retval None
AnnaBridge	157:e7ca05fa8600	361	*/
AnnaBridge	157:e7ca05fa8600	362	#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	157:e7ca05fa8600	363
AnnaBridge	157:e7ca05fa8600	364	/**
AnnaBridge	157:e7ca05fa8600	365	* @brief Read a value in LPUART register
AnnaBridge	157:e7ca05fa8600	366	* @param __INSTANCE__ LPUART Instance
AnnaBridge	157:e7ca05fa8600	367	* @param __REG__ Register to be read
AnnaBridge	157:e7ca05fa8600	368	* @retval Register value
AnnaBridge	157:e7ca05fa8600	369	*/
AnnaBridge	157:e7ca05fa8600	370	#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	157:e7ca05fa8600	371	/**
AnnaBridge	157:e7ca05fa8600	372	* @}
AnnaBridge	157:e7ca05fa8600	373	*/
AnnaBridge	157:e7ca05fa8600	374
AnnaBridge	157:e7ca05fa8600	375	/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
AnnaBridge	157:e7ca05fa8600	376	* @{
AnnaBridge	157:e7ca05fa8600	377	*/
AnnaBridge	157:e7ca05fa8600	378
AnnaBridge	157:e7ca05fa8600	379	/**
AnnaBridge	157:e7ca05fa8600	380	* @brief Compute LPUARTDIV value according to Peripheral Clock and
AnnaBridge	157:e7ca05fa8600	381	* expected Baud Rate (20-bit value of LPUARTDIV is returned)
AnnaBridge	157:e7ca05fa8600	382	* @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
AnnaBridge	157:e7ca05fa8600	383	* @param __BAUDRATE__ Baud Rate value to achieve
AnnaBridge	157:e7ca05fa8600	384	* @retval LPUARTDIV value to be used for BRR register filling
AnnaBridge	157:e7ca05fa8600	385	*/
AnnaBridge	157:e7ca05fa8600	386	#define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK)
AnnaBridge	157:e7ca05fa8600	387
AnnaBridge	157:e7ca05fa8600	388	/**
AnnaBridge	157:e7ca05fa8600	389	* @}
AnnaBridge	157:e7ca05fa8600	390	*/
AnnaBridge	157:e7ca05fa8600	391
AnnaBridge	157:e7ca05fa8600	392	/**
AnnaBridge	157:e7ca05fa8600	393	* @}
AnnaBridge	157:e7ca05fa8600	394	*/
AnnaBridge	157:e7ca05fa8600	395
AnnaBridge	157:e7ca05fa8600	396	/* Exported functions --------------------------------------------------------*/
AnnaBridge	157:e7ca05fa8600	397	/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
AnnaBridge	157:e7ca05fa8600	398	* @{
AnnaBridge	157:e7ca05fa8600	399	*/
AnnaBridge	157:e7ca05fa8600	400
AnnaBridge	157:e7ca05fa8600	401	/** @defgroup LPUART_LL_EF_Configuration Configuration functions
AnnaBridge	157:e7ca05fa8600	402	* @{
AnnaBridge	157:e7ca05fa8600	403	*/
AnnaBridge	157:e7ca05fa8600	404
AnnaBridge	157:e7ca05fa8600	405	/**
AnnaBridge	157:e7ca05fa8600	406	* @brief LPUART Enable
AnnaBridge	157:e7ca05fa8600	407	* @rmtoll CR1 UE LL_LPUART_Enable
AnnaBridge	157:e7ca05fa8600	408	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	409	* @retval None
AnnaBridge	157:e7ca05fa8600	410	*/
AnnaBridge	157:e7ca05fa8600	411	__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	412	{
AnnaBridge	157:e7ca05fa8600	413	SET_BIT(LPUARTx->CR1, USART_CR1_UE);
AnnaBridge	157:e7ca05fa8600	414	}
AnnaBridge	157:e7ca05fa8600	415
AnnaBridge	157:e7ca05fa8600	416	/**
AnnaBridge	157:e7ca05fa8600	417	* @brief LPUART Disable
AnnaBridge	157:e7ca05fa8600	418	* @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
AnnaBridge	157:e7ca05fa8600	419	* and current operations are discarded. The configuration of the LPUART is kept, but all the status
AnnaBridge	157:e7ca05fa8600	420	* flags, in the LPUARTx_ISR are set to their default values.
AnnaBridge	157:e7ca05fa8600	421	* @note In order to go into low-power mode without generating errors on the line,
AnnaBridge	157:e7ca05fa8600	422	* the TE bit must be reset before and the software must wait
AnnaBridge	157:e7ca05fa8600	423	* for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
AnnaBridge	157:e7ca05fa8600	424	* The DMA requests are also reset when UE = 0 so the DMA channel must
AnnaBridge	157:e7ca05fa8600	425	* be disabled before resetting the UE bit.
AnnaBridge	157:e7ca05fa8600	426	* @rmtoll CR1 UE LL_LPUART_Disable
AnnaBridge	157:e7ca05fa8600	427	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	428	* @retval None
AnnaBridge	157:e7ca05fa8600	429	*/
AnnaBridge	157:e7ca05fa8600	430	__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	431	{
AnnaBridge	157:e7ca05fa8600	432	CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
AnnaBridge	157:e7ca05fa8600	433	}
AnnaBridge	157:e7ca05fa8600	434
AnnaBridge	157:e7ca05fa8600	435	/**
AnnaBridge	157:e7ca05fa8600	436	* @brief Indicate if LPUART is enabled
AnnaBridge	157:e7ca05fa8600	437	* @rmtoll CR1 UE LL_LPUART_IsEnabled
AnnaBridge	157:e7ca05fa8600	438	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	439	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	440	*/
AnnaBridge	157:e7ca05fa8600	441	__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	442	{
AnnaBridge	157:e7ca05fa8600	443	return (READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
AnnaBridge	157:e7ca05fa8600	444	}
AnnaBridge	157:e7ca05fa8600	445
AnnaBridge	157:e7ca05fa8600	446	/**
AnnaBridge	157:e7ca05fa8600	447	* @brief LPUART enabled in STOP Mode
AnnaBridge	157:e7ca05fa8600	448	* @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
AnnaBridge	157:e7ca05fa8600	449	* LPUART clock selection is HSI or LSE in RCC.
AnnaBridge	157:e7ca05fa8600	450	* @rmtoll CR1 UESM LL_LPUART_EnableInStopMode
AnnaBridge	157:e7ca05fa8600	451	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	452	* @retval None
AnnaBridge	157:e7ca05fa8600	453	*/
AnnaBridge	157:e7ca05fa8600	454	__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	455	{
AnnaBridge	157:e7ca05fa8600	456	SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
AnnaBridge	157:e7ca05fa8600	457	}
AnnaBridge	157:e7ca05fa8600	458
AnnaBridge	157:e7ca05fa8600	459	/**
AnnaBridge	157:e7ca05fa8600	460	* @brief LPUART disabled in STOP Mode
AnnaBridge	157:e7ca05fa8600	461	* @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
AnnaBridge	157:e7ca05fa8600	462	* @rmtoll CR1 UESM LL_LPUART_DisableInStopMode
AnnaBridge	157:e7ca05fa8600	463	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	464	* @retval None
AnnaBridge	157:e7ca05fa8600	465	*/
AnnaBridge	157:e7ca05fa8600	466	__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	467	{
AnnaBridge	157:e7ca05fa8600	468	CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
AnnaBridge	157:e7ca05fa8600	469	}
AnnaBridge	157:e7ca05fa8600	470
AnnaBridge	157:e7ca05fa8600	471	/**
AnnaBridge	157:e7ca05fa8600	472	* @brief Indicate if LPUART is enabled in STOP Mode
AnnaBridge	157:e7ca05fa8600	473	* (able to wake up MCU from Stop mode or not)
AnnaBridge	157:e7ca05fa8600	474	* @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode
AnnaBridge	157:e7ca05fa8600	475	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	476	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	477	*/
AnnaBridge	157:e7ca05fa8600	478	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	479	{
AnnaBridge	157:e7ca05fa8600	480	return (READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM));
AnnaBridge	157:e7ca05fa8600	481	}
AnnaBridge	157:e7ca05fa8600	482
AnnaBridge	157:e7ca05fa8600	483	/**
AnnaBridge	157:e7ca05fa8600	484	* @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
AnnaBridge	157:e7ca05fa8600	485	* @rmtoll CR1 RE LL_LPUART_EnableDirectionRx
AnnaBridge	157:e7ca05fa8600	486	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	487	* @retval None
AnnaBridge	157:e7ca05fa8600	488	*/
AnnaBridge	157:e7ca05fa8600	489	__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	490	{
AnnaBridge	157:e7ca05fa8600	491	SET_BIT(LPUARTx->CR1, USART_CR1_RE);
AnnaBridge	157:e7ca05fa8600	492	}
AnnaBridge	157:e7ca05fa8600	493
AnnaBridge	157:e7ca05fa8600	494	/**
AnnaBridge	157:e7ca05fa8600	495	* @brief Receiver Disable
AnnaBridge	157:e7ca05fa8600	496	* @rmtoll CR1 RE LL_LPUART_DisableDirectionRx
AnnaBridge	157:e7ca05fa8600	497	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	498	* @retval None
AnnaBridge	157:e7ca05fa8600	499	*/
AnnaBridge	157:e7ca05fa8600	500	__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	501	{
AnnaBridge	157:e7ca05fa8600	502	CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
AnnaBridge	157:e7ca05fa8600	503	}
AnnaBridge	157:e7ca05fa8600	504
AnnaBridge	157:e7ca05fa8600	505	/**
AnnaBridge	157:e7ca05fa8600	506	* @brief Transmitter Enable
AnnaBridge	157:e7ca05fa8600	507	* @rmtoll CR1 TE LL_LPUART_EnableDirectionTx
AnnaBridge	157:e7ca05fa8600	508	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	509	* @retval None
AnnaBridge	157:e7ca05fa8600	510	*/
AnnaBridge	157:e7ca05fa8600	511	__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	512	{
AnnaBridge	157:e7ca05fa8600	513	SET_BIT(LPUARTx->CR1, USART_CR1_TE);
AnnaBridge	157:e7ca05fa8600	514	}
AnnaBridge	157:e7ca05fa8600	515
AnnaBridge	157:e7ca05fa8600	516	/**
AnnaBridge	157:e7ca05fa8600	517	* @brief Transmitter Disable
AnnaBridge	157:e7ca05fa8600	518	* @rmtoll CR1 TE LL_LPUART_DisableDirectionTx
AnnaBridge	157:e7ca05fa8600	519	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	520	* @retval None
AnnaBridge	157:e7ca05fa8600	521	*/
AnnaBridge	157:e7ca05fa8600	522	__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	523	{
AnnaBridge	157:e7ca05fa8600	524	CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
AnnaBridge	157:e7ca05fa8600	525	}
AnnaBridge	157:e7ca05fa8600	526
AnnaBridge	157:e7ca05fa8600	527	/**
AnnaBridge	157:e7ca05fa8600	528	* @brief Configure simultaneously enabled/disabled states
AnnaBridge	157:e7ca05fa8600	529	* of Transmitter and Receiver
AnnaBridge	157:e7ca05fa8600	530	* @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n
AnnaBridge	157:e7ca05fa8600	531	* CR1 TE LL_LPUART_SetTransferDirection
AnnaBridge	157:e7ca05fa8600	532	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	533	* @param TransferDirection This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	534	* @arg @ref LL_LPUART_DIRECTION_NONE
AnnaBridge	157:e7ca05fa8600	535	* @arg @ref LL_LPUART_DIRECTION_RX
AnnaBridge	157:e7ca05fa8600	536	* @arg @ref LL_LPUART_DIRECTION_TX
AnnaBridge	157:e7ca05fa8600	537	* @arg @ref LL_LPUART_DIRECTION_TX_RX
AnnaBridge	157:e7ca05fa8600	538	* @retval None
AnnaBridge	157:e7ca05fa8600	539	*/
AnnaBridge	157:e7ca05fa8600	540	__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
AnnaBridge	157:e7ca05fa8600	541	{
AnnaBridge	157:e7ca05fa8600	542	MODIFY_REG(LPUARTx->CR1, USART_CR1_RE \| USART_CR1_TE, TransferDirection);
AnnaBridge	157:e7ca05fa8600	543	}
AnnaBridge	157:e7ca05fa8600	544
AnnaBridge	157:e7ca05fa8600	545	/**
AnnaBridge	157:e7ca05fa8600	546	* @brief Return enabled/disabled states of Transmitter and Receiver
AnnaBridge	157:e7ca05fa8600	547	* @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n
AnnaBridge	157:e7ca05fa8600	548	* CR1 TE LL_LPUART_GetTransferDirection
AnnaBridge	157:e7ca05fa8600	549	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	550	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	551	* @arg @ref LL_LPUART_DIRECTION_NONE
AnnaBridge	157:e7ca05fa8600	552	* @arg @ref LL_LPUART_DIRECTION_RX
AnnaBridge	157:e7ca05fa8600	553	* @arg @ref LL_LPUART_DIRECTION_TX
AnnaBridge	157:e7ca05fa8600	554	* @arg @ref LL_LPUART_DIRECTION_TX_RX
AnnaBridge	157:e7ca05fa8600	555	*/
AnnaBridge	157:e7ca05fa8600	556	__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	557	{
AnnaBridge	157:e7ca05fa8600	558	return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE \| USART_CR1_TE));
AnnaBridge	157:e7ca05fa8600	559	}
AnnaBridge	157:e7ca05fa8600	560
AnnaBridge	157:e7ca05fa8600	561	/**
AnnaBridge	157:e7ca05fa8600	562	* @brief Configure Parity (enabled/disabled and parity mode if enabled)
AnnaBridge	157:e7ca05fa8600	563	* @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
AnnaBridge	157:e7ca05fa8600	564	* When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
AnnaBridge	157:e7ca05fa8600	565	* (depending on data width) and parity is checked on the received data.
AnnaBridge	157:e7ca05fa8600	566	* @rmtoll CR1 PS LL_LPUART_SetParity\n
AnnaBridge	157:e7ca05fa8600	567	* CR1 PCE LL_LPUART_SetParity
AnnaBridge	157:e7ca05fa8600	568	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	569	* @param Parity This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	570	* @arg @ref LL_LPUART_PARITY_NONE
AnnaBridge	157:e7ca05fa8600	571	* @arg @ref LL_LPUART_PARITY_EVEN
AnnaBridge	157:e7ca05fa8600	572	* @arg @ref LL_LPUART_PARITY_ODD
AnnaBridge	157:e7ca05fa8600	573	* @retval None
AnnaBridge	157:e7ca05fa8600	574	*/
AnnaBridge	157:e7ca05fa8600	575	__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
AnnaBridge	157:e7ca05fa8600	576	{
AnnaBridge	157:e7ca05fa8600	577	MODIFY_REG(LPUARTx->CR1, USART_CR1_PS \| USART_CR1_PCE, Parity);
AnnaBridge	157:e7ca05fa8600	578	}
AnnaBridge	157:e7ca05fa8600	579
AnnaBridge	157:e7ca05fa8600	580	/**
AnnaBridge	157:e7ca05fa8600	581	* @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
AnnaBridge	157:e7ca05fa8600	582	* @rmtoll CR1 PS LL_LPUART_GetParity\n
AnnaBridge	157:e7ca05fa8600	583	* CR1 PCE LL_LPUART_GetParity
AnnaBridge	157:e7ca05fa8600	584	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	585	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	586	* @arg @ref LL_LPUART_PARITY_NONE
AnnaBridge	157:e7ca05fa8600	587	* @arg @ref LL_LPUART_PARITY_EVEN
AnnaBridge	157:e7ca05fa8600	588	* @arg @ref LL_LPUART_PARITY_ODD
AnnaBridge	157:e7ca05fa8600	589	*/
AnnaBridge	157:e7ca05fa8600	590	__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	591	{
AnnaBridge	157:e7ca05fa8600	592	return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS \| USART_CR1_PCE));
AnnaBridge	157:e7ca05fa8600	593	}
AnnaBridge	157:e7ca05fa8600	594
AnnaBridge	157:e7ca05fa8600	595	/**
AnnaBridge	157:e7ca05fa8600	596	* @brief Set Receiver Wake Up method from Mute mode.
AnnaBridge	157:e7ca05fa8600	597	* @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod
AnnaBridge	157:e7ca05fa8600	598	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	599	* @param Method This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	600	* @arg @ref LL_LPUART_WAKEUP_IDLELINE
AnnaBridge	157:e7ca05fa8600	601	* @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
AnnaBridge	157:e7ca05fa8600	602	* @retval None
AnnaBridge	157:e7ca05fa8600	603	*/
AnnaBridge	157:e7ca05fa8600	604	__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
AnnaBridge	157:e7ca05fa8600	605	{
AnnaBridge	157:e7ca05fa8600	606	MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
AnnaBridge	157:e7ca05fa8600	607	}
AnnaBridge	157:e7ca05fa8600	608
AnnaBridge	157:e7ca05fa8600	609	/**
AnnaBridge	157:e7ca05fa8600	610	* @brief Return Receiver Wake Up method from Mute mode
AnnaBridge	157:e7ca05fa8600	611	* @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod
AnnaBridge	157:e7ca05fa8600	612	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	613	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	614	* @arg @ref LL_LPUART_WAKEUP_IDLELINE
AnnaBridge	157:e7ca05fa8600	615	* @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
AnnaBridge	157:e7ca05fa8600	616	*/
AnnaBridge	157:e7ca05fa8600	617	__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	618	{
AnnaBridge	157:e7ca05fa8600	619	return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
AnnaBridge	157:e7ca05fa8600	620	}
AnnaBridge	157:e7ca05fa8600	621
AnnaBridge	157:e7ca05fa8600	622	/**
AnnaBridge	157:e7ca05fa8600	623	* @brief Set Word length (nb of data bits, excluding start and stop bits)
AnnaBridge	157:e7ca05fa8600	624	* @rmtoll CR1 M LL_LPUART_SetDataWidth
AnnaBridge	157:e7ca05fa8600	625	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	626	* @param DataWidth This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	627	* @arg @ref LL_LPUART_DATAWIDTH_7B
AnnaBridge	157:e7ca05fa8600	628	* @arg @ref LL_LPUART_DATAWIDTH_8B
AnnaBridge	157:e7ca05fa8600	629	* @arg @ref LL_LPUART_DATAWIDTH_9B
AnnaBridge	157:e7ca05fa8600	630	* @retval None
AnnaBridge	157:e7ca05fa8600	631	*/
AnnaBridge	157:e7ca05fa8600	632	__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
AnnaBridge	157:e7ca05fa8600	633	{
AnnaBridge	157:e7ca05fa8600	634	MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
AnnaBridge	157:e7ca05fa8600	635	}
AnnaBridge	157:e7ca05fa8600	636
AnnaBridge	157:e7ca05fa8600	637	/**
AnnaBridge	157:e7ca05fa8600	638	* @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
AnnaBridge	157:e7ca05fa8600	639	* @rmtoll CR1 M LL_LPUART_GetDataWidth
AnnaBridge	157:e7ca05fa8600	640	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	641	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	642	* @arg @ref LL_LPUART_DATAWIDTH_7B
AnnaBridge	157:e7ca05fa8600	643	* @arg @ref LL_LPUART_DATAWIDTH_8B
AnnaBridge	157:e7ca05fa8600	644	* @arg @ref LL_LPUART_DATAWIDTH_9B
AnnaBridge	157:e7ca05fa8600	645	*/
AnnaBridge	157:e7ca05fa8600	646	__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	647	{
AnnaBridge	157:e7ca05fa8600	648	return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
AnnaBridge	157:e7ca05fa8600	649	}
AnnaBridge	157:e7ca05fa8600	650
AnnaBridge	157:e7ca05fa8600	651	/**
AnnaBridge	157:e7ca05fa8600	652	* @brief Allow switch between Mute Mode and Active mode
AnnaBridge	157:e7ca05fa8600	653	* @rmtoll CR1 MME LL_LPUART_EnableMuteMode
AnnaBridge	157:e7ca05fa8600	654	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	655	* @retval None
AnnaBridge	157:e7ca05fa8600	656	*/
AnnaBridge	157:e7ca05fa8600	657	__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	658	{
AnnaBridge	157:e7ca05fa8600	659	SET_BIT(LPUARTx->CR1, USART_CR1_MME);
AnnaBridge	157:e7ca05fa8600	660	}
AnnaBridge	157:e7ca05fa8600	661
AnnaBridge	157:e7ca05fa8600	662	/**
AnnaBridge	157:e7ca05fa8600	663	* @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
AnnaBridge	157:e7ca05fa8600	664	* @rmtoll CR1 MME LL_LPUART_DisableMuteMode
AnnaBridge	157:e7ca05fa8600	665	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	666	* @retval None
AnnaBridge	157:e7ca05fa8600	667	*/
AnnaBridge	157:e7ca05fa8600	668	__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	669	{
AnnaBridge	157:e7ca05fa8600	670	CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
AnnaBridge	157:e7ca05fa8600	671	}
AnnaBridge	157:e7ca05fa8600	672
AnnaBridge	157:e7ca05fa8600	673	/**
AnnaBridge	157:e7ca05fa8600	674	* @brief Indicate if switch between Mute Mode and Active mode is allowed
AnnaBridge	157:e7ca05fa8600	675	* @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode
AnnaBridge	157:e7ca05fa8600	676	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	677	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	678	*/
AnnaBridge	157:e7ca05fa8600	679	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	680	{
AnnaBridge	157:e7ca05fa8600	681	return (READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME));
AnnaBridge	157:e7ca05fa8600	682	}
AnnaBridge	157:e7ca05fa8600	683
AnnaBridge	157:e7ca05fa8600	684	/**
AnnaBridge	157:e7ca05fa8600	685	* @brief Set the length of the stop bits
AnnaBridge	157:e7ca05fa8600	686	* @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength
AnnaBridge	157:e7ca05fa8600	687	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	688	* @param StopBits This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	689	* @arg @ref LL_LPUART_STOPBITS_1
AnnaBridge	157:e7ca05fa8600	690	* @arg @ref LL_LPUART_STOPBITS_2
AnnaBridge	157:e7ca05fa8600	691	* @retval None
AnnaBridge	157:e7ca05fa8600	692	*/
AnnaBridge	157:e7ca05fa8600	693	__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
AnnaBridge	157:e7ca05fa8600	694	{
AnnaBridge	157:e7ca05fa8600	695	MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
AnnaBridge	157:e7ca05fa8600	696	}
AnnaBridge	157:e7ca05fa8600	697
AnnaBridge	157:e7ca05fa8600	698	/**
AnnaBridge	157:e7ca05fa8600	699	* @brief Retrieve the length of the stop bits
AnnaBridge	157:e7ca05fa8600	700	* @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength
AnnaBridge	157:e7ca05fa8600	701	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	702	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	703	* @arg @ref LL_LPUART_STOPBITS_1
AnnaBridge	157:e7ca05fa8600	704	* @arg @ref LL_LPUART_STOPBITS_2
AnnaBridge	157:e7ca05fa8600	705	*/
AnnaBridge	157:e7ca05fa8600	706	__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	707	{
AnnaBridge	157:e7ca05fa8600	708	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
AnnaBridge	157:e7ca05fa8600	709	}
AnnaBridge	157:e7ca05fa8600	710
AnnaBridge	157:e7ca05fa8600	711	/**
AnnaBridge	157:e7ca05fa8600	712	* @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
AnnaBridge	157:e7ca05fa8600	713	* @note Call of this function is equivalent to following function call sequence :
AnnaBridge	157:e7ca05fa8600	714	* - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
AnnaBridge	157:e7ca05fa8600	715	* - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
AnnaBridge	157:e7ca05fa8600	716	* - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
AnnaBridge	157:e7ca05fa8600	717	* @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n
AnnaBridge	157:e7ca05fa8600	718	* CR1 PCE LL_LPUART_ConfigCharacter\n
AnnaBridge	157:e7ca05fa8600	719	* CR1 M LL_LPUART_ConfigCharacter\n
AnnaBridge	157:e7ca05fa8600	720	* CR2 STOP LL_LPUART_ConfigCharacter
AnnaBridge	157:e7ca05fa8600	721	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	722	* @param DataWidth This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	723	* @arg @ref LL_LPUART_DATAWIDTH_7B
AnnaBridge	157:e7ca05fa8600	724	* @arg @ref LL_LPUART_DATAWIDTH_8B
AnnaBridge	157:e7ca05fa8600	725	* @arg @ref LL_LPUART_DATAWIDTH_9B
AnnaBridge	157:e7ca05fa8600	726	* @param Parity This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	727	* @arg @ref LL_LPUART_PARITY_NONE
AnnaBridge	157:e7ca05fa8600	728	* @arg @ref LL_LPUART_PARITY_EVEN
AnnaBridge	157:e7ca05fa8600	729	* @arg @ref LL_LPUART_PARITY_ODD
AnnaBridge	157:e7ca05fa8600	730	* @param StopBits This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	731	* @arg @ref LL_LPUART_STOPBITS_1
AnnaBridge	157:e7ca05fa8600	732	* @arg @ref LL_LPUART_STOPBITS_2
AnnaBridge	157:e7ca05fa8600	733	* @retval None
AnnaBridge	157:e7ca05fa8600	734	*/
AnnaBridge	157:e7ca05fa8600	735	__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
AnnaBridge	157:e7ca05fa8600	736	uint32_t StopBits)
AnnaBridge	157:e7ca05fa8600	737	{
AnnaBridge	157:e7ca05fa8600	738	MODIFY_REG(LPUARTx->CR1, USART_CR1_PS \| USART_CR1_PCE \| USART_CR1_M, Parity \| DataWidth);
AnnaBridge	157:e7ca05fa8600	739	MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
AnnaBridge	157:e7ca05fa8600	740	}
AnnaBridge	157:e7ca05fa8600	741
AnnaBridge	157:e7ca05fa8600	742	/**
AnnaBridge	157:e7ca05fa8600	743	* @brief Configure TX/RX pins swapping setting.
AnnaBridge	157:e7ca05fa8600	744	* @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap
AnnaBridge	157:e7ca05fa8600	745	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	746	* @param SwapConfig This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	747	* @arg @ref LL_LPUART_TXRX_STANDARD
AnnaBridge	157:e7ca05fa8600	748	* @arg @ref LL_LPUART_TXRX_SWAPPED
AnnaBridge	157:e7ca05fa8600	749	* @retval None
AnnaBridge	157:e7ca05fa8600	750	*/
AnnaBridge	157:e7ca05fa8600	751	__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
AnnaBridge	157:e7ca05fa8600	752	{
AnnaBridge	157:e7ca05fa8600	753	MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
AnnaBridge	157:e7ca05fa8600	754	}
AnnaBridge	157:e7ca05fa8600	755
AnnaBridge	157:e7ca05fa8600	756	/**
AnnaBridge	157:e7ca05fa8600	757	* @brief Retrieve TX/RX pins swapping configuration.
AnnaBridge	157:e7ca05fa8600	758	* @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap
AnnaBridge	157:e7ca05fa8600	759	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	760	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	761	* @arg @ref LL_LPUART_TXRX_STANDARD
AnnaBridge	157:e7ca05fa8600	762	* @arg @ref LL_LPUART_TXRX_SWAPPED
AnnaBridge	157:e7ca05fa8600	763	*/
AnnaBridge	157:e7ca05fa8600	764	__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	765	{
AnnaBridge	157:e7ca05fa8600	766	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
AnnaBridge	157:e7ca05fa8600	767	}
AnnaBridge	157:e7ca05fa8600	768
AnnaBridge	157:e7ca05fa8600	769	/**
AnnaBridge	157:e7ca05fa8600	770	* @brief Configure RX pin active level logic
AnnaBridge	157:e7ca05fa8600	771	* @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel
AnnaBridge	157:e7ca05fa8600	772	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	773	* @param PinInvMethod This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	774	* @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
AnnaBridge	157:e7ca05fa8600	775	* @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
AnnaBridge	157:e7ca05fa8600	776	* @retval None
AnnaBridge	157:e7ca05fa8600	777	*/
AnnaBridge	157:e7ca05fa8600	778	__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
AnnaBridge	157:e7ca05fa8600	779	{
AnnaBridge	157:e7ca05fa8600	780	MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
AnnaBridge	157:e7ca05fa8600	781	}
AnnaBridge	157:e7ca05fa8600	782
AnnaBridge	157:e7ca05fa8600	783	/**
AnnaBridge	157:e7ca05fa8600	784	* @brief Retrieve RX pin active level logic configuration
AnnaBridge	157:e7ca05fa8600	785	* @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel
AnnaBridge	157:e7ca05fa8600	786	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	787	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	788	* @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
AnnaBridge	157:e7ca05fa8600	789	* @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
AnnaBridge	157:e7ca05fa8600	790	*/
AnnaBridge	157:e7ca05fa8600	791	__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	792	{
AnnaBridge	157:e7ca05fa8600	793	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
AnnaBridge	157:e7ca05fa8600	794	}
AnnaBridge	157:e7ca05fa8600	795
AnnaBridge	157:e7ca05fa8600	796	/**
AnnaBridge	157:e7ca05fa8600	797	* @brief Configure TX pin active level logic
AnnaBridge	157:e7ca05fa8600	798	* @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel
AnnaBridge	157:e7ca05fa8600	799	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	800	* @param PinInvMethod This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	801	* @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
AnnaBridge	157:e7ca05fa8600	802	* @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
AnnaBridge	157:e7ca05fa8600	803	* @retval None
AnnaBridge	157:e7ca05fa8600	804	*/
AnnaBridge	157:e7ca05fa8600	805	__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
AnnaBridge	157:e7ca05fa8600	806	{
AnnaBridge	157:e7ca05fa8600	807	MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
AnnaBridge	157:e7ca05fa8600	808	}
AnnaBridge	157:e7ca05fa8600	809
AnnaBridge	157:e7ca05fa8600	810	/**
AnnaBridge	157:e7ca05fa8600	811	* @brief Retrieve TX pin active level logic configuration
AnnaBridge	157:e7ca05fa8600	812	* @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel
AnnaBridge	157:e7ca05fa8600	813	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	814	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	815	* @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
AnnaBridge	157:e7ca05fa8600	816	* @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
AnnaBridge	157:e7ca05fa8600	817	*/
AnnaBridge	157:e7ca05fa8600	818	__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	819	{
AnnaBridge	157:e7ca05fa8600	820	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
AnnaBridge	157:e7ca05fa8600	821	}
AnnaBridge	157:e7ca05fa8600	822
AnnaBridge	157:e7ca05fa8600	823	/**
AnnaBridge	157:e7ca05fa8600	824	* @brief Configure Binary data logic.
AnnaBridge	157:e7ca05fa8600	825	*
AnnaBridge	157:e7ca05fa8600	826	* @note Allow to define how Logical data from the data register are send/received :
AnnaBridge	157:e7ca05fa8600	827	* either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
AnnaBridge	157:e7ca05fa8600	828	* @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic
AnnaBridge	157:e7ca05fa8600	829	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	830	* @param DataLogic This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	831	* @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
AnnaBridge	157:e7ca05fa8600	832	* @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
AnnaBridge	157:e7ca05fa8600	833	* @retval None
AnnaBridge	157:e7ca05fa8600	834	*/
AnnaBridge	157:e7ca05fa8600	835	__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
AnnaBridge	157:e7ca05fa8600	836	{
AnnaBridge	157:e7ca05fa8600	837	MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
AnnaBridge	157:e7ca05fa8600	838	}
AnnaBridge	157:e7ca05fa8600	839
AnnaBridge	157:e7ca05fa8600	840	/**
AnnaBridge	157:e7ca05fa8600	841	* @brief Retrieve Binary data configuration
AnnaBridge	157:e7ca05fa8600	842	* @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic
AnnaBridge	157:e7ca05fa8600	843	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	844	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	845	* @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
AnnaBridge	157:e7ca05fa8600	846	* @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
AnnaBridge	157:e7ca05fa8600	847	*/
AnnaBridge	157:e7ca05fa8600	848	__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	849	{
AnnaBridge	157:e7ca05fa8600	850	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
AnnaBridge	157:e7ca05fa8600	851	}
AnnaBridge	157:e7ca05fa8600	852
AnnaBridge	157:e7ca05fa8600	853	/**
AnnaBridge	157:e7ca05fa8600	854	* @brief Configure transfer bit order (either Less or Most Significant Bit First)
AnnaBridge	157:e7ca05fa8600	855	* @note MSB First means data is transmitted/received with the MSB first, following the start bit.
AnnaBridge	157:e7ca05fa8600	856	* LSB First means data is transmitted/received with data bit 0 first, following the start bit.
AnnaBridge	157:e7ca05fa8600	857	* @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
AnnaBridge	157:e7ca05fa8600	858	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	859	* @param BitOrder This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	860	* @arg @ref LL_LPUART_BITORDER_LSBFIRST
AnnaBridge	157:e7ca05fa8600	861	* @arg @ref LL_LPUART_BITORDER_MSBFIRST
AnnaBridge	157:e7ca05fa8600	862	* @retval None
AnnaBridge	157:e7ca05fa8600	863	*/
AnnaBridge	157:e7ca05fa8600	864	__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
AnnaBridge	157:e7ca05fa8600	865	{
AnnaBridge	157:e7ca05fa8600	866	MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
AnnaBridge	157:e7ca05fa8600	867	}
AnnaBridge	157:e7ca05fa8600	868
AnnaBridge	157:e7ca05fa8600	869	/**
AnnaBridge	157:e7ca05fa8600	870	* @brief Return transfer bit order (either Less or Most Significant Bit First)
AnnaBridge	157:e7ca05fa8600	871	* @note MSB First means data is transmitted/received with the MSB first, following the start bit.
AnnaBridge	157:e7ca05fa8600	872	* LSB First means data is transmitted/received with data bit 0 first, following the start bit.
AnnaBridge	157:e7ca05fa8600	873	* @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
AnnaBridge	157:e7ca05fa8600	874	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	875	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	876	* @arg @ref LL_LPUART_BITORDER_LSBFIRST
AnnaBridge	157:e7ca05fa8600	877	* @arg @ref LL_LPUART_BITORDER_MSBFIRST
AnnaBridge	157:e7ca05fa8600	878	*/
AnnaBridge	157:e7ca05fa8600	879	__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	880	{
AnnaBridge	157:e7ca05fa8600	881	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
AnnaBridge	157:e7ca05fa8600	882	}
AnnaBridge	157:e7ca05fa8600	883
AnnaBridge	157:e7ca05fa8600	884	/**
AnnaBridge	157:e7ca05fa8600	885	* @brief Set Address of the LPUART node.
AnnaBridge	157:e7ca05fa8600	886	* @note This is used in multiprocessor communication during Mute mode or Stop mode,
AnnaBridge	157:e7ca05fa8600	887	* for wake up with address mark detection.
AnnaBridge	157:e7ca05fa8600	888	* @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
AnnaBridge	157:e7ca05fa8600	889	* (b7-b4 should be set to 0)
AnnaBridge	157:e7ca05fa8600	890	* 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
AnnaBridge	157:e7ca05fa8600	891	* (This is used in multiprocessor communication during Mute mode or Stop mode,
AnnaBridge	157:e7ca05fa8600	892	* for wake up with 7-bit address mark detection.
AnnaBridge	157:e7ca05fa8600	893	* The MSB of the character sent by the transmitter should be equal to 1.
AnnaBridge	157:e7ca05fa8600	894	* It may also be used for character detection during normal reception,
AnnaBridge	157:e7ca05fa8600	895	* Mute mode inactive (for example, end of block detection in ModBus protocol).
AnnaBridge	157:e7ca05fa8600	896	* In this case, the whole received character (8-bit) is compared to the ADD[7:0]
AnnaBridge	157:e7ca05fa8600	897	* value and CMF flag is set on match)
AnnaBridge	157:e7ca05fa8600	898	* @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n
AnnaBridge	157:e7ca05fa8600	899	* CR2 ADDM7 LL_LPUART_ConfigNodeAddress
AnnaBridge	157:e7ca05fa8600	900	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	901	* @param AddressLen This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	902	* @arg @ref LL_LPUART_ADDRESS_DETECT_4B
AnnaBridge	157:e7ca05fa8600	903	* @arg @ref LL_LPUART_ADDRESS_DETECT_7B
AnnaBridge	157:e7ca05fa8600	904	* @param NodeAddress 4 or 7 bit Address of the LPUART node.
AnnaBridge	157:e7ca05fa8600	905	* @retval None
AnnaBridge	157:e7ca05fa8600	906	*/
AnnaBridge	157:e7ca05fa8600	907	__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
AnnaBridge	157:e7ca05fa8600	908	{
AnnaBridge	157:e7ca05fa8600	909	MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD \| USART_CR2_ADDM7,
AnnaBridge	157:e7ca05fa8600	910	(uint32_t)(AddressLen \| (NodeAddress << LPUART_POSITION_CR2_ADD)));
AnnaBridge	157:e7ca05fa8600	911	}
AnnaBridge	157:e7ca05fa8600	912
AnnaBridge	157:e7ca05fa8600	913	/**
AnnaBridge	157:e7ca05fa8600	914	* @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2.
AnnaBridge	157:e7ca05fa8600	915	* @note If 4-bit Address Detection is selected in ADDM7,
AnnaBridge	157:e7ca05fa8600	916	* only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
AnnaBridge	157:e7ca05fa8600	917	* If 7-bit Address Detection is selected in ADDM7,
AnnaBridge	157:e7ca05fa8600	918	* only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
AnnaBridge	157:e7ca05fa8600	919	* @rmtoll CR2 ADD LL_LPUART_GetNodeAddress
AnnaBridge	157:e7ca05fa8600	920	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	921	* @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
AnnaBridge	157:e7ca05fa8600	922	*/
AnnaBridge	157:e7ca05fa8600	923	__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	924	{
AnnaBridge	157:e7ca05fa8600	925	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> LPUART_POSITION_CR2_ADD);
AnnaBridge	157:e7ca05fa8600	926	}
AnnaBridge	157:e7ca05fa8600	927
AnnaBridge	157:e7ca05fa8600	928	/**
AnnaBridge	157:e7ca05fa8600	929	* @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
AnnaBridge	157:e7ca05fa8600	930	* @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen
AnnaBridge	157:e7ca05fa8600	931	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	932	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	933	* @arg @ref LL_LPUART_ADDRESS_DETECT_4B
AnnaBridge	157:e7ca05fa8600	934	* @arg @ref LL_LPUART_ADDRESS_DETECT_7B
AnnaBridge	157:e7ca05fa8600	935	*/
AnnaBridge	157:e7ca05fa8600	936	__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	937	{
AnnaBridge	157:e7ca05fa8600	938	return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
AnnaBridge	157:e7ca05fa8600	939	}
AnnaBridge	157:e7ca05fa8600	940
AnnaBridge	157:e7ca05fa8600	941	/**
AnnaBridge	157:e7ca05fa8600	942	* @brief Enable RTS HW Flow Control
AnnaBridge	157:e7ca05fa8600	943	* @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
AnnaBridge	157:e7ca05fa8600	944	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	945	* @retval None
AnnaBridge	157:e7ca05fa8600	946	*/
AnnaBridge	157:e7ca05fa8600	947	__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	948	{
AnnaBridge	157:e7ca05fa8600	949	SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
AnnaBridge	157:e7ca05fa8600	950	}
AnnaBridge	157:e7ca05fa8600	951
AnnaBridge	157:e7ca05fa8600	952	/**
AnnaBridge	157:e7ca05fa8600	953	* @brief Disable RTS HW Flow Control
AnnaBridge	157:e7ca05fa8600	954	* @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
AnnaBridge	157:e7ca05fa8600	955	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	956	* @retval None
AnnaBridge	157:e7ca05fa8600	957	*/
AnnaBridge	157:e7ca05fa8600	958	__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	959	{
AnnaBridge	157:e7ca05fa8600	960	CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
AnnaBridge	157:e7ca05fa8600	961	}
AnnaBridge	157:e7ca05fa8600	962
AnnaBridge	157:e7ca05fa8600	963	/**
AnnaBridge	157:e7ca05fa8600	964	* @brief Enable CTS HW Flow Control
AnnaBridge	157:e7ca05fa8600	965	* @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
AnnaBridge	157:e7ca05fa8600	966	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	967	* @retval None
AnnaBridge	157:e7ca05fa8600	968	*/
AnnaBridge	157:e7ca05fa8600	969	__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	970	{
AnnaBridge	157:e7ca05fa8600	971	SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
AnnaBridge	157:e7ca05fa8600	972	}
AnnaBridge	157:e7ca05fa8600	973
AnnaBridge	157:e7ca05fa8600	974	/**
AnnaBridge	157:e7ca05fa8600	975	* @brief Disable CTS HW Flow Control
AnnaBridge	157:e7ca05fa8600	976	* @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
AnnaBridge	157:e7ca05fa8600	977	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	978	* @retval None
AnnaBridge	157:e7ca05fa8600	979	*/
AnnaBridge	157:e7ca05fa8600	980	__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	981	{
AnnaBridge	157:e7ca05fa8600	982	CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
AnnaBridge	157:e7ca05fa8600	983	}
AnnaBridge	157:e7ca05fa8600	984
AnnaBridge	157:e7ca05fa8600	985	/**
AnnaBridge	157:e7ca05fa8600	986	* @brief Configure HW Flow Control mode (both CTS and RTS)
AnnaBridge	157:e7ca05fa8600	987	* @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n
AnnaBridge	157:e7ca05fa8600	988	* CR3 CTSE LL_LPUART_SetHWFlowCtrl
AnnaBridge	157:e7ca05fa8600	989	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	990	* @param HardwareFlowControl This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	991	* @arg @ref LL_LPUART_HWCONTROL_NONE
AnnaBridge	157:e7ca05fa8600	992	* @arg @ref LL_LPUART_HWCONTROL_RTS
AnnaBridge	157:e7ca05fa8600	993	* @arg @ref LL_LPUART_HWCONTROL_CTS
AnnaBridge	157:e7ca05fa8600	994	* @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
AnnaBridge	157:e7ca05fa8600	995	* @retval None
AnnaBridge	157:e7ca05fa8600	996	*/
AnnaBridge	157:e7ca05fa8600	997	__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
AnnaBridge	157:e7ca05fa8600	998	{
AnnaBridge	157:e7ca05fa8600	999	MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE \| USART_CR3_CTSE, HardwareFlowControl);
AnnaBridge	157:e7ca05fa8600	1000	}
AnnaBridge	157:e7ca05fa8600	1001
AnnaBridge	157:e7ca05fa8600	1002	/**
AnnaBridge	157:e7ca05fa8600	1003	* @brief Return HW Flow Control configuration (both CTS and RTS)
AnnaBridge	157:e7ca05fa8600	1004	* @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n
AnnaBridge	157:e7ca05fa8600	1005	* CR3 CTSE LL_LPUART_GetHWFlowCtrl
AnnaBridge	157:e7ca05fa8600	1006	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1007	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	1008	* @arg @ref LL_LPUART_HWCONTROL_NONE
AnnaBridge	157:e7ca05fa8600	1009	* @arg @ref LL_LPUART_HWCONTROL_RTS
AnnaBridge	157:e7ca05fa8600	1010	* @arg @ref LL_LPUART_HWCONTROL_CTS
AnnaBridge	157:e7ca05fa8600	1011	* @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
AnnaBridge	157:e7ca05fa8600	1012	*/
AnnaBridge	157:e7ca05fa8600	1013	__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1014	{
AnnaBridge	157:e7ca05fa8600	1015	return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE \| USART_CR3_CTSE));
AnnaBridge	157:e7ca05fa8600	1016	}
AnnaBridge	157:e7ca05fa8600	1017
AnnaBridge	157:e7ca05fa8600	1018	/**
AnnaBridge	157:e7ca05fa8600	1019	* @brief Enable Overrun detection
AnnaBridge	157:e7ca05fa8600	1020	* @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect
AnnaBridge	157:e7ca05fa8600	1021	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1022	* @retval None
AnnaBridge	157:e7ca05fa8600	1023	*/
AnnaBridge	157:e7ca05fa8600	1024	__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1025	{
AnnaBridge	157:e7ca05fa8600	1026	CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
AnnaBridge	157:e7ca05fa8600	1027	}
AnnaBridge	157:e7ca05fa8600	1028
AnnaBridge	157:e7ca05fa8600	1029	/**
AnnaBridge	157:e7ca05fa8600	1030	* @brief Disable Overrun detection
AnnaBridge	157:e7ca05fa8600	1031	* @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect
AnnaBridge	157:e7ca05fa8600	1032	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1033	* @retval None
AnnaBridge	157:e7ca05fa8600	1034	*/
AnnaBridge	157:e7ca05fa8600	1035	__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1036	{
AnnaBridge	157:e7ca05fa8600	1037	SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
AnnaBridge	157:e7ca05fa8600	1038	}
AnnaBridge	157:e7ca05fa8600	1039
AnnaBridge	157:e7ca05fa8600	1040	/**
AnnaBridge	157:e7ca05fa8600	1041	* @brief Indicate if Overrun detection is enabled
AnnaBridge	157:e7ca05fa8600	1042	* @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
AnnaBridge	157:e7ca05fa8600	1043	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1044	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1045	*/
AnnaBridge	157:e7ca05fa8600	1046	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1047	{
AnnaBridge	157:e7ca05fa8600	1048	return (READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS);
AnnaBridge	157:e7ca05fa8600	1049	}
AnnaBridge	157:e7ca05fa8600	1050
AnnaBridge	157:e7ca05fa8600	1051	/**
AnnaBridge	157:e7ca05fa8600	1052	* @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
AnnaBridge	157:e7ca05fa8600	1053	* @rmtoll CR3 WUS LL_LPUART_SetWKUPType
AnnaBridge	157:e7ca05fa8600	1054	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1055	* @param Type This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	1056	* @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
AnnaBridge	157:e7ca05fa8600	1057	* @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
AnnaBridge	157:e7ca05fa8600	1058	* @arg @ref LL_LPUART_WAKEUP_ON_RXNE
AnnaBridge	157:e7ca05fa8600	1059	* @retval None
AnnaBridge	157:e7ca05fa8600	1060	*/
AnnaBridge	157:e7ca05fa8600	1061	__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
AnnaBridge	157:e7ca05fa8600	1062	{
AnnaBridge	157:e7ca05fa8600	1063	MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
AnnaBridge	157:e7ca05fa8600	1064	}
AnnaBridge	157:e7ca05fa8600	1065
AnnaBridge	157:e7ca05fa8600	1066	/**
AnnaBridge	157:e7ca05fa8600	1067	* @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
AnnaBridge	157:e7ca05fa8600	1068	* @rmtoll CR3 WUS LL_LPUART_GetWKUPType
AnnaBridge	157:e7ca05fa8600	1069	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1070	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	1071	* @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
AnnaBridge	157:e7ca05fa8600	1072	* @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
AnnaBridge	157:e7ca05fa8600	1073	* @arg @ref LL_LPUART_WAKEUP_ON_RXNE
AnnaBridge	157:e7ca05fa8600	1074	*/
AnnaBridge	157:e7ca05fa8600	1075	__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1076	{
AnnaBridge	157:e7ca05fa8600	1077	return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
AnnaBridge	157:e7ca05fa8600	1078	}
AnnaBridge	157:e7ca05fa8600	1079
AnnaBridge	157:e7ca05fa8600	1080	/**
AnnaBridge	157:e7ca05fa8600	1081	* @brief Configure LPUART BRR register for achieving expected Baud Rate value.
AnnaBridge	157:e7ca05fa8600	1082	*
AnnaBridge	157:e7ca05fa8600	1083	* @note Compute and set LPUARTDIV value in BRR Register (full BRR content)
AnnaBridge	157:e7ca05fa8600	1084	* according to used Peripheral Clock and expected Baud Rate values
AnnaBridge	157:e7ca05fa8600	1085	* @note Peripheral clock and Baud Rate values provided as function parameters should be valid
AnnaBridge	157:e7ca05fa8600	1086	* (Baud rate value != 0).
AnnaBridge	157:e7ca05fa8600	1087	* @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
AnnaBridge	157:e7ca05fa8600	1088	* a care should be taken when generating high baud rates using high PeriphClk
AnnaBridge	157:e7ca05fa8600	1089	* values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
AnnaBridge	157:e7ca05fa8600	1090	* @rmtoll BRR BRR LL_LPUART_SetBaudRate
AnnaBridge	157:e7ca05fa8600	1091	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1092	* @param PeriphClk Peripheral Clock
AnnaBridge	157:e7ca05fa8600	1093	* @param BaudRate Baud Rate
AnnaBridge	157:e7ca05fa8600	1094	* @retval None
AnnaBridge	157:e7ca05fa8600	1095	*/
AnnaBridge	157:e7ca05fa8600	1096	__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t BaudRate)
AnnaBridge	157:e7ca05fa8600	1097	{
AnnaBridge	157:e7ca05fa8600	1098	LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate);
AnnaBridge	157:e7ca05fa8600	1099	}
AnnaBridge	157:e7ca05fa8600	1100
AnnaBridge	157:e7ca05fa8600	1101	/**
AnnaBridge	157:e7ca05fa8600	1102	* @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register
AnnaBridge	157:e7ca05fa8600	1103	* (full BRR content), and to used Peripheral Clock values
AnnaBridge	157:e7ca05fa8600	1104	* @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
AnnaBridge	157:e7ca05fa8600	1105	* @rmtoll BRR BRR LL_LPUART_GetBaudRate
AnnaBridge	157:e7ca05fa8600	1106	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1107	* @param PeriphClk Peripheral Clock
AnnaBridge	157:e7ca05fa8600	1108	* @retval Baud Rate
AnnaBridge	157:e7ca05fa8600	1109	*/
AnnaBridge	157:e7ca05fa8600	1110	__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk)
AnnaBridge	157:e7ca05fa8600	1111	{
AnnaBridge	157:e7ca05fa8600	1112	register uint32_t lpuartdiv = 0x0U;
AnnaBridge	157:e7ca05fa8600	1113	register uint32_t brrresult = 0x0U;
AnnaBridge	157:e7ca05fa8600	1114
AnnaBridge	157:e7ca05fa8600	1115	lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
AnnaBridge	157:e7ca05fa8600	1116
AnnaBridge	157:e7ca05fa8600	1117	if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
AnnaBridge	157:e7ca05fa8600	1118	{
AnnaBridge	157:e7ca05fa8600	1119	brrresult = (uint32_t)(((uint64_t)(PeriphClk) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
AnnaBridge	157:e7ca05fa8600	1120	}
AnnaBridge	157:e7ca05fa8600	1121
AnnaBridge	157:e7ca05fa8600	1122	return (brrresult);
AnnaBridge	157:e7ca05fa8600	1123	}
AnnaBridge	157:e7ca05fa8600	1124
AnnaBridge	157:e7ca05fa8600	1125	/**
AnnaBridge	157:e7ca05fa8600	1126	* @}
AnnaBridge	157:e7ca05fa8600	1127	*/
AnnaBridge	157:e7ca05fa8600	1128
AnnaBridge	157:e7ca05fa8600	1129	/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
AnnaBridge	157:e7ca05fa8600	1130	* @{
AnnaBridge	157:e7ca05fa8600	1131	*/
AnnaBridge	157:e7ca05fa8600	1132
AnnaBridge	157:e7ca05fa8600	1133	/**
AnnaBridge	157:e7ca05fa8600	1134	* @brief Enable Single Wire Half-Duplex mode
AnnaBridge	157:e7ca05fa8600	1135	* @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex
AnnaBridge	157:e7ca05fa8600	1136	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1137	* @retval None
AnnaBridge	157:e7ca05fa8600	1138	*/
AnnaBridge	157:e7ca05fa8600	1139	__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1140	{
AnnaBridge	157:e7ca05fa8600	1141	SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
AnnaBridge	157:e7ca05fa8600	1142	}
AnnaBridge	157:e7ca05fa8600	1143
AnnaBridge	157:e7ca05fa8600	1144	/**
AnnaBridge	157:e7ca05fa8600	1145	* @brief Disable Single Wire Half-Duplex mode
AnnaBridge	157:e7ca05fa8600	1146	* @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex
AnnaBridge	157:e7ca05fa8600	1147	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1148	* @retval None
AnnaBridge	157:e7ca05fa8600	1149	*/
AnnaBridge	157:e7ca05fa8600	1150	__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1151	{
AnnaBridge	157:e7ca05fa8600	1152	CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
AnnaBridge	157:e7ca05fa8600	1153	}
AnnaBridge	157:e7ca05fa8600	1154
AnnaBridge	157:e7ca05fa8600	1155	/**
AnnaBridge	157:e7ca05fa8600	1156	* @brief Indicate if Single Wire Half-Duplex mode is enabled
AnnaBridge	157:e7ca05fa8600	1157	* @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
AnnaBridge	157:e7ca05fa8600	1158	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1159	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1160	*/
AnnaBridge	157:e7ca05fa8600	1161	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1162	{
AnnaBridge	157:e7ca05fa8600	1163	return (READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
AnnaBridge	157:e7ca05fa8600	1164	}
AnnaBridge	157:e7ca05fa8600	1165
AnnaBridge	157:e7ca05fa8600	1166	/**
AnnaBridge	157:e7ca05fa8600	1167	* @}
AnnaBridge	157:e7ca05fa8600	1168	*/
AnnaBridge	157:e7ca05fa8600	1169
AnnaBridge	157:e7ca05fa8600	1170	/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
AnnaBridge	157:e7ca05fa8600	1171	* @{
AnnaBridge	157:e7ca05fa8600	1172	*/
AnnaBridge	157:e7ca05fa8600	1173
AnnaBridge	157:e7ca05fa8600	1174	/**
AnnaBridge	157:e7ca05fa8600	1175	* @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
AnnaBridge	157:e7ca05fa8600	1176	* @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime
AnnaBridge	157:e7ca05fa8600	1177	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1178	* @param Time Value between Min_Data=0 and Max_Data=31
AnnaBridge	157:e7ca05fa8600	1179	* @retval None
AnnaBridge	157:e7ca05fa8600	1180	*/
AnnaBridge	157:e7ca05fa8600	1181	__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
AnnaBridge	157:e7ca05fa8600	1182	{
AnnaBridge	157:e7ca05fa8600	1183	MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << LPUART_POSITION_CR1_DEDT);
AnnaBridge	157:e7ca05fa8600	1184	}
AnnaBridge	157:e7ca05fa8600	1185
AnnaBridge	157:e7ca05fa8600	1186	/**
AnnaBridge	157:e7ca05fa8600	1187	* @brief Return DEDT (Driver Enable De-Assertion Time)
AnnaBridge	157:e7ca05fa8600	1188	* @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime
AnnaBridge	157:e7ca05fa8600	1189	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1190	* @retval Time value expressed on 5 bits ([4:0] bits) : c
AnnaBridge	157:e7ca05fa8600	1191	*/
AnnaBridge	157:e7ca05fa8600	1192	__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1193	{
AnnaBridge	157:e7ca05fa8600	1194	return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> LPUART_POSITION_CR1_DEDT);
AnnaBridge	157:e7ca05fa8600	1195	}
AnnaBridge	157:e7ca05fa8600	1196
AnnaBridge	157:e7ca05fa8600	1197	/**
AnnaBridge	157:e7ca05fa8600	1198	* @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
AnnaBridge	157:e7ca05fa8600	1199	* @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime
AnnaBridge	157:e7ca05fa8600	1200	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1201	* @param Time Value between Min_Data=0 and Max_Data=31
AnnaBridge	157:e7ca05fa8600	1202	* @retval None
AnnaBridge	157:e7ca05fa8600	1203	*/
AnnaBridge	157:e7ca05fa8600	1204	__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
AnnaBridge	157:e7ca05fa8600	1205	{
AnnaBridge	157:e7ca05fa8600	1206	MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << LPUART_POSITION_CR1_DEAT);
AnnaBridge	157:e7ca05fa8600	1207	}
AnnaBridge	157:e7ca05fa8600	1208
AnnaBridge	157:e7ca05fa8600	1209	/**
AnnaBridge	157:e7ca05fa8600	1210	* @brief Return DEAT (Driver Enable Assertion Time)
AnnaBridge	157:e7ca05fa8600	1211	* @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime
AnnaBridge	157:e7ca05fa8600	1212	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1213	* @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
AnnaBridge	157:e7ca05fa8600	1214	*/
AnnaBridge	157:e7ca05fa8600	1215	__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1216	{
AnnaBridge	157:e7ca05fa8600	1217	return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> LPUART_POSITION_CR1_DEAT);
AnnaBridge	157:e7ca05fa8600	1218	}
AnnaBridge	157:e7ca05fa8600	1219
AnnaBridge	157:e7ca05fa8600	1220	/**
AnnaBridge	157:e7ca05fa8600	1221	* @brief Enable Driver Enable (DE) Mode
AnnaBridge	157:e7ca05fa8600	1222	* @rmtoll CR3 DEM LL_LPUART_EnableDEMode
AnnaBridge	157:e7ca05fa8600	1223	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1224	* @retval None
AnnaBridge	157:e7ca05fa8600	1225	*/
AnnaBridge	157:e7ca05fa8600	1226	__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1227	{
AnnaBridge	157:e7ca05fa8600	1228	SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
AnnaBridge	157:e7ca05fa8600	1229	}
AnnaBridge	157:e7ca05fa8600	1230
AnnaBridge	157:e7ca05fa8600	1231	/**
AnnaBridge	157:e7ca05fa8600	1232	* @brief Disable Driver Enable (DE) Mode
AnnaBridge	157:e7ca05fa8600	1233	* @rmtoll CR3 DEM LL_LPUART_DisableDEMode
AnnaBridge	157:e7ca05fa8600	1234	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1235	* @retval None
AnnaBridge	157:e7ca05fa8600	1236	*/
AnnaBridge	157:e7ca05fa8600	1237	__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1238	{
AnnaBridge	157:e7ca05fa8600	1239	CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
AnnaBridge	157:e7ca05fa8600	1240	}
AnnaBridge	157:e7ca05fa8600	1241
AnnaBridge	157:e7ca05fa8600	1242	/**
AnnaBridge	157:e7ca05fa8600	1243	* @brief Indicate if Driver Enable (DE) Mode is enabled
AnnaBridge	157:e7ca05fa8600	1244	* @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode
AnnaBridge	157:e7ca05fa8600	1245	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1246	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1247	*/
AnnaBridge	157:e7ca05fa8600	1248	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1249	{
AnnaBridge	157:e7ca05fa8600	1250	return (READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM));
AnnaBridge	157:e7ca05fa8600	1251	}
AnnaBridge	157:e7ca05fa8600	1252
AnnaBridge	157:e7ca05fa8600	1253	/**
AnnaBridge	157:e7ca05fa8600	1254	* @brief Select Driver Enable Polarity
AnnaBridge	157:e7ca05fa8600	1255	* @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity
AnnaBridge	157:e7ca05fa8600	1256	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1257	* @param Polarity This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	1258	* @arg @ref LL_LPUART_DE_POLARITY_HIGH
AnnaBridge	157:e7ca05fa8600	1259	* @arg @ref LL_LPUART_DE_POLARITY_LOW
AnnaBridge	157:e7ca05fa8600	1260	* @retval None
AnnaBridge	157:e7ca05fa8600	1261	*/
AnnaBridge	157:e7ca05fa8600	1262	__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
AnnaBridge	157:e7ca05fa8600	1263	{
AnnaBridge	157:e7ca05fa8600	1264	MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
AnnaBridge	157:e7ca05fa8600	1265	}
AnnaBridge	157:e7ca05fa8600	1266
AnnaBridge	157:e7ca05fa8600	1267	/**
AnnaBridge	157:e7ca05fa8600	1268	* @brief Return Driver Enable Polarity
AnnaBridge	157:e7ca05fa8600	1269	* @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity
AnnaBridge	157:e7ca05fa8600	1270	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1271	* @retval Returned value can be one of the following values:
AnnaBridge	157:e7ca05fa8600	1272	* @arg @ref LL_LPUART_DE_POLARITY_HIGH
AnnaBridge	157:e7ca05fa8600	1273	* @arg @ref LL_LPUART_DE_POLARITY_LOW
AnnaBridge	157:e7ca05fa8600	1274	*/
AnnaBridge	157:e7ca05fa8600	1275	__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1276	{
AnnaBridge	157:e7ca05fa8600	1277	return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
AnnaBridge	157:e7ca05fa8600	1278	}
AnnaBridge	157:e7ca05fa8600	1279
AnnaBridge	157:e7ca05fa8600	1280	/**
AnnaBridge	157:e7ca05fa8600	1281	* @}
AnnaBridge	157:e7ca05fa8600	1282	*/
AnnaBridge	157:e7ca05fa8600	1283
AnnaBridge	157:e7ca05fa8600	1284	/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
AnnaBridge	157:e7ca05fa8600	1285	* @{
AnnaBridge	157:e7ca05fa8600	1286	*/
AnnaBridge	157:e7ca05fa8600	1287
AnnaBridge	157:e7ca05fa8600	1288	/**
AnnaBridge	157:e7ca05fa8600	1289	* @brief Check if the LPUART Parity Error Flag is set or not
AnnaBridge	157:e7ca05fa8600	1290	* @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE
AnnaBridge	157:e7ca05fa8600	1291	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1292	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1293	*/
AnnaBridge	157:e7ca05fa8600	1294	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1295	{
AnnaBridge	157:e7ca05fa8600	1296	return (READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE));
AnnaBridge	157:e7ca05fa8600	1297	}
AnnaBridge	157:e7ca05fa8600	1298
AnnaBridge	157:e7ca05fa8600	1299	/**
AnnaBridge	157:e7ca05fa8600	1300	* @brief Check if the LPUART Framing Error Flag is set or not
AnnaBridge	157:e7ca05fa8600	1301	* @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE
AnnaBridge	157:e7ca05fa8600	1302	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1303	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1304	*/
AnnaBridge	157:e7ca05fa8600	1305	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1306	{
AnnaBridge	157:e7ca05fa8600	1307	return (READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE));
AnnaBridge	157:e7ca05fa8600	1308	}
AnnaBridge	157:e7ca05fa8600	1309
AnnaBridge	157:e7ca05fa8600	1310	/**
AnnaBridge	157:e7ca05fa8600	1311	* @brief Check if the LPUART Noise detected Flag is set or not
AnnaBridge	157:e7ca05fa8600	1312	* @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE
AnnaBridge	157:e7ca05fa8600	1313	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1314	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1315	*/
AnnaBridge	157:e7ca05fa8600	1316	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1317	{
AnnaBridge	157:e7ca05fa8600	1318	return (READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE));
AnnaBridge	157:e7ca05fa8600	1319	}
AnnaBridge	157:e7ca05fa8600	1320
AnnaBridge	157:e7ca05fa8600	1321	/**
AnnaBridge	157:e7ca05fa8600	1322	* @brief Check if the LPUART OverRun Error Flag is set or not
AnnaBridge	157:e7ca05fa8600	1323	* @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE
AnnaBridge	157:e7ca05fa8600	1324	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1325	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1326	*/
AnnaBridge	157:e7ca05fa8600	1327	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1328	{
AnnaBridge	157:e7ca05fa8600	1329	return (READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE));
AnnaBridge	157:e7ca05fa8600	1330	}
AnnaBridge	157:e7ca05fa8600	1331
AnnaBridge	157:e7ca05fa8600	1332	/**
AnnaBridge	157:e7ca05fa8600	1333	* @brief Check if the LPUART IDLE line detected Flag is set or not
AnnaBridge	157:e7ca05fa8600	1334	* @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE
AnnaBridge	157:e7ca05fa8600	1335	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1336	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1337	*/
AnnaBridge	157:e7ca05fa8600	1338	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1339	{
AnnaBridge	157:e7ca05fa8600	1340	return (READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE));
AnnaBridge	157:e7ca05fa8600	1341	}
AnnaBridge	157:e7ca05fa8600	1342
AnnaBridge	157:e7ca05fa8600	1343	/**
AnnaBridge	157:e7ca05fa8600	1344	* @brief Check if the LPUART Read Data Register Not Empty Flag is set or not
AnnaBridge	157:e7ca05fa8600	1345	* @rmtoll ISR RXNE LL_LPUART_IsActiveFlag_RXNE
AnnaBridge	157:e7ca05fa8600	1346	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1347	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1348	*/
AnnaBridge	157:e7ca05fa8600	1349	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1350	{
AnnaBridge	157:e7ca05fa8600	1351	return (READ_BIT(LPUARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE));
AnnaBridge	157:e7ca05fa8600	1352	}
AnnaBridge	157:e7ca05fa8600	1353
AnnaBridge	157:e7ca05fa8600	1354	/**
AnnaBridge	157:e7ca05fa8600	1355	* @brief Check if the LPUART Transmission Complete Flag is set or not
AnnaBridge	157:e7ca05fa8600	1356	* @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC
AnnaBridge	157:e7ca05fa8600	1357	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1358	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1359	*/
AnnaBridge	157:e7ca05fa8600	1360	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1361	{
AnnaBridge	157:e7ca05fa8600	1362	return (READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC));
AnnaBridge	157:e7ca05fa8600	1363	}
AnnaBridge	157:e7ca05fa8600	1364
AnnaBridge	157:e7ca05fa8600	1365	/**
AnnaBridge	157:e7ca05fa8600	1366	* @brief Check if the LPUART Transmit Data Register Empty Flag is set or not
AnnaBridge	157:e7ca05fa8600	1367	* @rmtoll ISR TXE LL_LPUART_IsActiveFlag_TXE
AnnaBridge	157:e7ca05fa8600	1368	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1369	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1370	*/
AnnaBridge	157:e7ca05fa8600	1371	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1372	{
AnnaBridge	157:e7ca05fa8600	1373	return (READ_BIT(LPUARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE));
AnnaBridge	157:e7ca05fa8600	1374	}
AnnaBridge	157:e7ca05fa8600	1375
AnnaBridge	157:e7ca05fa8600	1376	/**
AnnaBridge	157:e7ca05fa8600	1377	* @brief Check if the LPUART CTS interrupt Flag is set or not
AnnaBridge	157:e7ca05fa8600	1378	* @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
AnnaBridge	157:e7ca05fa8600	1379	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1380	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1381	*/
AnnaBridge	157:e7ca05fa8600	1382	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1383	{
AnnaBridge	157:e7ca05fa8600	1384	return (READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF));
AnnaBridge	157:e7ca05fa8600	1385	}
AnnaBridge	157:e7ca05fa8600	1386
AnnaBridge	157:e7ca05fa8600	1387	/**
AnnaBridge	157:e7ca05fa8600	1388	* @brief Check if the LPUART CTS Flag is set or not
AnnaBridge	157:e7ca05fa8600	1389	* @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS
AnnaBridge	157:e7ca05fa8600	1390	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1391	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1392	*/
AnnaBridge	157:e7ca05fa8600	1393	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1394	{
AnnaBridge	157:e7ca05fa8600	1395	return (READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS));
AnnaBridge	157:e7ca05fa8600	1396	}
AnnaBridge	157:e7ca05fa8600	1397
AnnaBridge	157:e7ca05fa8600	1398	/**
AnnaBridge	157:e7ca05fa8600	1399	* @brief Check if the LPUART Busy Flag is set or not
AnnaBridge	157:e7ca05fa8600	1400	* @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY
AnnaBridge	157:e7ca05fa8600	1401	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1402	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1403	*/
AnnaBridge	157:e7ca05fa8600	1404	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1405	{
AnnaBridge	157:e7ca05fa8600	1406	return (READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY));
AnnaBridge	157:e7ca05fa8600	1407	}
AnnaBridge	157:e7ca05fa8600	1408
AnnaBridge	157:e7ca05fa8600	1409	/**
AnnaBridge	157:e7ca05fa8600	1410	* @brief Check if the LPUART Character Match Flag is set or not
AnnaBridge	157:e7ca05fa8600	1411	* @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM
AnnaBridge	157:e7ca05fa8600	1412	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1413	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1414	*/
AnnaBridge	157:e7ca05fa8600	1415	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1416	{
AnnaBridge	157:e7ca05fa8600	1417	return (READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF));
AnnaBridge	157:e7ca05fa8600	1418	}
AnnaBridge	157:e7ca05fa8600	1419
AnnaBridge	157:e7ca05fa8600	1420	/**
AnnaBridge	157:e7ca05fa8600	1421	* @brief Check if the LPUART Send Break Flag is set or not
AnnaBridge	157:e7ca05fa8600	1422	* @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK
AnnaBridge	157:e7ca05fa8600	1423	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1424	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1425	*/
AnnaBridge	157:e7ca05fa8600	1426	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1427	{
AnnaBridge	157:e7ca05fa8600	1428	return (READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF));
AnnaBridge	157:e7ca05fa8600	1429	}
AnnaBridge	157:e7ca05fa8600	1430
AnnaBridge	157:e7ca05fa8600	1431	/**
AnnaBridge	157:e7ca05fa8600	1432	* @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not
AnnaBridge	157:e7ca05fa8600	1433	* @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU
AnnaBridge	157:e7ca05fa8600	1434	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1435	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1436	*/
AnnaBridge	157:e7ca05fa8600	1437	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1438	{
AnnaBridge	157:e7ca05fa8600	1439	return (READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU));
AnnaBridge	157:e7ca05fa8600	1440	}
AnnaBridge	157:e7ca05fa8600	1441
AnnaBridge	157:e7ca05fa8600	1442	/**
AnnaBridge	157:e7ca05fa8600	1443	* @brief Check if the LPUART Wake Up from stop mode Flag is set or not
AnnaBridge	157:e7ca05fa8600	1444	* @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP
AnnaBridge	157:e7ca05fa8600	1445	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1446	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1447	*/
AnnaBridge	157:e7ca05fa8600	1448	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1449	{
AnnaBridge	157:e7ca05fa8600	1450	return (READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF));
AnnaBridge	157:e7ca05fa8600	1451	}
AnnaBridge	157:e7ca05fa8600	1452
AnnaBridge	157:e7ca05fa8600	1453	/**
AnnaBridge	157:e7ca05fa8600	1454	* @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not
AnnaBridge	157:e7ca05fa8600	1455	* @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK
AnnaBridge	157:e7ca05fa8600	1456	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1457	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1458	*/
AnnaBridge	157:e7ca05fa8600	1459	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1460	{
AnnaBridge	157:e7ca05fa8600	1461	return (READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK));
AnnaBridge	157:e7ca05fa8600	1462	}
AnnaBridge	157:e7ca05fa8600	1463
AnnaBridge	157:e7ca05fa8600	1464	/**
AnnaBridge	157:e7ca05fa8600	1465	* @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not
AnnaBridge	157:e7ca05fa8600	1466	* @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK
AnnaBridge	157:e7ca05fa8600	1467	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1468	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1469	*/
AnnaBridge	157:e7ca05fa8600	1470	__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1471	{
AnnaBridge	157:e7ca05fa8600	1472	return (READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK));
AnnaBridge	157:e7ca05fa8600	1473	}
AnnaBridge	157:e7ca05fa8600	1474
AnnaBridge	157:e7ca05fa8600	1475	/**
AnnaBridge	157:e7ca05fa8600	1476	* @brief Clear Parity Error Flag
AnnaBridge	157:e7ca05fa8600	1477	* @rmtoll ICR PECF LL_LPUART_ClearFlag_PE
AnnaBridge	157:e7ca05fa8600	1478	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1479	* @retval None
AnnaBridge	157:e7ca05fa8600	1480	*/
AnnaBridge	157:e7ca05fa8600	1481	__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1482	{
AnnaBridge	157:e7ca05fa8600	1483	WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
AnnaBridge	157:e7ca05fa8600	1484	}
AnnaBridge	157:e7ca05fa8600	1485
AnnaBridge	157:e7ca05fa8600	1486	/**
AnnaBridge	157:e7ca05fa8600	1487	* @brief Clear Framing Error Flag
AnnaBridge	157:e7ca05fa8600	1488	* @rmtoll ICR FECF LL_LPUART_ClearFlag_FE
AnnaBridge	157:e7ca05fa8600	1489	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1490	* @retval None
AnnaBridge	157:e7ca05fa8600	1491	*/
AnnaBridge	157:e7ca05fa8600	1492	__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1493	{
AnnaBridge	157:e7ca05fa8600	1494	WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
AnnaBridge	157:e7ca05fa8600	1495	}
AnnaBridge	157:e7ca05fa8600	1496
AnnaBridge	157:e7ca05fa8600	1497	/**
AnnaBridge	157:e7ca05fa8600	1498	* @brief Clear Noise detected Flag
AnnaBridge	157:e7ca05fa8600	1499	* @rmtoll ICR NCF LL_LPUART_ClearFlag_NE
AnnaBridge	157:e7ca05fa8600	1500	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1501	* @retval None
AnnaBridge	157:e7ca05fa8600	1502	*/
AnnaBridge	157:e7ca05fa8600	1503	__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1504	{
AnnaBridge	157:e7ca05fa8600	1505	WRITE_REG(LPUARTx->ICR, USART_ICR_NCF);
AnnaBridge	157:e7ca05fa8600	1506	}
AnnaBridge	157:e7ca05fa8600	1507
AnnaBridge	157:e7ca05fa8600	1508	/**
AnnaBridge	157:e7ca05fa8600	1509	* @brief Clear OverRun Error Flag
AnnaBridge	157:e7ca05fa8600	1510	* @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE
AnnaBridge	157:e7ca05fa8600	1511	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1512	* @retval None
AnnaBridge	157:e7ca05fa8600	1513	*/
AnnaBridge	157:e7ca05fa8600	1514	__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1515	{
AnnaBridge	157:e7ca05fa8600	1516	WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
AnnaBridge	157:e7ca05fa8600	1517	}
AnnaBridge	157:e7ca05fa8600	1518
AnnaBridge	157:e7ca05fa8600	1519	/**
AnnaBridge	157:e7ca05fa8600	1520	* @brief Clear IDLE line detected Flag
AnnaBridge	157:e7ca05fa8600	1521	* @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE
AnnaBridge	157:e7ca05fa8600	1522	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1523	* @retval None
AnnaBridge	157:e7ca05fa8600	1524	*/
AnnaBridge	157:e7ca05fa8600	1525	__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1526	{
AnnaBridge	157:e7ca05fa8600	1527	WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
AnnaBridge	157:e7ca05fa8600	1528	}
AnnaBridge	157:e7ca05fa8600	1529
AnnaBridge	157:e7ca05fa8600	1530	/**
AnnaBridge	157:e7ca05fa8600	1531	* @brief Clear Transmission Complete Flag
AnnaBridge	157:e7ca05fa8600	1532	* @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
AnnaBridge	157:e7ca05fa8600	1533	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1534	* @retval None
AnnaBridge	157:e7ca05fa8600	1535	*/
AnnaBridge	157:e7ca05fa8600	1536	__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1537	{
AnnaBridge	157:e7ca05fa8600	1538	WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
AnnaBridge	157:e7ca05fa8600	1539	}
AnnaBridge	157:e7ca05fa8600	1540
AnnaBridge	157:e7ca05fa8600	1541	/**
AnnaBridge	157:e7ca05fa8600	1542	* @brief Clear CTS Interrupt Flag
AnnaBridge	157:e7ca05fa8600	1543	* @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS
AnnaBridge	157:e7ca05fa8600	1544	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1545	* @retval None
AnnaBridge	157:e7ca05fa8600	1546	*/
AnnaBridge	157:e7ca05fa8600	1547	__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1548	{
AnnaBridge	157:e7ca05fa8600	1549	WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
AnnaBridge	157:e7ca05fa8600	1550	}
AnnaBridge	157:e7ca05fa8600	1551
AnnaBridge	157:e7ca05fa8600	1552	/**
AnnaBridge	157:e7ca05fa8600	1553	* @brief Clear Character Match Flag
AnnaBridge	157:e7ca05fa8600	1554	* @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM
AnnaBridge	157:e7ca05fa8600	1555	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1556	* @retval None
AnnaBridge	157:e7ca05fa8600	1557	*/
AnnaBridge	157:e7ca05fa8600	1558	__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1559	{
AnnaBridge	157:e7ca05fa8600	1560	WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
AnnaBridge	157:e7ca05fa8600	1561	}
AnnaBridge	157:e7ca05fa8600	1562
AnnaBridge	157:e7ca05fa8600	1563	/**
AnnaBridge	157:e7ca05fa8600	1564	* @brief Clear Wake Up from stop mode Flag
AnnaBridge	157:e7ca05fa8600	1565	* @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP
AnnaBridge	157:e7ca05fa8600	1566	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1567	* @retval None
AnnaBridge	157:e7ca05fa8600	1568	*/
AnnaBridge	157:e7ca05fa8600	1569	__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1570	{
AnnaBridge	157:e7ca05fa8600	1571	WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
AnnaBridge	157:e7ca05fa8600	1572	}
AnnaBridge	157:e7ca05fa8600	1573
AnnaBridge	157:e7ca05fa8600	1574	/**
AnnaBridge	157:e7ca05fa8600	1575	* @}
AnnaBridge	157:e7ca05fa8600	1576	*/
AnnaBridge	157:e7ca05fa8600	1577
AnnaBridge	157:e7ca05fa8600	1578	/** @defgroup LPUART_LL_EF_IT_Management IT_Management
AnnaBridge	157:e7ca05fa8600	1579	* @{
AnnaBridge	157:e7ca05fa8600	1580	*/
AnnaBridge	157:e7ca05fa8600	1581
AnnaBridge	157:e7ca05fa8600	1582	/**
AnnaBridge	157:e7ca05fa8600	1583	* @brief Enable IDLE Interrupt
AnnaBridge	157:e7ca05fa8600	1584	* @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE
AnnaBridge	157:e7ca05fa8600	1585	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1586	* @retval None
AnnaBridge	157:e7ca05fa8600	1587	*/
AnnaBridge	157:e7ca05fa8600	1588	__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1589	{
AnnaBridge	157:e7ca05fa8600	1590	SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
AnnaBridge	157:e7ca05fa8600	1591	}
AnnaBridge	157:e7ca05fa8600	1592
AnnaBridge	157:e7ca05fa8600	1593	/**
AnnaBridge	157:e7ca05fa8600	1594	* @brief Enable RX Not Empty Interrupt
AnnaBridge	157:e7ca05fa8600	1595	* @rmtoll CR1 RXNEIE LL_LPUART_EnableIT_RXNE
AnnaBridge	157:e7ca05fa8600	1596	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1597	* @retval None
AnnaBridge	157:e7ca05fa8600	1598	*/
AnnaBridge	157:e7ca05fa8600	1599	__STATIC_INLINE void LL_LPUART_EnableIT_RXNE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1600	{
AnnaBridge	157:e7ca05fa8600	1601	SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
AnnaBridge	157:e7ca05fa8600	1602	}
AnnaBridge	157:e7ca05fa8600	1603
AnnaBridge	157:e7ca05fa8600	1604	/**
AnnaBridge	157:e7ca05fa8600	1605	* @brief Enable Transmission Complete Interrupt
AnnaBridge	157:e7ca05fa8600	1606	* @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC
AnnaBridge	157:e7ca05fa8600	1607	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1608	* @retval None
AnnaBridge	157:e7ca05fa8600	1609	*/
AnnaBridge	157:e7ca05fa8600	1610	__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1611	{
AnnaBridge	157:e7ca05fa8600	1612	SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
AnnaBridge	157:e7ca05fa8600	1613	}
AnnaBridge	157:e7ca05fa8600	1614
AnnaBridge	157:e7ca05fa8600	1615	/**
AnnaBridge	157:e7ca05fa8600	1616	* @brief Enable TX Empty Interrupt
AnnaBridge	157:e7ca05fa8600	1617	* @rmtoll CR1 TXEIE LL_LPUART_EnableIT_TXE
AnnaBridge	157:e7ca05fa8600	1618	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1619	* @retval None
AnnaBridge	157:e7ca05fa8600	1620	*/
AnnaBridge	157:e7ca05fa8600	1621	__STATIC_INLINE void LL_LPUART_EnableIT_TXE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1622	{
AnnaBridge	157:e7ca05fa8600	1623	SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
AnnaBridge	157:e7ca05fa8600	1624	}
AnnaBridge	157:e7ca05fa8600	1625
AnnaBridge	157:e7ca05fa8600	1626	/**
AnnaBridge	157:e7ca05fa8600	1627	* @brief Enable Parity Error Interrupt
AnnaBridge	157:e7ca05fa8600	1628	* @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE
AnnaBridge	157:e7ca05fa8600	1629	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1630	* @retval None
AnnaBridge	157:e7ca05fa8600	1631	*/
AnnaBridge	157:e7ca05fa8600	1632	__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1633	{
AnnaBridge	157:e7ca05fa8600	1634	SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
AnnaBridge	157:e7ca05fa8600	1635	}
AnnaBridge	157:e7ca05fa8600	1636
AnnaBridge	157:e7ca05fa8600	1637	/**
AnnaBridge	157:e7ca05fa8600	1638	* @brief Enable Character Match Interrupt
AnnaBridge	157:e7ca05fa8600	1639	* @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM
AnnaBridge	157:e7ca05fa8600	1640	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1641	* @retval None
AnnaBridge	157:e7ca05fa8600	1642	*/
AnnaBridge	157:e7ca05fa8600	1643	__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1644	{
AnnaBridge	157:e7ca05fa8600	1645	SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
AnnaBridge	157:e7ca05fa8600	1646	}
AnnaBridge	157:e7ca05fa8600	1647
AnnaBridge	157:e7ca05fa8600	1648	/**
AnnaBridge	157:e7ca05fa8600	1649	* @brief Enable Error Interrupt
AnnaBridge	157:e7ca05fa8600	1650	* @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
AnnaBridge	157:e7ca05fa8600	1651	* error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
AnnaBridge	157:e7ca05fa8600	1652	* - 0: Interrupt is inhibited
AnnaBridge	157:e7ca05fa8600	1653	* - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
AnnaBridge	157:e7ca05fa8600	1654	* @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR
AnnaBridge	157:e7ca05fa8600	1655	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1656	* @retval None
AnnaBridge	157:e7ca05fa8600	1657	*/
AnnaBridge	157:e7ca05fa8600	1658	__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1659	{
AnnaBridge	157:e7ca05fa8600	1660	SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
AnnaBridge	157:e7ca05fa8600	1661	}
AnnaBridge	157:e7ca05fa8600	1662
AnnaBridge	157:e7ca05fa8600	1663	/**
AnnaBridge	157:e7ca05fa8600	1664	* @brief Enable CTS Interrupt
AnnaBridge	157:e7ca05fa8600	1665	* @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS
AnnaBridge	157:e7ca05fa8600	1666	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1667	* @retval None
AnnaBridge	157:e7ca05fa8600	1668	*/
AnnaBridge	157:e7ca05fa8600	1669	__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1670	{
AnnaBridge	157:e7ca05fa8600	1671	SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
AnnaBridge	157:e7ca05fa8600	1672	}
AnnaBridge	157:e7ca05fa8600	1673
AnnaBridge	157:e7ca05fa8600	1674	/**
AnnaBridge	157:e7ca05fa8600	1675	* @brief Enable Wake Up from Stop Mode Interrupt
AnnaBridge	157:e7ca05fa8600	1676	* @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP
AnnaBridge	157:e7ca05fa8600	1677	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1678	* @retval None
AnnaBridge	157:e7ca05fa8600	1679	*/
AnnaBridge	157:e7ca05fa8600	1680	__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1681	{
AnnaBridge	157:e7ca05fa8600	1682	SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
AnnaBridge	157:e7ca05fa8600	1683	}
AnnaBridge	157:e7ca05fa8600	1684
AnnaBridge	157:e7ca05fa8600	1685	/**
AnnaBridge	157:e7ca05fa8600	1686	* @brief Disable IDLE Interrupt
AnnaBridge	157:e7ca05fa8600	1687	* @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE
AnnaBridge	157:e7ca05fa8600	1688	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1689	* @retval None
AnnaBridge	157:e7ca05fa8600	1690	*/
AnnaBridge	157:e7ca05fa8600	1691	__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1692	{
AnnaBridge	157:e7ca05fa8600	1693	CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
AnnaBridge	157:e7ca05fa8600	1694	}
AnnaBridge	157:e7ca05fa8600	1695
AnnaBridge	157:e7ca05fa8600	1696	/**
AnnaBridge	157:e7ca05fa8600	1697	* @brief Disable RX Not Empty Interrupt
AnnaBridge	157:e7ca05fa8600	1698	* @rmtoll CR1 RXNEIE LL_LPUART_DisableIT_RXNE
AnnaBridge	157:e7ca05fa8600	1699	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1700	* @retval None
AnnaBridge	157:e7ca05fa8600	1701	*/
AnnaBridge	157:e7ca05fa8600	1702	__STATIC_INLINE void LL_LPUART_DisableIT_RXNE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1703	{
AnnaBridge	157:e7ca05fa8600	1704	CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
AnnaBridge	157:e7ca05fa8600	1705	}
AnnaBridge	157:e7ca05fa8600	1706
AnnaBridge	157:e7ca05fa8600	1707	/**
AnnaBridge	157:e7ca05fa8600	1708	* @brief Disable Transmission Complete Interrupt
AnnaBridge	157:e7ca05fa8600	1709	* @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC
AnnaBridge	157:e7ca05fa8600	1710	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1711	* @retval None
AnnaBridge	157:e7ca05fa8600	1712	*/
AnnaBridge	157:e7ca05fa8600	1713	__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1714	{
AnnaBridge	157:e7ca05fa8600	1715	CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
AnnaBridge	157:e7ca05fa8600	1716	}
AnnaBridge	157:e7ca05fa8600	1717
AnnaBridge	157:e7ca05fa8600	1718	/**
AnnaBridge	157:e7ca05fa8600	1719	* @brief Disable TX Empty Interrupt
AnnaBridge	157:e7ca05fa8600	1720	* @rmtoll CR1 TXEIE LL_LPUART_DisableIT_TXE
AnnaBridge	157:e7ca05fa8600	1721	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1722	* @retval None
AnnaBridge	157:e7ca05fa8600	1723	*/
AnnaBridge	157:e7ca05fa8600	1724	__STATIC_INLINE void LL_LPUART_DisableIT_TXE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1725	{
AnnaBridge	157:e7ca05fa8600	1726	CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
AnnaBridge	157:e7ca05fa8600	1727	}
AnnaBridge	157:e7ca05fa8600	1728
AnnaBridge	157:e7ca05fa8600	1729	/**
AnnaBridge	157:e7ca05fa8600	1730	* @brief Disable Parity Error Interrupt
AnnaBridge	157:e7ca05fa8600	1731	* @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE
AnnaBridge	157:e7ca05fa8600	1732	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1733	* @retval None
AnnaBridge	157:e7ca05fa8600	1734	*/
AnnaBridge	157:e7ca05fa8600	1735	__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1736	{
AnnaBridge	157:e7ca05fa8600	1737	CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
AnnaBridge	157:e7ca05fa8600	1738	}
AnnaBridge	157:e7ca05fa8600	1739
AnnaBridge	157:e7ca05fa8600	1740	/**
AnnaBridge	157:e7ca05fa8600	1741	* @brief Disable Character Match Interrupt
AnnaBridge	157:e7ca05fa8600	1742	* @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM
AnnaBridge	157:e7ca05fa8600	1743	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1744	* @retval None
AnnaBridge	157:e7ca05fa8600	1745	*/
AnnaBridge	157:e7ca05fa8600	1746	__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1747	{
AnnaBridge	157:e7ca05fa8600	1748	CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
AnnaBridge	157:e7ca05fa8600	1749	}
AnnaBridge	157:e7ca05fa8600	1750
AnnaBridge	157:e7ca05fa8600	1751	/**
AnnaBridge	157:e7ca05fa8600	1752	* @brief Disable Error Interrupt
AnnaBridge	157:e7ca05fa8600	1753	* @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
AnnaBridge	157:e7ca05fa8600	1754	* error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
AnnaBridge	157:e7ca05fa8600	1755	* - 0: Interrupt is inhibited
AnnaBridge	157:e7ca05fa8600	1756	* - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
AnnaBridge	157:e7ca05fa8600	1757	* @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR
AnnaBridge	157:e7ca05fa8600	1758	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1759	* @retval None
AnnaBridge	157:e7ca05fa8600	1760	*/
AnnaBridge	157:e7ca05fa8600	1761	__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1762	{
AnnaBridge	157:e7ca05fa8600	1763	CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
AnnaBridge	157:e7ca05fa8600	1764	}
AnnaBridge	157:e7ca05fa8600	1765
AnnaBridge	157:e7ca05fa8600	1766	/**
AnnaBridge	157:e7ca05fa8600	1767	* @brief Disable CTS Interrupt
AnnaBridge	157:e7ca05fa8600	1768	* @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS
AnnaBridge	157:e7ca05fa8600	1769	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1770	* @retval None
AnnaBridge	157:e7ca05fa8600	1771	*/
AnnaBridge	157:e7ca05fa8600	1772	__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1773	{
AnnaBridge	157:e7ca05fa8600	1774	CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
AnnaBridge	157:e7ca05fa8600	1775	}
AnnaBridge	157:e7ca05fa8600	1776
AnnaBridge	157:e7ca05fa8600	1777	/**
AnnaBridge	157:e7ca05fa8600	1778	* @brief Disable Wake Up from Stop Mode Interrupt
AnnaBridge	157:e7ca05fa8600	1779	* @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP
AnnaBridge	157:e7ca05fa8600	1780	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1781	* @retval None
AnnaBridge	157:e7ca05fa8600	1782	*/
AnnaBridge	157:e7ca05fa8600	1783	__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1784	{
AnnaBridge	157:e7ca05fa8600	1785	CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
AnnaBridge	157:e7ca05fa8600	1786	}
AnnaBridge	157:e7ca05fa8600	1787
AnnaBridge	157:e7ca05fa8600	1788	/**
AnnaBridge	157:e7ca05fa8600	1789	* @brief Check if the LPUART IDLE Interrupt source is enabled or disabled.
AnnaBridge	157:e7ca05fa8600	1790	* @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
AnnaBridge	157:e7ca05fa8600	1791	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1792	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1793	*/
AnnaBridge	157:e7ca05fa8600	1794	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1795	{
AnnaBridge	157:e7ca05fa8600	1796	return (READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
AnnaBridge	157:e7ca05fa8600	1797	}
AnnaBridge	157:e7ca05fa8600	1798
AnnaBridge	157:e7ca05fa8600	1799	/**
AnnaBridge	157:e7ca05fa8600	1800	* @brief Check if the LPUART RX Not Empty Interrupt is enabled or disabled.
AnnaBridge	157:e7ca05fa8600	1801	* @rmtoll CR1 RXNEIE LL_LPUART_IsEnabledIT_RXNE
AnnaBridge	157:e7ca05fa8600	1802	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1803	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1804	*/
AnnaBridge	157:e7ca05fa8600	1805	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1806	{
AnnaBridge	157:e7ca05fa8600	1807	return (READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
AnnaBridge	157:e7ca05fa8600	1808	}
AnnaBridge	157:e7ca05fa8600	1809
AnnaBridge	157:e7ca05fa8600	1810	/**
AnnaBridge	157:e7ca05fa8600	1811	* @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
AnnaBridge	157:e7ca05fa8600	1812	* @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC
AnnaBridge	157:e7ca05fa8600	1813	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1814	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1815	*/
AnnaBridge	157:e7ca05fa8600	1816	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1817	{
AnnaBridge	157:e7ca05fa8600	1818	return (READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
AnnaBridge	157:e7ca05fa8600	1819	}
AnnaBridge	157:e7ca05fa8600	1820
AnnaBridge	157:e7ca05fa8600	1821	/**
AnnaBridge	157:e7ca05fa8600	1822	* @brief Check if the LPUART TX Empty Interrupt is enabled or disabled.
AnnaBridge	157:e7ca05fa8600	1823	* @rmtoll CR1 TXEIE LL_LPUART_IsEnabledIT_TXE
AnnaBridge	157:e7ca05fa8600	1824	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1825	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1826	*/
AnnaBridge	157:e7ca05fa8600	1827	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1828	{
AnnaBridge	157:e7ca05fa8600	1829	return (READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
AnnaBridge	157:e7ca05fa8600	1830	}
AnnaBridge	157:e7ca05fa8600	1831
AnnaBridge	157:e7ca05fa8600	1832	/**
AnnaBridge	157:e7ca05fa8600	1833	* @brief Check if the LPUART Parity Error Interrupt is enabled or disabled.
AnnaBridge	157:e7ca05fa8600	1834	* @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE
AnnaBridge	157:e7ca05fa8600	1835	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1836	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1837	*/
AnnaBridge	157:e7ca05fa8600	1838	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1839	{
AnnaBridge	157:e7ca05fa8600	1840	return (READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
AnnaBridge	157:e7ca05fa8600	1841	}
AnnaBridge	157:e7ca05fa8600	1842
AnnaBridge	157:e7ca05fa8600	1843	/**
AnnaBridge	157:e7ca05fa8600	1844	* @brief Check if the LPUART Character Match Interrupt is enabled or disabled.
AnnaBridge	157:e7ca05fa8600	1845	* @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM
AnnaBridge	157:e7ca05fa8600	1846	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1847	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1848	*/
AnnaBridge	157:e7ca05fa8600	1849	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1850	{
AnnaBridge	157:e7ca05fa8600	1851	return (READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE));
AnnaBridge	157:e7ca05fa8600	1852	}
AnnaBridge	157:e7ca05fa8600	1853
AnnaBridge	157:e7ca05fa8600	1854	/**
AnnaBridge	157:e7ca05fa8600	1855	* @brief Check if the LPUART Error Interrupt is enabled or disabled.
AnnaBridge	157:e7ca05fa8600	1856	* @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR
AnnaBridge	157:e7ca05fa8600	1857	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1858	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1859	*/
AnnaBridge	157:e7ca05fa8600	1860	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1861	{
AnnaBridge	157:e7ca05fa8600	1862	return (READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
AnnaBridge	157:e7ca05fa8600	1863	}
AnnaBridge	157:e7ca05fa8600	1864
AnnaBridge	157:e7ca05fa8600	1865	/**
AnnaBridge	157:e7ca05fa8600	1866	* @brief Check if the LPUART CTS Interrupt is enabled or disabled.
AnnaBridge	157:e7ca05fa8600	1867	* @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
AnnaBridge	157:e7ca05fa8600	1868	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1869	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1870	*/
AnnaBridge	157:e7ca05fa8600	1871	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1872	{
AnnaBridge	157:e7ca05fa8600	1873	return (READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
AnnaBridge	157:e7ca05fa8600	1874	}
AnnaBridge	157:e7ca05fa8600	1875
AnnaBridge	157:e7ca05fa8600	1876	/**
AnnaBridge	157:e7ca05fa8600	1877	* @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
AnnaBridge	157:e7ca05fa8600	1878	* @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP
AnnaBridge	157:e7ca05fa8600	1879	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1880	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1881	*/
AnnaBridge	157:e7ca05fa8600	1882	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1883	{
AnnaBridge	157:e7ca05fa8600	1884	return (READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE));
AnnaBridge	157:e7ca05fa8600	1885	}
AnnaBridge	157:e7ca05fa8600	1886
AnnaBridge	157:e7ca05fa8600	1887	/**
AnnaBridge	157:e7ca05fa8600	1888	* @}
AnnaBridge	157:e7ca05fa8600	1889	*/
AnnaBridge	157:e7ca05fa8600	1890
AnnaBridge	157:e7ca05fa8600	1891	/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
AnnaBridge	157:e7ca05fa8600	1892	* @{
AnnaBridge	157:e7ca05fa8600	1893	*/
AnnaBridge	157:e7ca05fa8600	1894
AnnaBridge	157:e7ca05fa8600	1895	/**
AnnaBridge	157:e7ca05fa8600	1896	* @brief Enable DMA Mode for reception
AnnaBridge	157:e7ca05fa8600	1897	* @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX
AnnaBridge	157:e7ca05fa8600	1898	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1899	* @retval None
AnnaBridge	157:e7ca05fa8600	1900	*/
AnnaBridge	157:e7ca05fa8600	1901	__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1902	{
AnnaBridge	157:e7ca05fa8600	1903	SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
AnnaBridge	157:e7ca05fa8600	1904	}
AnnaBridge	157:e7ca05fa8600	1905
AnnaBridge	157:e7ca05fa8600	1906	/**
AnnaBridge	157:e7ca05fa8600	1907	* @brief Disable DMA Mode for reception
AnnaBridge	157:e7ca05fa8600	1908	* @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX
AnnaBridge	157:e7ca05fa8600	1909	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1910	* @retval None
AnnaBridge	157:e7ca05fa8600	1911	*/
AnnaBridge	157:e7ca05fa8600	1912	__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1913	{
AnnaBridge	157:e7ca05fa8600	1914	CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
AnnaBridge	157:e7ca05fa8600	1915	}
AnnaBridge	157:e7ca05fa8600	1916
AnnaBridge	157:e7ca05fa8600	1917	/**
AnnaBridge	157:e7ca05fa8600	1918	* @brief Check if DMA Mode is enabled for reception
AnnaBridge	157:e7ca05fa8600	1919	* @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
AnnaBridge	157:e7ca05fa8600	1920	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1921	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1922	*/
AnnaBridge	157:e7ca05fa8600	1923	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1924	{
AnnaBridge	157:e7ca05fa8600	1925	return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
AnnaBridge	157:e7ca05fa8600	1926	}
AnnaBridge	157:e7ca05fa8600	1927
AnnaBridge	157:e7ca05fa8600	1928	/**
AnnaBridge	157:e7ca05fa8600	1929	* @brief Enable DMA Mode for transmission
AnnaBridge	157:e7ca05fa8600	1930	* @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX
AnnaBridge	157:e7ca05fa8600	1931	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1932	* @retval None
AnnaBridge	157:e7ca05fa8600	1933	*/
AnnaBridge	157:e7ca05fa8600	1934	__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1935	{
AnnaBridge	157:e7ca05fa8600	1936	SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
AnnaBridge	157:e7ca05fa8600	1937	}
AnnaBridge	157:e7ca05fa8600	1938
AnnaBridge	157:e7ca05fa8600	1939	/**
AnnaBridge	157:e7ca05fa8600	1940	* @brief Disable DMA Mode for transmission
AnnaBridge	157:e7ca05fa8600	1941	* @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX
AnnaBridge	157:e7ca05fa8600	1942	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1943	* @retval None
AnnaBridge	157:e7ca05fa8600	1944	*/
AnnaBridge	157:e7ca05fa8600	1945	__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1946	{
AnnaBridge	157:e7ca05fa8600	1947	CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
AnnaBridge	157:e7ca05fa8600	1948	}
AnnaBridge	157:e7ca05fa8600	1949
AnnaBridge	157:e7ca05fa8600	1950	/**
AnnaBridge	157:e7ca05fa8600	1951	* @brief Check if DMA Mode is enabled for transmission
AnnaBridge	157:e7ca05fa8600	1952	* @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
AnnaBridge	157:e7ca05fa8600	1953	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1954	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1955	*/
AnnaBridge	157:e7ca05fa8600	1956	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1957	{
AnnaBridge	157:e7ca05fa8600	1958	return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
AnnaBridge	157:e7ca05fa8600	1959	}
AnnaBridge	157:e7ca05fa8600	1960
AnnaBridge	157:e7ca05fa8600	1961	/**
AnnaBridge	157:e7ca05fa8600	1962	* @brief Enable DMA Disabling on Reception Error
AnnaBridge	157:e7ca05fa8600	1963	* @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
AnnaBridge	157:e7ca05fa8600	1964	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1965	* @retval None
AnnaBridge	157:e7ca05fa8600	1966	*/
AnnaBridge	157:e7ca05fa8600	1967	__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1968	{
AnnaBridge	157:e7ca05fa8600	1969	SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
AnnaBridge	157:e7ca05fa8600	1970	}
AnnaBridge	157:e7ca05fa8600	1971
AnnaBridge	157:e7ca05fa8600	1972	/**
AnnaBridge	157:e7ca05fa8600	1973	* @brief Disable DMA Disabling on Reception Error
AnnaBridge	157:e7ca05fa8600	1974	* @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
AnnaBridge	157:e7ca05fa8600	1975	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1976	* @retval None
AnnaBridge	157:e7ca05fa8600	1977	*/
AnnaBridge	157:e7ca05fa8600	1978	__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1979	{
AnnaBridge	157:e7ca05fa8600	1980	CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
AnnaBridge	157:e7ca05fa8600	1981	}
AnnaBridge	157:e7ca05fa8600	1982
AnnaBridge	157:e7ca05fa8600	1983	/**
AnnaBridge	157:e7ca05fa8600	1984	* @brief Indicate if DMA Disabling on Reception Error is disabled
AnnaBridge	157:e7ca05fa8600	1985	* @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
AnnaBridge	157:e7ca05fa8600	1986	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1987	* @retval State of bit (1 or 0).
AnnaBridge	157:e7ca05fa8600	1988	*/
AnnaBridge	157:e7ca05fa8600	1989	__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	1990	{
AnnaBridge	157:e7ca05fa8600	1991	return (READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE));
AnnaBridge	157:e7ca05fa8600	1992	}
AnnaBridge	157:e7ca05fa8600	1993
AnnaBridge	157:e7ca05fa8600	1994	/**
AnnaBridge	157:e7ca05fa8600	1995	* @brief Get the LPUART data register address used for DMA transfer
AnnaBridge	157:e7ca05fa8600	1996	* @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n
AnnaBridge	157:e7ca05fa8600	1997	* @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr
AnnaBridge	157:e7ca05fa8600	1998	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	1999	* @param Direction This parameter can be one of the following values:
AnnaBridge	157:e7ca05fa8600	2000	* @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
AnnaBridge	157:e7ca05fa8600	2001	* @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
AnnaBridge	157:e7ca05fa8600	2002	* @retval Address of data register
AnnaBridge	157:e7ca05fa8600	2003	*/
AnnaBridge	157:e7ca05fa8600	2004	__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
AnnaBridge	157:e7ca05fa8600	2005	{
AnnaBridge	157:e7ca05fa8600	2006	register uint32_t data_reg_addr = 0U;
AnnaBridge	157:e7ca05fa8600	2007
AnnaBridge	157:e7ca05fa8600	2008	if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
AnnaBridge	157:e7ca05fa8600	2009	{
AnnaBridge	157:e7ca05fa8600	2010	/* return address of TDR register */
AnnaBridge	157:e7ca05fa8600	2011	data_reg_addr = (uint32_t) &(LPUARTx->TDR);
AnnaBridge	157:e7ca05fa8600	2012	}
AnnaBridge	157:e7ca05fa8600	2013	else
AnnaBridge	157:e7ca05fa8600	2014	{
AnnaBridge	157:e7ca05fa8600	2015	/* return address of RDR register */
AnnaBridge	157:e7ca05fa8600	2016	data_reg_addr = (uint32_t) &(LPUARTx->RDR);
AnnaBridge	157:e7ca05fa8600	2017	}
AnnaBridge	157:e7ca05fa8600	2018
AnnaBridge	157:e7ca05fa8600	2019	return data_reg_addr;
AnnaBridge	157:e7ca05fa8600	2020	}
AnnaBridge	157:e7ca05fa8600	2021
AnnaBridge	157:e7ca05fa8600	2022	/**
AnnaBridge	157:e7ca05fa8600	2023	* @}
AnnaBridge	157:e7ca05fa8600	2024	*/
AnnaBridge	157:e7ca05fa8600	2025
AnnaBridge	157:e7ca05fa8600	2026	/** @defgroup LPUART_LL_EF_Data_Management Data_Management
AnnaBridge	157:e7ca05fa8600	2027	* @{
AnnaBridge	157:e7ca05fa8600	2028	*/
AnnaBridge	157:e7ca05fa8600	2029
AnnaBridge	157:e7ca05fa8600	2030	/**
AnnaBridge	157:e7ca05fa8600	2031	* @brief Read Receiver Data register (Receive Data value, 8 bits)
AnnaBridge	157:e7ca05fa8600	2032	* @rmtoll RDR RDR LL_LPUART_ReceiveData8
AnnaBridge	157:e7ca05fa8600	2033	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	2034	* @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	157:e7ca05fa8600	2035	*/
AnnaBridge	157:e7ca05fa8600	2036	__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	2037	{
AnnaBridge	157:e7ca05fa8600	2038	return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
AnnaBridge	157:e7ca05fa8600	2039	}
AnnaBridge	157:e7ca05fa8600	2040
AnnaBridge	157:e7ca05fa8600	2041	/**
AnnaBridge	157:e7ca05fa8600	2042	* @brief Read Receiver Data register (Receive Data value, 9 bits)
AnnaBridge	157:e7ca05fa8600	2043	* @rmtoll RDR RDR LL_LPUART_ReceiveData9
AnnaBridge	157:e7ca05fa8600	2044	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	2045	* @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
AnnaBridge	157:e7ca05fa8600	2046	*/
AnnaBridge	157:e7ca05fa8600	2047	__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	2048	{
AnnaBridge	157:e7ca05fa8600	2049	return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
AnnaBridge	157:e7ca05fa8600	2050	}
AnnaBridge	157:e7ca05fa8600	2051
AnnaBridge	157:e7ca05fa8600	2052	/**
AnnaBridge	157:e7ca05fa8600	2053	* @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
AnnaBridge	157:e7ca05fa8600	2054	* @rmtoll TDR TDR LL_LPUART_TransmitData8
AnnaBridge	157:e7ca05fa8600	2055	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	2056	* @param Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	157:e7ca05fa8600	2057	* @retval None
AnnaBridge	157:e7ca05fa8600	2058	*/
AnnaBridge	157:e7ca05fa8600	2059	__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
AnnaBridge	157:e7ca05fa8600	2060	{
AnnaBridge	157:e7ca05fa8600	2061	LPUARTx->TDR = Value;
AnnaBridge	157:e7ca05fa8600	2062	}
AnnaBridge	157:e7ca05fa8600	2063
AnnaBridge	157:e7ca05fa8600	2064	/**
AnnaBridge	157:e7ca05fa8600	2065	* @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
AnnaBridge	157:e7ca05fa8600	2066	* @rmtoll TDR TDR LL_LPUART_TransmitData9
AnnaBridge	157:e7ca05fa8600	2067	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	2068	* @param Value between Min_Data=0x00 and Max_Data=0x1FF
AnnaBridge	157:e7ca05fa8600	2069	* @retval None
AnnaBridge	157:e7ca05fa8600	2070	*/
AnnaBridge	157:e7ca05fa8600	2071	__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
AnnaBridge	157:e7ca05fa8600	2072	{
AnnaBridge	157:e7ca05fa8600	2073	LPUARTx->TDR = Value & 0x1FFU;
AnnaBridge	157:e7ca05fa8600	2074	}
AnnaBridge	157:e7ca05fa8600	2075
AnnaBridge	157:e7ca05fa8600	2076	/**
AnnaBridge	157:e7ca05fa8600	2077	* @}
AnnaBridge	157:e7ca05fa8600	2078	*/
AnnaBridge	157:e7ca05fa8600	2079
AnnaBridge	157:e7ca05fa8600	2080	/** @defgroup LPUART_LL_EF_Execution Execution
AnnaBridge	157:e7ca05fa8600	2081	* @{
AnnaBridge	157:e7ca05fa8600	2082	*/
AnnaBridge	157:e7ca05fa8600	2083
AnnaBridge	157:e7ca05fa8600	2084	/**
AnnaBridge	157:e7ca05fa8600	2085	* @brief Request Break sending
AnnaBridge	157:e7ca05fa8600	2086	* @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending
AnnaBridge	157:e7ca05fa8600	2087	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	2088	* @retval None
AnnaBridge	157:e7ca05fa8600	2089	*/
AnnaBridge	157:e7ca05fa8600	2090	__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	2091	{
AnnaBridge	157:e7ca05fa8600	2092	SET_BIT(LPUARTx->RQR, USART_RQR_SBKRQ);
AnnaBridge	157:e7ca05fa8600	2093	}
AnnaBridge	157:e7ca05fa8600	2094
AnnaBridge	157:e7ca05fa8600	2095	/**
AnnaBridge	157:e7ca05fa8600	2096	* @brief Put LPUART in mute mode and set the RWU flag
AnnaBridge	157:e7ca05fa8600	2097	* @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode
AnnaBridge	157:e7ca05fa8600	2098	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	2099	* @retval None
AnnaBridge	157:e7ca05fa8600	2100	*/
AnnaBridge	157:e7ca05fa8600	2101	__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	2102	{
AnnaBridge	157:e7ca05fa8600	2103	SET_BIT(LPUARTx->RQR, USART_RQR_MMRQ);
AnnaBridge	157:e7ca05fa8600	2104	}
AnnaBridge	157:e7ca05fa8600	2105
AnnaBridge	157:e7ca05fa8600	2106	/**
AnnaBridge	157:e7ca05fa8600	2107	* @brief Request a Receive Data flush
AnnaBridge	157:e7ca05fa8600	2108	* @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush
AnnaBridge	157:e7ca05fa8600	2109	* @param LPUARTx LPUART Instance
AnnaBridge	157:e7ca05fa8600	2110	* @retval None
AnnaBridge	157:e7ca05fa8600	2111	*/
AnnaBridge	157:e7ca05fa8600	2112	__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
AnnaBridge	157:e7ca05fa8600	2113	{
AnnaBridge	157:e7ca05fa8600	2114	SET_BIT(LPUARTx->RQR, USART_RQR_RXFRQ);
AnnaBridge	157:e7ca05fa8600	2115	}
AnnaBridge	157:e7ca05fa8600	2116
AnnaBridge	157:e7ca05fa8600	2117	/**
AnnaBridge	157:e7ca05fa8600	2118	* @}
AnnaBridge	157:e7ca05fa8600	2119	*/
AnnaBridge	157:e7ca05fa8600	2120
AnnaBridge	157:e7ca05fa8600	2121	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	157:e7ca05fa8600	2122	/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	157:e7ca05fa8600	2123	* @{
AnnaBridge	157:e7ca05fa8600	2124	*/
AnnaBridge	157:e7ca05fa8600	2125	ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
AnnaBridge	157:e7ca05fa8600	2126	ErrorStatus LL_LPUART_Init(USART_TypeDef LPUARTx, LL_LPUART_InitTypeDef LPUART_InitStruct);
AnnaBridge	157:e7ca05fa8600	2127	void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
AnnaBridge	157:e7ca05fa8600	2128	/**
AnnaBridge	157:e7ca05fa8600	2129	* @}
AnnaBridge	157:e7ca05fa8600	2130	*/
AnnaBridge	157:e7ca05fa8600	2131	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	157:e7ca05fa8600	2132
AnnaBridge	157:e7ca05fa8600	2133	/**
AnnaBridge	157:e7ca05fa8600	2134	* @}
AnnaBridge	157:e7ca05fa8600	2135	*/
AnnaBridge	157:e7ca05fa8600	2136
AnnaBridge	157:e7ca05fa8600	2137	/**
AnnaBridge	157:e7ca05fa8600	2138	* @}
AnnaBridge	157:e7ca05fa8600	2139	*/
AnnaBridge	157:e7ca05fa8600	2140
AnnaBridge	157:e7ca05fa8600	2141	#endif /* LPUART1 */
AnnaBridge	157:e7ca05fa8600	2142
AnnaBridge	157:e7ca05fa8600	2143	/**
AnnaBridge	157:e7ca05fa8600	2144	* @}
AnnaBridge	157:e7ca05fa8600	2145	*/
AnnaBridge	157:e7ca05fa8600	2146
AnnaBridge	157:e7ca05fa8600	2147	#ifdef __cplusplus
AnnaBridge	157:e7ca05fa8600	2148	}
AnnaBridge	157:e7ca05fa8600	2149	#endif
AnnaBridge	157:e7ca05fa8600	2150
AnnaBridge	157:e7ca05fa8600	2151	#endif /* __STM32L0xx_LL_LPUART_H */
AnnaBridge	157:e7ca05fa8600	2152
AnnaBridge	157:e7ca05fa8600	2153	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/