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TARGET_NUCLEO_L011K4/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_lpuart.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 09 11:14:10 2017 +0000
Revision:
157:e7ca05fa8600
Child:
167:84c0a372a020
Release 155 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 157:e7ca05fa8600 1 /**
AnnaBridge 157:e7ca05fa8600 2 ******************************************************************************
AnnaBridge 157:e7ca05fa8600 3 * @file stm32l0xx_ll_lpuart.h
AnnaBridge 157:e7ca05fa8600 4 * @author MCD Application Team
AnnaBridge 157:e7ca05fa8600 5 * @version V1.7.0
AnnaBridge 157:e7ca05fa8600 6 * @date 31-May-2016
AnnaBridge 157:e7ca05fa8600 7 * @brief Header file of LPUART LL module.
AnnaBridge 157:e7ca05fa8600 8 ******************************************************************************
AnnaBridge 157:e7ca05fa8600 9 * @attention
AnnaBridge 157:e7ca05fa8600 10 *
AnnaBridge 157:e7ca05fa8600 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 157:e7ca05fa8600 12 *
AnnaBridge 157:e7ca05fa8600 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 157:e7ca05fa8600 14 * are permitted provided that the following conditions are met:
AnnaBridge 157:e7ca05fa8600 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 157:e7ca05fa8600 16 * this list of conditions and the following disclaimer.
AnnaBridge 157:e7ca05fa8600 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 157:e7ca05fa8600 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 157:e7ca05fa8600 19 * and/or other materials provided with the distribution.
AnnaBridge 157:e7ca05fa8600 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 157:e7ca05fa8600 21 * may be used to endorse or promote products derived from this software
AnnaBridge 157:e7ca05fa8600 22 * without specific prior written permission.
AnnaBridge 157:e7ca05fa8600 23 *
AnnaBridge 157:e7ca05fa8600 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 157:e7ca05fa8600 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 157:e7ca05fa8600 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 157:e7ca05fa8600 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 157:e7ca05fa8600 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 157:e7ca05fa8600 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 157:e7ca05fa8600 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 157:e7ca05fa8600 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 157:e7ca05fa8600 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 157:e7ca05fa8600 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 157:e7ca05fa8600 34 *
AnnaBridge 157:e7ca05fa8600 35 ******************************************************************************
AnnaBridge 157:e7ca05fa8600 36 */
AnnaBridge 157:e7ca05fa8600 37
AnnaBridge 157:e7ca05fa8600 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 157:e7ca05fa8600 39 #ifndef __STM32L0xx_LL_LPUART_H
AnnaBridge 157:e7ca05fa8600 40 #define __STM32L0xx_LL_LPUART_H
AnnaBridge 157:e7ca05fa8600 41
AnnaBridge 157:e7ca05fa8600 42 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 43 extern "C" {
AnnaBridge 157:e7ca05fa8600 44 #endif
AnnaBridge 157:e7ca05fa8600 45
AnnaBridge 157:e7ca05fa8600 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 47 #include "stm32l0xx.h"
AnnaBridge 157:e7ca05fa8600 48
AnnaBridge 157:e7ca05fa8600 49 /** @addtogroup STM32L0xx_LL_Driver
AnnaBridge 157:e7ca05fa8600 50 * @{
AnnaBridge 157:e7ca05fa8600 51 */
AnnaBridge 157:e7ca05fa8600 52
AnnaBridge 157:e7ca05fa8600 53 #if defined (LPUART1)
AnnaBridge 157:e7ca05fa8600 54
AnnaBridge 157:e7ca05fa8600 55 /** @defgroup LPUART_LL LPUART
AnnaBridge 157:e7ca05fa8600 56 * @{
AnnaBridge 157:e7ca05fa8600 57 */
AnnaBridge 157:e7ca05fa8600 58
AnnaBridge 157:e7ca05fa8600 59 /* Private types -------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 60 /* Private variables ---------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 61
AnnaBridge 157:e7ca05fa8600 62 /* Private constants ---------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 63 /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
AnnaBridge 157:e7ca05fa8600 64 * @{
AnnaBridge 157:e7ca05fa8600 65 */
AnnaBridge 157:e7ca05fa8600 66
AnnaBridge 157:e7ca05fa8600 67 /* Defines used for the bit position in the register and perform offsets*/
AnnaBridge 157:e7ca05fa8600 68 #define LPUART_POSITION_CR1_DEDT (uint32_t)16U
AnnaBridge 157:e7ca05fa8600 69 #define LPUART_POSITION_CR1_DEAT (uint32_t)21U
AnnaBridge 157:e7ca05fa8600 70 #define LPUART_POSITION_CR2_ADD (uint32_t)24U
AnnaBridge 157:e7ca05fa8600 71
AnnaBridge 157:e7ca05fa8600 72 /* Defines used in Baud Rate related macros and corresponding register setting computation */
AnnaBridge 157:e7ca05fa8600 73 #define LPUART_LPUARTDIV_FREQ_MUL (uint32_t)(256U)
AnnaBridge 157:e7ca05fa8600 74 #define LPUART_BRR_MASK (uint32_t)(0x000FFFFFU)
AnnaBridge 157:e7ca05fa8600 75 #define LPUART_BRR_MIN_VALUE (uint32_t)(0x00000300U)
AnnaBridge 157:e7ca05fa8600 76 /**
AnnaBridge 157:e7ca05fa8600 77 * @}
AnnaBridge 157:e7ca05fa8600 78 */
AnnaBridge 157:e7ca05fa8600 79
AnnaBridge 157:e7ca05fa8600 80
AnnaBridge 157:e7ca05fa8600 81 /* Private macros ------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 82 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 157:e7ca05fa8600 83 /** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
AnnaBridge 157:e7ca05fa8600 84 * @{
AnnaBridge 157:e7ca05fa8600 85 */
AnnaBridge 157:e7ca05fa8600 86 /**
AnnaBridge 157:e7ca05fa8600 87 * @}
AnnaBridge 157:e7ca05fa8600 88 */
AnnaBridge 157:e7ca05fa8600 89 #endif /*USE_FULL_LL_DRIVER*/
AnnaBridge 157:e7ca05fa8600 90
AnnaBridge 157:e7ca05fa8600 91 /* Exported types ------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 92 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 157:e7ca05fa8600 93 /** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
AnnaBridge 157:e7ca05fa8600 94 * @{
AnnaBridge 157:e7ca05fa8600 95 */
AnnaBridge 157:e7ca05fa8600 96
AnnaBridge 157:e7ca05fa8600 97 /**
AnnaBridge 157:e7ca05fa8600 98 * @brief LL LPUART Init Structure definition
AnnaBridge 157:e7ca05fa8600 99 */
AnnaBridge 157:e7ca05fa8600 100 typedef struct
AnnaBridge 157:e7ca05fa8600 101 {
AnnaBridge 157:e7ca05fa8600 102 uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate.
AnnaBridge 157:e7ca05fa8600 103
AnnaBridge 157:e7ca05fa8600 104 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/
AnnaBridge 157:e7ca05fa8600 105
AnnaBridge 157:e7ca05fa8600 106 uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
AnnaBridge 157:e7ca05fa8600 107 This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
AnnaBridge 157:e7ca05fa8600 108
AnnaBridge 157:e7ca05fa8600 109 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetDataWidth().*/
AnnaBridge 157:e7ca05fa8600 110
AnnaBridge 157:e7ca05fa8600 111 uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
AnnaBridge 157:e7ca05fa8600 112 This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
AnnaBridge 157:e7ca05fa8600 113
AnnaBridge 157:e7ca05fa8600 114 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetStopBitsLength().*/
AnnaBridge 157:e7ca05fa8600 115
AnnaBridge 157:e7ca05fa8600 116 uint32_t Parity; /*!< Specifies the parity mode.
AnnaBridge 157:e7ca05fa8600 117 This parameter can be a value of @ref LPUART_LL_EC_PARITY.
AnnaBridge 157:e7ca05fa8600 118
AnnaBridge 157:e7ca05fa8600 119 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetParity().*/
AnnaBridge 157:e7ca05fa8600 120
AnnaBridge 157:e7ca05fa8600 121 uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
AnnaBridge 157:e7ca05fa8600 122 This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
AnnaBridge 157:e7ca05fa8600 123
AnnaBridge 157:e7ca05fa8600 124 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetTransferDirection().*/
AnnaBridge 157:e7ca05fa8600 125
AnnaBridge 157:e7ca05fa8600 126 uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
AnnaBridge 157:e7ca05fa8600 127 This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
AnnaBridge 157:e7ca05fa8600 128
AnnaBridge 157:e7ca05fa8600 129 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetHWFlowCtrl().*/
AnnaBridge 157:e7ca05fa8600 130
AnnaBridge 157:e7ca05fa8600 131 } LL_LPUART_InitTypeDef;
AnnaBridge 157:e7ca05fa8600 132
AnnaBridge 157:e7ca05fa8600 133 /**
AnnaBridge 157:e7ca05fa8600 134 * @}
AnnaBridge 157:e7ca05fa8600 135 */
AnnaBridge 157:e7ca05fa8600 136 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 157:e7ca05fa8600 137
AnnaBridge 157:e7ca05fa8600 138 /* Exported constants --------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 139 /** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
AnnaBridge 157:e7ca05fa8600 140 * @{
AnnaBridge 157:e7ca05fa8600 141 */
AnnaBridge 157:e7ca05fa8600 142
AnnaBridge 157:e7ca05fa8600 143 /** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge 157:e7ca05fa8600 144 * @brief Flags defines which can be used with LL_LPUART_WriteReg function
AnnaBridge 157:e7ca05fa8600 145 * @{
AnnaBridge 157:e7ca05fa8600 146 */
AnnaBridge 157:e7ca05fa8600 147 #define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */
AnnaBridge 157:e7ca05fa8600 148 #define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */
AnnaBridge 157:e7ca05fa8600 149 #define LL_LPUART_ICR_NCF USART_ICR_NCF /*!< Noise detected flag */
AnnaBridge 157:e7ca05fa8600 150 #define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */
AnnaBridge 157:e7ca05fa8600 151 #define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */
AnnaBridge 157:e7ca05fa8600 152 #define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */
AnnaBridge 157:e7ca05fa8600 153 #define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */
AnnaBridge 157:e7ca05fa8600 154 #define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */
AnnaBridge 157:e7ca05fa8600 155 #define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */
AnnaBridge 157:e7ca05fa8600 156 /**
AnnaBridge 157:e7ca05fa8600 157 * @}
AnnaBridge 157:e7ca05fa8600 158 */
AnnaBridge 157:e7ca05fa8600 159
AnnaBridge 157:e7ca05fa8600 160 /** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge 157:e7ca05fa8600 161 * @brief Flags defines which can be used with LL_LPUART_ReadReg function
AnnaBridge 157:e7ca05fa8600 162 * @{
AnnaBridge 157:e7ca05fa8600 163 */
AnnaBridge 157:e7ca05fa8600 164 #define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
AnnaBridge 157:e7ca05fa8600 165 #define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
AnnaBridge 157:e7ca05fa8600 166 #define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
AnnaBridge 157:e7ca05fa8600 167 #define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
AnnaBridge 157:e7ca05fa8600 168 #define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
AnnaBridge 157:e7ca05fa8600 169 #define LL_LPUART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */
AnnaBridge 157:e7ca05fa8600 170 #define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
AnnaBridge 157:e7ca05fa8600 171 #define LL_LPUART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */
AnnaBridge 157:e7ca05fa8600 172 #define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
AnnaBridge 157:e7ca05fa8600 173 #define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
AnnaBridge 157:e7ca05fa8600 174 #define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
AnnaBridge 157:e7ca05fa8600 175 #define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
AnnaBridge 157:e7ca05fa8600 176 #define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
AnnaBridge 157:e7ca05fa8600 177 #define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
AnnaBridge 157:e7ca05fa8600 178 #define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
AnnaBridge 157:e7ca05fa8600 179 #define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
AnnaBridge 157:e7ca05fa8600 180 #define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
AnnaBridge 157:e7ca05fa8600 181 /**
AnnaBridge 157:e7ca05fa8600 182 * @}
AnnaBridge 157:e7ca05fa8600 183 */
AnnaBridge 157:e7ca05fa8600 184
AnnaBridge 157:e7ca05fa8600 185 /** @defgroup LPUART_LL_EC_IT IT Defines
AnnaBridge 157:e7ca05fa8600 186 * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions
AnnaBridge 157:e7ca05fa8600 187 * @{
AnnaBridge 157:e7ca05fa8600 188 */
AnnaBridge 157:e7ca05fa8600 189 #define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
AnnaBridge 157:e7ca05fa8600 190 #define LL_LPUART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */
AnnaBridge 157:e7ca05fa8600 191 #define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
AnnaBridge 157:e7ca05fa8600 192 #define LL_LPUART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */
AnnaBridge 157:e7ca05fa8600 193 #define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
AnnaBridge 157:e7ca05fa8600 194 #define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
AnnaBridge 157:e7ca05fa8600 195 #define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
AnnaBridge 157:e7ca05fa8600 196 #define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
AnnaBridge 157:e7ca05fa8600 197 #define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
AnnaBridge 157:e7ca05fa8600 198 /**
AnnaBridge 157:e7ca05fa8600 199 * @}
AnnaBridge 157:e7ca05fa8600 200 */
AnnaBridge 157:e7ca05fa8600 201
AnnaBridge 157:e7ca05fa8600 202 /** @defgroup LPUART_LL_EC_DIRECTION Direction
AnnaBridge 157:e7ca05fa8600 203 * @{
AnnaBridge 157:e7ca05fa8600 204 */
AnnaBridge 157:e7ca05fa8600 205 #define LL_LPUART_DIRECTION_NONE (uint32_t)0x00000000U /*!< Transmitter and Receiver are disabled */
AnnaBridge 157:e7ca05fa8600 206 #define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
AnnaBridge 157:e7ca05fa8600 207 #define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
AnnaBridge 157:e7ca05fa8600 208 #define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
AnnaBridge 157:e7ca05fa8600 209 /**
AnnaBridge 157:e7ca05fa8600 210 * @}
AnnaBridge 157:e7ca05fa8600 211 */
AnnaBridge 157:e7ca05fa8600 212
AnnaBridge 157:e7ca05fa8600 213 /** @defgroup LPUART_LL_EC_PARITY Parity Control
AnnaBridge 157:e7ca05fa8600 214 * @{
AnnaBridge 157:e7ca05fa8600 215 */
AnnaBridge 157:e7ca05fa8600 216 #define LL_LPUART_PARITY_NONE (uint32_t)0x00000000U /*!< Parity control disabled */
AnnaBridge 157:e7ca05fa8600 217 #define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
AnnaBridge 157:e7ca05fa8600 218 #define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
AnnaBridge 157:e7ca05fa8600 219 /**
AnnaBridge 157:e7ca05fa8600 220 * @}
AnnaBridge 157:e7ca05fa8600 221 */
AnnaBridge 157:e7ca05fa8600 222
AnnaBridge 157:e7ca05fa8600 223 /** @defgroup LPUART_LL_EC_WAKEUP Wakeup
AnnaBridge 157:e7ca05fa8600 224 * @{
AnnaBridge 157:e7ca05fa8600 225 */
AnnaBridge 157:e7ca05fa8600 226 #define LL_LPUART_WAKEUP_IDLELINE (uint32_t)0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
AnnaBridge 157:e7ca05fa8600 227 #define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
AnnaBridge 157:e7ca05fa8600 228 /**
AnnaBridge 157:e7ca05fa8600 229 * @}
AnnaBridge 157:e7ca05fa8600 230 */
AnnaBridge 157:e7ca05fa8600 231
AnnaBridge 157:e7ca05fa8600 232 /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
AnnaBridge 157:e7ca05fa8600 233 * @{
AnnaBridge 157:e7ca05fa8600 234 */
AnnaBridge 157:e7ca05fa8600 235 #define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
AnnaBridge 157:e7ca05fa8600 236 #define LL_LPUART_DATAWIDTH_8B (uint32_t)0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
AnnaBridge 157:e7ca05fa8600 237 #define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
AnnaBridge 157:e7ca05fa8600 238 /**
AnnaBridge 157:e7ca05fa8600 239 * @}
AnnaBridge 157:e7ca05fa8600 240 */
AnnaBridge 157:e7ca05fa8600 241
AnnaBridge 157:e7ca05fa8600 242 /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
AnnaBridge 157:e7ca05fa8600 243 * @{
AnnaBridge 157:e7ca05fa8600 244 */
AnnaBridge 157:e7ca05fa8600 245 #define LL_LPUART_STOPBITS_1 (uint32_t)0x00000000U /*!< 1 stop bit */
AnnaBridge 157:e7ca05fa8600 246 #define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
AnnaBridge 157:e7ca05fa8600 247 /**
AnnaBridge 157:e7ca05fa8600 248 * @}
AnnaBridge 157:e7ca05fa8600 249 */
AnnaBridge 157:e7ca05fa8600 250
AnnaBridge 157:e7ca05fa8600 251 /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
AnnaBridge 157:e7ca05fa8600 252 * @{
AnnaBridge 157:e7ca05fa8600 253 */
AnnaBridge 157:e7ca05fa8600 254 #define LL_LPUART_TXRX_STANDARD (uint32_t)0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
AnnaBridge 157:e7ca05fa8600 255 #define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
AnnaBridge 157:e7ca05fa8600 256 /**
AnnaBridge 157:e7ca05fa8600 257 * @}
AnnaBridge 157:e7ca05fa8600 258 */
AnnaBridge 157:e7ca05fa8600 259
AnnaBridge 157:e7ca05fa8600 260 /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
AnnaBridge 157:e7ca05fa8600 261 * @{
AnnaBridge 157:e7ca05fa8600 262 */
AnnaBridge 157:e7ca05fa8600 263 #define LL_LPUART_RXPIN_LEVEL_STANDARD (uint32_t)0x00000000U /*!< RX pin signal works using the standard logic levels */
AnnaBridge 157:e7ca05fa8600 264 #define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
AnnaBridge 157:e7ca05fa8600 265 /**
AnnaBridge 157:e7ca05fa8600 266 * @}
AnnaBridge 157:e7ca05fa8600 267 */
AnnaBridge 157:e7ca05fa8600 268
AnnaBridge 157:e7ca05fa8600 269 /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
AnnaBridge 157:e7ca05fa8600 270 * @{
AnnaBridge 157:e7ca05fa8600 271 */
AnnaBridge 157:e7ca05fa8600 272 #define LL_LPUART_TXPIN_LEVEL_STANDARD (uint32_t)0x00000000U /*!< TX pin signal works using the standard logic levels */
AnnaBridge 157:e7ca05fa8600 273 #define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
AnnaBridge 157:e7ca05fa8600 274 /**
AnnaBridge 157:e7ca05fa8600 275 * @}
AnnaBridge 157:e7ca05fa8600 276 */
AnnaBridge 157:e7ca05fa8600 277
AnnaBridge 157:e7ca05fa8600 278 /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
AnnaBridge 157:e7ca05fa8600 279 * @{
AnnaBridge 157:e7ca05fa8600 280 */
AnnaBridge 157:e7ca05fa8600 281 #define LL_LPUART_BINARY_LOGIC_POSITIVE (uint32_t)0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
AnnaBridge 157:e7ca05fa8600 282 #define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
AnnaBridge 157:e7ca05fa8600 283 /**
AnnaBridge 157:e7ca05fa8600 284 * @}
AnnaBridge 157:e7ca05fa8600 285 */
AnnaBridge 157:e7ca05fa8600 286
AnnaBridge 157:e7ca05fa8600 287 /** @defgroup LPUART_LL_EC_BITORDER Bit Order
AnnaBridge 157:e7ca05fa8600 288 * @{
AnnaBridge 157:e7ca05fa8600 289 */
AnnaBridge 157:e7ca05fa8600 290 #define LL_LPUART_BITORDER_LSBFIRST (uint32_t)0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */
AnnaBridge 157:e7ca05fa8600 291 #define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */
AnnaBridge 157:e7ca05fa8600 292 /**
AnnaBridge 157:e7ca05fa8600 293 * @}
AnnaBridge 157:e7ca05fa8600 294 */
AnnaBridge 157:e7ca05fa8600 295
AnnaBridge 157:e7ca05fa8600 296 /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
AnnaBridge 157:e7ca05fa8600 297 * @{
AnnaBridge 157:e7ca05fa8600 298 */
AnnaBridge 157:e7ca05fa8600 299 #define LL_LPUART_ADDRESS_DETECT_4B (uint32_t)0x00000000U /*!< 4-bit address detection method selected */
AnnaBridge 157:e7ca05fa8600 300 #define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
AnnaBridge 157:e7ca05fa8600 301 /**
AnnaBridge 157:e7ca05fa8600 302 * @}
AnnaBridge 157:e7ca05fa8600 303 */
AnnaBridge 157:e7ca05fa8600 304
AnnaBridge 157:e7ca05fa8600 305 /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
AnnaBridge 157:e7ca05fa8600 306 * @{
AnnaBridge 157:e7ca05fa8600 307 */
AnnaBridge 157:e7ca05fa8600 308 #define LL_LPUART_HWCONTROL_NONE (uint32_t)0x00000000U /*!< CTS and RTS hardware flow control disabled */
AnnaBridge 157:e7ca05fa8600 309 #define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
AnnaBridge 157:e7ca05fa8600 310 #define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
AnnaBridge 157:e7ca05fa8600 311 #define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
AnnaBridge 157:e7ca05fa8600 312 /**
AnnaBridge 157:e7ca05fa8600 313 * @}
AnnaBridge 157:e7ca05fa8600 314 */
AnnaBridge 157:e7ca05fa8600 315
AnnaBridge 157:e7ca05fa8600 316 /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
AnnaBridge 157:e7ca05fa8600 317 * @{
AnnaBridge 157:e7ca05fa8600 318 */
AnnaBridge 157:e7ca05fa8600 319 #define LL_LPUART_WAKEUP_ON_ADDRESS (uint32_t)0x00000000U /*!< Wake up active on address match */
AnnaBridge 157:e7ca05fa8600 320 #define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
AnnaBridge 157:e7ca05fa8600 321 #define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
AnnaBridge 157:e7ca05fa8600 322 /**
AnnaBridge 157:e7ca05fa8600 323 * @}
AnnaBridge 157:e7ca05fa8600 324 */
AnnaBridge 157:e7ca05fa8600 325
AnnaBridge 157:e7ca05fa8600 326 /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
AnnaBridge 157:e7ca05fa8600 327 * @{
AnnaBridge 157:e7ca05fa8600 328 */
AnnaBridge 157:e7ca05fa8600 329 #define LL_LPUART_DE_POLARITY_HIGH (uint32_t)0x00000000U /*!< DE signal is active high */
AnnaBridge 157:e7ca05fa8600 330 #define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
AnnaBridge 157:e7ca05fa8600 331 /**
AnnaBridge 157:e7ca05fa8600 332 * @}
AnnaBridge 157:e7ca05fa8600 333 */
AnnaBridge 157:e7ca05fa8600 334
AnnaBridge 157:e7ca05fa8600 335 /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
AnnaBridge 157:e7ca05fa8600 336 * @{
AnnaBridge 157:e7ca05fa8600 337 */
AnnaBridge 157:e7ca05fa8600 338 #define LL_LPUART_DMA_REG_DATA_TRANSMIT (uint32_t)0U /*!< Get address of data register used for transmission */
AnnaBridge 157:e7ca05fa8600 339 #define LL_LPUART_DMA_REG_DATA_RECEIVE (uint32_t)1U /*!< Get address of data register used for reception */
AnnaBridge 157:e7ca05fa8600 340 /**
AnnaBridge 157:e7ca05fa8600 341 * @}
AnnaBridge 157:e7ca05fa8600 342 */
AnnaBridge 157:e7ca05fa8600 343
AnnaBridge 157:e7ca05fa8600 344 /**
AnnaBridge 157:e7ca05fa8600 345 * @}
AnnaBridge 157:e7ca05fa8600 346 */
AnnaBridge 157:e7ca05fa8600 347
AnnaBridge 157:e7ca05fa8600 348 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 349 /** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
AnnaBridge 157:e7ca05fa8600 350 * @{
AnnaBridge 157:e7ca05fa8600 351 */
AnnaBridge 157:e7ca05fa8600 352
AnnaBridge 157:e7ca05fa8600 353 /** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge 157:e7ca05fa8600 354 * @{
AnnaBridge 157:e7ca05fa8600 355 */
AnnaBridge 157:e7ca05fa8600 356
AnnaBridge 157:e7ca05fa8600 357 /**
AnnaBridge 157:e7ca05fa8600 358 * @brief Write a value in LPUART register
AnnaBridge 157:e7ca05fa8600 359 * @param __INSTANCE__ LPUART Instance
AnnaBridge 157:e7ca05fa8600 360 * @param __REG__ Register to be written
AnnaBridge 157:e7ca05fa8600 361 * @param __VALUE__ Value to be written in the register
AnnaBridge 157:e7ca05fa8600 362 * @retval None
AnnaBridge 157:e7ca05fa8600 363 */
AnnaBridge 157:e7ca05fa8600 364 #define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge 157:e7ca05fa8600 365
AnnaBridge 157:e7ca05fa8600 366 /**
AnnaBridge 157:e7ca05fa8600 367 * @brief Read a value in LPUART register
AnnaBridge 157:e7ca05fa8600 368 * @param __INSTANCE__ LPUART Instance
AnnaBridge 157:e7ca05fa8600 369 * @param __REG__ Register to be read
AnnaBridge 157:e7ca05fa8600 370 * @retval Register value
AnnaBridge 157:e7ca05fa8600 371 */
AnnaBridge 157:e7ca05fa8600 372 #define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge 157:e7ca05fa8600 373 /**
AnnaBridge 157:e7ca05fa8600 374 * @}
AnnaBridge 157:e7ca05fa8600 375 */
AnnaBridge 157:e7ca05fa8600 376
AnnaBridge 157:e7ca05fa8600 377 /** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
AnnaBridge 157:e7ca05fa8600 378 * @{
AnnaBridge 157:e7ca05fa8600 379 */
AnnaBridge 157:e7ca05fa8600 380
AnnaBridge 157:e7ca05fa8600 381 /**
AnnaBridge 157:e7ca05fa8600 382 * @brief Compute LPUARTDIV value according to Peripheral Clock and
AnnaBridge 157:e7ca05fa8600 383 * expected Baud Rate (20-bit value of LPUARTDIV is returned)
AnnaBridge 157:e7ca05fa8600 384 * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
AnnaBridge 157:e7ca05fa8600 385 * @param __BAUDRATE__ Baud Rate value to achieve
AnnaBridge 157:e7ca05fa8600 386 * @retval LPUARTDIV value to be used for BRR register filling
AnnaBridge 157:e7ca05fa8600 387 */
AnnaBridge 157:e7ca05fa8600 388 #define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK)
AnnaBridge 157:e7ca05fa8600 389
AnnaBridge 157:e7ca05fa8600 390 /**
AnnaBridge 157:e7ca05fa8600 391 * @}
AnnaBridge 157:e7ca05fa8600 392 */
AnnaBridge 157:e7ca05fa8600 393
AnnaBridge 157:e7ca05fa8600 394 /**
AnnaBridge 157:e7ca05fa8600 395 * @}
AnnaBridge 157:e7ca05fa8600 396 */
AnnaBridge 157:e7ca05fa8600 397
AnnaBridge 157:e7ca05fa8600 398 /* Exported functions --------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 399 /** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
AnnaBridge 157:e7ca05fa8600 400 * @{
AnnaBridge 157:e7ca05fa8600 401 */
AnnaBridge 157:e7ca05fa8600 402
AnnaBridge 157:e7ca05fa8600 403 /** @defgroup LPUART_LL_EF_Configuration Configuration functions
AnnaBridge 157:e7ca05fa8600 404 * @{
AnnaBridge 157:e7ca05fa8600 405 */
AnnaBridge 157:e7ca05fa8600 406
AnnaBridge 157:e7ca05fa8600 407 /**
AnnaBridge 157:e7ca05fa8600 408 * @brief LPUART Enable
AnnaBridge 157:e7ca05fa8600 409 * @rmtoll CR1 UE LL_LPUART_Enable
AnnaBridge 157:e7ca05fa8600 410 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 411 * @retval None
AnnaBridge 157:e7ca05fa8600 412 */
AnnaBridge 157:e7ca05fa8600 413 __STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 414 {
AnnaBridge 157:e7ca05fa8600 415 SET_BIT(LPUARTx->CR1, USART_CR1_UE);
AnnaBridge 157:e7ca05fa8600 416 }
AnnaBridge 157:e7ca05fa8600 417
AnnaBridge 157:e7ca05fa8600 418 /**
AnnaBridge 157:e7ca05fa8600 419 * @brief LPUART Disable
AnnaBridge 157:e7ca05fa8600 420 * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
AnnaBridge 157:e7ca05fa8600 421 * and current operations are discarded. The configuration of the LPUART is kept, but all the status
AnnaBridge 157:e7ca05fa8600 422 * flags, in the LPUARTx_ISR are set to their default values.
AnnaBridge 157:e7ca05fa8600 423 * @note In order to go into low-power mode without generating errors on the line,
AnnaBridge 157:e7ca05fa8600 424 * the TE bit must be reset before and the software must wait
AnnaBridge 157:e7ca05fa8600 425 * for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
AnnaBridge 157:e7ca05fa8600 426 * The DMA requests are also reset when UE = 0 so the DMA channel must
AnnaBridge 157:e7ca05fa8600 427 * be disabled before resetting the UE bit.
AnnaBridge 157:e7ca05fa8600 428 * @rmtoll CR1 UE LL_LPUART_Disable
AnnaBridge 157:e7ca05fa8600 429 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 430 * @retval None
AnnaBridge 157:e7ca05fa8600 431 */
AnnaBridge 157:e7ca05fa8600 432 __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 433 {
AnnaBridge 157:e7ca05fa8600 434 CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
AnnaBridge 157:e7ca05fa8600 435 }
AnnaBridge 157:e7ca05fa8600 436
AnnaBridge 157:e7ca05fa8600 437 /**
AnnaBridge 157:e7ca05fa8600 438 * @brief Indicate if LPUART is enabled
AnnaBridge 157:e7ca05fa8600 439 * @rmtoll CR1 UE LL_LPUART_IsEnabled
AnnaBridge 157:e7ca05fa8600 440 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 441 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 442 */
AnnaBridge 157:e7ca05fa8600 443 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 444 {
AnnaBridge 157:e7ca05fa8600 445 return (READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
AnnaBridge 157:e7ca05fa8600 446 }
AnnaBridge 157:e7ca05fa8600 447
AnnaBridge 157:e7ca05fa8600 448 /**
AnnaBridge 157:e7ca05fa8600 449 * @brief LPUART enabled in STOP Mode
AnnaBridge 157:e7ca05fa8600 450 * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
AnnaBridge 157:e7ca05fa8600 451 * LPUART clock selection is HSI or LSE in RCC.
AnnaBridge 157:e7ca05fa8600 452 * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode
AnnaBridge 157:e7ca05fa8600 453 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 454 * @retval None
AnnaBridge 157:e7ca05fa8600 455 */
AnnaBridge 157:e7ca05fa8600 456 __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 457 {
AnnaBridge 157:e7ca05fa8600 458 SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
AnnaBridge 157:e7ca05fa8600 459 }
AnnaBridge 157:e7ca05fa8600 460
AnnaBridge 157:e7ca05fa8600 461 /**
AnnaBridge 157:e7ca05fa8600 462 * @brief LPUART disabled in STOP Mode
AnnaBridge 157:e7ca05fa8600 463 * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
AnnaBridge 157:e7ca05fa8600 464 * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode
AnnaBridge 157:e7ca05fa8600 465 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 466 * @retval None
AnnaBridge 157:e7ca05fa8600 467 */
AnnaBridge 157:e7ca05fa8600 468 __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 469 {
AnnaBridge 157:e7ca05fa8600 470 CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
AnnaBridge 157:e7ca05fa8600 471 }
AnnaBridge 157:e7ca05fa8600 472
AnnaBridge 157:e7ca05fa8600 473 /**
AnnaBridge 157:e7ca05fa8600 474 * @brief Indicate if LPUART is enabled in STOP Mode
AnnaBridge 157:e7ca05fa8600 475 * (able to wake up MCU from Stop mode or not)
AnnaBridge 157:e7ca05fa8600 476 * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode
AnnaBridge 157:e7ca05fa8600 477 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 478 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 479 */
AnnaBridge 157:e7ca05fa8600 480 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 481 {
AnnaBridge 157:e7ca05fa8600 482 return (READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM));
AnnaBridge 157:e7ca05fa8600 483 }
AnnaBridge 157:e7ca05fa8600 484
AnnaBridge 157:e7ca05fa8600 485 /**
AnnaBridge 157:e7ca05fa8600 486 * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
AnnaBridge 157:e7ca05fa8600 487 * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx
AnnaBridge 157:e7ca05fa8600 488 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 489 * @retval None
AnnaBridge 157:e7ca05fa8600 490 */
AnnaBridge 157:e7ca05fa8600 491 __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 492 {
AnnaBridge 157:e7ca05fa8600 493 SET_BIT(LPUARTx->CR1, USART_CR1_RE);
AnnaBridge 157:e7ca05fa8600 494 }
AnnaBridge 157:e7ca05fa8600 495
AnnaBridge 157:e7ca05fa8600 496 /**
AnnaBridge 157:e7ca05fa8600 497 * @brief Receiver Disable
AnnaBridge 157:e7ca05fa8600 498 * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx
AnnaBridge 157:e7ca05fa8600 499 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 500 * @retval None
AnnaBridge 157:e7ca05fa8600 501 */
AnnaBridge 157:e7ca05fa8600 502 __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 503 {
AnnaBridge 157:e7ca05fa8600 504 CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
AnnaBridge 157:e7ca05fa8600 505 }
AnnaBridge 157:e7ca05fa8600 506
AnnaBridge 157:e7ca05fa8600 507 /**
AnnaBridge 157:e7ca05fa8600 508 * @brief Transmitter Enable
AnnaBridge 157:e7ca05fa8600 509 * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx
AnnaBridge 157:e7ca05fa8600 510 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 511 * @retval None
AnnaBridge 157:e7ca05fa8600 512 */
AnnaBridge 157:e7ca05fa8600 513 __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 514 {
AnnaBridge 157:e7ca05fa8600 515 SET_BIT(LPUARTx->CR1, USART_CR1_TE);
AnnaBridge 157:e7ca05fa8600 516 }
AnnaBridge 157:e7ca05fa8600 517
AnnaBridge 157:e7ca05fa8600 518 /**
AnnaBridge 157:e7ca05fa8600 519 * @brief Transmitter Disable
AnnaBridge 157:e7ca05fa8600 520 * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx
AnnaBridge 157:e7ca05fa8600 521 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 522 * @retval None
AnnaBridge 157:e7ca05fa8600 523 */
AnnaBridge 157:e7ca05fa8600 524 __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 525 {
AnnaBridge 157:e7ca05fa8600 526 CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
AnnaBridge 157:e7ca05fa8600 527 }
AnnaBridge 157:e7ca05fa8600 528
AnnaBridge 157:e7ca05fa8600 529 /**
AnnaBridge 157:e7ca05fa8600 530 * @brief Configure simultaneously enabled/disabled states
AnnaBridge 157:e7ca05fa8600 531 * of Transmitter and Receiver
AnnaBridge 157:e7ca05fa8600 532 * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n
AnnaBridge 157:e7ca05fa8600 533 * CR1 TE LL_LPUART_SetTransferDirection
AnnaBridge 157:e7ca05fa8600 534 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 535 * @param TransferDirection This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 536 * @arg @ref LL_LPUART_DIRECTION_NONE
AnnaBridge 157:e7ca05fa8600 537 * @arg @ref LL_LPUART_DIRECTION_RX
AnnaBridge 157:e7ca05fa8600 538 * @arg @ref LL_LPUART_DIRECTION_TX
AnnaBridge 157:e7ca05fa8600 539 * @arg @ref LL_LPUART_DIRECTION_TX_RX
AnnaBridge 157:e7ca05fa8600 540 * @retval None
AnnaBridge 157:e7ca05fa8600 541 */
AnnaBridge 157:e7ca05fa8600 542 __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
AnnaBridge 157:e7ca05fa8600 543 {
AnnaBridge 157:e7ca05fa8600 544 MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
AnnaBridge 157:e7ca05fa8600 545 }
AnnaBridge 157:e7ca05fa8600 546
AnnaBridge 157:e7ca05fa8600 547 /**
AnnaBridge 157:e7ca05fa8600 548 * @brief Return enabled/disabled states of Transmitter and Receiver
AnnaBridge 157:e7ca05fa8600 549 * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n
AnnaBridge 157:e7ca05fa8600 550 * CR1 TE LL_LPUART_GetTransferDirection
AnnaBridge 157:e7ca05fa8600 551 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 552 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 553 * @arg @ref LL_LPUART_DIRECTION_NONE
AnnaBridge 157:e7ca05fa8600 554 * @arg @ref LL_LPUART_DIRECTION_RX
AnnaBridge 157:e7ca05fa8600 555 * @arg @ref LL_LPUART_DIRECTION_TX
AnnaBridge 157:e7ca05fa8600 556 * @arg @ref LL_LPUART_DIRECTION_TX_RX
AnnaBridge 157:e7ca05fa8600 557 */
AnnaBridge 157:e7ca05fa8600 558 __STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 559 {
AnnaBridge 157:e7ca05fa8600 560 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
AnnaBridge 157:e7ca05fa8600 561 }
AnnaBridge 157:e7ca05fa8600 562
AnnaBridge 157:e7ca05fa8600 563 /**
AnnaBridge 157:e7ca05fa8600 564 * @brief Configure Parity (enabled/disabled and parity mode if enabled)
AnnaBridge 157:e7ca05fa8600 565 * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
AnnaBridge 157:e7ca05fa8600 566 * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
AnnaBridge 157:e7ca05fa8600 567 * (depending on data width) and parity is checked on the received data.
AnnaBridge 157:e7ca05fa8600 568 * @rmtoll CR1 PS LL_LPUART_SetParity\n
AnnaBridge 157:e7ca05fa8600 569 * CR1 PCE LL_LPUART_SetParity
AnnaBridge 157:e7ca05fa8600 570 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 571 * @param Parity This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 572 * @arg @ref LL_LPUART_PARITY_NONE
AnnaBridge 157:e7ca05fa8600 573 * @arg @ref LL_LPUART_PARITY_EVEN
AnnaBridge 157:e7ca05fa8600 574 * @arg @ref LL_LPUART_PARITY_ODD
AnnaBridge 157:e7ca05fa8600 575 * @retval None
AnnaBridge 157:e7ca05fa8600 576 */
AnnaBridge 157:e7ca05fa8600 577 __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
AnnaBridge 157:e7ca05fa8600 578 {
AnnaBridge 157:e7ca05fa8600 579 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
AnnaBridge 157:e7ca05fa8600 580 }
AnnaBridge 157:e7ca05fa8600 581
AnnaBridge 157:e7ca05fa8600 582 /**
AnnaBridge 157:e7ca05fa8600 583 * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
AnnaBridge 157:e7ca05fa8600 584 * @rmtoll CR1 PS LL_LPUART_GetParity\n
AnnaBridge 157:e7ca05fa8600 585 * CR1 PCE LL_LPUART_GetParity
AnnaBridge 157:e7ca05fa8600 586 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 587 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 588 * @arg @ref LL_LPUART_PARITY_NONE
AnnaBridge 157:e7ca05fa8600 589 * @arg @ref LL_LPUART_PARITY_EVEN
AnnaBridge 157:e7ca05fa8600 590 * @arg @ref LL_LPUART_PARITY_ODD
AnnaBridge 157:e7ca05fa8600 591 */
AnnaBridge 157:e7ca05fa8600 592 __STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 593 {
AnnaBridge 157:e7ca05fa8600 594 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
AnnaBridge 157:e7ca05fa8600 595 }
AnnaBridge 157:e7ca05fa8600 596
AnnaBridge 157:e7ca05fa8600 597 /**
AnnaBridge 157:e7ca05fa8600 598 * @brief Set Receiver Wake Up method from Mute mode.
AnnaBridge 157:e7ca05fa8600 599 * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod
AnnaBridge 157:e7ca05fa8600 600 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 601 * @param Method This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 602 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
AnnaBridge 157:e7ca05fa8600 603 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
AnnaBridge 157:e7ca05fa8600 604 * @retval None
AnnaBridge 157:e7ca05fa8600 605 */
AnnaBridge 157:e7ca05fa8600 606 __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
AnnaBridge 157:e7ca05fa8600 607 {
AnnaBridge 157:e7ca05fa8600 608 MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
AnnaBridge 157:e7ca05fa8600 609 }
AnnaBridge 157:e7ca05fa8600 610
AnnaBridge 157:e7ca05fa8600 611 /**
AnnaBridge 157:e7ca05fa8600 612 * @brief Return Receiver Wake Up method from Mute mode
AnnaBridge 157:e7ca05fa8600 613 * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod
AnnaBridge 157:e7ca05fa8600 614 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 615 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 616 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
AnnaBridge 157:e7ca05fa8600 617 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
AnnaBridge 157:e7ca05fa8600 618 */
AnnaBridge 157:e7ca05fa8600 619 __STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 620 {
AnnaBridge 157:e7ca05fa8600 621 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
AnnaBridge 157:e7ca05fa8600 622 }
AnnaBridge 157:e7ca05fa8600 623
AnnaBridge 157:e7ca05fa8600 624 /**
AnnaBridge 157:e7ca05fa8600 625 * @brief Set Word length (nb of data bits, excluding start and stop bits)
AnnaBridge 157:e7ca05fa8600 626 * @rmtoll CR1 M LL_LPUART_SetDataWidth
AnnaBridge 157:e7ca05fa8600 627 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 628 * @param DataWidth This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 629 * @arg @ref LL_LPUART_DATAWIDTH_7B
AnnaBridge 157:e7ca05fa8600 630 * @arg @ref LL_LPUART_DATAWIDTH_8B
AnnaBridge 157:e7ca05fa8600 631 * @arg @ref LL_LPUART_DATAWIDTH_9B
AnnaBridge 157:e7ca05fa8600 632 * @retval None
AnnaBridge 157:e7ca05fa8600 633 */
AnnaBridge 157:e7ca05fa8600 634 __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
AnnaBridge 157:e7ca05fa8600 635 {
AnnaBridge 157:e7ca05fa8600 636 MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
AnnaBridge 157:e7ca05fa8600 637 }
AnnaBridge 157:e7ca05fa8600 638
AnnaBridge 157:e7ca05fa8600 639 /**
AnnaBridge 157:e7ca05fa8600 640 * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
AnnaBridge 157:e7ca05fa8600 641 * @rmtoll CR1 M LL_LPUART_GetDataWidth
AnnaBridge 157:e7ca05fa8600 642 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 643 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 644 * @arg @ref LL_LPUART_DATAWIDTH_7B
AnnaBridge 157:e7ca05fa8600 645 * @arg @ref LL_LPUART_DATAWIDTH_8B
AnnaBridge 157:e7ca05fa8600 646 * @arg @ref LL_LPUART_DATAWIDTH_9B
AnnaBridge 157:e7ca05fa8600 647 */
AnnaBridge 157:e7ca05fa8600 648 __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 649 {
AnnaBridge 157:e7ca05fa8600 650 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
AnnaBridge 157:e7ca05fa8600 651 }
AnnaBridge 157:e7ca05fa8600 652
AnnaBridge 157:e7ca05fa8600 653 /**
AnnaBridge 157:e7ca05fa8600 654 * @brief Allow switch between Mute Mode and Active mode
AnnaBridge 157:e7ca05fa8600 655 * @rmtoll CR1 MME LL_LPUART_EnableMuteMode
AnnaBridge 157:e7ca05fa8600 656 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 657 * @retval None
AnnaBridge 157:e7ca05fa8600 658 */
AnnaBridge 157:e7ca05fa8600 659 __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 660 {
AnnaBridge 157:e7ca05fa8600 661 SET_BIT(LPUARTx->CR1, USART_CR1_MME);
AnnaBridge 157:e7ca05fa8600 662 }
AnnaBridge 157:e7ca05fa8600 663
AnnaBridge 157:e7ca05fa8600 664 /**
AnnaBridge 157:e7ca05fa8600 665 * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
AnnaBridge 157:e7ca05fa8600 666 * @rmtoll CR1 MME LL_LPUART_DisableMuteMode
AnnaBridge 157:e7ca05fa8600 667 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 668 * @retval None
AnnaBridge 157:e7ca05fa8600 669 */
AnnaBridge 157:e7ca05fa8600 670 __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 671 {
AnnaBridge 157:e7ca05fa8600 672 CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
AnnaBridge 157:e7ca05fa8600 673 }
AnnaBridge 157:e7ca05fa8600 674
AnnaBridge 157:e7ca05fa8600 675 /**
AnnaBridge 157:e7ca05fa8600 676 * @brief Indicate if switch between Mute Mode and Active mode is allowed
AnnaBridge 157:e7ca05fa8600 677 * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode
AnnaBridge 157:e7ca05fa8600 678 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 679 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 680 */
AnnaBridge 157:e7ca05fa8600 681 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 682 {
AnnaBridge 157:e7ca05fa8600 683 return (READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME));
AnnaBridge 157:e7ca05fa8600 684 }
AnnaBridge 157:e7ca05fa8600 685
AnnaBridge 157:e7ca05fa8600 686 /**
AnnaBridge 157:e7ca05fa8600 687 * @brief Set the length of the stop bits
AnnaBridge 157:e7ca05fa8600 688 * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength
AnnaBridge 157:e7ca05fa8600 689 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 690 * @param StopBits This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 691 * @arg @ref LL_LPUART_STOPBITS_1
AnnaBridge 157:e7ca05fa8600 692 * @arg @ref LL_LPUART_STOPBITS_2
AnnaBridge 157:e7ca05fa8600 693 * @retval None
AnnaBridge 157:e7ca05fa8600 694 */
AnnaBridge 157:e7ca05fa8600 695 __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
AnnaBridge 157:e7ca05fa8600 696 {
AnnaBridge 157:e7ca05fa8600 697 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
AnnaBridge 157:e7ca05fa8600 698 }
AnnaBridge 157:e7ca05fa8600 699
AnnaBridge 157:e7ca05fa8600 700 /**
AnnaBridge 157:e7ca05fa8600 701 * @brief Retrieve the length of the stop bits
AnnaBridge 157:e7ca05fa8600 702 * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength
AnnaBridge 157:e7ca05fa8600 703 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 704 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 705 * @arg @ref LL_LPUART_STOPBITS_1
AnnaBridge 157:e7ca05fa8600 706 * @arg @ref LL_LPUART_STOPBITS_2
AnnaBridge 157:e7ca05fa8600 707 */
AnnaBridge 157:e7ca05fa8600 708 __STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 709 {
AnnaBridge 157:e7ca05fa8600 710 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
AnnaBridge 157:e7ca05fa8600 711 }
AnnaBridge 157:e7ca05fa8600 712
AnnaBridge 157:e7ca05fa8600 713 /**
AnnaBridge 157:e7ca05fa8600 714 * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
AnnaBridge 157:e7ca05fa8600 715 * @note Call of this function is equivalent to following function call sequence :
AnnaBridge 157:e7ca05fa8600 716 * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
AnnaBridge 157:e7ca05fa8600 717 * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
AnnaBridge 157:e7ca05fa8600 718 * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
AnnaBridge 157:e7ca05fa8600 719 * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n
AnnaBridge 157:e7ca05fa8600 720 * CR1 PCE LL_LPUART_ConfigCharacter\n
AnnaBridge 157:e7ca05fa8600 721 * CR1 M LL_LPUART_ConfigCharacter\n
AnnaBridge 157:e7ca05fa8600 722 * CR2 STOP LL_LPUART_ConfigCharacter
AnnaBridge 157:e7ca05fa8600 723 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 724 * @param DataWidth This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 725 * @arg @ref LL_LPUART_DATAWIDTH_7B
AnnaBridge 157:e7ca05fa8600 726 * @arg @ref LL_LPUART_DATAWIDTH_8B
AnnaBridge 157:e7ca05fa8600 727 * @arg @ref LL_LPUART_DATAWIDTH_9B
AnnaBridge 157:e7ca05fa8600 728 * @param Parity This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 729 * @arg @ref LL_LPUART_PARITY_NONE
AnnaBridge 157:e7ca05fa8600 730 * @arg @ref LL_LPUART_PARITY_EVEN
AnnaBridge 157:e7ca05fa8600 731 * @arg @ref LL_LPUART_PARITY_ODD
AnnaBridge 157:e7ca05fa8600 732 * @param StopBits This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 733 * @arg @ref LL_LPUART_STOPBITS_1
AnnaBridge 157:e7ca05fa8600 734 * @arg @ref LL_LPUART_STOPBITS_2
AnnaBridge 157:e7ca05fa8600 735 * @retval None
AnnaBridge 157:e7ca05fa8600 736 */
AnnaBridge 157:e7ca05fa8600 737 __STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
AnnaBridge 157:e7ca05fa8600 738 uint32_t StopBits)
AnnaBridge 157:e7ca05fa8600 739 {
AnnaBridge 157:e7ca05fa8600 740 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
AnnaBridge 157:e7ca05fa8600 741 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
AnnaBridge 157:e7ca05fa8600 742 }
AnnaBridge 157:e7ca05fa8600 743
AnnaBridge 157:e7ca05fa8600 744 /**
AnnaBridge 157:e7ca05fa8600 745 * @brief Configure TX/RX pins swapping setting.
AnnaBridge 157:e7ca05fa8600 746 * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap
AnnaBridge 157:e7ca05fa8600 747 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 748 * @param SwapConfig This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 749 * @arg @ref LL_LPUART_TXRX_STANDARD
AnnaBridge 157:e7ca05fa8600 750 * @arg @ref LL_LPUART_TXRX_SWAPPED
AnnaBridge 157:e7ca05fa8600 751 * @retval None
AnnaBridge 157:e7ca05fa8600 752 */
AnnaBridge 157:e7ca05fa8600 753 __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
AnnaBridge 157:e7ca05fa8600 754 {
AnnaBridge 157:e7ca05fa8600 755 MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
AnnaBridge 157:e7ca05fa8600 756 }
AnnaBridge 157:e7ca05fa8600 757
AnnaBridge 157:e7ca05fa8600 758 /**
AnnaBridge 157:e7ca05fa8600 759 * @brief Retrieve TX/RX pins swapping configuration.
AnnaBridge 157:e7ca05fa8600 760 * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap
AnnaBridge 157:e7ca05fa8600 761 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 762 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 763 * @arg @ref LL_LPUART_TXRX_STANDARD
AnnaBridge 157:e7ca05fa8600 764 * @arg @ref LL_LPUART_TXRX_SWAPPED
AnnaBridge 157:e7ca05fa8600 765 */
AnnaBridge 157:e7ca05fa8600 766 __STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 767 {
AnnaBridge 157:e7ca05fa8600 768 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
AnnaBridge 157:e7ca05fa8600 769 }
AnnaBridge 157:e7ca05fa8600 770
AnnaBridge 157:e7ca05fa8600 771 /**
AnnaBridge 157:e7ca05fa8600 772 * @brief Configure RX pin active level logic
AnnaBridge 157:e7ca05fa8600 773 * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel
AnnaBridge 157:e7ca05fa8600 774 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 775 * @param PinInvMethod This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 776 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
AnnaBridge 157:e7ca05fa8600 777 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
AnnaBridge 157:e7ca05fa8600 778 * @retval None
AnnaBridge 157:e7ca05fa8600 779 */
AnnaBridge 157:e7ca05fa8600 780 __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
AnnaBridge 157:e7ca05fa8600 781 {
AnnaBridge 157:e7ca05fa8600 782 MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
AnnaBridge 157:e7ca05fa8600 783 }
AnnaBridge 157:e7ca05fa8600 784
AnnaBridge 157:e7ca05fa8600 785 /**
AnnaBridge 157:e7ca05fa8600 786 * @brief Retrieve RX pin active level logic configuration
AnnaBridge 157:e7ca05fa8600 787 * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel
AnnaBridge 157:e7ca05fa8600 788 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 789 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 790 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
AnnaBridge 157:e7ca05fa8600 791 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
AnnaBridge 157:e7ca05fa8600 792 */
AnnaBridge 157:e7ca05fa8600 793 __STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 794 {
AnnaBridge 157:e7ca05fa8600 795 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
AnnaBridge 157:e7ca05fa8600 796 }
AnnaBridge 157:e7ca05fa8600 797
AnnaBridge 157:e7ca05fa8600 798 /**
AnnaBridge 157:e7ca05fa8600 799 * @brief Configure TX pin active level logic
AnnaBridge 157:e7ca05fa8600 800 * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel
AnnaBridge 157:e7ca05fa8600 801 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 802 * @param PinInvMethod This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 803 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
AnnaBridge 157:e7ca05fa8600 804 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
AnnaBridge 157:e7ca05fa8600 805 * @retval None
AnnaBridge 157:e7ca05fa8600 806 */
AnnaBridge 157:e7ca05fa8600 807 __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
AnnaBridge 157:e7ca05fa8600 808 {
AnnaBridge 157:e7ca05fa8600 809 MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
AnnaBridge 157:e7ca05fa8600 810 }
AnnaBridge 157:e7ca05fa8600 811
AnnaBridge 157:e7ca05fa8600 812 /**
AnnaBridge 157:e7ca05fa8600 813 * @brief Retrieve TX pin active level logic configuration
AnnaBridge 157:e7ca05fa8600 814 * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel
AnnaBridge 157:e7ca05fa8600 815 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 816 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 817 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
AnnaBridge 157:e7ca05fa8600 818 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
AnnaBridge 157:e7ca05fa8600 819 */
AnnaBridge 157:e7ca05fa8600 820 __STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 821 {
AnnaBridge 157:e7ca05fa8600 822 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
AnnaBridge 157:e7ca05fa8600 823 }
AnnaBridge 157:e7ca05fa8600 824
AnnaBridge 157:e7ca05fa8600 825 /**
AnnaBridge 157:e7ca05fa8600 826 * @brief Configure Binary data logic.
AnnaBridge 157:e7ca05fa8600 827 *
AnnaBridge 157:e7ca05fa8600 828 * @note Allow to define how Logical data from the data register are send/received :
AnnaBridge 157:e7ca05fa8600 829 * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
AnnaBridge 157:e7ca05fa8600 830 * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic
AnnaBridge 157:e7ca05fa8600 831 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 832 * @param DataLogic This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 833 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
AnnaBridge 157:e7ca05fa8600 834 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
AnnaBridge 157:e7ca05fa8600 835 * @retval None
AnnaBridge 157:e7ca05fa8600 836 */
AnnaBridge 157:e7ca05fa8600 837 __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
AnnaBridge 157:e7ca05fa8600 838 {
AnnaBridge 157:e7ca05fa8600 839 MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
AnnaBridge 157:e7ca05fa8600 840 }
AnnaBridge 157:e7ca05fa8600 841
AnnaBridge 157:e7ca05fa8600 842 /**
AnnaBridge 157:e7ca05fa8600 843 * @brief Retrieve Binary data configuration
AnnaBridge 157:e7ca05fa8600 844 * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic
AnnaBridge 157:e7ca05fa8600 845 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 846 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 847 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
AnnaBridge 157:e7ca05fa8600 848 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
AnnaBridge 157:e7ca05fa8600 849 */
AnnaBridge 157:e7ca05fa8600 850 __STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 851 {
AnnaBridge 157:e7ca05fa8600 852 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
AnnaBridge 157:e7ca05fa8600 853 }
AnnaBridge 157:e7ca05fa8600 854
AnnaBridge 157:e7ca05fa8600 855 /**
AnnaBridge 157:e7ca05fa8600 856 * @brief Configure transfer bit order (either Less or Most Significant Bit First)
AnnaBridge 157:e7ca05fa8600 857 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
AnnaBridge 157:e7ca05fa8600 858 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
AnnaBridge 157:e7ca05fa8600 859 * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
AnnaBridge 157:e7ca05fa8600 860 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 861 * @param BitOrder This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 862 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
AnnaBridge 157:e7ca05fa8600 863 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
AnnaBridge 157:e7ca05fa8600 864 * @retval None
AnnaBridge 157:e7ca05fa8600 865 */
AnnaBridge 157:e7ca05fa8600 866 __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
AnnaBridge 157:e7ca05fa8600 867 {
AnnaBridge 157:e7ca05fa8600 868 MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
AnnaBridge 157:e7ca05fa8600 869 }
AnnaBridge 157:e7ca05fa8600 870
AnnaBridge 157:e7ca05fa8600 871 /**
AnnaBridge 157:e7ca05fa8600 872 * @brief Return transfer bit order (either Less or Most Significant Bit First)
AnnaBridge 157:e7ca05fa8600 873 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
AnnaBridge 157:e7ca05fa8600 874 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
AnnaBridge 157:e7ca05fa8600 875 * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
AnnaBridge 157:e7ca05fa8600 876 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 877 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 878 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
AnnaBridge 157:e7ca05fa8600 879 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
AnnaBridge 157:e7ca05fa8600 880 */
AnnaBridge 157:e7ca05fa8600 881 __STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 882 {
AnnaBridge 157:e7ca05fa8600 883 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
AnnaBridge 157:e7ca05fa8600 884 }
AnnaBridge 157:e7ca05fa8600 885
AnnaBridge 157:e7ca05fa8600 886 /**
AnnaBridge 157:e7ca05fa8600 887 * @brief Set Address of the LPUART node.
AnnaBridge 157:e7ca05fa8600 888 * @note This is used in multiprocessor communication during Mute mode or Stop mode,
AnnaBridge 157:e7ca05fa8600 889 * for wake up with address mark detection.
AnnaBridge 157:e7ca05fa8600 890 * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
AnnaBridge 157:e7ca05fa8600 891 * (b7-b4 should be set to 0)
AnnaBridge 157:e7ca05fa8600 892 * 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
AnnaBridge 157:e7ca05fa8600 893 * (This is used in multiprocessor communication during Mute mode or Stop mode,
AnnaBridge 157:e7ca05fa8600 894 * for wake up with 7-bit address mark detection.
AnnaBridge 157:e7ca05fa8600 895 * The MSB of the character sent by the transmitter should be equal to 1.
AnnaBridge 157:e7ca05fa8600 896 * It may also be used for character detection during normal reception,
AnnaBridge 157:e7ca05fa8600 897 * Mute mode inactive (for example, end of block detection in ModBus protocol).
AnnaBridge 157:e7ca05fa8600 898 * In this case, the whole received character (8-bit) is compared to the ADD[7:0]
AnnaBridge 157:e7ca05fa8600 899 * value and CMF flag is set on match)
AnnaBridge 157:e7ca05fa8600 900 * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n
AnnaBridge 157:e7ca05fa8600 901 * CR2 ADDM7 LL_LPUART_ConfigNodeAddress
AnnaBridge 157:e7ca05fa8600 902 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 903 * @param AddressLen This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 904 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
AnnaBridge 157:e7ca05fa8600 905 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
AnnaBridge 157:e7ca05fa8600 906 * @param NodeAddress 4 or 7 bit Address of the LPUART node.
AnnaBridge 157:e7ca05fa8600 907 * @retval None
AnnaBridge 157:e7ca05fa8600 908 */
AnnaBridge 157:e7ca05fa8600 909 __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
AnnaBridge 157:e7ca05fa8600 910 {
AnnaBridge 157:e7ca05fa8600 911 MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
AnnaBridge 157:e7ca05fa8600 912 (uint32_t)(AddressLen | (NodeAddress << LPUART_POSITION_CR2_ADD)));
AnnaBridge 157:e7ca05fa8600 913 }
AnnaBridge 157:e7ca05fa8600 914
AnnaBridge 157:e7ca05fa8600 915 /**
AnnaBridge 157:e7ca05fa8600 916 * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2.
AnnaBridge 157:e7ca05fa8600 917 * @note If 4-bit Address Detection is selected in ADDM7,
AnnaBridge 157:e7ca05fa8600 918 * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
AnnaBridge 157:e7ca05fa8600 919 * If 7-bit Address Detection is selected in ADDM7,
AnnaBridge 157:e7ca05fa8600 920 * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
AnnaBridge 157:e7ca05fa8600 921 * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress
AnnaBridge 157:e7ca05fa8600 922 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 923 * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
AnnaBridge 157:e7ca05fa8600 924 */
AnnaBridge 157:e7ca05fa8600 925 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 926 {
AnnaBridge 157:e7ca05fa8600 927 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> LPUART_POSITION_CR2_ADD);
AnnaBridge 157:e7ca05fa8600 928 }
AnnaBridge 157:e7ca05fa8600 929
AnnaBridge 157:e7ca05fa8600 930 /**
AnnaBridge 157:e7ca05fa8600 931 * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
AnnaBridge 157:e7ca05fa8600 932 * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen
AnnaBridge 157:e7ca05fa8600 933 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 934 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 935 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
AnnaBridge 157:e7ca05fa8600 936 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
AnnaBridge 157:e7ca05fa8600 937 */
AnnaBridge 157:e7ca05fa8600 938 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 939 {
AnnaBridge 157:e7ca05fa8600 940 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
AnnaBridge 157:e7ca05fa8600 941 }
AnnaBridge 157:e7ca05fa8600 942
AnnaBridge 157:e7ca05fa8600 943 /**
AnnaBridge 157:e7ca05fa8600 944 * @brief Enable RTS HW Flow Control
AnnaBridge 157:e7ca05fa8600 945 * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
AnnaBridge 157:e7ca05fa8600 946 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 947 * @retval None
AnnaBridge 157:e7ca05fa8600 948 */
AnnaBridge 157:e7ca05fa8600 949 __STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 950 {
AnnaBridge 157:e7ca05fa8600 951 SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
AnnaBridge 157:e7ca05fa8600 952 }
AnnaBridge 157:e7ca05fa8600 953
AnnaBridge 157:e7ca05fa8600 954 /**
AnnaBridge 157:e7ca05fa8600 955 * @brief Disable RTS HW Flow Control
AnnaBridge 157:e7ca05fa8600 956 * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
AnnaBridge 157:e7ca05fa8600 957 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 958 * @retval None
AnnaBridge 157:e7ca05fa8600 959 */
AnnaBridge 157:e7ca05fa8600 960 __STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 961 {
AnnaBridge 157:e7ca05fa8600 962 CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
AnnaBridge 157:e7ca05fa8600 963 }
AnnaBridge 157:e7ca05fa8600 964
AnnaBridge 157:e7ca05fa8600 965 /**
AnnaBridge 157:e7ca05fa8600 966 * @brief Enable CTS HW Flow Control
AnnaBridge 157:e7ca05fa8600 967 * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
AnnaBridge 157:e7ca05fa8600 968 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 969 * @retval None
AnnaBridge 157:e7ca05fa8600 970 */
AnnaBridge 157:e7ca05fa8600 971 __STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 972 {
AnnaBridge 157:e7ca05fa8600 973 SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
AnnaBridge 157:e7ca05fa8600 974 }
AnnaBridge 157:e7ca05fa8600 975
AnnaBridge 157:e7ca05fa8600 976 /**
AnnaBridge 157:e7ca05fa8600 977 * @brief Disable CTS HW Flow Control
AnnaBridge 157:e7ca05fa8600 978 * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
AnnaBridge 157:e7ca05fa8600 979 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 980 * @retval None
AnnaBridge 157:e7ca05fa8600 981 */
AnnaBridge 157:e7ca05fa8600 982 __STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 983 {
AnnaBridge 157:e7ca05fa8600 984 CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
AnnaBridge 157:e7ca05fa8600 985 }
AnnaBridge 157:e7ca05fa8600 986
AnnaBridge 157:e7ca05fa8600 987 /**
AnnaBridge 157:e7ca05fa8600 988 * @brief Configure HW Flow Control mode (both CTS and RTS)
AnnaBridge 157:e7ca05fa8600 989 * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n
AnnaBridge 157:e7ca05fa8600 990 * CR3 CTSE LL_LPUART_SetHWFlowCtrl
AnnaBridge 157:e7ca05fa8600 991 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 992 * @param HardwareFlowControl This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 993 * @arg @ref LL_LPUART_HWCONTROL_NONE
AnnaBridge 157:e7ca05fa8600 994 * @arg @ref LL_LPUART_HWCONTROL_RTS
AnnaBridge 157:e7ca05fa8600 995 * @arg @ref LL_LPUART_HWCONTROL_CTS
AnnaBridge 157:e7ca05fa8600 996 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
AnnaBridge 157:e7ca05fa8600 997 * @retval None
AnnaBridge 157:e7ca05fa8600 998 */
AnnaBridge 157:e7ca05fa8600 999 __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
AnnaBridge 157:e7ca05fa8600 1000 {
AnnaBridge 157:e7ca05fa8600 1001 MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
AnnaBridge 157:e7ca05fa8600 1002 }
AnnaBridge 157:e7ca05fa8600 1003
AnnaBridge 157:e7ca05fa8600 1004 /**
AnnaBridge 157:e7ca05fa8600 1005 * @brief Return HW Flow Control configuration (both CTS and RTS)
AnnaBridge 157:e7ca05fa8600 1006 * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n
AnnaBridge 157:e7ca05fa8600 1007 * CR3 CTSE LL_LPUART_GetHWFlowCtrl
AnnaBridge 157:e7ca05fa8600 1008 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1009 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 1010 * @arg @ref LL_LPUART_HWCONTROL_NONE
AnnaBridge 157:e7ca05fa8600 1011 * @arg @ref LL_LPUART_HWCONTROL_RTS
AnnaBridge 157:e7ca05fa8600 1012 * @arg @ref LL_LPUART_HWCONTROL_CTS
AnnaBridge 157:e7ca05fa8600 1013 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
AnnaBridge 157:e7ca05fa8600 1014 */
AnnaBridge 157:e7ca05fa8600 1015 __STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1016 {
AnnaBridge 157:e7ca05fa8600 1017 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
AnnaBridge 157:e7ca05fa8600 1018 }
AnnaBridge 157:e7ca05fa8600 1019
AnnaBridge 157:e7ca05fa8600 1020 /**
AnnaBridge 157:e7ca05fa8600 1021 * @brief Enable Overrun detection
AnnaBridge 157:e7ca05fa8600 1022 * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect
AnnaBridge 157:e7ca05fa8600 1023 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1024 * @retval None
AnnaBridge 157:e7ca05fa8600 1025 */
AnnaBridge 157:e7ca05fa8600 1026 __STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1027 {
AnnaBridge 157:e7ca05fa8600 1028 CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
AnnaBridge 157:e7ca05fa8600 1029 }
AnnaBridge 157:e7ca05fa8600 1030
AnnaBridge 157:e7ca05fa8600 1031 /**
AnnaBridge 157:e7ca05fa8600 1032 * @brief Disable Overrun detection
AnnaBridge 157:e7ca05fa8600 1033 * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect
AnnaBridge 157:e7ca05fa8600 1034 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1035 * @retval None
AnnaBridge 157:e7ca05fa8600 1036 */
AnnaBridge 157:e7ca05fa8600 1037 __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1038 {
AnnaBridge 157:e7ca05fa8600 1039 SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
AnnaBridge 157:e7ca05fa8600 1040 }
AnnaBridge 157:e7ca05fa8600 1041
AnnaBridge 157:e7ca05fa8600 1042 /**
AnnaBridge 157:e7ca05fa8600 1043 * @brief Indicate if Overrun detection is enabled
AnnaBridge 157:e7ca05fa8600 1044 * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
AnnaBridge 157:e7ca05fa8600 1045 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1046 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1047 */
AnnaBridge 157:e7ca05fa8600 1048 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1049 {
AnnaBridge 157:e7ca05fa8600 1050 return (READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS);
AnnaBridge 157:e7ca05fa8600 1051 }
AnnaBridge 157:e7ca05fa8600 1052
AnnaBridge 157:e7ca05fa8600 1053 /**
AnnaBridge 157:e7ca05fa8600 1054 * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
AnnaBridge 157:e7ca05fa8600 1055 * @rmtoll CR3 WUS LL_LPUART_SetWKUPType
AnnaBridge 157:e7ca05fa8600 1056 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1057 * @param Type This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 1058 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
AnnaBridge 157:e7ca05fa8600 1059 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
AnnaBridge 157:e7ca05fa8600 1060 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
AnnaBridge 157:e7ca05fa8600 1061 * @retval None
AnnaBridge 157:e7ca05fa8600 1062 */
AnnaBridge 157:e7ca05fa8600 1063 __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
AnnaBridge 157:e7ca05fa8600 1064 {
AnnaBridge 157:e7ca05fa8600 1065 MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
AnnaBridge 157:e7ca05fa8600 1066 }
AnnaBridge 157:e7ca05fa8600 1067
AnnaBridge 157:e7ca05fa8600 1068 /**
AnnaBridge 157:e7ca05fa8600 1069 * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
AnnaBridge 157:e7ca05fa8600 1070 * @rmtoll CR3 WUS LL_LPUART_GetWKUPType
AnnaBridge 157:e7ca05fa8600 1071 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1072 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 1073 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
AnnaBridge 157:e7ca05fa8600 1074 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
AnnaBridge 157:e7ca05fa8600 1075 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
AnnaBridge 157:e7ca05fa8600 1076 */
AnnaBridge 157:e7ca05fa8600 1077 __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1078 {
AnnaBridge 157:e7ca05fa8600 1079 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
AnnaBridge 157:e7ca05fa8600 1080 }
AnnaBridge 157:e7ca05fa8600 1081
AnnaBridge 157:e7ca05fa8600 1082 /**
AnnaBridge 157:e7ca05fa8600 1083 * @brief Configure LPUART BRR register for achieving expected Baud Rate value.
AnnaBridge 157:e7ca05fa8600 1084 *
AnnaBridge 157:e7ca05fa8600 1085 * @note Compute and set LPUARTDIV value in BRR Register (full BRR content)
AnnaBridge 157:e7ca05fa8600 1086 * according to used Peripheral Clock and expected Baud Rate values
AnnaBridge 157:e7ca05fa8600 1087 * @note Peripheral clock and Baud Rate values provided as function parameters should be valid
AnnaBridge 157:e7ca05fa8600 1088 * (Baud rate value != 0).
AnnaBridge 157:e7ca05fa8600 1089 * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
AnnaBridge 157:e7ca05fa8600 1090 * a care should be taken when generating high baud rates using high PeriphClk
AnnaBridge 157:e7ca05fa8600 1091 * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
AnnaBridge 157:e7ca05fa8600 1092 * @rmtoll BRR BRR LL_LPUART_SetBaudRate
AnnaBridge 157:e7ca05fa8600 1093 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1094 * @param PeriphClk Peripheral Clock
AnnaBridge 157:e7ca05fa8600 1095 * @param BaudRate Baud Rate
AnnaBridge 157:e7ca05fa8600 1096 * @retval None
AnnaBridge 157:e7ca05fa8600 1097 */
AnnaBridge 157:e7ca05fa8600 1098 __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t BaudRate)
AnnaBridge 157:e7ca05fa8600 1099 {
AnnaBridge 157:e7ca05fa8600 1100 LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate);
AnnaBridge 157:e7ca05fa8600 1101 }
AnnaBridge 157:e7ca05fa8600 1102
AnnaBridge 157:e7ca05fa8600 1103 /**
AnnaBridge 157:e7ca05fa8600 1104 * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register
AnnaBridge 157:e7ca05fa8600 1105 * (full BRR content), and to used Peripheral Clock values
AnnaBridge 157:e7ca05fa8600 1106 * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
AnnaBridge 157:e7ca05fa8600 1107 * @rmtoll BRR BRR LL_LPUART_GetBaudRate
AnnaBridge 157:e7ca05fa8600 1108 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1109 * @param PeriphClk Peripheral Clock
AnnaBridge 157:e7ca05fa8600 1110 * @retval Baud Rate
AnnaBridge 157:e7ca05fa8600 1111 */
AnnaBridge 157:e7ca05fa8600 1112 __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk)
AnnaBridge 157:e7ca05fa8600 1113 {
AnnaBridge 157:e7ca05fa8600 1114 register uint32_t lpuartdiv = 0x0U;
AnnaBridge 157:e7ca05fa8600 1115 register uint32_t brrresult = 0x0U;
AnnaBridge 157:e7ca05fa8600 1116
AnnaBridge 157:e7ca05fa8600 1117 lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
AnnaBridge 157:e7ca05fa8600 1118
AnnaBridge 157:e7ca05fa8600 1119 if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
AnnaBridge 157:e7ca05fa8600 1120 {
AnnaBridge 157:e7ca05fa8600 1121 brrresult = (uint32_t)(((uint64_t)(PeriphClk) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
AnnaBridge 157:e7ca05fa8600 1122 }
AnnaBridge 157:e7ca05fa8600 1123
AnnaBridge 157:e7ca05fa8600 1124 return (brrresult);
AnnaBridge 157:e7ca05fa8600 1125 }
AnnaBridge 157:e7ca05fa8600 1126
AnnaBridge 157:e7ca05fa8600 1127 /**
AnnaBridge 157:e7ca05fa8600 1128 * @}
AnnaBridge 157:e7ca05fa8600 1129 */
AnnaBridge 157:e7ca05fa8600 1130
AnnaBridge 157:e7ca05fa8600 1131 /** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
AnnaBridge 157:e7ca05fa8600 1132 * @{
AnnaBridge 157:e7ca05fa8600 1133 */
AnnaBridge 157:e7ca05fa8600 1134
AnnaBridge 157:e7ca05fa8600 1135 /**
AnnaBridge 157:e7ca05fa8600 1136 * @brief Enable Single Wire Half-Duplex mode
AnnaBridge 157:e7ca05fa8600 1137 * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex
AnnaBridge 157:e7ca05fa8600 1138 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1139 * @retval None
AnnaBridge 157:e7ca05fa8600 1140 */
AnnaBridge 157:e7ca05fa8600 1141 __STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1142 {
AnnaBridge 157:e7ca05fa8600 1143 SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
AnnaBridge 157:e7ca05fa8600 1144 }
AnnaBridge 157:e7ca05fa8600 1145
AnnaBridge 157:e7ca05fa8600 1146 /**
AnnaBridge 157:e7ca05fa8600 1147 * @brief Disable Single Wire Half-Duplex mode
AnnaBridge 157:e7ca05fa8600 1148 * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex
AnnaBridge 157:e7ca05fa8600 1149 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1150 * @retval None
AnnaBridge 157:e7ca05fa8600 1151 */
AnnaBridge 157:e7ca05fa8600 1152 __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1153 {
AnnaBridge 157:e7ca05fa8600 1154 CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
AnnaBridge 157:e7ca05fa8600 1155 }
AnnaBridge 157:e7ca05fa8600 1156
AnnaBridge 157:e7ca05fa8600 1157 /**
AnnaBridge 157:e7ca05fa8600 1158 * @brief Indicate if Single Wire Half-Duplex mode is enabled
AnnaBridge 157:e7ca05fa8600 1159 * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
AnnaBridge 157:e7ca05fa8600 1160 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1161 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1162 */
AnnaBridge 157:e7ca05fa8600 1163 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1164 {
AnnaBridge 157:e7ca05fa8600 1165 return (READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
AnnaBridge 157:e7ca05fa8600 1166 }
AnnaBridge 157:e7ca05fa8600 1167
AnnaBridge 157:e7ca05fa8600 1168 /**
AnnaBridge 157:e7ca05fa8600 1169 * @}
AnnaBridge 157:e7ca05fa8600 1170 */
AnnaBridge 157:e7ca05fa8600 1171
AnnaBridge 157:e7ca05fa8600 1172 /** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
AnnaBridge 157:e7ca05fa8600 1173 * @{
AnnaBridge 157:e7ca05fa8600 1174 */
AnnaBridge 157:e7ca05fa8600 1175
AnnaBridge 157:e7ca05fa8600 1176 /**
AnnaBridge 157:e7ca05fa8600 1177 * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
AnnaBridge 157:e7ca05fa8600 1178 * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime
AnnaBridge 157:e7ca05fa8600 1179 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1180 * @param Time Value between Min_Data=0 and Max_Data=31
AnnaBridge 157:e7ca05fa8600 1181 * @retval None
AnnaBridge 157:e7ca05fa8600 1182 */
AnnaBridge 157:e7ca05fa8600 1183 __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
AnnaBridge 157:e7ca05fa8600 1184 {
AnnaBridge 157:e7ca05fa8600 1185 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << LPUART_POSITION_CR1_DEDT);
AnnaBridge 157:e7ca05fa8600 1186 }
AnnaBridge 157:e7ca05fa8600 1187
AnnaBridge 157:e7ca05fa8600 1188 /**
AnnaBridge 157:e7ca05fa8600 1189 * @brief Return DEDT (Driver Enable De-Assertion Time)
AnnaBridge 157:e7ca05fa8600 1190 * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime
AnnaBridge 157:e7ca05fa8600 1191 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1192 * @retval Time value expressed on 5 bits ([4:0] bits) : c
AnnaBridge 157:e7ca05fa8600 1193 */
AnnaBridge 157:e7ca05fa8600 1194 __STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1195 {
AnnaBridge 157:e7ca05fa8600 1196 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> LPUART_POSITION_CR1_DEDT);
AnnaBridge 157:e7ca05fa8600 1197 }
AnnaBridge 157:e7ca05fa8600 1198
AnnaBridge 157:e7ca05fa8600 1199 /**
AnnaBridge 157:e7ca05fa8600 1200 * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
AnnaBridge 157:e7ca05fa8600 1201 * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime
AnnaBridge 157:e7ca05fa8600 1202 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1203 * @param Time Value between Min_Data=0 and Max_Data=31
AnnaBridge 157:e7ca05fa8600 1204 * @retval None
AnnaBridge 157:e7ca05fa8600 1205 */
AnnaBridge 157:e7ca05fa8600 1206 __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
AnnaBridge 157:e7ca05fa8600 1207 {
AnnaBridge 157:e7ca05fa8600 1208 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << LPUART_POSITION_CR1_DEAT);
AnnaBridge 157:e7ca05fa8600 1209 }
AnnaBridge 157:e7ca05fa8600 1210
AnnaBridge 157:e7ca05fa8600 1211 /**
AnnaBridge 157:e7ca05fa8600 1212 * @brief Return DEAT (Driver Enable Assertion Time)
AnnaBridge 157:e7ca05fa8600 1213 * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime
AnnaBridge 157:e7ca05fa8600 1214 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1215 * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
AnnaBridge 157:e7ca05fa8600 1216 */
AnnaBridge 157:e7ca05fa8600 1217 __STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1218 {
AnnaBridge 157:e7ca05fa8600 1219 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> LPUART_POSITION_CR1_DEAT);
AnnaBridge 157:e7ca05fa8600 1220 }
AnnaBridge 157:e7ca05fa8600 1221
AnnaBridge 157:e7ca05fa8600 1222 /**
AnnaBridge 157:e7ca05fa8600 1223 * @brief Enable Driver Enable (DE) Mode
AnnaBridge 157:e7ca05fa8600 1224 * @rmtoll CR3 DEM LL_LPUART_EnableDEMode
AnnaBridge 157:e7ca05fa8600 1225 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1226 * @retval None
AnnaBridge 157:e7ca05fa8600 1227 */
AnnaBridge 157:e7ca05fa8600 1228 __STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1229 {
AnnaBridge 157:e7ca05fa8600 1230 SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
AnnaBridge 157:e7ca05fa8600 1231 }
AnnaBridge 157:e7ca05fa8600 1232
AnnaBridge 157:e7ca05fa8600 1233 /**
AnnaBridge 157:e7ca05fa8600 1234 * @brief Disable Driver Enable (DE) Mode
AnnaBridge 157:e7ca05fa8600 1235 * @rmtoll CR3 DEM LL_LPUART_DisableDEMode
AnnaBridge 157:e7ca05fa8600 1236 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1237 * @retval None
AnnaBridge 157:e7ca05fa8600 1238 */
AnnaBridge 157:e7ca05fa8600 1239 __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1240 {
AnnaBridge 157:e7ca05fa8600 1241 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
AnnaBridge 157:e7ca05fa8600 1242 }
AnnaBridge 157:e7ca05fa8600 1243
AnnaBridge 157:e7ca05fa8600 1244 /**
AnnaBridge 157:e7ca05fa8600 1245 * @brief Indicate if Driver Enable (DE) Mode is enabled
AnnaBridge 157:e7ca05fa8600 1246 * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode
AnnaBridge 157:e7ca05fa8600 1247 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1248 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1249 */
AnnaBridge 157:e7ca05fa8600 1250 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1251 {
AnnaBridge 157:e7ca05fa8600 1252 return (READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM));
AnnaBridge 157:e7ca05fa8600 1253 }
AnnaBridge 157:e7ca05fa8600 1254
AnnaBridge 157:e7ca05fa8600 1255 /**
AnnaBridge 157:e7ca05fa8600 1256 * @brief Select Driver Enable Polarity
AnnaBridge 157:e7ca05fa8600 1257 * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity
AnnaBridge 157:e7ca05fa8600 1258 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1259 * @param Polarity This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 1260 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
AnnaBridge 157:e7ca05fa8600 1261 * @arg @ref LL_LPUART_DE_POLARITY_LOW
AnnaBridge 157:e7ca05fa8600 1262 * @retval None
AnnaBridge 157:e7ca05fa8600 1263 */
AnnaBridge 157:e7ca05fa8600 1264 __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
AnnaBridge 157:e7ca05fa8600 1265 {
AnnaBridge 157:e7ca05fa8600 1266 MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
AnnaBridge 157:e7ca05fa8600 1267 }
AnnaBridge 157:e7ca05fa8600 1268
AnnaBridge 157:e7ca05fa8600 1269 /**
AnnaBridge 157:e7ca05fa8600 1270 * @brief Return Driver Enable Polarity
AnnaBridge 157:e7ca05fa8600 1271 * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity
AnnaBridge 157:e7ca05fa8600 1272 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1273 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 1274 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
AnnaBridge 157:e7ca05fa8600 1275 * @arg @ref LL_LPUART_DE_POLARITY_LOW
AnnaBridge 157:e7ca05fa8600 1276 */
AnnaBridge 157:e7ca05fa8600 1277 __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1278 {
AnnaBridge 157:e7ca05fa8600 1279 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
AnnaBridge 157:e7ca05fa8600 1280 }
AnnaBridge 157:e7ca05fa8600 1281
AnnaBridge 157:e7ca05fa8600 1282 /**
AnnaBridge 157:e7ca05fa8600 1283 * @}
AnnaBridge 157:e7ca05fa8600 1284 */
AnnaBridge 157:e7ca05fa8600 1285
AnnaBridge 157:e7ca05fa8600 1286 /** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
AnnaBridge 157:e7ca05fa8600 1287 * @{
AnnaBridge 157:e7ca05fa8600 1288 */
AnnaBridge 157:e7ca05fa8600 1289
AnnaBridge 157:e7ca05fa8600 1290 /**
AnnaBridge 157:e7ca05fa8600 1291 * @brief Check if the LPUART Parity Error Flag is set or not
AnnaBridge 157:e7ca05fa8600 1292 * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE
AnnaBridge 157:e7ca05fa8600 1293 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1294 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1295 */
AnnaBridge 157:e7ca05fa8600 1296 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1297 {
AnnaBridge 157:e7ca05fa8600 1298 return (READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE));
AnnaBridge 157:e7ca05fa8600 1299 }
AnnaBridge 157:e7ca05fa8600 1300
AnnaBridge 157:e7ca05fa8600 1301 /**
AnnaBridge 157:e7ca05fa8600 1302 * @brief Check if the LPUART Framing Error Flag is set or not
AnnaBridge 157:e7ca05fa8600 1303 * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE
AnnaBridge 157:e7ca05fa8600 1304 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1305 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1306 */
AnnaBridge 157:e7ca05fa8600 1307 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1308 {
AnnaBridge 157:e7ca05fa8600 1309 return (READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE));
AnnaBridge 157:e7ca05fa8600 1310 }
AnnaBridge 157:e7ca05fa8600 1311
AnnaBridge 157:e7ca05fa8600 1312 /**
AnnaBridge 157:e7ca05fa8600 1313 * @brief Check if the LPUART Noise detected Flag is set or not
AnnaBridge 157:e7ca05fa8600 1314 * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE
AnnaBridge 157:e7ca05fa8600 1315 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1316 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1317 */
AnnaBridge 157:e7ca05fa8600 1318 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1319 {
AnnaBridge 157:e7ca05fa8600 1320 return (READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE));
AnnaBridge 157:e7ca05fa8600 1321 }
AnnaBridge 157:e7ca05fa8600 1322
AnnaBridge 157:e7ca05fa8600 1323 /**
AnnaBridge 157:e7ca05fa8600 1324 * @brief Check if the LPUART OverRun Error Flag is set or not
AnnaBridge 157:e7ca05fa8600 1325 * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE
AnnaBridge 157:e7ca05fa8600 1326 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1327 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1328 */
AnnaBridge 157:e7ca05fa8600 1329 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1330 {
AnnaBridge 157:e7ca05fa8600 1331 return (READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE));
AnnaBridge 157:e7ca05fa8600 1332 }
AnnaBridge 157:e7ca05fa8600 1333
AnnaBridge 157:e7ca05fa8600 1334 /**
AnnaBridge 157:e7ca05fa8600 1335 * @brief Check if the LPUART IDLE line detected Flag is set or not
AnnaBridge 157:e7ca05fa8600 1336 * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE
AnnaBridge 157:e7ca05fa8600 1337 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1338 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1339 */
AnnaBridge 157:e7ca05fa8600 1340 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1341 {
AnnaBridge 157:e7ca05fa8600 1342 return (READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE));
AnnaBridge 157:e7ca05fa8600 1343 }
AnnaBridge 157:e7ca05fa8600 1344
AnnaBridge 157:e7ca05fa8600 1345 /**
AnnaBridge 157:e7ca05fa8600 1346 * @brief Check if the LPUART Read Data Register Not Empty Flag is set or not
AnnaBridge 157:e7ca05fa8600 1347 * @rmtoll ISR RXNE LL_LPUART_IsActiveFlag_RXNE
AnnaBridge 157:e7ca05fa8600 1348 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1349 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1350 */
AnnaBridge 157:e7ca05fa8600 1351 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1352 {
AnnaBridge 157:e7ca05fa8600 1353 return (READ_BIT(LPUARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE));
AnnaBridge 157:e7ca05fa8600 1354 }
AnnaBridge 157:e7ca05fa8600 1355
AnnaBridge 157:e7ca05fa8600 1356 /**
AnnaBridge 157:e7ca05fa8600 1357 * @brief Check if the LPUART Transmission Complete Flag is set or not
AnnaBridge 157:e7ca05fa8600 1358 * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC
AnnaBridge 157:e7ca05fa8600 1359 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1360 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1361 */
AnnaBridge 157:e7ca05fa8600 1362 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1363 {
AnnaBridge 157:e7ca05fa8600 1364 return (READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC));
AnnaBridge 157:e7ca05fa8600 1365 }
AnnaBridge 157:e7ca05fa8600 1366
AnnaBridge 157:e7ca05fa8600 1367 /**
AnnaBridge 157:e7ca05fa8600 1368 * @brief Check if the LPUART Transmit Data Register Empty Flag is set or not
AnnaBridge 157:e7ca05fa8600 1369 * @rmtoll ISR TXE LL_LPUART_IsActiveFlag_TXE
AnnaBridge 157:e7ca05fa8600 1370 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1371 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1372 */
AnnaBridge 157:e7ca05fa8600 1373 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1374 {
AnnaBridge 157:e7ca05fa8600 1375 return (READ_BIT(LPUARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE));
AnnaBridge 157:e7ca05fa8600 1376 }
AnnaBridge 157:e7ca05fa8600 1377
AnnaBridge 157:e7ca05fa8600 1378 /**
AnnaBridge 157:e7ca05fa8600 1379 * @brief Check if the LPUART CTS interrupt Flag is set or not
AnnaBridge 157:e7ca05fa8600 1380 * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
AnnaBridge 157:e7ca05fa8600 1381 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1382 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1383 */
AnnaBridge 157:e7ca05fa8600 1384 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1385 {
AnnaBridge 157:e7ca05fa8600 1386 return (READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF));
AnnaBridge 157:e7ca05fa8600 1387 }
AnnaBridge 157:e7ca05fa8600 1388
AnnaBridge 157:e7ca05fa8600 1389 /**
AnnaBridge 157:e7ca05fa8600 1390 * @brief Check if the LPUART CTS Flag is set or not
AnnaBridge 157:e7ca05fa8600 1391 * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS
AnnaBridge 157:e7ca05fa8600 1392 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1393 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1394 */
AnnaBridge 157:e7ca05fa8600 1395 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1396 {
AnnaBridge 157:e7ca05fa8600 1397 return (READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS));
AnnaBridge 157:e7ca05fa8600 1398 }
AnnaBridge 157:e7ca05fa8600 1399
AnnaBridge 157:e7ca05fa8600 1400 /**
AnnaBridge 157:e7ca05fa8600 1401 * @brief Check if the LPUART Busy Flag is set or not
AnnaBridge 157:e7ca05fa8600 1402 * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY
AnnaBridge 157:e7ca05fa8600 1403 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1404 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1405 */
AnnaBridge 157:e7ca05fa8600 1406 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1407 {
AnnaBridge 157:e7ca05fa8600 1408 return (READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY));
AnnaBridge 157:e7ca05fa8600 1409 }
AnnaBridge 157:e7ca05fa8600 1410
AnnaBridge 157:e7ca05fa8600 1411 /**
AnnaBridge 157:e7ca05fa8600 1412 * @brief Check if the LPUART Character Match Flag is set or not
AnnaBridge 157:e7ca05fa8600 1413 * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM
AnnaBridge 157:e7ca05fa8600 1414 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1415 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1416 */
AnnaBridge 157:e7ca05fa8600 1417 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1418 {
AnnaBridge 157:e7ca05fa8600 1419 return (READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF));
AnnaBridge 157:e7ca05fa8600 1420 }
AnnaBridge 157:e7ca05fa8600 1421
AnnaBridge 157:e7ca05fa8600 1422 /**
AnnaBridge 157:e7ca05fa8600 1423 * @brief Check if the LPUART Send Break Flag is set or not
AnnaBridge 157:e7ca05fa8600 1424 * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK
AnnaBridge 157:e7ca05fa8600 1425 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1426 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1427 */
AnnaBridge 157:e7ca05fa8600 1428 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1429 {
AnnaBridge 157:e7ca05fa8600 1430 return (READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF));
AnnaBridge 157:e7ca05fa8600 1431 }
AnnaBridge 157:e7ca05fa8600 1432
AnnaBridge 157:e7ca05fa8600 1433 /**
AnnaBridge 157:e7ca05fa8600 1434 * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not
AnnaBridge 157:e7ca05fa8600 1435 * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU
AnnaBridge 157:e7ca05fa8600 1436 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1437 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1438 */
AnnaBridge 157:e7ca05fa8600 1439 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1440 {
AnnaBridge 157:e7ca05fa8600 1441 return (READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU));
AnnaBridge 157:e7ca05fa8600 1442 }
AnnaBridge 157:e7ca05fa8600 1443
AnnaBridge 157:e7ca05fa8600 1444 /**
AnnaBridge 157:e7ca05fa8600 1445 * @brief Check if the LPUART Wake Up from stop mode Flag is set or not
AnnaBridge 157:e7ca05fa8600 1446 * @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP
AnnaBridge 157:e7ca05fa8600 1447 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1448 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1449 */
AnnaBridge 157:e7ca05fa8600 1450 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1451 {
AnnaBridge 157:e7ca05fa8600 1452 return (READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF));
AnnaBridge 157:e7ca05fa8600 1453 }
AnnaBridge 157:e7ca05fa8600 1454
AnnaBridge 157:e7ca05fa8600 1455 /**
AnnaBridge 157:e7ca05fa8600 1456 * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not
AnnaBridge 157:e7ca05fa8600 1457 * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK
AnnaBridge 157:e7ca05fa8600 1458 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1459 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1460 */
AnnaBridge 157:e7ca05fa8600 1461 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1462 {
AnnaBridge 157:e7ca05fa8600 1463 return (READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK));
AnnaBridge 157:e7ca05fa8600 1464 }
AnnaBridge 157:e7ca05fa8600 1465
AnnaBridge 157:e7ca05fa8600 1466 /**
AnnaBridge 157:e7ca05fa8600 1467 * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not
AnnaBridge 157:e7ca05fa8600 1468 * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK
AnnaBridge 157:e7ca05fa8600 1469 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1470 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1471 */
AnnaBridge 157:e7ca05fa8600 1472 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1473 {
AnnaBridge 157:e7ca05fa8600 1474 return (READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK));
AnnaBridge 157:e7ca05fa8600 1475 }
AnnaBridge 157:e7ca05fa8600 1476
AnnaBridge 157:e7ca05fa8600 1477 /**
AnnaBridge 157:e7ca05fa8600 1478 * @brief Clear Parity Error Flag
AnnaBridge 157:e7ca05fa8600 1479 * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE
AnnaBridge 157:e7ca05fa8600 1480 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1481 * @retval None
AnnaBridge 157:e7ca05fa8600 1482 */
AnnaBridge 157:e7ca05fa8600 1483 __STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1484 {
AnnaBridge 157:e7ca05fa8600 1485 WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
AnnaBridge 157:e7ca05fa8600 1486 }
AnnaBridge 157:e7ca05fa8600 1487
AnnaBridge 157:e7ca05fa8600 1488 /**
AnnaBridge 157:e7ca05fa8600 1489 * @brief Clear Framing Error Flag
AnnaBridge 157:e7ca05fa8600 1490 * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE
AnnaBridge 157:e7ca05fa8600 1491 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1492 * @retval None
AnnaBridge 157:e7ca05fa8600 1493 */
AnnaBridge 157:e7ca05fa8600 1494 __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1495 {
AnnaBridge 157:e7ca05fa8600 1496 WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
AnnaBridge 157:e7ca05fa8600 1497 }
AnnaBridge 157:e7ca05fa8600 1498
AnnaBridge 157:e7ca05fa8600 1499 /**
AnnaBridge 157:e7ca05fa8600 1500 * @brief Clear Noise detected Flag
AnnaBridge 157:e7ca05fa8600 1501 * @rmtoll ICR NCF LL_LPUART_ClearFlag_NE
AnnaBridge 157:e7ca05fa8600 1502 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1503 * @retval None
AnnaBridge 157:e7ca05fa8600 1504 */
AnnaBridge 157:e7ca05fa8600 1505 __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1506 {
AnnaBridge 157:e7ca05fa8600 1507 WRITE_REG(LPUARTx->ICR, USART_ICR_NCF);
AnnaBridge 157:e7ca05fa8600 1508 }
AnnaBridge 157:e7ca05fa8600 1509
AnnaBridge 157:e7ca05fa8600 1510 /**
AnnaBridge 157:e7ca05fa8600 1511 * @brief Clear OverRun Error Flag
AnnaBridge 157:e7ca05fa8600 1512 * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE
AnnaBridge 157:e7ca05fa8600 1513 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1514 * @retval None
AnnaBridge 157:e7ca05fa8600 1515 */
AnnaBridge 157:e7ca05fa8600 1516 __STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1517 {
AnnaBridge 157:e7ca05fa8600 1518 WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
AnnaBridge 157:e7ca05fa8600 1519 }
AnnaBridge 157:e7ca05fa8600 1520
AnnaBridge 157:e7ca05fa8600 1521 /**
AnnaBridge 157:e7ca05fa8600 1522 * @brief Clear IDLE line detected Flag
AnnaBridge 157:e7ca05fa8600 1523 * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE
AnnaBridge 157:e7ca05fa8600 1524 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1525 * @retval None
AnnaBridge 157:e7ca05fa8600 1526 */
AnnaBridge 157:e7ca05fa8600 1527 __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1528 {
AnnaBridge 157:e7ca05fa8600 1529 WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
AnnaBridge 157:e7ca05fa8600 1530 }
AnnaBridge 157:e7ca05fa8600 1531
AnnaBridge 157:e7ca05fa8600 1532 /**
AnnaBridge 157:e7ca05fa8600 1533 * @brief Clear Transmission Complete Flag
AnnaBridge 157:e7ca05fa8600 1534 * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
AnnaBridge 157:e7ca05fa8600 1535 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1536 * @retval None
AnnaBridge 157:e7ca05fa8600 1537 */
AnnaBridge 157:e7ca05fa8600 1538 __STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1539 {
AnnaBridge 157:e7ca05fa8600 1540 WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
AnnaBridge 157:e7ca05fa8600 1541 }
AnnaBridge 157:e7ca05fa8600 1542
AnnaBridge 157:e7ca05fa8600 1543 /**
AnnaBridge 157:e7ca05fa8600 1544 * @brief Clear CTS Interrupt Flag
AnnaBridge 157:e7ca05fa8600 1545 * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS
AnnaBridge 157:e7ca05fa8600 1546 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1547 * @retval None
AnnaBridge 157:e7ca05fa8600 1548 */
AnnaBridge 157:e7ca05fa8600 1549 __STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1550 {
AnnaBridge 157:e7ca05fa8600 1551 WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
AnnaBridge 157:e7ca05fa8600 1552 }
AnnaBridge 157:e7ca05fa8600 1553
AnnaBridge 157:e7ca05fa8600 1554 /**
AnnaBridge 157:e7ca05fa8600 1555 * @brief Clear Character Match Flag
AnnaBridge 157:e7ca05fa8600 1556 * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM
AnnaBridge 157:e7ca05fa8600 1557 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1558 * @retval None
AnnaBridge 157:e7ca05fa8600 1559 */
AnnaBridge 157:e7ca05fa8600 1560 __STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1561 {
AnnaBridge 157:e7ca05fa8600 1562 WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
AnnaBridge 157:e7ca05fa8600 1563 }
AnnaBridge 157:e7ca05fa8600 1564
AnnaBridge 157:e7ca05fa8600 1565 /**
AnnaBridge 157:e7ca05fa8600 1566 * @brief Clear Wake Up from stop mode Flag
AnnaBridge 157:e7ca05fa8600 1567 * @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP
AnnaBridge 157:e7ca05fa8600 1568 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1569 * @retval None
AnnaBridge 157:e7ca05fa8600 1570 */
AnnaBridge 157:e7ca05fa8600 1571 __STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1572 {
AnnaBridge 157:e7ca05fa8600 1573 WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
AnnaBridge 157:e7ca05fa8600 1574 }
AnnaBridge 157:e7ca05fa8600 1575
AnnaBridge 157:e7ca05fa8600 1576 /**
AnnaBridge 157:e7ca05fa8600 1577 * @}
AnnaBridge 157:e7ca05fa8600 1578 */
AnnaBridge 157:e7ca05fa8600 1579
AnnaBridge 157:e7ca05fa8600 1580 /** @defgroup LPUART_LL_EF_IT_Management IT_Management
AnnaBridge 157:e7ca05fa8600 1581 * @{
AnnaBridge 157:e7ca05fa8600 1582 */
AnnaBridge 157:e7ca05fa8600 1583
AnnaBridge 157:e7ca05fa8600 1584 /**
AnnaBridge 157:e7ca05fa8600 1585 * @brief Enable IDLE Interrupt
AnnaBridge 157:e7ca05fa8600 1586 * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE
AnnaBridge 157:e7ca05fa8600 1587 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1588 * @retval None
AnnaBridge 157:e7ca05fa8600 1589 */
AnnaBridge 157:e7ca05fa8600 1590 __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1591 {
AnnaBridge 157:e7ca05fa8600 1592 SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
AnnaBridge 157:e7ca05fa8600 1593 }
AnnaBridge 157:e7ca05fa8600 1594
AnnaBridge 157:e7ca05fa8600 1595 /**
AnnaBridge 157:e7ca05fa8600 1596 * @brief Enable RX Not Empty Interrupt
AnnaBridge 157:e7ca05fa8600 1597 * @rmtoll CR1 RXNEIE LL_LPUART_EnableIT_RXNE
AnnaBridge 157:e7ca05fa8600 1598 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1599 * @retval None
AnnaBridge 157:e7ca05fa8600 1600 */
AnnaBridge 157:e7ca05fa8600 1601 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1602 {
AnnaBridge 157:e7ca05fa8600 1603 SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
AnnaBridge 157:e7ca05fa8600 1604 }
AnnaBridge 157:e7ca05fa8600 1605
AnnaBridge 157:e7ca05fa8600 1606 /**
AnnaBridge 157:e7ca05fa8600 1607 * @brief Enable Transmission Complete Interrupt
AnnaBridge 157:e7ca05fa8600 1608 * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC
AnnaBridge 157:e7ca05fa8600 1609 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1610 * @retval None
AnnaBridge 157:e7ca05fa8600 1611 */
AnnaBridge 157:e7ca05fa8600 1612 __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1613 {
AnnaBridge 157:e7ca05fa8600 1614 SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
AnnaBridge 157:e7ca05fa8600 1615 }
AnnaBridge 157:e7ca05fa8600 1616
AnnaBridge 157:e7ca05fa8600 1617 /**
AnnaBridge 157:e7ca05fa8600 1618 * @brief Enable TX Empty Interrupt
AnnaBridge 157:e7ca05fa8600 1619 * @rmtoll CR1 TXEIE LL_LPUART_EnableIT_TXE
AnnaBridge 157:e7ca05fa8600 1620 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1621 * @retval None
AnnaBridge 157:e7ca05fa8600 1622 */
AnnaBridge 157:e7ca05fa8600 1623 __STATIC_INLINE void LL_LPUART_EnableIT_TXE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1624 {
AnnaBridge 157:e7ca05fa8600 1625 SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
AnnaBridge 157:e7ca05fa8600 1626 }
AnnaBridge 157:e7ca05fa8600 1627
AnnaBridge 157:e7ca05fa8600 1628 /**
AnnaBridge 157:e7ca05fa8600 1629 * @brief Enable Parity Error Interrupt
AnnaBridge 157:e7ca05fa8600 1630 * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE
AnnaBridge 157:e7ca05fa8600 1631 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1632 * @retval None
AnnaBridge 157:e7ca05fa8600 1633 */
AnnaBridge 157:e7ca05fa8600 1634 __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1635 {
AnnaBridge 157:e7ca05fa8600 1636 SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
AnnaBridge 157:e7ca05fa8600 1637 }
AnnaBridge 157:e7ca05fa8600 1638
AnnaBridge 157:e7ca05fa8600 1639 /**
AnnaBridge 157:e7ca05fa8600 1640 * @brief Enable Character Match Interrupt
AnnaBridge 157:e7ca05fa8600 1641 * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM
AnnaBridge 157:e7ca05fa8600 1642 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1643 * @retval None
AnnaBridge 157:e7ca05fa8600 1644 */
AnnaBridge 157:e7ca05fa8600 1645 __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1646 {
AnnaBridge 157:e7ca05fa8600 1647 SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
AnnaBridge 157:e7ca05fa8600 1648 }
AnnaBridge 157:e7ca05fa8600 1649
AnnaBridge 157:e7ca05fa8600 1650 /**
AnnaBridge 157:e7ca05fa8600 1651 * @brief Enable Error Interrupt
AnnaBridge 157:e7ca05fa8600 1652 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
AnnaBridge 157:e7ca05fa8600 1653 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
AnnaBridge 157:e7ca05fa8600 1654 * - 0: Interrupt is inhibited
AnnaBridge 157:e7ca05fa8600 1655 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
AnnaBridge 157:e7ca05fa8600 1656 * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR
AnnaBridge 157:e7ca05fa8600 1657 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1658 * @retval None
AnnaBridge 157:e7ca05fa8600 1659 */
AnnaBridge 157:e7ca05fa8600 1660 __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1661 {
AnnaBridge 157:e7ca05fa8600 1662 SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
AnnaBridge 157:e7ca05fa8600 1663 }
AnnaBridge 157:e7ca05fa8600 1664
AnnaBridge 157:e7ca05fa8600 1665 /**
AnnaBridge 157:e7ca05fa8600 1666 * @brief Enable CTS Interrupt
AnnaBridge 157:e7ca05fa8600 1667 * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS
AnnaBridge 157:e7ca05fa8600 1668 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1669 * @retval None
AnnaBridge 157:e7ca05fa8600 1670 */
AnnaBridge 157:e7ca05fa8600 1671 __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1672 {
AnnaBridge 157:e7ca05fa8600 1673 SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
AnnaBridge 157:e7ca05fa8600 1674 }
AnnaBridge 157:e7ca05fa8600 1675
AnnaBridge 157:e7ca05fa8600 1676 /**
AnnaBridge 157:e7ca05fa8600 1677 * @brief Enable Wake Up from Stop Mode Interrupt
AnnaBridge 157:e7ca05fa8600 1678 * @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP
AnnaBridge 157:e7ca05fa8600 1679 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1680 * @retval None
AnnaBridge 157:e7ca05fa8600 1681 */
AnnaBridge 157:e7ca05fa8600 1682 __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1683 {
AnnaBridge 157:e7ca05fa8600 1684 SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
AnnaBridge 157:e7ca05fa8600 1685 }
AnnaBridge 157:e7ca05fa8600 1686
AnnaBridge 157:e7ca05fa8600 1687 /**
AnnaBridge 157:e7ca05fa8600 1688 * @brief Disable IDLE Interrupt
AnnaBridge 157:e7ca05fa8600 1689 * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE
AnnaBridge 157:e7ca05fa8600 1690 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1691 * @retval None
AnnaBridge 157:e7ca05fa8600 1692 */
AnnaBridge 157:e7ca05fa8600 1693 __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1694 {
AnnaBridge 157:e7ca05fa8600 1695 CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
AnnaBridge 157:e7ca05fa8600 1696 }
AnnaBridge 157:e7ca05fa8600 1697
AnnaBridge 157:e7ca05fa8600 1698 /**
AnnaBridge 157:e7ca05fa8600 1699 * @brief Disable RX Not Empty Interrupt
AnnaBridge 157:e7ca05fa8600 1700 * @rmtoll CR1 RXNEIE LL_LPUART_DisableIT_RXNE
AnnaBridge 157:e7ca05fa8600 1701 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1702 * @retval None
AnnaBridge 157:e7ca05fa8600 1703 */
AnnaBridge 157:e7ca05fa8600 1704 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1705 {
AnnaBridge 157:e7ca05fa8600 1706 CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
AnnaBridge 157:e7ca05fa8600 1707 }
AnnaBridge 157:e7ca05fa8600 1708
AnnaBridge 157:e7ca05fa8600 1709 /**
AnnaBridge 157:e7ca05fa8600 1710 * @brief Disable Transmission Complete Interrupt
AnnaBridge 157:e7ca05fa8600 1711 * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC
AnnaBridge 157:e7ca05fa8600 1712 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1713 * @retval None
AnnaBridge 157:e7ca05fa8600 1714 */
AnnaBridge 157:e7ca05fa8600 1715 __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1716 {
AnnaBridge 157:e7ca05fa8600 1717 CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
AnnaBridge 157:e7ca05fa8600 1718 }
AnnaBridge 157:e7ca05fa8600 1719
AnnaBridge 157:e7ca05fa8600 1720 /**
AnnaBridge 157:e7ca05fa8600 1721 * @brief Disable TX Empty Interrupt
AnnaBridge 157:e7ca05fa8600 1722 * @rmtoll CR1 TXEIE LL_LPUART_DisableIT_TXE
AnnaBridge 157:e7ca05fa8600 1723 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1724 * @retval None
AnnaBridge 157:e7ca05fa8600 1725 */
AnnaBridge 157:e7ca05fa8600 1726 __STATIC_INLINE void LL_LPUART_DisableIT_TXE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1727 {
AnnaBridge 157:e7ca05fa8600 1728 CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
AnnaBridge 157:e7ca05fa8600 1729 }
AnnaBridge 157:e7ca05fa8600 1730
AnnaBridge 157:e7ca05fa8600 1731 /**
AnnaBridge 157:e7ca05fa8600 1732 * @brief Disable Parity Error Interrupt
AnnaBridge 157:e7ca05fa8600 1733 * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE
AnnaBridge 157:e7ca05fa8600 1734 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1735 * @retval None
AnnaBridge 157:e7ca05fa8600 1736 */
AnnaBridge 157:e7ca05fa8600 1737 __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1738 {
AnnaBridge 157:e7ca05fa8600 1739 CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
AnnaBridge 157:e7ca05fa8600 1740 }
AnnaBridge 157:e7ca05fa8600 1741
AnnaBridge 157:e7ca05fa8600 1742 /**
AnnaBridge 157:e7ca05fa8600 1743 * @brief Disable Character Match Interrupt
AnnaBridge 157:e7ca05fa8600 1744 * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM
AnnaBridge 157:e7ca05fa8600 1745 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1746 * @retval None
AnnaBridge 157:e7ca05fa8600 1747 */
AnnaBridge 157:e7ca05fa8600 1748 __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1749 {
AnnaBridge 157:e7ca05fa8600 1750 CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
AnnaBridge 157:e7ca05fa8600 1751 }
AnnaBridge 157:e7ca05fa8600 1752
AnnaBridge 157:e7ca05fa8600 1753 /**
AnnaBridge 157:e7ca05fa8600 1754 * @brief Disable Error Interrupt
AnnaBridge 157:e7ca05fa8600 1755 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
AnnaBridge 157:e7ca05fa8600 1756 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
AnnaBridge 157:e7ca05fa8600 1757 * - 0: Interrupt is inhibited
AnnaBridge 157:e7ca05fa8600 1758 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
AnnaBridge 157:e7ca05fa8600 1759 * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR
AnnaBridge 157:e7ca05fa8600 1760 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1761 * @retval None
AnnaBridge 157:e7ca05fa8600 1762 */
AnnaBridge 157:e7ca05fa8600 1763 __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1764 {
AnnaBridge 157:e7ca05fa8600 1765 CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
AnnaBridge 157:e7ca05fa8600 1766 }
AnnaBridge 157:e7ca05fa8600 1767
AnnaBridge 157:e7ca05fa8600 1768 /**
AnnaBridge 157:e7ca05fa8600 1769 * @brief Disable CTS Interrupt
AnnaBridge 157:e7ca05fa8600 1770 * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS
AnnaBridge 157:e7ca05fa8600 1771 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1772 * @retval None
AnnaBridge 157:e7ca05fa8600 1773 */
AnnaBridge 157:e7ca05fa8600 1774 __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1775 {
AnnaBridge 157:e7ca05fa8600 1776 CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
AnnaBridge 157:e7ca05fa8600 1777 }
AnnaBridge 157:e7ca05fa8600 1778
AnnaBridge 157:e7ca05fa8600 1779 /**
AnnaBridge 157:e7ca05fa8600 1780 * @brief Disable Wake Up from Stop Mode Interrupt
AnnaBridge 157:e7ca05fa8600 1781 * @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP
AnnaBridge 157:e7ca05fa8600 1782 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1783 * @retval None
AnnaBridge 157:e7ca05fa8600 1784 */
AnnaBridge 157:e7ca05fa8600 1785 __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1786 {
AnnaBridge 157:e7ca05fa8600 1787 CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
AnnaBridge 157:e7ca05fa8600 1788 }
AnnaBridge 157:e7ca05fa8600 1789
AnnaBridge 157:e7ca05fa8600 1790 /**
AnnaBridge 157:e7ca05fa8600 1791 * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled.
AnnaBridge 157:e7ca05fa8600 1792 * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
AnnaBridge 157:e7ca05fa8600 1793 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1794 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1795 */
AnnaBridge 157:e7ca05fa8600 1796 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1797 {
AnnaBridge 157:e7ca05fa8600 1798 return (READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
AnnaBridge 157:e7ca05fa8600 1799 }
AnnaBridge 157:e7ca05fa8600 1800
AnnaBridge 157:e7ca05fa8600 1801 /**
AnnaBridge 157:e7ca05fa8600 1802 * @brief Check if the LPUART RX Not Empty Interrupt is enabled or disabled.
AnnaBridge 157:e7ca05fa8600 1803 * @rmtoll CR1 RXNEIE LL_LPUART_IsEnabledIT_RXNE
AnnaBridge 157:e7ca05fa8600 1804 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1805 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1806 */
AnnaBridge 157:e7ca05fa8600 1807 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1808 {
AnnaBridge 157:e7ca05fa8600 1809 return (READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
AnnaBridge 157:e7ca05fa8600 1810 }
AnnaBridge 157:e7ca05fa8600 1811
AnnaBridge 157:e7ca05fa8600 1812 /**
AnnaBridge 157:e7ca05fa8600 1813 * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
AnnaBridge 157:e7ca05fa8600 1814 * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC
AnnaBridge 157:e7ca05fa8600 1815 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1816 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1817 */
AnnaBridge 157:e7ca05fa8600 1818 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1819 {
AnnaBridge 157:e7ca05fa8600 1820 return (READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
AnnaBridge 157:e7ca05fa8600 1821 }
AnnaBridge 157:e7ca05fa8600 1822
AnnaBridge 157:e7ca05fa8600 1823 /**
AnnaBridge 157:e7ca05fa8600 1824 * @brief Check if the LPUART TX Empty Interrupt is enabled or disabled.
AnnaBridge 157:e7ca05fa8600 1825 * @rmtoll CR1 TXEIE LL_LPUART_IsEnabledIT_TXE
AnnaBridge 157:e7ca05fa8600 1826 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1827 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1828 */
AnnaBridge 157:e7ca05fa8600 1829 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1830 {
AnnaBridge 157:e7ca05fa8600 1831 return (READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
AnnaBridge 157:e7ca05fa8600 1832 }
AnnaBridge 157:e7ca05fa8600 1833
AnnaBridge 157:e7ca05fa8600 1834 /**
AnnaBridge 157:e7ca05fa8600 1835 * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled.
AnnaBridge 157:e7ca05fa8600 1836 * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE
AnnaBridge 157:e7ca05fa8600 1837 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1838 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1839 */
AnnaBridge 157:e7ca05fa8600 1840 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1841 {
AnnaBridge 157:e7ca05fa8600 1842 return (READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
AnnaBridge 157:e7ca05fa8600 1843 }
AnnaBridge 157:e7ca05fa8600 1844
AnnaBridge 157:e7ca05fa8600 1845 /**
AnnaBridge 157:e7ca05fa8600 1846 * @brief Check if the LPUART Character Match Interrupt is enabled or disabled.
AnnaBridge 157:e7ca05fa8600 1847 * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM
AnnaBridge 157:e7ca05fa8600 1848 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1849 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1850 */
AnnaBridge 157:e7ca05fa8600 1851 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1852 {
AnnaBridge 157:e7ca05fa8600 1853 return (READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE));
AnnaBridge 157:e7ca05fa8600 1854 }
AnnaBridge 157:e7ca05fa8600 1855
AnnaBridge 157:e7ca05fa8600 1856 /**
AnnaBridge 157:e7ca05fa8600 1857 * @brief Check if the LPUART Error Interrupt is enabled or disabled.
AnnaBridge 157:e7ca05fa8600 1858 * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR
AnnaBridge 157:e7ca05fa8600 1859 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1860 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1861 */
AnnaBridge 157:e7ca05fa8600 1862 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1863 {
AnnaBridge 157:e7ca05fa8600 1864 return (READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
AnnaBridge 157:e7ca05fa8600 1865 }
AnnaBridge 157:e7ca05fa8600 1866
AnnaBridge 157:e7ca05fa8600 1867 /**
AnnaBridge 157:e7ca05fa8600 1868 * @brief Check if the LPUART CTS Interrupt is enabled or disabled.
AnnaBridge 157:e7ca05fa8600 1869 * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
AnnaBridge 157:e7ca05fa8600 1870 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1871 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1872 */
AnnaBridge 157:e7ca05fa8600 1873 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1874 {
AnnaBridge 157:e7ca05fa8600 1875 return (READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
AnnaBridge 157:e7ca05fa8600 1876 }
AnnaBridge 157:e7ca05fa8600 1877
AnnaBridge 157:e7ca05fa8600 1878 /**
AnnaBridge 157:e7ca05fa8600 1879 * @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
AnnaBridge 157:e7ca05fa8600 1880 * @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP
AnnaBridge 157:e7ca05fa8600 1881 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1882 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1883 */
AnnaBridge 157:e7ca05fa8600 1884 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1885 {
AnnaBridge 157:e7ca05fa8600 1886 return (READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE));
AnnaBridge 157:e7ca05fa8600 1887 }
AnnaBridge 157:e7ca05fa8600 1888
AnnaBridge 157:e7ca05fa8600 1889 /**
AnnaBridge 157:e7ca05fa8600 1890 * @}
AnnaBridge 157:e7ca05fa8600 1891 */
AnnaBridge 157:e7ca05fa8600 1892
AnnaBridge 157:e7ca05fa8600 1893 /** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
AnnaBridge 157:e7ca05fa8600 1894 * @{
AnnaBridge 157:e7ca05fa8600 1895 */
AnnaBridge 157:e7ca05fa8600 1896
AnnaBridge 157:e7ca05fa8600 1897 /**
AnnaBridge 157:e7ca05fa8600 1898 * @brief Enable DMA Mode for reception
AnnaBridge 157:e7ca05fa8600 1899 * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX
AnnaBridge 157:e7ca05fa8600 1900 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1901 * @retval None
AnnaBridge 157:e7ca05fa8600 1902 */
AnnaBridge 157:e7ca05fa8600 1903 __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1904 {
AnnaBridge 157:e7ca05fa8600 1905 SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
AnnaBridge 157:e7ca05fa8600 1906 }
AnnaBridge 157:e7ca05fa8600 1907
AnnaBridge 157:e7ca05fa8600 1908 /**
AnnaBridge 157:e7ca05fa8600 1909 * @brief Disable DMA Mode for reception
AnnaBridge 157:e7ca05fa8600 1910 * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX
AnnaBridge 157:e7ca05fa8600 1911 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1912 * @retval None
AnnaBridge 157:e7ca05fa8600 1913 */
AnnaBridge 157:e7ca05fa8600 1914 __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1915 {
AnnaBridge 157:e7ca05fa8600 1916 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
AnnaBridge 157:e7ca05fa8600 1917 }
AnnaBridge 157:e7ca05fa8600 1918
AnnaBridge 157:e7ca05fa8600 1919 /**
AnnaBridge 157:e7ca05fa8600 1920 * @brief Check if DMA Mode is enabled for reception
AnnaBridge 157:e7ca05fa8600 1921 * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
AnnaBridge 157:e7ca05fa8600 1922 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1923 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1924 */
AnnaBridge 157:e7ca05fa8600 1925 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1926 {
AnnaBridge 157:e7ca05fa8600 1927 return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
AnnaBridge 157:e7ca05fa8600 1928 }
AnnaBridge 157:e7ca05fa8600 1929
AnnaBridge 157:e7ca05fa8600 1930 /**
AnnaBridge 157:e7ca05fa8600 1931 * @brief Enable DMA Mode for transmission
AnnaBridge 157:e7ca05fa8600 1932 * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX
AnnaBridge 157:e7ca05fa8600 1933 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1934 * @retval None
AnnaBridge 157:e7ca05fa8600 1935 */
AnnaBridge 157:e7ca05fa8600 1936 __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1937 {
AnnaBridge 157:e7ca05fa8600 1938 SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
AnnaBridge 157:e7ca05fa8600 1939 }
AnnaBridge 157:e7ca05fa8600 1940
AnnaBridge 157:e7ca05fa8600 1941 /**
AnnaBridge 157:e7ca05fa8600 1942 * @brief Disable DMA Mode for transmission
AnnaBridge 157:e7ca05fa8600 1943 * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX
AnnaBridge 157:e7ca05fa8600 1944 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1945 * @retval None
AnnaBridge 157:e7ca05fa8600 1946 */
AnnaBridge 157:e7ca05fa8600 1947 __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1948 {
AnnaBridge 157:e7ca05fa8600 1949 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
AnnaBridge 157:e7ca05fa8600 1950 }
AnnaBridge 157:e7ca05fa8600 1951
AnnaBridge 157:e7ca05fa8600 1952 /**
AnnaBridge 157:e7ca05fa8600 1953 * @brief Check if DMA Mode is enabled for transmission
AnnaBridge 157:e7ca05fa8600 1954 * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
AnnaBridge 157:e7ca05fa8600 1955 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1956 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1957 */
AnnaBridge 157:e7ca05fa8600 1958 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1959 {
AnnaBridge 157:e7ca05fa8600 1960 return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
AnnaBridge 157:e7ca05fa8600 1961 }
AnnaBridge 157:e7ca05fa8600 1962
AnnaBridge 157:e7ca05fa8600 1963 /**
AnnaBridge 157:e7ca05fa8600 1964 * @brief Enable DMA Disabling on Reception Error
AnnaBridge 157:e7ca05fa8600 1965 * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
AnnaBridge 157:e7ca05fa8600 1966 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1967 * @retval None
AnnaBridge 157:e7ca05fa8600 1968 */
AnnaBridge 157:e7ca05fa8600 1969 __STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1970 {
AnnaBridge 157:e7ca05fa8600 1971 SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
AnnaBridge 157:e7ca05fa8600 1972 }
AnnaBridge 157:e7ca05fa8600 1973
AnnaBridge 157:e7ca05fa8600 1974 /**
AnnaBridge 157:e7ca05fa8600 1975 * @brief Disable DMA Disabling on Reception Error
AnnaBridge 157:e7ca05fa8600 1976 * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
AnnaBridge 157:e7ca05fa8600 1977 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1978 * @retval None
AnnaBridge 157:e7ca05fa8600 1979 */
AnnaBridge 157:e7ca05fa8600 1980 __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1981 {
AnnaBridge 157:e7ca05fa8600 1982 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
AnnaBridge 157:e7ca05fa8600 1983 }
AnnaBridge 157:e7ca05fa8600 1984
AnnaBridge 157:e7ca05fa8600 1985 /**
AnnaBridge 157:e7ca05fa8600 1986 * @brief Indicate if DMA Disabling on Reception Error is disabled
AnnaBridge 157:e7ca05fa8600 1987 * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
AnnaBridge 157:e7ca05fa8600 1988 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 1989 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 1990 */
AnnaBridge 157:e7ca05fa8600 1991 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 1992 {
AnnaBridge 157:e7ca05fa8600 1993 return (READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE));
AnnaBridge 157:e7ca05fa8600 1994 }
AnnaBridge 157:e7ca05fa8600 1995
AnnaBridge 157:e7ca05fa8600 1996 /**
AnnaBridge 157:e7ca05fa8600 1997 * @brief Get the LPUART data register address used for DMA transfer
AnnaBridge 157:e7ca05fa8600 1998 * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n
AnnaBridge 157:e7ca05fa8600 1999 * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr
AnnaBridge 157:e7ca05fa8600 2000 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 2001 * @param Direction This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 2002 * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
AnnaBridge 157:e7ca05fa8600 2003 * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
AnnaBridge 157:e7ca05fa8600 2004 * @retval Address of data register
AnnaBridge 157:e7ca05fa8600 2005 */
AnnaBridge 157:e7ca05fa8600 2006 __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
AnnaBridge 157:e7ca05fa8600 2007 {
AnnaBridge 157:e7ca05fa8600 2008 register uint32_t data_reg_addr = 0U;
AnnaBridge 157:e7ca05fa8600 2009
AnnaBridge 157:e7ca05fa8600 2010 if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
AnnaBridge 157:e7ca05fa8600 2011 {
AnnaBridge 157:e7ca05fa8600 2012 /* return address of TDR register */
AnnaBridge 157:e7ca05fa8600 2013 data_reg_addr = (uint32_t) &(LPUARTx->TDR);
AnnaBridge 157:e7ca05fa8600 2014 }
AnnaBridge 157:e7ca05fa8600 2015 else
AnnaBridge 157:e7ca05fa8600 2016 {
AnnaBridge 157:e7ca05fa8600 2017 /* return address of RDR register */
AnnaBridge 157:e7ca05fa8600 2018 data_reg_addr = (uint32_t) &(LPUARTx->RDR);
AnnaBridge 157:e7ca05fa8600 2019 }
AnnaBridge 157:e7ca05fa8600 2020
AnnaBridge 157:e7ca05fa8600 2021 return data_reg_addr;
AnnaBridge 157:e7ca05fa8600 2022 }
AnnaBridge 157:e7ca05fa8600 2023
AnnaBridge 157:e7ca05fa8600 2024 /**
AnnaBridge 157:e7ca05fa8600 2025 * @}
AnnaBridge 157:e7ca05fa8600 2026 */
AnnaBridge 157:e7ca05fa8600 2027
AnnaBridge 157:e7ca05fa8600 2028 /** @defgroup LPUART_LL_EF_Data_Management Data_Management
AnnaBridge 157:e7ca05fa8600 2029 * @{
AnnaBridge 157:e7ca05fa8600 2030 */
AnnaBridge 157:e7ca05fa8600 2031
AnnaBridge 157:e7ca05fa8600 2032 /**
AnnaBridge 157:e7ca05fa8600 2033 * @brief Read Receiver Data register (Receive Data value, 8 bits)
AnnaBridge 157:e7ca05fa8600 2034 * @rmtoll RDR RDR LL_LPUART_ReceiveData8
AnnaBridge 157:e7ca05fa8600 2035 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 2036 * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge 157:e7ca05fa8600 2037 */
AnnaBridge 157:e7ca05fa8600 2038 __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 2039 {
AnnaBridge 157:e7ca05fa8600 2040 return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
AnnaBridge 157:e7ca05fa8600 2041 }
AnnaBridge 157:e7ca05fa8600 2042
AnnaBridge 157:e7ca05fa8600 2043 /**
AnnaBridge 157:e7ca05fa8600 2044 * @brief Read Receiver Data register (Receive Data value, 9 bits)
AnnaBridge 157:e7ca05fa8600 2045 * @rmtoll RDR RDR LL_LPUART_ReceiveData9
AnnaBridge 157:e7ca05fa8600 2046 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 2047 * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
AnnaBridge 157:e7ca05fa8600 2048 */
AnnaBridge 157:e7ca05fa8600 2049 __STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 2050 {
AnnaBridge 157:e7ca05fa8600 2051 return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
AnnaBridge 157:e7ca05fa8600 2052 }
AnnaBridge 157:e7ca05fa8600 2053
AnnaBridge 157:e7ca05fa8600 2054 /**
AnnaBridge 157:e7ca05fa8600 2055 * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
AnnaBridge 157:e7ca05fa8600 2056 * @rmtoll TDR TDR LL_LPUART_TransmitData8
AnnaBridge 157:e7ca05fa8600 2057 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 2058 * @param Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge 157:e7ca05fa8600 2059 * @retval None
AnnaBridge 157:e7ca05fa8600 2060 */
AnnaBridge 157:e7ca05fa8600 2061 __STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
AnnaBridge 157:e7ca05fa8600 2062 {
AnnaBridge 157:e7ca05fa8600 2063 LPUARTx->TDR = Value;
AnnaBridge 157:e7ca05fa8600 2064 }
AnnaBridge 157:e7ca05fa8600 2065
AnnaBridge 157:e7ca05fa8600 2066 /**
AnnaBridge 157:e7ca05fa8600 2067 * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
AnnaBridge 157:e7ca05fa8600 2068 * @rmtoll TDR TDR LL_LPUART_TransmitData9
AnnaBridge 157:e7ca05fa8600 2069 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 2070 * @param Value between Min_Data=0x00 and Max_Data=0x1FF
AnnaBridge 157:e7ca05fa8600 2071 * @retval None
AnnaBridge 157:e7ca05fa8600 2072 */
AnnaBridge 157:e7ca05fa8600 2073 __STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
AnnaBridge 157:e7ca05fa8600 2074 {
AnnaBridge 157:e7ca05fa8600 2075 LPUARTx->TDR = Value & 0x1FFU;
AnnaBridge 157:e7ca05fa8600 2076 }
AnnaBridge 157:e7ca05fa8600 2077
AnnaBridge 157:e7ca05fa8600 2078 /**
AnnaBridge 157:e7ca05fa8600 2079 * @}
AnnaBridge 157:e7ca05fa8600 2080 */
AnnaBridge 157:e7ca05fa8600 2081
AnnaBridge 157:e7ca05fa8600 2082 /** @defgroup LPUART_LL_EF_Execution Execution
AnnaBridge 157:e7ca05fa8600 2083 * @{
AnnaBridge 157:e7ca05fa8600 2084 */
AnnaBridge 157:e7ca05fa8600 2085
AnnaBridge 157:e7ca05fa8600 2086 /**
AnnaBridge 157:e7ca05fa8600 2087 * @brief Request Break sending
AnnaBridge 157:e7ca05fa8600 2088 * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending
AnnaBridge 157:e7ca05fa8600 2089 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 2090 * @retval None
AnnaBridge 157:e7ca05fa8600 2091 */
AnnaBridge 157:e7ca05fa8600 2092 __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 2093 {
AnnaBridge 157:e7ca05fa8600 2094 SET_BIT(LPUARTx->RQR, USART_RQR_SBKRQ);
AnnaBridge 157:e7ca05fa8600 2095 }
AnnaBridge 157:e7ca05fa8600 2096
AnnaBridge 157:e7ca05fa8600 2097 /**
AnnaBridge 157:e7ca05fa8600 2098 * @brief Put LPUART in mute mode and set the RWU flag
AnnaBridge 157:e7ca05fa8600 2099 * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode
AnnaBridge 157:e7ca05fa8600 2100 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 2101 * @retval None
AnnaBridge 157:e7ca05fa8600 2102 */
AnnaBridge 157:e7ca05fa8600 2103 __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 2104 {
AnnaBridge 157:e7ca05fa8600 2105 SET_BIT(LPUARTx->RQR, USART_RQR_MMRQ);
AnnaBridge 157:e7ca05fa8600 2106 }
AnnaBridge 157:e7ca05fa8600 2107
AnnaBridge 157:e7ca05fa8600 2108 /**
AnnaBridge 157:e7ca05fa8600 2109 * @brief Request a Receive Data flush
AnnaBridge 157:e7ca05fa8600 2110 * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush
AnnaBridge 157:e7ca05fa8600 2111 * @param LPUARTx LPUART Instance
AnnaBridge 157:e7ca05fa8600 2112 * @retval None
AnnaBridge 157:e7ca05fa8600 2113 */
AnnaBridge 157:e7ca05fa8600 2114 __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
AnnaBridge 157:e7ca05fa8600 2115 {
AnnaBridge 157:e7ca05fa8600 2116 SET_BIT(LPUARTx->RQR, USART_RQR_RXFRQ);
AnnaBridge 157:e7ca05fa8600 2117 }
AnnaBridge 157:e7ca05fa8600 2118
AnnaBridge 157:e7ca05fa8600 2119 /**
AnnaBridge 157:e7ca05fa8600 2120 * @}
AnnaBridge 157:e7ca05fa8600 2121 */
AnnaBridge 157:e7ca05fa8600 2122
AnnaBridge 157:e7ca05fa8600 2123 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 157:e7ca05fa8600 2124 /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
AnnaBridge 157:e7ca05fa8600 2125 * @{
AnnaBridge 157:e7ca05fa8600 2126 */
AnnaBridge 157:e7ca05fa8600 2127 ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
AnnaBridge 157:e7ca05fa8600 2128 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);
AnnaBridge 157:e7ca05fa8600 2129 void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
AnnaBridge 157:e7ca05fa8600 2130 /**
AnnaBridge 157:e7ca05fa8600 2131 * @}
AnnaBridge 157:e7ca05fa8600 2132 */
AnnaBridge 157:e7ca05fa8600 2133 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 157:e7ca05fa8600 2134
AnnaBridge 157:e7ca05fa8600 2135 /**
AnnaBridge 157:e7ca05fa8600 2136 * @}
AnnaBridge 157:e7ca05fa8600 2137 */
AnnaBridge 157:e7ca05fa8600 2138
AnnaBridge 157:e7ca05fa8600 2139 /**
AnnaBridge 157:e7ca05fa8600 2140 * @}
AnnaBridge 157:e7ca05fa8600 2141 */
AnnaBridge 157:e7ca05fa8600 2142
AnnaBridge 157:e7ca05fa8600 2143 #endif /* LPUART1 */
AnnaBridge 157:e7ca05fa8600 2144
AnnaBridge 157:e7ca05fa8600 2145 /**
AnnaBridge 157:e7ca05fa8600 2146 * @}
AnnaBridge 157:e7ca05fa8600 2147 */
AnnaBridge 157:e7ca05fa8600 2148
AnnaBridge 157:e7ca05fa8600 2149 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 2150 }
AnnaBridge 157:e7ca05fa8600 2151 #endif
AnnaBridge 157:e7ca05fa8600 2152
AnnaBridge 157:e7ca05fa8600 2153 #endif /* __STM32L0xx_LL_LPUART_H */
AnnaBridge 157:e7ca05fa8600 2154
AnnaBridge 157:e7ca05fa8600 2155 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/