mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_L011K4/TOOLCHAIN_ARM_MICRO/stm32l0xx_ll_crs.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_NUCLEO_L011K4/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_crs.h@167:84c0a372a020 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 157:e7ca05fa8600 1 /**
AnnaBridge 157:e7ca05fa8600 2 ******************************************************************************
AnnaBridge 157:e7ca05fa8600 3 * @file stm32l0xx_ll_crs.h
AnnaBridge 157:e7ca05fa8600 4 * @author MCD Application Team
AnnaBridge 157:e7ca05fa8600 5 * @brief Header file of CRS LL module.
AnnaBridge 157:e7ca05fa8600 6 ******************************************************************************
AnnaBridge 157:e7ca05fa8600 7 * @attention
AnnaBridge 157:e7ca05fa8600 8 *
AnnaBridge 157:e7ca05fa8600 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 157:e7ca05fa8600 10 *
AnnaBridge 157:e7ca05fa8600 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 157:e7ca05fa8600 12 * are permitted provided that the following conditions are met:
AnnaBridge 157:e7ca05fa8600 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 157:e7ca05fa8600 14 * this list of conditions and the following disclaimer.
AnnaBridge 157:e7ca05fa8600 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 157:e7ca05fa8600 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 157:e7ca05fa8600 17 * and/or other materials provided with the distribution.
AnnaBridge 157:e7ca05fa8600 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 157:e7ca05fa8600 19 * may be used to endorse or promote products derived from this software
AnnaBridge 157:e7ca05fa8600 20 * without specific prior written permission.
AnnaBridge 157:e7ca05fa8600 21 *
AnnaBridge 157:e7ca05fa8600 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 157:e7ca05fa8600 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 157:e7ca05fa8600 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 157:e7ca05fa8600 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 157:e7ca05fa8600 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 157:e7ca05fa8600 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 157:e7ca05fa8600 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 157:e7ca05fa8600 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 157:e7ca05fa8600 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 157:e7ca05fa8600 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 157:e7ca05fa8600 32 *
AnnaBridge 157:e7ca05fa8600 33 ******************************************************************************
AnnaBridge 157:e7ca05fa8600 34 */
AnnaBridge 157:e7ca05fa8600 35
AnnaBridge 157:e7ca05fa8600 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 157:e7ca05fa8600 37 #ifndef __STM32L0xx_LL_CRS_H
AnnaBridge 157:e7ca05fa8600 38 #define __STM32L0xx_LL_CRS_H
AnnaBridge 157:e7ca05fa8600 39
AnnaBridge 157:e7ca05fa8600 40 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 41 extern "C" {
AnnaBridge 157:e7ca05fa8600 42 #endif
AnnaBridge 157:e7ca05fa8600 43
AnnaBridge 157:e7ca05fa8600 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 45 #include "stm32l0xx.h"
AnnaBridge 157:e7ca05fa8600 46
AnnaBridge 157:e7ca05fa8600 47 /** @addtogroup STM32L0xx_LL_Driver
AnnaBridge 157:e7ca05fa8600 48 * @{
AnnaBridge 157:e7ca05fa8600 49 */
AnnaBridge 157:e7ca05fa8600 50
AnnaBridge 157:e7ca05fa8600 51 #if defined(CRS)
AnnaBridge 157:e7ca05fa8600 52
AnnaBridge 157:e7ca05fa8600 53 /** @defgroup CRS_LL CRS
AnnaBridge 157:e7ca05fa8600 54 * @{
AnnaBridge 157:e7ca05fa8600 55 */
AnnaBridge 157:e7ca05fa8600 56
AnnaBridge 157:e7ca05fa8600 57 /* Private types -------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 58 /* Private variables ---------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 59
AnnaBridge 157:e7ca05fa8600 60 /* Private constants ---------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 61 /** @defgroup CRS_LL_Private_Constants CRS Private Constants
AnnaBridge 157:e7ca05fa8600 62 * @{
AnnaBridge 157:e7ca05fa8600 63 */
AnnaBridge 157:e7ca05fa8600 64
AnnaBridge 157:e7ca05fa8600 65 /* Defines used for the bit position in the register and perform offsets*/
AnnaBridge 167:84c0a372a020 66 #define CRS_POSITION_TRIM (CRS_CR_TRIM_Pos) /* bit position in CR reg */
AnnaBridge 167:84c0a372a020 67 #define CRS_POSITION_FECAP (CRS_ISR_FECAP_Pos) /* bit position in ISR reg */
AnnaBridge 167:84c0a372a020 68 #define CRS_POSITION_FELIM (CRS_CFGR_FELIM_Pos) /* bit position in CFGR reg */
AnnaBridge 157:e7ca05fa8600 69
AnnaBridge 157:e7ca05fa8600 70
AnnaBridge 157:e7ca05fa8600 71 /**
AnnaBridge 157:e7ca05fa8600 72 * @}
AnnaBridge 157:e7ca05fa8600 73 */
AnnaBridge 157:e7ca05fa8600 74
AnnaBridge 157:e7ca05fa8600 75 /* Private macros ------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 76
AnnaBridge 157:e7ca05fa8600 77 /* Exported types ------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 78 /* Exported constants --------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 79 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
AnnaBridge 157:e7ca05fa8600 80 * @{
AnnaBridge 157:e7ca05fa8600 81 */
AnnaBridge 157:e7ca05fa8600 82
AnnaBridge 157:e7ca05fa8600 83 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge 157:e7ca05fa8600 84 * @brief Flags defines which can be used with LL_CRS_ReadReg function
AnnaBridge 157:e7ca05fa8600 85 * @{
AnnaBridge 157:e7ca05fa8600 86 */
AnnaBridge 157:e7ca05fa8600 87 #define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
AnnaBridge 157:e7ca05fa8600 88 #define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
AnnaBridge 157:e7ca05fa8600 89 #define LL_CRS_ISR_ERRF CRS_ISR_ERRF
AnnaBridge 157:e7ca05fa8600 90 #define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
AnnaBridge 157:e7ca05fa8600 91 #define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
AnnaBridge 157:e7ca05fa8600 92 #define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
AnnaBridge 157:e7ca05fa8600 93 #define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
AnnaBridge 157:e7ca05fa8600 94 /**
AnnaBridge 157:e7ca05fa8600 95 * @}
AnnaBridge 157:e7ca05fa8600 96 */
AnnaBridge 157:e7ca05fa8600 97
AnnaBridge 157:e7ca05fa8600 98 /** @defgroup CRS_LL_EC_IT IT Defines
AnnaBridge 157:e7ca05fa8600 99 * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
AnnaBridge 157:e7ca05fa8600 100 * @{
AnnaBridge 157:e7ca05fa8600 101 */
AnnaBridge 157:e7ca05fa8600 102 #define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
AnnaBridge 157:e7ca05fa8600 103 #define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
AnnaBridge 157:e7ca05fa8600 104 #define LL_CRS_CR_ERRIE CRS_CR_ERRIE
AnnaBridge 157:e7ca05fa8600 105 #define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
AnnaBridge 157:e7ca05fa8600 106 /**
AnnaBridge 157:e7ca05fa8600 107 * @}
AnnaBridge 157:e7ca05fa8600 108 */
AnnaBridge 157:e7ca05fa8600 109
AnnaBridge 157:e7ca05fa8600 110 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
AnnaBridge 157:e7ca05fa8600 111 * @{
AnnaBridge 157:e7ca05fa8600 112 */
AnnaBridge 157:e7ca05fa8600 113 #define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */
AnnaBridge 157:e7ca05fa8600 114 #define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
AnnaBridge 157:e7ca05fa8600 115 #define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
AnnaBridge 157:e7ca05fa8600 116 #define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
AnnaBridge 157:e7ca05fa8600 117 #define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
AnnaBridge 157:e7ca05fa8600 118 #define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
AnnaBridge 157:e7ca05fa8600 119 #define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
AnnaBridge 157:e7ca05fa8600 120 #define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
AnnaBridge 157:e7ca05fa8600 121 /**
AnnaBridge 157:e7ca05fa8600 122 * @}
AnnaBridge 157:e7ca05fa8600 123 */
AnnaBridge 157:e7ca05fa8600 124
AnnaBridge 157:e7ca05fa8600 125 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
AnnaBridge 157:e7ca05fa8600 126 * @{
AnnaBridge 157:e7ca05fa8600 127 */
AnnaBridge 157:e7ca05fa8600 128 #define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal soucre GPIO */
AnnaBridge 157:e7ca05fa8600 129 #define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
AnnaBridge 157:e7ca05fa8600 130 #define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
AnnaBridge 157:e7ca05fa8600 131 /**
AnnaBridge 157:e7ca05fa8600 132 * @}
AnnaBridge 157:e7ca05fa8600 133 */
AnnaBridge 157:e7ca05fa8600 134
AnnaBridge 157:e7ca05fa8600 135 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
AnnaBridge 157:e7ca05fa8600 136 * @{
AnnaBridge 157:e7ca05fa8600 137 */
AnnaBridge 157:e7ca05fa8600 138 #define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */
AnnaBridge 157:e7ca05fa8600 139 #define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
AnnaBridge 157:e7ca05fa8600 140 /**
AnnaBridge 157:e7ca05fa8600 141 * @}
AnnaBridge 157:e7ca05fa8600 142 */
AnnaBridge 157:e7ca05fa8600 143
AnnaBridge 157:e7ca05fa8600 144 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
AnnaBridge 157:e7ca05fa8600 145 * @{
AnnaBridge 157:e7ca05fa8600 146 */
AnnaBridge 157:e7ca05fa8600 147 #define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */
AnnaBridge 157:e7ca05fa8600 148 #define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
AnnaBridge 157:e7ca05fa8600 149 /**
AnnaBridge 157:e7ca05fa8600 150 * @}
AnnaBridge 157:e7ca05fa8600 151 */
AnnaBridge 157:e7ca05fa8600 152
AnnaBridge 157:e7ca05fa8600 153 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
AnnaBridge 157:e7ca05fa8600 154 * @{
AnnaBridge 157:e7ca05fa8600 155 */
AnnaBridge 157:e7ca05fa8600 156 /**
AnnaBridge 157:e7ca05fa8600 157 * @brief Reset value of the RELOAD field
AnnaBridge 157:e7ca05fa8600 158 * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
AnnaBridge 157:e7ca05fa8600 159 * and a synchronization signal frequency of 1 kHz (SOF signal from USB)
AnnaBridge 157:e7ca05fa8600 160 */
AnnaBridge 157:e7ca05fa8600 161 #define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)
AnnaBridge 157:e7ca05fa8600 162
AnnaBridge 157:e7ca05fa8600 163 /**
AnnaBridge 157:e7ca05fa8600 164 * @brief Reset value of Frequency error limit.
AnnaBridge 157:e7ca05fa8600 165 */
AnnaBridge 157:e7ca05fa8600 166 #define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)
AnnaBridge 157:e7ca05fa8600 167
AnnaBridge 157:e7ca05fa8600 168 /**
AnnaBridge 157:e7ca05fa8600 169 * @brief Reset value of the HSI48 Calibration field
AnnaBridge 157:e7ca05fa8600 170 * @note The default value is 32, which corresponds to the middle of the trimming interval.
AnnaBridge 157:e7ca05fa8600 171 * The trimming step is around 67 kHz between two consecutive TRIM steps.
AnnaBridge 157:e7ca05fa8600 172 * A higher TRIM value corresponds to a higher output frequency
AnnaBridge 157:e7ca05fa8600 173 */
AnnaBridge 157:e7ca05fa8600 174 #define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U)
AnnaBridge 157:e7ca05fa8600 175 /**
AnnaBridge 157:e7ca05fa8600 176 * @}
AnnaBridge 157:e7ca05fa8600 177 */
AnnaBridge 157:e7ca05fa8600 178
AnnaBridge 157:e7ca05fa8600 179 /**
AnnaBridge 157:e7ca05fa8600 180 * @}
AnnaBridge 157:e7ca05fa8600 181 */
AnnaBridge 157:e7ca05fa8600 182
AnnaBridge 157:e7ca05fa8600 183 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 184 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
AnnaBridge 157:e7ca05fa8600 185 * @{
AnnaBridge 157:e7ca05fa8600 186 */
AnnaBridge 157:e7ca05fa8600 187
AnnaBridge 157:e7ca05fa8600 188 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge 157:e7ca05fa8600 189 * @{
AnnaBridge 157:e7ca05fa8600 190 */
AnnaBridge 157:e7ca05fa8600 191
AnnaBridge 157:e7ca05fa8600 192 /**
AnnaBridge 157:e7ca05fa8600 193 * @brief Write a value in CRS register
AnnaBridge 157:e7ca05fa8600 194 * @param __INSTANCE__ CRS Instance
AnnaBridge 157:e7ca05fa8600 195 * @param __REG__ Register to be written
AnnaBridge 157:e7ca05fa8600 196 * @param __VALUE__ Value to be written in the register
AnnaBridge 157:e7ca05fa8600 197 * @retval None
AnnaBridge 157:e7ca05fa8600 198 */
AnnaBridge 157:e7ca05fa8600 199 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge 157:e7ca05fa8600 200
AnnaBridge 157:e7ca05fa8600 201 /**
AnnaBridge 157:e7ca05fa8600 202 * @brief Read a value in CRS register
AnnaBridge 157:e7ca05fa8600 203 * @param __INSTANCE__ CRS Instance
AnnaBridge 157:e7ca05fa8600 204 * @param __REG__ Register to be read
AnnaBridge 157:e7ca05fa8600 205 * @retval Register value
AnnaBridge 157:e7ca05fa8600 206 */
AnnaBridge 157:e7ca05fa8600 207 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge 157:e7ca05fa8600 208 /**
AnnaBridge 157:e7ca05fa8600 209 * @}
AnnaBridge 157:e7ca05fa8600 210 */
AnnaBridge 157:e7ca05fa8600 211
AnnaBridge 157:e7ca05fa8600 212 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
AnnaBridge 157:e7ca05fa8600 213 * @{
AnnaBridge 157:e7ca05fa8600 214 */
AnnaBridge 157:e7ca05fa8600 215
AnnaBridge 157:e7ca05fa8600 216 /**
AnnaBridge 157:e7ca05fa8600 217 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
AnnaBridge 157:e7ca05fa8600 218 * @note The RELOAD value should be selected according to the ratio between
AnnaBridge 157:e7ca05fa8600 219 * the target frequency and the frequency of the synchronization source after
AnnaBridge 157:e7ca05fa8600 220 * prescaling. It is then decreased by one in order to reach the expected
AnnaBridge 157:e7ca05fa8600 221 * synchronization on the zero value. The formula is the following:
AnnaBridge 157:e7ca05fa8600 222 * RELOAD = (fTARGET / fSYNC) -1
AnnaBridge 157:e7ca05fa8600 223 * @param __FTARGET__ Target frequency (value in Hz)
AnnaBridge 157:e7ca05fa8600 224 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
AnnaBridge 157:e7ca05fa8600 225 * @retval Reload value (in Hz)
AnnaBridge 157:e7ca05fa8600 226 */
AnnaBridge 157:e7ca05fa8600 227 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
AnnaBridge 157:e7ca05fa8600 228
AnnaBridge 157:e7ca05fa8600 229 /**
AnnaBridge 157:e7ca05fa8600 230 * @}
AnnaBridge 157:e7ca05fa8600 231 */
AnnaBridge 157:e7ca05fa8600 232
AnnaBridge 157:e7ca05fa8600 233 /**
AnnaBridge 157:e7ca05fa8600 234 * @}
AnnaBridge 157:e7ca05fa8600 235 */
AnnaBridge 157:e7ca05fa8600 236
AnnaBridge 157:e7ca05fa8600 237 /* Exported functions --------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 238 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
AnnaBridge 157:e7ca05fa8600 239 * @{
AnnaBridge 157:e7ca05fa8600 240 */
AnnaBridge 157:e7ca05fa8600 241
AnnaBridge 157:e7ca05fa8600 242 /** @defgroup CRS_LL_EF_Configuration Configuration
AnnaBridge 157:e7ca05fa8600 243 * @{
AnnaBridge 157:e7ca05fa8600 244 */
AnnaBridge 157:e7ca05fa8600 245
AnnaBridge 157:e7ca05fa8600 246 /**
AnnaBridge 157:e7ca05fa8600 247 * @brief Enable Frequency error counter
AnnaBridge 157:e7ca05fa8600 248 * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
AnnaBridge 157:e7ca05fa8600 249 * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
AnnaBridge 157:e7ca05fa8600 250 * @retval None
AnnaBridge 157:e7ca05fa8600 251 */
AnnaBridge 157:e7ca05fa8600 252 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
AnnaBridge 157:e7ca05fa8600 253 {
AnnaBridge 157:e7ca05fa8600 254 SET_BIT(CRS->CR, CRS_CR_CEN);
AnnaBridge 157:e7ca05fa8600 255 }
AnnaBridge 157:e7ca05fa8600 256
AnnaBridge 157:e7ca05fa8600 257 /**
AnnaBridge 157:e7ca05fa8600 258 * @brief Disable Frequency error counter
AnnaBridge 157:e7ca05fa8600 259 * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
AnnaBridge 157:e7ca05fa8600 260 * @retval None
AnnaBridge 157:e7ca05fa8600 261 */
AnnaBridge 157:e7ca05fa8600 262 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
AnnaBridge 157:e7ca05fa8600 263 {
AnnaBridge 157:e7ca05fa8600 264 CLEAR_BIT(CRS->CR, CRS_CR_CEN);
AnnaBridge 157:e7ca05fa8600 265 }
AnnaBridge 157:e7ca05fa8600 266
AnnaBridge 157:e7ca05fa8600 267 /**
AnnaBridge 157:e7ca05fa8600 268 * @brief Check if Frequency error counter is enabled or not
AnnaBridge 157:e7ca05fa8600 269 * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
AnnaBridge 157:e7ca05fa8600 270 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 271 */
AnnaBridge 157:e7ca05fa8600 272 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
AnnaBridge 157:e7ca05fa8600 273 {
AnnaBridge 157:e7ca05fa8600 274 return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
AnnaBridge 157:e7ca05fa8600 275 }
AnnaBridge 157:e7ca05fa8600 276
AnnaBridge 157:e7ca05fa8600 277 /**
AnnaBridge 157:e7ca05fa8600 278 * @brief Enable Automatic trimming counter
AnnaBridge 157:e7ca05fa8600 279 * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
AnnaBridge 157:e7ca05fa8600 280 * @retval None
AnnaBridge 157:e7ca05fa8600 281 */
AnnaBridge 157:e7ca05fa8600 282 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
AnnaBridge 157:e7ca05fa8600 283 {
AnnaBridge 157:e7ca05fa8600 284 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
AnnaBridge 157:e7ca05fa8600 285 }
AnnaBridge 157:e7ca05fa8600 286
AnnaBridge 157:e7ca05fa8600 287 /**
AnnaBridge 157:e7ca05fa8600 288 * @brief Disable Automatic trimming counter
AnnaBridge 157:e7ca05fa8600 289 * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
AnnaBridge 157:e7ca05fa8600 290 * @retval None
AnnaBridge 157:e7ca05fa8600 291 */
AnnaBridge 157:e7ca05fa8600 292 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
AnnaBridge 157:e7ca05fa8600 293 {
AnnaBridge 157:e7ca05fa8600 294 CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
AnnaBridge 157:e7ca05fa8600 295 }
AnnaBridge 157:e7ca05fa8600 296
AnnaBridge 157:e7ca05fa8600 297 /**
AnnaBridge 157:e7ca05fa8600 298 * @brief Check if Automatic trimming is enabled or not
AnnaBridge 157:e7ca05fa8600 299 * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
AnnaBridge 157:e7ca05fa8600 300 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 301 */
AnnaBridge 157:e7ca05fa8600 302 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
AnnaBridge 157:e7ca05fa8600 303 {
AnnaBridge 157:e7ca05fa8600 304 return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
AnnaBridge 157:e7ca05fa8600 305 }
AnnaBridge 157:e7ca05fa8600 306
AnnaBridge 157:e7ca05fa8600 307 /**
AnnaBridge 157:e7ca05fa8600 308 * @brief Set HSI48 oscillator smooth trimming
AnnaBridge 157:e7ca05fa8600 309 * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
AnnaBridge 157:e7ca05fa8600 310 * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
AnnaBridge 157:e7ca05fa8600 311 * @param Value a number between Min_Data = 0 and Max_Data = 63
AnnaBridge 157:e7ca05fa8600 312 * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
AnnaBridge 157:e7ca05fa8600 313 * @retval None
AnnaBridge 157:e7ca05fa8600 314 */
AnnaBridge 157:e7ca05fa8600 315 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
AnnaBridge 157:e7ca05fa8600 316 {
AnnaBridge 157:e7ca05fa8600 317 MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM);
AnnaBridge 157:e7ca05fa8600 318 }
AnnaBridge 157:e7ca05fa8600 319
AnnaBridge 157:e7ca05fa8600 320 /**
AnnaBridge 157:e7ca05fa8600 321 * @brief Get HSI48 oscillator smooth trimming
AnnaBridge 157:e7ca05fa8600 322 * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
AnnaBridge 157:e7ca05fa8600 323 * @retval a number between Min_Data = 0 and Max_Data = 63
AnnaBridge 157:e7ca05fa8600 324 */
AnnaBridge 157:e7ca05fa8600 325 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
AnnaBridge 157:e7ca05fa8600 326 {
AnnaBridge 157:e7ca05fa8600 327 return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM);
AnnaBridge 157:e7ca05fa8600 328 }
AnnaBridge 157:e7ca05fa8600 329
AnnaBridge 157:e7ca05fa8600 330 /**
AnnaBridge 157:e7ca05fa8600 331 * @brief Set counter reload value
AnnaBridge 157:e7ca05fa8600 332 * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
AnnaBridge 157:e7ca05fa8600 333 * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
AnnaBridge 157:e7ca05fa8600 334 * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
AnnaBridge 157:e7ca05fa8600 335 * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
AnnaBridge 157:e7ca05fa8600 336 * @retval None
AnnaBridge 157:e7ca05fa8600 337 */
AnnaBridge 157:e7ca05fa8600 338 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
AnnaBridge 157:e7ca05fa8600 339 {
AnnaBridge 157:e7ca05fa8600 340 MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
AnnaBridge 157:e7ca05fa8600 341 }
AnnaBridge 157:e7ca05fa8600 342
AnnaBridge 157:e7ca05fa8600 343 /**
AnnaBridge 157:e7ca05fa8600 344 * @brief Get counter reload value
AnnaBridge 157:e7ca05fa8600 345 * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
AnnaBridge 157:e7ca05fa8600 346 * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
AnnaBridge 157:e7ca05fa8600 347 */
AnnaBridge 157:e7ca05fa8600 348 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
AnnaBridge 157:e7ca05fa8600 349 {
AnnaBridge 157:e7ca05fa8600 350 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
AnnaBridge 157:e7ca05fa8600 351 }
AnnaBridge 157:e7ca05fa8600 352
AnnaBridge 157:e7ca05fa8600 353 /**
AnnaBridge 157:e7ca05fa8600 354 * @brief Set frequency error limit
AnnaBridge 157:e7ca05fa8600 355 * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
AnnaBridge 157:e7ca05fa8600 356 * @param Value a number between Min_Data = 0 and Max_Data = 255
AnnaBridge 157:e7ca05fa8600 357 * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
AnnaBridge 157:e7ca05fa8600 358 * @retval None
AnnaBridge 157:e7ca05fa8600 359 */
AnnaBridge 157:e7ca05fa8600 360 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
AnnaBridge 157:e7ca05fa8600 361 {
AnnaBridge 157:e7ca05fa8600 362 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM);
AnnaBridge 157:e7ca05fa8600 363 }
AnnaBridge 157:e7ca05fa8600 364
AnnaBridge 157:e7ca05fa8600 365 /**
AnnaBridge 157:e7ca05fa8600 366 * @brief Get frequency error limit
AnnaBridge 157:e7ca05fa8600 367 * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
AnnaBridge 157:e7ca05fa8600 368 * @retval A number between Min_Data = 0 and Max_Data = 255
AnnaBridge 157:e7ca05fa8600 369 */
AnnaBridge 157:e7ca05fa8600 370 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
AnnaBridge 157:e7ca05fa8600 371 {
AnnaBridge 157:e7ca05fa8600 372 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM);
AnnaBridge 157:e7ca05fa8600 373 }
AnnaBridge 157:e7ca05fa8600 374
AnnaBridge 157:e7ca05fa8600 375 /**
AnnaBridge 157:e7ca05fa8600 376 * @brief Set division factor for SYNC signal
AnnaBridge 157:e7ca05fa8600 377 * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
AnnaBridge 157:e7ca05fa8600 378 * @param Divider This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 379 * @arg @ref LL_CRS_SYNC_DIV_1
AnnaBridge 157:e7ca05fa8600 380 * @arg @ref LL_CRS_SYNC_DIV_2
AnnaBridge 157:e7ca05fa8600 381 * @arg @ref LL_CRS_SYNC_DIV_4
AnnaBridge 157:e7ca05fa8600 382 * @arg @ref LL_CRS_SYNC_DIV_8
AnnaBridge 157:e7ca05fa8600 383 * @arg @ref LL_CRS_SYNC_DIV_16
AnnaBridge 157:e7ca05fa8600 384 * @arg @ref LL_CRS_SYNC_DIV_32
AnnaBridge 157:e7ca05fa8600 385 * @arg @ref LL_CRS_SYNC_DIV_64
AnnaBridge 157:e7ca05fa8600 386 * @arg @ref LL_CRS_SYNC_DIV_128
AnnaBridge 157:e7ca05fa8600 387 * @retval None
AnnaBridge 157:e7ca05fa8600 388 */
AnnaBridge 157:e7ca05fa8600 389 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
AnnaBridge 157:e7ca05fa8600 390 {
AnnaBridge 157:e7ca05fa8600 391 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
AnnaBridge 157:e7ca05fa8600 392 }
AnnaBridge 157:e7ca05fa8600 393
AnnaBridge 157:e7ca05fa8600 394 /**
AnnaBridge 157:e7ca05fa8600 395 * @brief Get division factor for SYNC signal
AnnaBridge 157:e7ca05fa8600 396 * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
AnnaBridge 157:e7ca05fa8600 397 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 398 * @arg @ref LL_CRS_SYNC_DIV_1
AnnaBridge 157:e7ca05fa8600 399 * @arg @ref LL_CRS_SYNC_DIV_2
AnnaBridge 157:e7ca05fa8600 400 * @arg @ref LL_CRS_SYNC_DIV_4
AnnaBridge 157:e7ca05fa8600 401 * @arg @ref LL_CRS_SYNC_DIV_8
AnnaBridge 157:e7ca05fa8600 402 * @arg @ref LL_CRS_SYNC_DIV_16
AnnaBridge 157:e7ca05fa8600 403 * @arg @ref LL_CRS_SYNC_DIV_32
AnnaBridge 157:e7ca05fa8600 404 * @arg @ref LL_CRS_SYNC_DIV_64
AnnaBridge 157:e7ca05fa8600 405 * @arg @ref LL_CRS_SYNC_DIV_128
AnnaBridge 157:e7ca05fa8600 406 */
AnnaBridge 157:e7ca05fa8600 407 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
AnnaBridge 157:e7ca05fa8600 408 {
AnnaBridge 157:e7ca05fa8600 409 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
AnnaBridge 157:e7ca05fa8600 410 }
AnnaBridge 157:e7ca05fa8600 411
AnnaBridge 157:e7ca05fa8600 412 /**
AnnaBridge 157:e7ca05fa8600 413 * @brief Set SYNC signal source
AnnaBridge 157:e7ca05fa8600 414 * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
AnnaBridge 157:e7ca05fa8600 415 * @param Source This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 416 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
AnnaBridge 157:e7ca05fa8600 417 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
AnnaBridge 157:e7ca05fa8600 418 * @arg @ref LL_CRS_SYNC_SOURCE_USB
AnnaBridge 157:e7ca05fa8600 419 * @retval None
AnnaBridge 157:e7ca05fa8600 420 */
AnnaBridge 157:e7ca05fa8600 421 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
AnnaBridge 157:e7ca05fa8600 422 {
AnnaBridge 157:e7ca05fa8600 423 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
AnnaBridge 157:e7ca05fa8600 424 }
AnnaBridge 157:e7ca05fa8600 425
AnnaBridge 157:e7ca05fa8600 426 /**
AnnaBridge 157:e7ca05fa8600 427 * @brief Get SYNC signal source
AnnaBridge 157:e7ca05fa8600 428 * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
AnnaBridge 157:e7ca05fa8600 429 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 430 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
AnnaBridge 157:e7ca05fa8600 431 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
AnnaBridge 157:e7ca05fa8600 432 * @arg @ref LL_CRS_SYNC_SOURCE_USB
AnnaBridge 157:e7ca05fa8600 433 */
AnnaBridge 157:e7ca05fa8600 434 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
AnnaBridge 157:e7ca05fa8600 435 {
AnnaBridge 157:e7ca05fa8600 436 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
AnnaBridge 157:e7ca05fa8600 437 }
AnnaBridge 157:e7ca05fa8600 438
AnnaBridge 157:e7ca05fa8600 439 /**
AnnaBridge 157:e7ca05fa8600 440 * @brief Set input polarity for the SYNC signal source
AnnaBridge 157:e7ca05fa8600 441 * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
AnnaBridge 157:e7ca05fa8600 442 * @param Polarity This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 443 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
AnnaBridge 157:e7ca05fa8600 444 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
AnnaBridge 157:e7ca05fa8600 445 * @retval None
AnnaBridge 157:e7ca05fa8600 446 */
AnnaBridge 157:e7ca05fa8600 447 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
AnnaBridge 157:e7ca05fa8600 448 {
AnnaBridge 157:e7ca05fa8600 449 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
AnnaBridge 157:e7ca05fa8600 450 }
AnnaBridge 157:e7ca05fa8600 451
AnnaBridge 157:e7ca05fa8600 452 /**
AnnaBridge 157:e7ca05fa8600 453 * @brief Get input polarity for the SYNC signal source
AnnaBridge 157:e7ca05fa8600 454 * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
AnnaBridge 157:e7ca05fa8600 455 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 456 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
AnnaBridge 157:e7ca05fa8600 457 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
AnnaBridge 157:e7ca05fa8600 458 */
AnnaBridge 157:e7ca05fa8600 459 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
AnnaBridge 157:e7ca05fa8600 460 {
AnnaBridge 157:e7ca05fa8600 461 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
AnnaBridge 157:e7ca05fa8600 462 }
AnnaBridge 157:e7ca05fa8600 463
AnnaBridge 157:e7ca05fa8600 464 /**
AnnaBridge 157:e7ca05fa8600 465 * @brief Configure CRS for the synchronization
AnnaBridge 157:e7ca05fa8600 466 * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
AnnaBridge 157:e7ca05fa8600 467 * CFGR RELOAD LL_CRS_ConfigSynchronization\n
AnnaBridge 157:e7ca05fa8600 468 * CFGR FELIM LL_CRS_ConfigSynchronization\n
AnnaBridge 157:e7ca05fa8600 469 * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
AnnaBridge 157:e7ca05fa8600 470 * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
AnnaBridge 157:e7ca05fa8600 471 * CFGR SYNCPOL LL_CRS_ConfigSynchronization
AnnaBridge 157:e7ca05fa8600 472 * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
AnnaBridge 157:e7ca05fa8600 473 * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
AnnaBridge 157:e7ca05fa8600 474 * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
AnnaBridge 157:e7ca05fa8600 475 * @param Settings This parameter can be a combination of the following values:
AnnaBridge 157:e7ca05fa8600 476 * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
AnnaBridge 157:e7ca05fa8600 477 * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
AnnaBridge 157:e7ca05fa8600 478 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
AnnaBridge 157:e7ca05fa8600 479 * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
AnnaBridge 157:e7ca05fa8600 480 * @retval None
AnnaBridge 157:e7ca05fa8600 481 */
AnnaBridge 157:e7ca05fa8600 482 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
AnnaBridge 157:e7ca05fa8600 483 {
AnnaBridge 157:e7ca05fa8600 484 MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
AnnaBridge 157:e7ca05fa8600 485 MODIFY_REG(CRS->CFGR,
AnnaBridge 157:e7ca05fa8600 486 CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
AnnaBridge 157:e7ca05fa8600 487 ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings);
AnnaBridge 157:e7ca05fa8600 488 }
AnnaBridge 157:e7ca05fa8600 489
AnnaBridge 157:e7ca05fa8600 490 /**
AnnaBridge 157:e7ca05fa8600 491 * @}
AnnaBridge 157:e7ca05fa8600 492 */
AnnaBridge 157:e7ca05fa8600 493
AnnaBridge 157:e7ca05fa8600 494 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
AnnaBridge 157:e7ca05fa8600 495 * @{
AnnaBridge 157:e7ca05fa8600 496 */
AnnaBridge 157:e7ca05fa8600 497
AnnaBridge 157:e7ca05fa8600 498 /**
AnnaBridge 157:e7ca05fa8600 499 * @brief Generate software SYNC event
AnnaBridge 157:e7ca05fa8600 500 * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
AnnaBridge 157:e7ca05fa8600 501 * @retval None
AnnaBridge 157:e7ca05fa8600 502 */
AnnaBridge 157:e7ca05fa8600 503 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
AnnaBridge 157:e7ca05fa8600 504 {
AnnaBridge 157:e7ca05fa8600 505 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
AnnaBridge 157:e7ca05fa8600 506 }
AnnaBridge 157:e7ca05fa8600 507
AnnaBridge 157:e7ca05fa8600 508 /**
AnnaBridge 157:e7ca05fa8600 509 * @brief Get the frequency error direction latched in the time of the last
AnnaBridge 157:e7ca05fa8600 510 * SYNC event
AnnaBridge 157:e7ca05fa8600 511 * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
AnnaBridge 157:e7ca05fa8600 512 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 513 * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
AnnaBridge 157:e7ca05fa8600 514 * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
AnnaBridge 157:e7ca05fa8600 515 */
AnnaBridge 157:e7ca05fa8600 516 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
AnnaBridge 157:e7ca05fa8600 517 {
AnnaBridge 157:e7ca05fa8600 518 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
AnnaBridge 157:e7ca05fa8600 519 }
AnnaBridge 157:e7ca05fa8600 520
AnnaBridge 157:e7ca05fa8600 521 /**
AnnaBridge 157:e7ca05fa8600 522 * @brief Get the frequency error counter value latched in the time of the last SYNC event
AnnaBridge 157:e7ca05fa8600 523 * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
AnnaBridge 157:e7ca05fa8600 524 * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
AnnaBridge 157:e7ca05fa8600 525 */
AnnaBridge 157:e7ca05fa8600 526 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
AnnaBridge 157:e7ca05fa8600 527 {
AnnaBridge 157:e7ca05fa8600 528 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP);
AnnaBridge 157:e7ca05fa8600 529 }
AnnaBridge 157:e7ca05fa8600 530
AnnaBridge 157:e7ca05fa8600 531 /**
AnnaBridge 157:e7ca05fa8600 532 * @}
AnnaBridge 157:e7ca05fa8600 533 */
AnnaBridge 157:e7ca05fa8600 534
AnnaBridge 157:e7ca05fa8600 535 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
AnnaBridge 157:e7ca05fa8600 536 * @{
AnnaBridge 157:e7ca05fa8600 537 */
AnnaBridge 157:e7ca05fa8600 538
AnnaBridge 157:e7ca05fa8600 539 /**
AnnaBridge 157:e7ca05fa8600 540 * @brief Check if SYNC event OK signal occurred or not
AnnaBridge 157:e7ca05fa8600 541 * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
AnnaBridge 157:e7ca05fa8600 542 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 543 */
AnnaBridge 157:e7ca05fa8600 544 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
AnnaBridge 157:e7ca05fa8600 545 {
AnnaBridge 157:e7ca05fa8600 546 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
AnnaBridge 157:e7ca05fa8600 547 }
AnnaBridge 157:e7ca05fa8600 548
AnnaBridge 157:e7ca05fa8600 549 /**
AnnaBridge 157:e7ca05fa8600 550 * @brief Check if SYNC warning signal occurred or not
AnnaBridge 157:e7ca05fa8600 551 * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
AnnaBridge 157:e7ca05fa8600 552 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 553 */
AnnaBridge 157:e7ca05fa8600 554 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
AnnaBridge 157:e7ca05fa8600 555 {
AnnaBridge 157:e7ca05fa8600 556 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
AnnaBridge 157:e7ca05fa8600 557 }
AnnaBridge 157:e7ca05fa8600 558
AnnaBridge 157:e7ca05fa8600 559 /**
AnnaBridge 157:e7ca05fa8600 560 * @brief Check if Synchronization or trimming error signal occurred or not
AnnaBridge 157:e7ca05fa8600 561 * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
AnnaBridge 157:e7ca05fa8600 562 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 563 */
AnnaBridge 157:e7ca05fa8600 564 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
AnnaBridge 157:e7ca05fa8600 565 {
AnnaBridge 157:e7ca05fa8600 566 return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
AnnaBridge 157:e7ca05fa8600 567 }
AnnaBridge 157:e7ca05fa8600 568
AnnaBridge 157:e7ca05fa8600 569 /**
AnnaBridge 157:e7ca05fa8600 570 * @brief Check if Expected SYNC signal occurred or not
AnnaBridge 157:e7ca05fa8600 571 * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
AnnaBridge 157:e7ca05fa8600 572 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 573 */
AnnaBridge 157:e7ca05fa8600 574 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
AnnaBridge 157:e7ca05fa8600 575 {
AnnaBridge 157:e7ca05fa8600 576 return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
AnnaBridge 157:e7ca05fa8600 577 }
AnnaBridge 157:e7ca05fa8600 578
AnnaBridge 157:e7ca05fa8600 579 /**
AnnaBridge 157:e7ca05fa8600 580 * @brief Check if SYNC error signal occurred or not
AnnaBridge 157:e7ca05fa8600 581 * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
AnnaBridge 157:e7ca05fa8600 582 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 583 */
AnnaBridge 157:e7ca05fa8600 584 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
AnnaBridge 157:e7ca05fa8600 585 {
AnnaBridge 157:e7ca05fa8600 586 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
AnnaBridge 157:e7ca05fa8600 587 }
AnnaBridge 157:e7ca05fa8600 588
AnnaBridge 157:e7ca05fa8600 589 /**
AnnaBridge 157:e7ca05fa8600 590 * @brief Check if SYNC missed error signal occurred or not
AnnaBridge 157:e7ca05fa8600 591 * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
AnnaBridge 157:e7ca05fa8600 592 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 593 */
AnnaBridge 157:e7ca05fa8600 594 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
AnnaBridge 157:e7ca05fa8600 595 {
AnnaBridge 157:e7ca05fa8600 596 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
AnnaBridge 157:e7ca05fa8600 597 }
AnnaBridge 157:e7ca05fa8600 598
AnnaBridge 157:e7ca05fa8600 599 /**
AnnaBridge 157:e7ca05fa8600 600 * @brief Check if Trimming overflow or underflow occurred or not
AnnaBridge 157:e7ca05fa8600 601 * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
AnnaBridge 157:e7ca05fa8600 602 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 603 */
AnnaBridge 157:e7ca05fa8600 604 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
AnnaBridge 157:e7ca05fa8600 605 {
AnnaBridge 157:e7ca05fa8600 606 return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
AnnaBridge 157:e7ca05fa8600 607 }
AnnaBridge 157:e7ca05fa8600 608
AnnaBridge 157:e7ca05fa8600 609 /**
AnnaBridge 157:e7ca05fa8600 610 * @brief Clear the SYNC event OK flag
AnnaBridge 157:e7ca05fa8600 611 * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
AnnaBridge 157:e7ca05fa8600 612 * @retval None
AnnaBridge 157:e7ca05fa8600 613 */
AnnaBridge 157:e7ca05fa8600 614 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
AnnaBridge 157:e7ca05fa8600 615 {
AnnaBridge 157:e7ca05fa8600 616 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
AnnaBridge 157:e7ca05fa8600 617 }
AnnaBridge 157:e7ca05fa8600 618
AnnaBridge 157:e7ca05fa8600 619 /**
AnnaBridge 157:e7ca05fa8600 620 * @brief Clear the SYNC warning flag
AnnaBridge 157:e7ca05fa8600 621 * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
AnnaBridge 157:e7ca05fa8600 622 * @retval None
AnnaBridge 157:e7ca05fa8600 623 */
AnnaBridge 157:e7ca05fa8600 624 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
AnnaBridge 157:e7ca05fa8600 625 {
AnnaBridge 157:e7ca05fa8600 626 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
AnnaBridge 157:e7ca05fa8600 627 }
AnnaBridge 157:e7ca05fa8600 628
AnnaBridge 157:e7ca05fa8600 629 /**
AnnaBridge 157:e7ca05fa8600 630 * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
AnnaBridge 157:e7ca05fa8600 631 * the ERR flag
AnnaBridge 157:e7ca05fa8600 632 * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
AnnaBridge 157:e7ca05fa8600 633 * @retval None
AnnaBridge 157:e7ca05fa8600 634 */
AnnaBridge 157:e7ca05fa8600 635 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
AnnaBridge 157:e7ca05fa8600 636 {
AnnaBridge 157:e7ca05fa8600 637 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
AnnaBridge 157:e7ca05fa8600 638 }
AnnaBridge 157:e7ca05fa8600 639
AnnaBridge 157:e7ca05fa8600 640 /**
AnnaBridge 157:e7ca05fa8600 641 * @brief Clear Expected SYNC flag
AnnaBridge 157:e7ca05fa8600 642 * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
AnnaBridge 157:e7ca05fa8600 643 * @retval None
AnnaBridge 157:e7ca05fa8600 644 */
AnnaBridge 157:e7ca05fa8600 645 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
AnnaBridge 157:e7ca05fa8600 646 {
AnnaBridge 157:e7ca05fa8600 647 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
AnnaBridge 157:e7ca05fa8600 648 }
AnnaBridge 157:e7ca05fa8600 649
AnnaBridge 157:e7ca05fa8600 650 /**
AnnaBridge 157:e7ca05fa8600 651 * @}
AnnaBridge 157:e7ca05fa8600 652 */
AnnaBridge 157:e7ca05fa8600 653
AnnaBridge 157:e7ca05fa8600 654 /** @defgroup CRS_LL_EF_IT_Management IT_Management
AnnaBridge 157:e7ca05fa8600 655 * @{
AnnaBridge 157:e7ca05fa8600 656 */
AnnaBridge 157:e7ca05fa8600 657
AnnaBridge 157:e7ca05fa8600 658 /**
AnnaBridge 157:e7ca05fa8600 659 * @brief Enable SYNC event OK interrupt
AnnaBridge 157:e7ca05fa8600 660 * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
AnnaBridge 157:e7ca05fa8600 661 * @retval None
AnnaBridge 157:e7ca05fa8600 662 */
AnnaBridge 157:e7ca05fa8600 663 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
AnnaBridge 157:e7ca05fa8600 664 {
AnnaBridge 157:e7ca05fa8600 665 SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
AnnaBridge 157:e7ca05fa8600 666 }
AnnaBridge 157:e7ca05fa8600 667
AnnaBridge 157:e7ca05fa8600 668 /**
AnnaBridge 157:e7ca05fa8600 669 * @brief Disable SYNC event OK interrupt
AnnaBridge 157:e7ca05fa8600 670 * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
AnnaBridge 157:e7ca05fa8600 671 * @retval None
AnnaBridge 157:e7ca05fa8600 672 */
AnnaBridge 157:e7ca05fa8600 673 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
AnnaBridge 157:e7ca05fa8600 674 {
AnnaBridge 157:e7ca05fa8600 675 CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
AnnaBridge 157:e7ca05fa8600 676 }
AnnaBridge 157:e7ca05fa8600 677
AnnaBridge 157:e7ca05fa8600 678 /**
AnnaBridge 157:e7ca05fa8600 679 * @brief Check if SYNC event OK interrupt is enabled or not
AnnaBridge 157:e7ca05fa8600 680 * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
AnnaBridge 157:e7ca05fa8600 681 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 682 */
AnnaBridge 157:e7ca05fa8600 683 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
AnnaBridge 157:e7ca05fa8600 684 {
AnnaBridge 157:e7ca05fa8600 685 return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
AnnaBridge 157:e7ca05fa8600 686 }
AnnaBridge 157:e7ca05fa8600 687
AnnaBridge 157:e7ca05fa8600 688 /**
AnnaBridge 157:e7ca05fa8600 689 * @brief Enable SYNC warning interrupt
AnnaBridge 157:e7ca05fa8600 690 * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
AnnaBridge 157:e7ca05fa8600 691 * @retval None
AnnaBridge 157:e7ca05fa8600 692 */
AnnaBridge 157:e7ca05fa8600 693 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
AnnaBridge 157:e7ca05fa8600 694 {
AnnaBridge 157:e7ca05fa8600 695 SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
AnnaBridge 157:e7ca05fa8600 696 }
AnnaBridge 157:e7ca05fa8600 697
AnnaBridge 157:e7ca05fa8600 698 /**
AnnaBridge 157:e7ca05fa8600 699 * @brief Disable SYNC warning interrupt
AnnaBridge 157:e7ca05fa8600 700 * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
AnnaBridge 157:e7ca05fa8600 701 * @retval None
AnnaBridge 157:e7ca05fa8600 702 */
AnnaBridge 157:e7ca05fa8600 703 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
AnnaBridge 157:e7ca05fa8600 704 {
AnnaBridge 157:e7ca05fa8600 705 CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
AnnaBridge 157:e7ca05fa8600 706 }
AnnaBridge 157:e7ca05fa8600 707
AnnaBridge 157:e7ca05fa8600 708 /**
AnnaBridge 157:e7ca05fa8600 709 * @brief Check if SYNC warning interrupt is enabled or not
AnnaBridge 157:e7ca05fa8600 710 * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
AnnaBridge 157:e7ca05fa8600 711 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 712 */
AnnaBridge 157:e7ca05fa8600 713 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
AnnaBridge 157:e7ca05fa8600 714 {
AnnaBridge 157:e7ca05fa8600 715 return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
AnnaBridge 157:e7ca05fa8600 716 }
AnnaBridge 157:e7ca05fa8600 717
AnnaBridge 157:e7ca05fa8600 718 /**
AnnaBridge 157:e7ca05fa8600 719 * @brief Enable Synchronization or trimming error interrupt
AnnaBridge 157:e7ca05fa8600 720 * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
AnnaBridge 157:e7ca05fa8600 721 * @retval None
AnnaBridge 157:e7ca05fa8600 722 */
AnnaBridge 157:e7ca05fa8600 723 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
AnnaBridge 157:e7ca05fa8600 724 {
AnnaBridge 157:e7ca05fa8600 725 SET_BIT(CRS->CR, CRS_CR_ERRIE);
AnnaBridge 157:e7ca05fa8600 726 }
AnnaBridge 157:e7ca05fa8600 727
AnnaBridge 157:e7ca05fa8600 728 /**
AnnaBridge 157:e7ca05fa8600 729 * @brief Disable Synchronization or trimming error interrupt
AnnaBridge 157:e7ca05fa8600 730 * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
AnnaBridge 157:e7ca05fa8600 731 * @retval None
AnnaBridge 157:e7ca05fa8600 732 */
AnnaBridge 157:e7ca05fa8600 733 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
AnnaBridge 157:e7ca05fa8600 734 {
AnnaBridge 157:e7ca05fa8600 735 CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
AnnaBridge 157:e7ca05fa8600 736 }
AnnaBridge 157:e7ca05fa8600 737
AnnaBridge 157:e7ca05fa8600 738 /**
AnnaBridge 157:e7ca05fa8600 739 * @brief Check if Synchronization or trimming error interrupt is enabled or not
AnnaBridge 157:e7ca05fa8600 740 * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
AnnaBridge 157:e7ca05fa8600 741 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 742 */
AnnaBridge 157:e7ca05fa8600 743 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
AnnaBridge 157:e7ca05fa8600 744 {
AnnaBridge 157:e7ca05fa8600 745 return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
AnnaBridge 157:e7ca05fa8600 746 }
AnnaBridge 157:e7ca05fa8600 747
AnnaBridge 157:e7ca05fa8600 748 /**
AnnaBridge 157:e7ca05fa8600 749 * @brief Enable Expected SYNC interrupt
AnnaBridge 157:e7ca05fa8600 750 * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
AnnaBridge 157:e7ca05fa8600 751 * @retval None
AnnaBridge 157:e7ca05fa8600 752 */
AnnaBridge 157:e7ca05fa8600 753 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
AnnaBridge 157:e7ca05fa8600 754 {
AnnaBridge 157:e7ca05fa8600 755 SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
AnnaBridge 157:e7ca05fa8600 756 }
AnnaBridge 157:e7ca05fa8600 757
AnnaBridge 157:e7ca05fa8600 758 /**
AnnaBridge 157:e7ca05fa8600 759 * @brief Disable Expected SYNC interrupt
AnnaBridge 157:e7ca05fa8600 760 * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
AnnaBridge 157:e7ca05fa8600 761 * @retval None
AnnaBridge 157:e7ca05fa8600 762 */
AnnaBridge 157:e7ca05fa8600 763 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
AnnaBridge 157:e7ca05fa8600 764 {
AnnaBridge 157:e7ca05fa8600 765 CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
AnnaBridge 157:e7ca05fa8600 766 }
AnnaBridge 157:e7ca05fa8600 767
AnnaBridge 157:e7ca05fa8600 768 /**
AnnaBridge 157:e7ca05fa8600 769 * @brief Check if Expected SYNC interrupt is enabled or not
AnnaBridge 157:e7ca05fa8600 770 * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
AnnaBridge 157:e7ca05fa8600 771 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 772 */
AnnaBridge 157:e7ca05fa8600 773 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
AnnaBridge 157:e7ca05fa8600 774 {
AnnaBridge 157:e7ca05fa8600 775 return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
AnnaBridge 157:e7ca05fa8600 776 }
AnnaBridge 157:e7ca05fa8600 777
AnnaBridge 157:e7ca05fa8600 778 /**
AnnaBridge 157:e7ca05fa8600 779 * @}
AnnaBridge 157:e7ca05fa8600 780 */
AnnaBridge 157:e7ca05fa8600 781
AnnaBridge 157:e7ca05fa8600 782 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 157:e7ca05fa8600 783 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
AnnaBridge 157:e7ca05fa8600 784 * @{
AnnaBridge 157:e7ca05fa8600 785 */
AnnaBridge 157:e7ca05fa8600 786
AnnaBridge 157:e7ca05fa8600 787 ErrorStatus LL_CRS_DeInit(void);
AnnaBridge 157:e7ca05fa8600 788
AnnaBridge 157:e7ca05fa8600 789 /**
AnnaBridge 157:e7ca05fa8600 790 * @}
AnnaBridge 157:e7ca05fa8600 791 */
AnnaBridge 157:e7ca05fa8600 792 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 157:e7ca05fa8600 793
AnnaBridge 157:e7ca05fa8600 794 /**
AnnaBridge 157:e7ca05fa8600 795 * @}
AnnaBridge 157:e7ca05fa8600 796 */
AnnaBridge 157:e7ca05fa8600 797
AnnaBridge 157:e7ca05fa8600 798 /**
AnnaBridge 157:e7ca05fa8600 799 * @}
AnnaBridge 157:e7ca05fa8600 800 */
AnnaBridge 157:e7ca05fa8600 801
AnnaBridge 157:e7ca05fa8600 802 #endif /* defined(CRS) */
AnnaBridge 157:e7ca05fa8600 803
AnnaBridge 157:e7ca05fa8600 804 /**
AnnaBridge 157:e7ca05fa8600 805 * @}
AnnaBridge 157:e7ca05fa8600 806 */
AnnaBridge 157:e7ca05fa8600 807
AnnaBridge 157:e7ca05fa8600 808 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 809 }
AnnaBridge 157:e7ca05fa8600 810 #endif
AnnaBridge 157:e7ca05fa8600 811
AnnaBridge 157:e7ca05fa8600 812 #endif /* __STM32L0xx_LL_CRS_H */
AnnaBridge 157:e7ca05fa8600 813
AnnaBridge 157:e7ca05fa8600 814 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/