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TARGET_NUCLEO_L011K4/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_crs.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 09 11:14:10 2017 +0000
Revision:
157:e7ca05fa8600
Child:
167:84c0a372a020
Release 155 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 157:e7ca05fa8600 1 /**
AnnaBridge 157:e7ca05fa8600 2 ******************************************************************************
AnnaBridge 157:e7ca05fa8600 3 * @file stm32l0xx_ll_crs.h
AnnaBridge 157:e7ca05fa8600 4 * @author MCD Application Team
AnnaBridge 157:e7ca05fa8600 5 * @version V1.7.0
AnnaBridge 157:e7ca05fa8600 6 * @date 31-May-2016
AnnaBridge 157:e7ca05fa8600 7 * @brief Header file of CRS LL module.
AnnaBridge 157:e7ca05fa8600 8 ******************************************************************************
AnnaBridge 157:e7ca05fa8600 9 * @attention
AnnaBridge 157:e7ca05fa8600 10 *
AnnaBridge 157:e7ca05fa8600 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 157:e7ca05fa8600 12 *
AnnaBridge 157:e7ca05fa8600 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 157:e7ca05fa8600 14 * are permitted provided that the following conditions are met:
AnnaBridge 157:e7ca05fa8600 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 157:e7ca05fa8600 16 * this list of conditions and the following disclaimer.
AnnaBridge 157:e7ca05fa8600 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 157:e7ca05fa8600 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 157:e7ca05fa8600 19 * and/or other materials provided with the distribution.
AnnaBridge 157:e7ca05fa8600 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 157:e7ca05fa8600 21 * may be used to endorse or promote products derived from this software
AnnaBridge 157:e7ca05fa8600 22 * without specific prior written permission.
AnnaBridge 157:e7ca05fa8600 23 *
AnnaBridge 157:e7ca05fa8600 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 157:e7ca05fa8600 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 157:e7ca05fa8600 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 157:e7ca05fa8600 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 157:e7ca05fa8600 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 157:e7ca05fa8600 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 157:e7ca05fa8600 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 157:e7ca05fa8600 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 157:e7ca05fa8600 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 157:e7ca05fa8600 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 157:e7ca05fa8600 34 *
AnnaBridge 157:e7ca05fa8600 35 ******************************************************************************
AnnaBridge 157:e7ca05fa8600 36 */
AnnaBridge 157:e7ca05fa8600 37
AnnaBridge 157:e7ca05fa8600 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 157:e7ca05fa8600 39 #ifndef __STM32L0xx_LL_CRS_H
AnnaBridge 157:e7ca05fa8600 40 #define __STM32L0xx_LL_CRS_H
AnnaBridge 157:e7ca05fa8600 41
AnnaBridge 157:e7ca05fa8600 42 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 43 extern "C" {
AnnaBridge 157:e7ca05fa8600 44 #endif
AnnaBridge 157:e7ca05fa8600 45
AnnaBridge 157:e7ca05fa8600 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 47 #include "stm32l0xx.h"
AnnaBridge 157:e7ca05fa8600 48
AnnaBridge 157:e7ca05fa8600 49 /** @addtogroup STM32L0xx_LL_Driver
AnnaBridge 157:e7ca05fa8600 50 * @{
AnnaBridge 157:e7ca05fa8600 51 */
AnnaBridge 157:e7ca05fa8600 52
AnnaBridge 157:e7ca05fa8600 53 #if defined(CRS)
AnnaBridge 157:e7ca05fa8600 54
AnnaBridge 157:e7ca05fa8600 55 /** @defgroup CRS_LL CRS
AnnaBridge 157:e7ca05fa8600 56 * @{
AnnaBridge 157:e7ca05fa8600 57 */
AnnaBridge 157:e7ca05fa8600 58
AnnaBridge 157:e7ca05fa8600 59 /* Private types -------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 60 /* Private variables ---------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 61
AnnaBridge 157:e7ca05fa8600 62 /* Private constants ---------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 63 /** @defgroup CRS_LL_Private_Constants CRS Private Constants
AnnaBridge 157:e7ca05fa8600 64 * @{
AnnaBridge 157:e7ca05fa8600 65 */
AnnaBridge 157:e7ca05fa8600 66
AnnaBridge 157:e7ca05fa8600 67 /* Defines used for the bit position in the register and perform offsets*/
AnnaBridge 157:e7ca05fa8600 68 #define CRS_POSITION_TRIM (uint32_t)8U /* bit position in CR reg */
AnnaBridge 157:e7ca05fa8600 69 #define CRS_POSITION_FECAP (uint32_t)16U /* bit position in ISR reg */
AnnaBridge 157:e7ca05fa8600 70 #define CRS_POSITION_RELOAD (uint32_t)0U /* bit position in CFGR reg */
AnnaBridge 157:e7ca05fa8600 71 #define CRS_POSITION_FELIM (uint32_t)16U /* bit position in CFGR reg */
AnnaBridge 157:e7ca05fa8600 72
AnnaBridge 157:e7ca05fa8600 73
AnnaBridge 157:e7ca05fa8600 74 /**
AnnaBridge 157:e7ca05fa8600 75 * @}
AnnaBridge 157:e7ca05fa8600 76 */
AnnaBridge 157:e7ca05fa8600 77
AnnaBridge 157:e7ca05fa8600 78 /* Private macros ------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 79
AnnaBridge 157:e7ca05fa8600 80 /* Exported types ------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 81 /* Exported constants --------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 82 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
AnnaBridge 157:e7ca05fa8600 83 * @{
AnnaBridge 157:e7ca05fa8600 84 */
AnnaBridge 157:e7ca05fa8600 85
AnnaBridge 157:e7ca05fa8600 86 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge 157:e7ca05fa8600 87 * @brief Flags defines which can be used with LL_CRS_ReadReg function
AnnaBridge 157:e7ca05fa8600 88 * @{
AnnaBridge 157:e7ca05fa8600 89 */
AnnaBridge 157:e7ca05fa8600 90 #define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
AnnaBridge 157:e7ca05fa8600 91 #define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
AnnaBridge 157:e7ca05fa8600 92 #define LL_CRS_ISR_ERRF CRS_ISR_ERRF
AnnaBridge 157:e7ca05fa8600 93 #define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
AnnaBridge 157:e7ca05fa8600 94 #define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
AnnaBridge 157:e7ca05fa8600 95 #define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
AnnaBridge 157:e7ca05fa8600 96 #define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
AnnaBridge 157:e7ca05fa8600 97 /**
AnnaBridge 157:e7ca05fa8600 98 * @}
AnnaBridge 157:e7ca05fa8600 99 */
AnnaBridge 157:e7ca05fa8600 100
AnnaBridge 157:e7ca05fa8600 101 /** @defgroup CRS_LL_EC_IT IT Defines
AnnaBridge 157:e7ca05fa8600 102 * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
AnnaBridge 157:e7ca05fa8600 103 * @{
AnnaBridge 157:e7ca05fa8600 104 */
AnnaBridge 157:e7ca05fa8600 105 #define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
AnnaBridge 157:e7ca05fa8600 106 #define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
AnnaBridge 157:e7ca05fa8600 107 #define LL_CRS_CR_ERRIE CRS_CR_ERRIE
AnnaBridge 157:e7ca05fa8600 108 #define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
AnnaBridge 157:e7ca05fa8600 109 /**
AnnaBridge 157:e7ca05fa8600 110 * @}
AnnaBridge 157:e7ca05fa8600 111 */
AnnaBridge 157:e7ca05fa8600 112
AnnaBridge 157:e7ca05fa8600 113 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
AnnaBridge 157:e7ca05fa8600 114 * @{
AnnaBridge 157:e7ca05fa8600 115 */
AnnaBridge 157:e7ca05fa8600 116 #define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */
AnnaBridge 157:e7ca05fa8600 117 #define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
AnnaBridge 157:e7ca05fa8600 118 #define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
AnnaBridge 157:e7ca05fa8600 119 #define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
AnnaBridge 157:e7ca05fa8600 120 #define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
AnnaBridge 157:e7ca05fa8600 121 #define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
AnnaBridge 157:e7ca05fa8600 122 #define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
AnnaBridge 157:e7ca05fa8600 123 #define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
AnnaBridge 157:e7ca05fa8600 124 /**
AnnaBridge 157:e7ca05fa8600 125 * @}
AnnaBridge 157:e7ca05fa8600 126 */
AnnaBridge 157:e7ca05fa8600 127
AnnaBridge 157:e7ca05fa8600 128 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
AnnaBridge 157:e7ca05fa8600 129 * @{
AnnaBridge 157:e7ca05fa8600 130 */
AnnaBridge 157:e7ca05fa8600 131 #define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal soucre GPIO */
AnnaBridge 157:e7ca05fa8600 132 #define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
AnnaBridge 157:e7ca05fa8600 133 #define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
AnnaBridge 157:e7ca05fa8600 134 /**
AnnaBridge 157:e7ca05fa8600 135 * @}
AnnaBridge 157:e7ca05fa8600 136 */
AnnaBridge 157:e7ca05fa8600 137
AnnaBridge 157:e7ca05fa8600 138 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
AnnaBridge 157:e7ca05fa8600 139 * @{
AnnaBridge 157:e7ca05fa8600 140 */
AnnaBridge 157:e7ca05fa8600 141 #define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */
AnnaBridge 157:e7ca05fa8600 142 #define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
AnnaBridge 157:e7ca05fa8600 143 /**
AnnaBridge 157:e7ca05fa8600 144 * @}
AnnaBridge 157:e7ca05fa8600 145 */
AnnaBridge 157:e7ca05fa8600 146
AnnaBridge 157:e7ca05fa8600 147 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
AnnaBridge 157:e7ca05fa8600 148 * @{
AnnaBridge 157:e7ca05fa8600 149 */
AnnaBridge 157:e7ca05fa8600 150 #define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */
AnnaBridge 157:e7ca05fa8600 151 #define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
AnnaBridge 157:e7ca05fa8600 152 /**
AnnaBridge 157:e7ca05fa8600 153 * @}
AnnaBridge 157:e7ca05fa8600 154 */
AnnaBridge 157:e7ca05fa8600 155
AnnaBridge 157:e7ca05fa8600 156 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
AnnaBridge 157:e7ca05fa8600 157 * @{
AnnaBridge 157:e7ca05fa8600 158 */
AnnaBridge 157:e7ca05fa8600 159 /**
AnnaBridge 157:e7ca05fa8600 160 * @brief Reset value of the RELOAD field
AnnaBridge 157:e7ca05fa8600 161 * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
AnnaBridge 157:e7ca05fa8600 162 * and a synchronization signal frequency of 1 kHz (SOF signal from USB)
AnnaBridge 157:e7ca05fa8600 163 */
AnnaBridge 157:e7ca05fa8600 164 #define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)
AnnaBridge 157:e7ca05fa8600 165
AnnaBridge 157:e7ca05fa8600 166 /**
AnnaBridge 157:e7ca05fa8600 167 * @brief Reset value of Frequency error limit.
AnnaBridge 157:e7ca05fa8600 168 */
AnnaBridge 157:e7ca05fa8600 169 #define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)
AnnaBridge 157:e7ca05fa8600 170
AnnaBridge 157:e7ca05fa8600 171 /**
AnnaBridge 157:e7ca05fa8600 172 * @brief Reset value of the HSI48 Calibration field
AnnaBridge 157:e7ca05fa8600 173 * @note The default value is 32, which corresponds to the middle of the trimming interval.
AnnaBridge 157:e7ca05fa8600 174 * The trimming step is around 67 kHz between two consecutive TRIM steps.
AnnaBridge 157:e7ca05fa8600 175 * A higher TRIM value corresponds to a higher output frequency
AnnaBridge 157:e7ca05fa8600 176 */
AnnaBridge 157:e7ca05fa8600 177 #define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U)
AnnaBridge 157:e7ca05fa8600 178 /**
AnnaBridge 157:e7ca05fa8600 179 * @}
AnnaBridge 157:e7ca05fa8600 180 */
AnnaBridge 157:e7ca05fa8600 181
AnnaBridge 157:e7ca05fa8600 182 /**
AnnaBridge 157:e7ca05fa8600 183 * @}
AnnaBridge 157:e7ca05fa8600 184 */
AnnaBridge 157:e7ca05fa8600 185
AnnaBridge 157:e7ca05fa8600 186 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 187 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
AnnaBridge 157:e7ca05fa8600 188 * @{
AnnaBridge 157:e7ca05fa8600 189 */
AnnaBridge 157:e7ca05fa8600 190
AnnaBridge 157:e7ca05fa8600 191 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge 157:e7ca05fa8600 192 * @{
AnnaBridge 157:e7ca05fa8600 193 */
AnnaBridge 157:e7ca05fa8600 194
AnnaBridge 157:e7ca05fa8600 195 /**
AnnaBridge 157:e7ca05fa8600 196 * @brief Write a value in CRS register
AnnaBridge 157:e7ca05fa8600 197 * @param __INSTANCE__ CRS Instance
AnnaBridge 157:e7ca05fa8600 198 * @param __REG__ Register to be written
AnnaBridge 157:e7ca05fa8600 199 * @param __VALUE__ Value to be written in the register
AnnaBridge 157:e7ca05fa8600 200 * @retval None
AnnaBridge 157:e7ca05fa8600 201 */
AnnaBridge 157:e7ca05fa8600 202 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge 157:e7ca05fa8600 203
AnnaBridge 157:e7ca05fa8600 204 /**
AnnaBridge 157:e7ca05fa8600 205 * @brief Read a value in CRS register
AnnaBridge 157:e7ca05fa8600 206 * @param __INSTANCE__ CRS Instance
AnnaBridge 157:e7ca05fa8600 207 * @param __REG__ Register to be read
AnnaBridge 157:e7ca05fa8600 208 * @retval Register value
AnnaBridge 157:e7ca05fa8600 209 */
AnnaBridge 157:e7ca05fa8600 210 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge 157:e7ca05fa8600 211 /**
AnnaBridge 157:e7ca05fa8600 212 * @}
AnnaBridge 157:e7ca05fa8600 213 */
AnnaBridge 157:e7ca05fa8600 214
AnnaBridge 157:e7ca05fa8600 215 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
AnnaBridge 157:e7ca05fa8600 216 * @{
AnnaBridge 157:e7ca05fa8600 217 */
AnnaBridge 157:e7ca05fa8600 218
AnnaBridge 157:e7ca05fa8600 219 /**
AnnaBridge 157:e7ca05fa8600 220 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
AnnaBridge 157:e7ca05fa8600 221 * @note The RELOAD value should be selected according to the ratio between
AnnaBridge 157:e7ca05fa8600 222 * the target frequency and the frequency of the synchronization source after
AnnaBridge 157:e7ca05fa8600 223 * prescaling. It is then decreased by one in order to reach the expected
AnnaBridge 157:e7ca05fa8600 224 * synchronization on the zero value. The formula is the following:
AnnaBridge 157:e7ca05fa8600 225 * RELOAD = (fTARGET / fSYNC) -1
AnnaBridge 157:e7ca05fa8600 226 * @param __FTARGET__ Target frequency (value in Hz)
AnnaBridge 157:e7ca05fa8600 227 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
AnnaBridge 157:e7ca05fa8600 228 * @retval Reload value (in Hz)
AnnaBridge 157:e7ca05fa8600 229 */
AnnaBridge 157:e7ca05fa8600 230 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
AnnaBridge 157:e7ca05fa8600 231
AnnaBridge 157:e7ca05fa8600 232 /**
AnnaBridge 157:e7ca05fa8600 233 * @}
AnnaBridge 157:e7ca05fa8600 234 */
AnnaBridge 157:e7ca05fa8600 235
AnnaBridge 157:e7ca05fa8600 236 /**
AnnaBridge 157:e7ca05fa8600 237 * @}
AnnaBridge 157:e7ca05fa8600 238 */
AnnaBridge 157:e7ca05fa8600 239
AnnaBridge 157:e7ca05fa8600 240 /* Exported functions --------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 241 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
AnnaBridge 157:e7ca05fa8600 242 * @{
AnnaBridge 157:e7ca05fa8600 243 */
AnnaBridge 157:e7ca05fa8600 244
AnnaBridge 157:e7ca05fa8600 245 /** @defgroup CRS_LL_EF_Configuration Configuration
AnnaBridge 157:e7ca05fa8600 246 * @{
AnnaBridge 157:e7ca05fa8600 247 */
AnnaBridge 157:e7ca05fa8600 248
AnnaBridge 157:e7ca05fa8600 249 /**
AnnaBridge 157:e7ca05fa8600 250 * @brief Enable Frequency error counter
AnnaBridge 157:e7ca05fa8600 251 * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
AnnaBridge 157:e7ca05fa8600 252 * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
AnnaBridge 157:e7ca05fa8600 253 * @retval None
AnnaBridge 157:e7ca05fa8600 254 */
AnnaBridge 157:e7ca05fa8600 255 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
AnnaBridge 157:e7ca05fa8600 256 {
AnnaBridge 157:e7ca05fa8600 257 SET_BIT(CRS->CR, CRS_CR_CEN);
AnnaBridge 157:e7ca05fa8600 258 }
AnnaBridge 157:e7ca05fa8600 259
AnnaBridge 157:e7ca05fa8600 260 /**
AnnaBridge 157:e7ca05fa8600 261 * @brief Disable Frequency error counter
AnnaBridge 157:e7ca05fa8600 262 * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
AnnaBridge 157:e7ca05fa8600 263 * @retval None
AnnaBridge 157:e7ca05fa8600 264 */
AnnaBridge 157:e7ca05fa8600 265 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
AnnaBridge 157:e7ca05fa8600 266 {
AnnaBridge 157:e7ca05fa8600 267 CLEAR_BIT(CRS->CR, CRS_CR_CEN);
AnnaBridge 157:e7ca05fa8600 268 }
AnnaBridge 157:e7ca05fa8600 269
AnnaBridge 157:e7ca05fa8600 270 /**
AnnaBridge 157:e7ca05fa8600 271 * @brief Check if Frequency error counter is enabled or not
AnnaBridge 157:e7ca05fa8600 272 * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
AnnaBridge 157:e7ca05fa8600 273 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 274 */
AnnaBridge 157:e7ca05fa8600 275 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
AnnaBridge 157:e7ca05fa8600 276 {
AnnaBridge 157:e7ca05fa8600 277 return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
AnnaBridge 157:e7ca05fa8600 278 }
AnnaBridge 157:e7ca05fa8600 279
AnnaBridge 157:e7ca05fa8600 280 /**
AnnaBridge 157:e7ca05fa8600 281 * @brief Enable Automatic trimming counter
AnnaBridge 157:e7ca05fa8600 282 * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
AnnaBridge 157:e7ca05fa8600 283 * @retval None
AnnaBridge 157:e7ca05fa8600 284 */
AnnaBridge 157:e7ca05fa8600 285 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
AnnaBridge 157:e7ca05fa8600 286 {
AnnaBridge 157:e7ca05fa8600 287 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
AnnaBridge 157:e7ca05fa8600 288 }
AnnaBridge 157:e7ca05fa8600 289
AnnaBridge 157:e7ca05fa8600 290 /**
AnnaBridge 157:e7ca05fa8600 291 * @brief Disable Automatic trimming counter
AnnaBridge 157:e7ca05fa8600 292 * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
AnnaBridge 157:e7ca05fa8600 293 * @retval None
AnnaBridge 157:e7ca05fa8600 294 */
AnnaBridge 157:e7ca05fa8600 295 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
AnnaBridge 157:e7ca05fa8600 296 {
AnnaBridge 157:e7ca05fa8600 297 CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
AnnaBridge 157:e7ca05fa8600 298 }
AnnaBridge 157:e7ca05fa8600 299
AnnaBridge 157:e7ca05fa8600 300 /**
AnnaBridge 157:e7ca05fa8600 301 * @brief Check if Automatic trimming is enabled or not
AnnaBridge 157:e7ca05fa8600 302 * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
AnnaBridge 157:e7ca05fa8600 303 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 304 */
AnnaBridge 157:e7ca05fa8600 305 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
AnnaBridge 157:e7ca05fa8600 306 {
AnnaBridge 157:e7ca05fa8600 307 return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
AnnaBridge 157:e7ca05fa8600 308 }
AnnaBridge 157:e7ca05fa8600 309
AnnaBridge 157:e7ca05fa8600 310 /**
AnnaBridge 157:e7ca05fa8600 311 * @brief Set HSI48 oscillator smooth trimming
AnnaBridge 157:e7ca05fa8600 312 * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
AnnaBridge 157:e7ca05fa8600 313 * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
AnnaBridge 157:e7ca05fa8600 314 * @param Value a number between Min_Data = 0 and Max_Data = 63
AnnaBridge 157:e7ca05fa8600 315 * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
AnnaBridge 157:e7ca05fa8600 316 * @retval None
AnnaBridge 157:e7ca05fa8600 317 */
AnnaBridge 157:e7ca05fa8600 318 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
AnnaBridge 157:e7ca05fa8600 319 {
AnnaBridge 157:e7ca05fa8600 320 MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM);
AnnaBridge 157:e7ca05fa8600 321 }
AnnaBridge 157:e7ca05fa8600 322
AnnaBridge 157:e7ca05fa8600 323 /**
AnnaBridge 157:e7ca05fa8600 324 * @brief Get HSI48 oscillator smooth trimming
AnnaBridge 157:e7ca05fa8600 325 * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
AnnaBridge 157:e7ca05fa8600 326 * @retval a number between Min_Data = 0 and Max_Data = 63
AnnaBridge 157:e7ca05fa8600 327 */
AnnaBridge 157:e7ca05fa8600 328 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
AnnaBridge 157:e7ca05fa8600 329 {
AnnaBridge 157:e7ca05fa8600 330 return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM);
AnnaBridge 157:e7ca05fa8600 331 }
AnnaBridge 157:e7ca05fa8600 332
AnnaBridge 157:e7ca05fa8600 333 /**
AnnaBridge 157:e7ca05fa8600 334 * @brief Set counter reload value
AnnaBridge 157:e7ca05fa8600 335 * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
AnnaBridge 157:e7ca05fa8600 336 * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
AnnaBridge 157:e7ca05fa8600 337 * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
AnnaBridge 157:e7ca05fa8600 338 * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
AnnaBridge 157:e7ca05fa8600 339 * @retval None
AnnaBridge 157:e7ca05fa8600 340 */
AnnaBridge 157:e7ca05fa8600 341 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
AnnaBridge 157:e7ca05fa8600 342 {
AnnaBridge 157:e7ca05fa8600 343 MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
AnnaBridge 157:e7ca05fa8600 344 }
AnnaBridge 157:e7ca05fa8600 345
AnnaBridge 157:e7ca05fa8600 346 /**
AnnaBridge 157:e7ca05fa8600 347 * @brief Get counter reload value
AnnaBridge 157:e7ca05fa8600 348 * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
AnnaBridge 157:e7ca05fa8600 349 * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
AnnaBridge 157:e7ca05fa8600 350 */
AnnaBridge 157:e7ca05fa8600 351 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
AnnaBridge 157:e7ca05fa8600 352 {
AnnaBridge 157:e7ca05fa8600 353 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
AnnaBridge 157:e7ca05fa8600 354 }
AnnaBridge 157:e7ca05fa8600 355
AnnaBridge 157:e7ca05fa8600 356 /**
AnnaBridge 157:e7ca05fa8600 357 * @brief Set frequency error limit
AnnaBridge 157:e7ca05fa8600 358 * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
AnnaBridge 157:e7ca05fa8600 359 * @param Value a number between Min_Data = 0 and Max_Data = 255
AnnaBridge 157:e7ca05fa8600 360 * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
AnnaBridge 157:e7ca05fa8600 361 * @retval None
AnnaBridge 157:e7ca05fa8600 362 */
AnnaBridge 157:e7ca05fa8600 363 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
AnnaBridge 157:e7ca05fa8600 364 {
AnnaBridge 157:e7ca05fa8600 365 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM);
AnnaBridge 157:e7ca05fa8600 366 }
AnnaBridge 157:e7ca05fa8600 367
AnnaBridge 157:e7ca05fa8600 368 /**
AnnaBridge 157:e7ca05fa8600 369 * @brief Get frequency error limit
AnnaBridge 157:e7ca05fa8600 370 * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
AnnaBridge 157:e7ca05fa8600 371 * @retval A number between Min_Data = 0 and Max_Data = 255
AnnaBridge 157:e7ca05fa8600 372 */
AnnaBridge 157:e7ca05fa8600 373 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
AnnaBridge 157:e7ca05fa8600 374 {
AnnaBridge 157:e7ca05fa8600 375 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM);
AnnaBridge 157:e7ca05fa8600 376 }
AnnaBridge 157:e7ca05fa8600 377
AnnaBridge 157:e7ca05fa8600 378 /**
AnnaBridge 157:e7ca05fa8600 379 * @brief Set division factor for SYNC signal
AnnaBridge 157:e7ca05fa8600 380 * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
AnnaBridge 157:e7ca05fa8600 381 * @param Divider This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 382 * @arg @ref LL_CRS_SYNC_DIV_1
AnnaBridge 157:e7ca05fa8600 383 * @arg @ref LL_CRS_SYNC_DIV_2
AnnaBridge 157:e7ca05fa8600 384 * @arg @ref LL_CRS_SYNC_DIV_4
AnnaBridge 157:e7ca05fa8600 385 * @arg @ref LL_CRS_SYNC_DIV_8
AnnaBridge 157:e7ca05fa8600 386 * @arg @ref LL_CRS_SYNC_DIV_16
AnnaBridge 157:e7ca05fa8600 387 * @arg @ref LL_CRS_SYNC_DIV_32
AnnaBridge 157:e7ca05fa8600 388 * @arg @ref LL_CRS_SYNC_DIV_64
AnnaBridge 157:e7ca05fa8600 389 * @arg @ref LL_CRS_SYNC_DIV_128
AnnaBridge 157:e7ca05fa8600 390 * @retval None
AnnaBridge 157:e7ca05fa8600 391 */
AnnaBridge 157:e7ca05fa8600 392 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
AnnaBridge 157:e7ca05fa8600 393 {
AnnaBridge 157:e7ca05fa8600 394 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
AnnaBridge 157:e7ca05fa8600 395 }
AnnaBridge 157:e7ca05fa8600 396
AnnaBridge 157:e7ca05fa8600 397 /**
AnnaBridge 157:e7ca05fa8600 398 * @brief Get division factor for SYNC signal
AnnaBridge 157:e7ca05fa8600 399 * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
AnnaBridge 157:e7ca05fa8600 400 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 401 * @arg @ref LL_CRS_SYNC_DIV_1
AnnaBridge 157:e7ca05fa8600 402 * @arg @ref LL_CRS_SYNC_DIV_2
AnnaBridge 157:e7ca05fa8600 403 * @arg @ref LL_CRS_SYNC_DIV_4
AnnaBridge 157:e7ca05fa8600 404 * @arg @ref LL_CRS_SYNC_DIV_8
AnnaBridge 157:e7ca05fa8600 405 * @arg @ref LL_CRS_SYNC_DIV_16
AnnaBridge 157:e7ca05fa8600 406 * @arg @ref LL_CRS_SYNC_DIV_32
AnnaBridge 157:e7ca05fa8600 407 * @arg @ref LL_CRS_SYNC_DIV_64
AnnaBridge 157:e7ca05fa8600 408 * @arg @ref LL_CRS_SYNC_DIV_128
AnnaBridge 157:e7ca05fa8600 409 */
AnnaBridge 157:e7ca05fa8600 410 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
AnnaBridge 157:e7ca05fa8600 411 {
AnnaBridge 157:e7ca05fa8600 412 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
AnnaBridge 157:e7ca05fa8600 413 }
AnnaBridge 157:e7ca05fa8600 414
AnnaBridge 157:e7ca05fa8600 415 /**
AnnaBridge 157:e7ca05fa8600 416 * @brief Set SYNC signal source
AnnaBridge 157:e7ca05fa8600 417 * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
AnnaBridge 157:e7ca05fa8600 418 * @param Source This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 419 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
AnnaBridge 157:e7ca05fa8600 420 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
AnnaBridge 157:e7ca05fa8600 421 * @arg @ref LL_CRS_SYNC_SOURCE_USB
AnnaBridge 157:e7ca05fa8600 422 * @retval None
AnnaBridge 157:e7ca05fa8600 423 */
AnnaBridge 157:e7ca05fa8600 424 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
AnnaBridge 157:e7ca05fa8600 425 {
AnnaBridge 157:e7ca05fa8600 426 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
AnnaBridge 157:e7ca05fa8600 427 }
AnnaBridge 157:e7ca05fa8600 428
AnnaBridge 157:e7ca05fa8600 429 /**
AnnaBridge 157:e7ca05fa8600 430 * @brief Get SYNC signal source
AnnaBridge 157:e7ca05fa8600 431 * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
AnnaBridge 157:e7ca05fa8600 432 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 433 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
AnnaBridge 157:e7ca05fa8600 434 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
AnnaBridge 157:e7ca05fa8600 435 * @arg @ref LL_CRS_SYNC_SOURCE_USB
AnnaBridge 157:e7ca05fa8600 436 */
AnnaBridge 157:e7ca05fa8600 437 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
AnnaBridge 157:e7ca05fa8600 438 {
AnnaBridge 157:e7ca05fa8600 439 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
AnnaBridge 157:e7ca05fa8600 440 }
AnnaBridge 157:e7ca05fa8600 441
AnnaBridge 157:e7ca05fa8600 442 /**
AnnaBridge 157:e7ca05fa8600 443 * @brief Set input polarity for the SYNC signal source
AnnaBridge 157:e7ca05fa8600 444 * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
AnnaBridge 157:e7ca05fa8600 445 * @param Polarity This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 446 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
AnnaBridge 157:e7ca05fa8600 447 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
AnnaBridge 157:e7ca05fa8600 448 * @retval None
AnnaBridge 157:e7ca05fa8600 449 */
AnnaBridge 157:e7ca05fa8600 450 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
AnnaBridge 157:e7ca05fa8600 451 {
AnnaBridge 157:e7ca05fa8600 452 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
AnnaBridge 157:e7ca05fa8600 453 }
AnnaBridge 157:e7ca05fa8600 454
AnnaBridge 157:e7ca05fa8600 455 /**
AnnaBridge 157:e7ca05fa8600 456 * @brief Get input polarity for the SYNC signal source
AnnaBridge 157:e7ca05fa8600 457 * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
AnnaBridge 157:e7ca05fa8600 458 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 459 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
AnnaBridge 157:e7ca05fa8600 460 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
AnnaBridge 157:e7ca05fa8600 461 */
AnnaBridge 157:e7ca05fa8600 462 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
AnnaBridge 157:e7ca05fa8600 463 {
AnnaBridge 157:e7ca05fa8600 464 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
AnnaBridge 157:e7ca05fa8600 465 }
AnnaBridge 157:e7ca05fa8600 466
AnnaBridge 157:e7ca05fa8600 467 /**
AnnaBridge 157:e7ca05fa8600 468 * @brief Configure CRS for the synchronization
AnnaBridge 157:e7ca05fa8600 469 * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
AnnaBridge 157:e7ca05fa8600 470 * CFGR RELOAD LL_CRS_ConfigSynchronization\n
AnnaBridge 157:e7ca05fa8600 471 * CFGR FELIM LL_CRS_ConfigSynchronization\n
AnnaBridge 157:e7ca05fa8600 472 * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
AnnaBridge 157:e7ca05fa8600 473 * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
AnnaBridge 157:e7ca05fa8600 474 * CFGR SYNCPOL LL_CRS_ConfigSynchronization
AnnaBridge 157:e7ca05fa8600 475 * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
AnnaBridge 157:e7ca05fa8600 476 * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
AnnaBridge 157:e7ca05fa8600 477 * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
AnnaBridge 157:e7ca05fa8600 478 * @param Settings This parameter can be a combination of the following values:
AnnaBridge 157:e7ca05fa8600 479 * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
AnnaBridge 157:e7ca05fa8600 480 * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
AnnaBridge 157:e7ca05fa8600 481 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
AnnaBridge 157:e7ca05fa8600 482 * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
AnnaBridge 157:e7ca05fa8600 483 * @retval None
AnnaBridge 157:e7ca05fa8600 484 */
AnnaBridge 157:e7ca05fa8600 485 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
AnnaBridge 157:e7ca05fa8600 486 {
AnnaBridge 157:e7ca05fa8600 487 MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
AnnaBridge 157:e7ca05fa8600 488 MODIFY_REG(CRS->CFGR,
AnnaBridge 157:e7ca05fa8600 489 CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
AnnaBridge 157:e7ca05fa8600 490 ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings);
AnnaBridge 157:e7ca05fa8600 491 }
AnnaBridge 157:e7ca05fa8600 492
AnnaBridge 157:e7ca05fa8600 493 /**
AnnaBridge 157:e7ca05fa8600 494 * @}
AnnaBridge 157:e7ca05fa8600 495 */
AnnaBridge 157:e7ca05fa8600 496
AnnaBridge 157:e7ca05fa8600 497 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
AnnaBridge 157:e7ca05fa8600 498 * @{
AnnaBridge 157:e7ca05fa8600 499 */
AnnaBridge 157:e7ca05fa8600 500
AnnaBridge 157:e7ca05fa8600 501 /**
AnnaBridge 157:e7ca05fa8600 502 * @brief Generate software SYNC event
AnnaBridge 157:e7ca05fa8600 503 * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
AnnaBridge 157:e7ca05fa8600 504 * @retval None
AnnaBridge 157:e7ca05fa8600 505 */
AnnaBridge 157:e7ca05fa8600 506 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
AnnaBridge 157:e7ca05fa8600 507 {
AnnaBridge 157:e7ca05fa8600 508 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
AnnaBridge 157:e7ca05fa8600 509 }
AnnaBridge 157:e7ca05fa8600 510
AnnaBridge 157:e7ca05fa8600 511 /**
AnnaBridge 157:e7ca05fa8600 512 * @brief Get the frequency error direction latched in the time of the last
AnnaBridge 157:e7ca05fa8600 513 * SYNC event
AnnaBridge 157:e7ca05fa8600 514 * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
AnnaBridge 157:e7ca05fa8600 515 * @retval Returned value can be one of the following values:
AnnaBridge 157:e7ca05fa8600 516 * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
AnnaBridge 157:e7ca05fa8600 517 * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
AnnaBridge 157:e7ca05fa8600 518 */
AnnaBridge 157:e7ca05fa8600 519 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
AnnaBridge 157:e7ca05fa8600 520 {
AnnaBridge 157:e7ca05fa8600 521 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
AnnaBridge 157:e7ca05fa8600 522 }
AnnaBridge 157:e7ca05fa8600 523
AnnaBridge 157:e7ca05fa8600 524 /**
AnnaBridge 157:e7ca05fa8600 525 * @brief Get the frequency error counter value latched in the time of the last SYNC event
AnnaBridge 157:e7ca05fa8600 526 * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
AnnaBridge 157:e7ca05fa8600 527 * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
AnnaBridge 157:e7ca05fa8600 528 */
AnnaBridge 157:e7ca05fa8600 529 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
AnnaBridge 157:e7ca05fa8600 530 {
AnnaBridge 157:e7ca05fa8600 531 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP);
AnnaBridge 157:e7ca05fa8600 532 }
AnnaBridge 157:e7ca05fa8600 533
AnnaBridge 157:e7ca05fa8600 534 /**
AnnaBridge 157:e7ca05fa8600 535 * @}
AnnaBridge 157:e7ca05fa8600 536 */
AnnaBridge 157:e7ca05fa8600 537
AnnaBridge 157:e7ca05fa8600 538 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
AnnaBridge 157:e7ca05fa8600 539 * @{
AnnaBridge 157:e7ca05fa8600 540 */
AnnaBridge 157:e7ca05fa8600 541
AnnaBridge 157:e7ca05fa8600 542 /**
AnnaBridge 157:e7ca05fa8600 543 * @brief Check if SYNC event OK signal occurred or not
AnnaBridge 157:e7ca05fa8600 544 * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
AnnaBridge 157:e7ca05fa8600 545 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 546 */
AnnaBridge 157:e7ca05fa8600 547 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
AnnaBridge 157:e7ca05fa8600 548 {
AnnaBridge 157:e7ca05fa8600 549 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
AnnaBridge 157:e7ca05fa8600 550 }
AnnaBridge 157:e7ca05fa8600 551
AnnaBridge 157:e7ca05fa8600 552 /**
AnnaBridge 157:e7ca05fa8600 553 * @brief Check if SYNC warning signal occurred or not
AnnaBridge 157:e7ca05fa8600 554 * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
AnnaBridge 157:e7ca05fa8600 555 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 556 */
AnnaBridge 157:e7ca05fa8600 557 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
AnnaBridge 157:e7ca05fa8600 558 {
AnnaBridge 157:e7ca05fa8600 559 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
AnnaBridge 157:e7ca05fa8600 560 }
AnnaBridge 157:e7ca05fa8600 561
AnnaBridge 157:e7ca05fa8600 562 /**
AnnaBridge 157:e7ca05fa8600 563 * @brief Check if Synchronization or trimming error signal occurred or not
AnnaBridge 157:e7ca05fa8600 564 * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
AnnaBridge 157:e7ca05fa8600 565 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 566 */
AnnaBridge 157:e7ca05fa8600 567 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
AnnaBridge 157:e7ca05fa8600 568 {
AnnaBridge 157:e7ca05fa8600 569 return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
AnnaBridge 157:e7ca05fa8600 570 }
AnnaBridge 157:e7ca05fa8600 571
AnnaBridge 157:e7ca05fa8600 572 /**
AnnaBridge 157:e7ca05fa8600 573 * @brief Check if Expected SYNC signal occurred or not
AnnaBridge 157:e7ca05fa8600 574 * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
AnnaBridge 157:e7ca05fa8600 575 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 576 */
AnnaBridge 157:e7ca05fa8600 577 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
AnnaBridge 157:e7ca05fa8600 578 {
AnnaBridge 157:e7ca05fa8600 579 return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
AnnaBridge 157:e7ca05fa8600 580 }
AnnaBridge 157:e7ca05fa8600 581
AnnaBridge 157:e7ca05fa8600 582 /**
AnnaBridge 157:e7ca05fa8600 583 * @brief Check if SYNC error signal occurred or not
AnnaBridge 157:e7ca05fa8600 584 * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
AnnaBridge 157:e7ca05fa8600 585 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 586 */
AnnaBridge 157:e7ca05fa8600 587 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
AnnaBridge 157:e7ca05fa8600 588 {
AnnaBridge 157:e7ca05fa8600 589 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
AnnaBridge 157:e7ca05fa8600 590 }
AnnaBridge 157:e7ca05fa8600 591
AnnaBridge 157:e7ca05fa8600 592 /**
AnnaBridge 157:e7ca05fa8600 593 * @brief Check if SYNC missed error signal occurred or not
AnnaBridge 157:e7ca05fa8600 594 * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
AnnaBridge 157:e7ca05fa8600 595 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 596 */
AnnaBridge 157:e7ca05fa8600 597 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
AnnaBridge 157:e7ca05fa8600 598 {
AnnaBridge 157:e7ca05fa8600 599 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
AnnaBridge 157:e7ca05fa8600 600 }
AnnaBridge 157:e7ca05fa8600 601
AnnaBridge 157:e7ca05fa8600 602 /**
AnnaBridge 157:e7ca05fa8600 603 * @brief Check if Trimming overflow or underflow occurred or not
AnnaBridge 157:e7ca05fa8600 604 * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
AnnaBridge 157:e7ca05fa8600 605 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 606 */
AnnaBridge 157:e7ca05fa8600 607 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
AnnaBridge 157:e7ca05fa8600 608 {
AnnaBridge 157:e7ca05fa8600 609 return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
AnnaBridge 157:e7ca05fa8600 610 }
AnnaBridge 157:e7ca05fa8600 611
AnnaBridge 157:e7ca05fa8600 612 /**
AnnaBridge 157:e7ca05fa8600 613 * @brief Clear the SYNC event OK flag
AnnaBridge 157:e7ca05fa8600 614 * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
AnnaBridge 157:e7ca05fa8600 615 * @retval None
AnnaBridge 157:e7ca05fa8600 616 */
AnnaBridge 157:e7ca05fa8600 617 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
AnnaBridge 157:e7ca05fa8600 618 {
AnnaBridge 157:e7ca05fa8600 619 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
AnnaBridge 157:e7ca05fa8600 620 }
AnnaBridge 157:e7ca05fa8600 621
AnnaBridge 157:e7ca05fa8600 622 /**
AnnaBridge 157:e7ca05fa8600 623 * @brief Clear the SYNC warning flag
AnnaBridge 157:e7ca05fa8600 624 * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
AnnaBridge 157:e7ca05fa8600 625 * @retval None
AnnaBridge 157:e7ca05fa8600 626 */
AnnaBridge 157:e7ca05fa8600 627 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
AnnaBridge 157:e7ca05fa8600 628 {
AnnaBridge 157:e7ca05fa8600 629 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
AnnaBridge 157:e7ca05fa8600 630 }
AnnaBridge 157:e7ca05fa8600 631
AnnaBridge 157:e7ca05fa8600 632 /**
AnnaBridge 157:e7ca05fa8600 633 * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
AnnaBridge 157:e7ca05fa8600 634 * the ERR flag
AnnaBridge 157:e7ca05fa8600 635 * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
AnnaBridge 157:e7ca05fa8600 636 * @retval None
AnnaBridge 157:e7ca05fa8600 637 */
AnnaBridge 157:e7ca05fa8600 638 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
AnnaBridge 157:e7ca05fa8600 639 {
AnnaBridge 157:e7ca05fa8600 640 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
AnnaBridge 157:e7ca05fa8600 641 }
AnnaBridge 157:e7ca05fa8600 642
AnnaBridge 157:e7ca05fa8600 643 /**
AnnaBridge 157:e7ca05fa8600 644 * @brief Clear Expected SYNC flag
AnnaBridge 157:e7ca05fa8600 645 * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
AnnaBridge 157:e7ca05fa8600 646 * @retval None
AnnaBridge 157:e7ca05fa8600 647 */
AnnaBridge 157:e7ca05fa8600 648 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
AnnaBridge 157:e7ca05fa8600 649 {
AnnaBridge 157:e7ca05fa8600 650 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
AnnaBridge 157:e7ca05fa8600 651 }
AnnaBridge 157:e7ca05fa8600 652
AnnaBridge 157:e7ca05fa8600 653 /**
AnnaBridge 157:e7ca05fa8600 654 * @}
AnnaBridge 157:e7ca05fa8600 655 */
AnnaBridge 157:e7ca05fa8600 656
AnnaBridge 157:e7ca05fa8600 657 /** @defgroup CRS_LL_EF_IT_Management IT_Management
AnnaBridge 157:e7ca05fa8600 658 * @{
AnnaBridge 157:e7ca05fa8600 659 */
AnnaBridge 157:e7ca05fa8600 660
AnnaBridge 157:e7ca05fa8600 661 /**
AnnaBridge 157:e7ca05fa8600 662 * @brief Enable SYNC event OK interrupt
AnnaBridge 157:e7ca05fa8600 663 * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
AnnaBridge 157:e7ca05fa8600 664 * @retval None
AnnaBridge 157:e7ca05fa8600 665 */
AnnaBridge 157:e7ca05fa8600 666 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
AnnaBridge 157:e7ca05fa8600 667 {
AnnaBridge 157:e7ca05fa8600 668 SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
AnnaBridge 157:e7ca05fa8600 669 }
AnnaBridge 157:e7ca05fa8600 670
AnnaBridge 157:e7ca05fa8600 671 /**
AnnaBridge 157:e7ca05fa8600 672 * @brief Disable SYNC event OK interrupt
AnnaBridge 157:e7ca05fa8600 673 * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
AnnaBridge 157:e7ca05fa8600 674 * @retval None
AnnaBridge 157:e7ca05fa8600 675 */
AnnaBridge 157:e7ca05fa8600 676 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
AnnaBridge 157:e7ca05fa8600 677 {
AnnaBridge 157:e7ca05fa8600 678 CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
AnnaBridge 157:e7ca05fa8600 679 }
AnnaBridge 157:e7ca05fa8600 680
AnnaBridge 157:e7ca05fa8600 681 /**
AnnaBridge 157:e7ca05fa8600 682 * @brief Check if SYNC event OK interrupt is enabled or not
AnnaBridge 157:e7ca05fa8600 683 * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
AnnaBridge 157:e7ca05fa8600 684 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 685 */
AnnaBridge 157:e7ca05fa8600 686 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
AnnaBridge 157:e7ca05fa8600 687 {
AnnaBridge 157:e7ca05fa8600 688 return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
AnnaBridge 157:e7ca05fa8600 689 }
AnnaBridge 157:e7ca05fa8600 690
AnnaBridge 157:e7ca05fa8600 691 /**
AnnaBridge 157:e7ca05fa8600 692 * @brief Enable SYNC warning interrupt
AnnaBridge 157:e7ca05fa8600 693 * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
AnnaBridge 157:e7ca05fa8600 694 * @retval None
AnnaBridge 157:e7ca05fa8600 695 */
AnnaBridge 157:e7ca05fa8600 696 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
AnnaBridge 157:e7ca05fa8600 697 {
AnnaBridge 157:e7ca05fa8600 698 SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
AnnaBridge 157:e7ca05fa8600 699 }
AnnaBridge 157:e7ca05fa8600 700
AnnaBridge 157:e7ca05fa8600 701 /**
AnnaBridge 157:e7ca05fa8600 702 * @brief Disable SYNC warning interrupt
AnnaBridge 157:e7ca05fa8600 703 * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
AnnaBridge 157:e7ca05fa8600 704 * @retval None
AnnaBridge 157:e7ca05fa8600 705 */
AnnaBridge 157:e7ca05fa8600 706 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
AnnaBridge 157:e7ca05fa8600 707 {
AnnaBridge 157:e7ca05fa8600 708 CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
AnnaBridge 157:e7ca05fa8600 709 }
AnnaBridge 157:e7ca05fa8600 710
AnnaBridge 157:e7ca05fa8600 711 /**
AnnaBridge 157:e7ca05fa8600 712 * @brief Check if SYNC warning interrupt is enabled or not
AnnaBridge 157:e7ca05fa8600 713 * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
AnnaBridge 157:e7ca05fa8600 714 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 715 */
AnnaBridge 157:e7ca05fa8600 716 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
AnnaBridge 157:e7ca05fa8600 717 {
AnnaBridge 157:e7ca05fa8600 718 return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
AnnaBridge 157:e7ca05fa8600 719 }
AnnaBridge 157:e7ca05fa8600 720
AnnaBridge 157:e7ca05fa8600 721 /**
AnnaBridge 157:e7ca05fa8600 722 * @brief Enable Synchronization or trimming error interrupt
AnnaBridge 157:e7ca05fa8600 723 * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
AnnaBridge 157:e7ca05fa8600 724 * @retval None
AnnaBridge 157:e7ca05fa8600 725 */
AnnaBridge 157:e7ca05fa8600 726 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
AnnaBridge 157:e7ca05fa8600 727 {
AnnaBridge 157:e7ca05fa8600 728 SET_BIT(CRS->CR, CRS_CR_ERRIE);
AnnaBridge 157:e7ca05fa8600 729 }
AnnaBridge 157:e7ca05fa8600 730
AnnaBridge 157:e7ca05fa8600 731 /**
AnnaBridge 157:e7ca05fa8600 732 * @brief Disable Synchronization or trimming error interrupt
AnnaBridge 157:e7ca05fa8600 733 * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
AnnaBridge 157:e7ca05fa8600 734 * @retval None
AnnaBridge 157:e7ca05fa8600 735 */
AnnaBridge 157:e7ca05fa8600 736 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
AnnaBridge 157:e7ca05fa8600 737 {
AnnaBridge 157:e7ca05fa8600 738 CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
AnnaBridge 157:e7ca05fa8600 739 }
AnnaBridge 157:e7ca05fa8600 740
AnnaBridge 157:e7ca05fa8600 741 /**
AnnaBridge 157:e7ca05fa8600 742 * @brief Check if Synchronization or trimming error interrupt is enabled or not
AnnaBridge 157:e7ca05fa8600 743 * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
AnnaBridge 157:e7ca05fa8600 744 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 745 */
AnnaBridge 157:e7ca05fa8600 746 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
AnnaBridge 157:e7ca05fa8600 747 {
AnnaBridge 157:e7ca05fa8600 748 return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
AnnaBridge 157:e7ca05fa8600 749 }
AnnaBridge 157:e7ca05fa8600 750
AnnaBridge 157:e7ca05fa8600 751 /**
AnnaBridge 157:e7ca05fa8600 752 * @brief Enable Expected SYNC interrupt
AnnaBridge 157:e7ca05fa8600 753 * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
AnnaBridge 157:e7ca05fa8600 754 * @retval None
AnnaBridge 157:e7ca05fa8600 755 */
AnnaBridge 157:e7ca05fa8600 756 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
AnnaBridge 157:e7ca05fa8600 757 {
AnnaBridge 157:e7ca05fa8600 758 SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
AnnaBridge 157:e7ca05fa8600 759 }
AnnaBridge 157:e7ca05fa8600 760
AnnaBridge 157:e7ca05fa8600 761 /**
AnnaBridge 157:e7ca05fa8600 762 * @brief Disable Expected SYNC interrupt
AnnaBridge 157:e7ca05fa8600 763 * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
AnnaBridge 157:e7ca05fa8600 764 * @retval None
AnnaBridge 157:e7ca05fa8600 765 */
AnnaBridge 157:e7ca05fa8600 766 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
AnnaBridge 157:e7ca05fa8600 767 {
AnnaBridge 157:e7ca05fa8600 768 CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
AnnaBridge 157:e7ca05fa8600 769 }
AnnaBridge 157:e7ca05fa8600 770
AnnaBridge 157:e7ca05fa8600 771 /**
AnnaBridge 157:e7ca05fa8600 772 * @brief Check if Expected SYNC interrupt is enabled or not
AnnaBridge 157:e7ca05fa8600 773 * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
AnnaBridge 157:e7ca05fa8600 774 * @retval State of bit (1 or 0).
AnnaBridge 157:e7ca05fa8600 775 */
AnnaBridge 157:e7ca05fa8600 776 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
AnnaBridge 157:e7ca05fa8600 777 {
AnnaBridge 157:e7ca05fa8600 778 return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
AnnaBridge 157:e7ca05fa8600 779 }
AnnaBridge 157:e7ca05fa8600 780
AnnaBridge 157:e7ca05fa8600 781 /**
AnnaBridge 157:e7ca05fa8600 782 * @}
AnnaBridge 157:e7ca05fa8600 783 */
AnnaBridge 157:e7ca05fa8600 784
AnnaBridge 157:e7ca05fa8600 785 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 157:e7ca05fa8600 786 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
AnnaBridge 157:e7ca05fa8600 787 * @{
AnnaBridge 157:e7ca05fa8600 788 */
AnnaBridge 157:e7ca05fa8600 789
AnnaBridge 157:e7ca05fa8600 790 ErrorStatus LL_CRS_DeInit(void);
AnnaBridge 157:e7ca05fa8600 791
AnnaBridge 157:e7ca05fa8600 792 /**
AnnaBridge 157:e7ca05fa8600 793 * @}
AnnaBridge 157:e7ca05fa8600 794 */
AnnaBridge 157:e7ca05fa8600 795 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 157:e7ca05fa8600 796
AnnaBridge 157:e7ca05fa8600 797 /**
AnnaBridge 157:e7ca05fa8600 798 * @}
AnnaBridge 157:e7ca05fa8600 799 */
AnnaBridge 157:e7ca05fa8600 800
AnnaBridge 157:e7ca05fa8600 801 /**
AnnaBridge 157:e7ca05fa8600 802 * @}
AnnaBridge 157:e7ca05fa8600 803 */
AnnaBridge 157:e7ca05fa8600 804
AnnaBridge 157:e7ca05fa8600 805 #endif /* defined(CRS) */
AnnaBridge 157:e7ca05fa8600 806
AnnaBridge 157:e7ca05fa8600 807 /**
AnnaBridge 157:e7ca05fa8600 808 * @}
AnnaBridge 157:e7ca05fa8600 809 */
AnnaBridge 157:e7ca05fa8600 810
AnnaBridge 157:e7ca05fa8600 811 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 812 }
AnnaBridge 157:e7ca05fa8600 813 #endif
AnnaBridge 157:e7ca05fa8600 814
AnnaBridge 157:e7ca05fa8600 815 #endif /* __STM32L0xx_LL_CRS_H */
AnnaBridge 157:e7ca05fa8600 816
AnnaBridge 157:e7ca05fa8600 817 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/