mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_L011K4/TOOLCHAIN_ARM_MICRO/stm32l0xx_ll_bus.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_bus.h@167:84c0a372a020 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 143:86740a56073b 1 /**
AnnaBridge 143:86740a56073b 2 ******************************************************************************
AnnaBridge 143:86740a56073b 3 * @file stm32l0xx_ll_bus.h
AnnaBridge 143:86740a56073b 4 * @author MCD Application Team
AnnaBridge 143:86740a56073b 5 * @brief Header file of BUS LL module.
AnnaBridge 143:86740a56073b 6
AnnaBridge 143:86740a56073b 7 @verbatim
AnnaBridge 143:86740a56073b 8 ##### RCC Limitations #####
AnnaBridge 143:86740a56073b 9 ==============================================================================
AnnaBridge 143:86740a56073b 10 [..]
AnnaBridge 143:86740a56073b 11 A delay between an RCC peripheral clock enable and the effective peripheral
AnnaBridge 143:86740a56073b 12 enabling should be taken into account in order to manage the peripheral read/write
AnnaBridge 143:86740a56073b 13 from/to registers.
AnnaBridge 143:86740a56073b 14 (+) This delay depends on the peripheral mapping.
AnnaBridge 143:86740a56073b 15 (++) AHB & APB peripherals, 1 dummy read is necessary
AnnaBridge 143:86740a56073b 16
AnnaBridge 143:86740a56073b 17 [..]
AnnaBridge 143:86740a56073b 18 Workarounds:
AnnaBridge 143:86740a56073b 19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
AnnaBridge 143:86740a56073b 20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
AnnaBridge 143:86740a56073b 21
AnnaBridge 143:86740a56073b 22 @endverbatim
AnnaBridge 143:86740a56073b 23 ******************************************************************************
AnnaBridge 143:86740a56073b 24 * @attention
AnnaBridge 143:86740a56073b 25 *
AnnaBridge 143:86740a56073b 26 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 143:86740a56073b 27 *
AnnaBridge 143:86740a56073b 28 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 143:86740a56073b 29 * are permitted provided that the following conditions are met:
AnnaBridge 143:86740a56073b 30 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 143:86740a56073b 31 * this list of conditions and the following disclaimer.
AnnaBridge 143:86740a56073b 32 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 143:86740a56073b 33 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 143:86740a56073b 34 * and/or other materials provided with the distribution.
AnnaBridge 143:86740a56073b 35 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 143:86740a56073b 36 * may be used to endorse or promote products derived from this software
AnnaBridge 143:86740a56073b 37 * without specific prior written permission.
AnnaBridge 143:86740a56073b 38 *
AnnaBridge 143:86740a56073b 39 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 143:86740a56073b 40 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 143:86740a56073b 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 143:86740a56073b 42 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 143:86740a56073b 43 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 143:86740a56073b 44 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 143:86740a56073b 45 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 143:86740a56073b 46 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 143:86740a56073b 47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 143:86740a56073b 48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 143:86740a56073b 49 *
AnnaBridge 143:86740a56073b 50 ******************************************************************************
AnnaBridge 143:86740a56073b 51 */
AnnaBridge 143:86740a56073b 52
AnnaBridge 143:86740a56073b 53 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 143:86740a56073b 54 #ifndef __STM32L0xx_LL_BUS_H
AnnaBridge 143:86740a56073b 55 #define __STM32L0xx_LL_BUS_H
AnnaBridge 143:86740a56073b 56
AnnaBridge 143:86740a56073b 57 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 58 extern "C" {
AnnaBridge 143:86740a56073b 59 #endif
AnnaBridge 143:86740a56073b 60
AnnaBridge 143:86740a56073b 61 /* Includes ------------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 62 #include "stm32l0xx.h"
AnnaBridge 143:86740a56073b 63
AnnaBridge 143:86740a56073b 64 /** @addtogroup STM32L0xx_LL_Driver
AnnaBridge 143:86740a56073b 65 * @{
AnnaBridge 143:86740a56073b 66 */
AnnaBridge 143:86740a56073b 67
AnnaBridge 143:86740a56073b 68 #if defined(RCC)
AnnaBridge 143:86740a56073b 69
AnnaBridge 143:86740a56073b 70 /** @defgroup BUS_LL BUS
AnnaBridge 143:86740a56073b 71 * @{
AnnaBridge 143:86740a56073b 72 */
AnnaBridge 143:86740a56073b 73
AnnaBridge 143:86740a56073b 74 /* Private types -------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 75 /* Private variables ---------------------------------------------------------*/
AnnaBridge 143:86740a56073b 76
AnnaBridge 143:86740a56073b 77 /* Private constants ---------------------------------------------------------*/
AnnaBridge 143:86740a56073b 78
AnnaBridge 143:86740a56073b 79 /* Private macros ------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 80
AnnaBridge 143:86740a56073b 81 /* Exported types ------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 82 /* Exported constants --------------------------------------------------------*/
AnnaBridge 143:86740a56073b 83 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
AnnaBridge 143:86740a56073b 84 * @{
AnnaBridge 143:86740a56073b 85 */
AnnaBridge 143:86740a56073b 86
AnnaBridge 143:86740a56073b 87 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
AnnaBridge 143:86740a56073b 88 * @{
AnnaBridge 143:86740a56073b 89 */
AnnaBridge 143:86740a56073b 90 #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
AnnaBridge 143:86740a56073b 91 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN /*!< DMA1 clock enable */
AnnaBridge 143:86740a56073b 92 #define LL_AHB1_GRP1_PERIPH_MIF RCC_AHBENR_MIFEN /*!< MIF clock enable */
AnnaBridge 143:86740a56073b 93 #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN /*!< Sleep Mode SRAM clock enable */
AnnaBridge 143:86740a56073b 94 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN /*!< CRC clock enable */
AnnaBridge 143:86740a56073b 95 #if defined(TSC)
AnnaBridge 143:86740a56073b 96 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN /*!< TSC clock enable */
AnnaBridge 143:86740a56073b 97 #endif /*TSC*/
AnnaBridge 143:86740a56073b 98 #if defined(RNG)
AnnaBridge 143:86740a56073b 99 #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN /*!< RNG clock enable */
AnnaBridge 143:86740a56073b 100 #endif /*RNG*/
AnnaBridge 143:86740a56073b 101 #if defined(AES)
AnnaBridge 143:86740a56073b 102 #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_CRYPEN /*!< CRYP clock enable */
AnnaBridge 143:86740a56073b 103 #endif /*AES*/
AnnaBridge 143:86740a56073b 104 /**
AnnaBridge 143:86740a56073b 105 * @}
AnnaBridge 143:86740a56073b 106 */
AnnaBridge 143:86740a56073b 107
AnnaBridge 143:86740a56073b 108
AnnaBridge 143:86740a56073b 109 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
AnnaBridge 143:86740a56073b 110 * @{
AnnaBridge 143:86740a56073b 111 */
AnnaBridge 143:86740a56073b 112 #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
AnnaBridge 143:86740a56073b 113 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN /*!< TIM2 clock enable */
AnnaBridge 143:86740a56073b 114 #if defined(TIM3)
AnnaBridge 143:86740a56073b 115 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN /*!< TIM3 clock enable */
AnnaBridge 143:86740a56073b 116 #endif
AnnaBridge 143:86740a56073b 117 #if defined(TIM6)
AnnaBridge 143:86740a56073b 118 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN /*!< TIM6 clock enable */
AnnaBridge 143:86740a56073b 119 #endif
AnnaBridge 143:86740a56073b 120 #if defined(TIM7)
AnnaBridge 143:86740a56073b 121 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN /*!< TIM7 clock enable */
AnnaBridge 143:86740a56073b 122 #endif
AnnaBridge 143:86740a56073b 123 #if defined(LCD)
AnnaBridge 143:86740a56073b 124 #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN /*!< LCD clock enable */
AnnaBridge 143:86740a56073b 125 #endif /*LCD*/
AnnaBridge 143:86740a56073b 126 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN /*!< WWDG clock enable */
AnnaBridge 143:86740a56073b 127 #if defined(SPI2)
AnnaBridge 143:86740a56073b 128 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN /*!< SPI2 clock enable */
AnnaBridge 143:86740a56073b 129 #endif
AnnaBridge 143:86740a56073b 130 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN /*!< USART2 clock enable */
AnnaBridge 143:86740a56073b 131 #define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APB1ENR_LPUART1EN /*!< LPUART1 clock enable */
AnnaBridge 143:86740a56073b 132 #if defined(USART4)
AnnaBridge 143:86740a56073b 133 #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN /*!< USART4 clock enable */
AnnaBridge 143:86740a56073b 134 #endif
AnnaBridge 143:86740a56073b 135 #if defined(USART5)
AnnaBridge 143:86740a56073b 136 #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN /*!< USART5 clock enable */
AnnaBridge 143:86740a56073b 137 #endif
AnnaBridge 143:86740a56073b 138 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN /*!< I2C1 clock enable */
AnnaBridge 143:86740a56073b 139 #if defined(I2C2)
AnnaBridge 143:86740a56073b 140 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN /*!< I2C2 clock enable */
AnnaBridge 143:86740a56073b 141 #endif
AnnaBridge 143:86740a56073b 142 #if defined(USB)
AnnaBridge 143:86740a56073b 143 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN /*!< USB clock enable */
AnnaBridge 143:86740a56073b 144 #endif /*USB*/
AnnaBridge 143:86740a56073b 145 #if defined(CRS)
AnnaBridge 143:86740a56073b 146 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN /*!< CRS clock enable */
AnnaBridge 143:86740a56073b 147 #endif /*CRS*/
AnnaBridge 143:86740a56073b 148 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN /*!< PWR clock enable */
AnnaBridge 143:86740a56073b 149 #if defined(DAC)
AnnaBridge 143:86740a56073b 150 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN /*!< DAC clock enable */
AnnaBridge 143:86740a56073b 151 #endif
AnnaBridge 143:86740a56073b 152 #if defined(I2C3)
AnnaBridge 143:86740a56073b 153 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN /*!< I2C3 clock enable */
AnnaBridge 143:86740a56073b 154 #endif
AnnaBridge 143:86740a56073b 155 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN /*!< LPTIM1 clock enable */
AnnaBridge 143:86740a56073b 156 /**
AnnaBridge 143:86740a56073b 157 * @}
AnnaBridge 143:86740a56073b 158 */
AnnaBridge 143:86740a56073b 159
AnnaBridge 143:86740a56073b 160
AnnaBridge 143:86740a56073b 161
AnnaBridge 143:86740a56073b 162
AnnaBridge 143:86740a56073b 163 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
AnnaBridge 143:86740a56073b 164 * @{
AnnaBridge 143:86740a56073b 165 */
AnnaBridge 143:86740a56073b 166 #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
AnnaBridge 143:86740a56073b 167 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN /*!< SYSCFG clock enable */
AnnaBridge 143:86740a56073b 168 #define LL_APB2_GRP1_PERIPH_TIM21 RCC_APB2ENR_TIM21EN /*!< TIM21 clock enable */
AnnaBridge 143:86740a56073b 169 #if defined(TIM22)
AnnaBridge 143:86740a56073b 170 #define LL_APB2_GRP1_PERIPH_TIM22 RCC_APB2ENR_TIM22EN /*!< TIM22 clock enable */
AnnaBridge 143:86740a56073b 171 #endif
AnnaBridge 143:86740a56073b 172 #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN /*!< FireWall clock enable */
AnnaBridge 143:86740a56073b 173 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN /*!< ADC1 clock enable */
AnnaBridge 143:86740a56073b 174 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN /*!< SPI1 clock enable */
AnnaBridge 143:86740a56073b 175 #if defined(USART1)
AnnaBridge 143:86740a56073b 176 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN /*!< USART1 clock enable */
AnnaBridge 143:86740a56073b 177 #endif
AnnaBridge 143:86740a56073b 178 #define LL_APB2_GRP1_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN /*!< DBGMCU clock enable */
AnnaBridge 143:86740a56073b 179
AnnaBridge 143:86740a56073b 180 /**
AnnaBridge 143:86740a56073b 181 * @}
AnnaBridge 143:86740a56073b 182 */
AnnaBridge 143:86740a56073b 183
AnnaBridge 143:86740a56073b 184
AnnaBridge 143:86740a56073b 185
AnnaBridge 143:86740a56073b 186 /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH
AnnaBridge 143:86740a56073b 187 * @{
AnnaBridge 143:86740a56073b 188 */
AnnaBridge 143:86740a56073b 189 #define LL_IOP_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
AnnaBridge 143:86740a56073b 190 #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN /*!< GPIO port A control */
AnnaBridge 143:86740a56073b 191 #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN /*!< GPIO port B control */
AnnaBridge 143:86740a56073b 192 #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN /*!< GPIO port C control */
AnnaBridge 143:86740a56073b 193 #if defined(GPIOD)
AnnaBridge 143:86740a56073b 194 #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN /*!< GPIO port D control */
AnnaBridge 143:86740a56073b 195 #endif /*GPIOD*/
AnnaBridge 143:86740a56073b 196 #if defined(GPIOE)
AnnaBridge 143:86740a56073b 197 #define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN /*!< GPIO port H control */
AnnaBridge 143:86740a56073b 198 #endif /*GPIOE*/
AnnaBridge 143:86740a56073b 199 #if defined(GPIOH)
AnnaBridge 143:86740a56073b 200 #define LL_IOP_GRP1_PERIPH_GPIOH RCC_IOPENR_GPIOHEN /*!< GPIO port H control */
AnnaBridge 143:86740a56073b 201 #endif /*GPIOH*/
AnnaBridge 143:86740a56073b 202 /**
AnnaBridge 143:86740a56073b 203 * @}
AnnaBridge 143:86740a56073b 204 */
AnnaBridge 143:86740a56073b 205
AnnaBridge 143:86740a56073b 206
AnnaBridge 143:86740a56073b 207 /**
AnnaBridge 143:86740a56073b 208 * @}
AnnaBridge 143:86740a56073b 209 */
AnnaBridge 143:86740a56073b 210
AnnaBridge 143:86740a56073b 211 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 212 /* Exported functions --------------------------------------------------------*/
AnnaBridge 143:86740a56073b 213 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
AnnaBridge 143:86740a56073b 214 * @{
AnnaBridge 143:86740a56073b 215 */
AnnaBridge 143:86740a56073b 216
AnnaBridge 143:86740a56073b 217 /** @defgroup BUS_LL_EF_AHB1 AHB1
AnnaBridge 143:86740a56073b 218 * @{
AnnaBridge 143:86740a56073b 219 */
AnnaBridge 143:86740a56073b 220
AnnaBridge 143:86740a56073b 221 /**
AnnaBridge 143:86740a56073b 222 * @brief Enable AHB1 peripherals clock.
AnnaBridge 143:86740a56073b 223 * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 224 * AHBENR MIFEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 225 * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 226 * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 227 * AHBENR RNGEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 228 * AHBENR CRYPEN LL_AHB1_GRP1_EnableClock
AnnaBridge 143:86740a56073b 229 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 230 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge 143:86740a56073b 231 * @arg @ref LL_AHB1_GRP1_PERIPH_MIF
AnnaBridge 143:86740a56073b 232 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge 143:86740a56073b 233 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
AnnaBridge 143:86740a56073b 234 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
AnnaBridge 143:86740a56073b 235 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
AnnaBridge 143:86740a56073b 236 *
AnnaBridge 143:86740a56073b 237 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 238 * @retval None
AnnaBridge 143:86740a56073b 239 */
AnnaBridge 143:86740a56073b 240 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge 143:86740a56073b 241 {
AnnaBridge 143:86740a56073b 242 __IO uint32_t tmpreg;
AnnaBridge 143:86740a56073b 243 SET_BIT(RCC->AHBENR, Periphs);
AnnaBridge 143:86740a56073b 244 /* Delay after an RCC peripheral clock enabling */
AnnaBridge 143:86740a56073b 245 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
AnnaBridge 143:86740a56073b 246 (void)tmpreg;
AnnaBridge 143:86740a56073b 247 }
AnnaBridge 143:86740a56073b 248
AnnaBridge 143:86740a56073b 249 /**
AnnaBridge 143:86740a56073b 250 * @brief Check if AHB1 peripheral clock is enabled or not
AnnaBridge 143:86740a56073b 251 * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 252 * AHBENR MIFEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 253 * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 254 * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 255 * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 256 * AHBENR CRYPEN LL_AHB1_GRP1_IsEnabledClock
AnnaBridge 143:86740a56073b 257 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 258 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge 143:86740a56073b 259 * @arg @ref LL_AHB1_GRP1_PERIPH_MIF
AnnaBridge 143:86740a56073b 260 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge 143:86740a56073b 261 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
AnnaBridge 143:86740a56073b 262 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
AnnaBridge 143:86740a56073b 263 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
AnnaBridge 143:86740a56073b 264 *
AnnaBridge 143:86740a56073b 265 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 266 * @retval State of Periphs (1 or 0).
AnnaBridge 143:86740a56073b 267 */
AnnaBridge 143:86740a56073b 268 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge 143:86740a56073b 269 {
AnnaBridge 143:86740a56073b 270 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
AnnaBridge 143:86740a56073b 271 }
AnnaBridge 143:86740a56073b 272
AnnaBridge 143:86740a56073b 273 /**
AnnaBridge 143:86740a56073b 274 * @brief Disable AHB1 peripherals clock.
AnnaBridge 143:86740a56073b 275 * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 276 * AHBENR MIFEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 277 * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 278 * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 279 * AHBENR RNGEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 280 * AHBENR CRYPEN LL_AHB1_GRP1_DisableClock
AnnaBridge 143:86740a56073b 281 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 282 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge 143:86740a56073b 283 * @arg @ref LL_AHB1_GRP1_PERIPH_MIF
AnnaBridge 143:86740a56073b 284 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge 143:86740a56073b 285 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
AnnaBridge 143:86740a56073b 286 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
AnnaBridge 143:86740a56073b 287 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
AnnaBridge 143:86740a56073b 288 *
AnnaBridge 143:86740a56073b 289 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 290 * @retval None
AnnaBridge 143:86740a56073b 291 */
AnnaBridge 143:86740a56073b 292 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge 143:86740a56073b 293 {
AnnaBridge 143:86740a56073b 294 CLEAR_BIT(RCC->AHBENR, Periphs);
AnnaBridge 143:86740a56073b 295 }
AnnaBridge 143:86740a56073b 296
AnnaBridge 143:86740a56073b 297 /**
AnnaBridge 143:86740a56073b 298 * @brief Force AHB1 peripherals reset.
AnnaBridge 143:86740a56073b 299 * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 300 * AHBRSTR MIFRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 301 * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 302 * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 303 * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 304 * AHBRSTR CRYPRST LL_AHB1_GRP1_ForceReset
AnnaBridge 143:86740a56073b 305 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 306 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
AnnaBridge 143:86740a56073b 307 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge 143:86740a56073b 308 * @arg @ref LL_AHB1_GRP1_PERIPH_MIF
AnnaBridge 143:86740a56073b 309 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge 143:86740a56073b 310 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
AnnaBridge 143:86740a56073b 311 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
AnnaBridge 143:86740a56073b 312 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
AnnaBridge 143:86740a56073b 313 *
AnnaBridge 143:86740a56073b 314 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 315 * @retval None
AnnaBridge 143:86740a56073b 316 */
AnnaBridge 143:86740a56073b 317 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge 143:86740a56073b 318 {
AnnaBridge 143:86740a56073b 319 SET_BIT(RCC->AHBRSTR, Periphs);
AnnaBridge 143:86740a56073b 320 }
AnnaBridge 143:86740a56073b 321
AnnaBridge 143:86740a56073b 322 /**
AnnaBridge 143:86740a56073b 323 * @brief Release AHB1 peripherals reset.
AnnaBridge 143:86740a56073b 324 * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 325 * AHBRSTR MIFRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 326 * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 327 * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 328 * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 329 * AHBRSTR CRYPRST LL_AHB1_GRP1_ReleaseReset
AnnaBridge 143:86740a56073b 330 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 331 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
AnnaBridge 143:86740a56073b 332 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge 143:86740a56073b 333 * @arg @ref LL_AHB1_GRP1_PERIPH_MIF
AnnaBridge 143:86740a56073b 334 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge 143:86740a56073b 335 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
AnnaBridge 143:86740a56073b 336 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
AnnaBridge 143:86740a56073b 337 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
AnnaBridge 143:86740a56073b 338 *
AnnaBridge 143:86740a56073b 339 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 340 * @retval None
AnnaBridge 143:86740a56073b 341 */
AnnaBridge 143:86740a56073b 342 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge 143:86740a56073b 343 {
AnnaBridge 143:86740a56073b 344 CLEAR_BIT(RCC->AHBRSTR, Periphs);
AnnaBridge 143:86740a56073b 345 }
AnnaBridge 143:86740a56073b 346
AnnaBridge 143:86740a56073b 347 /**
AnnaBridge 143:86740a56073b 348 * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode.
AnnaBridge 143:86740a56073b 349 * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 350 * AHBSMENR MIFSMEN LL_AHB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 351 * AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 352 * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 353 * AHBSMENR TSCSMEN LL_AHB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 354 * AHBSMENR RNGSMEN LL_AHB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 355 * AHBSMENR CRYPSMEN LL_AHB1_GRP1_EnableClockSleep
AnnaBridge 143:86740a56073b 356 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 357 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge 143:86740a56073b 358 * @arg @ref LL_AHB1_GRP1_PERIPH_MIF
AnnaBridge 143:86740a56073b 359 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
AnnaBridge 143:86740a56073b 360 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge 143:86740a56073b 361 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
AnnaBridge 143:86740a56073b 362 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
AnnaBridge 143:86740a56073b 363 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
AnnaBridge 143:86740a56073b 364 *
AnnaBridge 143:86740a56073b 365 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 366 * @retval None
AnnaBridge 143:86740a56073b 367 */
AnnaBridge 143:86740a56073b 368 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
AnnaBridge 143:86740a56073b 369 {
AnnaBridge 143:86740a56073b 370 __IO uint32_t tmpreg;
AnnaBridge 143:86740a56073b 371 SET_BIT(RCC->AHBSMENR, Periphs);
AnnaBridge 143:86740a56073b 372 /* Delay after an RCC peripheral clock enabling */
AnnaBridge 143:86740a56073b 373 tmpreg = READ_BIT(RCC->AHBSMENR, Periphs);
AnnaBridge 143:86740a56073b 374 (void)tmpreg;
AnnaBridge 143:86740a56073b 375 }
AnnaBridge 143:86740a56073b 376
AnnaBridge 143:86740a56073b 377 /**
AnnaBridge 143:86740a56073b 378 * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode.
AnnaBridge 143:86740a56073b 379 * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 380 * AHBSMENR MIFSMEN LL_AHB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 381 * AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 382 * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 383 * AHBSMENR TSCSMEN LL_AHB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 384 * AHBSMENR RNGSMEN LL_AHB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 385 * AHBSMENR CRYPSMEN LL_AHB1_GRP1_DisableClockSleep
AnnaBridge 143:86740a56073b 386 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 387 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge 143:86740a56073b 388 * @arg @ref LL_AHB1_GRP1_PERIPH_MIF
AnnaBridge 143:86740a56073b 389 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
AnnaBridge 143:86740a56073b 390 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge 143:86740a56073b 391 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
AnnaBridge 143:86740a56073b 392 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
AnnaBridge 143:86740a56073b 393 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
AnnaBridge 143:86740a56073b 394 *
AnnaBridge 143:86740a56073b 395 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 396 * @retval None
AnnaBridge 143:86740a56073b 397 */
AnnaBridge 143:86740a56073b 398 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
AnnaBridge 143:86740a56073b 399 {
AnnaBridge 143:86740a56073b 400 CLEAR_BIT(RCC->AHBSMENR, Periphs);
AnnaBridge 143:86740a56073b 401 }
AnnaBridge 143:86740a56073b 402
AnnaBridge 143:86740a56073b 403 /**
AnnaBridge 143:86740a56073b 404 * @}
AnnaBridge 143:86740a56073b 405 */
AnnaBridge 143:86740a56073b 406
AnnaBridge 143:86740a56073b 407 /** @defgroup BUS_LL_EF_APB1 APB1
AnnaBridge 143:86740a56073b 408 * @{
AnnaBridge 143:86740a56073b 409 */
AnnaBridge 143:86740a56073b 410
AnnaBridge 143:86740a56073b 411 /**
AnnaBridge 143:86740a56073b 412 * @brief Enable APB1 peripherals clock.
AnnaBridge 143:86740a56073b 413 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 414 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 415 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 416 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 417 * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 418 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 419 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 420 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 421 * APB1ENR LPUART1EN LL_APB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 422 * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 423 * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 424 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 425 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 426 * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 427 * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 428 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 429 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 430 * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 431 * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock
AnnaBridge 143:86740a56073b 432 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 433 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge 143:86740a56073b 434 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge 143:86740a56073b 435 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
AnnaBridge 143:86740a56073b 436 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
AnnaBridge 143:86740a56073b 437 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
AnnaBridge 143:86740a56073b 438 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge 143:86740a56073b 439 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge 143:86740a56073b 440 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge 143:86740a56073b 441 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
AnnaBridge 143:86740a56073b 442 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
AnnaBridge 143:86740a56073b 443 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
AnnaBridge 143:86740a56073b 444 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge 143:86740a56073b 445 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
AnnaBridge 143:86740a56073b 446 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
AnnaBridge 143:86740a56073b 447 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
AnnaBridge 143:86740a56073b 448 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge 143:86740a56073b 449 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
AnnaBridge 143:86740a56073b 450 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
AnnaBridge 143:86740a56073b 451 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge 143:86740a56073b 452 *
AnnaBridge 143:86740a56073b 453 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 454 * @retval None
AnnaBridge 143:86740a56073b 455 */
AnnaBridge 143:86740a56073b 456 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge 143:86740a56073b 457 {
AnnaBridge 143:86740a56073b 458 __IO uint32_t tmpreg;
AnnaBridge 143:86740a56073b 459 SET_BIT(RCC->APB1ENR, Periphs);
AnnaBridge 143:86740a56073b 460 /* Delay after an RCC peripheral clock enabling */
AnnaBridge 143:86740a56073b 461 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
AnnaBridge 143:86740a56073b 462 (void)tmpreg;
AnnaBridge 143:86740a56073b 463 }
AnnaBridge 143:86740a56073b 464
AnnaBridge 143:86740a56073b 465 /**
AnnaBridge 143:86740a56073b 466 * @brief Check if APB1 peripheral clock is enabled or not
AnnaBridge 143:86740a56073b 467 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 468 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 469 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 470 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 471 * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 472 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 473 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 474 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 475 * APB1ENR LPUART1EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 476 * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 477 * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 478 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 479 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 480 * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 481 * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 482 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 483 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 484 * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 485 * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock
AnnaBridge 143:86740a56073b 486 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 487 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge 143:86740a56073b 488 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge 143:86740a56073b 489 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
AnnaBridge 143:86740a56073b 490 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
AnnaBridge 143:86740a56073b 491 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
AnnaBridge 143:86740a56073b 492 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge 143:86740a56073b 493 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge 143:86740a56073b 494 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge 143:86740a56073b 495 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
AnnaBridge 143:86740a56073b 496 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
AnnaBridge 143:86740a56073b 497 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
AnnaBridge 143:86740a56073b 498 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge 143:86740a56073b 499 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
AnnaBridge 143:86740a56073b 500 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
AnnaBridge 143:86740a56073b 501 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
AnnaBridge 143:86740a56073b 502 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge 143:86740a56073b 503 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
AnnaBridge 143:86740a56073b 504 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
AnnaBridge 143:86740a56073b 505 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge 143:86740a56073b 506 *
AnnaBridge 143:86740a56073b 507 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 508 * @retval State of Periphs (1 or 0).
AnnaBridge 143:86740a56073b 509 */
AnnaBridge 143:86740a56073b 510 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge 143:86740a56073b 511 {
AnnaBridge 143:86740a56073b 512 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
AnnaBridge 143:86740a56073b 513 }
AnnaBridge 143:86740a56073b 514
AnnaBridge 143:86740a56073b 515 /**
AnnaBridge 143:86740a56073b 516 * @brief Disable APB1 peripherals clock.
AnnaBridge 143:86740a56073b 517 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 518 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 519 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 520 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 521 * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 522 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 523 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 524 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 525 * APB1ENR LPUART1EN LL_APB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 526 * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 527 * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 528 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 529 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 530 * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 531 * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 532 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 533 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 534 * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 535 * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock
AnnaBridge 143:86740a56073b 536 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 537 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge 143:86740a56073b 538 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge 143:86740a56073b 539 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
AnnaBridge 143:86740a56073b 540 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
AnnaBridge 143:86740a56073b 541 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
AnnaBridge 143:86740a56073b 542 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge 143:86740a56073b 543 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge 143:86740a56073b 544 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge 143:86740a56073b 545 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
AnnaBridge 143:86740a56073b 546 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
AnnaBridge 143:86740a56073b 547 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
AnnaBridge 143:86740a56073b 548 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge 143:86740a56073b 549 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
AnnaBridge 143:86740a56073b 550 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
AnnaBridge 143:86740a56073b 551 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
AnnaBridge 143:86740a56073b 552 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge 143:86740a56073b 553 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
AnnaBridge 143:86740a56073b 554 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
AnnaBridge 143:86740a56073b 555 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge 143:86740a56073b 556 *
AnnaBridge 143:86740a56073b 557 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 558 * @retval None
AnnaBridge 143:86740a56073b 559 */
AnnaBridge 143:86740a56073b 560 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge 143:86740a56073b 561 {
AnnaBridge 143:86740a56073b 562 CLEAR_BIT(RCC->APB1ENR, Periphs);
AnnaBridge 143:86740a56073b 563 }
AnnaBridge 143:86740a56073b 564
AnnaBridge 143:86740a56073b 565 /**
AnnaBridge 143:86740a56073b 566 * @brief Force APB1 peripherals reset.
AnnaBridge 143:86740a56073b 567 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 568 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 569 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 570 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 571 * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 572 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 573 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 574 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 575 * APB1RSTR LPUART1RST LL_APB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 576 * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 577 * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 578 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 579 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 580 * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 581 * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 582 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 583 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 584 * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 585 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset
AnnaBridge 143:86740a56073b 586 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 587 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
AnnaBridge 143:86740a56073b 588 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge 143:86740a56073b 589 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge 143:86740a56073b 590 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
AnnaBridge 143:86740a56073b 591 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
AnnaBridge 143:86740a56073b 592 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
AnnaBridge 143:86740a56073b 593 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge 143:86740a56073b 594 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge 143:86740a56073b 595 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge 143:86740a56073b 596 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
AnnaBridge 143:86740a56073b 597 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
AnnaBridge 143:86740a56073b 598 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
AnnaBridge 143:86740a56073b 599 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge 143:86740a56073b 600 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
AnnaBridge 143:86740a56073b 601 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
AnnaBridge 143:86740a56073b 602 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
AnnaBridge 143:86740a56073b 603 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge 143:86740a56073b 604 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
AnnaBridge 143:86740a56073b 605 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
AnnaBridge 143:86740a56073b 606 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge 143:86740a56073b 607 *
AnnaBridge 143:86740a56073b 608 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 609 * @retval None
AnnaBridge 143:86740a56073b 610 */
AnnaBridge 143:86740a56073b 611 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge 143:86740a56073b 612 {
AnnaBridge 143:86740a56073b 613 SET_BIT(RCC->APB1RSTR, Periphs);
AnnaBridge 143:86740a56073b 614 }
AnnaBridge 143:86740a56073b 615
AnnaBridge 143:86740a56073b 616 /**
AnnaBridge 143:86740a56073b 617 * @brief Release APB1 peripherals reset.
AnnaBridge 143:86740a56073b 618 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 619 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 620 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 621 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 622 * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 623 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 624 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 625 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 626 * APB1RSTR LPUART1RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 627 * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 628 * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 629 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 630 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 631 * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 632 * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 633 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 634 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 635 * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 636 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset
AnnaBridge 143:86740a56073b 637 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 638 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
AnnaBridge 143:86740a56073b 639 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge 143:86740a56073b 640 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge 143:86740a56073b 641 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
AnnaBridge 143:86740a56073b 642 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
AnnaBridge 143:86740a56073b 643 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
AnnaBridge 143:86740a56073b 644 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge 143:86740a56073b 645 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge 143:86740a56073b 646 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge 143:86740a56073b 647 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
AnnaBridge 143:86740a56073b 648 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
AnnaBridge 143:86740a56073b 649 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
AnnaBridge 143:86740a56073b 650 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge 143:86740a56073b 651 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
AnnaBridge 143:86740a56073b 652 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
AnnaBridge 143:86740a56073b 653 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
AnnaBridge 143:86740a56073b 654 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge 143:86740a56073b 655 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
AnnaBridge 143:86740a56073b 656 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
AnnaBridge 143:86740a56073b 657 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge 143:86740a56073b 658 *
AnnaBridge 143:86740a56073b 659 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 660 * @retval None
AnnaBridge 143:86740a56073b 661 */
AnnaBridge 143:86740a56073b 662 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge 143:86740a56073b 663 {
AnnaBridge 143:86740a56073b 664 CLEAR_BIT(RCC->APB1RSTR, Periphs);
AnnaBridge 143:86740a56073b 665 }
AnnaBridge 143:86740a56073b 666
AnnaBridge 143:86740a56073b 667 /**
AnnaBridge 143:86740a56073b 668 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
AnnaBridge 143:86740a56073b 669 * @rmtoll APB1SMENR TIM2SMEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 670 * APB1SMENR TIM3SMEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 671 * APB1SMENR TIM6SMEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 672 * APB1SMENR TIM7SMEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 673 * APB1SMENR LCDSMEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 674 * APB1SMENR WWDGSMEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 675 * APB1SMENR SPI2SMEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 676 * APB1SMENR USART2SMEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 677 * APB1SMENR LPUART1SMEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 678 * APB1SMENR USART4SMEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 679 * APB1SMENR USART5SMEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 680 * APB1SMENR I2C1SMEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 681 * APB1SMENR I2C2SMEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 682 * APB1SMENR USBSMEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 683 * APB1SMENR CRSSMEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 684 * APB1SMENR PWRSMEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 685 * APB1SMENR DACSMEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 686 * APB1SMENR I2C3SMEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 687 * APB1SMENR LPTIM1SMEN LL_APB1_GRP1_EnableClockSleep
AnnaBridge 143:86740a56073b 688 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 689 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge 143:86740a56073b 690 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge 143:86740a56073b 691 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
AnnaBridge 143:86740a56073b 692 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
AnnaBridge 143:86740a56073b 693 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
AnnaBridge 143:86740a56073b 694 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge 143:86740a56073b 695 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge 143:86740a56073b 696 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge 143:86740a56073b 697 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
AnnaBridge 143:86740a56073b 698 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
AnnaBridge 143:86740a56073b 699 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
AnnaBridge 143:86740a56073b 700 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge 143:86740a56073b 701 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
AnnaBridge 143:86740a56073b 702 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
AnnaBridge 143:86740a56073b 703 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
AnnaBridge 143:86740a56073b 704 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge 143:86740a56073b 705 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
AnnaBridge 143:86740a56073b 706 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
AnnaBridge 143:86740a56073b 707 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge 143:86740a56073b 708 *
AnnaBridge 143:86740a56073b 709 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 710 * @retval None
AnnaBridge 143:86740a56073b 711 */
AnnaBridge 143:86740a56073b 712 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
AnnaBridge 143:86740a56073b 713 {
AnnaBridge 143:86740a56073b 714 __IO uint32_t tmpreg;
AnnaBridge 143:86740a56073b 715 SET_BIT(RCC->APB1SMENR, Periphs);
AnnaBridge 143:86740a56073b 716 /* Delay after an RCC peripheral clock enabling */
AnnaBridge 143:86740a56073b 717 tmpreg = READ_BIT(RCC->APB1SMENR, Periphs);
AnnaBridge 143:86740a56073b 718 (void)tmpreg;
AnnaBridge 143:86740a56073b 719 }
AnnaBridge 143:86740a56073b 720
AnnaBridge 143:86740a56073b 721 /**
AnnaBridge 143:86740a56073b 722 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
AnnaBridge 143:86740a56073b 723 * @rmtoll APB1SMENR TIM2SMEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 724 * APB1SMENR TIM3SMEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 725 * APB1SMENR TIM6SMEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 726 * APB1SMENR TIM7SMEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 727 * APB1SMENR LCDSMEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 728 * APB1SMENR WWDGSMEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 729 * APB1SMENR SPI2SMEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 730 * APB1SMENR USART2SMEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 731 * APB1SMENR LPUART1SMEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 732 * APB1SMENR USART4SMEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 733 * APB1SMENR USART5SMEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 734 * APB1SMENR I2C1SMEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 735 * APB1SMENR I2C2SMEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 736 * APB1SMENR USBSMEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 737 * APB1SMENR CRSSMEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 738 * APB1SMENR PWRSMEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 739 * APB1SMENR DACSMEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 740 * APB1SMENR I2C3SMEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 741 * APB1SMENR LPTIM1SMEN LL_APB1_GRP1_DisableClockSleep
AnnaBridge 143:86740a56073b 742 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 743 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge 143:86740a56073b 744 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge 143:86740a56073b 745 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
AnnaBridge 143:86740a56073b 746 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
AnnaBridge 143:86740a56073b 747 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
AnnaBridge 143:86740a56073b 748 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge 143:86740a56073b 749 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge 143:86740a56073b 750 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge 143:86740a56073b 751 * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
AnnaBridge 143:86740a56073b 752 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
AnnaBridge 143:86740a56073b 753 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
AnnaBridge 143:86740a56073b 754 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge 143:86740a56073b 755 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
AnnaBridge 143:86740a56073b 756 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
AnnaBridge 143:86740a56073b 757 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
AnnaBridge 143:86740a56073b 758 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge 143:86740a56073b 759 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
AnnaBridge 143:86740a56073b 760 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
AnnaBridge 143:86740a56073b 761 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge 143:86740a56073b 762 *
AnnaBridge 143:86740a56073b 763 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 764 * @retval None
AnnaBridge 143:86740a56073b 765 */
AnnaBridge 143:86740a56073b 766 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
AnnaBridge 143:86740a56073b 767 {
AnnaBridge 143:86740a56073b 768 CLEAR_BIT(RCC->APB1SMENR, Periphs);
AnnaBridge 143:86740a56073b 769 }
AnnaBridge 143:86740a56073b 770
AnnaBridge 143:86740a56073b 771 /**
AnnaBridge 143:86740a56073b 772 * @}
AnnaBridge 143:86740a56073b 773 */
AnnaBridge 143:86740a56073b 774
AnnaBridge 143:86740a56073b 775 /** @defgroup BUS_LL_EF_APB2 APB2
AnnaBridge 143:86740a56073b 776 * @{
AnnaBridge 143:86740a56073b 777 */
AnnaBridge 143:86740a56073b 778
AnnaBridge 143:86740a56073b 779 /**
AnnaBridge 143:86740a56073b 780 * @brief Enable APB2 peripherals clock.
AnnaBridge 143:86740a56073b 781 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 782 * APB2ENR TIM21EN LL_APB2_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 783 * APB2ENR TIM22EN LL_APB2_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 784 * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 785 * APB2ENR ADCEN LL_APB2_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 786 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 787 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 788 * APB2ENR DBGEN LL_APB2_GRP1_EnableClock
AnnaBridge 143:86740a56073b 789 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 790 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge 143:86740a56073b 791 * @arg @ref LL_APB2_GRP1_PERIPH_TIM21
AnnaBridge 143:86740a56073b 792 * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*)
AnnaBridge 143:86740a56073b 793 * @arg @ref LL_APB2_GRP1_PERIPH_FW
AnnaBridge 143:86740a56073b 794 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
AnnaBridge 143:86740a56073b 795 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge 143:86740a56073b 796 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
AnnaBridge 143:86740a56073b 797 * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
AnnaBridge 143:86740a56073b 798 *
AnnaBridge 143:86740a56073b 799 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 800 * @retval None
AnnaBridge 143:86740a56073b 801 */
AnnaBridge 143:86740a56073b 802 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge 143:86740a56073b 803 {
AnnaBridge 143:86740a56073b 804 __IO uint32_t tmpreg;
AnnaBridge 143:86740a56073b 805 SET_BIT(RCC->APB2ENR, Periphs);
AnnaBridge 143:86740a56073b 806 /* Delay after an RCC peripheral clock enabling */
AnnaBridge 143:86740a56073b 807 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
AnnaBridge 143:86740a56073b 808 (void)tmpreg;
AnnaBridge 143:86740a56073b 809 }
AnnaBridge 143:86740a56073b 810
AnnaBridge 143:86740a56073b 811 /**
AnnaBridge 143:86740a56073b 812 * @brief Check if APB2 peripheral clock is enabled or not
AnnaBridge 143:86740a56073b 813 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 814 * APB2ENR TIM21EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 815 * APB2ENR TIM22EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 816 * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 817 * APB2ENR ADCEN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 818 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 819 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 820 * APB2ENR DBGEN LL_APB2_GRP1_IsEnabledClock
AnnaBridge 143:86740a56073b 821 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 822 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge 143:86740a56073b 823 * @arg @ref LL_APB2_GRP1_PERIPH_TIM21
AnnaBridge 143:86740a56073b 824 * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*)
AnnaBridge 143:86740a56073b 825 * @arg @ref LL_APB2_GRP1_PERIPH_FW
AnnaBridge 143:86740a56073b 826 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
AnnaBridge 143:86740a56073b 827 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge 143:86740a56073b 828 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
AnnaBridge 143:86740a56073b 829 * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
AnnaBridge 143:86740a56073b 830 *
AnnaBridge 143:86740a56073b 831 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 832 * @retval State of Periphs (1 or 0).
AnnaBridge 143:86740a56073b 833 */
AnnaBridge 143:86740a56073b 834 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge 143:86740a56073b 835 {
AnnaBridge 143:86740a56073b 836 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
AnnaBridge 143:86740a56073b 837 }
AnnaBridge 143:86740a56073b 838
AnnaBridge 143:86740a56073b 839 /**
AnnaBridge 143:86740a56073b 840 * @brief Disable APB2 peripherals clock.
AnnaBridge 143:86740a56073b 841 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 842 * APB2ENR TIM21EN LL_APB2_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 843 * APB2ENR TIM22EN LL_APB2_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 844 * APB2ENR FWEN LL_APB2_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 845 * APB2ENR ADCEN LL_APB2_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 846 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 847 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 848 * APB2ENR DBGEN LL_APB2_GRP1_DisableClock
AnnaBridge 143:86740a56073b 849 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 850 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge 143:86740a56073b 851 * @arg @ref LL_APB2_GRP1_PERIPH_TIM21
AnnaBridge 143:86740a56073b 852 * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*)
AnnaBridge 143:86740a56073b 853 * @arg @ref LL_APB2_GRP1_PERIPH_FW
AnnaBridge 143:86740a56073b 854 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
AnnaBridge 143:86740a56073b 855 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge 143:86740a56073b 856 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
AnnaBridge 143:86740a56073b 857 * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
AnnaBridge 143:86740a56073b 858 *
AnnaBridge 143:86740a56073b 859 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 860 * @retval None
AnnaBridge 143:86740a56073b 861 */
AnnaBridge 143:86740a56073b 862 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge 143:86740a56073b 863 {
AnnaBridge 143:86740a56073b 864 CLEAR_BIT(RCC->APB2ENR, Periphs);
AnnaBridge 143:86740a56073b 865 }
AnnaBridge 143:86740a56073b 866
AnnaBridge 143:86740a56073b 867 /**
AnnaBridge 143:86740a56073b 868 * @brief Force APB2 peripherals reset.
AnnaBridge 143:86740a56073b 869 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 870 * APB2RSTR TIM21RST LL_APB2_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 871 * APB2RSTR TIM22RST LL_APB2_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 872 * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 873 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 874 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 875 * APB2RSTR DBGRST LL_APB2_GRP1_ForceReset
AnnaBridge 143:86740a56073b 876 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 877 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
AnnaBridge 143:86740a56073b 878 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge 143:86740a56073b 879 * @arg @ref LL_APB2_GRP1_PERIPH_TIM21
AnnaBridge 143:86740a56073b 880 * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*)
AnnaBridge 143:86740a56073b 881 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
AnnaBridge 143:86740a56073b 882 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge 143:86740a56073b 883 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
AnnaBridge 143:86740a56073b 884 * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
AnnaBridge 143:86740a56073b 885 *
AnnaBridge 143:86740a56073b 886 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 887 * @retval None
AnnaBridge 143:86740a56073b 888 */
AnnaBridge 143:86740a56073b 889 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge 143:86740a56073b 890 {
AnnaBridge 143:86740a56073b 891 SET_BIT(RCC->APB2RSTR, Periphs);
AnnaBridge 143:86740a56073b 892 }
AnnaBridge 143:86740a56073b 893
AnnaBridge 143:86740a56073b 894 /**
AnnaBridge 143:86740a56073b 895 * @brief Release APB2 peripherals reset.
AnnaBridge 143:86740a56073b 896 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 897 * APB2RSTR TIM21RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 898 * APB2RSTR TIM22RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 899 * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 900 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 901 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 902 * APB2RSTR DBGRST LL_APB2_GRP1_ReleaseReset
AnnaBridge 143:86740a56073b 903 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 904 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
AnnaBridge 143:86740a56073b 905 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge 143:86740a56073b 906 * @arg @ref LL_APB2_GRP1_PERIPH_TIM21
AnnaBridge 143:86740a56073b 907 * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*)
AnnaBridge 143:86740a56073b 908 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
AnnaBridge 143:86740a56073b 909 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge 143:86740a56073b 910 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
AnnaBridge 143:86740a56073b 911 * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
AnnaBridge 143:86740a56073b 912 *
AnnaBridge 143:86740a56073b 913 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 914 * @retval None
AnnaBridge 143:86740a56073b 915 */
AnnaBridge 143:86740a56073b 916 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge 143:86740a56073b 917 {
AnnaBridge 143:86740a56073b 918 CLEAR_BIT(RCC->APB2RSTR, Periphs);
AnnaBridge 143:86740a56073b 919 }
AnnaBridge 143:86740a56073b 920
AnnaBridge 143:86740a56073b 921 /**
AnnaBridge 143:86740a56073b 922 * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode.
AnnaBridge 143:86740a56073b 923 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 924 * APB2SMENR TIM21SMEN LL_APB2_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 925 * APB2SMENR TIM22SMEN LL_APB2_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 926 * APB2SMENR ADCSMEN LL_APB2_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 927 * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 928 * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 929 * APB2SMENR DBGSMEN LL_APB2_GRP1_EnableClockSleep
AnnaBridge 143:86740a56073b 930 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 931 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge 143:86740a56073b 932 * @arg @ref LL_APB2_GRP1_PERIPH_TIM21
AnnaBridge 143:86740a56073b 933 * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*)
AnnaBridge 143:86740a56073b 934 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
AnnaBridge 143:86740a56073b 935 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge 143:86740a56073b 936 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
AnnaBridge 143:86740a56073b 937 * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
AnnaBridge 143:86740a56073b 938 *
AnnaBridge 143:86740a56073b 939 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 940 * @retval None
AnnaBridge 143:86740a56073b 941 */
AnnaBridge 143:86740a56073b 942 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
AnnaBridge 143:86740a56073b 943 {
AnnaBridge 143:86740a56073b 944 __IO uint32_t tmpreg;
AnnaBridge 143:86740a56073b 945 SET_BIT(RCC->APB2SMENR, Periphs);
AnnaBridge 143:86740a56073b 946 /* Delay after an RCC peripheral clock enabling */
AnnaBridge 143:86740a56073b 947 tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
AnnaBridge 143:86740a56073b 948 (void)tmpreg;
AnnaBridge 143:86740a56073b 949 }
AnnaBridge 143:86740a56073b 950
AnnaBridge 143:86740a56073b 951 /**
AnnaBridge 143:86740a56073b 952 * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode.
AnnaBridge 143:86740a56073b 953 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 954 * APB2SMENR TIM21SMEN LL_APB2_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 955 * APB2SMENR TIM22SMEN LL_APB2_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 956 * APB2SMENR ADCSMEN LL_APB2_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 957 * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 958 * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 959 * APB2SMENR DBGSMEN LL_APB2_GRP1_DisableClockSleep
AnnaBridge 143:86740a56073b 960 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 961 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge 143:86740a56073b 962 * @arg @ref LL_APB2_GRP1_PERIPH_TIM21
AnnaBridge 143:86740a56073b 963 * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*)
AnnaBridge 143:86740a56073b 964 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
AnnaBridge 143:86740a56073b 965 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge 143:86740a56073b 966 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
AnnaBridge 143:86740a56073b 967 * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
AnnaBridge 143:86740a56073b 968 *
AnnaBridge 143:86740a56073b 969 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 970 * @retval None
AnnaBridge 143:86740a56073b 971 */
AnnaBridge 143:86740a56073b 972 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
AnnaBridge 143:86740a56073b 973 {
AnnaBridge 143:86740a56073b 974 CLEAR_BIT(RCC->APB2SMENR, Periphs);
AnnaBridge 143:86740a56073b 975 }
AnnaBridge 143:86740a56073b 976
AnnaBridge 143:86740a56073b 977 /**
AnnaBridge 143:86740a56073b 978 * @}
AnnaBridge 143:86740a56073b 979 */
AnnaBridge 143:86740a56073b 980 /** @defgroup BUS_LL_EF_IOP IOP
AnnaBridge 143:86740a56073b 981 * @{
AnnaBridge 143:86740a56073b 982 */
AnnaBridge 143:86740a56073b 983
AnnaBridge 143:86740a56073b 984 /**
AnnaBridge 143:86740a56073b 985 * @brief Enable IOP peripherals clock.
AnnaBridge 143:86740a56073b 986 * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 987 * IOPENR GPIOBEN LL_IOP_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 988 * IOPENR GPIOCEN LL_IOP_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 989 * IOPENR GPIODEN LL_IOP_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 990 * IOPENR GPIOEEN LL_IOP_GRP1_EnableClock\n
AnnaBridge 143:86740a56073b 991 * IOPENR GPIOHEN LL_IOP_GRP1_EnableClock
AnnaBridge 143:86740a56073b 992 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 993 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
AnnaBridge 143:86740a56073b 994 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
AnnaBridge 143:86740a56073b 995 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
AnnaBridge 143:86740a56073b 996 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
AnnaBridge 143:86740a56073b 997 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
AnnaBridge 143:86740a56073b 998 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
AnnaBridge 143:86740a56073b 999 *
AnnaBridge 143:86740a56073b 1000 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 1001 * @retval None
AnnaBridge 143:86740a56073b 1002 */
AnnaBridge 143:86740a56073b 1003 __STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge 143:86740a56073b 1004 {
AnnaBridge 143:86740a56073b 1005 __IO uint32_t tmpreg;
AnnaBridge 143:86740a56073b 1006 SET_BIT(RCC->IOPENR, Periphs);
AnnaBridge 143:86740a56073b 1007 /* Delay after an RCC peripheral clock enabling */
AnnaBridge 143:86740a56073b 1008 tmpreg = READ_BIT(RCC->IOPENR, Periphs);
AnnaBridge 143:86740a56073b 1009 (void)tmpreg;
AnnaBridge 143:86740a56073b 1010 }
AnnaBridge 143:86740a56073b 1011
AnnaBridge 143:86740a56073b 1012 /**
AnnaBridge 143:86740a56073b 1013 * @brief Check if IOP peripheral clock is enabled or not
AnnaBridge 143:86740a56073b 1014 * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 1015 * IOPENR GPIOBEN LL_IOP_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 1016 * IOPENR GPIOCEN LL_IOP_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 1017 * IOPENR GPIODEN LL_IOP_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 1018 * IOPENR GPIOEEN LL_IOP_GRP1_IsEnabledClock\n
AnnaBridge 143:86740a56073b 1019 * IOPENR GPIOHEN LL_IOP_GRP1_IsEnabledClock
AnnaBridge 143:86740a56073b 1020 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 1021 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
AnnaBridge 143:86740a56073b 1022 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
AnnaBridge 143:86740a56073b 1023 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
AnnaBridge 143:86740a56073b 1024 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
AnnaBridge 143:86740a56073b 1025 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
AnnaBridge 143:86740a56073b 1026 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
AnnaBridge 143:86740a56073b 1027 *
AnnaBridge 143:86740a56073b 1028 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 1029 * @retval State of Periphs (1 or 0).
AnnaBridge 143:86740a56073b 1030 */
AnnaBridge 143:86740a56073b 1031 __STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge 143:86740a56073b 1032 {
AnnaBridge 143:86740a56073b 1033 return (READ_BIT(RCC->IOPENR, Periphs) == Periphs);
AnnaBridge 143:86740a56073b 1034 }
AnnaBridge 143:86740a56073b 1035
AnnaBridge 143:86740a56073b 1036 /**
AnnaBridge 143:86740a56073b 1037 * @brief Disable IOP peripherals clock.
AnnaBridge 143:86740a56073b 1038 * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 1039 * IOPENR GPIOBEN LL_IOP_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 1040 * IOPENR GPIOCEN LL_IOP_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 1041 * IOPENR GPIODEN LL_IOP_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 1042 * IOPENR GPIOEEN LL_IOP_GRP1_DisableClock\n
AnnaBridge 143:86740a56073b 1043 * IOPENR GPIOHEN LL_IOP_GRP1_DisableClock
AnnaBridge 143:86740a56073b 1044 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 1045 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
AnnaBridge 143:86740a56073b 1046 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
AnnaBridge 143:86740a56073b 1047 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
AnnaBridge 143:86740a56073b 1048 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
AnnaBridge 143:86740a56073b 1049 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
AnnaBridge 143:86740a56073b 1050 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
AnnaBridge 143:86740a56073b 1051 *
AnnaBridge 143:86740a56073b 1052 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 1053 * @retval None
AnnaBridge 143:86740a56073b 1054 */
AnnaBridge 143:86740a56073b 1055 __STATIC_INLINE void LL_IOP_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge 143:86740a56073b 1056 {
AnnaBridge 143:86740a56073b 1057 CLEAR_BIT(RCC->IOPENR, Periphs);
AnnaBridge 143:86740a56073b 1058 }
AnnaBridge 143:86740a56073b 1059
AnnaBridge 143:86740a56073b 1060 /**
AnnaBridge 143:86740a56073b 1061 * @brief Disable IOP peripherals clock.
AnnaBridge 143:86740a56073b 1062 * @rmtoll IOPRSTR GPIOASMEN LL_IOP_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 1063 * IOPRSTR GPIOBSMEN LL_IOP_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 1064 * IOPRSTR GPIOCSMEN LL_IOP_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 1065 * IOPRSTR GPIODSMEN LL_IOP_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 1066 * IOPRSTR GPIOESMEN LL_IOP_GRP1_ForceReset\n
AnnaBridge 143:86740a56073b 1067 * IOPRSTR GPIOHSMEN LL_IOP_GRP1_ForceReset
AnnaBridge 143:86740a56073b 1068 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 1069 * @arg @ref LL_IOP_GRP1_PERIPH_ALL
AnnaBridge 143:86740a56073b 1070 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
AnnaBridge 143:86740a56073b 1071 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
AnnaBridge 143:86740a56073b 1072 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
AnnaBridge 143:86740a56073b 1073 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
AnnaBridge 143:86740a56073b 1074 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
AnnaBridge 143:86740a56073b 1075 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
AnnaBridge 143:86740a56073b 1076 *
AnnaBridge 143:86740a56073b 1077 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 1078 * @retval None
AnnaBridge 143:86740a56073b 1079 */
AnnaBridge 143:86740a56073b 1080 __STATIC_INLINE void LL_IOP_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge 143:86740a56073b 1081 {
AnnaBridge 143:86740a56073b 1082 SET_BIT(RCC->IOPRSTR, Periphs);
AnnaBridge 143:86740a56073b 1083 }
AnnaBridge 143:86740a56073b 1084
AnnaBridge 143:86740a56073b 1085 /**
AnnaBridge 143:86740a56073b 1086 * @brief Release IOP peripherals reset.
AnnaBridge 143:86740a56073b 1087 * @rmtoll IOPRSTR GPIOASMEN LL_IOP_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 1088 * IOPRSTR GPIOBSMEN LL_IOP_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 1089 * IOPRSTR GPIOCSMEN LL_IOP_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 1090 * IOPRSTR GPIODSMEN LL_IOP_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 1091 * IOPRSTR GPIOESMEN LL_IOP_GRP1_ReleaseReset\n
AnnaBridge 143:86740a56073b 1092 * IOPRSTR GPIOHSMEN LL_IOP_GRP1_ReleaseReset
AnnaBridge 143:86740a56073b 1093 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 1094 * @arg @ref LL_IOP_GRP1_PERIPH_ALL
AnnaBridge 143:86740a56073b 1095 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
AnnaBridge 143:86740a56073b 1096 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
AnnaBridge 143:86740a56073b 1097 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
AnnaBridge 143:86740a56073b 1098 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
AnnaBridge 143:86740a56073b 1099 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
AnnaBridge 143:86740a56073b 1100 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
AnnaBridge 143:86740a56073b 1101 *
AnnaBridge 143:86740a56073b 1102 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 1103 * @retval None
AnnaBridge 143:86740a56073b 1104 */
AnnaBridge 143:86740a56073b 1105 __STATIC_INLINE void LL_IOP_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge 143:86740a56073b 1106 {
AnnaBridge 143:86740a56073b 1107 CLEAR_BIT(RCC->IOPRSTR, Periphs);
AnnaBridge 143:86740a56073b 1108 }
AnnaBridge 143:86740a56073b 1109
AnnaBridge 143:86740a56073b 1110 /**
AnnaBridge 143:86740a56073b 1111 * @brief Enable IOP peripherals clock during Low Power (Sleep) mode.
AnnaBridge 143:86740a56073b 1112 * @rmtoll IOPSMENR GPIOARST LL_IOP_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 1113 * IOPSMENR GPIOBRST LL_IOP_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 1114 * IOPSMENR GPIOCRST LL_IOP_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 1115 * IOPSMENR GPIODRST LL_IOP_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 1116 * IOPSMENR GPIOERST LL_IOP_GRP1_EnableClockSleep\n
AnnaBridge 143:86740a56073b 1117 * IOPSMENR GPIOHRST LL_IOP_GRP1_EnableClockSleep
AnnaBridge 143:86740a56073b 1118 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 1119 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
AnnaBridge 143:86740a56073b 1120 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
AnnaBridge 143:86740a56073b 1121 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
AnnaBridge 143:86740a56073b 1122 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
AnnaBridge 143:86740a56073b 1123 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
AnnaBridge 143:86740a56073b 1124 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
AnnaBridge 143:86740a56073b 1125 *
AnnaBridge 143:86740a56073b 1126 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 1127 * @retval None
AnnaBridge 143:86740a56073b 1128 */
AnnaBridge 143:86740a56073b 1129 __STATIC_INLINE void LL_IOP_GRP1_EnableClockSleep(uint32_t Periphs)
AnnaBridge 143:86740a56073b 1130 {
AnnaBridge 143:86740a56073b 1131 __IO uint32_t tmpreg;
AnnaBridge 143:86740a56073b 1132 SET_BIT(RCC->IOPSMENR, Periphs);
AnnaBridge 143:86740a56073b 1133 /* Delay after an RCC peripheral clock enabling */
AnnaBridge 143:86740a56073b 1134 tmpreg = READ_BIT(RCC->IOPSMENR, Periphs);
AnnaBridge 143:86740a56073b 1135 (void)tmpreg;
AnnaBridge 143:86740a56073b 1136 }
AnnaBridge 143:86740a56073b 1137
AnnaBridge 143:86740a56073b 1138 /**
AnnaBridge 143:86740a56073b 1139 * @brief Disable IOP peripherals clock during Low Power (Sleep) mode.
AnnaBridge 143:86740a56073b 1140 * @rmtoll IOPSMENR GPIOARST LL_IOP_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 1141 * IOPSMENR GPIOBRST LL_IOP_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 1142 * IOPSMENR GPIOCRST LL_IOP_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 1143 * IOPSMENR GPIODRST LL_IOP_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 1144 * IOPSMENR GPIOERST LL_IOP_GRP1_DisableClockSleep\n
AnnaBridge 143:86740a56073b 1145 * IOPSMENR GPIOHRST LL_IOP_GRP1_DisableClockSleep
AnnaBridge 143:86740a56073b 1146 * @param Periphs This parameter can be a combination of the following values:
AnnaBridge 143:86740a56073b 1147 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
AnnaBridge 143:86740a56073b 1148 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
AnnaBridge 143:86740a56073b 1149 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
AnnaBridge 143:86740a56073b 1150 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
AnnaBridge 143:86740a56073b 1151 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
AnnaBridge 143:86740a56073b 1152 * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
AnnaBridge 143:86740a56073b 1153 *
AnnaBridge 143:86740a56073b 1154 * (*) value not defined in all devices.
AnnaBridge 143:86740a56073b 1155 * @retval None
AnnaBridge 143:86740a56073b 1156 */
AnnaBridge 143:86740a56073b 1157 __STATIC_INLINE void LL_IOP_GRP1_DisableClockSleep(uint32_t Periphs)
AnnaBridge 143:86740a56073b 1158 {
AnnaBridge 143:86740a56073b 1159 CLEAR_BIT(RCC->IOPSMENR, Periphs);
AnnaBridge 143:86740a56073b 1160 }
AnnaBridge 143:86740a56073b 1161
AnnaBridge 143:86740a56073b 1162 /**
AnnaBridge 143:86740a56073b 1163 * @}
AnnaBridge 143:86740a56073b 1164 */
AnnaBridge 143:86740a56073b 1165
AnnaBridge 143:86740a56073b 1166
AnnaBridge 143:86740a56073b 1167 /**
AnnaBridge 143:86740a56073b 1168 * @}
AnnaBridge 143:86740a56073b 1169 */
AnnaBridge 143:86740a56073b 1170
AnnaBridge 143:86740a56073b 1171 /**
AnnaBridge 143:86740a56073b 1172 * @}
AnnaBridge 143:86740a56073b 1173 */
AnnaBridge 143:86740a56073b 1174
AnnaBridge 143:86740a56073b 1175 #endif /* defined(RCC) */
AnnaBridge 143:86740a56073b 1176
AnnaBridge 143:86740a56073b 1177 /**
AnnaBridge 143:86740a56073b 1178 * @}
AnnaBridge 143:86740a56073b 1179 */
AnnaBridge 143:86740a56073b 1180
AnnaBridge 143:86740a56073b 1181 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 1182 }
AnnaBridge 143:86740a56073b 1183 #endif
AnnaBridge 143:86740a56073b 1184
AnnaBridge 143:86740a56073b 1185 #endif /* __STM32L0xx_LL_BUS_H */
AnnaBridge 143:86740a56073b 1186
AnnaBridge 143:86740a56073b 1187 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/