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TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_bus.h@143:86740a56073b, 2017-05-26 (annotated)
- Committer:
- AnnaBridge
- Date:
- Fri May 26 12:30:20 2017 +0100
- Revision:
- 143:86740a56073b
- Child:
- 167:84c0a372a020
Release 143 of the mbed library.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 143:86740a56073b | 1 | /** |
| AnnaBridge | 143:86740a56073b | 2 | ****************************************************************************** |
| AnnaBridge | 143:86740a56073b | 3 | * @file stm32l0xx_ll_bus.h |
| AnnaBridge | 143:86740a56073b | 4 | * @author MCD Application Team |
| AnnaBridge | 143:86740a56073b | 5 | * @version V1.7.0 |
| AnnaBridge | 143:86740a56073b | 6 | * @date 31-May-2016 |
| AnnaBridge | 143:86740a56073b | 7 | * @brief Header file of BUS LL module. |
| AnnaBridge | 143:86740a56073b | 8 | |
| AnnaBridge | 143:86740a56073b | 9 | @verbatim |
| AnnaBridge | 143:86740a56073b | 10 | ##### RCC Limitations ##### |
| AnnaBridge | 143:86740a56073b | 11 | ============================================================================== |
| AnnaBridge | 143:86740a56073b | 12 | [..] |
| AnnaBridge | 143:86740a56073b | 13 | A delay between an RCC peripheral clock enable and the effective peripheral |
| AnnaBridge | 143:86740a56073b | 14 | enabling should be taken into account in order to manage the peripheral read/write |
| AnnaBridge | 143:86740a56073b | 15 | from/to registers. |
| AnnaBridge | 143:86740a56073b | 16 | (+) This delay depends on the peripheral mapping. |
| AnnaBridge | 143:86740a56073b | 17 | (++) AHB & APB peripherals, 1 dummy read is necessary |
| AnnaBridge | 143:86740a56073b | 18 | |
| AnnaBridge | 143:86740a56073b | 19 | [..] |
| AnnaBridge | 143:86740a56073b | 20 | Workarounds: |
| AnnaBridge | 143:86740a56073b | 21 | (#) For AHB & APB peripherals, a dummy read to the peripheral register has been |
| AnnaBridge | 143:86740a56073b | 22 | inserted in each LL_{BUS}_GRP{x}_EnableClock() function. |
| AnnaBridge | 143:86740a56073b | 23 | |
| AnnaBridge | 143:86740a56073b | 24 | @endverbatim |
| AnnaBridge | 143:86740a56073b | 25 | ****************************************************************************** |
| AnnaBridge | 143:86740a56073b | 26 | * @attention |
| AnnaBridge | 143:86740a56073b | 27 | * |
| AnnaBridge | 143:86740a56073b | 28 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 143:86740a56073b | 29 | * |
| AnnaBridge | 143:86740a56073b | 30 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 143:86740a56073b | 31 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 143:86740a56073b | 32 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 143:86740a56073b | 33 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 143:86740a56073b | 34 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 143:86740a56073b | 35 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 143:86740a56073b | 36 | * and/or other materials provided with the distribution. |
| AnnaBridge | 143:86740a56073b | 37 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 143:86740a56073b | 38 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 143:86740a56073b | 39 | * without specific prior written permission. |
| AnnaBridge | 143:86740a56073b | 40 | * |
| AnnaBridge | 143:86740a56073b | 41 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 143:86740a56073b | 42 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 143:86740a56073b | 43 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 143:86740a56073b | 44 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 143:86740a56073b | 45 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 143:86740a56073b | 46 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 143:86740a56073b | 47 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 143:86740a56073b | 48 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 143:86740a56073b | 49 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 143:86740a56073b | 50 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 143:86740a56073b | 51 | * |
| AnnaBridge | 143:86740a56073b | 52 | ****************************************************************************** |
| AnnaBridge | 143:86740a56073b | 53 | */ |
| AnnaBridge | 143:86740a56073b | 54 | |
| AnnaBridge | 143:86740a56073b | 55 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 56 | #ifndef __STM32L0xx_LL_BUS_H |
| AnnaBridge | 143:86740a56073b | 57 | #define __STM32L0xx_LL_BUS_H |
| AnnaBridge | 143:86740a56073b | 58 | |
| AnnaBridge | 143:86740a56073b | 59 | #ifdef __cplusplus |
| AnnaBridge | 143:86740a56073b | 60 | extern "C" { |
| AnnaBridge | 143:86740a56073b | 61 | #endif |
| AnnaBridge | 143:86740a56073b | 62 | |
| AnnaBridge | 143:86740a56073b | 63 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 64 | #include "stm32l0xx.h" |
| AnnaBridge | 143:86740a56073b | 65 | |
| AnnaBridge | 143:86740a56073b | 66 | /** @addtogroup STM32L0xx_LL_Driver |
| AnnaBridge | 143:86740a56073b | 67 | * @{ |
| AnnaBridge | 143:86740a56073b | 68 | */ |
| AnnaBridge | 143:86740a56073b | 69 | |
| AnnaBridge | 143:86740a56073b | 70 | #if defined(RCC) |
| AnnaBridge | 143:86740a56073b | 71 | |
| AnnaBridge | 143:86740a56073b | 72 | /** @defgroup BUS_LL BUS |
| AnnaBridge | 143:86740a56073b | 73 | * @{ |
| AnnaBridge | 143:86740a56073b | 74 | */ |
| AnnaBridge | 143:86740a56073b | 75 | |
| AnnaBridge | 143:86740a56073b | 76 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 77 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 78 | |
| AnnaBridge | 143:86740a56073b | 79 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 80 | |
| AnnaBridge | 143:86740a56073b | 81 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 82 | |
| AnnaBridge | 143:86740a56073b | 83 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 84 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 85 | /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants |
| AnnaBridge | 143:86740a56073b | 86 | * @{ |
| AnnaBridge | 143:86740a56073b | 87 | */ |
| AnnaBridge | 143:86740a56073b | 88 | |
| AnnaBridge | 143:86740a56073b | 89 | /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH |
| AnnaBridge | 143:86740a56073b | 90 | * @{ |
| AnnaBridge | 143:86740a56073b | 91 | */ |
| AnnaBridge | 143:86740a56073b | 92 | #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU |
| AnnaBridge | 143:86740a56073b | 93 | #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN /*!< DMA1 clock enable */ |
| AnnaBridge | 143:86740a56073b | 94 | #define LL_AHB1_GRP1_PERIPH_MIF RCC_AHBENR_MIFEN /*!< MIF clock enable */ |
| AnnaBridge | 143:86740a56073b | 95 | #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN /*!< Sleep Mode SRAM clock enable */ |
| AnnaBridge | 143:86740a56073b | 96 | #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN /*!< CRC clock enable */ |
| AnnaBridge | 143:86740a56073b | 97 | #if defined(TSC) |
| AnnaBridge | 143:86740a56073b | 98 | #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN /*!< TSC clock enable */ |
| AnnaBridge | 143:86740a56073b | 99 | #endif /*TSC*/ |
| AnnaBridge | 143:86740a56073b | 100 | #if defined(RNG) |
| AnnaBridge | 143:86740a56073b | 101 | #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN /*!< RNG clock enable */ |
| AnnaBridge | 143:86740a56073b | 102 | #endif /*RNG*/ |
| AnnaBridge | 143:86740a56073b | 103 | #if defined(AES) |
| AnnaBridge | 143:86740a56073b | 104 | #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_CRYPEN /*!< CRYP clock enable */ |
| AnnaBridge | 143:86740a56073b | 105 | #endif /*AES*/ |
| AnnaBridge | 143:86740a56073b | 106 | /** |
| AnnaBridge | 143:86740a56073b | 107 | * @} |
| AnnaBridge | 143:86740a56073b | 108 | */ |
| AnnaBridge | 143:86740a56073b | 109 | |
| AnnaBridge | 143:86740a56073b | 110 | |
| AnnaBridge | 143:86740a56073b | 111 | /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH |
| AnnaBridge | 143:86740a56073b | 112 | * @{ |
| AnnaBridge | 143:86740a56073b | 113 | */ |
| AnnaBridge | 143:86740a56073b | 114 | #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU |
| AnnaBridge | 143:86740a56073b | 115 | #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN /*!< TIM2 clock enable */ |
| AnnaBridge | 143:86740a56073b | 116 | #if defined(TIM3) |
| AnnaBridge | 143:86740a56073b | 117 | #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN /*!< TIM3 clock enable */ |
| AnnaBridge | 143:86740a56073b | 118 | #endif |
| AnnaBridge | 143:86740a56073b | 119 | #if defined(TIM6) |
| AnnaBridge | 143:86740a56073b | 120 | #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN /*!< TIM6 clock enable */ |
| AnnaBridge | 143:86740a56073b | 121 | #endif |
| AnnaBridge | 143:86740a56073b | 122 | #if defined(TIM7) |
| AnnaBridge | 143:86740a56073b | 123 | #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN /*!< TIM7 clock enable */ |
| AnnaBridge | 143:86740a56073b | 124 | #endif |
| AnnaBridge | 143:86740a56073b | 125 | #if defined(LCD) |
| AnnaBridge | 143:86740a56073b | 126 | #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN /*!< LCD clock enable */ |
| AnnaBridge | 143:86740a56073b | 127 | #endif /*LCD*/ |
| AnnaBridge | 143:86740a56073b | 128 | #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN /*!< WWDG clock enable */ |
| AnnaBridge | 143:86740a56073b | 129 | #if defined(SPI2) |
| AnnaBridge | 143:86740a56073b | 130 | #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN /*!< SPI2 clock enable */ |
| AnnaBridge | 143:86740a56073b | 131 | #endif |
| AnnaBridge | 143:86740a56073b | 132 | #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN /*!< USART2 clock enable */ |
| AnnaBridge | 143:86740a56073b | 133 | #define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APB1ENR_LPUART1EN /*!< LPUART1 clock enable */ |
| AnnaBridge | 143:86740a56073b | 134 | #if defined(USART4) |
| AnnaBridge | 143:86740a56073b | 135 | #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN /*!< USART4 clock enable */ |
| AnnaBridge | 143:86740a56073b | 136 | #endif |
| AnnaBridge | 143:86740a56073b | 137 | #if defined(USART5) |
| AnnaBridge | 143:86740a56073b | 138 | #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN /*!< USART5 clock enable */ |
| AnnaBridge | 143:86740a56073b | 139 | #endif |
| AnnaBridge | 143:86740a56073b | 140 | #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN /*!< I2C1 clock enable */ |
| AnnaBridge | 143:86740a56073b | 141 | #if defined(I2C2) |
| AnnaBridge | 143:86740a56073b | 142 | #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN /*!< I2C2 clock enable */ |
| AnnaBridge | 143:86740a56073b | 143 | #endif |
| AnnaBridge | 143:86740a56073b | 144 | #if defined(USB) |
| AnnaBridge | 143:86740a56073b | 145 | #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN /*!< USB clock enable */ |
| AnnaBridge | 143:86740a56073b | 146 | #endif /*USB*/ |
| AnnaBridge | 143:86740a56073b | 147 | #if defined(CRS) |
| AnnaBridge | 143:86740a56073b | 148 | #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN /*!< CRS clock enable */ |
| AnnaBridge | 143:86740a56073b | 149 | #endif /*CRS*/ |
| AnnaBridge | 143:86740a56073b | 150 | #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN /*!< PWR clock enable */ |
| AnnaBridge | 143:86740a56073b | 151 | #if defined(DAC) |
| AnnaBridge | 143:86740a56073b | 152 | #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN /*!< DAC clock enable */ |
| AnnaBridge | 143:86740a56073b | 153 | #endif |
| AnnaBridge | 143:86740a56073b | 154 | #if defined(I2C3) |
| AnnaBridge | 143:86740a56073b | 155 | #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN /*!< I2C3 clock enable */ |
| AnnaBridge | 143:86740a56073b | 156 | #endif |
| AnnaBridge | 143:86740a56073b | 157 | #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN /*!< LPTIM1 clock enable */ |
| AnnaBridge | 143:86740a56073b | 158 | /** |
| AnnaBridge | 143:86740a56073b | 159 | * @} |
| AnnaBridge | 143:86740a56073b | 160 | */ |
| AnnaBridge | 143:86740a56073b | 161 | |
| AnnaBridge | 143:86740a56073b | 162 | |
| AnnaBridge | 143:86740a56073b | 163 | |
| AnnaBridge | 143:86740a56073b | 164 | |
| AnnaBridge | 143:86740a56073b | 165 | /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH |
| AnnaBridge | 143:86740a56073b | 166 | * @{ |
| AnnaBridge | 143:86740a56073b | 167 | */ |
| AnnaBridge | 143:86740a56073b | 168 | #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU |
| AnnaBridge | 143:86740a56073b | 169 | #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN /*!< SYSCFG clock enable */ |
| AnnaBridge | 143:86740a56073b | 170 | #define LL_APB2_GRP1_PERIPH_TIM21 RCC_APB2ENR_TIM21EN /*!< TIM21 clock enable */ |
| AnnaBridge | 143:86740a56073b | 171 | #if defined(TIM22) |
| AnnaBridge | 143:86740a56073b | 172 | #define LL_APB2_GRP1_PERIPH_TIM22 RCC_APB2ENR_TIM22EN /*!< TIM22 clock enable */ |
| AnnaBridge | 143:86740a56073b | 173 | #endif |
| AnnaBridge | 143:86740a56073b | 174 | #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN /*!< FireWall clock enable */ |
| AnnaBridge | 143:86740a56073b | 175 | #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN /*!< ADC1 clock enable */ |
| AnnaBridge | 143:86740a56073b | 176 | #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN /*!< SPI1 clock enable */ |
| AnnaBridge | 143:86740a56073b | 177 | #if defined(USART1) |
| AnnaBridge | 143:86740a56073b | 178 | #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN /*!< USART1 clock enable */ |
| AnnaBridge | 143:86740a56073b | 179 | #endif |
| AnnaBridge | 143:86740a56073b | 180 | #define LL_APB2_GRP1_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN /*!< DBGMCU clock enable */ |
| AnnaBridge | 143:86740a56073b | 181 | |
| AnnaBridge | 143:86740a56073b | 182 | /** |
| AnnaBridge | 143:86740a56073b | 183 | * @} |
| AnnaBridge | 143:86740a56073b | 184 | */ |
| AnnaBridge | 143:86740a56073b | 185 | |
| AnnaBridge | 143:86740a56073b | 186 | |
| AnnaBridge | 143:86740a56073b | 187 | |
| AnnaBridge | 143:86740a56073b | 188 | /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH |
| AnnaBridge | 143:86740a56073b | 189 | * @{ |
| AnnaBridge | 143:86740a56073b | 190 | */ |
| AnnaBridge | 143:86740a56073b | 191 | #define LL_IOP_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU |
| AnnaBridge | 143:86740a56073b | 192 | #define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN /*!< GPIO port A control */ |
| AnnaBridge | 143:86740a56073b | 193 | #define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN /*!< GPIO port B control */ |
| AnnaBridge | 143:86740a56073b | 194 | #define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN /*!< GPIO port C control */ |
| AnnaBridge | 143:86740a56073b | 195 | #if defined(GPIOD) |
| AnnaBridge | 143:86740a56073b | 196 | #define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN /*!< GPIO port D control */ |
| AnnaBridge | 143:86740a56073b | 197 | #endif /*GPIOD*/ |
| AnnaBridge | 143:86740a56073b | 198 | #if defined(GPIOE) |
| AnnaBridge | 143:86740a56073b | 199 | #define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN /*!< GPIO port H control */ |
| AnnaBridge | 143:86740a56073b | 200 | #endif /*GPIOE*/ |
| AnnaBridge | 143:86740a56073b | 201 | #if defined(GPIOH) |
| AnnaBridge | 143:86740a56073b | 202 | #define LL_IOP_GRP1_PERIPH_GPIOH RCC_IOPENR_GPIOHEN /*!< GPIO port H control */ |
| AnnaBridge | 143:86740a56073b | 203 | #endif /*GPIOH*/ |
| AnnaBridge | 143:86740a56073b | 204 | /** |
| AnnaBridge | 143:86740a56073b | 205 | * @} |
| AnnaBridge | 143:86740a56073b | 206 | */ |
| AnnaBridge | 143:86740a56073b | 207 | |
| AnnaBridge | 143:86740a56073b | 208 | |
| AnnaBridge | 143:86740a56073b | 209 | /** |
| AnnaBridge | 143:86740a56073b | 210 | * @} |
| AnnaBridge | 143:86740a56073b | 211 | */ |
| AnnaBridge | 143:86740a56073b | 212 | |
| AnnaBridge | 143:86740a56073b | 213 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 214 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 215 | /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions |
| AnnaBridge | 143:86740a56073b | 216 | * @{ |
| AnnaBridge | 143:86740a56073b | 217 | */ |
| AnnaBridge | 143:86740a56073b | 218 | |
| AnnaBridge | 143:86740a56073b | 219 | /** @defgroup BUS_LL_EF_AHB1 AHB1 |
| AnnaBridge | 143:86740a56073b | 220 | * @{ |
| AnnaBridge | 143:86740a56073b | 221 | */ |
| AnnaBridge | 143:86740a56073b | 222 | |
| AnnaBridge | 143:86740a56073b | 223 | /** |
| AnnaBridge | 143:86740a56073b | 224 | * @brief Enable AHB1 peripherals clock. |
| AnnaBridge | 143:86740a56073b | 225 | * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 226 | * AHBENR MIFEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 227 | * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 228 | * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 229 | * AHBENR RNGEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 230 | * AHBENR CRYPEN LL_AHB1_GRP1_EnableClock |
| AnnaBridge | 143:86740a56073b | 231 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 232 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 143:86740a56073b | 233 | * @arg @ref LL_AHB1_GRP1_PERIPH_MIF |
| AnnaBridge | 143:86740a56073b | 234 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 143:86740a56073b | 235 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) |
| AnnaBridge | 143:86740a56073b | 236 | * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) |
| AnnaBridge | 143:86740a56073b | 237 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 143:86740a56073b | 238 | * |
| AnnaBridge | 143:86740a56073b | 239 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 240 | * @retval None |
| AnnaBridge | 143:86740a56073b | 241 | */ |
| AnnaBridge | 143:86740a56073b | 242 | __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 243 | { |
| AnnaBridge | 143:86740a56073b | 244 | __IO uint32_t tmpreg; |
| AnnaBridge | 143:86740a56073b | 245 | SET_BIT(RCC->AHBENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 246 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 143:86740a56073b | 247 | tmpreg = READ_BIT(RCC->AHBENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 248 | (void)tmpreg; |
| AnnaBridge | 143:86740a56073b | 249 | } |
| AnnaBridge | 143:86740a56073b | 250 | |
| AnnaBridge | 143:86740a56073b | 251 | /** |
| AnnaBridge | 143:86740a56073b | 252 | * @brief Check if AHB1 peripheral clock is enabled or not |
| AnnaBridge | 143:86740a56073b | 253 | * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 254 | * AHBENR MIFEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 255 | * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 256 | * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 257 | * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 258 | * AHBENR CRYPEN LL_AHB1_GRP1_IsEnabledClock |
| AnnaBridge | 143:86740a56073b | 259 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 260 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 143:86740a56073b | 261 | * @arg @ref LL_AHB1_GRP1_PERIPH_MIF |
| AnnaBridge | 143:86740a56073b | 262 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 143:86740a56073b | 263 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) |
| AnnaBridge | 143:86740a56073b | 264 | * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) |
| AnnaBridge | 143:86740a56073b | 265 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 143:86740a56073b | 266 | * |
| AnnaBridge | 143:86740a56073b | 267 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 268 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 143:86740a56073b | 269 | */ |
| AnnaBridge | 143:86740a56073b | 270 | __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 271 | { |
| AnnaBridge | 143:86740a56073b | 272 | return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); |
| AnnaBridge | 143:86740a56073b | 273 | } |
| AnnaBridge | 143:86740a56073b | 274 | |
| AnnaBridge | 143:86740a56073b | 275 | /** |
| AnnaBridge | 143:86740a56073b | 276 | * @brief Disable AHB1 peripherals clock. |
| AnnaBridge | 143:86740a56073b | 277 | * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 278 | * AHBENR MIFEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 279 | * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 280 | * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 281 | * AHBENR RNGEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 282 | * AHBENR CRYPEN LL_AHB1_GRP1_DisableClock |
| AnnaBridge | 143:86740a56073b | 283 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 284 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 143:86740a56073b | 285 | * @arg @ref LL_AHB1_GRP1_PERIPH_MIF |
| AnnaBridge | 143:86740a56073b | 286 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 143:86740a56073b | 287 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) |
| AnnaBridge | 143:86740a56073b | 288 | * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) |
| AnnaBridge | 143:86740a56073b | 289 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 143:86740a56073b | 290 | * |
| AnnaBridge | 143:86740a56073b | 291 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 292 | * @retval None |
| AnnaBridge | 143:86740a56073b | 293 | */ |
| AnnaBridge | 143:86740a56073b | 294 | __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 295 | { |
| AnnaBridge | 143:86740a56073b | 296 | CLEAR_BIT(RCC->AHBENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 297 | } |
| AnnaBridge | 143:86740a56073b | 298 | |
| AnnaBridge | 143:86740a56073b | 299 | /** |
| AnnaBridge | 143:86740a56073b | 300 | * @brief Force AHB1 peripherals reset. |
| AnnaBridge | 143:86740a56073b | 301 | * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 302 | * AHBRSTR MIFRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 303 | * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 304 | * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 305 | * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 306 | * AHBRSTR CRYPRST LL_AHB1_GRP1_ForceReset |
| AnnaBridge | 143:86740a56073b | 307 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 308 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
| AnnaBridge | 143:86740a56073b | 309 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 143:86740a56073b | 310 | * @arg @ref LL_AHB1_GRP1_PERIPH_MIF |
| AnnaBridge | 143:86740a56073b | 311 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 143:86740a56073b | 312 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) |
| AnnaBridge | 143:86740a56073b | 313 | * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) |
| AnnaBridge | 143:86740a56073b | 314 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 143:86740a56073b | 315 | * |
| AnnaBridge | 143:86740a56073b | 316 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 317 | * @retval None |
| AnnaBridge | 143:86740a56073b | 318 | */ |
| AnnaBridge | 143:86740a56073b | 319 | __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 320 | { |
| AnnaBridge | 143:86740a56073b | 321 | SET_BIT(RCC->AHBRSTR, Periphs); |
| AnnaBridge | 143:86740a56073b | 322 | } |
| AnnaBridge | 143:86740a56073b | 323 | |
| AnnaBridge | 143:86740a56073b | 324 | /** |
| AnnaBridge | 143:86740a56073b | 325 | * @brief Release AHB1 peripherals reset. |
| AnnaBridge | 143:86740a56073b | 326 | * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 327 | * AHBRSTR MIFRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 328 | * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 329 | * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 330 | * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 331 | * AHBRSTR CRYPRST LL_AHB1_GRP1_ReleaseReset |
| AnnaBridge | 143:86740a56073b | 332 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 333 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
| AnnaBridge | 143:86740a56073b | 334 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 143:86740a56073b | 335 | * @arg @ref LL_AHB1_GRP1_PERIPH_MIF |
| AnnaBridge | 143:86740a56073b | 336 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 143:86740a56073b | 337 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) |
| AnnaBridge | 143:86740a56073b | 338 | * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) |
| AnnaBridge | 143:86740a56073b | 339 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 143:86740a56073b | 340 | * |
| AnnaBridge | 143:86740a56073b | 341 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 342 | * @retval None |
| AnnaBridge | 143:86740a56073b | 343 | */ |
| AnnaBridge | 143:86740a56073b | 344 | __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 345 | { |
| AnnaBridge | 143:86740a56073b | 346 | CLEAR_BIT(RCC->AHBRSTR, Periphs); |
| AnnaBridge | 143:86740a56073b | 347 | } |
| AnnaBridge | 143:86740a56073b | 348 | |
| AnnaBridge | 143:86740a56073b | 349 | /** |
| AnnaBridge | 143:86740a56073b | 350 | * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. |
| AnnaBridge | 143:86740a56073b | 351 | * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 352 | * AHBSMENR MIFSMEN LL_AHB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 353 | * AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 354 | * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 355 | * AHBSMENR TSCSMEN LL_AHB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 356 | * AHBSMENR RNGSMEN LL_AHB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 357 | * AHBSMENR CRYPSMEN LL_AHB1_GRP1_EnableClockSleep |
| AnnaBridge | 143:86740a56073b | 358 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 359 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 143:86740a56073b | 360 | * @arg @ref LL_AHB1_GRP1_PERIPH_MIF |
| AnnaBridge | 143:86740a56073b | 361 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM |
| AnnaBridge | 143:86740a56073b | 362 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 143:86740a56073b | 363 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) |
| AnnaBridge | 143:86740a56073b | 364 | * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) |
| AnnaBridge | 143:86740a56073b | 365 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 143:86740a56073b | 366 | * |
| AnnaBridge | 143:86740a56073b | 367 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 368 | * @retval None |
| AnnaBridge | 143:86740a56073b | 369 | */ |
| AnnaBridge | 143:86740a56073b | 370 | __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 371 | { |
| AnnaBridge | 143:86740a56073b | 372 | __IO uint32_t tmpreg; |
| AnnaBridge | 143:86740a56073b | 373 | SET_BIT(RCC->AHBSMENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 374 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 143:86740a56073b | 375 | tmpreg = READ_BIT(RCC->AHBSMENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 376 | (void)tmpreg; |
| AnnaBridge | 143:86740a56073b | 377 | } |
| AnnaBridge | 143:86740a56073b | 378 | |
| AnnaBridge | 143:86740a56073b | 379 | /** |
| AnnaBridge | 143:86740a56073b | 380 | * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. |
| AnnaBridge | 143:86740a56073b | 381 | * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 382 | * AHBSMENR MIFSMEN LL_AHB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 383 | * AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 384 | * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 385 | * AHBSMENR TSCSMEN LL_AHB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 386 | * AHBSMENR RNGSMEN LL_AHB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 387 | * AHBSMENR CRYPSMEN LL_AHB1_GRP1_DisableClockSleep |
| AnnaBridge | 143:86740a56073b | 388 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 389 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 143:86740a56073b | 390 | * @arg @ref LL_AHB1_GRP1_PERIPH_MIF |
| AnnaBridge | 143:86740a56073b | 391 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM |
| AnnaBridge | 143:86740a56073b | 392 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 143:86740a56073b | 393 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) |
| AnnaBridge | 143:86740a56073b | 394 | * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) |
| AnnaBridge | 143:86740a56073b | 395 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 143:86740a56073b | 396 | * |
| AnnaBridge | 143:86740a56073b | 397 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 398 | * @retval None |
| AnnaBridge | 143:86740a56073b | 399 | */ |
| AnnaBridge | 143:86740a56073b | 400 | __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 401 | { |
| AnnaBridge | 143:86740a56073b | 402 | CLEAR_BIT(RCC->AHBSMENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 403 | } |
| AnnaBridge | 143:86740a56073b | 404 | |
| AnnaBridge | 143:86740a56073b | 405 | /** |
| AnnaBridge | 143:86740a56073b | 406 | * @} |
| AnnaBridge | 143:86740a56073b | 407 | */ |
| AnnaBridge | 143:86740a56073b | 408 | |
| AnnaBridge | 143:86740a56073b | 409 | /** @defgroup BUS_LL_EF_APB1 APB1 |
| AnnaBridge | 143:86740a56073b | 410 | * @{ |
| AnnaBridge | 143:86740a56073b | 411 | */ |
| AnnaBridge | 143:86740a56073b | 412 | |
| AnnaBridge | 143:86740a56073b | 413 | /** |
| AnnaBridge | 143:86740a56073b | 414 | * @brief Enable APB1 peripherals clock. |
| AnnaBridge | 143:86740a56073b | 415 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 416 | * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 417 | * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 418 | * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 419 | * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 420 | * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 421 | * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 422 | * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 423 | * APB1ENR LPUART1EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 424 | * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 425 | * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 426 | * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 427 | * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 428 | * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 429 | * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 430 | * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 431 | * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 432 | * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 433 | * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock |
| AnnaBridge | 143:86740a56073b | 434 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 435 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 143:86740a56073b | 436 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| AnnaBridge | 143:86740a56073b | 437 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| AnnaBridge | 143:86740a56073b | 438 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| AnnaBridge | 143:86740a56073b | 439 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| AnnaBridge | 143:86740a56073b | 440 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 143:86740a56073b | 441 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 143:86740a56073b | 442 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 143:86740a56073b | 443 | * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 |
| AnnaBridge | 143:86740a56073b | 444 | * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) |
| AnnaBridge | 143:86740a56073b | 445 | * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) |
| AnnaBridge | 143:86740a56073b | 446 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 143:86740a56073b | 447 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 143:86740a56073b | 448 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 143:86740a56073b | 449 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| AnnaBridge | 143:86740a56073b | 450 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 143:86740a56073b | 451 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| AnnaBridge | 143:86740a56073b | 452 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| AnnaBridge | 143:86740a56073b | 453 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| AnnaBridge | 143:86740a56073b | 454 | * |
| AnnaBridge | 143:86740a56073b | 455 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 456 | * @retval None |
| AnnaBridge | 143:86740a56073b | 457 | */ |
| AnnaBridge | 143:86740a56073b | 458 | __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 459 | { |
| AnnaBridge | 143:86740a56073b | 460 | __IO uint32_t tmpreg; |
| AnnaBridge | 143:86740a56073b | 461 | SET_BIT(RCC->APB1ENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 462 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 143:86740a56073b | 463 | tmpreg = READ_BIT(RCC->APB1ENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 464 | (void)tmpreg; |
| AnnaBridge | 143:86740a56073b | 465 | } |
| AnnaBridge | 143:86740a56073b | 466 | |
| AnnaBridge | 143:86740a56073b | 467 | /** |
| AnnaBridge | 143:86740a56073b | 468 | * @brief Check if APB1 peripheral clock is enabled or not |
| AnnaBridge | 143:86740a56073b | 469 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 470 | * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 471 | * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 472 | * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 473 | * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 474 | * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 475 | * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 476 | * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 477 | * APB1ENR LPUART1EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 478 | * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 479 | * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 480 | * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 481 | * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 482 | * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 483 | * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 484 | * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 485 | * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 486 | * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 487 | * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock |
| AnnaBridge | 143:86740a56073b | 488 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 489 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 143:86740a56073b | 490 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| AnnaBridge | 143:86740a56073b | 491 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| AnnaBridge | 143:86740a56073b | 492 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| AnnaBridge | 143:86740a56073b | 493 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| AnnaBridge | 143:86740a56073b | 494 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 143:86740a56073b | 495 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 143:86740a56073b | 496 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 143:86740a56073b | 497 | * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 |
| AnnaBridge | 143:86740a56073b | 498 | * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) |
| AnnaBridge | 143:86740a56073b | 499 | * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) |
| AnnaBridge | 143:86740a56073b | 500 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 143:86740a56073b | 501 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 143:86740a56073b | 502 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 143:86740a56073b | 503 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| AnnaBridge | 143:86740a56073b | 504 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 143:86740a56073b | 505 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| AnnaBridge | 143:86740a56073b | 506 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| AnnaBridge | 143:86740a56073b | 507 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| AnnaBridge | 143:86740a56073b | 508 | * |
| AnnaBridge | 143:86740a56073b | 509 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 510 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 143:86740a56073b | 511 | */ |
| AnnaBridge | 143:86740a56073b | 512 | __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 513 | { |
| AnnaBridge | 143:86740a56073b | 514 | return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); |
| AnnaBridge | 143:86740a56073b | 515 | } |
| AnnaBridge | 143:86740a56073b | 516 | |
| AnnaBridge | 143:86740a56073b | 517 | /** |
| AnnaBridge | 143:86740a56073b | 518 | * @brief Disable APB1 peripherals clock. |
| AnnaBridge | 143:86740a56073b | 519 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 520 | * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 521 | * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 522 | * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 523 | * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 524 | * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 525 | * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 526 | * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 527 | * APB1ENR LPUART1EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 528 | * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 529 | * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 530 | * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 531 | * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 532 | * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 533 | * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 534 | * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 535 | * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 536 | * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 537 | * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock |
| AnnaBridge | 143:86740a56073b | 538 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 539 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 143:86740a56073b | 540 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| AnnaBridge | 143:86740a56073b | 541 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| AnnaBridge | 143:86740a56073b | 542 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| AnnaBridge | 143:86740a56073b | 543 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| AnnaBridge | 143:86740a56073b | 544 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 143:86740a56073b | 545 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 143:86740a56073b | 546 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 143:86740a56073b | 547 | * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 |
| AnnaBridge | 143:86740a56073b | 548 | * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) |
| AnnaBridge | 143:86740a56073b | 549 | * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) |
| AnnaBridge | 143:86740a56073b | 550 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 143:86740a56073b | 551 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 143:86740a56073b | 552 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 143:86740a56073b | 553 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| AnnaBridge | 143:86740a56073b | 554 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 143:86740a56073b | 555 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| AnnaBridge | 143:86740a56073b | 556 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| AnnaBridge | 143:86740a56073b | 557 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| AnnaBridge | 143:86740a56073b | 558 | * |
| AnnaBridge | 143:86740a56073b | 559 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 560 | * @retval None |
| AnnaBridge | 143:86740a56073b | 561 | */ |
| AnnaBridge | 143:86740a56073b | 562 | __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 563 | { |
| AnnaBridge | 143:86740a56073b | 564 | CLEAR_BIT(RCC->APB1ENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 565 | } |
| AnnaBridge | 143:86740a56073b | 566 | |
| AnnaBridge | 143:86740a56073b | 567 | /** |
| AnnaBridge | 143:86740a56073b | 568 | * @brief Force APB1 peripherals reset. |
| AnnaBridge | 143:86740a56073b | 569 | * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 570 | * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 571 | * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 572 | * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 573 | * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 574 | * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 575 | * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 576 | * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 577 | * APB1RSTR LPUART1RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 578 | * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 579 | * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 580 | * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 581 | * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 582 | * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 583 | * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 584 | * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 585 | * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 586 | * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 587 | * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset |
| AnnaBridge | 143:86740a56073b | 588 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 589 | * @arg @ref LL_APB1_GRP1_PERIPH_ALL |
| AnnaBridge | 143:86740a56073b | 590 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 143:86740a56073b | 591 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| AnnaBridge | 143:86740a56073b | 592 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| AnnaBridge | 143:86740a56073b | 593 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| AnnaBridge | 143:86740a56073b | 594 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| AnnaBridge | 143:86740a56073b | 595 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 143:86740a56073b | 596 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 143:86740a56073b | 597 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 143:86740a56073b | 598 | * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 |
| AnnaBridge | 143:86740a56073b | 599 | * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) |
| AnnaBridge | 143:86740a56073b | 600 | * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) |
| AnnaBridge | 143:86740a56073b | 601 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 143:86740a56073b | 602 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 143:86740a56073b | 603 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 143:86740a56073b | 604 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| AnnaBridge | 143:86740a56073b | 605 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 143:86740a56073b | 606 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| AnnaBridge | 143:86740a56073b | 607 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| AnnaBridge | 143:86740a56073b | 608 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| AnnaBridge | 143:86740a56073b | 609 | * |
| AnnaBridge | 143:86740a56073b | 610 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 611 | * @retval None |
| AnnaBridge | 143:86740a56073b | 612 | */ |
| AnnaBridge | 143:86740a56073b | 613 | __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 614 | { |
| AnnaBridge | 143:86740a56073b | 615 | SET_BIT(RCC->APB1RSTR, Periphs); |
| AnnaBridge | 143:86740a56073b | 616 | } |
| AnnaBridge | 143:86740a56073b | 617 | |
| AnnaBridge | 143:86740a56073b | 618 | /** |
| AnnaBridge | 143:86740a56073b | 619 | * @brief Release APB1 peripherals reset. |
| AnnaBridge | 143:86740a56073b | 620 | * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 621 | * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 622 | * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 623 | * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 624 | * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 625 | * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 626 | * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 627 | * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 628 | * APB1RSTR LPUART1RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 629 | * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 630 | * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 631 | * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 632 | * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 633 | * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 634 | * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 635 | * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 636 | * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 637 | * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 638 | * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset |
| AnnaBridge | 143:86740a56073b | 639 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 640 | * @arg @ref LL_APB1_GRP1_PERIPH_ALL |
| AnnaBridge | 143:86740a56073b | 641 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 143:86740a56073b | 642 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| AnnaBridge | 143:86740a56073b | 643 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| AnnaBridge | 143:86740a56073b | 644 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| AnnaBridge | 143:86740a56073b | 645 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| AnnaBridge | 143:86740a56073b | 646 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 143:86740a56073b | 647 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 143:86740a56073b | 648 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 143:86740a56073b | 649 | * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 |
| AnnaBridge | 143:86740a56073b | 650 | * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) |
| AnnaBridge | 143:86740a56073b | 651 | * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) |
| AnnaBridge | 143:86740a56073b | 652 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 143:86740a56073b | 653 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 143:86740a56073b | 654 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 143:86740a56073b | 655 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| AnnaBridge | 143:86740a56073b | 656 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 143:86740a56073b | 657 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| AnnaBridge | 143:86740a56073b | 658 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| AnnaBridge | 143:86740a56073b | 659 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| AnnaBridge | 143:86740a56073b | 660 | * |
| AnnaBridge | 143:86740a56073b | 661 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 662 | * @retval None |
| AnnaBridge | 143:86740a56073b | 663 | */ |
| AnnaBridge | 143:86740a56073b | 664 | __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 665 | { |
| AnnaBridge | 143:86740a56073b | 666 | CLEAR_BIT(RCC->APB1RSTR, Periphs); |
| AnnaBridge | 143:86740a56073b | 667 | } |
| AnnaBridge | 143:86740a56073b | 668 | |
| AnnaBridge | 143:86740a56073b | 669 | /** |
| AnnaBridge | 143:86740a56073b | 670 | * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. |
| AnnaBridge | 143:86740a56073b | 671 | * @rmtoll APB1SMENR TIM2SMEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 672 | * APB1SMENR TIM3SMEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 673 | * APB1SMENR TIM6SMEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 674 | * APB1SMENR TIM7SMEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 675 | * APB1SMENR LCDSMEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 676 | * APB1SMENR WWDGSMEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 677 | * APB1SMENR SPI2SMEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 678 | * APB1SMENR USART2SMEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 679 | * APB1SMENR LPUART1SMEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 680 | * APB1SMENR USART4SMEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 681 | * APB1SMENR USART5SMEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 682 | * APB1SMENR I2C1SMEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 683 | * APB1SMENR I2C2SMEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 684 | * APB1SMENR USBSMEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 685 | * APB1SMENR CRSSMEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 686 | * APB1SMENR PWRSMEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 687 | * APB1SMENR DACSMEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 688 | * APB1SMENR I2C3SMEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 689 | * APB1SMENR LPTIM1SMEN LL_APB1_GRP1_EnableClockSleep |
| AnnaBridge | 143:86740a56073b | 690 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 691 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 143:86740a56073b | 692 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| AnnaBridge | 143:86740a56073b | 693 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| AnnaBridge | 143:86740a56073b | 694 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| AnnaBridge | 143:86740a56073b | 695 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| AnnaBridge | 143:86740a56073b | 696 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 143:86740a56073b | 697 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 143:86740a56073b | 698 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 143:86740a56073b | 699 | * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 |
| AnnaBridge | 143:86740a56073b | 700 | * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) |
| AnnaBridge | 143:86740a56073b | 701 | * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) |
| AnnaBridge | 143:86740a56073b | 702 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 143:86740a56073b | 703 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 143:86740a56073b | 704 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 143:86740a56073b | 705 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| AnnaBridge | 143:86740a56073b | 706 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 143:86740a56073b | 707 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| AnnaBridge | 143:86740a56073b | 708 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| AnnaBridge | 143:86740a56073b | 709 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| AnnaBridge | 143:86740a56073b | 710 | * |
| AnnaBridge | 143:86740a56073b | 711 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 712 | * @retval None |
| AnnaBridge | 143:86740a56073b | 713 | */ |
| AnnaBridge | 143:86740a56073b | 714 | __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 715 | { |
| AnnaBridge | 143:86740a56073b | 716 | __IO uint32_t tmpreg; |
| AnnaBridge | 143:86740a56073b | 717 | SET_BIT(RCC->APB1SMENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 718 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 143:86740a56073b | 719 | tmpreg = READ_BIT(RCC->APB1SMENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 720 | (void)tmpreg; |
| AnnaBridge | 143:86740a56073b | 721 | } |
| AnnaBridge | 143:86740a56073b | 722 | |
| AnnaBridge | 143:86740a56073b | 723 | /** |
| AnnaBridge | 143:86740a56073b | 724 | * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. |
| AnnaBridge | 143:86740a56073b | 725 | * @rmtoll APB1SMENR TIM2SMEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 726 | * APB1SMENR TIM3SMEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 727 | * APB1SMENR TIM6SMEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 728 | * APB1SMENR TIM7SMEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 729 | * APB1SMENR LCDSMEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 730 | * APB1SMENR WWDGSMEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 731 | * APB1SMENR SPI2SMEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 732 | * APB1SMENR USART2SMEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 733 | * APB1SMENR LPUART1SMEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 734 | * APB1SMENR USART4SMEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 735 | * APB1SMENR USART5SMEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 736 | * APB1SMENR I2C1SMEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 737 | * APB1SMENR I2C2SMEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 738 | * APB1SMENR USBSMEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 739 | * APB1SMENR CRSSMEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 740 | * APB1SMENR PWRSMEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 741 | * APB1SMENR DACSMEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 742 | * APB1SMENR I2C3SMEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 743 | * APB1SMENR LPTIM1SMEN LL_APB1_GRP1_DisableClockSleep |
| AnnaBridge | 143:86740a56073b | 744 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 745 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 143:86740a56073b | 746 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| AnnaBridge | 143:86740a56073b | 747 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| AnnaBridge | 143:86740a56073b | 748 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| AnnaBridge | 143:86740a56073b | 749 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| AnnaBridge | 143:86740a56073b | 750 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 143:86740a56073b | 751 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 143:86740a56073b | 752 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 143:86740a56073b | 753 | * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 |
| AnnaBridge | 143:86740a56073b | 754 | * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) |
| AnnaBridge | 143:86740a56073b | 755 | * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) |
| AnnaBridge | 143:86740a56073b | 756 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 143:86740a56073b | 757 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 143:86740a56073b | 758 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 143:86740a56073b | 759 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| AnnaBridge | 143:86740a56073b | 760 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 143:86740a56073b | 761 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| AnnaBridge | 143:86740a56073b | 762 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| AnnaBridge | 143:86740a56073b | 763 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| AnnaBridge | 143:86740a56073b | 764 | * |
| AnnaBridge | 143:86740a56073b | 765 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 766 | * @retval None |
| AnnaBridge | 143:86740a56073b | 767 | */ |
| AnnaBridge | 143:86740a56073b | 768 | __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 769 | { |
| AnnaBridge | 143:86740a56073b | 770 | CLEAR_BIT(RCC->APB1SMENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 771 | } |
| AnnaBridge | 143:86740a56073b | 772 | |
| AnnaBridge | 143:86740a56073b | 773 | /** |
| AnnaBridge | 143:86740a56073b | 774 | * @} |
| AnnaBridge | 143:86740a56073b | 775 | */ |
| AnnaBridge | 143:86740a56073b | 776 | |
| AnnaBridge | 143:86740a56073b | 777 | /** @defgroup BUS_LL_EF_APB2 APB2 |
| AnnaBridge | 143:86740a56073b | 778 | * @{ |
| AnnaBridge | 143:86740a56073b | 779 | */ |
| AnnaBridge | 143:86740a56073b | 780 | |
| AnnaBridge | 143:86740a56073b | 781 | /** |
| AnnaBridge | 143:86740a56073b | 782 | * @brief Enable APB2 peripherals clock. |
| AnnaBridge | 143:86740a56073b | 783 | * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 784 | * APB2ENR TIM21EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 785 | * APB2ENR TIM22EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 786 | * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 787 | * APB2ENR ADCEN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 788 | * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 789 | * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 790 | * APB2ENR DBGEN LL_APB2_GRP1_EnableClock |
| AnnaBridge | 143:86740a56073b | 791 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 792 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 143:86740a56073b | 793 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 |
| AnnaBridge | 143:86740a56073b | 794 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) |
| AnnaBridge | 143:86740a56073b | 795 | * @arg @ref LL_APB2_GRP1_PERIPH_FW |
| AnnaBridge | 143:86740a56073b | 796 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 143:86740a56073b | 797 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 143:86740a56073b | 798 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) |
| AnnaBridge | 143:86740a56073b | 799 | * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU |
| AnnaBridge | 143:86740a56073b | 800 | * |
| AnnaBridge | 143:86740a56073b | 801 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 802 | * @retval None |
| AnnaBridge | 143:86740a56073b | 803 | */ |
| AnnaBridge | 143:86740a56073b | 804 | __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 805 | { |
| AnnaBridge | 143:86740a56073b | 806 | __IO uint32_t tmpreg; |
| AnnaBridge | 143:86740a56073b | 807 | SET_BIT(RCC->APB2ENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 808 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 143:86740a56073b | 809 | tmpreg = READ_BIT(RCC->APB2ENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 810 | (void)tmpreg; |
| AnnaBridge | 143:86740a56073b | 811 | } |
| AnnaBridge | 143:86740a56073b | 812 | |
| AnnaBridge | 143:86740a56073b | 813 | /** |
| AnnaBridge | 143:86740a56073b | 814 | * @brief Check if APB2 peripheral clock is enabled or not |
| AnnaBridge | 143:86740a56073b | 815 | * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 816 | * APB2ENR TIM21EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 817 | * APB2ENR TIM22EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 818 | * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 819 | * APB2ENR ADCEN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 820 | * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 821 | * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 822 | * APB2ENR DBGEN LL_APB2_GRP1_IsEnabledClock |
| AnnaBridge | 143:86740a56073b | 823 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 824 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 143:86740a56073b | 825 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 |
| AnnaBridge | 143:86740a56073b | 826 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) |
| AnnaBridge | 143:86740a56073b | 827 | * @arg @ref LL_APB2_GRP1_PERIPH_FW |
| AnnaBridge | 143:86740a56073b | 828 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 143:86740a56073b | 829 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 143:86740a56073b | 830 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) |
| AnnaBridge | 143:86740a56073b | 831 | * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU |
| AnnaBridge | 143:86740a56073b | 832 | * |
| AnnaBridge | 143:86740a56073b | 833 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 834 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 143:86740a56073b | 835 | */ |
| AnnaBridge | 143:86740a56073b | 836 | __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 837 | { |
| AnnaBridge | 143:86740a56073b | 838 | return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); |
| AnnaBridge | 143:86740a56073b | 839 | } |
| AnnaBridge | 143:86740a56073b | 840 | |
| AnnaBridge | 143:86740a56073b | 841 | /** |
| AnnaBridge | 143:86740a56073b | 842 | * @brief Disable APB2 peripherals clock. |
| AnnaBridge | 143:86740a56073b | 843 | * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 844 | * APB2ENR TIM21EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 845 | * APB2ENR TIM22EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 846 | * APB2ENR FWEN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 847 | * APB2ENR ADCEN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 848 | * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 849 | * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 850 | * APB2ENR DBGEN LL_APB2_GRP1_DisableClock |
| AnnaBridge | 143:86740a56073b | 851 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 852 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 143:86740a56073b | 853 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 |
| AnnaBridge | 143:86740a56073b | 854 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) |
| AnnaBridge | 143:86740a56073b | 855 | * @arg @ref LL_APB2_GRP1_PERIPH_FW |
| AnnaBridge | 143:86740a56073b | 856 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 143:86740a56073b | 857 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 143:86740a56073b | 858 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) |
| AnnaBridge | 143:86740a56073b | 859 | * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU |
| AnnaBridge | 143:86740a56073b | 860 | * |
| AnnaBridge | 143:86740a56073b | 861 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 862 | * @retval None |
| AnnaBridge | 143:86740a56073b | 863 | */ |
| AnnaBridge | 143:86740a56073b | 864 | __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 865 | { |
| AnnaBridge | 143:86740a56073b | 866 | CLEAR_BIT(RCC->APB2ENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 867 | } |
| AnnaBridge | 143:86740a56073b | 868 | |
| AnnaBridge | 143:86740a56073b | 869 | /** |
| AnnaBridge | 143:86740a56073b | 870 | * @brief Force APB2 peripherals reset. |
| AnnaBridge | 143:86740a56073b | 871 | * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 872 | * APB2RSTR TIM21RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 873 | * APB2RSTR TIM22RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 874 | * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 875 | * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 876 | * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 877 | * APB2RSTR DBGRST LL_APB2_GRP1_ForceReset |
| AnnaBridge | 143:86740a56073b | 878 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 879 | * @arg @ref LL_APB2_GRP1_PERIPH_ALL |
| AnnaBridge | 143:86740a56073b | 880 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 143:86740a56073b | 881 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 |
| AnnaBridge | 143:86740a56073b | 882 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) |
| AnnaBridge | 143:86740a56073b | 883 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 143:86740a56073b | 884 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 143:86740a56073b | 885 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) |
| AnnaBridge | 143:86740a56073b | 886 | * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU |
| AnnaBridge | 143:86740a56073b | 887 | * |
| AnnaBridge | 143:86740a56073b | 888 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 889 | * @retval None |
| AnnaBridge | 143:86740a56073b | 890 | */ |
| AnnaBridge | 143:86740a56073b | 891 | __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 892 | { |
| AnnaBridge | 143:86740a56073b | 893 | SET_BIT(RCC->APB2RSTR, Periphs); |
| AnnaBridge | 143:86740a56073b | 894 | } |
| AnnaBridge | 143:86740a56073b | 895 | |
| AnnaBridge | 143:86740a56073b | 896 | /** |
| AnnaBridge | 143:86740a56073b | 897 | * @brief Release APB2 peripherals reset. |
| AnnaBridge | 143:86740a56073b | 898 | * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 899 | * APB2RSTR TIM21RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 900 | * APB2RSTR TIM22RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 901 | * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 902 | * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 903 | * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 904 | * APB2RSTR DBGRST LL_APB2_GRP1_ReleaseReset |
| AnnaBridge | 143:86740a56073b | 905 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 906 | * @arg @ref LL_APB2_GRP1_PERIPH_ALL |
| AnnaBridge | 143:86740a56073b | 907 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 143:86740a56073b | 908 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 |
| AnnaBridge | 143:86740a56073b | 909 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) |
| AnnaBridge | 143:86740a56073b | 910 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 143:86740a56073b | 911 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 143:86740a56073b | 912 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) |
| AnnaBridge | 143:86740a56073b | 913 | * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU |
| AnnaBridge | 143:86740a56073b | 914 | * |
| AnnaBridge | 143:86740a56073b | 915 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 916 | * @retval None |
| AnnaBridge | 143:86740a56073b | 917 | */ |
| AnnaBridge | 143:86740a56073b | 918 | __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 919 | { |
| AnnaBridge | 143:86740a56073b | 920 | CLEAR_BIT(RCC->APB2RSTR, Periphs); |
| AnnaBridge | 143:86740a56073b | 921 | } |
| AnnaBridge | 143:86740a56073b | 922 | |
| AnnaBridge | 143:86740a56073b | 923 | /** |
| AnnaBridge | 143:86740a56073b | 924 | * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode. |
| AnnaBridge | 143:86740a56073b | 925 | * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 926 | * APB2SMENR TIM21SMEN LL_APB2_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 927 | * APB2SMENR TIM22SMEN LL_APB2_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 928 | * APB2SMENR ADCSMEN LL_APB2_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 929 | * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 930 | * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 931 | * APB2SMENR DBGSMEN LL_APB2_GRP1_EnableClockSleep |
| AnnaBridge | 143:86740a56073b | 932 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 933 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 143:86740a56073b | 934 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 |
| AnnaBridge | 143:86740a56073b | 935 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) |
| AnnaBridge | 143:86740a56073b | 936 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 143:86740a56073b | 937 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 143:86740a56073b | 938 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) |
| AnnaBridge | 143:86740a56073b | 939 | * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU |
| AnnaBridge | 143:86740a56073b | 940 | * |
| AnnaBridge | 143:86740a56073b | 941 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 942 | * @retval None |
| AnnaBridge | 143:86740a56073b | 943 | */ |
| AnnaBridge | 143:86740a56073b | 944 | __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 945 | { |
| AnnaBridge | 143:86740a56073b | 946 | __IO uint32_t tmpreg; |
| AnnaBridge | 143:86740a56073b | 947 | SET_BIT(RCC->APB2SMENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 948 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 143:86740a56073b | 949 | tmpreg = READ_BIT(RCC->APB2SMENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 950 | (void)tmpreg; |
| AnnaBridge | 143:86740a56073b | 951 | } |
| AnnaBridge | 143:86740a56073b | 952 | |
| AnnaBridge | 143:86740a56073b | 953 | /** |
| AnnaBridge | 143:86740a56073b | 954 | * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode. |
| AnnaBridge | 143:86740a56073b | 955 | * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 956 | * APB2SMENR TIM21SMEN LL_APB2_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 957 | * APB2SMENR TIM22SMEN LL_APB2_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 958 | * APB2SMENR ADCSMEN LL_APB2_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 959 | * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 960 | * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 961 | * APB2SMENR DBGSMEN LL_APB2_GRP1_DisableClockSleep |
| AnnaBridge | 143:86740a56073b | 962 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 963 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 143:86740a56073b | 964 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 |
| AnnaBridge | 143:86740a56073b | 965 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) |
| AnnaBridge | 143:86740a56073b | 966 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 143:86740a56073b | 967 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 143:86740a56073b | 968 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) |
| AnnaBridge | 143:86740a56073b | 969 | * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU |
| AnnaBridge | 143:86740a56073b | 970 | * |
| AnnaBridge | 143:86740a56073b | 971 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 972 | * @retval None |
| AnnaBridge | 143:86740a56073b | 973 | */ |
| AnnaBridge | 143:86740a56073b | 974 | __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 975 | { |
| AnnaBridge | 143:86740a56073b | 976 | CLEAR_BIT(RCC->APB2SMENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 977 | } |
| AnnaBridge | 143:86740a56073b | 978 | |
| AnnaBridge | 143:86740a56073b | 979 | /** |
| AnnaBridge | 143:86740a56073b | 980 | * @} |
| AnnaBridge | 143:86740a56073b | 981 | */ |
| AnnaBridge | 143:86740a56073b | 982 | /** @defgroup BUS_LL_EF_IOP IOP |
| AnnaBridge | 143:86740a56073b | 983 | * @{ |
| AnnaBridge | 143:86740a56073b | 984 | */ |
| AnnaBridge | 143:86740a56073b | 985 | |
| AnnaBridge | 143:86740a56073b | 986 | /** |
| AnnaBridge | 143:86740a56073b | 987 | * @brief Enable IOP peripherals clock. |
| AnnaBridge | 143:86740a56073b | 988 | * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 989 | * IOPENR GPIOBEN LL_IOP_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 990 | * IOPENR GPIOCEN LL_IOP_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 991 | * IOPENR GPIODEN LL_IOP_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 992 | * IOPENR GPIOEEN LL_IOP_GRP1_EnableClock\n |
| AnnaBridge | 143:86740a56073b | 993 | * IOPENR GPIOHEN LL_IOP_GRP1_EnableClock |
| AnnaBridge | 143:86740a56073b | 994 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 995 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA |
| AnnaBridge | 143:86740a56073b | 996 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB |
| AnnaBridge | 143:86740a56073b | 997 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC |
| AnnaBridge | 143:86740a56073b | 998 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) |
| AnnaBridge | 143:86740a56073b | 999 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 143:86740a56073b | 1000 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) |
| AnnaBridge | 143:86740a56073b | 1001 | * |
| AnnaBridge | 143:86740a56073b | 1002 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 1003 | * @retval None |
| AnnaBridge | 143:86740a56073b | 1004 | */ |
| AnnaBridge | 143:86740a56073b | 1005 | __STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 1006 | { |
| AnnaBridge | 143:86740a56073b | 1007 | __IO uint32_t tmpreg; |
| AnnaBridge | 143:86740a56073b | 1008 | SET_BIT(RCC->IOPENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 1009 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 143:86740a56073b | 1010 | tmpreg = READ_BIT(RCC->IOPENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 1011 | (void)tmpreg; |
| AnnaBridge | 143:86740a56073b | 1012 | } |
| AnnaBridge | 143:86740a56073b | 1013 | |
| AnnaBridge | 143:86740a56073b | 1014 | /** |
| AnnaBridge | 143:86740a56073b | 1015 | * @brief Check if IOP peripheral clock is enabled or not |
| AnnaBridge | 143:86740a56073b | 1016 | * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 1017 | * IOPENR GPIOBEN LL_IOP_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 1018 | * IOPENR GPIOCEN LL_IOP_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 1019 | * IOPENR GPIODEN LL_IOP_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 1020 | * IOPENR GPIOEEN LL_IOP_GRP1_IsEnabledClock\n |
| AnnaBridge | 143:86740a56073b | 1021 | * IOPENR GPIOHEN LL_IOP_GRP1_IsEnabledClock |
| AnnaBridge | 143:86740a56073b | 1022 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 1023 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA |
| AnnaBridge | 143:86740a56073b | 1024 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB |
| AnnaBridge | 143:86740a56073b | 1025 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC |
| AnnaBridge | 143:86740a56073b | 1026 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) |
| AnnaBridge | 143:86740a56073b | 1027 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 143:86740a56073b | 1028 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) |
| AnnaBridge | 143:86740a56073b | 1029 | * |
| AnnaBridge | 143:86740a56073b | 1030 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 1031 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 143:86740a56073b | 1032 | */ |
| AnnaBridge | 143:86740a56073b | 1033 | __STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 1034 | { |
| AnnaBridge | 143:86740a56073b | 1035 | return (READ_BIT(RCC->IOPENR, Periphs) == Periphs); |
| AnnaBridge | 143:86740a56073b | 1036 | } |
| AnnaBridge | 143:86740a56073b | 1037 | |
| AnnaBridge | 143:86740a56073b | 1038 | /** |
| AnnaBridge | 143:86740a56073b | 1039 | * @brief Disable IOP peripherals clock. |
| AnnaBridge | 143:86740a56073b | 1040 | * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 1041 | * IOPENR GPIOBEN LL_IOP_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 1042 | * IOPENR GPIOCEN LL_IOP_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 1043 | * IOPENR GPIODEN LL_IOP_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 1044 | * IOPENR GPIOEEN LL_IOP_GRP1_DisableClock\n |
| AnnaBridge | 143:86740a56073b | 1045 | * IOPENR GPIOHEN LL_IOP_GRP1_DisableClock |
| AnnaBridge | 143:86740a56073b | 1046 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 1047 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA |
| AnnaBridge | 143:86740a56073b | 1048 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB |
| AnnaBridge | 143:86740a56073b | 1049 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC |
| AnnaBridge | 143:86740a56073b | 1050 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) |
| AnnaBridge | 143:86740a56073b | 1051 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 143:86740a56073b | 1052 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) |
| AnnaBridge | 143:86740a56073b | 1053 | * |
| AnnaBridge | 143:86740a56073b | 1054 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 1055 | * @retval None |
| AnnaBridge | 143:86740a56073b | 1056 | */ |
| AnnaBridge | 143:86740a56073b | 1057 | __STATIC_INLINE void LL_IOP_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 1058 | { |
| AnnaBridge | 143:86740a56073b | 1059 | CLEAR_BIT(RCC->IOPENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 1060 | } |
| AnnaBridge | 143:86740a56073b | 1061 | |
| AnnaBridge | 143:86740a56073b | 1062 | /** |
| AnnaBridge | 143:86740a56073b | 1063 | * @brief Disable IOP peripherals clock. |
| AnnaBridge | 143:86740a56073b | 1064 | * @rmtoll IOPRSTR GPIOASMEN LL_IOP_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 1065 | * IOPRSTR GPIOBSMEN LL_IOP_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 1066 | * IOPRSTR GPIOCSMEN LL_IOP_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 1067 | * IOPRSTR GPIODSMEN LL_IOP_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 1068 | * IOPRSTR GPIOESMEN LL_IOP_GRP1_ForceReset\n |
| AnnaBridge | 143:86740a56073b | 1069 | * IOPRSTR GPIOHSMEN LL_IOP_GRP1_ForceReset |
| AnnaBridge | 143:86740a56073b | 1070 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 1071 | * @arg @ref LL_IOP_GRP1_PERIPH_ALL |
| AnnaBridge | 143:86740a56073b | 1072 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA |
| AnnaBridge | 143:86740a56073b | 1073 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB |
| AnnaBridge | 143:86740a56073b | 1074 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC |
| AnnaBridge | 143:86740a56073b | 1075 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) |
| AnnaBridge | 143:86740a56073b | 1076 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 143:86740a56073b | 1077 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) |
| AnnaBridge | 143:86740a56073b | 1078 | * |
| AnnaBridge | 143:86740a56073b | 1079 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 1080 | * @retval None |
| AnnaBridge | 143:86740a56073b | 1081 | */ |
| AnnaBridge | 143:86740a56073b | 1082 | __STATIC_INLINE void LL_IOP_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 1083 | { |
| AnnaBridge | 143:86740a56073b | 1084 | SET_BIT(RCC->IOPRSTR, Periphs); |
| AnnaBridge | 143:86740a56073b | 1085 | } |
| AnnaBridge | 143:86740a56073b | 1086 | |
| AnnaBridge | 143:86740a56073b | 1087 | /** |
| AnnaBridge | 143:86740a56073b | 1088 | * @brief Release IOP peripherals reset. |
| AnnaBridge | 143:86740a56073b | 1089 | * @rmtoll IOPRSTR GPIOASMEN LL_IOP_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 1090 | * IOPRSTR GPIOBSMEN LL_IOP_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 1091 | * IOPRSTR GPIOCSMEN LL_IOP_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 1092 | * IOPRSTR GPIODSMEN LL_IOP_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 1093 | * IOPRSTR GPIOESMEN LL_IOP_GRP1_ReleaseReset\n |
| AnnaBridge | 143:86740a56073b | 1094 | * IOPRSTR GPIOHSMEN LL_IOP_GRP1_ReleaseReset |
| AnnaBridge | 143:86740a56073b | 1095 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 1096 | * @arg @ref LL_IOP_GRP1_PERIPH_ALL |
| AnnaBridge | 143:86740a56073b | 1097 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA |
| AnnaBridge | 143:86740a56073b | 1098 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB |
| AnnaBridge | 143:86740a56073b | 1099 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC |
| AnnaBridge | 143:86740a56073b | 1100 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) |
| AnnaBridge | 143:86740a56073b | 1101 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 143:86740a56073b | 1102 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) |
| AnnaBridge | 143:86740a56073b | 1103 | * |
| AnnaBridge | 143:86740a56073b | 1104 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 1105 | * @retval None |
| AnnaBridge | 143:86740a56073b | 1106 | */ |
| AnnaBridge | 143:86740a56073b | 1107 | __STATIC_INLINE void LL_IOP_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 1108 | { |
| AnnaBridge | 143:86740a56073b | 1109 | CLEAR_BIT(RCC->IOPRSTR, Periphs); |
| AnnaBridge | 143:86740a56073b | 1110 | } |
| AnnaBridge | 143:86740a56073b | 1111 | |
| AnnaBridge | 143:86740a56073b | 1112 | /** |
| AnnaBridge | 143:86740a56073b | 1113 | * @brief Enable IOP peripherals clock during Low Power (Sleep) mode. |
| AnnaBridge | 143:86740a56073b | 1114 | * @rmtoll IOPSMENR GPIOARST LL_IOP_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 1115 | * IOPSMENR GPIOBRST LL_IOP_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 1116 | * IOPSMENR GPIOCRST LL_IOP_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 1117 | * IOPSMENR GPIODRST LL_IOP_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 1118 | * IOPSMENR GPIOERST LL_IOP_GRP1_EnableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 1119 | * IOPSMENR GPIOHRST LL_IOP_GRP1_EnableClockSleep |
| AnnaBridge | 143:86740a56073b | 1120 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 1121 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA |
| AnnaBridge | 143:86740a56073b | 1122 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB |
| AnnaBridge | 143:86740a56073b | 1123 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC |
| AnnaBridge | 143:86740a56073b | 1124 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) |
| AnnaBridge | 143:86740a56073b | 1125 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 143:86740a56073b | 1126 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) |
| AnnaBridge | 143:86740a56073b | 1127 | * |
| AnnaBridge | 143:86740a56073b | 1128 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 1129 | * @retval None |
| AnnaBridge | 143:86740a56073b | 1130 | */ |
| AnnaBridge | 143:86740a56073b | 1131 | __STATIC_INLINE void LL_IOP_GRP1_EnableClockSleep(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 1132 | { |
| AnnaBridge | 143:86740a56073b | 1133 | __IO uint32_t tmpreg; |
| AnnaBridge | 143:86740a56073b | 1134 | SET_BIT(RCC->IOPSMENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 1135 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 143:86740a56073b | 1136 | tmpreg = READ_BIT(RCC->IOPSMENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 1137 | (void)tmpreg; |
| AnnaBridge | 143:86740a56073b | 1138 | } |
| AnnaBridge | 143:86740a56073b | 1139 | |
| AnnaBridge | 143:86740a56073b | 1140 | /** |
| AnnaBridge | 143:86740a56073b | 1141 | * @brief Disable IOP peripherals clock during Low Power (Sleep) mode. |
| AnnaBridge | 143:86740a56073b | 1142 | * @rmtoll IOPSMENR GPIOARST LL_IOP_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 1143 | * IOPSMENR GPIOBRST LL_IOP_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 1144 | * IOPSMENR GPIOCRST LL_IOP_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 1145 | * IOPSMENR GPIODRST LL_IOP_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 1146 | * IOPSMENR GPIOERST LL_IOP_GRP1_DisableClockSleep\n |
| AnnaBridge | 143:86740a56073b | 1147 | * IOPSMENR GPIOHRST LL_IOP_GRP1_DisableClockSleep |
| AnnaBridge | 143:86740a56073b | 1148 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 143:86740a56073b | 1149 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA |
| AnnaBridge | 143:86740a56073b | 1150 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB |
| AnnaBridge | 143:86740a56073b | 1151 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC |
| AnnaBridge | 143:86740a56073b | 1152 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) |
| AnnaBridge | 143:86740a56073b | 1153 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 143:86740a56073b | 1154 | * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) |
| AnnaBridge | 143:86740a56073b | 1155 | * |
| AnnaBridge | 143:86740a56073b | 1156 | * (*) value not defined in all devices. |
| AnnaBridge | 143:86740a56073b | 1157 | * @retval None |
| AnnaBridge | 143:86740a56073b | 1158 | */ |
| AnnaBridge | 143:86740a56073b | 1159 | __STATIC_INLINE void LL_IOP_GRP1_DisableClockSleep(uint32_t Periphs) |
| AnnaBridge | 143:86740a56073b | 1160 | { |
| AnnaBridge | 143:86740a56073b | 1161 | CLEAR_BIT(RCC->IOPSMENR, Periphs); |
| AnnaBridge | 143:86740a56073b | 1162 | } |
| AnnaBridge | 143:86740a56073b | 1163 | |
| AnnaBridge | 143:86740a56073b | 1164 | /** |
| AnnaBridge | 143:86740a56073b | 1165 | * @} |
| AnnaBridge | 143:86740a56073b | 1166 | */ |
| AnnaBridge | 143:86740a56073b | 1167 | |
| AnnaBridge | 143:86740a56073b | 1168 | |
| AnnaBridge | 143:86740a56073b | 1169 | /** |
| AnnaBridge | 143:86740a56073b | 1170 | * @} |
| AnnaBridge | 143:86740a56073b | 1171 | */ |
| AnnaBridge | 143:86740a56073b | 1172 | |
| AnnaBridge | 143:86740a56073b | 1173 | /** |
| AnnaBridge | 143:86740a56073b | 1174 | * @} |
| AnnaBridge | 143:86740a56073b | 1175 | */ |
| AnnaBridge | 143:86740a56073b | 1176 | |
| AnnaBridge | 143:86740a56073b | 1177 | #endif /* defined(RCC) */ |
| AnnaBridge | 143:86740a56073b | 1178 | |
| AnnaBridge | 143:86740a56073b | 1179 | /** |
| AnnaBridge | 143:86740a56073b | 1180 | * @} |
| AnnaBridge | 143:86740a56073b | 1181 | */ |
| AnnaBridge | 143:86740a56073b | 1182 | |
| AnnaBridge | 143:86740a56073b | 1183 | #ifdef __cplusplus |
| AnnaBridge | 143:86740a56073b | 1184 | } |
| AnnaBridge | 143:86740a56073b | 1185 | #endif |
| AnnaBridge | 143:86740a56073b | 1186 | |
| AnnaBridge | 143:86740a56073b | 1187 | #endif /* __STM32L0xx_LL_BUS_H */ |
| AnnaBridge | 143:86740a56073b | 1188 | |
| AnnaBridge | 143:86740a56073b | 1189 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
