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TARGET_NUCLEO_L011K4/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_smbus.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smbus.h@167:84c0a372a020
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 143:86740a56073b | 1 | /** |
| AnnaBridge | 143:86740a56073b | 2 | ****************************************************************************** |
| AnnaBridge | 143:86740a56073b | 3 | * @file stm32l0xx_hal_smbus.h |
| AnnaBridge | 143:86740a56073b | 4 | * @author MCD Application Team |
| AnnaBridge | 143:86740a56073b | 5 | * @brief Header file of SMBUS HAL module. |
| AnnaBridge | 143:86740a56073b | 6 | ****************************************************************************** |
| AnnaBridge | 143:86740a56073b | 7 | * @attention |
| AnnaBridge | 143:86740a56073b | 8 | * |
| AnnaBridge | 143:86740a56073b | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 143:86740a56073b | 10 | * |
| AnnaBridge | 143:86740a56073b | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 143:86740a56073b | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 143:86740a56073b | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 143:86740a56073b | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 143:86740a56073b | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 143:86740a56073b | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 143:86740a56073b | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 143:86740a56073b | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 143:86740a56073b | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 143:86740a56073b | 20 | * without specific prior written permission. |
| AnnaBridge | 143:86740a56073b | 21 | * |
| AnnaBridge | 143:86740a56073b | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 143:86740a56073b | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 143:86740a56073b | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 143:86740a56073b | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 143:86740a56073b | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 143:86740a56073b | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 143:86740a56073b | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 143:86740a56073b | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 143:86740a56073b | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 143:86740a56073b | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 143:86740a56073b | 32 | * |
| AnnaBridge | 143:86740a56073b | 33 | ****************************************************************************** |
| AnnaBridge | 167:84c0a372a020 | 34 | */ |
| AnnaBridge | 143:86740a56073b | 35 | |
| AnnaBridge | 143:86740a56073b | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 37 | #ifndef __STM32L0xx_HAL_SMBUS_H |
| AnnaBridge | 143:86740a56073b | 38 | #define __STM32L0xx_HAL_SMBUS_H |
| AnnaBridge | 143:86740a56073b | 39 | |
| AnnaBridge | 143:86740a56073b | 40 | #ifdef __cplusplus |
| AnnaBridge | 167:84c0a372a020 | 41 | extern "C" { |
| AnnaBridge | 143:86740a56073b | 42 | #endif |
| AnnaBridge | 143:86740a56073b | 43 | |
| AnnaBridge | 143:86740a56073b | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 167:84c0a372a020 | 45 | #include "stm32l0xx_hal_def.h" |
| AnnaBridge | 143:86740a56073b | 46 | |
| AnnaBridge | 143:86740a56073b | 47 | /** @addtogroup STM32L0xx_HAL_Driver |
| AnnaBridge | 143:86740a56073b | 48 | * @{ |
| AnnaBridge | 143:86740a56073b | 49 | */ |
| AnnaBridge | 143:86740a56073b | 50 | |
| AnnaBridge | 167:84c0a372a020 | 51 | /** @addtogroup SMBUS |
| AnnaBridge | 143:86740a56073b | 52 | * @{ |
| AnnaBridge | 167:84c0a372a020 | 53 | */ |
| AnnaBridge | 143:86740a56073b | 54 | |
| AnnaBridge | 143:86740a56073b | 55 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 56 | /** @defgroup SMBUS_Exported_Types SMBUS Exported Types |
| AnnaBridge | 143:86740a56073b | 57 | * @{ |
| AnnaBridge | 143:86740a56073b | 58 | */ |
| AnnaBridge | 143:86740a56073b | 59 | |
| AnnaBridge | 167:84c0a372a020 | 60 | /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition |
| AnnaBridge | 167:84c0a372a020 | 61 | * @brief SMBUS Configuration Structure definition |
| AnnaBridge | 167:84c0a372a020 | 62 | * @{ |
| AnnaBridge | 143:86740a56073b | 63 | */ |
| AnnaBridge | 143:86740a56073b | 64 | typedef struct |
| AnnaBridge | 143:86740a56073b | 65 | { |
| AnnaBridge | 143:86740a56073b | 66 | uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. |
| AnnaBridge | 167:84c0a372a020 | 67 | This parameter calculated by referring to SMBUS initialization |
| AnnaBridge | 167:84c0a372a020 | 68 | section in Reference manual */ |
| AnnaBridge | 143:86740a56073b | 69 | uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. |
| AnnaBridge | 167:84c0a372a020 | 70 | This parameter can be a value of @ref SMBUS_Analog_Filter */ |
| AnnaBridge | 143:86740a56073b | 71 | |
| AnnaBridge | 143:86740a56073b | 72 | uint32_t OwnAddress1; /*!< Specifies the first device own address. |
| AnnaBridge | 143:86740a56073b | 73 | This parameter can be a 7-bit or 10-bit address. */ |
| AnnaBridge | 143:86740a56073b | 74 | |
| AnnaBridge | 143:86740a56073b | 75 | uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. |
| AnnaBridge | 143:86740a56073b | 76 | This parameter can be a value of @ref SMBUS_addressing_mode */ |
| AnnaBridge | 143:86740a56073b | 77 | |
| AnnaBridge | 143:86740a56073b | 78 | uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. |
| AnnaBridge | 143:86740a56073b | 79 | This parameter can be a value of @ref SMBUS_dual_addressing_mode */ |
| AnnaBridge | 143:86740a56073b | 80 | |
| AnnaBridge | 143:86740a56073b | 81 | uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected |
| AnnaBridge | 143:86740a56073b | 82 | This parameter can be a 7-bit address. */ |
| AnnaBridge | 143:86740a56073b | 83 | |
| AnnaBridge | 143:86740a56073b | 84 | uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected |
| AnnaBridge | 167:84c0a372a020 | 85 | This parameter can be a value of @ref SMBUS_own_address2_masks. */ |
| AnnaBridge | 143:86740a56073b | 86 | |
| AnnaBridge | 143:86740a56073b | 87 | uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. |
| AnnaBridge | 167:84c0a372a020 | 88 | This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ |
| AnnaBridge | 143:86740a56073b | 89 | |
| AnnaBridge | 143:86740a56073b | 90 | uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. |
| AnnaBridge | 143:86740a56073b | 91 | This parameter can be a value of @ref SMBUS_nostretch_mode */ |
| AnnaBridge | 143:86740a56073b | 92 | |
| AnnaBridge | 143:86740a56073b | 93 | uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. |
| AnnaBridge | 143:86740a56073b | 94 | This parameter can be a value of @ref SMBUS_packet_error_check_mode */ |
| AnnaBridge | 143:86740a56073b | 95 | |
| AnnaBridge | 143:86740a56073b | 96 | uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. |
| AnnaBridge | 143:86740a56073b | 97 | This parameter can be a value of @ref SMBUS_peripheral_mode */ |
| AnnaBridge | 143:86740a56073b | 98 | |
| AnnaBridge | 143:86740a56073b | 99 | uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. |
| AnnaBridge | 167:84c0a372a020 | 100 | (Enable bits and different timeout values) |
| AnnaBridge | 167:84c0a372a020 | 101 | This parameter calculated by referring to SMBUS initialization |
| AnnaBridge | 143:86740a56073b | 102 | section in Reference manual */ |
| AnnaBridge | 143:86740a56073b | 103 | } SMBUS_InitTypeDef; |
| AnnaBridge | 167:84c0a372a020 | 104 | /** |
| AnnaBridge | 167:84c0a372a020 | 105 | * @} |
| AnnaBridge | 167:84c0a372a020 | 106 | */ |
| AnnaBridge | 143:86740a56073b | 107 | |
| AnnaBridge | 167:84c0a372a020 | 108 | /** @defgroup HAL_state_definition HAL state definition |
| AnnaBridge | 167:84c0a372a020 | 109 | * @brief HAL State definition |
| AnnaBridge | 143:86740a56073b | 110 | * @{ |
| AnnaBridge | 167:84c0a372a020 | 111 | */ |
| AnnaBridge | 167:84c0a372a020 | 112 | #define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */ |
| AnnaBridge | 167:84c0a372a020 | 113 | #define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */ |
| AnnaBridge | 167:84c0a372a020 | 114 | #define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */ |
| AnnaBridge | 167:84c0a372a020 | 115 | #define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ |
| AnnaBridge | 167:84c0a372a020 | 116 | #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ |
| AnnaBridge | 167:84c0a372a020 | 117 | #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ |
| AnnaBridge | 167:84c0a372a020 | 118 | #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ |
| AnnaBridge | 167:84c0a372a020 | 119 | #define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ |
| AnnaBridge | 167:84c0a372a020 | 120 | #define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ |
| AnnaBridge | 167:84c0a372a020 | 121 | #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ |
| AnnaBridge | 167:84c0a372a020 | 122 | /** |
| AnnaBridge | 143:86740a56073b | 123 | * @} |
| AnnaBridge | 143:86740a56073b | 124 | */ |
| AnnaBridge | 143:86740a56073b | 125 | |
| AnnaBridge | 167:84c0a372a020 | 126 | /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition |
| AnnaBridge | 167:84c0a372a020 | 127 | * @brief SMBUS Error Code definition |
| AnnaBridge | 167:84c0a372a020 | 128 | * @{ |
| AnnaBridge | 167:84c0a372a020 | 129 | */ |
| AnnaBridge | 167:84c0a372a020 | 130 | #define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */ |
| AnnaBridge | 167:84c0a372a020 | 131 | #define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ |
| AnnaBridge | 167:84c0a372a020 | 132 | #define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ |
| AnnaBridge | 167:84c0a372a020 | 133 | #define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ |
| AnnaBridge | 167:84c0a372a020 | 134 | #define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ |
| AnnaBridge | 167:84c0a372a020 | 135 | #define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ |
| AnnaBridge | 167:84c0a372a020 | 136 | #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ |
| AnnaBridge | 167:84c0a372a020 | 137 | #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ |
| AnnaBridge | 167:84c0a372a020 | 138 | #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ |
| AnnaBridge | 167:84c0a372a020 | 139 | /** |
| AnnaBridge | 167:84c0a372a020 | 140 | * @} |
| AnnaBridge | 167:84c0a372a020 | 141 | */ |
| AnnaBridge | 167:84c0a372a020 | 142 | |
| AnnaBridge | 167:84c0a372a020 | 143 | /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition |
| AnnaBridge | 167:84c0a372a020 | 144 | * @brief SMBUS handle Structure definition |
| AnnaBridge | 167:84c0a372a020 | 145 | * @{ |
| AnnaBridge | 143:86740a56073b | 146 | */ |
| AnnaBridge | 143:86740a56073b | 147 | typedef struct |
| AnnaBridge | 143:86740a56073b | 148 | { |
| AnnaBridge | 167:84c0a372a020 | 149 | I2C_TypeDef *Instance; /*!< SMBUS registers base address */ |
| AnnaBridge | 167:84c0a372a020 | 150 | |
| AnnaBridge | 167:84c0a372a020 | 151 | SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ |
| AnnaBridge | 167:84c0a372a020 | 152 | |
| AnnaBridge | 167:84c0a372a020 | 153 | uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ |
| AnnaBridge | 167:84c0a372a020 | 154 | |
| AnnaBridge | 167:84c0a372a020 | 155 | uint16_t XferSize; /*!< SMBUS transfer size */ |
| AnnaBridge | 167:84c0a372a020 | 156 | |
| AnnaBridge | 167:84c0a372a020 | 157 | __IO uint16_t XferCount; /*!< SMBUS transfer counter */ |
| AnnaBridge | 167:84c0a372a020 | 158 | |
| AnnaBridge | 167:84c0a372a020 | 159 | __IO uint32_t XferOptions; /*!< SMBUS transfer options */ |
| AnnaBridge | 167:84c0a372a020 | 160 | |
| AnnaBridge | 167:84c0a372a020 | 161 | __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */ |
| AnnaBridge | 143:86740a56073b | 162 | |
| AnnaBridge | 167:84c0a372a020 | 163 | HAL_LockTypeDef Lock; /*!< SMBUS locking object */ |
| AnnaBridge | 143:86740a56073b | 164 | |
| AnnaBridge | 167:84c0a372a020 | 165 | __IO uint32_t State; /*!< SMBUS communication state */ |
| AnnaBridge | 167:84c0a372a020 | 166 | |
| AnnaBridge | 167:84c0a372a020 | 167 | __IO uint32_t ErrorCode; /*!< SMBUS Error code */ |
| AnnaBridge | 143:86740a56073b | 168 | |
| AnnaBridge | 167:84c0a372a020 | 169 | } SMBUS_HandleTypeDef; |
| AnnaBridge | 167:84c0a372a020 | 170 | /** |
| AnnaBridge | 167:84c0a372a020 | 171 | * @} |
| AnnaBridge | 167:84c0a372a020 | 172 | */ |
| AnnaBridge | 143:86740a56073b | 173 | |
| AnnaBridge | 167:84c0a372a020 | 174 | /** |
| AnnaBridge | 167:84c0a372a020 | 175 | * @} |
| AnnaBridge | 167:84c0a372a020 | 176 | */ |
| AnnaBridge | 143:86740a56073b | 177 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 178 | |
| AnnaBridge | 143:86740a56073b | 179 | /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants |
| AnnaBridge | 143:86740a56073b | 180 | * @{ |
| AnnaBridge | 143:86740a56073b | 181 | */ |
| AnnaBridge | 143:86740a56073b | 182 | |
| AnnaBridge | 143:86740a56073b | 183 | /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter |
| AnnaBridge | 143:86740a56073b | 184 | * @{ |
| AnnaBridge | 143:86740a56073b | 185 | */ |
| AnnaBridge | 167:84c0a372a020 | 186 | #define SMBUS_ANALOGFILTER_ENABLE (0x00000000U) |
| AnnaBridge | 167:84c0a372a020 | 187 | #define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF |
| AnnaBridge | 143:86740a56073b | 188 | /** |
| AnnaBridge | 143:86740a56073b | 189 | * @} |
| AnnaBridge | 143:86740a56073b | 190 | */ |
| AnnaBridge | 143:86740a56073b | 191 | |
| AnnaBridge | 167:84c0a372a020 | 192 | /** @defgroup SMBUS_addressing_mode SMBUS addressing mode |
| AnnaBridge | 143:86740a56073b | 193 | * @{ |
| AnnaBridge | 143:86740a56073b | 194 | */ |
| AnnaBridge | 167:84c0a372a020 | 195 | #define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U) |
| AnnaBridge | 167:84c0a372a020 | 196 | #define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U) |
| AnnaBridge | 143:86740a56073b | 197 | /** |
| AnnaBridge | 143:86740a56073b | 198 | * @} |
| AnnaBridge | 143:86740a56073b | 199 | */ |
| AnnaBridge | 143:86740a56073b | 200 | |
| AnnaBridge | 167:84c0a372a020 | 201 | /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode |
| AnnaBridge | 143:86740a56073b | 202 | * @{ |
| AnnaBridge | 143:86740a56073b | 203 | */ |
| AnnaBridge | 143:86740a56073b | 204 | |
| AnnaBridge | 167:84c0a372a020 | 205 | #define SMBUS_DUALADDRESS_DISABLE (0x00000000U) |
| AnnaBridge | 167:84c0a372a020 | 206 | #define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN |
| AnnaBridge | 143:86740a56073b | 207 | /** |
| AnnaBridge | 143:86740a56073b | 208 | * @} |
| AnnaBridge | 143:86740a56073b | 209 | */ |
| AnnaBridge | 143:86740a56073b | 210 | |
| AnnaBridge | 167:84c0a372a020 | 211 | /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks |
| AnnaBridge | 143:86740a56073b | 212 | * @{ |
| AnnaBridge | 143:86740a56073b | 213 | */ |
| AnnaBridge | 143:86740a56073b | 214 | |
| AnnaBridge | 143:86740a56073b | 215 | #define SMBUS_OA2_NOMASK ((uint8_t)0x00U) |
| AnnaBridge | 143:86740a56073b | 216 | #define SMBUS_OA2_MASK01 ((uint8_t)0x01U) |
| AnnaBridge | 143:86740a56073b | 217 | #define SMBUS_OA2_MASK02 ((uint8_t)0x02U) |
| AnnaBridge | 143:86740a56073b | 218 | #define SMBUS_OA2_MASK03 ((uint8_t)0x03U) |
| AnnaBridge | 143:86740a56073b | 219 | #define SMBUS_OA2_MASK04 ((uint8_t)0x04U) |
| AnnaBridge | 143:86740a56073b | 220 | #define SMBUS_OA2_MASK05 ((uint8_t)0x05U) |
| AnnaBridge | 143:86740a56073b | 221 | #define SMBUS_OA2_MASK06 ((uint8_t)0x06U) |
| AnnaBridge | 143:86740a56073b | 222 | #define SMBUS_OA2_MASK07 ((uint8_t)0x07U) |
| AnnaBridge | 143:86740a56073b | 223 | /** |
| AnnaBridge | 143:86740a56073b | 224 | * @} |
| AnnaBridge | 143:86740a56073b | 225 | */ |
| AnnaBridge | 143:86740a56073b | 226 | |
| AnnaBridge | 143:86740a56073b | 227 | |
| AnnaBridge | 167:84c0a372a020 | 228 | /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode |
| AnnaBridge | 143:86740a56073b | 229 | * @{ |
| AnnaBridge | 143:86740a56073b | 230 | */ |
| AnnaBridge | 167:84c0a372a020 | 231 | #define SMBUS_GENERALCALL_DISABLE (0x00000000U) |
| AnnaBridge | 167:84c0a372a020 | 232 | #define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN |
| AnnaBridge | 143:86740a56073b | 233 | /** |
| AnnaBridge | 143:86740a56073b | 234 | * @} |
| AnnaBridge | 143:86740a56073b | 235 | */ |
| AnnaBridge | 143:86740a56073b | 236 | |
| AnnaBridge | 167:84c0a372a020 | 237 | /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode |
| AnnaBridge | 143:86740a56073b | 238 | * @{ |
| AnnaBridge | 143:86740a56073b | 239 | */ |
| AnnaBridge | 167:84c0a372a020 | 240 | #define SMBUS_NOSTRETCH_DISABLE (0x00000000U) |
| AnnaBridge | 167:84c0a372a020 | 241 | #define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH |
| AnnaBridge | 143:86740a56073b | 242 | /** |
| AnnaBridge | 143:86740a56073b | 243 | * @} |
| AnnaBridge | 143:86740a56073b | 244 | */ |
| AnnaBridge | 143:86740a56073b | 245 | |
| AnnaBridge | 167:84c0a372a020 | 246 | /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode |
| AnnaBridge | 143:86740a56073b | 247 | * @{ |
| AnnaBridge | 143:86740a56073b | 248 | */ |
| AnnaBridge | 167:84c0a372a020 | 249 | #define SMBUS_PEC_DISABLE (0x00000000U) |
| AnnaBridge | 143:86740a56073b | 250 | #define SMBUS_PEC_ENABLE I2C_CR1_PECEN |
| AnnaBridge | 143:86740a56073b | 251 | /** |
| AnnaBridge | 143:86740a56073b | 252 | * @} |
| AnnaBridge | 143:86740a56073b | 253 | */ |
| AnnaBridge | 143:86740a56073b | 254 | |
| AnnaBridge | 167:84c0a372a020 | 255 | /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode |
| AnnaBridge | 143:86740a56073b | 256 | * @{ |
| AnnaBridge | 143:86740a56073b | 257 | */ |
| AnnaBridge | 167:84c0a372a020 | 258 | #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN |
| AnnaBridge | 167:84c0a372a020 | 259 | #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U) |
| AnnaBridge | 167:84c0a372a020 | 260 | #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN |
| AnnaBridge | 143:86740a56073b | 261 | /** |
| AnnaBridge | 143:86740a56073b | 262 | * @} |
| AnnaBridge | 143:86740a56073b | 263 | */ |
| AnnaBridge | 143:86740a56073b | 264 | |
| AnnaBridge | 167:84c0a372a020 | 265 | /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition |
| AnnaBridge | 143:86740a56073b | 266 | * @{ |
| AnnaBridge | 143:86740a56073b | 267 | */ |
| AnnaBridge | 143:86740a56073b | 268 | |
| AnnaBridge | 167:84c0a372a020 | 269 | #define SMBUS_SOFTEND_MODE (0x00000000U) |
| AnnaBridge | 143:86740a56073b | 270 | #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD |
| AnnaBridge | 143:86740a56073b | 271 | #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND |
| AnnaBridge | 143:86740a56073b | 272 | #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE |
| AnnaBridge | 167:84c0a372a020 | 273 | /** |
| AnnaBridge | 167:84c0a372a020 | 274 | * @} |
| AnnaBridge | 167:84c0a372a020 | 275 | */ |
| AnnaBridge | 143:86740a56073b | 276 | |
| AnnaBridge | 167:84c0a372a020 | 277 | /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition |
| AnnaBridge | 167:84c0a372a020 | 278 | * @{ |
| AnnaBridge | 167:84c0a372a020 | 279 | */ |
| AnnaBridge | 143:86740a56073b | 280 | |
| AnnaBridge | 167:84c0a372a020 | 281 | #define SMBUS_NO_STARTSTOP (0x00000000U) |
| AnnaBridge | 167:84c0a372a020 | 282 | #define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) |
| AnnaBridge | 167:84c0a372a020 | 283 | #define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) |
| AnnaBridge | 167:84c0a372a020 | 284 | #define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) |
| AnnaBridge | 143:86740a56073b | 285 | /** |
| AnnaBridge | 143:86740a56073b | 286 | * @} |
| AnnaBridge | 143:86740a56073b | 287 | */ |
| AnnaBridge | 143:86740a56073b | 288 | |
| AnnaBridge | 167:84c0a372a020 | 289 | /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition |
| AnnaBridge | 143:86740a56073b | 290 | * @{ |
| AnnaBridge | 143:86740a56073b | 291 | */ |
| AnnaBridge | 143:86740a56073b | 292 | |
| AnnaBridge | 167:84c0a372a020 | 293 | /* List of XferOptions in usage of : |
| AnnaBridge | 167:84c0a372a020 | 294 | * 1- Restart condition when direction change |
| AnnaBridge | 167:84c0a372a020 | 295 | * 2- No Restart condition in other use cases |
| AnnaBridge | 167:84c0a372a020 | 296 | */ |
| AnnaBridge | 167:84c0a372a020 | 297 | #define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE |
| AnnaBridge | 167:84c0a372a020 | 298 | #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) |
| AnnaBridge | 167:84c0a372a020 | 299 | #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE |
| AnnaBridge | 167:84c0a372a020 | 300 | #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE |
| AnnaBridge | 167:84c0a372a020 | 301 | #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) |
| AnnaBridge | 167:84c0a372a020 | 302 | #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) |
| AnnaBridge | 167:84c0a372a020 | 303 | |
| AnnaBridge | 167:84c0a372a020 | 304 | /* List of XferOptions in usage of : |
| AnnaBridge | 167:84c0a372a020 | 305 | * 1- Restart condition in all use cases (direction change or not) |
| AnnaBridge | 167:84c0a372a020 | 306 | */ |
| AnnaBridge | 167:84c0a372a020 | 307 | #define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) |
| AnnaBridge | 167:84c0a372a020 | 308 | #define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) |
| AnnaBridge | 167:84c0a372a020 | 309 | #define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) |
| AnnaBridge | 167:84c0a372a020 | 310 | #define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) |
| AnnaBridge | 143:86740a56073b | 311 | /** |
| AnnaBridge | 143:86740a56073b | 312 | * @} |
| AnnaBridge | 143:86740a56073b | 313 | */ |
| AnnaBridge | 143:86740a56073b | 314 | |
| AnnaBridge | 167:84c0a372a020 | 315 | /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition |
| AnnaBridge | 143:86740a56073b | 316 | * @brief SMBUS Interrupt definition |
| AnnaBridge | 143:86740a56073b | 317 | * Elements values convention: 0xXXXXXXXX |
| AnnaBridge | 143:86740a56073b | 318 | * - XXXXXXXX : Interrupt control mask |
| AnnaBridge | 143:86740a56073b | 319 | * @{ |
| AnnaBridge | 143:86740a56073b | 320 | */ |
| AnnaBridge | 167:84c0a372a020 | 321 | #define SMBUS_IT_ERRI I2C_CR1_ERRIE |
| AnnaBridge | 167:84c0a372a020 | 322 | #define SMBUS_IT_TCI I2C_CR1_TCIE |
| AnnaBridge | 167:84c0a372a020 | 323 | #define SMBUS_IT_STOPI I2C_CR1_STOPIE |
| AnnaBridge | 167:84c0a372a020 | 324 | #define SMBUS_IT_NACKI I2C_CR1_NACKIE |
| AnnaBridge | 167:84c0a372a020 | 325 | #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE |
| AnnaBridge | 167:84c0a372a020 | 326 | #define SMBUS_IT_RXI I2C_CR1_RXIE |
| AnnaBridge | 167:84c0a372a020 | 327 | #define SMBUS_IT_TXI I2C_CR1_TXIE |
| AnnaBridge | 167:84c0a372a020 | 328 | #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI) |
| AnnaBridge | 167:84c0a372a020 | 329 | #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) |
| AnnaBridge | 167:84c0a372a020 | 330 | #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) |
| AnnaBridge | 167:84c0a372a020 | 331 | #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) |
| AnnaBridge | 143:86740a56073b | 332 | /** |
| AnnaBridge | 143:86740a56073b | 333 | * @} |
| AnnaBridge | 143:86740a56073b | 334 | */ |
| AnnaBridge | 143:86740a56073b | 335 | |
| AnnaBridge | 167:84c0a372a020 | 336 | /** @defgroup SMBUS_Flag_definition SMBUS Flag definition |
| AnnaBridge | 143:86740a56073b | 337 | * @brief Flag definition |
| AnnaBridge | 143:86740a56073b | 338 | * Elements values convention: 0xXXXXYYYY |
| AnnaBridge | 143:86740a56073b | 339 | * - XXXXXXXX : Flag mask |
| AnnaBridge | 143:86740a56073b | 340 | * @{ |
| AnnaBridge | 167:84c0a372a020 | 341 | */ |
| AnnaBridge | 143:86740a56073b | 342 | |
| AnnaBridge | 167:84c0a372a020 | 343 | #define SMBUS_FLAG_TXE I2C_ISR_TXE |
| AnnaBridge | 167:84c0a372a020 | 344 | #define SMBUS_FLAG_TXIS I2C_ISR_TXIS |
| AnnaBridge | 167:84c0a372a020 | 345 | #define SMBUS_FLAG_RXNE I2C_ISR_RXNE |
| AnnaBridge | 167:84c0a372a020 | 346 | #define SMBUS_FLAG_ADDR I2C_ISR_ADDR |
| AnnaBridge | 167:84c0a372a020 | 347 | #define SMBUS_FLAG_AF I2C_ISR_NACKF |
| AnnaBridge | 167:84c0a372a020 | 348 | #define SMBUS_FLAG_STOPF I2C_ISR_STOPF |
| AnnaBridge | 167:84c0a372a020 | 349 | #define SMBUS_FLAG_TC I2C_ISR_TC |
| AnnaBridge | 167:84c0a372a020 | 350 | #define SMBUS_FLAG_TCR I2C_ISR_TCR |
| AnnaBridge | 167:84c0a372a020 | 351 | #define SMBUS_FLAG_BERR I2C_ISR_BERR |
| AnnaBridge | 167:84c0a372a020 | 352 | #define SMBUS_FLAG_ARLO I2C_ISR_ARLO |
| AnnaBridge | 167:84c0a372a020 | 353 | #define SMBUS_FLAG_OVR I2C_ISR_OVR |
| AnnaBridge | 167:84c0a372a020 | 354 | #define SMBUS_FLAG_PECERR I2C_ISR_PECERR |
| AnnaBridge | 167:84c0a372a020 | 355 | #define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT |
| AnnaBridge | 167:84c0a372a020 | 356 | #define SMBUS_FLAG_ALERT I2C_ISR_ALERT |
| AnnaBridge | 167:84c0a372a020 | 357 | #define SMBUS_FLAG_BUSY I2C_ISR_BUSY |
| AnnaBridge | 167:84c0a372a020 | 358 | #define SMBUS_FLAG_DIR I2C_ISR_DIR |
| AnnaBridge | 143:86740a56073b | 359 | /** |
| AnnaBridge | 143:86740a56073b | 360 | * @} |
| AnnaBridge | 143:86740a56073b | 361 | */ |
| AnnaBridge | 143:86740a56073b | 362 | |
| AnnaBridge | 143:86740a56073b | 363 | /** |
| AnnaBridge | 143:86740a56073b | 364 | * @} |
| AnnaBridge | 143:86740a56073b | 365 | */ |
| AnnaBridge | 143:86740a56073b | 366 | |
| AnnaBridge | 167:84c0a372a020 | 367 | /* Exported macros ------------------------------------------------------------*/ |
| AnnaBridge | 143:86740a56073b | 368 | /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros |
| AnnaBridge | 143:86740a56073b | 369 | * @{ |
| AnnaBridge | 143:86740a56073b | 370 | */ |
| AnnaBridge | 143:86740a56073b | 371 | |
| AnnaBridge | 167:84c0a372a020 | 372 | /** @brief Reset SMBUS handle state. |
| AnnaBridge | 167:84c0a372a020 | 373 | * @param __HANDLE__ specifies the SMBUS Handle. |
| AnnaBridge | 143:86740a56073b | 374 | * @retval None |
| AnnaBridge | 143:86740a56073b | 375 | */ |
| AnnaBridge | 143:86740a56073b | 376 | #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) |
| AnnaBridge | 143:86740a56073b | 377 | |
| AnnaBridge | 167:84c0a372a020 | 378 | /** @brief Enable the specified SMBUS interrupts. |
| AnnaBridge | 167:84c0a372a020 | 379 | * @param __HANDLE__ specifies the SMBUS Handle. |
| AnnaBridge | 167:84c0a372a020 | 380 | * @param __INTERRUPT__ specifies the interrupt source to enable. |
| AnnaBridge | 143:86740a56073b | 381 | * This parameter can be one of the following values: |
| AnnaBridge | 167:84c0a372a020 | 382 | * @arg @ref SMBUS_IT_ERRI Errors interrupt enable |
| AnnaBridge | 167:84c0a372a020 | 383 | * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable |
| AnnaBridge | 167:84c0a372a020 | 384 | * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable |
| AnnaBridge | 167:84c0a372a020 | 385 | * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable |
| AnnaBridge | 167:84c0a372a020 | 386 | * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable |
| AnnaBridge | 167:84c0a372a020 | 387 | * @arg @ref SMBUS_IT_RXI RX interrupt enable |
| AnnaBridge | 167:84c0a372a020 | 388 | * @arg @ref SMBUS_IT_TXI TX interrupt enable |
| AnnaBridge | 167:84c0a372a020 | 389 | * |
| AnnaBridge | 143:86740a56073b | 390 | * @retval None |
| AnnaBridge | 143:86740a56073b | 391 | */ |
| AnnaBridge | 143:86740a56073b | 392 | #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) |
| AnnaBridge | 167:84c0a372a020 | 393 | |
| AnnaBridge | 167:84c0a372a020 | 394 | /** @brief Disable the specified SMBUS interrupts. |
| AnnaBridge | 167:84c0a372a020 | 395 | * @param __HANDLE__ specifies the SMBUS Handle. |
| AnnaBridge | 167:84c0a372a020 | 396 | * @param __INTERRUPT__ specifies the interrupt source to disable. |
| AnnaBridge | 167:84c0a372a020 | 397 | * This parameter can be one of the following values: |
| AnnaBridge | 167:84c0a372a020 | 398 | * @arg @ref SMBUS_IT_ERRI Errors interrupt enable |
| AnnaBridge | 167:84c0a372a020 | 399 | * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable |
| AnnaBridge | 167:84c0a372a020 | 400 | * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable |
| AnnaBridge | 167:84c0a372a020 | 401 | * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable |
| AnnaBridge | 167:84c0a372a020 | 402 | * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable |
| AnnaBridge | 167:84c0a372a020 | 403 | * @arg @ref SMBUS_IT_RXI RX interrupt enable |
| AnnaBridge | 167:84c0a372a020 | 404 | * @arg @ref SMBUS_IT_TXI TX interrupt enable |
| AnnaBridge | 167:84c0a372a020 | 405 | * |
| AnnaBridge | 167:84c0a372a020 | 406 | * @retval None |
| AnnaBridge | 167:84c0a372a020 | 407 | */ |
| AnnaBridge | 143:86740a56073b | 408 | #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) |
| AnnaBridge | 167:84c0a372a020 | 409 | |
| AnnaBridge | 167:84c0a372a020 | 410 | /** @brief Check whether the specified SMBUS interrupt source is enabled or not. |
| AnnaBridge | 167:84c0a372a020 | 411 | * @param __HANDLE__ specifies the SMBUS Handle. |
| AnnaBridge | 167:84c0a372a020 | 412 | * @param __INTERRUPT__ specifies the SMBUS interrupt source to check. |
| AnnaBridge | 143:86740a56073b | 413 | * This parameter can be one of the following values: |
| AnnaBridge | 167:84c0a372a020 | 414 | * @arg @ref SMBUS_IT_ERRI Errors interrupt enable |
| AnnaBridge | 167:84c0a372a020 | 415 | * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable |
| AnnaBridge | 167:84c0a372a020 | 416 | * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable |
| AnnaBridge | 167:84c0a372a020 | 417 | * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable |
| AnnaBridge | 167:84c0a372a020 | 418 | * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable |
| AnnaBridge | 167:84c0a372a020 | 419 | * @arg @ref SMBUS_IT_RXI RX interrupt enable |
| AnnaBridge | 167:84c0a372a020 | 420 | * @arg @ref SMBUS_IT_TXI TX interrupt enable |
| AnnaBridge | 167:84c0a372a020 | 421 | * |
| AnnaBridge | 143:86740a56073b | 422 | * @retval The new state of __IT__ (TRUE or FALSE). |
| AnnaBridge | 143:86740a56073b | 423 | */ |
| AnnaBridge | 143:86740a56073b | 424 | #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| AnnaBridge | 143:86740a56073b | 425 | |
| AnnaBridge | 167:84c0a372a020 | 426 | /** @brief Check whether the specified SMBUS flag is set or not. |
| AnnaBridge | 167:84c0a372a020 | 427 | * @param __HANDLE__ specifies the SMBUS Handle. |
| AnnaBridge | 167:84c0a372a020 | 428 | * @param __FLAG__ specifies the flag to check. |
| AnnaBridge | 143:86740a56073b | 429 | * This parameter can be one of the following values: |
| AnnaBridge | 167:84c0a372a020 | 430 | * @arg @ref SMBUS_FLAG_TXE Transmit data register empty |
| AnnaBridge | 167:84c0a372a020 | 431 | * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status |
| AnnaBridge | 167:84c0a372a020 | 432 | * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty |
| AnnaBridge | 167:84c0a372a020 | 433 | * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) |
| AnnaBridge | 167:84c0a372a020 | 434 | * @arg @ref SMBUS_FLAG_AF NACK received flag |
| AnnaBridge | 167:84c0a372a020 | 435 | * @arg @ref SMBUS_FLAG_STOPF STOP detection flag |
| AnnaBridge | 167:84c0a372a020 | 436 | * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) |
| AnnaBridge | 167:84c0a372a020 | 437 | * @arg @ref SMBUS_FLAG_TCR Transfer complete reload |
| AnnaBridge | 167:84c0a372a020 | 438 | * @arg @ref SMBUS_FLAG_BERR Bus error |
| AnnaBridge | 167:84c0a372a020 | 439 | * @arg @ref SMBUS_FLAG_ARLO Arbitration lost |
| AnnaBridge | 167:84c0a372a020 | 440 | * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun |
| AnnaBridge | 167:84c0a372a020 | 441 | * @arg @ref SMBUS_FLAG_PECERR PEC error in reception |
| AnnaBridge | 167:84c0a372a020 | 442 | * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag |
| AnnaBridge | 167:84c0a372a020 | 443 | * @arg @ref SMBUS_FLAG_ALERT SMBus alert |
| AnnaBridge | 167:84c0a372a020 | 444 | * @arg @ref SMBUS_FLAG_BUSY Bus busy |
| AnnaBridge | 167:84c0a372a020 | 445 | * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) |
| AnnaBridge | 167:84c0a372a020 | 446 | * |
| AnnaBridge | 143:86740a56073b | 447 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| AnnaBridge | 143:86740a56073b | 448 | */ |
| AnnaBridge | 167:84c0a372a020 | 449 | #define SMBUS_FLAG_MASK (0x0001FFFFU) |
| AnnaBridge | 143:86740a56073b | 450 | #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) |
| AnnaBridge | 167:84c0a372a020 | 451 | |
| AnnaBridge | 167:84c0a372a020 | 452 | /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. |
| AnnaBridge | 167:84c0a372a020 | 453 | * @param __HANDLE__ specifies the SMBUS Handle. |
| AnnaBridge | 167:84c0a372a020 | 454 | * @param __FLAG__ specifies the flag to clear. |
| AnnaBridge | 143:86740a56073b | 455 | * This parameter can be any combination of the following values: |
| AnnaBridge | 167:84c0a372a020 | 456 | * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) |
| AnnaBridge | 167:84c0a372a020 | 457 | * @arg @ref SMBUS_FLAG_AF NACK received flag |
| AnnaBridge | 167:84c0a372a020 | 458 | * @arg @ref SMBUS_FLAG_STOPF STOP detection flag |
| AnnaBridge | 167:84c0a372a020 | 459 | * @arg @ref SMBUS_FLAG_BERR Bus error |
| AnnaBridge | 167:84c0a372a020 | 460 | * @arg @ref SMBUS_FLAG_ARLO Arbitration lost |
| AnnaBridge | 167:84c0a372a020 | 461 | * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun |
| AnnaBridge | 167:84c0a372a020 | 462 | * @arg @ref SMBUS_FLAG_PECERR PEC error in reception |
| AnnaBridge | 167:84c0a372a020 | 463 | * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag |
| AnnaBridge | 167:84c0a372a020 | 464 | * @arg @ref SMBUS_FLAG_ALERT SMBus alert |
| AnnaBridge | 167:84c0a372a020 | 465 | * |
| AnnaBridge | 143:86740a56073b | 466 | * @retval None |
| AnnaBridge | 143:86740a56073b | 467 | */ |
| AnnaBridge | 167:84c0a372a020 | 468 | #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) |
| AnnaBridge | 143:86740a56073b | 469 | |
| AnnaBridge | 167:84c0a372a020 | 470 | /** @brief Enable the specified SMBUS peripheral. |
| AnnaBridge | 167:84c0a372a020 | 471 | * @param __HANDLE__ specifies the SMBUS Handle. |
| AnnaBridge | 167:84c0a372a020 | 472 | * @retval None |
| AnnaBridge | 167:84c0a372a020 | 473 | */ |
| AnnaBridge | 167:84c0a372a020 | 474 | #define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) |
| AnnaBridge | 143:86740a56073b | 475 | |
| AnnaBridge | 167:84c0a372a020 | 476 | /** @brief Disable the specified SMBUS peripheral. |
| AnnaBridge | 167:84c0a372a020 | 477 | * @param __HANDLE__ specifies the SMBUS Handle. |
| AnnaBridge | 167:84c0a372a020 | 478 | * @retval None |
| AnnaBridge | 167:84c0a372a020 | 479 | */ |
| AnnaBridge | 167:84c0a372a020 | 480 | #define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) |
| AnnaBridge | 143:86740a56073b | 481 | |
| AnnaBridge | 167:84c0a372a020 | 482 | /** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode. |
| AnnaBridge | 167:84c0a372a020 | 483 | * @param __HANDLE__ specifies the SMBUS Handle. |
| AnnaBridge | 167:84c0a372a020 | 484 | * @retval None |
| AnnaBridge | 167:84c0a372a020 | 485 | */ |
| AnnaBridge | 167:84c0a372a020 | 486 | #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) |
| AnnaBridge | 143:86740a56073b | 487 | |
| AnnaBridge | 143:86740a56073b | 488 | /** |
| AnnaBridge | 143:86740a56073b | 489 | * @} |
| AnnaBridge | 167:84c0a372a020 | 490 | */ |
| AnnaBridge | 143:86740a56073b | 491 | |
| AnnaBridge | 143:86740a56073b | 492 | |
| AnnaBridge | 167:84c0a372a020 | 493 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 167:84c0a372a020 | 494 | |
| AnnaBridge | 167:84c0a372a020 | 495 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 167:84c0a372a020 | 496 | /** @defgroup SMBUS_Private_Macro SMBUS Private Macros |
| AnnaBridge | 143:86740a56073b | 497 | * @{ |
| AnnaBridge | 143:86740a56073b | 498 | */ |
| AnnaBridge | 143:86740a56073b | 499 | |
| AnnaBridge | 167:84c0a372a020 | 500 | #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ |
| AnnaBridge | 167:84c0a372a020 | 501 | ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) |
| AnnaBridge | 167:84c0a372a020 | 502 | |
| AnnaBridge | 167:84c0a372a020 | 503 | #define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) |
| AnnaBridge | 167:84c0a372a020 | 504 | |
| AnnaBridge | 167:84c0a372a020 | 505 | #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ |
| AnnaBridge | 167:84c0a372a020 | 506 | ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) |
| AnnaBridge | 167:84c0a372a020 | 507 | |
| AnnaBridge | 167:84c0a372a020 | 508 | #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ |
| AnnaBridge | 167:84c0a372a020 | 509 | ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) |
| AnnaBridge | 167:84c0a372a020 | 510 | |
| AnnaBridge | 167:84c0a372a020 | 511 | #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ |
| AnnaBridge | 167:84c0a372a020 | 512 | ((MASK) == SMBUS_OA2_MASK01) || \ |
| AnnaBridge | 167:84c0a372a020 | 513 | ((MASK) == SMBUS_OA2_MASK02) || \ |
| AnnaBridge | 167:84c0a372a020 | 514 | ((MASK) == SMBUS_OA2_MASK03) || \ |
| AnnaBridge | 167:84c0a372a020 | 515 | ((MASK) == SMBUS_OA2_MASK04) || \ |
| AnnaBridge | 167:84c0a372a020 | 516 | ((MASK) == SMBUS_OA2_MASK05) || \ |
| AnnaBridge | 167:84c0a372a020 | 517 | ((MASK) == SMBUS_OA2_MASK06) || \ |
| AnnaBridge | 167:84c0a372a020 | 518 | ((MASK) == SMBUS_OA2_MASK07)) |
| AnnaBridge | 167:84c0a372a020 | 519 | |
| AnnaBridge | 167:84c0a372a020 | 520 | #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ |
| AnnaBridge | 167:84c0a372a020 | 521 | ((CALL) == SMBUS_GENERALCALL_ENABLE)) |
| AnnaBridge | 167:84c0a372a020 | 522 | |
| AnnaBridge | 167:84c0a372a020 | 523 | #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ |
| AnnaBridge | 167:84c0a372a020 | 524 | ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) |
| AnnaBridge | 167:84c0a372a020 | 525 | |
| AnnaBridge | 167:84c0a372a020 | 526 | #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ |
| AnnaBridge | 167:84c0a372a020 | 527 | ((PEC) == SMBUS_PEC_ENABLE)) |
| AnnaBridge | 167:84c0a372a020 | 528 | |
| AnnaBridge | 167:84c0a372a020 | 529 | #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ |
| AnnaBridge | 167:84c0a372a020 | 530 | ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ |
| AnnaBridge | 167:84c0a372a020 | 531 | ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) |
| AnnaBridge | 167:84c0a372a020 | 532 | |
| AnnaBridge | 167:84c0a372a020 | 533 | #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ |
| AnnaBridge | 167:84c0a372a020 | 534 | ((MODE) == SMBUS_AUTOEND_MODE) || \ |
| AnnaBridge | 167:84c0a372a020 | 535 | ((MODE) == SMBUS_SOFTEND_MODE) || \ |
| AnnaBridge | 167:84c0a372a020 | 536 | ((MODE) == SMBUS_SENDPEC_MODE) || \ |
| AnnaBridge | 167:84c0a372a020 | 537 | ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ |
| AnnaBridge | 167:84c0a372a020 | 538 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ |
| AnnaBridge | 167:84c0a372a020 | 539 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ |
| AnnaBridge | 167:84c0a372a020 | 540 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) |
| AnnaBridge | 167:84c0a372a020 | 541 | |
| AnnaBridge | 167:84c0a372a020 | 542 | |
| AnnaBridge | 167:84c0a372a020 | 543 | #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ |
| AnnaBridge | 167:84c0a372a020 | 544 | ((REQUEST) == SMBUS_GENERATE_START_READ) || \ |
| AnnaBridge | 167:84c0a372a020 | 545 | ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ |
| AnnaBridge | 167:84c0a372a020 | 546 | ((REQUEST) == SMBUS_NO_STARTSTOP)) |
| AnnaBridge | 167:84c0a372a020 | 547 | |
| AnnaBridge | 167:84c0a372a020 | 548 | |
| AnnaBridge | 167:84c0a372a020 | 549 | #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \ |
| AnnaBridge | 167:84c0a372a020 | 550 | ((REQUEST) == SMBUS_NEXT_FRAME) || \ |
| AnnaBridge | 167:84c0a372a020 | 551 | ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ |
| AnnaBridge | 167:84c0a372a020 | 552 | ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ |
| AnnaBridge | 167:84c0a372a020 | 553 | ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ |
| AnnaBridge | 167:84c0a372a020 | 554 | ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC) || \ |
| AnnaBridge | 167:84c0a372a020 | 555 | IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) |
| AnnaBridge | 167:84c0a372a020 | 556 | |
| AnnaBridge | 167:84c0a372a020 | 557 | #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ |
| AnnaBridge | 167:84c0a372a020 | 558 | ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ |
| AnnaBridge | 167:84c0a372a020 | 559 | ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ |
| AnnaBridge | 167:84c0a372a020 | 560 | ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) |
| AnnaBridge | 167:84c0a372a020 | 561 | |
| AnnaBridge | 167:84c0a372a020 | 562 | #define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) |
| AnnaBridge | 167:84c0a372a020 | 563 | #define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) |
| AnnaBridge | 167:84c0a372a020 | 564 | |
| AnnaBridge | 167:84c0a372a020 | 565 | #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ |
| AnnaBridge | 167:84c0a372a020 | 566 | (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) |
| AnnaBridge | 167:84c0a372a020 | 567 | |
| AnnaBridge | 167:84c0a372a020 | 568 | #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) |
| AnnaBridge | 167:84c0a372a020 | 569 | #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) |
| AnnaBridge | 167:84c0a372a020 | 570 | #define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) |
| AnnaBridge | 167:84c0a372a020 | 571 | #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) |
| AnnaBridge | 167:84c0a372a020 | 572 | #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) |
| AnnaBridge | 167:84c0a372a020 | 573 | |
| AnnaBridge | 167:84c0a372a020 | 574 | #define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR) |
| AnnaBridge | 167:84c0a372a020 | 575 | #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) |
| AnnaBridge | 167:84c0a372a020 | 576 | |
| AnnaBridge | 167:84c0a372a020 | 577 | #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) |
| AnnaBridge | 167:84c0a372a020 | 578 | #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) |
| AnnaBridge | 167:84c0a372a020 | 579 | |
| AnnaBridge | 143:86740a56073b | 580 | /** |
| AnnaBridge | 143:86740a56073b | 581 | * @} |
| AnnaBridge | 167:84c0a372a020 | 582 | */ |
| AnnaBridge | 167:84c0a372a020 | 583 | |
| AnnaBridge | 167:84c0a372a020 | 584 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 167:84c0a372a020 | 585 | /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions |
| AnnaBridge | 143:86740a56073b | 586 | * @{ |
| AnnaBridge | 143:86740a56073b | 587 | */ |
| AnnaBridge | 167:84c0a372a020 | 588 | |
| AnnaBridge | 167:84c0a372a020 | 589 | /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions |
| AnnaBridge | 167:84c0a372a020 | 590 | * @{ |
| AnnaBridge | 167:84c0a372a020 | 591 | */ |
| AnnaBridge | 167:84c0a372a020 | 592 | |
| AnnaBridge | 167:84c0a372a020 | 593 | /* Initialization and de-initialization functions **********************************/ |
| AnnaBridge | 167:84c0a372a020 | 594 | HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); |
| AnnaBridge | 167:84c0a372a020 | 595 | HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); |
| AnnaBridge | 167:84c0a372a020 | 596 | void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); |
| AnnaBridge | 167:84c0a372a020 | 597 | void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); |
| AnnaBridge | 167:84c0a372a020 | 598 | HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); |
| AnnaBridge | 167:84c0a372a020 | 599 | HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); |
| AnnaBridge | 143:86740a56073b | 600 | |
| AnnaBridge | 167:84c0a372a020 | 601 | /** |
| AnnaBridge | 167:84c0a372a020 | 602 | * @} |
| AnnaBridge | 167:84c0a372a020 | 603 | */ |
| AnnaBridge | 167:84c0a372a020 | 604 | |
| AnnaBridge | 167:84c0a372a020 | 605 | /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions |
| AnnaBridge | 167:84c0a372a020 | 606 | * @{ |
| AnnaBridge | 167:84c0a372a020 | 607 | */ |
| AnnaBridge | 167:84c0a372a020 | 608 | |
| AnnaBridge | 167:84c0a372a020 | 609 | /* IO operation functions *****************************************************/ |
| AnnaBridge | 167:84c0a372a020 | 610 | /** @addtogroup Blocking_mode_Polling Blocking mode Polling |
| AnnaBridge | 167:84c0a372a020 | 611 | * @{ |
| AnnaBridge | 167:84c0a372a020 | 612 | */ |
| AnnaBridge | 143:86740a56073b | 613 | /******* Blocking mode: Polling */ |
| AnnaBridge | 143:86740a56073b | 614 | HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); |
| AnnaBridge | 167:84c0a372a020 | 615 | /** |
| AnnaBridge | 167:84c0a372a020 | 616 | * @} |
| AnnaBridge | 167:84c0a372a020 | 617 | */ |
| AnnaBridge | 143:86740a56073b | 618 | |
| AnnaBridge | 167:84c0a372a020 | 619 | /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt |
| AnnaBridge | 167:84c0a372a020 | 620 | * @{ |
| AnnaBridge | 167:84c0a372a020 | 621 | */ |
| AnnaBridge | 143:86740a56073b | 622 | /******* Non-Blocking mode: Interrupt */ |
| AnnaBridge | 143:86740a56073b | 623 | HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
| AnnaBridge | 143:86740a56073b | 624 | HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
| AnnaBridge | 143:86740a56073b | 625 | HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); |
| AnnaBridge | 143:86740a56073b | 626 | HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
| AnnaBridge | 143:86740a56073b | 627 | HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
| AnnaBridge | 143:86740a56073b | 628 | |
| AnnaBridge | 167:84c0a372a020 | 629 | HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); |
| AnnaBridge | 167:84c0a372a020 | 630 | HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); |
| AnnaBridge | 167:84c0a372a020 | 631 | HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); |
| AnnaBridge | 167:84c0a372a020 | 632 | HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); |
| AnnaBridge | 167:84c0a372a020 | 633 | /** |
| AnnaBridge | 167:84c0a372a020 | 634 | * @} |
| AnnaBridge | 167:84c0a372a020 | 635 | */ |
| AnnaBridge | 167:84c0a372a020 | 636 | |
| AnnaBridge | 167:84c0a372a020 | 637 | /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks |
| AnnaBridge | 167:84c0a372a020 | 638 | * @{ |
| AnnaBridge | 167:84c0a372a020 | 639 | */ |
| AnnaBridge | 143:86740a56073b | 640 | /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ |
| AnnaBridge | 143:86740a56073b | 641 | void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); |
| AnnaBridge | 143:86740a56073b | 642 | void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); |
| AnnaBridge | 143:86740a56073b | 643 | void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| AnnaBridge | 143:86740a56073b | 644 | void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| AnnaBridge | 143:86740a56073b | 645 | void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| AnnaBridge | 143:86740a56073b | 646 | void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| AnnaBridge | 143:86740a56073b | 647 | void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); |
| AnnaBridge | 143:86740a56073b | 648 | void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| AnnaBridge | 167:84c0a372a020 | 649 | void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); |
| AnnaBridge | 143:86740a56073b | 650 | |
| AnnaBridge | 143:86740a56073b | 651 | /** |
| AnnaBridge | 143:86740a56073b | 652 | * @} |
| AnnaBridge | 143:86740a56073b | 653 | */ |
| AnnaBridge | 143:86740a56073b | 654 | |
| AnnaBridge | 167:84c0a372a020 | 655 | /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions |
| AnnaBridge | 167:84c0a372a020 | 656 | * @{ |
| AnnaBridge | 167:84c0a372a020 | 657 | */ |
| AnnaBridge | 167:84c0a372a020 | 658 | |
| AnnaBridge | 167:84c0a372a020 | 659 | /* Peripheral State and Errors functions **************************************************/ |
| AnnaBridge | 143:86740a56073b | 660 | uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); |
| AnnaBridge | 143:86740a56073b | 661 | uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); |
| AnnaBridge | 143:86740a56073b | 662 | |
| AnnaBridge | 143:86740a56073b | 663 | /** |
| AnnaBridge | 143:86740a56073b | 664 | * @} |
| AnnaBridge | 143:86740a56073b | 665 | */ |
| AnnaBridge | 143:86740a56073b | 666 | |
| AnnaBridge | 143:86740a56073b | 667 | /** |
| AnnaBridge | 143:86740a56073b | 668 | * @} |
| AnnaBridge | 143:86740a56073b | 669 | */ |
| AnnaBridge | 167:84c0a372a020 | 670 | |
| AnnaBridge | 167:84c0a372a020 | 671 | /* Private Functions ---------------------------------------------------------*/ |
| AnnaBridge | 167:84c0a372a020 | 672 | /** @defgroup SMBUS_Private_Functions SMBUS Private Functions |
| AnnaBridge | 167:84c0a372a020 | 673 | * @{ |
| AnnaBridge | 167:84c0a372a020 | 674 | */ |
| AnnaBridge | 167:84c0a372a020 | 675 | /* Private functions are defined in stm32l0xx_hal_smbus.c file */ |
| AnnaBridge | 167:84c0a372a020 | 676 | /** |
| AnnaBridge | 167:84c0a372a020 | 677 | * @} |
| AnnaBridge | 167:84c0a372a020 | 678 | */ |
| AnnaBridge | 167:84c0a372a020 | 679 | |
| AnnaBridge | 167:84c0a372a020 | 680 | /** |
| AnnaBridge | 167:84c0a372a020 | 681 | * @} |
| AnnaBridge | 167:84c0a372a020 | 682 | */ |
| AnnaBridge | 167:84c0a372a020 | 683 | |
| AnnaBridge | 167:84c0a372a020 | 684 | /** |
| AnnaBridge | 167:84c0a372a020 | 685 | * @} |
| AnnaBridge | 167:84c0a372a020 | 686 | */ |
| AnnaBridge | 167:84c0a372a020 | 687 | |
| AnnaBridge | 167:84c0a372a020 | 688 | /** |
| AnnaBridge | 167:84c0a372a020 | 689 | * @} |
| AnnaBridge | 167:84c0a372a020 | 690 | */ |
| AnnaBridge | 167:84c0a372a020 | 691 | |
| AnnaBridge | 143:86740a56073b | 692 | #ifdef __cplusplus |
| AnnaBridge | 143:86740a56073b | 693 | } |
| AnnaBridge | 143:86740a56073b | 694 | #endif |
| AnnaBridge | 143:86740a56073b | 695 | |
| AnnaBridge | 143:86740a56073b | 696 | |
| AnnaBridge | 143:86740a56073b | 697 | #endif /* __STM32L0xx_HAL_SMBUS_H */ |
| AnnaBridge | 143:86740a56073b | 698 | |
| AnnaBridge | 143:86740a56073b | 699 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
