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TARGET_NUCLEO_L011K4/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_rcc_ex.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc_ex.h@167:84c0a372a020

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	143:86740a56073b	1	/**
AnnaBridge	143:86740a56073b	2	******************************************************************************
AnnaBridge	143:86740a56073b	3	* @file stm32l0xx_hal_rcc_ex.h
AnnaBridge	143:86740a56073b	4	* @author MCD Application Team
AnnaBridge	143:86740a56073b	5	* @brief Header file of RCC HAL Extension module.
AnnaBridge	143:86740a56073b	6	******************************************************************************
AnnaBridge	143:86740a56073b	7	* @attention
AnnaBridge	143:86740a56073b	8	*
AnnaBridge	143:86740a56073b	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	143:86740a56073b	10	*
AnnaBridge	143:86740a56073b	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	143:86740a56073b	12	* are permitted provided that the following conditions are met:
AnnaBridge	143:86740a56073b	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	143:86740a56073b	14	* this list of conditions and the following disclaimer.
AnnaBridge	143:86740a56073b	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	143:86740a56073b	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	143:86740a56073b	17	* and/or other materials provided with the distribution.
AnnaBridge	143:86740a56073b	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	143:86740a56073b	19	* may be used to endorse or promote products derived from this software
AnnaBridge	143:86740a56073b	20	* without specific prior written permission.
AnnaBridge	143:86740a56073b	21	*
AnnaBridge	143:86740a56073b	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	143:86740a56073b	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	143:86740a56073b	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	143:86740a56073b	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	143:86740a56073b	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	143:86740a56073b	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	143:86740a56073b	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	143:86740a56073b	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	143:86740a56073b	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	143:86740a56073b	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	143:86740a56073b	32	*
AnnaBridge	143:86740a56073b	33	******************************************************************************
AnnaBridge	167:84c0a372a020	34	*/
AnnaBridge	143:86740a56073b	35
AnnaBridge	143:86740a56073b	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	143:86740a56073b	37	#ifndef __STM32L0xx_HAL_RCC_EX_H
AnnaBridge	143:86740a56073b	38	#define __STM32L0xx_HAL_RCC_EX_H
AnnaBridge	143:86740a56073b	39
AnnaBridge	143:86740a56073b	40	#ifdef __cplusplus
AnnaBridge	143:86740a56073b	41	extern "C" {
AnnaBridge	143:86740a56073b	42	#endif
AnnaBridge	143:86740a56073b	43
AnnaBridge	143:86740a56073b	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	45	#include "stm32l0xx_hal_def.h"
AnnaBridge	143:86740a56073b	46
AnnaBridge	143:86740a56073b	47	/** @addtogroup STM32L0xx_HAL_Driver
AnnaBridge	143:86740a56073b	48	* @{
AnnaBridge	143:86740a56073b	49	*/
AnnaBridge	143:86740a56073b	50
AnnaBridge	167:84c0a372a020	51	/** @addtogroup RCCEx
AnnaBridge	143:86740a56073b	52	* @{
AnnaBridge	143:86740a56073b	53	*/
AnnaBridge	143:86740a56073b	54
AnnaBridge	167:84c0a372a020	55	/** @addtogroup RCCEx_Private_Constants
AnnaBridge	167:84c0a372a020	56	* @{
AnnaBridge	167:84c0a372a020	57	*/
AnnaBridge	167:84c0a372a020	58
AnnaBridge	167:84c0a372a020	59
AnnaBridge	167:84c0a372a020	60	#if defined(CRS)
AnnaBridge	167:84c0a372a020	61	/* CRS IT Error Mask */
AnnaBridge	167:84c0a372a020	62	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
AnnaBridge	167:84c0a372a020	63
AnnaBridge	167:84c0a372a020	64	/* CRS Flag Error Mask */
AnnaBridge	167:84c0a372a020	65	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
AnnaBridge	167:84c0a372a020	66
AnnaBridge	167:84c0a372a020	67	#endif /* CRS */
AnnaBridge	167:84c0a372a020	68	/**
AnnaBridge	167:84c0a372a020	69	* @}
AnnaBridge	167:84c0a372a020	70	*/
AnnaBridge	167:84c0a372a020	71
AnnaBridge	167:84c0a372a020	72	/** @addtogroup RCCEx_Private_Macros
AnnaBridge	167:84c0a372a020	73	* @{
AnnaBridge	167:84c0a372a020	74	*/
AnnaBridge	167:84c0a372a020	75	#if defined (STM32L052xx) \|\| defined(STM32L062xx)
AnnaBridge	167:84c0a372a020	76	#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
AnnaBridge	167:84c0a372a020	77	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
AnnaBridge	167:84c0a372a020	78	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1))
AnnaBridge	167:84c0a372a020	79	#elif defined (STM32L053xx) \|\| defined(STM32L063xx)
AnnaBridge	167:84c0a372a020	80	#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
AnnaBridge	167:84c0a372a020	81	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
AnnaBridge	167:84c0a372a020	82	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_LCD))
AnnaBridge	167:84c0a372a020	83	#elif defined (STM32L072xx) \|\| defined(STM32L082xx)
AnnaBridge	167:84c0a372a020	84	#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
AnnaBridge	167:84c0a372a020	85	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
AnnaBridge	167:84c0a372a020	86	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_I2C3 ))
AnnaBridge	167:84c0a372a020	87	#elif defined (STM32L073xx) \|\| defined(STM32L083xx)
AnnaBridge	167:84c0a372a020	88	#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
AnnaBridge	167:84c0a372a020	89	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
AnnaBridge	167:84c0a372a020	90	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_I2C3 \| \
AnnaBridge	167:84c0a372a020	91	RCC_PERIPHCLK_LCD))
AnnaBridge	167:84c0a372a020	92	#endif
AnnaBridge	167:84c0a372a020	93
AnnaBridge	167:84c0a372a020	94	#if defined(STM32L011xx) \|\| defined(STM32L021xx) \|\| defined(STM32L031xx) \|\| defined(STM32L041xx)
AnnaBridge	167:84c0a372a020	95	#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= ( RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
AnnaBridge	167:84c0a372a020	96	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_RTC \| \
AnnaBridge	167:84c0a372a020	97	RCC_PERIPHCLK_LPTIM1))
AnnaBridge	167:84c0a372a020	98	#elif defined(STM32L051xx) \|\| defined(STM32L061xx)
AnnaBridge	167:84c0a372a020	99	#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
AnnaBridge	167:84c0a372a020	100	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
AnnaBridge	167:84c0a372a020	101	RCC_PERIPHCLK_LPTIM1))
AnnaBridge	167:84c0a372a020	102	#elif defined(STM32L071xx) \|\| defined(STM32L081xx)
AnnaBridge	167:84c0a372a020	103	#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
AnnaBridge	167:84c0a372a020	104	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
AnnaBridge	167:84c0a372a020	105	RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_I2C3))
AnnaBridge	167:84c0a372a020	106	#endif
AnnaBridge	167:84c0a372a020	107
AnnaBridge	167:84c0a372a020	108	#if defined (RCC_CCIPR_USART1SEL)
AnnaBridge	167:84c0a372a020	109	#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
AnnaBridge	167:84c0a372a020	110	((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	167:84c0a372a020	111	((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) \|\| \
AnnaBridge	167:84c0a372a020	112	((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
AnnaBridge	167:84c0a372a020	113	#endif /* RCC_CCIPR_USART1SEL */
AnnaBridge	167:84c0a372a020	114
AnnaBridge	167:84c0a372a020	115	#define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
AnnaBridge	167:84c0a372a020	116	((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	167:84c0a372a020	117	((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) \|\| \
AnnaBridge	167:84c0a372a020	118	((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
AnnaBridge	167:84c0a372a020	119
AnnaBridge	167:84c0a372a020	120	#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) \|\| \
AnnaBridge	167:84c0a372a020	121	((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	167:84c0a372a020	122	((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) \|\| \
AnnaBridge	167:84c0a372a020	123	((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
AnnaBridge	167:84c0a372a020	124
AnnaBridge	167:84c0a372a020	125	#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) \|\| \
AnnaBridge	167:84c0a372a020	126	((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)\|\| \
AnnaBridge	167:84c0a372a020	127	((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
AnnaBridge	167:84c0a372a020	128
AnnaBridge	167:84c0a372a020	129	#if defined(RCC_CCIPR_I2C3SEL)
AnnaBridge	167:84c0a372a020	130	#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) \|\| \
AnnaBridge	167:84c0a372a020	131	((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)\|\| \
AnnaBridge	167:84c0a372a020	132	((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
AnnaBridge	167:84c0a372a020	133	#endif /* RCC_CCIPR_I2C3SEL */
AnnaBridge	167:84c0a372a020	134
AnnaBridge	167:84c0a372a020	135	#if defined(USB)
AnnaBridge	167:84c0a372a020	136	#define IS_RCC_USBCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) \|\| \
AnnaBridge	167:84c0a372a020	137	((__SOURCE__) == RCC_USBCLKSOURCE_PLL))
AnnaBridge	167:84c0a372a020	138	#endif /* USB */
AnnaBridge	167:84c0a372a020	139
AnnaBridge	167:84c0a372a020	140	#if defined(RNG)
AnnaBridge	167:84c0a372a020	141	#define IS_RCC_RNGCLKSOURCE(_SOURCE_) (((_SOURCE_) == RCC_RNGCLKSOURCE_HSI48) \|\| \
AnnaBridge	167:84c0a372a020	142	((_SOURCE_) == RCC_RNGCLKSOURCE_PLLCLK))
AnnaBridge	167:84c0a372a020	143	#endif /* RNG */
AnnaBridge	167:84c0a372a020	144
AnnaBridge	167:84c0a372a020	145	#if defined(RCC_CCIPR_HSI48SEL)
AnnaBridge	167:84c0a372a020	146	#define IS_RCC_HSI48MCLKSOURCE(__HSI48MCLK__) (((__HSI48MCLK__) == RCC_HSI48M_PLL) \|\| ((__HSI48MCLK__) == RCC_HSI48M_HSI48))
AnnaBridge	167:84c0a372a020	147	#endif /* RCC_CCIPR_HSI48SEL */
AnnaBridge	167:84c0a372a020	148
AnnaBridge	167:84c0a372a020	149	#define IS_RCC_LPTIMCLK(__LPTIMCLK_) (((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_PCLK) \|\| \
AnnaBridge	167:84c0a372a020	150	((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSI) \|\| \
AnnaBridge	167:84c0a372a020	151	((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_HSI) \|\| \
AnnaBridge	167:84c0a372a020	152	((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSE))
AnnaBridge	167:84c0a372a020	153
AnnaBridge	167:84c0a372a020	154	#define IS_RCC_STOPWAKEUP_CLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) \|\| \
AnnaBridge	167:84c0a372a020	155	((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
AnnaBridge	167:84c0a372a020	156
AnnaBridge	167:84c0a372a020	157	#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) \|\| ((__SOURCE__) == RCC_LSEDRIVE_MEDIUMLOW) \|\| \
AnnaBridge	167:84c0a372a020	158	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) \|\| ((__SOURCE__) == RCC_LSEDRIVE_HIGH))
AnnaBridge	167:84c0a372a020	159
AnnaBridge	167:84c0a372a020	160	#if defined(CRS)
AnnaBridge	167:84c0a372a020	161
AnnaBridge	167:84c0a372a020	162	#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
AnnaBridge	167:84c0a372a020	163	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) \|\| \
AnnaBridge	167:84c0a372a020	164	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
AnnaBridge	167:84c0a372a020	165	#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV2) \|\| \
AnnaBridge	167:84c0a372a020	166	((_DIV_) == RCC_CRS_SYNC_DIV4) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV8) \|\| \
AnnaBridge	167:84c0a372a020	167	((_DIV_) == RCC_CRS_SYNC_DIV16) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV32) \|\| \
AnnaBridge	167:84c0a372a020	168	((_DIV_) == RCC_CRS_SYNC_DIV64) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV128))
AnnaBridge	167:84c0a372a020	169	#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
AnnaBridge	167:84c0a372a020	170	((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
AnnaBridge	167:84c0a372a020	171	#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
AnnaBridge	167:84c0a372a020	172	#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
AnnaBridge	167:84c0a372a020	173	#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
AnnaBridge	167:84c0a372a020	174	#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) \|\| \
AnnaBridge	167:84c0a372a020	175	((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
AnnaBridge	167:84c0a372a020	176	#endif /* CRS */
AnnaBridge	167:84c0a372a020	177	/**
AnnaBridge	167:84c0a372a020	178	* @}
AnnaBridge	167:84c0a372a020	179	*/
AnnaBridge	167:84c0a372a020	180
AnnaBridge	143:86740a56073b	181	/* Exported types ------------------------------------------------------------*/
AnnaBridge	167:84c0a372a020	182
AnnaBridge	167:84c0a372a020	183	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
AnnaBridge	143:86740a56073b	184	* @{
AnnaBridge	143:86740a56073b	185	*/
AnnaBridge	143:86740a56073b	186
AnnaBridge	143:86740a56073b	187	/**
AnnaBridge	143:86740a56073b	188	* @brief RCC extended clocks structure definition
AnnaBridge	143:86740a56073b	189	*/
AnnaBridge	143:86740a56073b	190	typedef struct
AnnaBridge	143:86740a56073b	191	{
AnnaBridge	167:84c0a372a020	192	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	167:84c0a372a020	193	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	167:84c0a372a020	194
AnnaBridge	167:84c0a372a020	195	uint32_t RTCClockSelection; /*!< specifies the RTC clock source.
AnnaBridge	167:84c0a372a020	196	This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
AnnaBridge	167:84c0a372a020	197
AnnaBridge	167:84c0a372a020	198	#if defined(LCD)
AnnaBridge	167:84c0a372a020	199
AnnaBridge	167:84c0a372a020	200	uint32_t LCDClockSelection; /*!< specifies the LCD clock source.
AnnaBridge	167:84c0a372a020	201	This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
AnnaBridge	167:84c0a372a020	202
AnnaBridge	167:84c0a372a020	203	#endif /* LCD */
AnnaBridge	167:84c0a372a020	204	#if defined(RCC_CCIPR_USART1SEL)
AnnaBridge	143:86740a56073b	205	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	143:86740a56073b	206	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge	167:84c0a372a020	207	#endif /* RCC_CCIPR_USART1SEL */
AnnaBridge	143:86740a56073b	208	uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge	143:86740a56073b	209	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
AnnaBridge	143:86740a56073b	210
AnnaBridge	143:86740a56073b	211	uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source
AnnaBridge	143:86740a56073b	212	This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
AnnaBridge	143:86740a56073b	213
AnnaBridge	143:86740a56073b	214	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	143:86740a56073b	215	This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
AnnaBridge	143:86740a56073b	216
AnnaBridge	167:84c0a372a020	217	#if defined(RCC_CCIPR_I2C3SEL)
AnnaBridge	143:86740a56073b	218	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
AnnaBridge	143:86740a56073b	219	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
AnnaBridge	167:84c0a372a020	220	#endif /* RCC_CCIPR_I2C3SEL */
AnnaBridge	143:86740a56073b	221	uint32_t LptimClockSelection; /*!< LPTIM1 clock source
AnnaBridge	143:86740a56073b	222	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
AnnaBridge	167:84c0a372a020	223	#if defined(USB)
AnnaBridge	167:84c0a372a020	224	uint32_t UsbClockSelection; /*!< Specifies USB and RNG Clock Selection
AnnaBridge	167:84c0a372a020	225	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
AnnaBridge	167:84c0a372a020	226	#endif /* USB */
AnnaBridge	167:84c0a372a020	227	} RCC_PeriphCLKInitTypeDef;
AnnaBridge	143:86740a56073b	228
AnnaBridge	167:84c0a372a020	229	#if defined (CRS)
AnnaBridge	143:86740a56073b	230	/**
AnnaBridge	143:86740a56073b	231	* @brief RCC_CRS Init structure definition
AnnaBridge	143:86740a56073b	232	*/
AnnaBridge	143:86740a56073b	233	typedef struct
AnnaBridge	143:86740a56073b	234	{
AnnaBridge	143:86740a56073b	235	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
AnnaBridge	143:86740a56073b	236	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
AnnaBridge	143:86740a56073b	237
AnnaBridge	143:86740a56073b	238	uint32_t Source; /*!< Specifies the SYNC signal source.
AnnaBridge	143:86740a56073b	239	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
AnnaBridge	143:86740a56073b	240
AnnaBridge	143:86740a56073b	241	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
AnnaBridge	143:86740a56073b	242	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
AnnaBridge	143:86740a56073b	243
AnnaBridge	143:86740a56073b	244	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
AnnaBridge	167:84c0a372a020	245	It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
AnnaBridge	143:86740a56073b	246	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
AnnaBridge	143:86740a56073b	247
AnnaBridge	143:86740a56073b	248	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
AnnaBridge	143:86740a56073b	249	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
AnnaBridge	143:86740a56073b	250
AnnaBridge	143:86740a56073b	251	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
AnnaBridge	143:86740a56073b	252	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
AnnaBridge	167:84c0a372a020	253
AnnaBridge	143:86740a56073b	254	}RCC_CRSInitTypeDef;
AnnaBridge	143:86740a56073b	255
AnnaBridge	143:86740a56073b	256	/**
AnnaBridge	143:86740a56073b	257	* @brief RCC_CRS Synchronization structure definition
AnnaBridge	143:86740a56073b	258	*/
AnnaBridge	143:86740a56073b	259	typedef struct
AnnaBridge	143:86740a56073b	260	{
AnnaBridge	143:86740a56073b	261	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
AnnaBridge	167:84c0a372a020	262	This parameter must be a number between 0 and 0xFFFF */
AnnaBridge	143:86740a56073b	263
AnnaBridge	143:86740a56073b	264	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
AnnaBridge	143:86740a56073b	265	This parameter must be a number between 0 and 0x3F */
AnnaBridge	167:84c0a372a020	266
AnnaBridge	143:86740a56073b	267	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
AnnaBridge	167:84c0a372a020	268	value latched in the time of the last SYNC event.
AnnaBridge	143:86740a56073b	269	This parameter must be a number between 0 and 0xFFFF */
AnnaBridge	167:84c0a372a020	270
AnnaBridge	143:86740a56073b	271	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
AnnaBridge	143:86740a56073b	272	frequency error counter latched in the time of the last SYNC event.
AnnaBridge	143:86740a56073b	273	It shows whether the actual frequency is below or above the target.
AnnaBridge	143:86740a56073b	274	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
AnnaBridge	143:86740a56073b	275
AnnaBridge	143:86740a56073b	276	}RCC_CRSSynchroInfoTypeDef;
AnnaBridge	143:86740a56073b	277
AnnaBridge	167:84c0a372a020	278	#endif /* CRS */
AnnaBridge	143:86740a56073b	279
AnnaBridge	143:86740a56073b	280	/**
AnnaBridge	143:86740a56073b	281	* @}
AnnaBridge	143:86740a56073b	282	*/
AnnaBridge	143:86740a56073b	283
AnnaBridge	167:84c0a372a020	284	/* Exported constants --------------------------------------------------------*/
AnnaBridge	143:86740a56073b	285
AnnaBridge	167:84c0a372a020	286	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
AnnaBridge	143:86740a56073b	287	* @{
AnnaBridge	143:86740a56073b	288	*/
AnnaBridge	143:86740a56073b	289
AnnaBridge	143:86740a56073b	290
AnnaBridge	143:86740a56073b	291	/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
AnnaBridge	143:86740a56073b	292	* @{
AnnaBridge	143:86740a56073b	293	*/
AnnaBridge	143:86740a56073b	294	#define RCC_EXTI_LINE_LSECSS (EXTI_IMR_IM19) /!< External interrupt line 19 connected to the LSE CSS EXTI Line /
AnnaBridge	143:86740a56073b	295	/**
AnnaBridge	143:86740a56073b	296	* @}
AnnaBridge	143:86740a56073b	297	*/
AnnaBridge	143:86740a56073b	298
AnnaBridge	167:84c0a372a020	299	/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
AnnaBridge	167:84c0a372a020	300	* @{
AnnaBridge	167:84c0a372a020	301	*/
AnnaBridge	167:84c0a372a020	302	#if defined(RCC_CCIPR_USART1SEL)
AnnaBridge	167:84c0a372a020	303	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
AnnaBridge	167:84c0a372a020	304	#endif /* RCC_CCIPR_USART1SEL */
AnnaBridge	167:84c0a372a020	305	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
AnnaBridge	167:84c0a372a020	306	#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004)
AnnaBridge	167:84c0a372a020	307	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008)
AnnaBridge	167:84c0a372a020	308	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010)
AnnaBridge	167:84c0a372a020	309	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
AnnaBridge	167:84c0a372a020	310	#if defined(USB)
AnnaBridge	167:84c0a372a020	311	#define RCC_PERIPHCLK_USB ((uint32_t)0x00000040)
AnnaBridge	167:84c0a372a020	312	#endif /* USB */
AnnaBridge	167:84c0a372a020	313	#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080)
AnnaBridge	167:84c0a372a020	314	#if defined(LCD)
AnnaBridge	167:84c0a372a020	315	#define RCC_PERIPHCLK_LCD ((uint32_t)0x00000800)
AnnaBridge	167:84c0a372a020	316	#endif /* LCD */
AnnaBridge	167:84c0a372a020	317	#if defined(RCC_CCIPR_I2C3SEL)
AnnaBridge	167:84c0a372a020	318	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
AnnaBridge	167:84c0a372a020	319	#endif /* RCC_CCIPR_I2C3SEL */
AnnaBridge	167:84c0a372a020	320
AnnaBridge	167:84c0a372a020	321	/**
AnnaBridge	167:84c0a372a020	322	* @}
AnnaBridge	167:84c0a372a020	323	*/
AnnaBridge	167:84c0a372a020	324
AnnaBridge	167:84c0a372a020	325	#if defined (RCC_CCIPR_USART1SEL)
AnnaBridge	167:84c0a372a020	326	/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source
AnnaBridge	167:84c0a372a020	327	* @{
AnnaBridge	167:84c0a372a020	328	*/
AnnaBridge	167:84c0a372a020	329	#define RCC_USART1CLKSOURCE_PCLK2 (0x00000000U)
AnnaBridge	167:84c0a372a020	330	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
AnnaBridge	167:84c0a372a020	331	#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
AnnaBridge	167:84c0a372a020	332	#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 \| RCC_CCIPR_USART1SEL_1)
AnnaBridge	167:84c0a372a020	333	/**
AnnaBridge	167:84c0a372a020	334	* @}
AnnaBridge	167:84c0a372a020	335	*/
AnnaBridge	167:84c0a372a020	336	#endif /* RCC_CCIPR_USART1SEL */
AnnaBridge	167:84c0a372a020	337
AnnaBridge	167:84c0a372a020	338	/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
AnnaBridge	143:86740a56073b	339	* @{
AnnaBridge	143:86740a56073b	340	*/
AnnaBridge	167:84c0a372a020	341	#define RCC_USART2CLKSOURCE_PCLK1 (0x00000000U)
AnnaBridge	167:84c0a372a020	342	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
AnnaBridge	167:84c0a372a020	343	#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
AnnaBridge	167:84c0a372a020	344	#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 \| RCC_CCIPR_USART2SEL_1)
AnnaBridge	167:84c0a372a020	345	/**
AnnaBridge	167:84c0a372a020	346	* @}
AnnaBridge	167:84c0a372a020	347	*/
AnnaBridge	167:84c0a372a020	348
AnnaBridge	167:84c0a372a020	349	/** @defgroup RCCEx_LPUART1_Clock_Source RCCEx LPUART1 Clock Source
AnnaBridge	167:84c0a372a020	350	* @{
AnnaBridge	167:84c0a372a020	351	*/
AnnaBridge	167:84c0a372a020	352	#define RCC_LPUART1CLKSOURCE_PCLK1 (0x00000000U)
AnnaBridge	167:84c0a372a020	353	#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
AnnaBridge	167:84c0a372a020	354	#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
AnnaBridge	167:84c0a372a020	355	#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 \| RCC_CCIPR_LPUART1SEL_1)
AnnaBridge	167:84c0a372a020	356	/**
AnnaBridge	167:84c0a372a020	357	* @}
AnnaBridge	167:84c0a372a020	358	*/
AnnaBridge	167:84c0a372a020	359
AnnaBridge	167:84c0a372a020	360	/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source
AnnaBridge	167:84c0a372a020	361	* @{
AnnaBridge	167:84c0a372a020	362	*/
AnnaBridge	167:84c0a372a020	363	#define RCC_I2C1CLKSOURCE_PCLK1 (0x00000000U)
AnnaBridge	167:84c0a372a020	364	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
AnnaBridge	167:84c0a372a020	365	#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
AnnaBridge	167:84c0a372a020	366	/**
AnnaBridge	167:84c0a372a020	367	* @}
AnnaBridge	167:84c0a372a020	368	*/
AnnaBridge	167:84c0a372a020	369
AnnaBridge	167:84c0a372a020	370	#if defined(RCC_CCIPR_I2C3SEL)
AnnaBridge	167:84c0a372a020	371
AnnaBridge	167:84c0a372a020	372	/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source
AnnaBridge	167:84c0a372a020	373	* @{
AnnaBridge	167:84c0a372a020	374	*/
AnnaBridge	167:84c0a372a020	375	#define RCC_I2C3CLKSOURCE_PCLK1 (0x00000000U)
AnnaBridge	167:84c0a372a020	376	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
AnnaBridge	167:84c0a372a020	377	#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
AnnaBridge	167:84c0a372a020	378	/**
AnnaBridge	167:84c0a372a020	379	* @}
AnnaBridge	167:84c0a372a020	380	*/
AnnaBridge	167:84c0a372a020	381	#endif /* RCC_CCIPR_I2C3SEL */
AnnaBridge	167:84c0a372a020	382
AnnaBridge	167:84c0a372a020	383	/** @defgroup RCCEx_TIM_PRescaler_Selection RCCEx TIM Prescaler Selection
AnnaBridge	167:84c0a372a020	384	* @{
AnnaBridge	167:84c0a372a020	385	*/
AnnaBridge	167:84c0a372a020	386	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
AnnaBridge	167:84c0a372a020	387	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
AnnaBridge	143:86740a56073b	388	/**
AnnaBridge	143:86740a56073b	389	* @}
AnnaBridge	143:86740a56073b	390	*/
AnnaBridge	143:86740a56073b	391
AnnaBridge	167:84c0a372a020	392	#if defined(USB)
AnnaBridge	167:84c0a372a020	393	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
AnnaBridge	167:84c0a372a020	394	* @{
AnnaBridge	167:84c0a372a020	395	*/
AnnaBridge	167:84c0a372a020	396	#define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
AnnaBridge	167:84c0a372a020	397	#define RCC_USBCLKSOURCE_PLL (0x00000000U)
AnnaBridge	167:84c0a372a020	398	/**
AnnaBridge	167:84c0a372a020	399	* @}
AnnaBridge	167:84c0a372a020	400	*/
AnnaBridge	167:84c0a372a020	401	#endif /* USB */
AnnaBridge	167:84c0a372a020	402
AnnaBridge	167:84c0a372a020	403	#if defined(RNG)
AnnaBridge	167:84c0a372a020	404	/** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source
AnnaBridge	167:84c0a372a020	405	* @{
AnnaBridge	167:84c0a372a020	406	*/
AnnaBridge	167:84c0a372a020	407	#define RCC_RNGCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
AnnaBridge	167:84c0a372a020	408	#define RCC_RNGCLKSOURCE_PLLCLK (0x00000000U)
AnnaBridge	167:84c0a372a020	409	/**
AnnaBridge	167:84c0a372a020	410	* @}
AnnaBridge	167:84c0a372a020	411	*/
AnnaBridge	167:84c0a372a020	412	#endif /* RNG */
AnnaBridge	167:84c0a372a020	413
AnnaBridge	167:84c0a372a020	414	#if defined(RCC_CCIPR_HSI48SEL)
AnnaBridge	167:84c0a372a020	415	/** @defgroup RCCEx_HSI48M_Clock_Source RCCEx HSI48M Clock Source
AnnaBridge	167:84c0a372a020	416	* @{
AnnaBridge	167:84c0a372a020	417	*/
AnnaBridge	167:84c0a372a020	418	#define RCC_FLAG_HSI48 SYSCFG_CFGR3_VREFINT_RDYF
AnnaBridge	167:84c0a372a020	419
AnnaBridge	167:84c0a372a020	420	#define RCC_HSI48M_PLL (0x00000000U)
AnnaBridge	167:84c0a372a020	421	#define RCC_HSI48M_HSI48 RCC_CCIPR_HSI48SEL
AnnaBridge	167:84c0a372a020	422
AnnaBridge	167:84c0a372a020	423	/**
AnnaBridge	167:84c0a372a020	424	* @}
AnnaBridge	167:84c0a372a020	425	*/
AnnaBridge	167:84c0a372a020	426	#endif /* RCC_CCIPR_HSI48SEL */
AnnaBridge	167:84c0a372a020	427
AnnaBridge	167:84c0a372a020	428	/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
AnnaBridge	167:84c0a372a020	429	* @{
AnnaBridge	167:84c0a372a020	430	*/
AnnaBridge	167:84c0a372a020	431	#define RCC_LPTIM1CLKSOURCE_PCLK (0x00000000U)
AnnaBridge	167:84c0a372a020	432	#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
AnnaBridge	167:84c0a372a020	433	#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
AnnaBridge	167:84c0a372a020	434	#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
AnnaBridge	167:84c0a372a020	435	/**
AnnaBridge	167:84c0a372a020	436	* @}
AnnaBridge	167:84c0a372a020	437	*/
AnnaBridge	167:84c0a372a020	438
AnnaBridge	167:84c0a372a020	439	/** @defgroup RCCEx_StopWakeUp_Clock RCCEx StopWakeUp Clock
AnnaBridge	143:86740a56073b	440	* @{
AnnaBridge	143:86740a56073b	441	*/
AnnaBridge	167:84c0a372a020	442
AnnaBridge	167:84c0a372a020	443	#define RCC_STOP_WAKEUPCLOCK_MSI (0x00000000U)
AnnaBridge	167:84c0a372a020	444	#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK
AnnaBridge	167:84c0a372a020	445	/**
AnnaBridge	167:84c0a372a020	446	* @}
AnnaBridge	167:84c0a372a020	447	*/
AnnaBridge	167:84c0a372a020	448
AnnaBridge	167:84c0a372a020	449	/** @defgroup RCCEx_LSEDrive_Configuration RCCEx LSE Drive Configuration
AnnaBridge	167:84c0a372a020	450	* @{
AnnaBridge	167:84c0a372a020	451	*/
AnnaBridge	167:84c0a372a020	452
AnnaBridge	167:84c0a372a020	453	#define RCC_LSEDRIVE_LOW (0x00000000U)
AnnaBridge	167:84c0a372a020	454	#define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0
AnnaBridge	167:84c0a372a020	455	#define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1
AnnaBridge	167:84c0a372a020	456	#define RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV
AnnaBridge	167:84c0a372a020	457	/**
AnnaBridge	167:84c0a372a020	458	* @}
AnnaBridge	167:84c0a372a020	459	*/
AnnaBridge	167:84c0a372a020	460
AnnaBridge	167:84c0a372a020	461	#if defined(CRS)
AnnaBridge	167:84c0a372a020	462
AnnaBridge	167:84c0a372a020	463	/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
AnnaBridge	167:84c0a372a020	464	* @{
AnnaBridge	167:84c0a372a020	465	*/
AnnaBridge	167:84c0a372a020	466	#define RCC_CRS_NONE (0x00000000U)
AnnaBridge	167:84c0a372a020	467	#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001)
AnnaBridge	167:84c0a372a020	468	#define RCC_CRS_SYNCOK ((uint32_t)0x00000002)
AnnaBridge	167:84c0a372a020	469	#define RCC_CRS_SYNCWARN ((uint32_t)0x00000004)
AnnaBridge	167:84c0a372a020	470	#define RCC_CRS_SYNCERR ((uint32_t)0x00000008)
AnnaBridge	167:84c0a372a020	471	#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010)
AnnaBridge	167:84c0a372a020	472	#define RCC_CRS_TRIMOVF ((uint32_t)0x00000020)
AnnaBridge	167:84c0a372a020	473
AnnaBridge	167:84c0a372a020	474	/**
AnnaBridge	167:84c0a372a020	475	* @}
AnnaBridge	167:84c0a372a020	476	*/
AnnaBridge	167:84c0a372a020	477
AnnaBridge	167:84c0a372a020	478	/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source
AnnaBridge	167:84c0a372a020	479	* @{
AnnaBridge	167:84c0a372a020	480	*/
AnnaBridge	167:84c0a372a020	481	#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /!< Synchro Signal source GPIO /
AnnaBridge	167:84c0a372a020	482	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
AnnaBridge	167:84c0a372a020	483	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
AnnaBridge	167:84c0a372a020	484	/**
AnnaBridge	167:84c0a372a020	485	* @}
AnnaBridge	167:84c0a372a020	486	*/
AnnaBridge	167:84c0a372a020	487
AnnaBridge	167:84c0a372a020	488	/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider
AnnaBridge	167:84c0a372a020	489	* @{
AnnaBridge	167:84c0a372a020	490	*/
AnnaBridge	167:84c0a372a020	491	#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /!< Synchro Signal not divided (default) /
AnnaBridge	143:86740a56073b	492	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
AnnaBridge	143:86740a56073b	493	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
AnnaBridge	143:86740a56073b	494	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
AnnaBridge	143:86740a56073b	495	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
AnnaBridge	143:86740a56073b	496	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
AnnaBridge	143:86740a56073b	497	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
AnnaBridge	143:86740a56073b	498	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
AnnaBridge	143:86740a56073b	499	/**
AnnaBridge	143:86740a56073b	500	* @}
AnnaBridge	143:86740a56073b	501	*/
AnnaBridge	143:86740a56073b	502
AnnaBridge	167:84c0a372a020	503	/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity
AnnaBridge	143:86740a56073b	504	* @{
AnnaBridge	143:86740a56073b	505	*/
AnnaBridge	167:84c0a372a020	506	#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /!< Synchro Active on rising edge (default) /
AnnaBridge	167:84c0a372a020	507	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
AnnaBridge	143:86740a56073b	508	/**
AnnaBridge	143:86740a56073b	509	* @}
AnnaBridge	143:86740a56073b	510	*/
AnnaBridge	167:84c0a372a020	511
AnnaBridge	167:84c0a372a020	512	/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value
AnnaBridge	143:86740a56073b	513	* @{
AnnaBridge	143:86740a56073b	514	*/
AnnaBridge	167:84c0a372a020	515	#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
AnnaBridge	167:84c0a372a020	516	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
AnnaBridge	143:86740a56073b	517	/**
AnnaBridge	143:86740a56073b	518	* @}
AnnaBridge	143:86740a56073b	519	*/
AnnaBridge	143:86740a56073b	520
AnnaBridge	167:84c0a372a020	521	/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value
AnnaBridge	143:86740a56073b	522	* @{
AnnaBridge	143:86740a56073b	523	*/
AnnaBridge	167:84c0a372a020	524	#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /!< Default Frequency error limit /
AnnaBridge	143:86740a56073b	525	/**
AnnaBridge	143:86740a56073b	526	* @}
AnnaBridge	143:86740a56073b	527	*/
AnnaBridge	143:86740a56073b	528
AnnaBridge	167:84c0a372a020	529	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye
AnnaBridge	143:86740a56073b	530	* @{
AnnaBridge	143:86740a56073b	531	*/
AnnaBridge	167:84c0a372a020	532	#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
AnnaBridge	167:84c0a372a020	533	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
AnnaBridge	167:84c0a372a020	534	corresponds to a higher output frequency */
AnnaBridge	143:86740a56073b	535	/**
AnnaBridge	143:86740a56073b	536	* @}
AnnaBridge	143:86740a56073b	537	*/
AnnaBridge	143:86740a56073b	538
AnnaBridge	167:84c0a372a020	539	/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction
AnnaBridge	143:86740a56073b	540	* @{
AnnaBridge	143:86740a56073b	541	*/
AnnaBridge	167:84c0a372a020	542	#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /!< Upcounting direction, the actual frequency is above the target /
AnnaBridge	167:84c0a372a020	543	#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
AnnaBridge	143:86740a56073b	544	/**
AnnaBridge	143:86740a56073b	545	* @}
AnnaBridge	143:86740a56073b	546	*/
AnnaBridge	143:86740a56073b	547
AnnaBridge	167:84c0a372a020	548	/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
AnnaBridge	143:86740a56073b	549	* @{
AnnaBridge	143:86740a56073b	550	*/
AnnaBridge	167:84c0a372a020	551	#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /!< SYNC event OK /
AnnaBridge	167:84c0a372a020	552	#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /!< SYNC warning /
AnnaBridge	167:84c0a372a020	553	#define RCC_CRS_IT_ERR CRS_CR_ERRIE /!< Error /
AnnaBridge	167:84c0a372a020	554	#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /!< Expected SYNC /
AnnaBridge	167:84c0a372a020	555	#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /!< SYNC error /
AnnaBridge	167:84c0a372a020	556	#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /!< SYNC missed /
AnnaBridge	167:84c0a372a020	557	#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /!< Trimming overflow or underflow /
AnnaBridge	143:86740a56073b	558
AnnaBridge	143:86740a56073b	559	/**
AnnaBridge	143:86740a56073b	560	* @}
AnnaBridge	143:86740a56073b	561	*/
AnnaBridge	143:86740a56073b	562
AnnaBridge	167:84c0a372a020	563	/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
AnnaBridge	143:86740a56073b	564	* @{
AnnaBridge	143:86740a56073b	565	*/
AnnaBridge	167:84c0a372a020	566	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK flag /
AnnaBridge	167:84c0a372a020	567	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning flag /
AnnaBridge	167:84c0a372a020	568	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /!< Error flag /
AnnaBridge	167:84c0a372a020	569	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC flag /
AnnaBridge	167:84c0a372a020	570	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
AnnaBridge	167:84c0a372a020	571	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
AnnaBridge	167:84c0a372a020	572	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
AnnaBridge	143:86740a56073b	573
AnnaBridge	143:86740a56073b	574	/**
AnnaBridge	143:86740a56073b	575	* @}
AnnaBridge	143:86740a56073b	576	*/
AnnaBridge	143:86740a56073b	577
AnnaBridge	167:84c0a372a020	578	#endif /* CRS */
AnnaBridge	167:84c0a372a020	579
AnnaBridge	143:86740a56073b	580	/**
AnnaBridge	143:86740a56073b	581	* @}
AnnaBridge	167:84c0a372a020	582	*/
AnnaBridge	143:86740a56073b	583
AnnaBridge	143:86740a56073b	584	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	585	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
AnnaBridge	167:84c0a372a020	586	* @{
AnnaBridge	167:84c0a372a020	587	*/
AnnaBridge	167:84c0a372a020	588
AnnaBridge	143:86740a56073b	589	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable
AnnaBridge	143:86740a56073b	590	* @brief Enable or disable the AHB peripheral clock.
AnnaBridge	143:86740a56073b	591	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	143:86740a56073b	592	* is disabled and the application software has to enable this clock before
AnnaBridge	143:86740a56073b	593	* using it.
AnnaBridge	143:86740a56073b	594	* @{
AnnaBridge	143:86740a56073b	595	*/
AnnaBridge	143:86740a56073b	596
AnnaBridge	143:86740a56073b	597	#if defined(STM32L062xx) \|\| defined(STM32L063xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx) \|\| defined(STM32L041xx) \|\| defined(STM32L021xx)
AnnaBridge	167:84c0a372a020	598	#define __HAL_RCC_AES_CLK_ENABLE() do { \
AnnaBridge	167:84c0a372a020	599	__IO uint32_t tmpreg; \
AnnaBridge	167:84c0a372a020	600	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\
AnnaBridge	167:84c0a372a020	601	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	167:84c0a372a020	602	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\
AnnaBridge	167:84c0a372a020	603	UNUSED(tmpreg); \
AnnaBridge	167:84c0a372a020	604	} while(0)
AnnaBridge	143:86740a56073b	605	#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_CRYPEN))
AnnaBridge	167:84c0a372a020	606
AnnaBridge	167:84c0a372a020	607	#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN) != RESET)
AnnaBridge	167:84c0a372a020	608	#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN) == RESET)
AnnaBridge	167:84c0a372a020	609
AnnaBridge	143:86740a56073b	610	#endif /* STM32L062xx \|\| STM32L063xx \|\| STM32L072xx \|\| STM32L073xx \|\| STM32L082xx \|\| STM32L083xx \|\| STM32L041xx \|\| STM32L021xx */
AnnaBridge	143:86740a56073b	611
AnnaBridge	143:86740a56073b	612	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge	167:84c0a372a020	613	#define __HAL_RCC_TSC_CLK_ENABLE() do { \
AnnaBridge	167:84c0a372a020	614	__IO uint32_t tmpreg; \
AnnaBridge	167:84c0a372a020	615	SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
AnnaBridge	167:84c0a372a020	616	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	167:84c0a372a020	617	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
AnnaBridge	167:84c0a372a020	618	UNUSED(tmpreg); \
AnnaBridge	167:84c0a372a020	619	} while(0)
AnnaBridge	143:86740a56073b	620	#define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_TSCEN))
AnnaBridge	143:86740a56073b	621
AnnaBridge	167:84c0a372a020	622	#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) != RESET)
AnnaBridge	167:84c0a372a020	623	#define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) == RESET)
AnnaBridge	167:84c0a372a020	624
AnnaBridge	167:84c0a372a020	625	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
AnnaBridge	167:84c0a372a020	626	__IO uint32_t tmpreg; \
AnnaBridge	167:84c0a372a020	627	SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN);\
AnnaBridge	167:84c0a372a020	628	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	167:84c0a372a020	629	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN);\
AnnaBridge	167:84c0a372a020	630	UNUSED(tmpreg); \
AnnaBridge	167:84c0a372a020	631	} while(0)
AnnaBridge	143:86740a56073b	632	#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_RNGEN))
AnnaBridge	167:84c0a372a020	633
AnnaBridge	167:84c0a372a020	634	#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) != RESET)
AnnaBridge	167:84c0a372a020	635	#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) == RESET)
AnnaBridge	167:84c0a372a020	636	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
AnnaBridge	167:84c0a372a020	637
AnnaBridge	167:84c0a372a020	638	/**
AnnaBridge	167:84c0a372a020	639	* @}
AnnaBridge	167:84c0a372a020	640	*/
AnnaBridge	167:84c0a372a020	641
AnnaBridge	167:84c0a372a020	642	/** @defgroup RCCEx_IOPORT_Clock_Enable_Disable IOPORT Peripheral Clock Enable Disable
AnnaBridge	167:84c0a372a020	643	* @brief Enable or disable the IOPORT peripheral clock.
AnnaBridge	167:84c0a372a020	644	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	167:84c0a372a020	645	* is disabled and the application software has to enable this clock before
AnnaBridge	167:84c0a372a020	646	* using it.
AnnaBridge	167:84c0a372a020	647	* @{
AnnaBridge	167:84c0a372a020	648	*/
AnnaBridge	167:84c0a372a020	649	#if defined(GPIOE)
AnnaBridge	167:84c0a372a020	650	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge	167:84c0a372a020	651	__IO uint32_t tmpreg; \
AnnaBridge	167:84c0a372a020	652	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
AnnaBridge	167:84c0a372a020	653	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	167:84c0a372a020	654	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
AnnaBridge	167:84c0a372a020	655	UNUSED(tmpreg); \
AnnaBridge	167:84c0a372a020	656	} while(0)
AnnaBridge	167:84c0a372a020	657
AnnaBridge	167:84c0a372a020	658	#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIOEEN))
AnnaBridge	167:84c0a372a020	659
AnnaBridge	167:84c0a372a020	660	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) != RESET)
AnnaBridge	167:84c0a372a020	661	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) == RESET)
AnnaBridge	167:84c0a372a020	662
AnnaBridge	167:84c0a372a020	663	#endif /* GPIOE */
AnnaBridge	167:84c0a372a020	664	#if defined(GPIOD)
AnnaBridge	167:84c0a372a020	665	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge	167:84c0a372a020	666	__IO uint32_t tmpreg; \
AnnaBridge	167:84c0a372a020	667	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
AnnaBridge	167:84c0a372a020	668	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	167:84c0a372a020	669	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
AnnaBridge	167:84c0a372a020	670	UNUSED(tmpreg); \
AnnaBridge	167:84c0a372a020	671	} while(0)
AnnaBridge	167:84c0a372a020	672	#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIODEN))
AnnaBridge	167:84c0a372a020	673
AnnaBridge	167:84c0a372a020	674	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) != RESET)
AnnaBridge	167:84c0a372a020	675	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) == RESET)
AnnaBridge	167:84c0a372a020	676
AnnaBridge	167:84c0a372a020	677	#endif /* GPIOD */
AnnaBridge	167:84c0a372a020	678	/**
AnnaBridge	167:84c0a372a020	679	* @}
AnnaBridge	167:84c0a372a020	680	*/
AnnaBridge	167:84c0a372a020	681
AnnaBridge	167:84c0a372a020	682	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge	167:84c0a372a020	683	* @brief Enable or disable the APB1 peripheral clock.
AnnaBridge	167:84c0a372a020	684	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	167:84c0a372a020	685	* is disabled and the application software has to enable this clock before
AnnaBridge	167:84c0a372a020	686	* using it.
AnnaBridge	167:84c0a372a020	687	* @{
AnnaBridge	167:84c0a372a020	688	*/
AnnaBridge	167:84c0a372a020	689
AnnaBridge	167:84c0a372a020	690	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge	167:84c0a372a020	691	#define __HAL_RCC_USB_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN))
AnnaBridge	167:84c0a372a020	692	#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN))
AnnaBridge	167:84c0a372a020	693
AnnaBridge	167:84c0a372a020	694	#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN) != RESET)
AnnaBridge	167:84c0a372a020	695	#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN) == RESET)
AnnaBridge	167:84c0a372a020	696
AnnaBridge	167:84c0a372a020	697	#define __HAL_RCC_CRS_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_CRSEN))
AnnaBridge	167:84c0a372a020	698	#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR,(RCC_APB1ENR_CRSEN))
AnnaBridge	167:84c0a372a020	699
AnnaBridge	167:84c0a372a020	700	#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN) != RESET)
AnnaBridge	167:84c0a372a020	701	#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN) == RESET)
AnnaBridge	167:84c0a372a020	702
AnnaBridge	167:84c0a372a020	703	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
AnnaBridge	167:84c0a372a020	704
AnnaBridge	167:84c0a372a020	705
AnnaBridge	167:84c0a372a020	706	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
AnnaBridge	167:84c0a372a020	707	#define __HAL_RCC_LCD_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN))
AnnaBridge	167:84c0a372a020	708	#define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN))
AnnaBridge	167:84c0a372a020	709
AnnaBridge	167:84c0a372a020	710	#define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN) != RESET)
AnnaBridge	167:84c0a372a020	711	#define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN) == RESET)
AnnaBridge	167:84c0a372a020	712
AnnaBridge	167:84c0a372a020	713	#endif /* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx */
AnnaBridge	167:84c0a372a020	714
AnnaBridge	167:84c0a372a020	715	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \
AnnaBridge	167:84c0a372a020	716	\|\| defined(STM32L052xx) \|\| defined(STM32L062xx) \
AnnaBridge	167:84c0a372a020	717	\|\| defined(STM32L051xx) \|\| defined(STM32L061xx)
AnnaBridge	167:84c0a372a020	718	#define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
AnnaBridge	167:84c0a372a020	719	#define __HAL_RCC_TIM6_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
AnnaBridge	167:84c0a372a020	720	#define __HAL_RCC_SPI2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
AnnaBridge	167:84c0a372a020	721	#define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
AnnaBridge	167:84c0a372a020	722	#define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
AnnaBridge	167:84c0a372a020	723	#define __HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
AnnaBridge	167:84c0a372a020	724	#define __HAL_RCC_I2C2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
AnnaBridge	167:84c0a372a020	725	#define __HAL_RCC_DAC_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
AnnaBridge	167:84c0a372a020	726	#define __HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
AnnaBridge	167:84c0a372a020	727
AnnaBridge	167:84c0a372a020	728	#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
AnnaBridge	167:84c0a372a020	729	#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
AnnaBridge	167:84c0a372a020	730	#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
AnnaBridge	167:84c0a372a020	731	#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
AnnaBridge	167:84c0a372a020	732	#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
AnnaBridge	167:84c0a372a020	733	#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
AnnaBridge	167:84c0a372a020	734	#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
AnnaBridge	167:84c0a372a020	735	#define __HAL_RCC_DAC_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
AnnaBridge	167:84c0a372a020	736	#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
AnnaBridge	167:84c0a372a020	737
AnnaBridge	167:84c0a372a020	738	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) != RESET)
AnnaBridge	167:84c0a372a020	739	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) != RESET)
AnnaBridge	167:84c0a372a020	740	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) != RESET)
AnnaBridge	167:84c0a372a020	741	#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) != RESET)
AnnaBridge	167:84c0a372a020	742	#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) != RESET)
AnnaBridge	167:84c0a372a020	743	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) != RESET)
AnnaBridge	167:84c0a372a020	744	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) != RESET)
AnnaBridge	167:84c0a372a020	745	#define __HAL_RCC_DAC_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) != RESET)
AnnaBridge	167:84c0a372a020	746	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) != RESET)
AnnaBridge	167:84c0a372a020	747	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) == RESET)
AnnaBridge	167:84c0a372a020	748	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) == RESET)
AnnaBridge	167:84c0a372a020	749	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) == RESET)
AnnaBridge	167:84c0a372a020	750	#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) == RESET)
AnnaBridge	167:84c0a372a020	751	#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) == RESET)
AnnaBridge	167:84c0a372a020	752	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) == RESET)
AnnaBridge	167:84c0a372a020	753	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) == RESET)
AnnaBridge	167:84c0a372a020	754	#define __HAL_RCC_DAC_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) == RESET)
AnnaBridge	167:84c0a372a020	755	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) == RESET)
AnnaBridge	167:84c0a372a020	756
AnnaBridge	167:84c0a372a020	757	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
AnnaBridge	167:84c0a372a020	758	/* STM32L052xx \|\| STM32L062xx \|\| */
AnnaBridge	167:84c0a372a020	759	/* STM32L053xx \|\| STM32L063xx \|\| */
AnnaBridge	167:84c0a372a020	760
AnnaBridge	167:84c0a372a020	761	#if defined(STM32L011xx) \|\| defined(STM32L021xx) \|\| defined(STM32L031xx) \|\| defined(STM32L041xx)
AnnaBridge	167:84c0a372a020	762	#define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
AnnaBridge	167:84c0a372a020	763	#define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
AnnaBridge	167:84c0a372a020	764	#define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
AnnaBridge	167:84c0a372a020	765	#define __HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
AnnaBridge	167:84c0a372a020	766	#define __HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
AnnaBridge	167:84c0a372a020	767
AnnaBridge	167:84c0a372a020	768	#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
AnnaBridge	167:84c0a372a020	769	#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
AnnaBridge	167:84c0a372a020	770	#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
AnnaBridge	167:84c0a372a020	771	#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
AnnaBridge	167:84c0a372a020	772	#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
AnnaBridge	167:84c0a372a020	773
AnnaBridge	167:84c0a372a020	774	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) != RESET)
AnnaBridge	167:84c0a372a020	775	#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) != RESET)
AnnaBridge	167:84c0a372a020	776	#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) != RESET)
AnnaBridge	167:84c0a372a020	777	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) != RESET)
AnnaBridge	167:84c0a372a020	778	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) != RESET)
AnnaBridge	167:84c0a372a020	779	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) == RESET)
AnnaBridge	167:84c0a372a020	780	#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) == RESET)
AnnaBridge	167:84c0a372a020	781	#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) == RESET)
AnnaBridge	167:84c0a372a020	782	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) == RESET)
AnnaBridge	167:84c0a372a020	783	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) == RESET)
AnnaBridge	167:84c0a372a020	784
AnnaBridge	167:84c0a372a020	785	#endif /* STM32L011xx \|\| STM32L021xx \|\| STM32L031xx \|\| STM32L041xx */
AnnaBridge	167:84c0a372a020	786
AnnaBridge	167:84c0a372a020	787
AnnaBridge	167:84c0a372a020	788	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \
AnnaBridge	167:84c0a372a020	789	\|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \
AnnaBridge	167:84c0a372a020	790	\|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
AnnaBridge	167:84c0a372a020	791	#define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
AnnaBridge	167:84c0a372a020	792	#define __HAL_RCC_TIM3_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN))
AnnaBridge	167:84c0a372a020	793	#define __HAL_RCC_TIM6_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
AnnaBridge	167:84c0a372a020	794	#define __HAL_RCC_TIM7_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN))
AnnaBridge	167:84c0a372a020	795	#define __HAL_RCC_SPI2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
AnnaBridge	167:84c0a372a020	796	#define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
AnnaBridge	167:84c0a372a020	797	#define __HAL_RCC_USART4_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN))
AnnaBridge	167:84c0a372a020	798	#define __HAL_RCC_USART5_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN))
AnnaBridge	167:84c0a372a020	799	#define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
AnnaBridge	167:84c0a372a020	800	#define __HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
AnnaBridge	167:84c0a372a020	801	#define __HAL_RCC_I2C2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
AnnaBridge	167:84c0a372a020	802	#define __HAL_RCC_I2C3_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN))
AnnaBridge	167:84c0a372a020	803	#define __HAL_RCC_DAC_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
AnnaBridge	167:84c0a372a020	804	#define __HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
AnnaBridge	167:84c0a372a020	805
AnnaBridge	167:84c0a372a020	806	#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
AnnaBridge	167:84c0a372a020	807	#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN))
AnnaBridge	167:84c0a372a020	808	#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
AnnaBridge	167:84c0a372a020	809	#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN))
AnnaBridge	167:84c0a372a020	810	#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
AnnaBridge	167:84c0a372a020	811	#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
AnnaBridge	167:84c0a372a020	812	#define __HAL_RCC_USART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN))
AnnaBridge	167:84c0a372a020	813	#define __HAL_RCC_USART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN))
AnnaBridge	167:84c0a372a020	814	#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
AnnaBridge	167:84c0a372a020	815	#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
AnnaBridge	167:84c0a372a020	816	#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
AnnaBridge	167:84c0a372a020	817	#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN))
AnnaBridge	167:84c0a372a020	818	#define __HAL_RCC_DAC_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
AnnaBridge	167:84c0a372a020	819	#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
AnnaBridge	167:84c0a372a020	820
AnnaBridge	167:84c0a372a020	821	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) != RESET)
AnnaBridge	167:84c0a372a020	822	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN) != RESET)
AnnaBridge	167:84c0a372a020	823	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) != RESET)
AnnaBridge	167:84c0a372a020	824	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN) != RESET)
AnnaBridge	167:84c0a372a020	825	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) != RESET)
AnnaBridge	167:84c0a372a020	826	#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) != RESET)
AnnaBridge	167:84c0a372a020	827	#define __HAL_RCC_USART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN) != RESET)
AnnaBridge	167:84c0a372a020	828	#define __HAL_RCC_USART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN) != RESET)
AnnaBridge	167:84c0a372a020	829	#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) != RESET)
AnnaBridge	167:84c0a372a020	830	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) != RESET)
AnnaBridge	167:84c0a372a020	831	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) != RESET)
AnnaBridge	167:84c0a372a020	832	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN) != RESET)
AnnaBridge	167:84c0a372a020	833	#define __HAL_RCC_DAC_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) != RESET)
AnnaBridge	167:84c0a372a020	834	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) != RESET)
AnnaBridge	167:84c0a372a020	835	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) == RESET)
AnnaBridge	167:84c0a372a020	836	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN) == RESET)
AnnaBridge	167:84c0a372a020	837	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) == RESET)
AnnaBridge	167:84c0a372a020	838	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN) == RESET)
AnnaBridge	167:84c0a372a020	839	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) == RESET)
AnnaBridge	167:84c0a372a020	840	#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) == RESET)
AnnaBridge	167:84c0a372a020	841	#define __HAL_RCC_USART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN) == RESET)
AnnaBridge	167:84c0a372a020	842	#define __HAL_RCC_USART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN) == RESET)
AnnaBridge	167:84c0a372a020	843	#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) == RESET)
AnnaBridge	167:84c0a372a020	844	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) == RESET)
AnnaBridge	167:84c0a372a020	845	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) == RESET)
AnnaBridge	167:84c0a372a020	846	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN) == RESET)
AnnaBridge	167:84c0a372a020	847	#define __HAL_RCC_DAC_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) == RESET)
AnnaBridge	167:84c0a372a020	848	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) == RESET)
AnnaBridge	167:84c0a372a020	849
AnnaBridge	167:84c0a372a020	850	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
AnnaBridge	167:84c0a372a020	851	/* STM32L072xx \|\| STM32L082xx \|\| */
AnnaBridge	167:84c0a372a020	852	/* STM32L073xx \|\| STM32L083xx */
AnnaBridge	167:84c0a372a020	853
AnnaBridge	167:84c0a372a020	854	/**
AnnaBridge	167:84c0a372a020	855	* @}
AnnaBridge	167:84c0a372a020	856	*/
AnnaBridge	167:84c0a372a020	857
AnnaBridge	167:84c0a372a020	858	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \
AnnaBridge	167:84c0a372a020	859	\|\| defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \
AnnaBridge	167:84c0a372a020	860	\|\| defined(STM32L051xx) \|\| defined(STM32L061xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx) \
AnnaBridge	167:84c0a372a020	861	\|\| defined(STM32L031xx) \|\| defined(STM32L041xx) \|\| defined(STM32L011xx) \|\| defined(STM32L021xx)
AnnaBridge	167:84c0a372a020	862	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge	167:84c0a372a020	863	* @brief Enable or disable the APB2 peripheral clock.
AnnaBridge	167:84c0a372a020	864	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	167:84c0a372a020	865	* is disabled and the application software has to enable this clock before
AnnaBridge	167:84c0a372a020	866	* using it.
AnnaBridge	167:84c0a372a020	867	* @{
AnnaBridge	167:84c0a372a020	868	*/
AnnaBridge	167:84c0a372a020	869	#define __HAL_RCC_TIM21_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN))
AnnaBridge	167:84c0a372a020	870	#if !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge	167:84c0a372a020	871	#define __HAL_RCC_TIM22_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN))
AnnaBridge	167:84c0a372a020	872	#endif
AnnaBridge	167:84c0a372a020	873	#define __HAL_RCC_ADC1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN))
AnnaBridge	167:84c0a372a020	874	#define __HAL_RCC_SPI1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN))
AnnaBridge	167:84c0a372a020	875	#define __HAL_RCC_USART1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN))
AnnaBridge	167:84c0a372a020	876
AnnaBridge	167:84c0a372a020	877	#define __HAL_RCC_TIM21_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN))
AnnaBridge	167:84c0a372a020	878	#if !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge	167:84c0a372a020	879	#define __HAL_RCC_TIM22_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN))
AnnaBridge	167:84c0a372a020	880	#endif
AnnaBridge	167:84c0a372a020	881	#define __HAL_RCC_ADC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN))
AnnaBridge	167:84c0a372a020	882	#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN))
AnnaBridge	167:84c0a372a020	883	#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN))
AnnaBridge	167:84c0a372a020	884	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
AnnaBridge	167:84c0a372a020	885	#define __HAL_RCC_FIREWALL_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN))
AnnaBridge	167:84c0a372a020	886	#define __HAL_RCC_FIREWALL_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN))
AnnaBridge	167:84c0a372a020	887	#endif /* !(STM32L011xx) && !(STM32L021xx) && !STM32L031xx && !STM32L041xx */
AnnaBridge	167:84c0a372a020	888
AnnaBridge	167:84c0a372a020	889	#define __HAL_RCC_TIM21_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM21EN) != RESET)
AnnaBridge	167:84c0a372a020	890	#if !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge	167:84c0a372a020	891	#define __HAL_RCC_TIM22_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM22EN) != RESET)
AnnaBridge	167:84c0a372a020	892	#endif
AnnaBridge	167:84c0a372a020	893	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN) != RESET)
AnnaBridge	167:84c0a372a020	894	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET)
AnnaBridge	167:84c0a372a020	895	#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET)
AnnaBridge	167:84c0a372a020	896
AnnaBridge	167:84c0a372a020	897	#define __HAL_RCC_TIM21_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN) == RESET)
AnnaBridge	167:84c0a372a020	898	#if !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge	167:84c0a372a020	899	#define __HAL_RCC_TIM22_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN) == RESET)
AnnaBridge	167:84c0a372a020	900	#endif
AnnaBridge	167:84c0a372a020	901	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN) == RESET)
AnnaBridge	167:84c0a372a020	902	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN) == RESET)
AnnaBridge	167:84c0a372a020	903	#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN) == RESET)
AnnaBridge	167:84c0a372a020	904	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
AnnaBridge	167:84c0a372a020	905	#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MIFIEN) != RESET)
AnnaBridge	167:84c0a372a020	906	#define __HAL_RCC_FIREWALL_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN) == RESET)
AnnaBridge	167:84c0a372a020	907	#endif /* !(STM32L011xx) && !(STM32L021xx) && !STM32L031xx && !STM32L041xx */
AnnaBridge	167:84c0a372a020	908
AnnaBridge	167:84c0a372a020	909	#endif /* STM32L051xx \|\| STM32L061xx \|\| STM32L071xx \|\| STM32L081xx \|\| */
AnnaBridge	167:84c0a372a020	910	/* STM32L052xx \|\| STM32L062xx \|\| STM32L072xx \|\| STM32L082xx \|\| */
AnnaBridge	167:84c0a372a020	911	/* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx \|\| */
AnnaBridge	167:84c0a372a020	912	/* STM32L031xx \|\| STM32L041xx \|\| STM32L011xx \|\| STM32L021xx */
AnnaBridge	167:84c0a372a020	913
AnnaBridge	167:84c0a372a020	914	/**
AnnaBridge	167:84c0a372a020	915	* @}
AnnaBridge	167:84c0a372a020	916	*/
AnnaBridge	167:84c0a372a020	917
AnnaBridge	167:84c0a372a020	918	/** @defgroup RCCEx_AHB_Force_Release_Reset AHB Peripheral Force Release Reset
AnnaBridge	167:84c0a372a020	919	* @brief Force or release AHB peripheral reset.
AnnaBridge	167:84c0a372a020	920	* @{
AnnaBridge	167:84c0a372a020	921	*/
AnnaBridge	167:84c0a372a020	922	#if defined(STM32L062xx) \|\| defined(STM32L063xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx) \|\| defined(STM32L041xx) \|\| defined(STM32L021xx)
AnnaBridge	167:84c0a372a020	923	#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRYPRST))
AnnaBridge	167:84c0a372a020	924	#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRYPRST))
AnnaBridge	167:84c0a372a020	925	#endif /* STM32L062xx \|\| STM32L063xx \|\| STM32L072xx \|\| STM32L073xx \|\| STM32L082xx \|\| STM32L083xx \|\| STM32L041xx \|\| STM32L021xx*/
AnnaBridge	167:84c0a372a020	926
AnnaBridge	167:84c0a372a020	927	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge	167:84c0a372a020	928	#define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_TSCRST))
AnnaBridge	167:84c0a372a020	929	#define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_TSCRST))
AnnaBridge	167:84c0a372a020	930	#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_RNGRST))
AnnaBridge	167:84c0a372a020	931	#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_RNGRST))
AnnaBridge	143:86740a56073b	932	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
AnnaBridge	143:86740a56073b	933
AnnaBridge	167:84c0a372a020	934	/**
AnnaBridge	167:84c0a372a020	935	* @}
AnnaBridge	167:84c0a372a020	936	*/
AnnaBridge	167:84c0a372a020	937
AnnaBridge	167:84c0a372a020	938	/** @defgroup RCCEx_IOPORT_Force_Release_Reset IOPORT Peripheral Force Release Reset
AnnaBridge	167:84c0a372a020	939	* @brief Force or release IOPORT peripheral reset.
AnnaBridge	167:84c0a372a020	940	* @{
AnnaBridge	167:84c0a372a020	941	*/
AnnaBridge	167:84c0a372a020	942	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \
AnnaBridge	167:84c0a372a020	943	\|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \
AnnaBridge	167:84c0a372a020	944	\|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
AnnaBridge	167:84c0a372a020	945	#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOERST))
AnnaBridge	167:84c0a372a020	946
AnnaBridge	167:84c0a372a020	947	#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIOERST))
AnnaBridge	167:84c0a372a020	948
AnnaBridge	167:84c0a372a020	949	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
AnnaBridge	167:84c0a372a020	950	/* STM32L072xx \|\| STM32L082xx \|\| */
AnnaBridge	167:84c0a372a020	951	/* STM32L073xx \|\| STM32L083xx */
AnnaBridge	167:84c0a372a020	952	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
AnnaBridge	167:84c0a372a020	953	#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIODRST))
AnnaBridge	167:84c0a372a020	954	#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIODRST))
AnnaBridge	167:84c0a372a020	955	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */
AnnaBridge	167:84c0a372a020	956	/**
AnnaBridge	167:84c0a372a020	957	* @}
AnnaBridge	167:84c0a372a020	958	*/
AnnaBridge	167:84c0a372a020	959
AnnaBridge	167:84c0a372a020	960	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
AnnaBridge	167:84c0a372a020	961	* @brief Force or release APB1 peripheral reset.
AnnaBridge	167:84c0a372a020	962	* @{
AnnaBridge	167:84c0a372a020	963	*/
AnnaBridge	167:84c0a372a020	964
AnnaBridge	167:84c0a372a020	965	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \
AnnaBridge	167:84c0a372a020	966	\|\| defined(STM32L052xx) \|\| defined(STM32L062xx) \
AnnaBridge	167:84c0a372a020	967	\|\| defined(STM32L051xx) \|\| defined(STM32L061xx)
AnnaBridge	167:84c0a372a020	968	#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
AnnaBridge	167:84c0a372a020	969	#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
AnnaBridge	167:84c0a372a020	970	#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
AnnaBridge	167:84c0a372a020	971	#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
AnnaBridge	167:84c0a372a020	972	#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
AnnaBridge	167:84c0a372a020	973	#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
AnnaBridge	167:84c0a372a020	974	#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
AnnaBridge	167:84c0a372a020	975	#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
AnnaBridge	167:84c0a372a020	976	#define __HAL_RCC_DAC_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
AnnaBridge	167:84c0a372a020	977
AnnaBridge	167:84c0a372a020	978	#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
AnnaBridge	167:84c0a372a020	979	#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
AnnaBridge	167:84c0a372a020	980	#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
AnnaBridge	167:84c0a372a020	981	#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
AnnaBridge	167:84c0a372a020	982	#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
AnnaBridge	167:84c0a372a020	983	#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
AnnaBridge	167:84c0a372a020	984	#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
AnnaBridge	167:84c0a372a020	985	#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
AnnaBridge	167:84c0a372a020	986	#define __HAL_RCC_DAC_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
AnnaBridge	167:84c0a372a020	987	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
AnnaBridge	167:84c0a372a020	988	/* STM32L052xx \|\| STM32L062xx \|\| */
AnnaBridge	167:84c0a372a020	989	/* STM32L053xx \|\| STM32L063xx */
AnnaBridge	167:84c0a372a020	990	#if defined(STM32L011xx) \|\| defined(STM32L021xx) \|\| defined(STM32L031xx) \|\| defined(STM32L041xx)
AnnaBridge	167:84c0a372a020	991	#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
AnnaBridge	167:84c0a372a020	992	#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
AnnaBridge	167:84c0a372a020	993	#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
AnnaBridge	167:84c0a372a020	994	#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
AnnaBridge	167:84c0a372a020	995	#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
AnnaBridge	167:84c0a372a020	996
AnnaBridge	167:84c0a372a020	997	#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
AnnaBridge	167:84c0a372a020	998	#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
AnnaBridge	167:84c0a372a020	999	#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
AnnaBridge	167:84c0a372a020	1000	#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
AnnaBridge	167:84c0a372a020	1001	#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
AnnaBridge	167:84c0a372a020	1002	#endif /* STM32L031xx \|\| STM32L041xx \|\| STM32L011xx \|\| STM32L021xx */
AnnaBridge	167:84c0a372a020	1003
AnnaBridge	167:84c0a372a020	1004	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \
AnnaBridge	167:84c0a372a020	1005	\|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \
AnnaBridge	167:84c0a372a020	1006	\|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
AnnaBridge	167:84c0a372a020	1007	#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
AnnaBridge	167:84c0a372a020	1008	#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST))
AnnaBridge	167:84c0a372a020	1009	#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
AnnaBridge	167:84c0a372a020	1010	#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST))
AnnaBridge	167:84c0a372a020	1011	#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
AnnaBridge	167:84c0a372a020	1012	#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
AnnaBridge	167:84c0a372a020	1013	#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
AnnaBridge	167:84c0a372a020	1014	#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST))
AnnaBridge	167:84c0a372a020	1015	#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
AnnaBridge	167:84c0a372a020	1016	#define __HAL_RCC_USART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST))
AnnaBridge	167:84c0a372a020	1017	#define __HAL_RCC_USART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST))
AnnaBridge	167:84c0a372a020	1018	#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
AnnaBridge	167:84c0a372a020	1019	#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
AnnaBridge	167:84c0a372a020	1020	#define __HAL_RCC_DAC_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
AnnaBridge	167:84c0a372a020	1021
AnnaBridge	167:84c0a372a020	1022	#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
AnnaBridge	167:84c0a372a020	1023	#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST))
AnnaBridge	167:84c0a372a020	1024	#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
AnnaBridge	167:84c0a372a020	1025	#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST))
AnnaBridge	167:84c0a372a020	1026	#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
AnnaBridge	167:84c0a372a020	1027	#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
AnnaBridge	167:84c0a372a020	1028	#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
AnnaBridge	167:84c0a372a020	1029	#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST))
AnnaBridge	167:84c0a372a020	1030	#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
AnnaBridge	167:84c0a372a020	1031	#define __HAL_RCC_USART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST))
AnnaBridge	167:84c0a372a020	1032	#define __HAL_RCC_USART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST))
AnnaBridge	167:84c0a372a020	1033	#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
AnnaBridge	167:84c0a372a020	1034	#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
AnnaBridge	167:84c0a372a020	1035	#define __HAL_RCC_DAC_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
AnnaBridge	167:84c0a372a020	1036	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
AnnaBridge	167:84c0a372a020	1037	/* STM32L072xx \|\| STM32L082xx \|\| */
AnnaBridge	167:84c0a372a020	1038	/* STM32L073xx \|\| STM32L083xx \|\| */
AnnaBridge	167:84c0a372a020	1039
AnnaBridge	167:84c0a372a020	1040	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge	167:84c0a372a020	1041	#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USBRST))
AnnaBridge	167:84c0a372a020	1042	#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USBRST))
AnnaBridge	167:84c0a372a020	1043	#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_CRSRST))
AnnaBridge	167:84c0a372a020	1044	#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR,(RCC_APB1RSTR_CRSRST))
AnnaBridge	167:84c0a372a020	1045	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
AnnaBridge	167:84c0a372a020	1046
AnnaBridge	167:84c0a372a020	1047	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
AnnaBridge	167:84c0a372a020	1048	#define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LCDRST))
AnnaBridge	167:84c0a372a020	1049	#define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LCDRST))
AnnaBridge	167:84c0a372a020	1050	#endif /* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx */
AnnaBridge	167:84c0a372a020	1051
AnnaBridge	167:84c0a372a020	1052	/**
AnnaBridge	167:84c0a372a020	1053	* @}
AnnaBridge	167:84c0a372a020	1054	*/
AnnaBridge	167:84c0a372a020	1055
AnnaBridge	167:84c0a372a020	1056	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \
AnnaBridge	167:84c0a372a020	1057	\|\| defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \
AnnaBridge	167:84c0a372a020	1058	\|\| defined(STM32L051xx) \|\| defined(STM32L061xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
AnnaBridge	167:84c0a372a020	1059
AnnaBridge	167:84c0a372a020	1060	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
AnnaBridge	167:84c0a372a020	1061	* @brief Force or release APB2 peripheral reset.
AnnaBridge	167:84c0a372a020	1062	* @{
AnnaBridge	167:84c0a372a020	1063	*/
AnnaBridge	167:84c0a372a020	1064	#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST))
AnnaBridge	167:84c0a372a020	1065	#define __HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
AnnaBridge	167:84c0a372a020	1066	#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
AnnaBridge	167:84c0a372a020	1067	#define __HAL_RCC_TIM21_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
AnnaBridge	167:84c0a372a020	1068	#if !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge	167:84c0a372a020	1069	#define __HAL_RCC_TIM22_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
AnnaBridge	167:84c0a372a020	1070	#endif
AnnaBridge	167:84c0a372a020	1071
AnnaBridge	167:84c0a372a020	1072	#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST))
AnnaBridge	167:84c0a372a020	1073	#define __HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
AnnaBridge	167:84c0a372a020	1074	#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
AnnaBridge	167:84c0a372a020	1075	#define __HAL_RCC_TIM21_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
AnnaBridge	167:84c0a372a020	1076	#if !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge	167:84c0a372a020	1077	#define __HAL_RCC_TIM22_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
AnnaBridge	167:84c0a372a020	1078	#endif
AnnaBridge	167:84c0a372a020	1079	#endif /* STM32L051xx \|\| STM32L061xx \|\| STM32L071xx \|\| STM32L081xx \|\| */
AnnaBridge	167:84c0a372a020	1080	/* STM32L052xx \|\| STM32L062xx \|\| STM32L072xx \|\| STM32L082xx \|\| */
AnnaBridge	167:84c0a372a020	1081	/* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx \|\| */
AnnaBridge	167:84c0a372a020	1082	#if defined(STM32L011xx) \|\| defined(STM32L021xx) \|\| defined(STM32L031xx) \|\| defined(STM32L041xx)
AnnaBridge	167:84c0a372a020	1083	#define __HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
AnnaBridge	167:84c0a372a020	1084	#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
AnnaBridge	167:84c0a372a020	1085	#define __HAL_RCC_TIM21_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
AnnaBridge	167:84c0a372a020	1086	#if !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge	167:84c0a372a020	1087	#define __HAL_RCC_TIM22_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
AnnaBridge	167:84c0a372a020	1088	#endif
AnnaBridge	167:84c0a372a020	1089	#define __HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
AnnaBridge	167:84c0a372a020	1090	#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
AnnaBridge	167:84c0a372a020	1091	#define __HAL_RCC_TIM21_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
AnnaBridge	167:84c0a372a020	1092	#if !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge	167:84c0a372a020	1093	#define __HAL_RCC_TIM22_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
AnnaBridge	167:84c0a372a020	1094	#endif
AnnaBridge	167:84c0a372a020	1095	#endif /* STM32L031xx \|\| STM32L041xx \|\| STM32L011xx \|\| STM32L021xx*/
AnnaBridge	167:84c0a372a020	1096
AnnaBridge	167:84c0a372a020	1097	/**
AnnaBridge	167:84c0a372a020	1098	* @}
AnnaBridge	167:84c0a372a020	1099	*/
AnnaBridge	167:84c0a372a020	1100
AnnaBridge	167:84c0a372a020	1101	/** @defgroup RCCEx_AHB_Clock_Sleep_Enable_Disable AHB Peripheral Clock Sleep Enable Disable
AnnaBridge	167:84c0a372a020	1102	* @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
AnnaBridge	167:84c0a372a020	1103	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	167:84c0a372a020	1104	* power consumption.
AnnaBridge	167:84c0a372a020	1105	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	167:84c0a372a020	1106	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	167:84c0a372a020	1107	* @{
AnnaBridge	167:84c0a372a020	1108	*/
AnnaBridge	167:84c0a372a020	1109
AnnaBridge	167:84c0a372a020	1110	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge	167:84c0a372a020	1111	#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_TSCSMEN))
AnnaBridge	167:84c0a372a020	1112	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_RNGSMEN))
AnnaBridge	167:84c0a372a020	1113	#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_TSCSMEN))
AnnaBridge	167:84c0a372a020	1114	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_RNGSMEN))
AnnaBridge	167:84c0a372a020	1115
AnnaBridge	167:84c0a372a020	1116	#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_TSCSMEN) != RESET)
AnnaBridge	167:84c0a372a020	1117	#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) != RESET)
AnnaBridge	167:84c0a372a020	1118	#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_TSCSMEN) == RESET)
AnnaBridge	167:84c0a372a020	1119	#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) == RESET)
AnnaBridge	167:84c0a372a020	1120	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
AnnaBridge	167:84c0a372a020	1121
AnnaBridge	167:84c0a372a020	1122	#if defined(STM32L062xx) \|\| defined(STM32L063xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx) \|\| defined(STM32L041xx)
AnnaBridge	167:84c0a372a020	1123	#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBLPENR, (RCC_AHBSMENR_CRYPSMEN))
AnnaBridge	167:84c0a372a020	1124	#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBLPENR, (RCC_AHBSMENR_CRYPSMEN))
AnnaBridge	167:84c0a372a020	1125
AnnaBridge	167:84c0a372a020	1126	#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBLPENR, RCC_AHBSMENR_CRYPSMEN) != RESET)
AnnaBridge	167:84c0a372a020	1127	#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBLPENR, RCC_AHBSMENR_CRYPSMEN) == RESET)
AnnaBridge	167:84c0a372a020	1128	#endif /* STM32L062xx \|\| STM32L063xx \|\| STM32L072xx \|\| STM32L073xx \|\| STM32L082xx \|\| STM32L083xx \|\| STM32L041xx */
AnnaBridge	167:84c0a372a020	1129
AnnaBridge	167:84c0a372a020	1130	/**
AnnaBridge	167:84c0a372a020	1131	* @}
AnnaBridge	167:84c0a372a020	1132	*/
AnnaBridge	167:84c0a372a020	1133
AnnaBridge	167:84c0a372a020	1134	/** @defgroup RCCEx_IOPORT_Clock_Sleep_Enable_Disable IOPORT Peripheral Clock Sleep Enable Disable
AnnaBridge	167:84c0a372a020	1135	* @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
AnnaBridge	167:84c0a372a020	1136	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	167:84c0a372a020	1137	* power consumption.
AnnaBridge	167:84c0a372a020	1138	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	167:84c0a372a020	1139	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	167:84c0a372a020	1140	* @{
AnnaBridge	167:84c0a372a020	1141	*/
AnnaBridge	167:84c0a372a020	1142	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \
AnnaBridge	167:84c0a372a020	1143	\|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \
AnnaBridge	167:84c0a372a020	1144	\|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
AnnaBridge	167:84c0a372a020	1145	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOESMEN))
AnnaBridge	167:84c0a372a020	1146	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIOESMEN))
AnnaBridge	167:84c0a372a020	1147
AnnaBridge	167:84c0a372a020	1148	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) != RESET)
AnnaBridge	167:84c0a372a020	1149	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) == RESET)
AnnaBridge	167:84c0a372a020	1150	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
AnnaBridge	167:84c0a372a020	1151	/* STM32L072xx \|\| STM32L082xx \|\| */
AnnaBridge	167:84c0a372a020	1152	/* STM32L073xx \|\| STM32L083xx \|\| */
AnnaBridge	167:84c0a372a020	1153	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
AnnaBridge	167:84c0a372a020	1154	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIODSMEN))
AnnaBridge	167:84c0a372a020	1155	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIODSMEN))
AnnaBridge	167:84c0a372a020	1156
AnnaBridge	167:84c0a372a020	1157	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) != RESET)
AnnaBridge	167:84c0a372a020	1158	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) == RESET)
AnnaBridge	167:84c0a372a020	1159	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */
AnnaBridge	167:84c0a372a020	1160	/**
AnnaBridge	167:84c0a372a020	1161	* @}
AnnaBridge	167:84c0a372a020	1162	*/
AnnaBridge	167:84c0a372a020	1163
AnnaBridge	167:84c0a372a020	1164
AnnaBridge	167:84c0a372a020	1165	/** @defgroup RCCEx_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
AnnaBridge	167:84c0a372a020	1166	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	167:84c0a372a020	1167	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	167:84c0a372a020	1168	* power consumption.
AnnaBridge	167:84c0a372a020	1169	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	167:84c0a372a020	1170	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	167:84c0a372a020	1171	* @{
AnnaBridge	167:84c0a372a020	1172	*/
AnnaBridge	167:84c0a372a020	1173
AnnaBridge	167:84c0a372a020	1174	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \
AnnaBridge	167:84c0a372a020	1175	\|\| defined(STM32L052xx) \|\| defined(STM32L062xx) \
AnnaBridge	167:84c0a372a020	1176	\|\| defined(STM32L051xx) \|\| defined(STM32L061xx)
AnnaBridge	167:84c0a372a020	1177	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
AnnaBridge	167:84c0a372a020	1178	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
AnnaBridge	167:84c0a372a020	1179	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
AnnaBridge	167:84c0a372a020	1180	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
AnnaBridge	167:84c0a372a020	1181	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
AnnaBridge	167:84c0a372a020	1182	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
AnnaBridge	167:84c0a372a020	1183	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
AnnaBridge	167:84c0a372a020	1184	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
AnnaBridge	167:84c0a372a020	1185	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
AnnaBridge	167:84c0a372a020	1186
AnnaBridge	167:84c0a372a020	1187	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
AnnaBridge	167:84c0a372a020	1188	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
AnnaBridge	167:84c0a372a020	1189	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
AnnaBridge	167:84c0a372a020	1190	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
AnnaBridge	167:84c0a372a020	1191	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
AnnaBridge	167:84c0a372a020	1192	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
AnnaBridge	167:84c0a372a020	1193	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
AnnaBridge	167:84c0a372a020	1194	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
AnnaBridge	167:84c0a372a020	1195	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
AnnaBridge	167:84c0a372a020	1196
AnnaBridge	167:84c0a372a020	1197	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1198	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1199	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1200	#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1201	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1202	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1203	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1204	#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) != RESET)
AnnaBridge	167:84c0a372a020	1205	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1206	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1207	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1208	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1209	#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1210	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1211	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1212	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1213	#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) == RESET)
AnnaBridge	167:84c0a372a020	1214	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1215	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
AnnaBridge	167:84c0a372a020	1216	/* STM32L052xx \|\| STM32L062xx \|\| */
AnnaBridge	167:84c0a372a020	1217	/* STM32L053xx \|\| STM32L063xx */
AnnaBridge	167:84c0a372a020	1218
AnnaBridge	167:84c0a372a020	1219	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \
AnnaBridge	167:84c0a372a020	1220	\|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \
AnnaBridge	167:84c0a372a020	1221	\|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
AnnaBridge	167:84c0a372a020	1222	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
AnnaBridge	167:84c0a372a020	1223	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN))
AnnaBridge	167:84c0a372a020	1224	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
AnnaBridge	167:84c0a372a020	1225	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN))
AnnaBridge	167:84c0a372a020	1226	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
AnnaBridge	167:84c0a372a020	1227	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
AnnaBridge	167:84c0a372a020	1228	#define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN))
AnnaBridge	167:84c0a372a020	1229	#define __HAL_RCC_USART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN))
AnnaBridge	167:84c0a372a020	1230	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
AnnaBridge	167:84c0a372a020	1231	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
AnnaBridge	167:84c0a372a020	1232	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
AnnaBridge	167:84c0a372a020	1233	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN))
AnnaBridge	167:84c0a372a020	1234	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
AnnaBridge	167:84c0a372a020	1235	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
AnnaBridge	167:84c0a372a020	1236
AnnaBridge	167:84c0a372a020	1237	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
AnnaBridge	167:84c0a372a020	1238	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN))
AnnaBridge	167:84c0a372a020	1239	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
AnnaBridge	167:84c0a372a020	1240	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN))
AnnaBridge	167:84c0a372a020	1241	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
AnnaBridge	167:84c0a372a020	1242	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
AnnaBridge	167:84c0a372a020	1243	#define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN))
AnnaBridge	167:84c0a372a020	1244	#define __HAL_RCC_USART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN))
AnnaBridge	167:84c0a372a020	1245	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
AnnaBridge	167:84c0a372a020	1246	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
AnnaBridge	167:84c0a372a020	1247	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
AnnaBridge	167:84c0a372a020	1248	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN))
AnnaBridge	167:84c0a372a020	1249	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
AnnaBridge	167:84c0a372a020	1250	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
AnnaBridge	167:84c0a372a020	1251
AnnaBridge	167:84c0a372a020	1252	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1253	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM3SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1254	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1255	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM7SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1256	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1257	#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1258	#define __HAL_RCC_USART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART4SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1259	#define __HAL_RCC_USART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART5SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1260	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1261	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1262	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1263	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C3SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1264	#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) != RESET)
AnnaBridge	167:84c0a372a020	1265	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1266	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1267	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM3SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1268	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1269	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM7SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1270	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1271	#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1272	#define __HAL_RCC_USART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART4SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1273	#define __HAL_RCC_USART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART5SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1274	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1275	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1276	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1277	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C3SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1278	#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) == RESET)
AnnaBridge	167:84c0a372a020	1279	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1280	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
AnnaBridge	167:84c0a372a020	1281	/* STM32L072xx \|\| STM32L082xx \|\| */
AnnaBridge	167:84c0a372a020	1282	/* STM32L073xx \|\| STM32L083xx \|\| */
AnnaBridge	167:84c0a372a020	1283
AnnaBridge	167:84c0a372a020	1284	#if defined(STM32L011xx) \|\| defined(STM32L021xx) \|\| defined(STM32L031xx) \|\| defined(STM32L041xx)
AnnaBridge	167:84c0a372a020	1285	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
AnnaBridge	167:84c0a372a020	1286	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
AnnaBridge	167:84c0a372a020	1287	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
AnnaBridge	167:84c0a372a020	1288	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
AnnaBridge	167:84c0a372a020	1289	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
AnnaBridge	167:84c0a372a020	1290
AnnaBridge	167:84c0a372a020	1291	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
AnnaBridge	167:84c0a372a020	1292	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
AnnaBridge	167:84c0a372a020	1293	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
AnnaBridge	167:84c0a372a020	1294	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
AnnaBridge	167:84c0a372a020	1295	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
AnnaBridge	167:84c0a372a020	1296
AnnaBridge	167:84c0a372a020	1297	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1298	#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1299	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1300	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1301	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1302	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1303	#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1304	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1305	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1306	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1307
AnnaBridge	167:84c0a372a020	1308	#endif /* STM32L031xx \|\| STM32L041xx \|\| STM32L011xx \|\| STM32L021xx */
AnnaBridge	167:84c0a372a020	1309
AnnaBridge	167:84c0a372a020	1310	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge	167:84c0a372a020	1311	#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USBSMEN))
AnnaBridge	167:84c0a372a020	1312	#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USBSMEN))
AnnaBridge	167:84c0a372a020	1313	#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_CRSSMEN))
AnnaBridge	167:84c0a372a020	1314	#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_CRSSMEN))
AnnaBridge	167:84c0a372a020	1315
AnnaBridge	167:84c0a372a020	1316	#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USBSMEN) != RESET)
AnnaBridge	167:84c0a372a020	1317	#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USBSMEN) == RESET)
AnnaBridge	167:84c0a372a020	1318	#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_CRSSMEN) != RESET)
AnnaBridge	167:84c0a372a020	1319	#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_CRSSMEN) == RESET)
AnnaBridge	167:84c0a372a020	1320	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
AnnaBridge	167:84c0a372a020	1321
AnnaBridge	167:84c0a372a020	1322	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
AnnaBridge	167:84c0a372a020	1323	#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LCDSMEN))
AnnaBridge	167:84c0a372a020	1324	#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LCDSMEN))
AnnaBridge	167:84c0a372a020	1325
AnnaBridge	167:84c0a372a020	1326	#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LCDSMEN) != RESET)
AnnaBridge	167:84c0a372a020	1327	#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LCDSMEN) == RESET)
AnnaBridge	167:84c0a372a020	1328	#endif /* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx */
AnnaBridge	167:84c0a372a020	1329
AnnaBridge	167:84c0a372a020	1330	/**
AnnaBridge	167:84c0a372a020	1331	* @}
AnnaBridge	167:84c0a372a020	1332	*/
AnnaBridge	167:84c0a372a020	1333
AnnaBridge	167:84c0a372a020	1334	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \
AnnaBridge	167:84c0a372a020	1335	\|\| defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \
AnnaBridge	167:84c0a372a020	1336	\|\| defined(STM32L051xx) \|\| defined(STM32L061xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx) \
AnnaBridge	167:84c0a372a020	1337	\|\| defined(STM32L031xx) \|\| defined(STM32L041xx) \|\| defined(STM32L011xx) \|\| defined(STM32L021xx)
AnnaBridge	167:84c0a372a020	1338
AnnaBridge	167:84c0a372a020	1339	/** @defgroup RCCEx_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
AnnaBridge	167:84c0a372a020	1340	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	167:84c0a372a020	1341	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	167:84c0a372a020	1342	* power consumption.
AnnaBridge	167:84c0a372a020	1343	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	167:84c0a372a020	1344	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	167:84c0a372a020	1345	* @{
AnnaBridge	167:84c0a372a020	1346	*/
AnnaBridge	167:84c0a372a020	1347	#define __HAL_RCC_TIM21_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN))
AnnaBridge	167:84c0a372a020	1348	#if !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge	167:84c0a372a020	1349	#define __HAL_RCC_TIM22_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN))
AnnaBridge	167:84c0a372a020	1350	#endif
AnnaBridge	167:84c0a372a020	1351	#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN))
AnnaBridge	167:84c0a372a020	1352	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN))
AnnaBridge	167:84c0a372a020	1353	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN))
AnnaBridge	167:84c0a372a020	1354
AnnaBridge	167:84c0a372a020	1355	#define __HAL_RCC_TIM21_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN))
AnnaBridge	167:84c0a372a020	1356	#if !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge	167:84c0a372a020	1357	#define __HAL_RCC_TIM22_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN))
AnnaBridge	167:84c0a372a020	1358	#endif
AnnaBridge	167:84c0a372a020	1359	#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN))
AnnaBridge	167:84c0a372a020	1360	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN))
AnnaBridge	167:84c0a372a020	1361	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN))
AnnaBridge	167:84c0a372a020	1362
AnnaBridge	167:84c0a372a020	1363	#define __HAL_RCC_TIM21_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM21SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1364	#if !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge	167:84c0a372a020	1365	#define __HAL_RCC_TIM22_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM22SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1366	#endif
AnnaBridge	167:84c0a372a020	1367	#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_ADC1SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1368	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1369	#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1370
AnnaBridge	167:84c0a372a020	1371	#define __HAL_RCC_TIM21_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1372	#if !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge	167:84c0a372a020	1373	#define __HAL_RCC_TIM22_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1374	#endif
AnnaBridge	167:84c0a372a020	1375	#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1376	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1377	#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN) == RESET)
AnnaBridge	167:84c0a372a020	1378
AnnaBridge	167:84c0a372a020	1379	/**
AnnaBridge	167:84c0a372a020	1380	* @}
AnnaBridge	167:84c0a372a020	1381	*/
AnnaBridge	167:84c0a372a020	1382
AnnaBridge	167:84c0a372a020	1383	#endif /* STM32L051xx \|\| STM32L061xx \|\| STM32L071xx \|\| STM32L081xx \|\| */
AnnaBridge	167:84c0a372a020	1384	/* STM32L052xx \|\| STM32L062xx \|\| STM32L072xx \|\| STM32L082xx \|\| */
AnnaBridge	167:84c0a372a020	1385	/* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx \|\| */
AnnaBridge	167:84c0a372a020	1386	/* STM32L031xx \|\| STM32L041xx \|\| STM32L011xx \|\| STM32L021xx */
AnnaBridge	167:84c0a372a020	1387
AnnaBridge	143:86740a56073b	1388
AnnaBridge	143:86740a56073b	1389	/**
AnnaBridge	143:86740a56073b	1390	* @brief Enable interrupt on RCC LSE CSS EXTI Line 19.
AnnaBridge	143:86740a56073b	1391	* @retval None
AnnaBridge	143:86740a56073b	1392	*/
AnnaBridge	143:86740a56073b	1393	#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
AnnaBridge	143:86740a56073b	1394
AnnaBridge	143:86740a56073b	1395	/**
AnnaBridge	143:86740a56073b	1396	* @brief Disable interrupt on RCC LSE CSS EXTI Line 19.
AnnaBridge	143:86740a56073b	1397	* @retval None
AnnaBridge	143:86740a56073b	1398	*/
AnnaBridge	143:86740a56073b	1399	#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
AnnaBridge	143:86740a56073b	1400
AnnaBridge	143:86740a56073b	1401	/**
AnnaBridge	143:86740a56073b	1402	* @brief Enable event on RCC LSE CSS EXTI Line 19.
AnnaBridge	143:86740a56073b	1403	* @retval None.
AnnaBridge	143:86740a56073b	1404	*/
AnnaBridge	143:86740a56073b	1405	#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
AnnaBridge	143:86740a56073b	1406
AnnaBridge	143:86740a56073b	1407	/**
AnnaBridge	143:86740a56073b	1408	* @brief Disable event on RCC LSE CSS EXTI Line 19.
AnnaBridge	143:86740a56073b	1409	* @retval None.
AnnaBridge	143:86740a56073b	1410	*/
AnnaBridge	143:86740a56073b	1411	#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
AnnaBridge	143:86740a56073b	1412
AnnaBridge	143:86740a56073b	1413
AnnaBridge	143:86740a56073b	1414	/**
AnnaBridge	143:86740a56073b	1415	* @brief RCC LSE CSS EXTI line configuration: set falling edge trigger.
AnnaBridge	143:86740a56073b	1416	* @retval None.
AnnaBridge	143:86740a56073b	1417	*/
AnnaBridge	143:86740a56073b	1418	#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
AnnaBridge	143:86740a56073b	1419
AnnaBridge	143:86740a56073b	1420
AnnaBridge	143:86740a56073b	1421	/**
AnnaBridge	143:86740a56073b	1422	* @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
AnnaBridge	143:86740a56073b	1423	* @retval None.
AnnaBridge	143:86740a56073b	1424	*/
AnnaBridge	143:86740a56073b	1425	#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
AnnaBridge	143:86740a56073b	1426
AnnaBridge	143:86740a56073b	1427
AnnaBridge	143:86740a56073b	1428	/**
AnnaBridge	143:86740a56073b	1429	* @brief RCC LSE CSS EXTI line configuration: set rising edge trigger.
AnnaBridge	143:86740a56073b	1430	* @retval None.
AnnaBridge	143:86740a56073b	1431	*/
AnnaBridge	143:86740a56073b	1432	#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
AnnaBridge	143:86740a56073b	1433
AnnaBridge	143:86740a56073b	1434	/**
AnnaBridge	143:86740a56073b	1435	* @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
AnnaBridge	143:86740a56073b	1436	* @retval None.
AnnaBridge	143:86740a56073b	1437	*/
AnnaBridge	143:86740a56073b	1438	#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
AnnaBridge	143:86740a56073b	1439
AnnaBridge	143:86740a56073b	1440	/**
AnnaBridge	143:86740a56073b	1441	* @brief RCC LSE CSS EXTI line configuration: set rising & falling edge trigger.
AnnaBridge	143:86740a56073b	1442	* @retval None.
AnnaBridge	143:86740a56073b	1443	*/
AnnaBridge	143:86740a56073b	1444	#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
AnnaBridge	143:86740a56073b	1445	do { \
AnnaBridge	143:86740a56073b	1446	__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
AnnaBridge	143:86740a56073b	1447	__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
AnnaBridge	143:86740a56073b	1448	} while(0)
AnnaBridge	143:86740a56073b	1449
AnnaBridge	143:86740a56073b	1450	/**
AnnaBridge	143:86740a56073b	1451	* @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
AnnaBridge	143:86740a56073b	1452	* @retval None.
AnnaBridge	143:86740a56073b	1453	*/
AnnaBridge	143:86740a56073b	1454	#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
AnnaBridge	143:86740a56073b	1455	do { \
AnnaBridge	143:86740a56073b	1456	__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
AnnaBridge	143:86740a56073b	1457	__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
AnnaBridge	143:86740a56073b	1458	} while(0)
AnnaBridge	143:86740a56073b	1459
AnnaBridge	143:86740a56073b	1460	/**
AnnaBridge	143:86740a56073b	1461	* @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
AnnaBridge	143:86740a56073b	1462	* @retval EXTI RCC LSE CSS Line Status.
AnnaBridge	143:86740a56073b	1463	*/
AnnaBridge	143:86740a56073b	1464	#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (EXTI->PR & (RCC_EXTI_LINE_LSECSS))
AnnaBridge	143:86740a56073b	1465
AnnaBridge	143:86740a56073b	1466	/**
AnnaBridge	143:86740a56073b	1467	* @brief Clear the RCC LSE CSS EXTI flag.
AnnaBridge	143:86740a56073b	1468	* @retval None.
AnnaBridge	143:86740a56073b	1469	*/
AnnaBridge	143:86740a56073b	1470	#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() (EXTI->PR = (RCC_EXTI_LINE_LSECSS))
AnnaBridge	143:86740a56073b	1471
AnnaBridge	143:86740a56073b	1472	/**
AnnaBridge	143:86740a56073b	1473	* @brief Generate a Software interrupt on selected EXTI line.
AnnaBridge	143:86740a56073b	1474	* @retval None.
AnnaBridge	143:86740a56073b	1475	*/
AnnaBridge	143:86740a56073b	1476	#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS)
AnnaBridge	143:86740a56073b	1477
AnnaBridge	143:86740a56073b	1478
AnnaBridge	167:84c0a372a020	1479	#if defined(LCD)
AnnaBridge	167:84c0a372a020	1480
AnnaBridge	167:84c0a372a020	1481	/** @defgroup RCCEx_LCD_Configuration LCD Configuration
AnnaBridge	167:84c0a372a020	1482	* @brief Macros to configure clock source of LCD peripherals.
AnnaBridge	143:86740a56073b	1483	* @{
AnnaBridge	167:84c0a372a020	1484	*/
AnnaBridge	143:86740a56073b	1485
AnnaBridge	143:86740a56073b	1486	/** @brief Macro to configures LCD clock (LCDCLK).
AnnaBridge	143:86740a56073b	1487	* @note LCD and RTC use the same configuration
AnnaBridge	143:86740a56073b	1488	* @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the
AnnaBridge	167:84c0a372a020	1489	* LCD clock source.
AnnaBridge	143:86740a56073b	1490	*
AnnaBridge	143:86740a56073b	1491	* @param __LCD_CLKSOURCE__ specifies the LCD clock source.
AnnaBridge	143:86740a56073b	1492	* This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1493	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock
AnnaBridge	143:86740a56073b	1494	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock
AnnaBridge	143:86740a56073b	1495	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock
AnnaBridge	143:86740a56073b	1496	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as LCD clock
AnnaBridge	143:86740a56073b	1497	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as LCD clock
AnnaBridge	143:86740a56073b	1498	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as LCD clock
AnnaBridge	143:86740a56073b	1499	*/
AnnaBridge	143:86740a56073b	1500	#define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__)
AnnaBridge	143:86740a56073b	1501
AnnaBridge	167:84c0a372a020	1502	/** @brief Macro to get the LCD clock source.
AnnaBridge	143:86740a56073b	1503	*/
AnnaBridge	143:86740a56073b	1504	#define __HAL_RCC_GET_LCD_SOURCE() __HAL_RCC_GET_RTC_SOURCE()
AnnaBridge	143:86740a56073b	1505
AnnaBridge	167:84c0a372a020	1506	/** @brief Macro to get the LCD clock pre-scaler.
AnnaBridge	143:86740a56073b	1507	*/
AnnaBridge	143:86740a56073b	1508	#define __HAL_RCC_GET_LCD_HSE_PRESCALER() __HAL_RCC_GET_RTC_HSE_PRESCALER()
AnnaBridge	167:84c0a372a020	1509
AnnaBridge	143:86740a56073b	1510	/**
AnnaBridge	143:86740a56073b	1511	* @}
AnnaBridge	143:86740a56073b	1512	*/
AnnaBridge	167:84c0a372a020	1513
AnnaBridge	167:84c0a372a020	1514	#endif /* LCD */
AnnaBridge	167:84c0a372a020	1515
AnnaBridge	167:84c0a372a020	1516	/** @brief Macro to configure the I2C1 clock (I2C1CLK).
AnnaBridge	143:86740a56073b	1517	*
AnnaBridge	167:84c0a372a020	1518	* @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
AnnaBridge	143:86740a56073b	1519	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1520	* @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
AnnaBridge	167:84c0a372a020	1521	* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
AnnaBridge	167:84c0a372a020	1522	* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
AnnaBridge	143:86740a56073b	1523	*/
AnnaBridge	143:86740a56073b	1524	#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
AnnaBridge	143:86740a56073b	1525	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
AnnaBridge	143:86740a56073b	1526
AnnaBridge	143:86740a56073b	1527	/** @brief Macro to get the I2C1 clock source.
AnnaBridge	143:86740a56073b	1528	* @retval The clock source can be one of the following values:
AnnaBridge	167:84c0a372a020	1529	* @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
AnnaBridge	167:84c0a372a020	1530	* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
AnnaBridge	167:84c0a372a020	1531	* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
AnnaBridge	143:86740a56073b	1532	*/
AnnaBridge	143:86740a56073b	1533	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
AnnaBridge	143:86740a56073b	1534
AnnaBridge	167:84c0a372a020	1535	#if defined(RCC_CCIPR_I2C3SEL)
AnnaBridge	167:84c0a372a020	1536	/** @brief Macro to configure the I2C3 clock (I2C3CLK).
AnnaBridge	143:86740a56073b	1537	*
AnnaBridge	167:84c0a372a020	1538	* @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
AnnaBridge	143:86740a56073b	1539	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1540	* @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
AnnaBridge	167:84c0a372a020	1541	* @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
AnnaBridge	167:84c0a372a020	1542	* @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
AnnaBridge	143:86740a56073b	1543	*/
AnnaBridge	143:86740a56073b	1544	#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
AnnaBridge	143:86740a56073b	1545	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
AnnaBridge	143:86740a56073b	1546
AnnaBridge	143:86740a56073b	1547	/** @brief Macro to get the I2C3 clock source.
AnnaBridge	143:86740a56073b	1548	* @retval The clock source can be one of the following values:
AnnaBridge	167:84c0a372a020	1549	* @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
AnnaBridge	167:84c0a372a020	1550	* @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
AnnaBridge	167:84c0a372a020	1551	* @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
AnnaBridge	143:86740a56073b	1552	*/
AnnaBridge	143:86740a56073b	1553	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
AnnaBridge	143:86740a56073b	1554
AnnaBridge	167:84c0a372a020	1555	#endif /* RCC_CCIPR_I2C3SEL */
AnnaBridge	143:86740a56073b	1556
AnnaBridge	167:84c0a372a020	1557	#if defined (RCC_CCIPR_USART1SEL)
AnnaBridge	167:84c0a372a020	1558	/** @brief Macro to configure the USART1 clock (USART1CLK).
AnnaBridge	143:86740a56073b	1559	*
AnnaBridge	167:84c0a372a020	1560	* @param __USART1_CLKSOURCE__ specifies the USART1 clock source.
AnnaBridge	143:86740a56073b	1561	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1562	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge	167:84c0a372a020	1563	* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
AnnaBridge	167:84c0a372a020	1564	* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
AnnaBridge	167:84c0a372a020	1565	* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
AnnaBridge	143:86740a56073b	1566	*/
AnnaBridge	143:86740a56073b	1567	#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
AnnaBridge	143:86740a56073b	1568	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
AnnaBridge	143:86740a56073b	1569
AnnaBridge	143:86740a56073b	1570	/** @brief Macro to get the USART1 clock source.
AnnaBridge	143:86740a56073b	1571	* @retval The clock source can be one of the following values:
AnnaBridge	167:84c0a372a020	1572	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge	167:84c0a372a020	1573	* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
AnnaBridge	167:84c0a372a020	1574	* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
AnnaBridge	167:84c0a372a020	1575	* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
AnnaBridge	143:86740a56073b	1576	*/
AnnaBridge	143:86740a56073b	1577	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
AnnaBridge	167:84c0a372a020	1578	#endif /* RCC_CCIPR_USART1SEL */
AnnaBridge	143:86740a56073b	1579
AnnaBridge	167:84c0a372a020	1580	/** @brief Macro to configure the USART2 clock (USART2CLK).
AnnaBridge	143:86740a56073b	1581	*
AnnaBridge	167:84c0a372a020	1582	* @param __USART2_CLKSOURCE__ specifies the USART2 clock source.
AnnaBridge	143:86740a56073b	1583	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1584	* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
AnnaBridge	167:84c0a372a020	1585	* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
AnnaBridge	167:84c0a372a020	1586	* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
AnnaBridge	167:84c0a372a020	1587	* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
AnnaBridge	143:86740a56073b	1588	*/
AnnaBridge	143:86740a56073b	1589	#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
AnnaBridge	143:86740a56073b	1590	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
AnnaBridge	143:86740a56073b	1591
AnnaBridge	143:86740a56073b	1592	/** @brief Macro to get the USART2 clock source.
AnnaBridge	143:86740a56073b	1593	* @retval The clock source can be one of the following values:
AnnaBridge	167:84c0a372a020	1594	* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
AnnaBridge	167:84c0a372a020	1595	* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
AnnaBridge	167:84c0a372a020	1596	* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
AnnaBridge	167:84c0a372a020	1597	* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
AnnaBridge	143:86740a56073b	1598	*/
AnnaBridge	143:86740a56073b	1599	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
AnnaBridge	143:86740a56073b	1600
AnnaBridge	167:84c0a372a020	1601	/** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
AnnaBridge	143:86740a56073b	1602	*
AnnaBridge	167:84c0a372a020	1603	* @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
AnnaBridge	143:86740a56073b	1604	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1605	* @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
AnnaBridge	167:84c0a372a020	1606	* @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
AnnaBridge	167:84c0a372a020	1607	* @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
AnnaBridge	167:84c0a372a020	1608	* @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
AnnaBridge	143:86740a56073b	1609	*/
AnnaBridge	143:86740a56073b	1610	#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
AnnaBridge	143:86740a56073b	1611	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
AnnaBridge	143:86740a56073b	1612
AnnaBridge	143:86740a56073b	1613	/** @brief Macro to get the LPUART1 clock source.
AnnaBridge	143:86740a56073b	1614	* @retval The clock source can be one of the following values:
AnnaBridge	167:84c0a372a020	1615	* @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
AnnaBridge	167:84c0a372a020	1616	* @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
AnnaBridge	167:84c0a372a020	1617	* @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
AnnaBridge	167:84c0a372a020	1618	* @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
AnnaBridge	143:86740a56073b	1619	*/
AnnaBridge	143:86740a56073b	1620	#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
AnnaBridge	143:86740a56073b	1621
AnnaBridge	167:84c0a372a020	1622	/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
AnnaBridge	143:86740a56073b	1623	*
AnnaBridge	167:84c0a372a020	1624	* @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
AnnaBridge	143:86740a56073b	1625	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1626	* @arg @ref RCC_LPTIM1CLKSOURCE_PCLK PCLK selected as LPTIM1 clock
AnnaBridge	167:84c0a372a020	1627	* @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
AnnaBridge	167:84c0a372a020	1628	* @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock
AnnaBridge	167:84c0a372a020	1629	* @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
AnnaBridge	143:86740a56073b	1630	*/
AnnaBridge	143:86740a56073b	1631	#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
AnnaBridge	143:86740a56073b	1632	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
AnnaBridge	143:86740a56073b	1633
AnnaBridge	143:86740a56073b	1634	/** @brief Macro to get the LPTIM1 clock source.
AnnaBridge	143:86740a56073b	1635	* @retval The clock source can be one of the following values:
AnnaBridge	167:84c0a372a020	1636	* @arg @ref RCC_LPTIM1CLKSOURCE_PCLK PCLK selected as LPUART1 clock
AnnaBridge	167:84c0a372a020	1637	* @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock
AnnaBridge	167:84c0a372a020	1638	* @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock
AnnaBridge	167:84c0a372a020	1639	* @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock
AnnaBridge	143:86740a56073b	1640	*/
AnnaBridge	143:86740a56073b	1641	#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
AnnaBridge	143:86740a56073b	1642
AnnaBridge	167:84c0a372a020	1643	#if defined(USB)
AnnaBridge	143:86740a56073b	1644	/** @brief Macro to configure the USB clock (USBCLK).
AnnaBridge	167:84c0a372a020	1645	* @param __USB_CLKSOURCE__ specifies the USB clock source.
AnnaBridge	143:86740a56073b	1646	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1647	* @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock
AnnaBridge	167:84c0a372a020	1648	* @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock
AnnaBridge	143:86740a56073b	1649	*/
AnnaBridge	167:84c0a372a020	1650	#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
AnnaBridge	167:84c0a372a020	1651	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__USB_CLKSOURCE__))
AnnaBridge	143:86740a56073b	1652
AnnaBridge	143:86740a56073b	1653	/** @brief Macro to get the USB clock source.
AnnaBridge	143:86740a56073b	1654	* @retval The clock source can be one of the following values:
AnnaBridge	167:84c0a372a020	1655	* @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock
AnnaBridge	167:84c0a372a020	1656	* @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock
AnnaBridge	143:86740a56073b	1657	*/
AnnaBridge	143:86740a56073b	1658	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
AnnaBridge	167:84c0a372a020	1659	#endif /* USB */
AnnaBridge	143:86740a56073b	1660
AnnaBridge	167:84c0a372a020	1661	#if defined(RNG)
AnnaBridge	143:86740a56073b	1662	/** @brief Macro to configure the RNG clock (RNGCLK).
AnnaBridge	167:84c0a372a020	1663	* @param __RNG_CLKSOURCE__ specifies the USB clock source.
AnnaBridge	143:86740a56073b	1664	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1665	* @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock
AnnaBridge	167:84c0a372a020	1666	* @arg @ref RCC_RNGCLKSOURCE_PLLCLK PLL Clock selected as RNG clock
AnnaBridge	143:86740a56073b	1667	*/
AnnaBridge	167:84c0a372a020	1668	#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
AnnaBridge	167:84c0a372a020	1669	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__RNG_CLKSOURCE__))
AnnaBridge	143:86740a56073b	1670
AnnaBridge	143:86740a56073b	1671	/** @brief Macro to get the RNG clock source.
AnnaBridge	143:86740a56073b	1672	* @retval The clock source can be one of the following values:
AnnaBridge	167:84c0a372a020	1673	* @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock
AnnaBridge	167:84c0a372a020	1674	* @arg @ref RCC_RNGCLKSOURCE_PLLCLK PLL Clock selected as RNG clock
AnnaBridge	143:86740a56073b	1675	*/
AnnaBridge	143:86740a56073b	1676	#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
AnnaBridge	167:84c0a372a020	1677	#endif /* RNG */
AnnaBridge	143:86740a56073b	1678
AnnaBridge	167:84c0a372a020	1679	#if defined(RCC_CCIPR_HSI48SEL)
AnnaBridge	167:84c0a372a020	1680	/** @brief Macro to select the HSI48M clock source
AnnaBridge	143:86740a56073b	1681	* @note This macro can be replaced by either __HAL_RCC_RNG_CONFIG or
AnnaBridge	143:86740a56073b	1682	* __HAL_RCC_USB_CONFIG to configure respectively RNG or UBS clock sources.
AnnaBridge	143:86740a56073b	1683	*
AnnaBridge	167:84c0a372a020	1684	* @param __HSI48M_CLKSOURCE__ specifies the HSI48M clock source dedicated for
AnnaBridge	143:86740a56073b	1685	* USB an RNG peripherals.
AnnaBridge	143:86740a56073b	1686	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1687	* @arg @ref RCC_HSI48M_PLL A dedicated 48MHZ PLL output.
AnnaBridge	167:84c0a372a020	1688	* @arg @ref RCC_HSI48M_HSI48 48MHZ issued from internal HSI48 oscillator.
AnnaBridge	143:86740a56073b	1689	*/
AnnaBridge	167:84c0a372a020	1690	#define __HAL_RCC_HSI48M_CONFIG(__HSI48M_CLKSOURCE__) \
AnnaBridge	167:84c0a372a020	1691	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__HSI48M_CLKSOURCE__))
AnnaBridge	143:86740a56073b	1692
AnnaBridge	167:84c0a372a020	1693	/** @brief Macro to get the HSI48M clock source.
AnnaBridge	143:86740a56073b	1694	* @note This macro can be replaced by either __HAL_RCC_GET_RNG_SOURCE or
AnnaBridge	143:86740a56073b	1695	* __HAL_RCC_GET_USB_SOURCE to get respectively RNG or UBS clock sources.
AnnaBridge	143:86740a56073b	1696	* @retval The clock source can be one of the following values:
AnnaBridge	167:84c0a372a020	1697	* @arg @ref RCC_HSI48M_PLL A dedicated 48MHZ PLL output.
AnnaBridge	167:84c0a372a020	1698	* @arg @ref RCC_HSI48M_HSI48 48MHZ issued from internal HSI48 oscillator.
AnnaBridge	143:86740a56073b	1699	*/
AnnaBridge	143:86740a56073b	1700	#define __HAL_RCC_GET_HSI48M_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
AnnaBridge	167:84c0a372a020	1701	#endif /* RCC_CCIPR_HSI48SEL */
AnnaBridge	143:86740a56073b	1702
AnnaBridge	143:86740a56073b	1703	/**
AnnaBridge	167:84c0a372a020	1704	* @brief Macro to enable the force of the Internal High Speed oscillator (HSI)
AnnaBridge	143:86740a56073b	1705	* in STOP mode to be quickly available as kernel clock for USART and I2C.
AnnaBridge	143:86740a56073b	1706	* @note The Enable of this function has not effect on the HSION bit.
AnnaBridge	167:84c0a372a020	1707	*/
AnnaBridge	167:84c0a372a020	1708	#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
AnnaBridge	167:84c0a372a020	1709
AnnaBridge	167:84c0a372a020	1710	/**
AnnaBridge	167:84c0a372a020	1711	* @brief Macro to disable the force of the Internal High Speed oscillator (HSI)
AnnaBridge	167:84c0a372a020	1712	* in STOP mode to be quickly available as kernel clock for USART and I2C.
AnnaBridge	143:86740a56073b	1713	* @retval None
AnnaBridge	143:86740a56073b	1714	*/
AnnaBridge	143:86740a56073b	1715	#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
AnnaBridge	143:86740a56073b	1716
AnnaBridge	143:86740a56073b	1717	/**
AnnaBridge	143:86740a56073b	1718	* @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
AnnaBridge	167:84c0a372a020	1719	* @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability.
AnnaBridge	143:86740a56073b	1720	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1721	* @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
AnnaBridge	167:84c0a372a020	1722	* @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
AnnaBridge	167:84c0a372a020	1723	* @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
AnnaBridge	167:84c0a372a020	1724	* @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
AnnaBridge	143:86740a56073b	1725	* @retval None
AnnaBridge	143:86740a56073b	1726	*/
AnnaBridge	167:84c0a372a020	1727	#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->CSR,\
AnnaBridge	167:84c0a372a020	1728	RCC_CSR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
AnnaBridge	143:86740a56073b	1729
AnnaBridge	143:86740a56073b	1730	/**
AnnaBridge	143:86740a56073b	1731	* @brief Macro to configures the wake up from stop clock.
AnnaBridge	167:84c0a372a020	1732	* @param __RCC_STOPWUCLK__ specifies the clock source used after wake up from stop
AnnaBridge	143:86740a56073b	1733	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1734	* @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source
AnnaBridge	167:84c0a372a020	1735	* @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source
AnnaBridge	143:86740a56073b	1736	* @retval None
AnnaBridge	143:86740a56073b	1737	*/
AnnaBridge	143:86740a56073b	1738	#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) (MODIFY_REG(RCC->CFGR,\
AnnaBridge	143:86740a56073b	1739	RCC_CFGR_STOPWUCK, (uint32_t)(__RCC_STOPWUCLK__) ))
AnnaBridge	167:84c0a372a020	1740
AnnaBridge	167:84c0a372a020	1741	#if defined(CRS)
AnnaBridge	143:86740a56073b	1742	/**
AnnaBridge	143:86740a56073b	1743	* @brief Enables the specified CRS interrupts.
AnnaBridge	167:84c0a372a020	1744	* @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
AnnaBridge	143:86740a56073b	1745	* This parameter can be any combination of the following values:
AnnaBridge	167:84c0a372a020	1746	* @arg @ref RCC_CRS_IT_SYNCOK
AnnaBridge	167:84c0a372a020	1747	* @arg @ref RCC_CRS_IT_SYNCWARN
AnnaBridge	167:84c0a372a020	1748	* @arg @ref RCC_CRS_IT_ERR
AnnaBridge	167:84c0a372a020	1749	* @arg @ref RCC_CRS_IT_ESYNC
AnnaBridge	143:86740a56073b	1750	* @retval None
AnnaBridge	143:86740a56073b	1751	*/
AnnaBridge	143:86740a56073b	1752	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
AnnaBridge	143:86740a56073b	1753
AnnaBridge	143:86740a56073b	1754	/**
AnnaBridge	143:86740a56073b	1755	* @brief Disables the specified CRS interrupts.
AnnaBridge	167:84c0a372a020	1756	* @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
AnnaBridge	143:86740a56073b	1757	* This parameter can be any combination of the following values:
AnnaBridge	167:84c0a372a020	1758	* @arg @ref RCC_CRS_IT_SYNCOK
AnnaBridge	167:84c0a372a020	1759	* @arg @ref RCC_CRS_IT_SYNCWARN
AnnaBridge	167:84c0a372a020	1760	* @arg @ref RCC_CRS_IT_ERR
AnnaBridge	167:84c0a372a020	1761	* @arg @ref RCC_CRS_IT_ESYNC
AnnaBridge	143:86740a56073b	1762	* @retval None
AnnaBridge	143:86740a56073b	1763	*/
AnnaBridge	143:86740a56073b	1764	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR,(__INTERRUPT__))
AnnaBridge	143:86740a56073b	1765
AnnaBridge	143:86740a56073b	1766	/** @brief Check the CRS interrupt has occurred or not.
AnnaBridge	167:84c0a372a020	1767	* @param __INTERRUPT__ specifies the CRS interrupt source to check.
AnnaBridge	143:86740a56073b	1768	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1769	* @arg @ref RCC_CRS_IT_SYNCOK
AnnaBridge	167:84c0a372a020	1770	* @arg @ref RCC_CRS_IT_SYNCWARN
AnnaBridge	167:84c0a372a020	1771	* @arg @ref RCC_CRS_IT_ERR
AnnaBridge	167:84c0a372a020	1772	* @arg @ref RCC_CRS_IT_ESYNC
AnnaBridge	143:86740a56073b	1773	* @retval The new state of __INTERRUPT__ (SET or RESET).
AnnaBridge	143:86740a56073b	1774	*/
AnnaBridge	143:86740a56073b	1775	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
AnnaBridge	143:86740a56073b	1776
AnnaBridge	143:86740a56073b	1777	/** @brief Clear the CRS interrupt pending bits
AnnaBridge	143:86740a56073b	1778	* bits to clear the selected interrupt pending bits.
AnnaBridge	167:84c0a372a020	1779	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge	143:86740a56073b	1780	* This parameter can be any combination of the following values:
AnnaBridge	167:84c0a372a020	1781	* @arg @ref RCC_CRS_IT_SYNCOK
AnnaBridge	167:84c0a372a020	1782	* @arg @ref RCC_CRS_IT_SYNCWARN
AnnaBridge	167:84c0a372a020	1783	* @arg @ref RCC_CRS_IT_ERR
AnnaBridge	167:84c0a372a020	1784	* @arg @ref RCC_CRS_IT_ESYNC
AnnaBridge	167:84c0a372a020	1785	* @arg @ref RCC_CRS_IT_TRIMOVF
AnnaBridge	167:84c0a372a020	1786	* @arg @ref RCC_CRS_IT_SYNCERR
AnnaBridge	167:84c0a372a020	1787	* @arg @ref RCC_CRS_IT_SYNCMISS
AnnaBridge	143:86740a56073b	1788	*/
AnnaBridge	167:84c0a372a020	1789	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
AnnaBridge	167:84c0a372a020	1790	if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
AnnaBridge	167:84c0a372a020	1791	{ \
AnnaBridge	167:84c0a372a020	1792	WRITE_REG(CRS->ICR, CRS_ICR_ERRC \| ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
AnnaBridge	167:84c0a372a020	1793	} \
AnnaBridge	167:84c0a372a020	1794	else \
AnnaBridge	167:84c0a372a020	1795	{ \
AnnaBridge	167:84c0a372a020	1796	WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
AnnaBridge	167:84c0a372a020	1797	} \
AnnaBridge	167:84c0a372a020	1798	} while(0)
AnnaBridge	143:86740a56073b	1799
AnnaBridge	143:86740a56073b	1800	/**
AnnaBridge	143:86740a56073b	1801	* @brief Checks whether the specified CRS flag is set or not.
AnnaBridge	167:84c0a372a020	1802	* @param __FLAG__ specifies the flag to check.
AnnaBridge	143:86740a56073b	1803	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1804	* @arg @ref RCC_CRS_FLAG_SYNCOK
AnnaBridge	167:84c0a372a020	1805	* @arg @ref RCC_CRS_FLAG_SYNCWARN
AnnaBridge	167:84c0a372a020	1806	* @arg @ref RCC_CRS_FLAG_ERR
AnnaBridge	167:84c0a372a020	1807	* @arg @ref RCC_CRS_FLAG_ESYNC
AnnaBridge	167:84c0a372a020	1808	* @arg @ref RCC_CRS_FLAG_TRIMOVF
AnnaBridge	167:84c0a372a020	1809	* @arg @ref RCC_CRS_FLAG_SYNCERR
AnnaBridge	167:84c0a372a020	1810	* @arg @ref RCC_CRS_FLAG_SYNCMISS
AnnaBridge	167:84c0a372a020	1811	* @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge	143:86740a56073b	1812	*/
AnnaBridge	143:86740a56073b	1813	#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) ((CRS->ISR & (__FLAG__)) == (__FLAG__))
AnnaBridge	143:86740a56073b	1814
AnnaBridge	143:86740a56073b	1815	/**
AnnaBridge	143:86740a56073b	1816	* @brief Clears the CRS specified FLAG.
AnnaBridge	167:84c0a372a020	1817	* @param __FLAG__ specifies the flag to clear.
AnnaBridge	143:86740a56073b	1818	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1819	* @arg @ref RCC_CRS_FLAG_SYNCOK
AnnaBridge	167:84c0a372a020	1820	* @arg @ref RCC_CRS_FLAG_SYNCWARN
AnnaBridge	167:84c0a372a020	1821	* @arg @ref RCC_CRS_FLAG_ERR
AnnaBridge	167:84c0a372a020	1822	* @arg @ref RCC_CRS_FLAG_ESYNC
AnnaBridge	167:84c0a372a020	1823	* @arg @ref RCC_CRS_FLAG_TRIMOVF
AnnaBridge	167:84c0a372a020	1824	* @arg @ref RCC_CRS_FLAG_SYNCERR
AnnaBridge	167:84c0a372a020	1825	* @arg @ref RCC_CRS_FLAG_SYNCMISS
AnnaBridge	143:86740a56073b	1826	* @retval None
AnnaBridge	143:86740a56073b	1827	*/
AnnaBridge	167:84c0a372a020	1828	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
AnnaBridge	167:84c0a372a020	1829	if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \
AnnaBridge	167:84c0a372a020	1830	{ \
AnnaBridge	167:84c0a372a020	1831	WRITE_REG(CRS->ICR, CRS_ICR_ERRC \| ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
AnnaBridge	167:84c0a372a020	1832	} \
AnnaBridge	167:84c0a372a020	1833	else \
AnnaBridge	167:84c0a372a020	1834	{ \
AnnaBridge	167:84c0a372a020	1835	WRITE_REG(CRS->ICR, (__FLAG__)); \
AnnaBridge	167:84c0a372a020	1836	} \
AnnaBridge	167:84c0a372a020	1837	} while(0)
AnnaBridge	143:86740a56073b	1838
AnnaBridge	143:86740a56073b	1839	/**
AnnaBridge	143:86740a56073b	1840	* @brief Enables the oscillator clock for frequency error counter.
AnnaBridge	143:86740a56073b	1841	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
AnnaBridge	143:86740a56073b	1842	* @retval None
AnnaBridge	143:86740a56073b	1843	*/
AnnaBridge	143:86740a56073b	1844	#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
AnnaBridge	143:86740a56073b	1845
AnnaBridge	143:86740a56073b	1846	/**
AnnaBridge	143:86740a56073b	1847	* @brief Disables the oscillator clock for frequency error counter.
AnnaBridge	143:86740a56073b	1848	* @retval None
AnnaBridge	143:86740a56073b	1849	*/
AnnaBridge	167:84c0a372a020	1850	#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
AnnaBridge	143:86740a56073b	1851
AnnaBridge	143:86740a56073b	1852	/**
AnnaBridge	143:86740a56073b	1853	* @brief Enables the automatic hardware adjustment of TRIM bits.
AnnaBridge	143:86740a56073b	1854	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
AnnaBridge	143:86740a56073b	1855	* @retval None
AnnaBridge	143:86740a56073b	1856	*/
AnnaBridge	143:86740a56073b	1857	#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
AnnaBridge	143:86740a56073b	1858
AnnaBridge	143:86740a56073b	1859	/**
AnnaBridge	143:86740a56073b	1860	* @brief Enables or disables the automatic hardware adjustment of TRIM bits.
AnnaBridge	143:86740a56073b	1861	* @retval None
AnnaBridge	143:86740a56073b	1862	*/
AnnaBridge	167:84c0a372a020	1863	#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
AnnaBridge	143:86740a56073b	1864
AnnaBridge	143:86740a56073b	1865	/**
AnnaBridge	143:86740a56073b	1866	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
AnnaBridge	143:86740a56073b	1867	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
AnnaBridge	143:86740a56073b	1868	* of the synchronization source after prescaling. It is then decreased by one in order to
AnnaBridge	143:86740a56073b	1869	* reach the expected synchronization on the zero value. The formula is the following:
AnnaBridge	143:86740a56073b	1870	* RELOAD = (fTARGET / fSYNC) -1
AnnaBridge	143:86740a56073b	1871	* @param __FTARGET__ Target frequency (value in Hz)
AnnaBridge	167:84c0a372a020	1872	* @param __FSYNC__ Synchronization signal frequency (value in Hz)
AnnaBridge	143:86740a56073b	1873	* @retval None
AnnaBridge	143:86740a56073b	1874	*/
AnnaBridge	143:86740a56073b	1875	#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1)
AnnaBridge	143:86740a56073b	1876
AnnaBridge	167:84c0a372a020	1877	#endif /* CRS */
AnnaBridge	167:84c0a372a020	1878
AnnaBridge	143:86740a56073b	1879
AnnaBridge	167:84c0a372a020	1880	#if defined(RCC_CR_HSIOUTEN)
AnnaBridge	167:84c0a372a020	1881	/** @brief Enable he HSI OUT .
AnnaBridge	143:86740a56073b	1882	* @note After reset, the HSI output is not available
AnnaBridge	143:86740a56073b	1883	*/
AnnaBridge	143:86740a56073b	1884
AnnaBridge	143:86740a56073b	1885	#define __HAL_RCC_HSI_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIOUTEN)
AnnaBridge	167:84c0a372a020	1886
AnnaBridge	167:84c0a372a020	1887	/** @brief Disable the HSI OUT .
AnnaBridge	167:84c0a372a020	1888	* @note After reset, the HSI output is not available
AnnaBridge	167:84c0a372a020	1889	*/
AnnaBridge	167:84c0a372a020	1890
AnnaBridge	143:86740a56073b	1891	#define __HAL_RCC_HSI_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN)
AnnaBridge	143:86740a56073b	1892
AnnaBridge	167:84c0a372a020	1893	#endif /* RCC_CR_HSIOUTEN */
AnnaBridge	143:86740a56073b	1894
AnnaBridge	167:84c0a372a020	1895	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)\
AnnaBridge	167:84c0a372a020	1896	\|\| defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx)
AnnaBridge	143:86740a56073b	1897
AnnaBridge	143:86740a56073b	1898	/**
AnnaBridge	167:84c0a372a020	1899	* @brief Enable the Internal High Speed oscillator for USB (HSI48).
AnnaBridge	143:86740a56073b	1900	* @note After enabling the HSI48, the application software should wait on
AnnaBridge	143:86740a56073b	1901	* HSI48RDY flag to be set indicating that HSI48 clock is stable and can
AnnaBridge	143:86740a56073b	1902	* be used to clock the USB.
AnnaBridge	143:86740a56073b	1903	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	143:86740a56073b	1904	*/
AnnaBridge	167:84c0a372a020	1905	#define __HAL_RCC_HSI48_ENABLE() do { SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
AnnaBridge	167:84c0a372a020	1906	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
AnnaBridge	167:84c0a372a020	1907	SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48); \
AnnaBridge	167:84c0a372a020	1908	} while (0)
AnnaBridge	167:84c0a372a020	1909	/**
AnnaBridge	167:84c0a372a020	1910	* @brief Disable the Internal High Speed oscillator for USB (HSI48).
AnnaBridge	167:84c0a372a020	1911	*/
AnnaBridge	143:86740a56073b	1912	#define __HAL_RCC_HSI48_DISABLE() do { CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
AnnaBridge	167:84c0a372a020	1913	CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48); \
AnnaBridge	167:84c0a372a020	1914	} while (0)
AnnaBridge	167:84c0a372a020	1915
AnnaBridge	167:84c0a372a020	1916	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
AnnaBridge	167:84c0a372a020	1917	* @retval The clock source can be one of the following values:
AnnaBridge	167:84c0a372a020	1918	* @arg @ref RCC_HSI48_ON HSI48 enabled
AnnaBridge	167:84c0a372a020	1919	* @arg @ref RCC_HSI48_OFF HSI48 disabled
AnnaBridge	167:84c0a372a020	1920	*/
AnnaBridge	167:84c0a372a020	1921	#define __HAL_RCC_GET_HSI48_STATE() \
AnnaBridge	167:84c0a372a020	1922	(((uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
AnnaBridge	167:84c0a372a020	1923
AnnaBridge	143:86740a56073b	1924	/** @brief Enable or disable the HSI48M DIV6 OUT .
AnnaBridge	143:86740a56073b	1925	* @note After reset, the HSI48Mhz (divided by 6) output is not available
AnnaBridge	143:86740a56073b	1926	*/
AnnaBridge	143:86740a56073b	1927
AnnaBridge	143:86740a56073b	1928	#define __HAL_RCC_HSI48M_DIV6_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
AnnaBridge	143:86740a56073b	1929	#define __HAL_RCC_HSI48M_DIV6_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
AnnaBridge	143:86740a56073b	1930
AnnaBridge	143:86740a56073b	1931	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
AnnaBridge	143:86740a56073b	1932	/* STM32L072xx \|\| STM32L082xx \|\| */
AnnaBridge	143:86740a56073b	1933	/* STM32L073xx \|\| STM32L083xx */
AnnaBridge	143:86740a56073b	1934
AnnaBridge	167:84c0a372a020	1935
AnnaBridge	143:86740a56073b	1936	/**
AnnaBridge	143:86740a56073b	1937	* @}
AnnaBridge	143:86740a56073b	1938	*/
AnnaBridge	143:86740a56073b	1939
AnnaBridge	167:84c0a372a020	1940	/* Exported functions --------------------------------------------------------*/
AnnaBridge	167:84c0a372a020	1941	/** @addtogroup RCCEx_Exported_Functions
AnnaBridge	143:86740a56073b	1942	* @{
AnnaBridge	143:86740a56073b	1943	*/
AnnaBridge	143:86740a56073b	1944
AnnaBridge	167:84c0a372a020	1945	/** @addtogroup RCCEx_Exported_Functions_Group1
AnnaBridge	143:86740a56073b	1946	* @{
AnnaBridge	143:86740a56073b	1947	*/
AnnaBridge	143:86740a56073b	1948
AnnaBridge	167:84c0a372a020	1949	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge	167:84c0a372a020	1950	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge	167:84c0a372a020	1951	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
AnnaBridge	143:86740a56073b	1952
AnnaBridge	143:86740a56073b	1953
AnnaBridge	167:84c0a372a020	1954	void HAL_RCCEx_EnableLSECSS(void);
AnnaBridge	167:84c0a372a020	1955	void HAL_RCCEx_DisableLSECSS(void);
AnnaBridge	167:84c0a372a020	1956	void HAL_RCCEx_EnableLSECSS_IT(void);
AnnaBridge	167:84c0a372a020	1957	void HAL_RCCEx_LSECSS_IRQHandler(void);
AnnaBridge	167:84c0a372a020	1958	void HAL_RCCEx_LSECSS_Callback(void);
AnnaBridge	143:86740a56073b	1959
AnnaBridge	143:86740a56073b	1960
AnnaBridge	167:84c0a372a020	1961	#if defined(SYSCFG_CFGR3_ENREF_HSI48)
AnnaBridge	167:84c0a372a020	1962	void HAL_RCCEx_EnableHSI48_VREFINT(void);
AnnaBridge	167:84c0a372a020	1963	void HAL_RCCEx_DisableHSI48_VREFINT(void);
AnnaBridge	167:84c0a372a020	1964	#endif /* SYSCFG_CFGR3_ENREF_HSI48 */
AnnaBridge	143:86740a56073b	1965
AnnaBridge	143:86740a56073b	1966	/**
AnnaBridge	143:86740a56073b	1967	* @}
AnnaBridge	143:86740a56073b	1968	*/
AnnaBridge	167:84c0a372a020	1969
AnnaBridge	167:84c0a372a020	1970	#if defined(CRS)
AnnaBridge	167:84c0a372a020	1971
AnnaBridge	167:84c0a372a020	1972	/** @addtogroup RCCEx_Exported_Functions_Group3
AnnaBridge	167:84c0a372a020	1973	* @{
AnnaBridge	167:84c0a372a020	1974	*/
AnnaBridge	167:84c0a372a020	1975
AnnaBridge	167:84c0a372a020	1976	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
AnnaBridge	167:84c0a372a020	1977	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
AnnaBridge	167:84c0a372a020	1978	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
AnnaBridge	167:84c0a372a020	1979	uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
AnnaBridge	167:84c0a372a020	1980	void HAL_RCCEx_CRS_IRQHandler(void);
AnnaBridge	167:84c0a372a020	1981	void HAL_RCCEx_CRS_SyncOkCallback(void);
AnnaBridge	167:84c0a372a020	1982	void HAL_RCCEx_CRS_SyncWarnCallback(void);
AnnaBridge	167:84c0a372a020	1983	void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
AnnaBridge	167:84c0a372a020	1984	void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
AnnaBridge	167:84c0a372a020	1985
AnnaBridge	167:84c0a372a020	1986	/**
AnnaBridge	167:84c0a372a020	1987	* @}
AnnaBridge	167:84c0a372a020	1988	*/
AnnaBridge	167:84c0a372a020	1989
AnnaBridge	167:84c0a372a020	1990	#endif /* CRS */
AnnaBridge	167:84c0a372a020	1991
AnnaBridge	143:86740a56073b	1992	/**
AnnaBridge	143:86740a56073b	1993	* @}
AnnaBridge	143:86740a56073b	1994	*/
AnnaBridge	143:86740a56073b	1995
AnnaBridge	143:86740a56073b	1996	/**
AnnaBridge	143:86740a56073b	1997	* @}
AnnaBridge	167:84c0a372a020	1998	*/
AnnaBridge	167:84c0a372a020	1999
AnnaBridge	143:86740a56073b	2000	/**
AnnaBridge	143:86740a56073b	2001	* @}
AnnaBridge	143:86740a56073b	2002	*/
AnnaBridge	143:86740a56073b	2003
AnnaBridge	143:86740a56073b	2004	#ifdef __cplusplus
AnnaBridge	143:86740a56073b	2005	}
AnnaBridge	143:86740a56073b	2006	#endif
AnnaBridge	143:86740a56073b	2007
AnnaBridge	143:86740a56073b	2008	#endif /* __STM32L0xx_HAL_RCC_EX_H */
AnnaBridge	143:86740a56073b	2009
AnnaBridge	143:86740a56073b	2010	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
AnnaBridge	143:86740a56073b	2011