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TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc_ex.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Child:
167:84c0a372a020
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 143:86740a56073b 1 /**
AnnaBridge 143:86740a56073b 2 ******************************************************************************
AnnaBridge 143:86740a56073b 3 * @file stm32l0xx_hal_rcc_ex.h
AnnaBridge 143:86740a56073b 4 * @author MCD Application Team
AnnaBridge 143:86740a56073b 5 * @version V1.7.0
AnnaBridge 143:86740a56073b 6 * @date 31-May-2016
AnnaBridge 143:86740a56073b 7 * @brief Header file of RCC HAL Extension module.
AnnaBridge 143:86740a56073b 8 ******************************************************************************
AnnaBridge 143:86740a56073b 9 * @attention
AnnaBridge 143:86740a56073b 10 *
AnnaBridge 143:86740a56073b 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 143:86740a56073b 12 *
AnnaBridge 143:86740a56073b 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 143:86740a56073b 14 * are permitted provided that the following conditions are met:
AnnaBridge 143:86740a56073b 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 143:86740a56073b 16 * this list of conditions and the following disclaimer.
AnnaBridge 143:86740a56073b 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 143:86740a56073b 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 143:86740a56073b 19 * and/or other materials provided with the distribution.
AnnaBridge 143:86740a56073b 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 143:86740a56073b 21 * may be used to endorse or promote products derived from this software
AnnaBridge 143:86740a56073b 22 * without specific prior written permission.
AnnaBridge 143:86740a56073b 23 *
AnnaBridge 143:86740a56073b 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 143:86740a56073b 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 143:86740a56073b 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 143:86740a56073b 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 143:86740a56073b 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 143:86740a56073b 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 143:86740a56073b 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 143:86740a56073b 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 143:86740a56073b 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 143:86740a56073b 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 143:86740a56073b 34 *
AnnaBridge 143:86740a56073b 35 ******************************************************************************
AnnaBridge 143:86740a56073b 36 */
AnnaBridge 143:86740a56073b 37
AnnaBridge 143:86740a56073b 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 143:86740a56073b 39 #ifndef __STM32L0xx_HAL_RCC_EX_H
AnnaBridge 143:86740a56073b 40 #define __STM32L0xx_HAL_RCC_EX_H
AnnaBridge 143:86740a56073b 41
AnnaBridge 143:86740a56073b 42 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 43 extern "C" {
AnnaBridge 143:86740a56073b 44 #endif
AnnaBridge 143:86740a56073b 45
AnnaBridge 143:86740a56073b 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 47 #include "stm32l0xx_hal_def.h"
AnnaBridge 143:86740a56073b 48
AnnaBridge 143:86740a56073b 49 /** @addtogroup STM32L0xx_HAL_Driver
AnnaBridge 143:86740a56073b 50 * @{
AnnaBridge 143:86740a56073b 51 */
AnnaBridge 143:86740a56073b 52
AnnaBridge 143:86740a56073b 53 /** @defgroup RCCEx RCCEx
AnnaBridge 143:86740a56073b 54 * @{
AnnaBridge 143:86740a56073b 55 */
AnnaBridge 143:86740a56073b 56
AnnaBridge 143:86740a56073b 57 /* Exported types ------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 58 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
AnnaBridge 143:86740a56073b 59 * @{
AnnaBridge 143:86740a56073b 60 */
AnnaBridge 143:86740a56073b 61
AnnaBridge 143:86740a56073b 62 /**
AnnaBridge 143:86740a56073b 63 * @brief RCC extended clocks structure definition
AnnaBridge 143:86740a56073b 64 */
AnnaBridge 143:86740a56073b 65 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge 143:86740a56073b 66 typedef struct
AnnaBridge 143:86740a56073b 67 {
AnnaBridge 143:86740a56073b 68 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge 143:86740a56073b 69 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge 143:86740a56073b 70 uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge 143:86740a56073b 71 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge 143:86740a56073b 72
AnnaBridge 143:86740a56073b 73 uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge 143:86740a56073b 74 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
AnnaBridge 143:86740a56073b 75
AnnaBridge 143:86740a56073b 76 uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source
AnnaBridge 143:86740a56073b 77 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
AnnaBridge 143:86740a56073b 78
AnnaBridge 143:86740a56073b 79 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge 143:86740a56073b 80 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
AnnaBridge 143:86740a56073b 81 #if defined (STM32L072xx) || defined(STM32L073xx) || defined(STM32L082xx) || defined(STM32L083xx)
AnnaBridge 143:86740a56073b 82 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
AnnaBridge 143:86740a56073b 83 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
AnnaBridge 143:86740a56073b 84 #endif
AnnaBridge 143:86740a56073b 85
AnnaBridge 143:86740a56073b 86 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge 143:86740a56073b 87 This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge 143:86740a56073b 88 #if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
AnnaBridge 143:86740a56073b 89 uint32_t LCDClockSelection; /*!< specifies the LCD clock source.
AnnaBridge 143:86740a56073b 90 This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge 143:86740a56073b 91 #endif
AnnaBridge 143:86740a56073b 92
AnnaBridge 143:86740a56073b 93 uint32_t UsbClockSelection; /*!< Specifies USB and RNG Clock Selection
AnnaBridge 143:86740a56073b 94 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
AnnaBridge 143:86740a56073b 95
AnnaBridge 143:86740a56073b 96 uint32_t LptimClockSelection; /*!< LPTIM1 clock source
AnnaBridge 143:86740a56073b 97 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
AnnaBridge 143:86740a56073b 98
AnnaBridge 143:86740a56073b 99 }RCC_PeriphCLKInitTypeDef;
AnnaBridge 143:86740a56073b 100
AnnaBridge 143:86740a56073b 101
AnnaBridge 143:86740a56073b 102 #else /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
AnnaBridge 143:86740a56073b 103
AnnaBridge 143:86740a56073b 104 typedef struct
AnnaBridge 143:86740a56073b 105 {
AnnaBridge 143:86740a56073b 106 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge 143:86740a56073b 107 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge 143:86740a56073b 108 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx)
AnnaBridge 143:86740a56073b 109 uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge 143:86740a56073b 110 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge 143:86740a56073b 111 #endif
AnnaBridge 143:86740a56073b 112 uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge 143:86740a56073b 113 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
AnnaBridge 143:86740a56073b 114
AnnaBridge 143:86740a56073b 115 uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source
AnnaBridge 143:86740a56073b 116 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
AnnaBridge 143:86740a56073b 117
AnnaBridge 143:86740a56073b 118 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge 143:86740a56073b 119 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
AnnaBridge 143:86740a56073b 120
AnnaBridge 143:86740a56073b 121 #if defined (STM32L071xx) || defined(STM32L081xx)
AnnaBridge 143:86740a56073b 122 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
AnnaBridge 143:86740a56073b 123 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
AnnaBridge 143:86740a56073b 124 #endif
AnnaBridge 143:86740a56073b 125
AnnaBridge 143:86740a56073b 126 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge 143:86740a56073b 127 This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge 143:86740a56073b 128
AnnaBridge 143:86740a56073b 129 uint32_t LptimClockSelection; /*!< LPTIM1 clock source
AnnaBridge 143:86740a56073b 130 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
AnnaBridge 143:86740a56073b 131
AnnaBridge 143:86740a56073b 132 }RCC_PeriphCLKInitTypeDef;
AnnaBridge 143:86740a56073b 133
AnnaBridge 143:86740a56073b 134 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
AnnaBridge 143:86740a56073b 135
AnnaBridge 143:86740a56073b 136 /**
AnnaBridge 143:86740a56073b 137 * @}
AnnaBridge 143:86740a56073b 138 */
AnnaBridge 143:86740a56073b 139
AnnaBridge 143:86740a56073b 140 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
AnnaBridge 143:86740a56073b 141 * @{
AnnaBridge 143:86740a56073b 142 */
AnnaBridge 143:86740a56073b 143 /**
AnnaBridge 143:86740a56073b 144 * @}
AnnaBridge 143:86740a56073b 145 */
AnnaBridge 143:86740a56073b 146
AnnaBridge 143:86740a56073b 147 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge 143:86740a56073b 148
AnnaBridge 143:86740a56073b 149 /** @addtogroup RCCEx_Exported_Constants
AnnaBridge 143:86740a56073b 150 * @{
AnnaBridge 143:86740a56073b 151 */
AnnaBridge 143:86740a56073b 152 /**
AnnaBridge 143:86740a56073b 153 * @brief RCC CRS Status definition
AnnaBridge 143:86740a56073b 154 */
AnnaBridge 143:86740a56073b 155
AnnaBridge 143:86740a56073b 156 #define RCC_CRS_NONE ((uint32_t) 0x00000000U)
AnnaBridge 143:86740a56073b 157 #define RCC_CRS_TIMEOUT ((uint32_t) 0x00000001U)
AnnaBridge 143:86740a56073b 158 #define RCC_CRS_SYNCOK ((uint32_t) 0x00000002U)
AnnaBridge 143:86740a56073b 159 #define RCC_CRS_SYNCWARN ((uint32_t) 0x00000004U)
AnnaBridge 143:86740a56073b 160 #define RCC_CRS_SYNCERR ((uint32_t) 0x00000008U)
AnnaBridge 143:86740a56073b 161 #define RCC_CRS_SYNCMISS ((uint32_t) 0x00000010U)
AnnaBridge 143:86740a56073b 162 #define RCC_CRS_TRIMOVF ((uint32_t) 0x00000020U)
AnnaBridge 143:86740a56073b 163
AnnaBridge 143:86740a56073b 164 /**
AnnaBridge 143:86740a56073b 165 * @}
AnnaBridge 143:86740a56073b 166 */
AnnaBridge 143:86740a56073b 167
AnnaBridge 143:86740a56073b 168 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
AnnaBridge 143:86740a56073b 169 * @{
AnnaBridge 143:86740a56073b 170 */
AnnaBridge 143:86740a56073b 171 /**
AnnaBridge 143:86740a56073b 172 * @brief RCC_CRS Init structure definition
AnnaBridge 143:86740a56073b 173 */
AnnaBridge 143:86740a56073b 174 typedef struct
AnnaBridge 143:86740a56073b 175 {
AnnaBridge 143:86740a56073b 176 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
AnnaBridge 143:86740a56073b 177 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
AnnaBridge 143:86740a56073b 178
AnnaBridge 143:86740a56073b 179 uint32_t Source; /*!< Specifies the SYNC signal source.
AnnaBridge 143:86740a56073b 180 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
AnnaBridge 143:86740a56073b 181
AnnaBridge 143:86740a56073b 182 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
AnnaBridge 143:86740a56073b 183 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
AnnaBridge 143:86740a56073b 184
AnnaBridge 143:86740a56073b 185 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
AnnaBridge 143:86740a56073b 186 It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
AnnaBridge 143:86740a56073b 187 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
AnnaBridge 143:86740a56073b 188
AnnaBridge 143:86740a56073b 189 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
AnnaBridge 143:86740a56073b 190 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
AnnaBridge 143:86740a56073b 191
AnnaBridge 143:86740a56073b 192 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
AnnaBridge 143:86740a56073b 193 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
AnnaBridge 143:86740a56073b 194
AnnaBridge 143:86740a56073b 195 }RCC_CRSInitTypeDef;
AnnaBridge 143:86740a56073b 196
AnnaBridge 143:86740a56073b 197 /**
AnnaBridge 143:86740a56073b 198 * @brief RCC_CRS Synchronization structure definition
AnnaBridge 143:86740a56073b 199 */
AnnaBridge 143:86740a56073b 200 typedef struct
AnnaBridge 143:86740a56073b 201 {
AnnaBridge 143:86740a56073b 202 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
AnnaBridge 143:86740a56073b 203 This parameter must be a number between 0 and 0xFFFF*/
AnnaBridge 143:86740a56073b 204
AnnaBridge 143:86740a56073b 205 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
AnnaBridge 143:86740a56073b 206 This parameter must be a number between 0 and 0x3F */
AnnaBridge 143:86740a56073b 207
AnnaBridge 143:86740a56073b 208 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
AnnaBridge 143:86740a56073b 209 value latched in the time of the last SYNC event.
AnnaBridge 143:86740a56073b 210 This parameter must be a number between 0 and 0xFFFF */
AnnaBridge 143:86740a56073b 211
AnnaBridge 143:86740a56073b 212 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
AnnaBridge 143:86740a56073b 213 frequency error counter latched in the time of the last SYNC event.
AnnaBridge 143:86740a56073b 214 It shows whether the actual frequency is below or above the target.
AnnaBridge 143:86740a56073b 215 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
AnnaBridge 143:86740a56073b 216
AnnaBridge 143:86740a56073b 217 }RCC_CRSSynchroInfoTypeDef;
AnnaBridge 143:86740a56073b 218
AnnaBridge 143:86740a56073b 219 /**
AnnaBridge 143:86740a56073b 220 * @}
AnnaBridge 143:86740a56073b 221 */
AnnaBridge 143:86740a56073b 222
AnnaBridge 143:86740a56073b 223 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
AnnaBridge 143:86740a56073b 224
AnnaBridge 143:86740a56073b 225 /* Exported constants --------------------------------------------------------*/
AnnaBridge 143:86740a56073b 226 /** @addtogroup RCCEx_Exported_Constants
AnnaBridge 143:86740a56073b 227 * @{
AnnaBridge 143:86740a56073b 228 */
AnnaBridge 143:86740a56073b 229
AnnaBridge 143:86740a56073b 230 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
AnnaBridge 143:86740a56073b 231 * @{
AnnaBridge 143:86740a56073b 232 */
AnnaBridge 143:86740a56073b 233 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge 143:86740a56073b 234
AnnaBridge 143:86740a56073b 235 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001U)
AnnaBridge 143:86740a56073b 236 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002U)
AnnaBridge 143:86740a56073b 237 #define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004U)
AnnaBridge 143:86740a56073b 238 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008U)
AnnaBridge 143:86740a56073b 239 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010U)
AnnaBridge 143:86740a56073b 240 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)
AnnaBridge 143:86740a56073b 241 #define RCC_PERIPHCLK_USB ((uint32_t)0x00000040U)
AnnaBridge 143:86740a56073b 242 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080U)
AnnaBridge 143:86740a56073b 243 #if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
AnnaBridge 143:86740a56073b 244 #define RCC_PERIPHCLK_LCD ((uint32_t)0x00000800U)
AnnaBridge 143:86740a56073b 245 #endif
AnnaBridge 143:86740a56073b 246 #if defined (STM32L072xx) || defined(STM32L073xx) || defined(STM32L082xx) || defined(STM32L083xx)
AnnaBridge 143:86740a56073b 247 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100U)
AnnaBridge 143:86740a56073b 248 #endif
AnnaBridge 143:86740a56073b 249
AnnaBridge 143:86740a56073b 250
AnnaBridge 143:86740a56073b 251 #else /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
AnnaBridge 143:86740a56073b 252
AnnaBridge 143:86740a56073b 253 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
AnnaBridge 143:86740a56073b 254 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001U)
AnnaBridge 143:86740a56073b 255 #endif
AnnaBridge 143:86740a56073b 256 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002U)
AnnaBridge 143:86740a56073b 257 #define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004U)
AnnaBridge 143:86740a56073b 258 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008U)
AnnaBridge 143:86740a56073b 259 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
AnnaBridge 143:86740a56073b 260 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010U)
AnnaBridge 143:86740a56073b 261 #endif
AnnaBridge 143:86740a56073b 262 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)
AnnaBridge 143:86740a56073b 263 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080U)
AnnaBridge 143:86740a56073b 264 #if defined(STM32L071xx) || defined(STM32L081xx)
AnnaBridge 143:86740a56073b 265 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100U)
AnnaBridge 143:86740a56073b 266 #endif
AnnaBridge 143:86740a56073b 267
AnnaBridge 143:86740a56073b 268 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
AnnaBridge 143:86740a56073b 269 /**
AnnaBridge 143:86740a56073b 270 * @}
AnnaBridge 143:86740a56073b 271 */
AnnaBridge 143:86740a56073b 272
AnnaBridge 143:86740a56073b 273 /** @defgroup RCCEx_USART1_Clock_Source RCC USART1 Clock Source
AnnaBridge 143:86740a56073b 274 * @{
AnnaBridge 143:86740a56073b 275 */
AnnaBridge 143:86740a56073b 276 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
AnnaBridge 143:86740a56073b 277 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
AnnaBridge 143:86740a56073b 278 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
AnnaBridge 143:86740a56073b 279 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
AnnaBridge 143:86740a56073b 280
AnnaBridge 143:86740a56073b 281 /**
AnnaBridge 143:86740a56073b 282 * @}
AnnaBridge 143:86740a56073b 283 */
AnnaBridge 143:86740a56073b 284
AnnaBridge 143:86740a56073b 285 /** @defgroup RCCEx_USART2_Clock_Source RCC USART2 Clock Source
AnnaBridge 143:86740a56073b 286 * @{
AnnaBridge 143:86740a56073b 287 */
AnnaBridge 143:86740a56073b 288 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 143:86740a56073b 289 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
AnnaBridge 143:86740a56073b 290 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
AnnaBridge 143:86740a56073b 291 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
AnnaBridge 143:86740a56073b 292
AnnaBridge 143:86740a56073b 293 /**
AnnaBridge 143:86740a56073b 294 * @}
AnnaBridge 143:86740a56073b 295 */
AnnaBridge 143:86740a56073b 296
AnnaBridge 143:86740a56073b 297 /** @defgroup RCCEx_LPUART1_Clock_Source RCC LPUART Clock Source
AnnaBridge 143:86740a56073b 298 * @{
AnnaBridge 143:86740a56073b 299 */
AnnaBridge 143:86740a56073b 300 #define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 143:86740a56073b 301 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
AnnaBridge 143:86740a56073b 302 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
AnnaBridge 143:86740a56073b 303 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
AnnaBridge 143:86740a56073b 304
AnnaBridge 143:86740a56073b 305 /**
AnnaBridge 143:86740a56073b 306 * @}
AnnaBridge 143:86740a56073b 307 */
AnnaBridge 143:86740a56073b 308
AnnaBridge 143:86740a56073b 309 /** @defgroup RCCEx_I2C1_Clock_Source RCC I2C1 Clock Source
AnnaBridge 143:86740a56073b 310 * @{
AnnaBridge 143:86740a56073b 311 */
AnnaBridge 143:86740a56073b 312 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 143:86740a56073b 313 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
AnnaBridge 143:86740a56073b 314 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
AnnaBridge 143:86740a56073b 315
AnnaBridge 143:86740a56073b 316 /**
AnnaBridge 143:86740a56073b 317 * @}
AnnaBridge 143:86740a56073b 318 */
AnnaBridge 143:86740a56073b 319
AnnaBridge 143:86740a56073b 320 #if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx)|| defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
AnnaBridge 143:86740a56073b 321
AnnaBridge 143:86740a56073b 322 /** @defgroup RCCEx_I2C3_Clock_Source RCC I2C3 Clock Source
AnnaBridge 143:86740a56073b 323 * @{
AnnaBridge 143:86740a56073b 324 */
AnnaBridge 143:86740a56073b 325 #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 143:86740a56073b 326 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
AnnaBridge 143:86740a56073b 327 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
AnnaBridge 143:86740a56073b 328
AnnaBridge 143:86740a56073b 329 /**
AnnaBridge 143:86740a56073b 330 * @}
AnnaBridge 143:86740a56073b 331 */
AnnaBridge 143:86740a56073b 332 #endif /* defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx)|| defined(STM32L082xx) || defined(STM32L083xx) */
AnnaBridge 143:86740a56073b 333
AnnaBridge 143:86740a56073b 334
AnnaBridge 143:86740a56073b 335
AnnaBridge 143:86740a56073b 336 /** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM Prescaler Selection
AnnaBridge 143:86740a56073b 337 * @{
AnnaBridge 143:86740a56073b 338 */
AnnaBridge 143:86740a56073b 339 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00U)
AnnaBridge 143:86740a56073b 340 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01U)
AnnaBridge 143:86740a56073b 341 /**
AnnaBridge 143:86740a56073b 342 * @}
AnnaBridge 143:86740a56073b 343 */
AnnaBridge 143:86740a56073b 344
AnnaBridge 143:86740a56073b 345 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge 143:86740a56073b 346 /** @defgroup RCCEx_USB_Clock_Source RCC USB Clock Source
AnnaBridge 143:86740a56073b 347 * @{
AnnaBridge 143:86740a56073b 348 */
AnnaBridge 143:86740a56073b 349 #define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
AnnaBridge 143:86740a56073b 350 #define RCC_USBCLKSOURCE_PLL ((uint32_t)0x00000000U)
AnnaBridge 143:86740a56073b 351
AnnaBridge 143:86740a56073b 352 /**
AnnaBridge 143:86740a56073b 353 * @}
AnnaBridge 143:86740a56073b 354 */
AnnaBridge 143:86740a56073b 355
AnnaBridge 143:86740a56073b 356 /** @defgroup RCCEx_RNG_Clock_Source RCC RNG Clock Source
AnnaBridge 143:86740a56073b 357 * @{
AnnaBridge 143:86740a56073b 358 */
AnnaBridge 143:86740a56073b 359 #define RCC_RNGCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
AnnaBridge 143:86740a56073b 360 #define RCC_RNGCLKSOURCE_PLLCLK ((uint32_t)0x00000000U)
AnnaBridge 143:86740a56073b 361
AnnaBridge 143:86740a56073b 362 /**
AnnaBridge 143:86740a56073b 363 * @}
AnnaBridge 143:86740a56073b 364 */
AnnaBridge 143:86740a56073b 365
AnnaBridge 143:86740a56073b 366 /** @defgroup RCCEx_HSI48M_Clock_Source RCC HSI48M Clock Source
AnnaBridge 143:86740a56073b 367 * @{
AnnaBridge 143:86740a56073b 368 */
AnnaBridge 143:86740a56073b 369 #define RCC_FLAG_HSI48 SYSCFG_CFGR3_VREFINT_RDYF
AnnaBridge 143:86740a56073b 370
AnnaBridge 143:86740a56073b 371 #define RCC_HSI48M_PLL ((uint32_t)0x00000000U)
AnnaBridge 143:86740a56073b 372 #define RCC_HSI48M_HSI48 RCC_CCIPR_HSI48SEL
AnnaBridge 143:86740a56073b 373
AnnaBridge 143:86740a56073b 374
AnnaBridge 143:86740a56073b 375 /**
AnnaBridge 143:86740a56073b 376 * @}
AnnaBridge 143:86740a56073b 377 */
AnnaBridge 143:86740a56073b 378 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
AnnaBridge 143:86740a56073b 379
AnnaBridge 143:86740a56073b 380 /** @defgroup RCC_HSI_Config RCC HSI Configuration
AnnaBridge 143:86740a56073b 381 * @{
AnnaBridge 143:86740a56073b 382 */
AnnaBridge 143:86740a56073b 383 #define RCC_HSI_OFF ((uint8_t)0x00U)
AnnaBridge 143:86740a56073b 384 #define RCC_HSI_ON RCC_CR_HSION
AnnaBridge 143:86740a56073b 385 #define RCC_HSI_DIV4 (RCC_CR_HSIDIVEN | RCC_CR_HSION)
AnnaBridge 143:86740a56073b 386 #if defined(STM32L073xx) || defined(STM32L083xx) || \
AnnaBridge 143:86740a56073b 387 defined(STM32L072xx) || defined(STM32L082xx) || \
AnnaBridge 143:86740a56073b 388 defined(STM32L071xx) || defined(STM32L081xx)
AnnaBridge 143:86740a56073b 389 #define RCC_HSI_OUTEN RCC_CR_HSIOUTEN
AnnaBridge 143:86740a56073b 390 #endif
AnnaBridge 143:86740a56073b 391
AnnaBridge 143:86740a56073b 392 /**
AnnaBridge 143:86740a56073b 393 * @}
AnnaBridge 143:86740a56073b 394 */
AnnaBridge 143:86740a56073b 395
AnnaBridge 143:86740a56073b 396 /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
AnnaBridge 143:86740a56073b 397 * @{
AnnaBridge 143:86740a56073b 398 */
AnnaBridge 143:86740a56073b 399 #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
AnnaBridge 143:86740a56073b 400 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
AnnaBridge 143:86740a56073b 401 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
AnnaBridge 143:86740a56073b 402 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
AnnaBridge 143:86740a56073b 403
AnnaBridge 143:86740a56073b 404 /**
AnnaBridge 143:86740a56073b 405 * @}
AnnaBridge 143:86740a56073b 406 */
AnnaBridge 143:86740a56073b 407
AnnaBridge 143:86740a56073b 408 /** @defgroup RCCEx_StopWakeUp_Clock RCC StopWakeUp Clock
AnnaBridge 143:86740a56073b 409 * @{
AnnaBridge 143:86740a56073b 410 */
AnnaBridge 143:86740a56073b 411
AnnaBridge 143:86740a56073b 412 #define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00U)
AnnaBridge 143:86740a56073b 413 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK
AnnaBridge 143:86740a56073b 414
AnnaBridge 143:86740a56073b 415 /**
AnnaBridge 143:86740a56073b 416 * @}
AnnaBridge 143:86740a56073b 417 */
AnnaBridge 143:86740a56073b 418
AnnaBridge 143:86740a56073b 419 /** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration
AnnaBridge 143:86740a56073b 420 * @{
AnnaBridge 143:86740a56073b 421 */
AnnaBridge 143:86740a56073b 422
AnnaBridge 143:86740a56073b 423 #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U)
AnnaBridge 143:86740a56073b 424 #define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0
AnnaBridge 143:86740a56073b 425 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1
AnnaBridge 143:86740a56073b 426 #define RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV
AnnaBridge 143:86740a56073b 427
AnnaBridge 143:86740a56073b 428 /**
AnnaBridge 143:86740a56073b 429 * @}
AnnaBridge 143:86740a56073b 430 */
AnnaBridge 143:86740a56073b 431
AnnaBridge 143:86740a56073b 432 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
AnnaBridge 143:86740a56073b 433 * @{
AnnaBridge 143:86740a56073b 434 */
AnnaBridge 143:86740a56073b 435 #define RCC_EXTI_LINE_LSECSS (EXTI_IMR_IM19) /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
AnnaBridge 143:86740a56073b 436 /**
AnnaBridge 143:86740a56073b 437 * @}
AnnaBridge 143:86740a56073b 438 */
AnnaBridge 143:86740a56073b 439
AnnaBridge 143:86740a56073b 440 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge 143:86740a56073b 441 /** @defgroup RCCEx_CRS_SynchroSource RCC CRS Synchro Source
AnnaBridge 143:86740a56073b 442 * @{
AnnaBridge 143:86740a56073b 443 */
AnnaBridge 143:86740a56073b 444 #define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal source GPIO */
AnnaBridge 143:86740a56073b 445 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
AnnaBridge 143:86740a56073b 446 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
AnnaBridge 143:86740a56073b 447
AnnaBridge 143:86740a56073b 448 /**
AnnaBridge 143:86740a56073b 449 * @}
AnnaBridge 143:86740a56073b 450 */
AnnaBridge 143:86740a56073b 451
AnnaBridge 143:86740a56073b 452 /** @defgroup RCCEx_CRS_SynchroDivider RCC CRS Synchro Divider
AnnaBridge 143:86740a56073b 453 * @{
AnnaBridge 143:86740a56073b 454 */
AnnaBridge 143:86740a56073b 455 #define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */
AnnaBridge 143:86740a56073b 456 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
AnnaBridge 143:86740a56073b 457 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
AnnaBridge 143:86740a56073b 458 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
AnnaBridge 143:86740a56073b 459 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
AnnaBridge 143:86740a56073b 460 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
AnnaBridge 143:86740a56073b 461 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
AnnaBridge 143:86740a56073b 462 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
AnnaBridge 143:86740a56073b 463
AnnaBridge 143:86740a56073b 464 /**
AnnaBridge 143:86740a56073b 465 * @}
AnnaBridge 143:86740a56073b 466 */
AnnaBridge 143:86740a56073b 467
AnnaBridge 143:86740a56073b 468 /** @defgroup RCCEx_CRS_SynchroPolarity RCC CRS Synchro Polarity
AnnaBridge 143:86740a56073b 469 * @{
AnnaBridge 143:86740a56073b 470 */
AnnaBridge 143:86740a56073b 471 #define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */
AnnaBridge 143:86740a56073b 472 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
AnnaBridge 143:86740a56073b 473
AnnaBridge 143:86740a56073b 474 /**
AnnaBridge 143:86740a56073b 475 * @}
AnnaBridge 143:86740a56073b 476 */
AnnaBridge 143:86740a56073b 477
AnnaBridge 143:86740a56073b 478 /** @defgroup RCCEx_CRS_ReloadValueDefault RCC CRS Reload Default Value
AnnaBridge 143:86740a56073b 479 * @{
AnnaBridge 143:86740a56073b 480 */
AnnaBridge 143:86740a56073b 481 #define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU) /*!< The reset value of the RELOAD field corresponds
AnnaBridge 143:86740a56073b 482 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
AnnaBridge 143:86740a56073b 483
AnnaBridge 143:86740a56073b 484 /**
AnnaBridge 143:86740a56073b 485 * @}
AnnaBridge 143:86740a56073b 486 */
AnnaBridge 143:86740a56073b 487
AnnaBridge 143:86740a56073b 488 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCC CRS Error Limit Default
AnnaBridge 143:86740a56073b 489 * @{
AnnaBridge 143:86740a56073b 490 */
AnnaBridge 143:86740a56073b 491 #define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U) /*!< Default Frequency error limit */
AnnaBridge 143:86740a56073b 492
AnnaBridge 143:86740a56073b 493 /**
AnnaBridge 143:86740a56073b 494 * @}
AnnaBridge 143:86740a56073b 495 */
AnnaBridge 143:86740a56073b 496
AnnaBridge 143:86740a56073b 497 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCC CRS HSI48 Calibration Default
AnnaBridge 143:86740a56073b 498 * @{
AnnaBridge 143:86740a56073b 499 */
AnnaBridge 143:86740a56073b 500 #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
AnnaBridge 143:86740a56073b 501 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
AnnaBridge 143:86740a56073b 502 corresponds to a higher output frequency */
AnnaBridge 143:86740a56073b 503
AnnaBridge 143:86740a56073b 504 /**
AnnaBridge 143:86740a56073b 505 * @}
AnnaBridge 143:86740a56073b 506 */
AnnaBridge 143:86740a56073b 507
AnnaBridge 143:86740a56073b 508 /** @defgroup RCCEx_CRS_FreqErrorDirection RCC CRS Frequency Error Direction
AnnaBridge 143:86740a56073b 509 * @{
AnnaBridge 143:86740a56073b 510 */
AnnaBridge 143:86740a56073b 511 #define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */
AnnaBridge 143:86740a56073b 512 #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
AnnaBridge 143:86740a56073b 513
AnnaBridge 143:86740a56073b 514 /**
AnnaBridge 143:86740a56073b 515 * @}
AnnaBridge 143:86740a56073b 516 */
AnnaBridge 143:86740a56073b 517
AnnaBridge 143:86740a56073b 518 /** @defgroup RCCEx_CRS_Interrupt_Sources RCC CRS Interrupt Sources
AnnaBridge 143:86740a56073b 519 * @{
AnnaBridge 143:86740a56073b 520 */
AnnaBridge 143:86740a56073b 521 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */
AnnaBridge 143:86740a56073b 522 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */
AnnaBridge 143:86740a56073b 523 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< error */
AnnaBridge 143:86740a56073b 524 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */
AnnaBridge 143:86740a56073b 525 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */
AnnaBridge 143:86740a56073b 526 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */
AnnaBridge 143:86740a56073b 527 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed*/
AnnaBridge 143:86740a56073b 528
AnnaBridge 143:86740a56073b 529 /**
AnnaBridge 143:86740a56073b 530 * @}
AnnaBridge 143:86740a56073b 531 */
AnnaBridge 143:86740a56073b 532
AnnaBridge 143:86740a56073b 533 /** @defgroup RCCEx_CRS_Flags RCC CRS Flags
AnnaBridge 143:86740a56073b 534 * @{
AnnaBridge 143:86740a56073b 535 */
AnnaBridge 143:86740a56073b 536 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
AnnaBridge 143:86740a56073b 537 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
AnnaBridge 143:86740a56073b 538 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
AnnaBridge 143:86740a56073b 539 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
AnnaBridge 143:86740a56073b 540 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
AnnaBridge 143:86740a56073b 541 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
AnnaBridge 143:86740a56073b 542 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
AnnaBridge 143:86740a56073b 543
AnnaBridge 143:86740a56073b 544 /**
AnnaBridge 143:86740a56073b 545 * @}
AnnaBridge 143:86740a56073b 546 */
AnnaBridge 143:86740a56073b 547
AnnaBridge 143:86740a56073b 548 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
AnnaBridge 143:86740a56073b 549 /**
AnnaBridge 143:86740a56073b 550 * @}
AnnaBridge 143:86740a56073b 551 */
AnnaBridge 143:86740a56073b 552
AnnaBridge 143:86740a56073b 553 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 554 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
AnnaBridge 143:86740a56073b 555 * @{
AnnaBridge 143:86740a56073b 556 */
AnnaBridge 143:86740a56073b 557 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable
AnnaBridge 143:86740a56073b 558 * @brief Enable or disable the AHB peripheral clock.
AnnaBridge 143:86740a56073b 559 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 143:86740a56073b 560 * is disabled and the application software has to enable this clock before
AnnaBridge 143:86740a56073b 561 * using it.
AnnaBridge 143:86740a56073b 562 * @{
AnnaBridge 143:86740a56073b 563 */
AnnaBridge 143:86740a56073b 564
AnnaBridge 143:86740a56073b 565 #if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx) || defined(STM32L041xx) || defined(STM32L021xx)
AnnaBridge 143:86740a56073b 566 #define __HAL_RCC_AES_CLK_ENABLE() SET_BIT(RCC->AHBENR, (RCC_AHBENR_CRYPEN))
AnnaBridge 143:86740a56073b 567 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_CRYPEN))
AnnaBridge 143:86740a56073b 568 #endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx || STM32L041xx || STM32L021xx */
AnnaBridge 143:86740a56073b 569
AnnaBridge 143:86740a56073b 570 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge 143:86740a56073b 571 #define __HAL_RCC_TSC_CLK_ENABLE() SET_BIT(RCC->AHBENR, (RCC_AHBENR_TSCEN))
AnnaBridge 143:86740a56073b 572 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_TSCEN))
AnnaBridge 143:86740a56073b 573
AnnaBridge 143:86740a56073b 574 #define __HAL_RCC_RNG_CLK_ENABLE() SET_BIT(RCC->AHBENR, (RCC_AHBENR_RNGEN))
AnnaBridge 143:86740a56073b 575 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_RNGEN))
AnnaBridge 143:86740a56073b 576 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
AnnaBridge 143:86740a56073b 577
AnnaBridge 143:86740a56073b 578
AnnaBridge 143:86740a56073b 579 /**
AnnaBridge 143:86740a56073b 580 * @brief Enable interrupt on RCC LSE CSS EXTI Line 19.
AnnaBridge 143:86740a56073b 581 * @retval None
AnnaBridge 143:86740a56073b 582 */
AnnaBridge 143:86740a56073b 583 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
AnnaBridge 143:86740a56073b 584
AnnaBridge 143:86740a56073b 585 /**
AnnaBridge 143:86740a56073b 586 * @brief Disable interrupt on RCC LSE CSS EXTI Line 19.
AnnaBridge 143:86740a56073b 587 * @retval None
AnnaBridge 143:86740a56073b 588 */
AnnaBridge 143:86740a56073b 589 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
AnnaBridge 143:86740a56073b 590
AnnaBridge 143:86740a56073b 591 /**
AnnaBridge 143:86740a56073b 592 * @brief Enable event on RCC LSE CSS EXTI Line 19.
AnnaBridge 143:86740a56073b 593 * @retval None.
AnnaBridge 143:86740a56073b 594 */
AnnaBridge 143:86740a56073b 595 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
AnnaBridge 143:86740a56073b 596
AnnaBridge 143:86740a56073b 597 /**
AnnaBridge 143:86740a56073b 598 * @brief Disable event on RCC LSE CSS EXTI Line 19.
AnnaBridge 143:86740a56073b 599 * @retval None.
AnnaBridge 143:86740a56073b 600 */
AnnaBridge 143:86740a56073b 601 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
AnnaBridge 143:86740a56073b 602
AnnaBridge 143:86740a56073b 603
AnnaBridge 143:86740a56073b 604 /**
AnnaBridge 143:86740a56073b 605 * @brief RCC LSE CSS EXTI line configuration: set falling edge trigger.
AnnaBridge 143:86740a56073b 606 * @retval None.
AnnaBridge 143:86740a56073b 607 */
AnnaBridge 143:86740a56073b 608 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
AnnaBridge 143:86740a56073b 609
AnnaBridge 143:86740a56073b 610
AnnaBridge 143:86740a56073b 611 /**
AnnaBridge 143:86740a56073b 612 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
AnnaBridge 143:86740a56073b 613 * @retval None.
AnnaBridge 143:86740a56073b 614 */
AnnaBridge 143:86740a56073b 615 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
AnnaBridge 143:86740a56073b 616
AnnaBridge 143:86740a56073b 617
AnnaBridge 143:86740a56073b 618 /**
AnnaBridge 143:86740a56073b 619 * @brief RCC LSE CSS EXTI line configuration: set rising edge trigger.
AnnaBridge 143:86740a56073b 620 * @retval None.
AnnaBridge 143:86740a56073b 621 */
AnnaBridge 143:86740a56073b 622 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
AnnaBridge 143:86740a56073b 623
AnnaBridge 143:86740a56073b 624 /**
AnnaBridge 143:86740a56073b 625 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
AnnaBridge 143:86740a56073b 626 * @retval None.
AnnaBridge 143:86740a56073b 627 */
AnnaBridge 143:86740a56073b 628 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
AnnaBridge 143:86740a56073b 629
AnnaBridge 143:86740a56073b 630 /**
AnnaBridge 143:86740a56073b 631 * @brief RCC LSE CSS EXTI line configuration: set rising & falling edge trigger.
AnnaBridge 143:86740a56073b 632 * @retval None.
AnnaBridge 143:86740a56073b 633 */
AnnaBridge 143:86740a56073b 634 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
AnnaBridge 143:86740a56073b 635 do { \
AnnaBridge 143:86740a56073b 636 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
AnnaBridge 143:86740a56073b 637 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
AnnaBridge 143:86740a56073b 638 } while(0)
AnnaBridge 143:86740a56073b 639
AnnaBridge 143:86740a56073b 640 /**
AnnaBridge 143:86740a56073b 641 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
AnnaBridge 143:86740a56073b 642 * @retval None.
AnnaBridge 143:86740a56073b 643 */
AnnaBridge 143:86740a56073b 644 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
AnnaBridge 143:86740a56073b 645 do { \
AnnaBridge 143:86740a56073b 646 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
AnnaBridge 143:86740a56073b 647 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
AnnaBridge 143:86740a56073b 648 } while(0)
AnnaBridge 143:86740a56073b 649
AnnaBridge 143:86740a56073b 650 /**
AnnaBridge 143:86740a56073b 651 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
AnnaBridge 143:86740a56073b 652 * @retval EXTI RCC LSE CSS Line Status.
AnnaBridge 143:86740a56073b 653 */
AnnaBridge 143:86740a56073b 654 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (EXTI->PR & (RCC_EXTI_LINE_LSECSS))
AnnaBridge 143:86740a56073b 655
AnnaBridge 143:86740a56073b 656 /**
AnnaBridge 143:86740a56073b 657 * @brief Clear the RCC LSE CSS EXTI flag.
AnnaBridge 143:86740a56073b 658 * @retval None.
AnnaBridge 143:86740a56073b 659 */
AnnaBridge 143:86740a56073b 660 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() (EXTI->PR = (RCC_EXTI_LINE_LSECSS))
AnnaBridge 143:86740a56073b 661
AnnaBridge 143:86740a56073b 662 /**
AnnaBridge 143:86740a56073b 663 * @brief Generate a Software interrupt on selected EXTI line.
AnnaBridge 143:86740a56073b 664 * @retval None.
AnnaBridge 143:86740a56073b 665 */
AnnaBridge 143:86740a56073b 666 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS)
AnnaBridge 143:86740a56073b 667
AnnaBridge 143:86740a56073b 668
AnnaBridge 143:86740a56073b 669
AnnaBridge 143:86740a56073b 670 /**
AnnaBridge 143:86740a56073b 671 * @}
AnnaBridge 143:86740a56073b 672 */
AnnaBridge 143:86740a56073b 673
AnnaBridge 143:86740a56073b 674 /** @defgroup RCCEx_IOPORT_Clock_Enable_Disable IOPORT Peripheral Clock Enable Disable
AnnaBridge 143:86740a56073b 675 * @brief Enable or disable the IOPORT peripheral clock.
AnnaBridge 143:86740a56073b 676 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 143:86740a56073b 677 * is disabled and the application software has to enable this clock before
AnnaBridge 143:86740a56073b 678 * using it.
AnnaBridge 143:86740a56073b 679 * @{
AnnaBridge 143:86740a56073b 680 */
AnnaBridge 143:86740a56073b 681 #if defined(STM32L073xx) || defined(STM32L083xx) || \
AnnaBridge 143:86740a56073b 682 defined(STM32L072xx) || defined(STM32L082xx) || \
AnnaBridge 143:86740a56073b 683 defined(STM32L071xx) || defined(STM32L081xx)
AnnaBridge 143:86740a56073b 684 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge 143:86740a56073b 685 __IO uint32_t tmpreg; \
AnnaBridge 143:86740a56073b 686 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
AnnaBridge 143:86740a56073b 687 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 143:86740a56073b 688 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
AnnaBridge 143:86740a56073b 689 UNUSED(tmpreg); \
AnnaBridge 143:86740a56073b 690 } while(0)
AnnaBridge 143:86740a56073b 691
AnnaBridge 143:86740a56073b 692 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIOEEN))
AnnaBridge 143:86740a56073b 693
AnnaBridge 143:86740a56073b 694 #endif /* STM32L071xx || STM32L081xx || */
AnnaBridge 143:86740a56073b 695 /* STM32L072xx || STM32L082xx || */
AnnaBridge 143:86740a56073b 696 /* STM32L073xx || STM32L083xx */
AnnaBridge 143:86740a56073b 697 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
AnnaBridge 143:86740a56073b 698 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge 143:86740a56073b 699 __IO uint32_t tmpreg; \
AnnaBridge 143:86740a56073b 700 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
AnnaBridge 143:86740a56073b 701 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 143:86740a56073b 702 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
AnnaBridge 143:86740a56073b 703 UNUSED(tmpreg); \
AnnaBridge 143:86740a56073b 704 } while(0)
AnnaBridge 143:86740a56073b 705 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIODEN))
AnnaBridge 143:86740a56073b 706 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */
AnnaBridge 143:86740a56073b 707 /**
AnnaBridge 143:86740a56073b 708 * @}
AnnaBridge 143:86740a56073b 709 */
AnnaBridge 143:86740a56073b 710
AnnaBridge 143:86740a56073b 711 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge 143:86740a56073b 712 * @brief Enable or disable the APB1 peripheral clock.
AnnaBridge 143:86740a56073b 713 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 143:86740a56073b 714 * is disabled and the application software has to enable this clock before
AnnaBridge 143:86740a56073b 715 * using it.
AnnaBridge 143:86740a56073b 716 * @{
AnnaBridge 143:86740a56073b 717 */
AnnaBridge 143:86740a56073b 718
AnnaBridge 143:86740a56073b 719 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge 143:86740a56073b 720 #define __HAL_RCC_USB_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN))
AnnaBridge 143:86740a56073b 721 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN))
AnnaBridge 143:86740a56073b 722
AnnaBridge 143:86740a56073b 723 #define __HAL_RCC_CRS_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_CRSEN))
AnnaBridge 143:86740a56073b 724 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR,(RCC_APB1ENR_CRSEN))
AnnaBridge 143:86740a56073b 725 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
AnnaBridge 143:86740a56073b 726
AnnaBridge 143:86740a56073b 727
AnnaBridge 143:86740a56073b 728 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
AnnaBridge 143:86740a56073b 729 #define __HAL_RCC_LCD_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN))
AnnaBridge 143:86740a56073b 730 #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN))
AnnaBridge 143:86740a56073b 731 #endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
AnnaBridge 143:86740a56073b 732
AnnaBridge 143:86740a56073b 733 #if defined(STM32L053xx) || defined(STM32L063xx) || \
AnnaBridge 143:86740a56073b 734 defined(STM32L052xx) || defined(STM32L062xx) || \
AnnaBridge 143:86740a56073b 735 defined(STM32L051xx) || defined(STM32L061xx)
AnnaBridge 143:86740a56073b 736 #define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
AnnaBridge 143:86740a56073b 737 #define __HAL_RCC_TIM6_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
AnnaBridge 143:86740a56073b 738 #define __HAL_RCC_SPI2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
AnnaBridge 143:86740a56073b 739 #define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
AnnaBridge 143:86740a56073b 740 #define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
AnnaBridge 143:86740a56073b 741 #define __HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
AnnaBridge 143:86740a56073b 742 #define __HAL_RCC_I2C2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
AnnaBridge 143:86740a56073b 743 #define __HAL_RCC_DAC_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
AnnaBridge 143:86740a56073b 744 #define __HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
AnnaBridge 143:86740a56073b 745
AnnaBridge 143:86740a56073b 746 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
AnnaBridge 143:86740a56073b 747 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
AnnaBridge 143:86740a56073b 748 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
AnnaBridge 143:86740a56073b 749 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
AnnaBridge 143:86740a56073b 750 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
AnnaBridge 143:86740a56073b 751 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
AnnaBridge 143:86740a56073b 752 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
AnnaBridge 143:86740a56073b 753 #define __HAL_RCC_DAC_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
AnnaBridge 143:86740a56073b 754 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
AnnaBridge 143:86740a56073b 755 #endif /* STM32L051xx || STM32L061xx || */
AnnaBridge 143:86740a56073b 756 /* STM32L052xx || STM32L062xx || */
AnnaBridge 143:86740a56073b 757 /* STM32L053xx || STM32L063xx || */
AnnaBridge 143:86740a56073b 758
AnnaBridge 143:86740a56073b 759 #if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx)
AnnaBridge 143:86740a56073b 760 #define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
AnnaBridge 143:86740a56073b 761 #define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
AnnaBridge 143:86740a56073b 762 #define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
AnnaBridge 143:86740a56073b 763 #define __HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
AnnaBridge 143:86740a56073b 764 #define __HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
AnnaBridge 143:86740a56073b 765
AnnaBridge 143:86740a56073b 766 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
AnnaBridge 143:86740a56073b 767 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
AnnaBridge 143:86740a56073b 768 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
AnnaBridge 143:86740a56073b 769 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
AnnaBridge 143:86740a56073b 770 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
AnnaBridge 143:86740a56073b 771 #endif /* STM32L011xx || STM32L021xx || STM32L031xx || STM32L041xx */
AnnaBridge 143:86740a56073b 772
AnnaBridge 143:86740a56073b 773
AnnaBridge 143:86740a56073b 774 #if defined(STM32L073xx) || defined(STM32L083xx) || \
AnnaBridge 143:86740a56073b 775 defined(STM32L072xx) || defined(STM32L082xx) || \
AnnaBridge 143:86740a56073b 776 defined(STM32L071xx) || defined(STM32L081xx)
AnnaBridge 143:86740a56073b 777 #define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
AnnaBridge 143:86740a56073b 778 #define __HAL_RCC_TIM3_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN))
AnnaBridge 143:86740a56073b 779 #define __HAL_RCC_TIM6_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
AnnaBridge 143:86740a56073b 780 #define __HAL_RCC_TIM7_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN))
AnnaBridge 143:86740a56073b 781 #define __HAL_RCC_SPI2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
AnnaBridge 143:86740a56073b 782 #define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
AnnaBridge 143:86740a56073b 783 #define __HAL_RCC_USART4_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN))
AnnaBridge 143:86740a56073b 784 #define __HAL_RCC_USART5_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN))
AnnaBridge 143:86740a56073b 785 #define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
AnnaBridge 143:86740a56073b 786 #define __HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
AnnaBridge 143:86740a56073b 787 #define __HAL_RCC_I2C2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
AnnaBridge 143:86740a56073b 788 #define __HAL_RCC_I2C3_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN))
AnnaBridge 143:86740a56073b 789 #define __HAL_RCC_DAC_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
AnnaBridge 143:86740a56073b 790 #define __HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
AnnaBridge 143:86740a56073b 791
AnnaBridge 143:86740a56073b 792 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
AnnaBridge 143:86740a56073b 793 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN))
AnnaBridge 143:86740a56073b 794 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
AnnaBridge 143:86740a56073b 795 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN))
AnnaBridge 143:86740a56073b 796 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
AnnaBridge 143:86740a56073b 797 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
AnnaBridge 143:86740a56073b 798 #define __HAL_RCC_USART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN))
AnnaBridge 143:86740a56073b 799 #define __HAL_RCC_USART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN))
AnnaBridge 143:86740a56073b 800 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
AnnaBridge 143:86740a56073b 801 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
AnnaBridge 143:86740a56073b 802 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
AnnaBridge 143:86740a56073b 803 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN))
AnnaBridge 143:86740a56073b 804 #define __HAL_RCC_DAC_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
AnnaBridge 143:86740a56073b 805 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
AnnaBridge 143:86740a56073b 806 #endif /* STM32L071xx || STM32L081xx || */
AnnaBridge 143:86740a56073b 807 /* STM32L072xx || STM32L082xx || */
AnnaBridge 143:86740a56073b 808 /* STM32L073xx || STM32L083xx */
AnnaBridge 143:86740a56073b 809
AnnaBridge 143:86740a56073b 810 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
AnnaBridge 143:86740a56073b 811 defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) || \
AnnaBridge 143:86740a56073b 812 defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx) || \
AnnaBridge 143:86740a56073b 813 defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L011xx) || defined(STM32L021xx)
AnnaBridge 143:86740a56073b 814 /**
AnnaBridge 143:86740a56073b 815 * @}
AnnaBridge 143:86740a56073b 816 */
AnnaBridge 143:86740a56073b 817
AnnaBridge 143:86740a56073b 818 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge 143:86740a56073b 819 * @brief Enable or disable the APB2 peripheral clock.
AnnaBridge 143:86740a56073b 820 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 143:86740a56073b 821 * is disabled and the application software has to enable this clock before
AnnaBridge 143:86740a56073b 822 * using it.
AnnaBridge 143:86740a56073b 823 * @{
AnnaBridge 143:86740a56073b 824 */
AnnaBridge 143:86740a56073b 825 #define __HAL_RCC_TIM21_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN))
AnnaBridge 143:86740a56073b 826 #if !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge 143:86740a56073b 827 #define __HAL_RCC_TIM22_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN))
AnnaBridge 143:86740a56073b 828 #endif
AnnaBridge 143:86740a56073b 829 #define __HAL_RCC_ADC1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN))
AnnaBridge 143:86740a56073b 830 #define __HAL_RCC_SPI1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN))
AnnaBridge 143:86740a56073b 831 #define __HAL_RCC_USART1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN))
AnnaBridge 143:86740a56073b 832
AnnaBridge 143:86740a56073b 833 #define __HAL_RCC_TIM21_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN))
AnnaBridge 143:86740a56073b 834 #if !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge 143:86740a56073b 835 #define __HAL_RCC_TIM22_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN))
AnnaBridge 143:86740a56073b 836 #endif
AnnaBridge 143:86740a56073b 837 #define __HAL_RCC_ADC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN))
AnnaBridge 143:86740a56073b 838 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN))
AnnaBridge 143:86740a56073b 839 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN))
AnnaBridge 143:86740a56073b 840 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
AnnaBridge 143:86740a56073b 841 #define __HAL_RCC_FIREWALL_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN))
AnnaBridge 143:86740a56073b 842 #define __HAL_RCC_FIREWALL_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN))
AnnaBridge 143:86740a56073b 843 #endif /* !(STM32L011xx) && !(STM32L021xx) && !STM32L031xx && !STM32L041xx */
AnnaBridge 143:86740a56073b 844 #endif /* STM32L051xx || STM32L061xx || STM32L071xx || STM32L081xx || */
AnnaBridge 143:86740a56073b 845 /* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */
AnnaBridge 143:86740a56073b 846 /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx || */
AnnaBridge 143:86740a56073b 847 /* STM32L031xx || STM32L041xx || STM32L011xx || STM32L021xx */
AnnaBridge 143:86740a56073b 848
AnnaBridge 143:86740a56073b 849 /**
AnnaBridge 143:86740a56073b 850 * @}
AnnaBridge 143:86740a56073b 851 */
AnnaBridge 143:86740a56073b 852
AnnaBridge 143:86740a56073b 853 /** @defgroup RCCEx_AHB_Force_Release_Reset AHB Peripheral Force Release Reset
AnnaBridge 143:86740a56073b 854 * @brief Force or release AHB peripheral reset.
AnnaBridge 143:86740a56073b 855 * @{
AnnaBridge 143:86740a56073b 856 */
AnnaBridge 143:86740a56073b 857 #if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx) || defined(STM32L041xx) || defined(STM32L021xx)
AnnaBridge 143:86740a56073b 858 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRYPRST))
AnnaBridge 143:86740a56073b 859 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRYPRST))
AnnaBridge 143:86740a56073b 860 #endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx || STM32L041xx || STM32L021xx*/
AnnaBridge 143:86740a56073b 861
AnnaBridge 143:86740a56073b 862 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge 143:86740a56073b 863 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_TSCRST))
AnnaBridge 143:86740a56073b 864 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_TSCRST))
AnnaBridge 143:86740a56073b 865 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_RNGRST))
AnnaBridge 143:86740a56073b 866 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_RNGRST))
AnnaBridge 143:86740a56073b 867 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
AnnaBridge 143:86740a56073b 868
AnnaBridge 143:86740a56073b 869 /**
AnnaBridge 143:86740a56073b 870 * @}
AnnaBridge 143:86740a56073b 871 */
AnnaBridge 143:86740a56073b 872
AnnaBridge 143:86740a56073b 873 /** @defgroup RCCEx_IOPORT_Force_Release_Reset IOPORT Peripheral Force Release Reset
AnnaBridge 143:86740a56073b 874 * @brief Force or release IOPORT peripheral reset.
AnnaBridge 143:86740a56073b 875 * @{
AnnaBridge 143:86740a56073b 876 */
AnnaBridge 143:86740a56073b 877 #if defined(STM32L073xx) || defined(STM32L083xx) || \
AnnaBridge 143:86740a56073b 878 defined(STM32L072xx) || defined(STM32L082xx) || \
AnnaBridge 143:86740a56073b 879 defined(STM32L071xx) || defined(STM32L081xx)
AnnaBridge 143:86740a56073b 880 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOERST))
AnnaBridge 143:86740a56073b 881
AnnaBridge 143:86740a56073b 882 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIOERST))
AnnaBridge 143:86740a56073b 883
AnnaBridge 143:86740a56073b 884 #endif /* STM32L071xx || STM32L081xx || */
AnnaBridge 143:86740a56073b 885 /* STM32L072xx || STM32L082xx || */
AnnaBridge 143:86740a56073b 886 /* STM32L073xx || STM32L083xx */
AnnaBridge 143:86740a56073b 887 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
AnnaBridge 143:86740a56073b 888 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIODRST))
AnnaBridge 143:86740a56073b 889 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIODRST))
AnnaBridge 143:86740a56073b 890 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */
AnnaBridge 143:86740a56073b 891 /**
AnnaBridge 143:86740a56073b 892 * @}
AnnaBridge 143:86740a56073b 893 */
AnnaBridge 143:86740a56073b 894
AnnaBridge 143:86740a56073b 895 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
AnnaBridge 143:86740a56073b 896 * @brief Force or release APB1 peripheral reset.
AnnaBridge 143:86740a56073b 897 * @{
AnnaBridge 143:86740a56073b 898 */
AnnaBridge 143:86740a56073b 899
AnnaBridge 143:86740a56073b 900 #if defined(STM32L053xx) || defined(STM32L063xx) || \
AnnaBridge 143:86740a56073b 901 defined(STM32L052xx) || defined(STM32L062xx) || \
AnnaBridge 143:86740a56073b 902 defined(STM32L051xx) || defined(STM32L061xx)
AnnaBridge 143:86740a56073b 903 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
AnnaBridge 143:86740a56073b 904 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
AnnaBridge 143:86740a56073b 905 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
AnnaBridge 143:86740a56073b 906 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
AnnaBridge 143:86740a56073b 907 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
AnnaBridge 143:86740a56073b 908 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
AnnaBridge 143:86740a56073b 909 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
AnnaBridge 143:86740a56073b 910 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
AnnaBridge 143:86740a56073b 911 #define __HAL_RCC_DAC_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
AnnaBridge 143:86740a56073b 912
AnnaBridge 143:86740a56073b 913 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
AnnaBridge 143:86740a56073b 914 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
AnnaBridge 143:86740a56073b 915 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
AnnaBridge 143:86740a56073b 916 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
AnnaBridge 143:86740a56073b 917 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
AnnaBridge 143:86740a56073b 918 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
AnnaBridge 143:86740a56073b 919 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
AnnaBridge 143:86740a56073b 920 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
AnnaBridge 143:86740a56073b 921 #define __HAL_RCC_DAC_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
AnnaBridge 143:86740a56073b 922 #endif /* STM32L051xx || STM32L061xx || */
AnnaBridge 143:86740a56073b 923 /* STM32L052xx || STM32L062xx || */
AnnaBridge 143:86740a56073b 924 /* STM32L053xx || STM32L063xx */
AnnaBridge 143:86740a56073b 925 #if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx)
AnnaBridge 143:86740a56073b 926 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
AnnaBridge 143:86740a56073b 927 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
AnnaBridge 143:86740a56073b 928 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
AnnaBridge 143:86740a56073b 929 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
AnnaBridge 143:86740a56073b 930 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
AnnaBridge 143:86740a56073b 931
AnnaBridge 143:86740a56073b 932 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
AnnaBridge 143:86740a56073b 933 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
AnnaBridge 143:86740a56073b 934 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
AnnaBridge 143:86740a56073b 935 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
AnnaBridge 143:86740a56073b 936 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
AnnaBridge 143:86740a56073b 937 #endif /* STM32L031xx || STM32L041xx || STM32L011xx || STM32L021xx */
AnnaBridge 143:86740a56073b 938
AnnaBridge 143:86740a56073b 939 #if defined(STM32L073xx) || defined(STM32L083xx) || \
AnnaBridge 143:86740a56073b 940 defined(STM32L072xx) || defined(STM32L082xx) || \
AnnaBridge 143:86740a56073b 941 defined(STM32L071xx) || defined(STM32L081xx)
AnnaBridge 143:86740a56073b 942 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
AnnaBridge 143:86740a56073b 943 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST))
AnnaBridge 143:86740a56073b 944 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
AnnaBridge 143:86740a56073b 945 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST))
AnnaBridge 143:86740a56073b 946 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
AnnaBridge 143:86740a56073b 947 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
AnnaBridge 143:86740a56073b 948 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
AnnaBridge 143:86740a56073b 949 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST))
AnnaBridge 143:86740a56073b 950 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
AnnaBridge 143:86740a56073b 951 #define __HAL_RCC_USART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST))
AnnaBridge 143:86740a56073b 952 #define __HAL_RCC_USART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST))
AnnaBridge 143:86740a56073b 953 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
AnnaBridge 143:86740a56073b 954 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
AnnaBridge 143:86740a56073b 955 #define __HAL_RCC_DAC_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
AnnaBridge 143:86740a56073b 956
AnnaBridge 143:86740a56073b 957 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
AnnaBridge 143:86740a56073b 958 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST))
AnnaBridge 143:86740a56073b 959 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
AnnaBridge 143:86740a56073b 960 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST))
AnnaBridge 143:86740a56073b 961 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
AnnaBridge 143:86740a56073b 962 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
AnnaBridge 143:86740a56073b 963 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
AnnaBridge 143:86740a56073b 964 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST))
AnnaBridge 143:86740a56073b 965 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
AnnaBridge 143:86740a56073b 966 #define __HAL_RCC_USART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST))
AnnaBridge 143:86740a56073b 967 #define __HAL_RCC_USART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST))
AnnaBridge 143:86740a56073b 968 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
AnnaBridge 143:86740a56073b 969 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
AnnaBridge 143:86740a56073b 970 #define __HAL_RCC_DAC_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
AnnaBridge 143:86740a56073b 971 #endif /* STM32L071xx || STM32L081xx || */
AnnaBridge 143:86740a56073b 972 /* STM32L072xx || STM32L082xx || */
AnnaBridge 143:86740a56073b 973 /* STM32L073xx || STM32L083xx || */
AnnaBridge 143:86740a56073b 974
AnnaBridge 143:86740a56073b 975 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge 143:86740a56073b 976 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USBRST))
AnnaBridge 143:86740a56073b 977 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USBRST))
AnnaBridge 143:86740a56073b 978 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_CRSRST))
AnnaBridge 143:86740a56073b 979 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR,(RCC_APB1RSTR_CRSRST))
AnnaBridge 143:86740a56073b 980 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
AnnaBridge 143:86740a56073b 981
AnnaBridge 143:86740a56073b 982 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
AnnaBridge 143:86740a56073b 983 #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LCDRST))
AnnaBridge 143:86740a56073b 984 #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LCDRST))
AnnaBridge 143:86740a56073b 985 #endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
AnnaBridge 143:86740a56073b 986
AnnaBridge 143:86740a56073b 987 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
AnnaBridge 143:86740a56073b 988 defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) || \
AnnaBridge 143:86740a56073b 989 defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx)
AnnaBridge 143:86740a56073b 990
AnnaBridge 143:86740a56073b 991 /**
AnnaBridge 143:86740a56073b 992 * @}
AnnaBridge 143:86740a56073b 993 */
AnnaBridge 143:86740a56073b 994
AnnaBridge 143:86740a56073b 995 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
AnnaBridge 143:86740a56073b 996 * @brief Force or release APB2 peripheral reset.
AnnaBridge 143:86740a56073b 997 * @{
AnnaBridge 143:86740a56073b 998 */
AnnaBridge 143:86740a56073b 999 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST))
AnnaBridge 143:86740a56073b 1000 #define __HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
AnnaBridge 143:86740a56073b 1001 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
AnnaBridge 143:86740a56073b 1002 #define __HAL_RCC_TIM21_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
AnnaBridge 143:86740a56073b 1003 #if !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge 143:86740a56073b 1004 #define __HAL_RCC_TIM22_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
AnnaBridge 143:86740a56073b 1005 #endif
AnnaBridge 143:86740a56073b 1006
AnnaBridge 143:86740a56073b 1007 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST))
AnnaBridge 143:86740a56073b 1008 #define __HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
AnnaBridge 143:86740a56073b 1009 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
AnnaBridge 143:86740a56073b 1010 #define __HAL_RCC_TIM21_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
AnnaBridge 143:86740a56073b 1011 #if !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge 143:86740a56073b 1012 #define __HAL_RCC_TIM22_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
AnnaBridge 143:86740a56073b 1013 #endif
AnnaBridge 143:86740a56073b 1014 #endif /* STM32L051xx || STM32L061xx || STM32L071xx || STM32L081xx || */
AnnaBridge 143:86740a56073b 1015 /* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */
AnnaBridge 143:86740a56073b 1016 /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx || */
AnnaBridge 143:86740a56073b 1017 #if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx)
AnnaBridge 143:86740a56073b 1018 #define __HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
AnnaBridge 143:86740a56073b 1019 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
AnnaBridge 143:86740a56073b 1020 #define __HAL_RCC_TIM21_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
AnnaBridge 143:86740a56073b 1021 #if !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge 143:86740a56073b 1022 #define __HAL_RCC_TIM22_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
AnnaBridge 143:86740a56073b 1023 #endif
AnnaBridge 143:86740a56073b 1024 #define __HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
AnnaBridge 143:86740a56073b 1025 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
AnnaBridge 143:86740a56073b 1026 #define __HAL_RCC_TIM21_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
AnnaBridge 143:86740a56073b 1027 #if !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge 143:86740a56073b 1028 #define __HAL_RCC_TIM22_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
AnnaBridge 143:86740a56073b 1029 #endif
AnnaBridge 143:86740a56073b 1030 #endif /* STM32L031xx || STM32L041xx || STM32L011xx || STM32L021xx*/
AnnaBridge 143:86740a56073b 1031
AnnaBridge 143:86740a56073b 1032
AnnaBridge 143:86740a56073b 1033 /**
AnnaBridge 143:86740a56073b 1034 * @}
AnnaBridge 143:86740a56073b 1035 */
AnnaBridge 143:86740a56073b 1036
AnnaBridge 143:86740a56073b 1037 /** @defgroup RCCEx_AHB_Clock_Sleep_Enable_Disable AHB Peripheral Clock Sleep Enable Disable
AnnaBridge 143:86740a56073b 1038 * @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
AnnaBridge 143:86740a56073b 1039 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 143:86740a56073b 1040 * power consumption.
AnnaBridge 143:86740a56073b 1041 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 143:86740a56073b 1042 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 143:86740a56073b 1043 * @{
AnnaBridge 143:86740a56073b 1044 */
AnnaBridge 143:86740a56073b 1045
AnnaBridge 143:86740a56073b 1046 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge 143:86740a56073b 1047 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_TSCSMEN))
AnnaBridge 143:86740a56073b 1048 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_RNGSMEN))
AnnaBridge 143:86740a56073b 1049 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_TSCSMEN))
AnnaBridge 143:86740a56073b 1050 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_RNGSMEN))
AnnaBridge 143:86740a56073b 1051 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
AnnaBridge 143:86740a56073b 1052
AnnaBridge 143:86740a56073b 1053 #if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx) || defined(STM32L041xx)
AnnaBridge 143:86740a56073b 1054 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBLPENR, (RCC_AHBSMENR_CRYPSMEN))
AnnaBridge 143:86740a56073b 1055 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBLPENR, (RCC_AHBSMENR_CRYPSMEN))
AnnaBridge 143:86740a56073b 1056 #endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx || STM32L041xx */
AnnaBridge 143:86740a56073b 1057
AnnaBridge 143:86740a56073b 1058 /**
AnnaBridge 143:86740a56073b 1059 * @}
AnnaBridge 143:86740a56073b 1060 */
AnnaBridge 143:86740a56073b 1061
AnnaBridge 143:86740a56073b 1062 /** @defgroup RCCEx_IOPORT_Clock_Sleep_Enable_Disable IOPORT Peripheral Clock Sleep Enable Disable
AnnaBridge 143:86740a56073b 1063 * @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
AnnaBridge 143:86740a56073b 1064 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 143:86740a56073b 1065 * power consumption.
AnnaBridge 143:86740a56073b 1066 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 143:86740a56073b 1067 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 143:86740a56073b 1068 * @{
AnnaBridge 143:86740a56073b 1069 */
AnnaBridge 143:86740a56073b 1070 #if defined(STM32L073xx) || defined(STM32L083xx) || \
AnnaBridge 143:86740a56073b 1071 defined(STM32L072xx) || defined(STM32L082xx) || \
AnnaBridge 143:86740a56073b 1072 defined(STM32L071xx) || defined(STM32L081xx)
AnnaBridge 143:86740a56073b 1073 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOESMEN))
AnnaBridge 143:86740a56073b 1074 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIOESMEN))
AnnaBridge 143:86740a56073b 1075
AnnaBridge 143:86740a56073b 1076 #endif /* STM32L071xx || STM32L081xx || */
AnnaBridge 143:86740a56073b 1077 /* STM32L072xx || STM32L082xx || */
AnnaBridge 143:86740a56073b 1078 /* STM32L073xx || STM32L083xx || */
AnnaBridge 143:86740a56073b 1079 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
AnnaBridge 143:86740a56073b 1080 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIODSMEN))
AnnaBridge 143:86740a56073b 1081 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIODSMEN))
AnnaBridge 143:86740a56073b 1082 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */
AnnaBridge 143:86740a56073b 1083 /**
AnnaBridge 143:86740a56073b 1084 * @}
AnnaBridge 143:86740a56073b 1085 */
AnnaBridge 143:86740a56073b 1086
AnnaBridge 143:86740a56073b 1087
AnnaBridge 143:86740a56073b 1088 /** @defgroup RCCEx_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
AnnaBridge 143:86740a56073b 1089 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 143:86740a56073b 1090 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 143:86740a56073b 1091 * power consumption.
AnnaBridge 143:86740a56073b 1092 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 143:86740a56073b 1093 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 143:86740a56073b 1094 * @{
AnnaBridge 143:86740a56073b 1095 */
AnnaBridge 143:86740a56073b 1096
AnnaBridge 143:86740a56073b 1097 #if defined(STM32L053xx) || defined(STM32L063xx) || \
AnnaBridge 143:86740a56073b 1098 defined(STM32L052xx) || defined(STM32L062xx) || \
AnnaBridge 143:86740a56073b 1099 defined(STM32L051xx) || defined(STM32L061xx)
AnnaBridge 143:86740a56073b 1100 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
AnnaBridge 143:86740a56073b 1101 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
AnnaBridge 143:86740a56073b 1102 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
AnnaBridge 143:86740a56073b 1103 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
AnnaBridge 143:86740a56073b 1104 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
AnnaBridge 143:86740a56073b 1105 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
AnnaBridge 143:86740a56073b 1106 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
AnnaBridge 143:86740a56073b 1107 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
AnnaBridge 143:86740a56073b 1108 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
AnnaBridge 143:86740a56073b 1109
AnnaBridge 143:86740a56073b 1110 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
AnnaBridge 143:86740a56073b 1111 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
AnnaBridge 143:86740a56073b 1112 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
AnnaBridge 143:86740a56073b 1113 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
AnnaBridge 143:86740a56073b 1114 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
AnnaBridge 143:86740a56073b 1115 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
AnnaBridge 143:86740a56073b 1116 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
AnnaBridge 143:86740a56073b 1117 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
AnnaBridge 143:86740a56073b 1118 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
AnnaBridge 143:86740a56073b 1119 #endif /* STM32L051xx || STM32L061xx || */
AnnaBridge 143:86740a56073b 1120 /* STM32L052xx || STM32L062xx || */
AnnaBridge 143:86740a56073b 1121 /* STM32L053xx || STM32L063xx */
AnnaBridge 143:86740a56073b 1122
AnnaBridge 143:86740a56073b 1123 #if defined(STM32L073xx) || defined(STM32L083xx) || \
AnnaBridge 143:86740a56073b 1124 defined(STM32L072xx) || defined(STM32L082xx) || \
AnnaBridge 143:86740a56073b 1125 defined(STM32L071xx) || defined(STM32L081xx)
AnnaBridge 143:86740a56073b 1126 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
AnnaBridge 143:86740a56073b 1127 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN))
AnnaBridge 143:86740a56073b 1128 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
AnnaBridge 143:86740a56073b 1129 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN))
AnnaBridge 143:86740a56073b 1130 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
AnnaBridge 143:86740a56073b 1131 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
AnnaBridge 143:86740a56073b 1132 #define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN))
AnnaBridge 143:86740a56073b 1133 #define __HAL_RCC_USART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN))
AnnaBridge 143:86740a56073b 1134 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
AnnaBridge 143:86740a56073b 1135 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
AnnaBridge 143:86740a56073b 1136 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
AnnaBridge 143:86740a56073b 1137 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN))
AnnaBridge 143:86740a56073b 1138 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
AnnaBridge 143:86740a56073b 1139 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
AnnaBridge 143:86740a56073b 1140
AnnaBridge 143:86740a56073b 1141 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
AnnaBridge 143:86740a56073b 1142 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN))
AnnaBridge 143:86740a56073b 1143 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
AnnaBridge 143:86740a56073b 1144 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN))
AnnaBridge 143:86740a56073b 1145 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
AnnaBridge 143:86740a56073b 1146 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
AnnaBridge 143:86740a56073b 1147 #define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN))
AnnaBridge 143:86740a56073b 1148 #define __HAL_RCC_USART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN))
AnnaBridge 143:86740a56073b 1149 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
AnnaBridge 143:86740a56073b 1150 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
AnnaBridge 143:86740a56073b 1151 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
AnnaBridge 143:86740a56073b 1152 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN))
AnnaBridge 143:86740a56073b 1153 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
AnnaBridge 143:86740a56073b 1154 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
AnnaBridge 143:86740a56073b 1155 #endif /* STM32L071xx || STM32L081xx || */
AnnaBridge 143:86740a56073b 1156 /* STM32L072xx || STM32L082xx || */
AnnaBridge 143:86740a56073b 1157 /* STM32L073xx || STM32L083xx || */
AnnaBridge 143:86740a56073b 1158
AnnaBridge 143:86740a56073b 1159 #if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx)
AnnaBridge 143:86740a56073b 1160 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
AnnaBridge 143:86740a56073b 1161 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
AnnaBridge 143:86740a56073b 1162 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
AnnaBridge 143:86740a56073b 1163 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
AnnaBridge 143:86740a56073b 1164 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
AnnaBridge 143:86740a56073b 1165
AnnaBridge 143:86740a56073b 1166 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
AnnaBridge 143:86740a56073b 1167 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
AnnaBridge 143:86740a56073b 1168 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
AnnaBridge 143:86740a56073b 1169 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
AnnaBridge 143:86740a56073b 1170 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
AnnaBridge 143:86740a56073b 1171 #endif /* STM32L031xx || STM32L041xx || STM32L011xx || STM32L021xx */
AnnaBridge 143:86740a56073b 1172
AnnaBridge 143:86740a56073b 1173 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge 143:86740a56073b 1174 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USBSMEN))
AnnaBridge 143:86740a56073b 1175 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USBSMEN))
AnnaBridge 143:86740a56073b 1176 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_CRSSMEN))
AnnaBridge 143:86740a56073b 1177 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_CRSSMEN))
AnnaBridge 143:86740a56073b 1178 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
AnnaBridge 143:86740a56073b 1179
AnnaBridge 143:86740a56073b 1180 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
AnnaBridge 143:86740a56073b 1181 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LCDSMEN))
AnnaBridge 143:86740a56073b 1182 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LCDSMEN))
AnnaBridge 143:86740a56073b 1183 #endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
AnnaBridge 143:86740a56073b 1184
AnnaBridge 143:86740a56073b 1185 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
AnnaBridge 143:86740a56073b 1186 defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) || \
AnnaBridge 143:86740a56073b 1187 defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx) || \
AnnaBridge 143:86740a56073b 1188 defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L011xx) || defined(STM32L021xx)
AnnaBridge 143:86740a56073b 1189
AnnaBridge 143:86740a56073b 1190 /**
AnnaBridge 143:86740a56073b 1191 * @}
AnnaBridge 143:86740a56073b 1192 */
AnnaBridge 143:86740a56073b 1193
AnnaBridge 143:86740a56073b 1194 /** @defgroup RCCEx_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
AnnaBridge 143:86740a56073b 1195 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 143:86740a56073b 1196 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 143:86740a56073b 1197 * power consumption.
AnnaBridge 143:86740a56073b 1198 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 143:86740a56073b 1199 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 143:86740a56073b 1200 * @{
AnnaBridge 143:86740a56073b 1201 */
AnnaBridge 143:86740a56073b 1202 #define __HAL_RCC_TIM21_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN))
AnnaBridge 143:86740a56073b 1203 #if !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge 143:86740a56073b 1204 #define __HAL_RCC_TIM22_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN))
AnnaBridge 143:86740a56073b 1205 #endif
AnnaBridge 143:86740a56073b 1206 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN))
AnnaBridge 143:86740a56073b 1207 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN))
AnnaBridge 143:86740a56073b 1208 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN))
AnnaBridge 143:86740a56073b 1209
AnnaBridge 143:86740a56073b 1210 #define __HAL_RCC_TIM21_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN))
AnnaBridge 143:86740a56073b 1211 #if !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge 143:86740a56073b 1212 #define __HAL_RCC_TIM22_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN))
AnnaBridge 143:86740a56073b 1213 #endif
AnnaBridge 143:86740a56073b 1214 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN))
AnnaBridge 143:86740a56073b 1215 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN))
AnnaBridge 143:86740a56073b 1216 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN))
AnnaBridge 143:86740a56073b 1217 #endif /* STM32L051xx || STM32L061xx || STM32L071xx || STM32L081xx || */
AnnaBridge 143:86740a56073b 1218 /* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */
AnnaBridge 143:86740a56073b 1219 /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx || */
AnnaBridge 143:86740a56073b 1220 /* STM32L031xx || STM32L041xx || STM32L011xx || STM32L021xx */
AnnaBridge 143:86740a56073b 1221
AnnaBridge 143:86740a56073b 1222 /** @brief Macro to configures LCD clock (LCDCLK).
AnnaBridge 143:86740a56073b 1223 * @note LCD and RTC use the same configuration
AnnaBridge 143:86740a56073b 1224 * @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the
AnnaBridge 143:86740a56073b 1225 * LCD clock source.
AnnaBridge 143:86740a56073b 1226 *
AnnaBridge 143:86740a56073b 1227 * @param __LCD_CLKSOURCE__ specifies the LCD clock source.
AnnaBridge 143:86740a56073b 1228 * This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1229 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock
AnnaBridge 143:86740a56073b 1230 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock
AnnaBridge 143:86740a56073b 1231 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock
AnnaBridge 143:86740a56073b 1232 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as LCD clock
AnnaBridge 143:86740a56073b 1233 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as LCD clock
AnnaBridge 143:86740a56073b 1234 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as LCD clock
AnnaBridge 143:86740a56073b 1235 */
AnnaBridge 143:86740a56073b 1236 #define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__)
AnnaBridge 143:86740a56073b 1237
AnnaBridge 143:86740a56073b 1238 /** @brief macros to get the LCD clock source.
AnnaBridge 143:86740a56073b 1239 */
AnnaBridge 143:86740a56073b 1240 #define __HAL_RCC_GET_LCD_SOURCE() __HAL_RCC_GET_RTC_SOURCE()
AnnaBridge 143:86740a56073b 1241
AnnaBridge 143:86740a56073b 1242 /** @brief macros to get the LCD clock pre-scaler.
AnnaBridge 143:86740a56073b 1243 */
AnnaBridge 143:86740a56073b 1244 #define __HAL_RCC_GET_LCD_HSE_PRESCALER() __HAL_RCC_GET_RTC_HSE_PRESCALER()
AnnaBridge 143:86740a56073b 1245 /**
AnnaBridge 143:86740a56073b 1246 * @}
AnnaBridge 143:86740a56073b 1247 */
AnnaBridge 143:86740a56073b 1248
AnnaBridge 143:86740a56073b 1249 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
AnnaBridge 143:86740a56073b 1250 *
AnnaBridge 143:86740a56073b 1251 * @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source.
AnnaBridge 143:86740a56073b 1252 * This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1253 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
AnnaBridge 143:86740a56073b 1254 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
AnnaBridge 143:86740a56073b 1255 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
AnnaBridge 143:86740a56073b 1256 * @retval None
AnnaBridge 143:86740a56073b 1257 */
AnnaBridge 143:86740a56073b 1258 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
AnnaBridge 143:86740a56073b 1259 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
AnnaBridge 143:86740a56073b 1260
AnnaBridge 143:86740a56073b 1261 /** @brief Macro to get the I2C1 clock source.
AnnaBridge 143:86740a56073b 1262 * @retval The clock source can be one of the following values:
AnnaBridge 143:86740a56073b 1263 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
AnnaBridge 143:86740a56073b 1264 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
AnnaBridge 143:86740a56073b 1265 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
AnnaBridge 143:86740a56073b 1266 */
AnnaBridge 143:86740a56073b 1267 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
AnnaBridge 143:86740a56073b 1268
AnnaBridge 143:86740a56073b 1269 #if defined (STM32L073xx) || defined(STM32L083xx) || \
AnnaBridge 143:86740a56073b 1270 defined(STM32L072xx) || defined(STM32L082xx) || \
AnnaBridge 143:86740a56073b 1271 defined(STM32L071xx) || defined(STM32L081xx)
AnnaBridge 143:86740a56073b 1272 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
AnnaBridge 143:86740a56073b 1273 *
AnnaBridge 143:86740a56073b 1274 * @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source.
AnnaBridge 143:86740a56073b 1275 * This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1276 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
AnnaBridge 143:86740a56073b 1277 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
AnnaBridge 143:86740a56073b 1278 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
AnnaBridge 143:86740a56073b 1279 * @retval None
AnnaBridge 143:86740a56073b 1280 */
AnnaBridge 143:86740a56073b 1281 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
AnnaBridge 143:86740a56073b 1282 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
AnnaBridge 143:86740a56073b 1283
AnnaBridge 143:86740a56073b 1284 /** @brief Macro to get the I2C3 clock source.
AnnaBridge 143:86740a56073b 1285 * @retval The clock source can be one of the following values:
AnnaBridge 143:86740a56073b 1286 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
AnnaBridge 143:86740a56073b 1287 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
AnnaBridge 143:86740a56073b 1288 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
AnnaBridge 143:86740a56073b 1289 */
AnnaBridge 143:86740a56073b 1290 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
AnnaBridge 143:86740a56073b 1291
AnnaBridge 143:86740a56073b 1292 #endif /* STM32L071xx || STM32L081xx || */
AnnaBridge 143:86740a56073b 1293 /* STM32L072xx || STM32L082xx || */
AnnaBridge 143:86740a56073b 1294 /* STM32L073xx || STM32L083xx || */
AnnaBridge 143:86740a56073b 1295
AnnaBridge 143:86740a56073b 1296 /** @brief Macro to configure the USART1 clock (USART1CLK).
AnnaBridge 143:86740a56073b 1297 *
AnnaBridge 143:86740a56073b 1298 * @param __USART1_CLKSOURCE__: specifies the USART1 clock source.
AnnaBridge 143:86740a56073b 1299 * This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1300 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
AnnaBridge 143:86740a56073b 1301 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
AnnaBridge 143:86740a56073b 1302 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
AnnaBridge 143:86740a56073b 1303 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
AnnaBridge 143:86740a56073b 1304 * @retval None
AnnaBridge 143:86740a56073b 1305 */
AnnaBridge 143:86740a56073b 1306 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
AnnaBridge 143:86740a56073b 1307 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
AnnaBridge 143:86740a56073b 1308
AnnaBridge 143:86740a56073b 1309 /** @brief Macro to get the USART1 clock source.
AnnaBridge 143:86740a56073b 1310 * @retval The clock source can be one of the following values:
AnnaBridge 143:86740a56073b 1311 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
AnnaBridge 143:86740a56073b 1312 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
AnnaBridge 143:86740a56073b 1313 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
AnnaBridge 143:86740a56073b 1314 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
AnnaBridge 143:86740a56073b 1315 */
AnnaBridge 143:86740a56073b 1316 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
AnnaBridge 143:86740a56073b 1317
AnnaBridge 143:86740a56073b 1318 /** @brief Macro to configure the USART2 clock (USART2CLK).
AnnaBridge 143:86740a56073b 1319 *
AnnaBridge 143:86740a56073b 1320 * @param __USART2_CLKSOURCE__: specifies the USART2 clock source.
AnnaBridge 143:86740a56073b 1321 * This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1322 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
AnnaBridge 143:86740a56073b 1323 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
AnnaBridge 143:86740a56073b 1324 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
AnnaBridge 143:86740a56073b 1325 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
AnnaBridge 143:86740a56073b 1326 * @retval None
AnnaBridge 143:86740a56073b 1327 */
AnnaBridge 143:86740a56073b 1328 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
AnnaBridge 143:86740a56073b 1329 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
AnnaBridge 143:86740a56073b 1330
AnnaBridge 143:86740a56073b 1331 /** @brief Macro to get the USART2 clock source.
AnnaBridge 143:86740a56073b 1332 * @retval The clock source can be one of the following values:
AnnaBridge 143:86740a56073b 1333 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
AnnaBridge 143:86740a56073b 1334 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
AnnaBridge 143:86740a56073b 1335 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
AnnaBridge 143:86740a56073b 1336 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
AnnaBridge 143:86740a56073b 1337 */
AnnaBridge 143:86740a56073b 1338 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
AnnaBridge 143:86740a56073b 1339
AnnaBridge 143:86740a56073b 1340 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
AnnaBridge 143:86740a56073b 1341 *
AnnaBridge 143:86740a56073b 1342 * @param __LPUART1_CLKSOURCE__: specifies the LPUART1 clock source.
AnnaBridge 143:86740a56073b 1343 * This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1344 * @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
AnnaBridge 143:86740a56073b 1345 * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
AnnaBridge 143:86740a56073b 1346 * @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock
AnnaBridge 143:86740a56073b 1347 * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
AnnaBridge 143:86740a56073b 1348 * @retval None
AnnaBridge 143:86740a56073b 1349 */
AnnaBridge 143:86740a56073b 1350 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
AnnaBridge 143:86740a56073b 1351 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
AnnaBridge 143:86740a56073b 1352
AnnaBridge 143:86740a56073b 1353 /** @brief Macro to get the LPUART1 clock source.
AnnaBridge 143:86740a56073b 1354 * @retval The clock source can be one of the following values:
AnnaBridge 143:86740a56073b 1355 * @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
AnnaBridge 143:86740a56073b 1356 * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
AnnaBridge 143:86740a56073b 1357 * @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock
AnnaBridge 143:86740a56073b 1358 * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
AnnaBridge 143:86740a56073b 1359 */
AnnaBridge 143:86740a56073b 1360 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
AnnaBridge 143:86740a56073b 1361
AnnaBridge 143:86740a56073b 1362 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
AnnaBridge 143:86740a56073b 1363 *
AnnaBridge 143:86740a56073b 1364 * @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.
AnnaBridge 143:86740a56073b 1365 * This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1366 * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
AnnaBridge 143:86740a56073b 1367 * @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPTIM1 clock
AnnaBridge 143:86740a56073b 1368 * @arg RCC_LPTIM1CLKSOURCE_HSI : LSI selected as LPTIM1 clock
AnnaBridge 143:86740a56073b 1369 * @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPTIM1 clock
AnnaBridge 143:86740a56073b 1370 * @retval None
AnnaBridge 143:86740a56073b 1371 */
AnnaBridge 143:86740a56073b 1372 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
AnnaBridge 143:86740a56073b 1373 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
AnnaBridge 143:86740a56073b 1374
AnnaBridge 143:86740a56073b 1375 /** @brief Macro to get the LPTIM1 clock source.
AnnaBridge 143:86740a56073b 1376 * @retval The clock source can be one of the following values:
AnnaBridge 143:86740a56073b 1377 * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPUART1 clock
AnnaBridge 143:86740a56073b 1378 * @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPUART1 clock
AnnaBridge 143:86740a56073b 1379 * @arg RCC_LPTIM1CLKSOURCE_HSI : System Clock selected as LPUART1 clock
AnnaBridge 143:86740a56073b 1380 * @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPUART1 clock
AnnaBridge 143:86740a56073b 1381 */
AnnaBridge 143:86740a56073b 1382 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
AnnaBridge 143:86740a56073b 1383
AnnaBridge 143:86740a56073b 1384 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge 143:86740a56073b 1385 /** @brief Macro to configure the USB clock (USBCLK).
AnnaBridge 143:86740a56073b 1386 * @param __USBCLKSource__: specifies the USB clock source.
AnnaBridge 143:86740a56073b 1387 * This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1388 * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
AnnaBridge 143:86740a56073b 1389 * @arg RCC_USBCLKSOURCE_PLL: PLL Clock selected as USB clock
AnnaBridge 143:86740a56073b 1390 */
AnnaBridge 143:86740a56073b 1391 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
AnnaBridge 143:86740a56073b 1392 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__USBCLKSource__))
AnnaBridge 143:86740a56073b 1393
AnnaBridge 143:86740a56073b 1394 /** @brief Macro to get the USB clock source.
AnnaBridge 143:86740a56073b 1395 * @retval The clock source can be one of the following values:
AnnaBridge 143:86740a56073b 1396 * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
AnnaBridge 143:86740a56073b 1397 * @arg RCC_USBCLKSOURCE_PLL: PLL Clock selected as USB clock
AnnaBridge 143:86740a56073b 1398 */
AnnaBridge 143:86740a56073b 1399 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
AnnaBridge 143:86740a56073b 1400
AnnaBridge 143:86740a56073b 1401 /** @brief Macro to configure the RNG clock (RNGCLK).
AnnaBridge 143:86740a56073b 1402 * @param __RNGCLKSource__: specifies the USB clock source.
AnnaBridge 143:86740a56073b 1403 * This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1404 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
AnnaBridge 143:86740a56073b 1405 * @arg RCC_RNGCLKSOURCE_PLLCLK: PLL Clock selected as RNG clock
AnnaBridge 143:86740a56073b 1406 */
AnnaBridge 143:86740a56073b 1407 #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
AnnaBridge 143:86740a56073b 1408 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__RNGCLKSource__))
AnnaBridge 143:86740a56073b 1409
AnnaBridge 143:86740a56073b 1410 /** @brief Macro to get the RNG clock source.
AnnaBridge 143:86740a56073b 1411 * @retval The clock source can be one of the following values:
AnnaBridge 143:86740a56073b 1412 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
AnnaBridge 143:86740a56073b 1413 * @arg RCC_RNGCLKSOURCE_PLLCLK: PLL Clock selected as RNG clock
AnnaBridge 143:86740a56073b 1414 */
AnnaBridge 143:86740a56073b 1415 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
AnnaBridge 143:86740a56073b 1416
AnnaBridge 143:86740a56073b 1417 /** @brief macro to select the HSI48M clock source
AnnaBridge 143:86740a56073b 1418 * @note This macro can be replaced by either __HAL_RCC_RNG_CONFIG or
AnnaBridge 143:86740a56073b 1419 * __HAL_RCC_USB_CONFIG to configure respectively RNG or UBS clock sources.
AnnaBridge 143:86740a56073b 1420 *
AnnaBridge 143:86740a56073b 1421 * @param __HSI48MCLKSource__: specifies the HSI48M clock source dedicated for
AnnaBridge 143:86740a56073b 1422 * USB an RNG peripherals.
AnnaBridge 143:86740a56073b 1423 * This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1424 * @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output.
AnnaBridge 143:86740a56073b 1425 * @arg RCC_HSI48M_HSI48: 48MHZ issued from internal HSI48 oscillator.
AnnaBridge 143:86740a56073b 1426 */
AnnaBridge 143:86740a56073b 1427 #define __HAL_RCC_HSI48M_CONFIG(__HSI48MCLKSource__) \
AnnaBridge 143:86740a56073b 1428 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__HSI48MCLKSource__))
AnnaBridge 143:86740a56073b 1429
AnnaBridge 143:86740a56073b 1430 /** @brief macro to get the HSI48M clock source.
AnnaBridge 143:86740a56073b 1431 * @note This macro can be replaced by either __HAL_RCC_GET_RNG_SOURCE or
AnnaBridge 143:86740a56073b 1432 * __HAL_RCC_GET_USB_SOURCE to get respectively RNG or UBS clock sources.
AnnaBridge 143:86740a56073b 1433 * @retval The clock source can be one of the following values:
AnnaBridge 143:86740a56073b 1434 * @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output.
AnnaBridge 143:86740a56073b 1435 * @arg RCC_HSI48M_HSI48: 48MHZ issued from internal HSI48 oscillator.
AnnaBridge 143:86740a56073b 1436 */
AnnaBridge 143:86740a56073b 1437 #define __HAL_RCC_GET_HSI48M_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
AnnaBridge 143:86740a56073b 1438 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
AnnaBridge 143:86740a56073b 1439
AnnaBridge 143:86740a56073b 1440 /**
AnnaBridge 143:86740a56073b 1441 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
AnnaBridge 143:86740a56073b 1442 * in STOP mode to be quickly available as kernel clock for USART and I2C.
AnnaBridge 143:86740a56073b 1443 * @note The Enable of this function has not effect on the HSION bit.
AnnaBridge 143:86740a56073b 1444 * @retval None
AnnaBridge 143:86740a56073b 1445 */
AnnaBridge 143:86740a56073b 1446 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
AnnaBridge 143:86740a56073b 1447 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
AnnaBridge 143:86740a56073b 1448
AnnaBridge 143:86740a56073b 1449 /**
AnnaBridge 143:86740a56073b 1450 * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
AnnaBridge 143:86740a56073b 1451 * @param __RCC_LSEDrive__: specifies the new state of the LSE drive capability.
AnnaBridge 143:86740a56073b 1452 * This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1453 * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
AnnaBridge 143:86740a56073b 1454 * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
AnnaBridge 143:86740a56073b 1455 * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
AnnaBridge 143:86740a56073b 1456 * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
AnnaBridge 143:86740a56073b 1457 * @retval None
AnnaBridge 143:86740a56073b 1458 */
AnnaBridge 143:86740a56073b 1459 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDrive__) (MODIFY_REG(RCC->CSR,\
AnnaBridge 143:86740a56073b 1460 RCC_CSR_LSEDRV, (uint32_t)(__RCC_LSEDrive__) ))
AnnaBridge 143:86740a56073b 1461
AnnaBridge 143:86740a56073b 1462 /**
AnnaBridge 143:86740a56073b 1463 * @brief Macro to configures the wake up from stop clock.
AnnaBridge 143:86740a56073b 1464 * @param __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop
AnnaBridge 143:86740a56073b 1465 * This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1466 * @arg RCC_STOP_WAKEUPCLOCK_MSI: MSI selected as system clock source
AnnaBridge 143:86740a56073b 1467 * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
AnnaBridge 143:86740a56073b 1468 * @retval None
AnnaBridge 143:86740a56073b 1469 */
AnnaBridge 143:86740a56073b 1470 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) (MODIFY_REG(RCC->CFGR,\
AnnaBridge 143:86740a56073b 1471 RCC_CFGR_STOPWUCK, (uint32_t)(__RCC_STOPWUCLK__) ))
AnnaBridge 143:86740a56073b 1472
AnnaBridge 143:86740a56073b 1473 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge 143:86740a56073b 1474 /**
AnnaBridge 143:86740a56073b 1475 * @brief Enables the specified CRS interrupts.
AnnaBridge 143:86740a56073b 1476 * @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
AnnaBridge 143:86740a56073b 1477 * This parameter can be any combination of the following values:
AnnaBridge 143:86740a56073b 1478 * @arg RCC_CRS_IT_SYNCOK
AnnaBridge 143:86740a56073b 1479 * @arg RCC_CRS_IT_SYNCWARN
AnnaBridge 143:86740a56073b 1480 * @arg RCC_CRS_IT_ERR
AnnaBridge 143:86740a56073b 1481 * @arg RCC_CRS_IT_ESYNC
AnnaBridge 143:86740a56073b 1482 * @retval None
AnnaBridge 143:86740a56073b 1483 */
AnnaBridge 143:86740a56073b 1484 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
AnnaBridge 143:86740a56073b 1485
AnnaBridge 143:86740a56073b 1486 /**
AnnaBridge 143:86740a56073b 1487 * @brief Disables the specified CRS interrupts.
AnnaBridge 143:86740a56073b 1488 * @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
AnnaBridge 143:86740a56073b 1489 * This parameter can be any combination of the following values:
AnnaBridge 143:86740a56073b 1490 * @arg RCC_CRS_IT_SYNCOK
AnnaBridge 143:86740a56073b 1491 * @arg RCC_CRS_IT_SYNCWARN
AnnaBridge 143:86740a56073b 1492 * @arg RCC_CRS_IT_ERR
AnnaBridge 143:86740a56073b 1493 * @arg RCC_CRS_IT_ESYNC
AnnaBridge 143:86740a56073b 1494 * @retval None
AnnaBridge 143:86740a56073b 1495 */
AnnaBridge 143:86740a56073b 1496 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR,(__INTERRUPT__))
AnnaBridge 143:86740a56073b 1497
AnnaBridge 143:86740a56073b 1498 /** @brief Check the CRS interrupt has occurred or not.
AnnaBridge 143:86740a56073b 1499 * @param __INTERRUPT__: specifies the CRS interrupt source to check.
AnnaBridge 143:86740a56073b 1500 * This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1501 * @arg RCC_CRS_IT_SYNCOK
AnnaBridge 143:86740a56073b 1502 * @arg RCC_CRS_IT_SYNCWARN
AnnaBridge 143:86740a56073b 1503 * @arg RCC_CRS_IT_ERR
AnnaBridge 143:86740a56073b 1504 * @arg RCC_CRS_IT_ESYNC
AnnaBridge 143:86740a56073b 1505 * @retval The new state of __INTERRUPT__ (SET or RESET).
AnnaBridge 143:86740a56073b 1506 */
AnnaBridge 143:86740a56073b 1507 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
AnnaBridge 143:86740a56073b 1508
AnnaBridge 143:86740a56073b 1509 /** @brief Clear the CRS interrupt pending bits
AnnaBridge 143:86740a56073b 1510 * bits to clear the selected interrupt pending bits.
AnnaBridge 143:86740a56073b 1511 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
AnnaBridge 143:86740a56073b 1512 * This parameter can be any combination of the following values:
AnnaBridge 143:86740a56073b 1513 * @arg RCC_CRS_IT_SYNCOK
AnnaBridge 143:86740a56073b 1514 * @arg RCC_CRS_IT_SYNCWARN
AnnaBridge 143:86740a56073b 1515 * @arg RCC_CRS_IT_ERR
AnnaBridge 143:86740a56073b 1516 * @arg RCC_CRS_IT_ESYNC
AnnaBridge 143:86740a56073b 1517 * @arg RCC_CRS_IT_TRIMOVF
AnnaBridge 143:86740a56073b 1518 * @arg RCC_CRS_IT_SYNCERR
AnnaBridge 143:86740a56073b 1519 * @arg RCC_CRS_IT_SYNCMISS
AnnaBridge 143:86740a56073b 1520 */
AnnaBridge 143:86740a56073b 1521 /* CRS IT Error Mask */
AnnaBridge 143:86740a56073b 1522 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
AnnaBridge 143:86740a56073b 1523
AnnaBridge 143:86740a56073b 1524 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \
AnnaBridge 143:86740a56073b 1525 (CRS->ICR = (__INTERRUPT__)))
AnnaBridge 143:86740a56073b 1526
AnnaBridge 143:86740a56073b 1527 /**
AnnaBridge 143:86740a56073b 1528 * @brief Checks whether the specified CRS flag is set or not.
AnnaBridge 143:86740a56073b 1529 * @param __FLAG__: specifies the flag to check.
AnnaBridge 143:86740a56073b 1530 * This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1531 * @arg RCC_CRS_FLAG_SYNCOK
AnnaBridge 143:86740a56073b 1532 * @arg RCC_CRS_FLAG_SYNCWARN
AnnaBridge 143:86740a56073b 1533 * @arg RCC_CRS_FLAG_ERR
AnnaBridge 143:86740a56073b 1534 * @arg RCC_CRS_FLAG_ESYNC
AnnaBridge 143:86740a56073b 1535 * @arg RCC_CRS_FLAG_TRIMOVF
AnnaBridge 143:86740a56073b 1536 * @arg RCC_CRS_FLAG_SYNCERR
AnnaBridge 143:86740a56073b 1537 * @arg RCC_CRS_FLAG_SYNCMISS
AnnaBridge 143:86740a56073b 1538 * @retval The new state of _FLAG_ (TRUE or FALSE).
AnnaBridge 143:86740a56073b 1539 */
AnnaBridge 143:86740a56073b 1540 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) ((CRS->ISR & (__FLAG__)) == (__FLAG__))
AnnaBridge 143:86740a56073b 1541
AnnaBridge 143:86740a56073b 1542 /**
AnnaBridge 143:86740a56073b 1543 * @brief Clears the CRS specified FLAG.
AnnaBridge 143:86740a56073b 1544 * @param _FLAG_: specifies the flag to clear.
AnnaBridge 143:86740a56073b 1545 * This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1546 * @arg RCC_CRS_FLAG_SYNCOK
AnnaBridge 143:86740a56073b 1547 * @arg RCC_CRS_FLAG_SYNCWARN
AnnaBridge 143:86740a56073b 1548 * @arg RCC_CRS_FLAG_ERR
AnnaBridge 143:86740a56073b 1549 * @arg RCC_CRS_FLAG_ESYNC
AnnaBridge 143:86740a56073b 1550 * @arg RCC_CRS_FLAG_TRIMOVF
AnnaBridge 143:86740a56073b 1551 * @arg RCC_CRS_FLAG_SYNCERR
AnnaBridge 143:86740a56073b 1552 * @arg RCC_CRS_FLAG_SYNCMISS
AnnaBridge 143:86740a56073b 1553 * @retval None
AnnaBridge 143:86740a56073b 1554 */
AnnaBridge 143:86740a56073b 1555
AnnaBridge 143:86740a56073b 1556 /* CRS Flag Error Mask */
AnnaBridge 143:86740a56073b 1557 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
AnnaBridge 143:86740a56073b 1558
AnnaBridge 143:86740a56073b 1559 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \
AnnaBridge 143:86740a56073b 1560 (CRS->ICR = (__FLAG__)))
AnnaBridge 143:86740a56073b 1561
AnnaBridge 143:86740a56073b 1562
AnnaBridge 143:86740a56073b 1563 /**
AnnaBridge 143:86740a56073b 1564 * @brief Enables the oscillator clock for frequency error counter.
AnnaBridge 143:86740a56073b 1565 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
AnnaBridge 143:86740a56073b 1566 * @retval None
AnnaBridge 143:86740a56073b 1567 */
AnnaBridge 143:86740a56073b 1568 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
AnnaBridge 143:86740a56073b 1569
AnnaBridge 143:86740a56073b 1570 /**
AnnaBridge 143:86740a56073b 1571 * @brief Disables the oscillator clock for frequency error counter.
AnnaBridge 143:86740a56073b 1572 * @retval None
AnnaBridge 143:86740a56073b 1573 */
AnnaBridge 143:86740a56073b 1574 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR,CRS_CR_CEN)
AnnaBridge 143:86740a56073b 1575
AnnaBridge 143:86740a56073b 1576 /**
AnnaBridge 143:86740a56073b 1577 * @brief Enables the automatic hardware adjustment of TRIM bits.
AnnaBridge 143:86740a56073b 1578 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
AnnaBridge 143:86740a56073b 1579 * @retval None
AnnaBridge 143:86740a56073b 1580 */
AnnaBridge 143:86740a56073b 1581 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
AnnaBridge 143:86740a56073b 1582
AnnaBridge 143:86740a56073b 1583 /**
AnnaBridge 143:86740a56073b 1584 * @brief Enables or disables the automatic hardware adjustment of TRIM bits.
AnnaBridge 143:86740a56073b 1585 * @retval None
AnnaBridge 143:86740a56073b 1586 */
AnnaBridge 143:86740a56073b 1587 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR,CRS_CR_AUTOTRIMEN)
AnnaBridge 143:86740a56073b 1588
AnnaBridge 143:86740a56073b 1589 /**
AnnaBridge 143:86740a56073b 1590 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
AnnaBridge 143:86740a56073b 1591 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
AnnaBridge 143:86740a56073b 1592 * of the synchronization source after prescaling. It is then decreased by one in order to
AnnaBridge 143:86740a56073b 1593 * reach the expected synchronization on the zero value. The formula is the following:
AnnaBridge 143:86740a56073b 1594 * RELOAD = (fTARGET / fSYNC) -1
AnnaBridge 143:86740a56073b 1595 * @param __FTARGET__ Target frequency (value in Hz)
AnnaBridge 143:86740a56073b 1596 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
AnnaBridge 143:86740a56073b 1597 * @retval None
AnnaBridge 143:86740a56073b 1598 */
AnnaBridge 143:86740a56073b 1599 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1)
AnnaBridge 143:86740a56073b 1600
AnnaBridge 143:86740a56073b 1601 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
AnnaBridge 143:86740a56073b 1602
AnnaBridge 143:86740a56073b 1603 #if defined(STM32L073xx) || defined(STM32L083xx) || \
AnnaBridge 143:86740a56073b 1604 defined(STM32L072xx) || defined(STM32L082xx) || \
AnnaBridge 143:86740a56073b 1605 defined(STM32L071xx) || defined(STM32L081xx)
AnnaBridge 143:86740a56073b 1606 /** @brief Enable or disable the HSI OUT .
AnnaBridge 143:86740a56073b 1607 * @note After reset, the HSI output is not available
AnnaBridge 143:86740a56073b 1608 */
AnnaBridge 143:86740a56073b 1609
AnnaBridge 143:86740a56073b 1610 #define __HAL_RCC_HSI_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIOUTEN)
AnnaBridge 143:86740a56073b 1611 #define __HAL_RCC_HSI_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN)
AnnaBridge 143:86740a56073b 1612
AnnaBridge 143:86740a56073b 1613 #endif /* STM32L071xx || STM32L081xx || */
AnnaBridge 143:86740a56073b 1614 /* STM32L072xx || STM32L082xx || */
AnnaBridge 143:86740a56073b 1615 /* STM32L073xx || STM32L083xx */
AnnaBridge 143:86740a56073b 1616
AnnaBridge 143:86740a56073b 1617 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) ||\
AnnaBridge 143:86740a56073b 1618 defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx)
AnnaBridge 143:86740a56073b 1619
AnnaBridge 143:86740a56073b 1620 /**
AnnaBridge 143:86740a56073b 1621 * @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
AnnaBridge 143:86740a56073b 1622 * @note After enabling the HSI48, the application software should wait on
AnnaBridge 143:86740a56073b 1623 * HSI48RDY flag to be set indicating that HSI48 clock is stable and can
AnnaBridge 143:86740a56073b 1624 * be used to clock the USB.
AnnaBridge 143:86740a56073b 1625 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge 143:86740a56073b 1626 */
AnnaBridge 143:86740a56073b 1627 #define __HAL_RCC_HSI48_ENABLE() do { SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
AnnaBridge 143:86740a56073b 1628 RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; \
AnnaBridge 143:86740a56073b 1629 SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENREF_HSI48); \
AnnaBridge 143:86740a56073b 1630 } while (0)
AnnaBridge 143:86740a56073b 1631 #define __HAL_RCC_HSI48_DISABLE() do { CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
AnnaBridge 143:86740a56073b 1632 SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENREF_HSI48)); \
AnnaBridge 143:86740a56073b 1633 } while (0)
AnnaBridge 143:86740a56073b 1634 /** @brief Enable or disable the HSI48M DIV6 OUT .
AnnaBridge 143:86740a56073b 1635 * @note After reset, the HSI48Mhz (divided by 6) output is not available
AnnaBridge 143:86740a56073b 1636 */
AnnaBridge 143:86740a56073b 1637
AnnaBridge 143:86740a56073b 1638 #define __HAL_RCC_HSI48M_DIV6_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
AnnaBridge 143:86740a56073b 1639 #define __HAL_RCC_HSI48M_DIV6_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
AnnaBridge 143:86740a56073b 1640
AnnaBridge 143:86740a56073b 1641 #endif /* STM32L071xx || STM32L081xx || */
AnnaBridge 143:86740a56073b 1642 /* STM32L072xx || STM32L082xx || */
AnnaBridge 143:86740a56073b 1643 /* STM32L073xx || STM32L083xx */
AnnaBridge 143:86740a56073b 1644
AnnaBridge 143:86740a56073b 1645 /**
AnnaBridge 143:86740a56073b 1646 * @}
AnnaBridge 143:86740a56073b 1647 */
AnnaBridge 143:86740a56073b 1648
AnnaBridge 143:86740a56073b 1649 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
AnnaBridge 143:86740a56073b 1650 * @{
AnnaBridge 143:86740a56073b 1651 */
AnnaBridge 143:86740a56073b 1652
AnnaBridge 143:86740a56073b 1653 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
AnnaBridge 143:86740a56073b 1654
AnnaBridge 143:86740a56073b 1655 * @{
AnnaBridge 143:86740a56073b 1656 */
AnnaBridge 143:86740a56073b 1657 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge 143:86740a56073b 1658 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge 143:86740a56073b 1659 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
AnnaBridge 143:86740a56073b 1660 void HAL_RCCEx_EnableLSECSS(void);
AnnaBridge 143:86740a56073b 1661 void HAL_RCCEx_DisableLSECSS(void);
AnnaBridge 143:86740a56073b 1662 void HAL_RCCEx_EnableLSECSS_IT(void);
AnnaBridge 143:86740a56073b 1663 void HAL_RCCEx_LSECSS_IRQHandler(void);
AnnaBridge 143:86740a56073b 1664 void HAL_RCCEx_LSECSS_Callback(void);
AnnaBridge 143:86740a56073b 1665
AnnaBridge 143:86740a56073b 1666 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge 143:86740a56073b 1667 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
AnnaBridge 143:86740a56073b 1668 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
AnnaBridge 143:86740a56073b 1669 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
AnnaBridge 143:86740a56073b 1670 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
AnnaBridge 143:86740a56073b 1671 void HAL_RCCEx_EnableHSI48_VREFINT(void);
AnnaBridge 143:86740a56073b 1672 void HAL_RCCEx_DisableHSI48_VREFINT(void);
AnnaBridge 143:86740a56073b 1673 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
AnnaBridge 143:86740a56073b 1674
AnnaBridge 143:86740a56073b 1675 /**
AnnaBridge 143:86740a56073b 1676 * @}
AnnaBridge 143:86740a56073b 1677 */
AnnaBridge 143:86740a56073b 1678 /**
AnnaBridge 143:86740a56073b 1679 * @}
AnnaBridge 143:86740a56073b 1680 */
AnnaBridge 143:86740a56073b 1681
AnnaBridge 143:86740a56073b 1682
AnnaBridge 143:86740a56073b 1683 /* Private macros ------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 1684 /** @addtogroup RCCEx_Private_Macros
AnnaBridge 143:86740a56073b 1685 * @{
AnnaBridge 143:86740a56073b 1686 */
AnnaBridge 143:86740a56073b 1687
AnnaBridge 143:86740a56073b 1688 #if defined (STM32L052xx) || defined(STM32L062xx)
AnnaBridge 143:86740a56073b 1689 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
AnnaBridge 143:86740a56073b 1690 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
AnnaBridge 143:86740a56073b 1691 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1))
AnnaBridge 143:86740a56073b 1692 #elif defined (STM32L053xx) || defined(STM32L063xx)
AnnaBridge 143:86740a56073b 1693 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
AnnaBridge 143:86740a56073b 1694 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
AnnaBridge 143:86740a56073b 1695 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LCD))
AnnaBridge 143:86740a56073b 1696 #elif defined (STM32L072xx) || defined(STM32L082xx)
AnnaBridge 143:86740a56073b 1697 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
AnnaBridge 143:86740a56073b 1698 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
AnnaBridge 143:86740a56073b 1699 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3 ))
AnnaBridge 143:86740a56073b 1700 #elif defined (STM32L073xx) || defined(STM32L083xx)
AnnaBridge 143:86740a56073b 1701 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
AnnaBridge 143:86740a56073b 1702 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
AnnaBridge 143:86740a56073b 1703 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3 | \
AnnaBridge 143:86740a56073b 1704 RCC_PERIPHCLK_LCD))
AnnaBridge 143:86740a56073b 1705 #endif
AnnaBridge 143:86740a56073b 1706
AnnaBridge 143:86740a56073b 1707 #if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx)
AnnaBridge 143:86740a56073b 1708 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= ( RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
AnnaBridge 143:86740a56073b 1709 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC | \
AnnaBridge 143:86740a56073b 1710 RCC_PERIPHCLK_LPTIM1))
AnnaBridge 143:86740a56073b 1711 #elif defined(STM32L051xx) || defined(STM32L061xx)
AnnaBridge 143:86740a56073b 1712 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
AnnaBridge 143:86740a56073b 1713 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
AnnaBridge 143:86740a56073b 1714 RCC_PERIPHCLK_LPTIM1))
AnnaBridge 143:86740a56073b 1715 #elif defined(STM32L071xx) || defined(STM32L081xx)
AnnaBridge 143:86740a56073b 1716 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
AnnaBridge 143:86740a56073b 1717 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
AnnaBridge 143:86740a56073b 1718 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3))
AnnaBridge 143:86740a56073b 1719 #endif
AnnaBridge 143:86740a56073b 1720
AnnaBridge 143:86740a56073b 1721 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
AnnaBridge 143:86740a56073b 1722 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
AnnaBridge 143:86740a56073b 1723 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
AnnaBridge 143:86740a56073b 1724 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
AnnaBridge 143:86740a56073b 1725
AnnaBridge 143:86740a56073b 1726
AnnaBridge 143:86740a56073b 1727 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
AnnaBridge 143:86740a56073b 1728 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
AnnaBridge 143:86740a56073b 1729 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
AnnaBridge 143:86740a56073b 1730 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
AnnaBridge 143:86740a56073b 1731
AnnaBridge 143:86740a56073b 1732 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
AnnaBridge 143:86740a56073b 1733 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
AnnaBridge 143:86740a56073b 1734 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
AnnaBridge 143:86740a56073b 1735 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
AnnaBridge 143:86740a56073b 1736
AnnaBridge 143:86740a56073b 1737 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
AnnaBridge 143:86740a56073b 1738 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
AnnaBridge 143:86740a56073b 1739 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
AnnaBridge 143:86740a56073b 1740
AnnaBridge 143:86740a56073b 1741 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
AnnaBridge 143:86740a56073b 1742 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
AnnaBridge 143:86740a56073b 1743 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
AnnaBridge 143:86740a56073b 1744
AnnaBridge 143:86740a56073b 1745 #define IS_RCC_USBCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
AnnaBridge 143:86740a56073b 1746 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL))
AnnaBridge 143:86740a56073b 1747
AnnaBridge 143:86740a56073b 1748 #define IS_RCC_RNGCLKSOURCE(_SOURCE_) (((_SOURCE_) == RCC_RNGCLKSOURCE_HSI48) || \
AnnaBridge 143:86740a56073b 1749 ((_SOURCE_) == RCC_RNGCLKSOURCE_PLLCLK))
AnnaBridge 143:86740a56073b 1750
AnnaBridge 143:86740a56073b 1751 #define IS_RCC_HSI48MCLKSOURCE(__HSI48MCLK__) (((__HSI48MCLK__) == RCC_HSI48M_PLL) || ((__HSI48MCLK__) == RCC_HSI48M_HSI48))
AnnaBridge 143:86740a56073b 1752
AnnaBridge 143:86740a56073b 1753 #if defined(STM32L073xx) || defined(STM32L083xx) || \
AnnaBridge 143:86740a56073b 1754 defined(STM32L072xx) || defined(STM32L082xx) || \
AnnaBridge 143:86740a56073b 1755 defined(STM32L071xx) || defined(STM32L081xx)
AnnaBridge 143:86740a56073b 1756
AnnaBridge 143:86740a56073b 1757 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \
AnnaBridge 143:86740a56073b 1758 ((__HSI__) == RCC_HSI_DIV4) || ((__HSI__) == RCC_HSI_OUTEN ))
AnnaBridge 143:86740a56073b 1759 #else
AnnaBridge 143:86740a56073b 1760 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \
AnnaBridge 143:86740a56073b 1761 ((__HSI__) == RCC_HSI_DIV4))
AnnaBridge 143:86740a56073b 1762 #endif
AnnaBridge 143:86740a56073b 1763
AnnaBridge 143:86740a56073b 1764 #define IS_RCC_LPTIMCLK(__LPTIMCLK_) (((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_PCLK) || \
AnnaBridge 143:86740a56073b 1765 ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSI) || \
AnnaBridge 143:86740a56073b 1766 ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_HSI) || \
AnnaBridge 143:86740a56073b 1767 ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSE))
AnnaBridge 143:86740a56073b 1768
AnnaBridge 143:86740a56073b 1769 #define IS_RCC_STOPWAKEUP_CLOCK(__SOURCE__) (((__SOURCE__) == RCC_StopWakeUpClock_MSI) || \
AnnaBridge 143:86740a56073b 1770 ((__SOURCE__) == RCC_StopWakeUpClock_HSI))
AnnaBridge 143:86740a56073b 1771
AnnaBridge 143:86740a56073b 1772 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || ((__SOURCE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
AnnaBridge 143:86740a56073b 1773 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || ((__SOURCE__) == RCC_LSEDRIVE_HIGH))
AnnaBridge 143:86740a56073b 1774
AnnaBridge 143:86740a56073b 1775 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
AnnaBridge 143:86740a56073b 1776 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) ||\
AnnaBridge 143:86740a56073b 1777 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
AnnaBridge 143:86740a56073b 1778
AnnaBridge 143:86740a56073b 1779 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) ||\
AnnaBridge 143:86740a56073b 1780 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
AnnaBridge 143:86740a56073b 1781 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
AnnaBridge 143:86740a56073b 1782 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
AnnaBridge 143:86740a56073b 1783
AnnaBridge 143:86740a56073b 1784 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
AnnaBridge 143:86740a56073b 1785 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
AnnaBridge 143:86740a56073b 1786
AnnaBridge 143:86740a56073b 1787 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
AnnaBridge 143:86740a56073b 1788
AnnaBridge 143:86740a56073b 1789 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
AnnaBridge 143:86740a56073b 1790
AnnaBridge 143:86740a56073b 1791 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
AnnaBridge 143:86740a56073b 1792
AnnaBridge 143:86740a56073b 1793 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
AnnaBridge 143:86740a56073b 1794 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
AnnaBridge 143:86740a56073b 1795
AnnaBridge 143:86740a56073b 1796 /**
AnnaBridge 143:86740a56073b 1797 * @}
AnnaBridge 143:86740a56073b 1798 */
AnnaBridge 143:86740a56073b 1799
AnnaBridge 143:86740a56073b 1800
AnnaBridge 143:86740a56073b 1801 /**
AnnaBridge 143:86740a56073b 1802 * @}
AnnaBridge 143:86740a56073b 1803 */
AnnaBridge 143:86740a56073b 1804
AnnaBridge 143:86740a56073b 1805 /**
AnnaBridge 143:86740a56073b 1806 * @}
AnnaBridge 143:86740a56073b 1807 */
AnnaBridge 143:86740a56073b 1808
AnnaBridge 143:86740a56073b 1809 /**
AnnaBridge 143:86740a56073b 1810 * @}
AnnaBridge 143:86740a56073b 1811 */
AnnaBridge 143:86740a56073b 1812
AnnaBridge 143:86740a56073b 1813 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 1814 }
AnnaBridge 143:86740a56073b 1815 #endif
AnnaBridge 143:86740a56073b 1816
AnnaBridge 143:86740a56073b 1817 #endif /* __STM32L0xx_HAL_RCC_EX_H */
AnnaBridge 143:86740a56073b 1818
AnnaBridge 143:86740a56073b 1819 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
AnnaBridge 143:86740a56073b 1820