mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_L011K4/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_rcc.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.h@167:84c0a372a020

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	143:86740a56073b	1	/**
AnnaBridge	143:86740a56073b	2	******************************************************************************
AnnaBridge	143:86740a56073b	3	* @file stm32l0xx_hal_rcc.h
AnnaBridge	143:86740a56073b	4	* @author MCD Application Team
AnnaBridge	143:86740a56073b	5	* @brief Header file of RCC HAL module.
AnnaBridge	143:86740a56073b	6	******************************************************************************
AnnaBridge	143:86740a56073b	7	* @attention
AnnaBridge	143:86740a56073b	8	*
AnnaBridge	143:86740a56073b	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	143:86740a56073b	10	*
AnnaBridge	143:86740a56073b	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	143:86740a56073b	12	* are permitted provided that the following conditions are met:
AnnaBridge	143:86740a56073b	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	143:86740a56073b	14	* this list of conditions and the following disclaimer.
AnnaBridge	143:86740a56073b	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	143:86740a56073b	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	143:86740a56073b	17	* and/or other materials provided with the distribution.
AnnaBridge	143:86740a56073b	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	143:86740a56073b	19	* may be used to endorse or promote products derived from this software
AnnaBridge	143:86740a56073b	20	* without specific prior written permission.
AnnaBridge	143:86740a56073b	21	*
AnnaBridge	143:86740a56073b	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	143:86740a56073b	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	143:86740a56073b	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	143:86740a56073b	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	143:86740a56073b	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	143:86740a56073b	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	143:86740a56073b	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	143:86740a56073b	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	143:86740a56073b	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	143:86740a56073b	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	143:86740a56073b	32	*
AnnaBridge	143:86740a56073b	33	******************************************************************************
AnnaBridge	143:86740a56073b	34	*/
AnnaBridge	143:86740a56073b	35
AnnaBridge	143:86740a56073b	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	143:86740a56073b	37	#ifndef __STM32L0xx_HAL_RCC_H
AnnaBridge	143:86740a56073b	38	#define __STM32L0xx_HAL_RCC_H
AnnaBridge	143:86740a56073b	39
AnnaBridge	143:86740a56073b	40	#ifdef __cplusplus
AnnaBridge	143:86740a56073b	41	extern "C" {
AnnaBridge	143:86740a56073b	42	#endif
AnnaBridge	143:86740a56073b	43
AnnaBridge	143:86740a56073b	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	45	#include "stm32l0xx_hal_def.h"
AnnaBridge	143:86740a56073b	46
AnnaBridge	143:86740a56073b	47	/** @addtogroup STM32L0xx_HAL_Driver
AnnaBridge	143:86740a56073b	48	* @{
AnnaBridge	143:86740a56073b	49	*/
AnnaBridge	143:86740a56073b	50
AnnaBridge	167:84c0a372a020	51	/** @addtogroup RCC
AnnaBridge	167:84c0a372a020	52	* @{
AnnaBridge	167:84c0a372a020	53	*/
AnnaBridge	167:84c0a372a020	54
AnnaBridge	167:84c0a372a020	55	/** @addtogroup RCC_Private_Constants
AnnaBridge	167:84c0a372a020	56	* @{
AnnaBridge	167:84c0a372a020	57	*/
AnnaBridge	167:84c0a372a020	58
AnnaBridge	167:84c0a372a020	59	/** @defgroup RCC_Timeout RCC Timeout
AnnaBridge	167:84c0a372a020	60	* @{
AnnaBridge	167:84c0a372a020	61	*/
AnnaBridge	167:84c0a372a020	62
AnnaBridge	167:84c0a372a020	63	/* Disable Backup domain write protection state change timeout */
AnnaBridge	167:84c0a372a020	64	#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */
AnnaBridge	167:84c0a372a020	65	/* LSE state change timeout */
AnnaBridge	167:84c0a372a020	66	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
AnnaBridge	167:84c0a372a020	67	#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
AnnaBridge	167:84c0a372a020	68	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
AnnaBridge	167:84c0a372a020	69	#define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
AnnaBridge	167:84c0a372a020	70	#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
AnnaBridge	167:84c0a372a020	71	#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
AnnaBridge	167:84c0a372a020	72	#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
AnnaBridge	167:84c0a372a020	73	#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
AnnaBridge	167:84c0a372a020	74	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	167:84c0a372a020	75	#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
AnnaBridge	167:84c0a372a020	76	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	167:84c0a372a020	77	/**
AnnaBridge	167:84c0a372a020	78	* @}
AnnaBridge	167:84c0a372a020	79	*/
AnnaBridge	167:84c0a372a020	80
AnnaBridge	167:84c0a372a020	81
AnnaBridge	167:84c0a372a020	82	/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
AnnaBridge	167:84c0a372a020	83	* @brief RCC registers bit address in the alias region
AnnaBridge	167:84c0a372a020	84	* @{
AnnaBridge	167:84c0a372a020	85	*/
AnnaBridge	167:84c0a372a020	86	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
AnnaBridge	167:84c0a372a020	87	/* --- CR Register ---*/
AnnaBridge	167:84c0a372a020	88	/* Alias word address of HSION bit */
AnnaBridge	167:84c0a372a020	89	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
AnnaBridge	167:84c0a372a020	90	/* --- CFGR Register ---*/
AnnaBridge	167:84c0a372a020	91	/* Alias word address of I2SSRC bit */
AnnaBridge	167:84c0a372a020	92	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
AnnaBridge	167:84c0a372a020	93	/* --- CSR Register ---*/
AnnaBridge	167:84c0a372a020	94	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
AnnaBridge	167:84c0a372a020	95
AnnaBridge	167:84c0a372a020	96	/* CR register byte 3 (Bits[23:16]) base address */
AnnaBridge	167:84c0a372a020	97	#define RCC_CR_BYTE2_ADDRESS (0x40023802U)
AnnaBridge	167:84c0a372a020	98
AnnaBridge	167:84c0a372a020	99	/* CIER register byte 0 (Bits[0:8]) base address */
AnnaBridge	167:84c0a372a020	100	#define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10U + 0x00U))
AnnaBridge	167:84c0a372a020	101	/**
AnnaBridge	167:84c0a372a020	102	* @}
AnnaBridge	167:84c0a372a020	103	*/
AnnaBridge	167:84c0a372a020	104
AnnaBridge	167:84c0a372a020	105
AnnaBridge	167:84c0a372a020	106	/* Defines used for Flags */
AnnaBridge	167:84c0a372a020	107	#define CR_REG_INDEX ((uint8_t)1)
AnnaBridge	167:84c0a372a020	108	#define CSR_REG_INDEX ((uint8_t)2)
AnnaBridge	167:84c0a372a020	109	#define CRRCR_REG_INDEX ((uint8_t)3)
AnnaBridge	167:84c0a372a020	110
AnnaBridge	167:84c0a372a020	111	#define RCC_FLAG_MASK ((uint8_t)0x1F)
AnnaBridge	167:84c0a372a020	112
AnnaBridge	167:84c0a372a020	113	/**
AnnaBridge	167:84c0a372a020	114	* @}
AnnaBridge	167:84c0a372a020	115	*/
AnnaBridge	167:84c0a372a020	116
AnnaBridge	167:84c0a372a020	117	/** @addtogroup RCC_Private_Macros
AnnaBridge	143:86740a56073b	118	* @{
AnnaBridge	143:86740a56073b	119	*/
AnnaBridge	167:84c0a372a020	120	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	167:84c0a372a020	121	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
AnnaBridge	167:84c0a372a020	122	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
AnnaBridge	167:84c0a372a020	123	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
AnnaBridge	167:84c0a372a020	124	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) \|\| \
AnnaBridge	167:84c0a372a020	125	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
AnnaBridge	167:84c0a372a020	126	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
AnnaBridge	167:84c0a372a020	127	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI))
AnnaBridge	167:84c0a372a020	128
AnnaBridge	167:84c0a372a020	129	#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) \|\| ((__HSI48__) == RCC_HSI48_ON))
AnnaBridge	167:84c0a372a020	130	#else
AnnaBridge	167:84c0a372a020	131	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
AnnaBridge	167:84c0a372a020	132	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
AnnaBridge	167:84c0a372a020	133	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
AnnaBridge	167:84c0a372a020	134	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
AnnaBridge	167:84c0a372a020	135	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
AnnaBridge	167:84c0a372a020	136	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI))
AnnaBridge	167:84c0a372a020	137	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	167:84c0a372a020	138	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
AnnaBridge	167:84c0a372a020	139	((__SOURCE__) == RCC_PLLSOURCE_HSE))
AnnaBridge	167:84c0a372a020	140	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
AnnaBridge	167:84c0a372a020	141	((__HSE__) == RCC_HSE_BYPASS))
AnnaBridge	167:84c0a372a020	142	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
AnnaBridge	167:84c0a372a020	143	((__LSE__) == RCC_LSE_BYPASS))
AnnaBridge	167:84c0a372a020	144	#if defined(RCC_CR_HSIOUTEN)
AnnaBridge	167:84c0a372a020	145	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON) \|\| \
AnnaBridge	167:84c0a372a020	146	((__HSI__) == RCC_HSI_DIV4) \|\| ((__HSI__) == RCC_HSI_OUTEN ))
AnnaBridge	167:84c0a372a020	147	#else
AnnaBridge	167:84c0a372a020	148	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON) \|\| \
AnnaBridge	167:84c0a372a020	149	((__HSI__) == RCC_HSI_DIV4))
AnnaBridge	167:84c0a372a020	150	#endif /* RCC_CR_HSIOUTEN */
AnnaBridge	167:84c0a372a020	151	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
AnnaBridge	167:84c0a372a020	152	#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFF)
AnnaBridge	167:84c0a372a020	153	#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) \|\| \
AnnaBridge	167:84c0a372a020	154	((__RANGE__) == RCC_MSIRANGE_1) \|\| \
AnnaBridge	167:84c0a372a020	155	((__RANGE__) == RCC_MSIRANGE_2) \|\| \
AnnaBridge	167:84c0a372a020	156	((__RANGE__) == RCC_MSIRANGE_3) \|\| \
AnnaBridge	167:84c0a372a020	157	((__RANGE__) == RCC_MSIRANGE_4) \|\| \
AnnaBridge	167:84c0a372a020	158	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
AnnaBridge	167:84c0a372a020	159	((__RANGE__) == RCC_MSIRANGE_6))
AnnaBridge	167:84c0a372a020	160	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
AnnaBridge	167:84c0a372a020	161	#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) \|\| ((__MSI__) == RCC_MSI_ON))
AnnaBridge	167:84c0a372a020	162
AnnaBridge	167:84c0a372a020	163	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\| ((__PLL__) == RCC_PLL_OFF) \|\| \
AnnaBridge	167:84c0a372a020	164	((__PLL__) == RCC_PLL_ON))
AnnaBridge	167:84c0a372a020	165	#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) \|\| \
AnnaBridge	167:84c0a372a020	166	((__DIV__) == RCC_PLL_DIV3) \|\| ((__DIV__) == RCC_PLL_DIV4))
AnnaBridge	167:84c0a372a020	167
AnnaBridge	167:84c0a372a020	168	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3) \|\| ((__MUL__) == RCC_PLL_MUL4) \|\| \
AnnaBridge	167:84c0a372a020	169	((__MUL__) == RCC_PLL_MUL6) \|\| ((__MUL__) == RCC_PLL_MUL8) \|\| \
AnnaBridge	167:84c0a372a020	170	((__MUL__) == RCC_PLL_MUL12) \|\| ((__MUL__) == RCC_PLL_MUL16) \|\| \
AnnaBridge	167:84c0a372a020	171	((__MUL__) == RCC_PLL_MUL24) \|\| ((__MUL__) == RCC_PLL_MUL32) \|\| \
AnnaBridge	167:84c0a372a020	172	((__MUL__) == RCC_PLL_MUL48))
AnnaBridge	167:84c0a372a020	173	#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) \|\| \
AnnaBridge	167:84c0a372a020	174	(((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) \|\| \
AnnaBridge	167:84c0a372a020	175	(((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) \|\| \
AnnaBridge	167:84c0a372a020	176	(((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
AnnaBridge	167:84c0a372a020	177	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) \|\| \
AnnaBridge	167:84c0a372a020	178	((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
AnnaBridge	167:84c0a372a020	179	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
AnnaBridge	167:84c0a372a020	180	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
AnnaBridge	167:84c0a372a020	181	#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_MSI) \|\| \
AnnaBridge	167:84c0a372a020	182	((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
AnnaBridge	167:84c0a372a020	183	((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
AnnaBridge	167:84c0a372a020	184	((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
AnnaBridge	167:84c0a372a020	185	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
AnnaBridge	167:84c0a372a020	186	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
AnnaBridge	167:84c0a372a020	187	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
AnnaBridge	167:84c0a372a020	188	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
AnnaBridge	167:84c0a372a020	189	((__HCLK__) == RCC_SYSCLK_DIV512))
AnnaBridge	167:84c0a372a020	190	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
AnnaBridge	167:84c0a372a020	191	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
AnnaBridge	167:84c0a372a020	192	((__PCLK__) == RCC_HCLK_DIV16))
AnnaBridge	167:84c0a372a020	193	#if defined(STM32L031xx) \|\| defined(STM32L041xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \
AnnaBridge	167:84c0a372a020	194	\|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
AnnaBridge	167:84c0a372a020	195	#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO1) \|\| ((__MCO__) == RCC_MCO2) \|\| ((__MCO__) == RCC_MCO3))
AnnaBridge	167:84c0a372a020	196	#else
AnnaBridge	167:84c0a372a020	197	#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO1) \|\| ((__MCO__) == RCC_MCO2))
AnnaBridge	167:84c0a372a020	198
AnnaBridge	167:84c0a372a020	199	#endif
AnnaBridge	167:84c0a372a020	200	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) \|\| ((__DIV__) == RCC_MCODIV_2) \|\| \
AnnaBridge	167:84c0a372a020	201	((__DIV__) == RCC_MCODIV_4) \|\| ((__DIV__) == RCC_MCODIV_8) \|\| \
AnnaBridge	167:84c0a372a020	202	((__DIV__) == RCC_MCODIV_16))
AnnaBridge	167:84c0a372a020	203	#if defined(RCC_CFGR_MCOSEL_HSI48)
AnnaBridge	167:84c0a372a020	204	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
AnnaBridge	167:84c0a372a020	205	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
AnnaBridge	167:84c0a372a020	206	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
AnnaBridge	167:84c0a372a020	207	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \|\| \
AnnaBridge	167:84c0a372a020	208	((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
AnnaBridge	167:84c0a372a020	209	#else
AnnaBridge	167:84c0a372a020	210	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
AnnaBridge	167:84c0a372a020	211	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
AnnaBridge	167:84c0a372a020	212	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
AnnaBridge	167:84c0a372a020	213	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
AnnaBridge	167:84c0a372a020	214	#endif /* RCC_CFGR_MCOSEL_HSI48 */
AnnaBridge	167:84c0a372a020	215	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) \|\| \
AnnaBridge	167:84c0a372a020	216	((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
AnnaBridge	167:84c0a372a020	217	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
AnnaBridge	167:84c0a372a020	218	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) \|\| \
AnnaBridge	167:84c0a372a020	219	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) \|\| \
AnnaBridge	167:84c0a372a020	220	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) \|\| \
AnnaBridge	167:84c0a372a020	221	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
AnnaBridge	167:84c0a372a020	222
AnnaBridge	167:84c0a372a020	223	/**
AnnaBridge	167:84c0a372a020	224	* @}
AnnaBridge	167:84c0a372a020	225	*/
AnnaBridge	167:84c0a372a020	226
AnnaBridge	167:84c0a372a020	227	/* Exported types ------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	228
AnnaBridge	143:86740a56073b	229	/** @defgroup RCC_Exported_Types RCC Exported Types
AnnaBridge	143:86740a56073b	230	* @{
AnnaBridge	143:86740a56073b	231	*/
AnnaBridge	143:86740a56073b	232
AnnaBridge	167:84c0a372a020	233	/**
AnnaBridge	167:84c0a372a020	234	* @brief RCC PLL configuration structure definition
AnnaBridge	143:86740a56073b	235	*/
AnnaBridge	143:86740a56073b	236	typedef struct
AnnaBridge	143:86740a56073b	237	{
AnnaBridge	167:84c0a372a020	238	uint32_t PLLState; /*!< PLLState: The new state of the PLL.
AnnaBridge	167:84c0a372a020	239	This parameter can be a value of @ref RCC_PLL_Config */
AnnaBridge	143:86740a56073b	240
AnnaBridge	167:84c0a372a020	241	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
AnnaBridge	167:84c0a372a020	242	This parameter must be a value of @ref RCC_PLL_Clock_Source */
AnnaBridge	143:86740a56073b	243
AnnaBridge	167:84c0a372a020	244	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
AnnaBridge	167:84c0a372a020	245	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
AnnaBridge	143:86740a56073b	246
AnnaBridge	167:84c0a372a020	247	uint32_t PLLDIV; /*!< PLLDIV: Division factor for PLL VCO input clock
AnnaBridge	167:84c0a372a020	248	This parameter must be a value of @ref RCC_PLL_Division_Factor*/
AnnaBridge	167:84c0a372a020	249	} RCC_PLLInitTypeDef;
AnnaBridge	167:84c0a372a020	250
AnnaBridge	143:86740a56073b	251	/**
AnnaBridge	143:86740a56073b	252	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
AnnaBridge	143:86740a56073b	253	*/
AnnaBridge	143:86740a56073b	254	typedef struct
AnnaBridge	143:86740a56073b	255	{
AnnaBridge	167:84c0a372a020	256	uint32_t OscillatorType; /*!< The oscillators to be configured.
AnnaBridge	167:84c0a372a020	257	This parameter can be a value of @ref RCC_Oscillator_Type */
AnnaBridge	143:86740a56073b	258
AnnaBridge	167:84c0a372a020	259	uint32_t HSEState; /*!< The new state of the HSE.
AnnaBridge	167:84c0a372a020	260	This parameter can be a value of @ref RCC_HSE_Config */
AnnaBridge	143:86740a56073b	261
AnnaBridge	167:84c0a372a020	262	uint32_t LSEState; /*!< The new state of the LSE.
AnnaBridge	167:84c0a372a020	263	This parameter can be a value of @ref RCC_LSE_Config */
AnnaBridge	143:86740a56073b	264
AnnaBridge	167:84c0a372a020	265	uint32_t HSIState; /*!< The new state of the HSI.
AnnaBridge	167:84c0a372a020	266	This parameter can be a value of @ref RCC_HSI_Config */
AnnaBridge	143:86740a56073b	267
AnnaBridge	167:84c0a372a020	268	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge	167:84c0a372a020	269	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
AnnaBridge	167:84c0a372a020	270
AnnaBridge	167:84c0a372a020	271	uint32_t LSIState; /*!< The new state of the LSI.
AnnaBridge	167:84c0a372a020	272	This parameter can be a value of @ref RCC_LSI_Config */
AnnaBridge	143:86740a56073b	273
AnnaBridge	167:84c0a372a020	274	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	167:84c0a372a020	275	uint32_t HSI48State; /*!< The new state of the HSI48.
AnnaBridge	167:84c0a372a020	276	This parameter can be a value of @ref RCC_HSI48_Config */
AnnaBridge	143:86740a56073b	277
AnnaBridge	167:84c0a372a020	278	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	167:84c0a372a020	279	uint32_t MSIState; /*!< The new state of the MSI.
AnnaBridge	167:84c0a372a020	280	This parameter can be a value of @ref RCC_MSI_Config */
AnnaBridge	143:86740a56073b	281
AnnaBridge	167:84c0a372a020	282	uint32_t MSICalibrationValue; /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT).
AnnaBridge	167:84c0a372a020	283	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
AnnaBridge	143:86740a56073b	284
AnnaBridge	143:86740a56073b	285	uint32_t MSIClockRange; /*!< The MSI frequency range.
AnnaBridge	167:84c0a372a020	286	This parameter can be a value of @ref RCC_MSI_Clock_Range */
AnnaBridge	143:86740a56073b	287
AnnaBridge	167:84c0a372a020	288	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
AnnaBridge	143:86740a56073b	289
AnnaBridge	167:84c0a372a020	290	} RCC_OscInitTypeDef;
AnnaBridge	143:86740a56073b	291
AnnaBridge	143:86740a56073b	292	/**
AnnaBridge	143:86740a56073b	293	* @brief RCC System, AHB and APB busses clock configuration structure definition
AnnaBridge	143:86740a56073b	294	*/
AnnaBridge	143:86740a56073b	295	typedef struct
AnnaBridge	143:86740a56073b	296	{
AnnaBridge	143:86740a56073b	297	uint32_t ClockType; /*!< The clock to be configured.
AnnaBridge	143:86740a56073b	298	This parameter can be a value of @ref RCC_System_Clock_Type */
AnnaBridge	143:86740a56073b	299
AnnaBridge	143:86740a56073b	300	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
AnnaBridge	143:86740a56073b	301	This parameter can be a value of @ref RCC_System_Clock_Source */
AnnaBridge	143:86740a56073b	302
AnnaBridge	143:86740a56073b	303	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
AnnaBridge	143:86740a56073b	304	This parameter can be a value of @ref RCC_AHB_Clock_Source */
AnnaBridge	143:86740a56073b	305
AnnaBridge	143:86740a56073b	306	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge	143:86740a56073b	307	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge	143:86740a56073b	308
AnnaBridge	143:86740a56073b	309	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge	143:86740a56073b	310	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge	167:84c0a372a020	311	} RCC_ClkInitTypeDef;
AnnaBridge	143:86740a56073b	312
AnnaBridge	143:86740a56073b	313	/**
AnnaBridge	143:86740a56073b	314	* @}
AnnaBridge	143:86740a56073b	315	*/
AnnaBridge	143:86740a56073b	316
AnnaBridge	143:86740a56073b	317	/* Exported constants --------------------------------------------------------*/
AnnaBridge	143:86740a56073b	318	/** @defgroup RCC_Exported_Constants RCC Exported Constants
AnnaBridge	143:86740a56073b	319	* @{
AnnaBridge	143:86740a56073b	320	*/
AnnaBridge	143:86740a56073b	321
AnnaBridge	167:84c0a372a020	322	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
AnnaBridge	143:86740a56073b	323	* @{
AnnaBridge	143:86740a56073b	324	*/
AnnaBridge	143:86740a56073b	325
AnnaBridge	167:84c0a372a020	326	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /!< HSI clock selected as PLL entry clock source /
AnnaBridge	167:84c0a372a020	327	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
AnnaBridge	143:86740a56073b	328
AnnaBridge	143:86740a56073b	329	/**
AnnaBridge	143:86740a56073b	330	* @}
AnnaBridge	143:86740a56073b	331	*/
AnnaBridge	143:86740a56073b	332
AnnaBridge	167:84c0a372a020	333	/** @defgroup RCC_Oscillator_Type Oscillator Type
AnnaBridge	143:86740a56073b	334	* @{
AnnaBridge	143:86740a56073b	335	*/
AnnaBridge	167:84c0a372a020	336	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
AnnaBridge	167:84c0a372a020	337	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
AnnaBridge	167:84c0a372a020	338	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
AnnaBridge	167:84c0a372a020	339	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
AnnaBridge	167:84c0a372a020	340	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
AnnaBridge	167:84c0a372a020	341	#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010)
AnnaBridge	167:84c0a372a020	342	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	167:84c0a372a020	343	#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
AnnaBridge	167:84c0a372a020	344	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	143:86740a56073b	345	/**
AnnaBridge	143:86740a56073b	346	* @}
AnnaBridge	143:86740a56073b	347	*/
AnnaBridge	143:86740a56073b	348
AnnaBridge	167:84c0a372a020	349	/** @defgroup RCC_HSE_Config HSE Config
AnnaBridge	143:86740a56073b	350	* @{
AnnaBridge	143:86740a56073b	351	*/
AnnaBridge	167:84c0a372a020	352	#define RCC_HSE_OFF ((uint32_t)0x00000000) /!< HSE clock deactivation /
AnnaBridge	167:84c0a372a020	353	#define RCC_HSE_ON RCC_CR_HSEON /!< HSE clock activation /
AnnaBridge	167:84c0a372a020	354	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON)) /!< External clock source for HSE clock /
AnnaBridge	167:84c0a372a020	355	/**
AnnaBridge	167:84c0a372a020	356	* @}
AnnaBridge	167:84c0a372a020	357	*/
AnnaBridge	143:86740a56073b	358
AnnaBridge	167:84c0a372a020	359	/** @defgroup RCC_LSE_Config LSE Config
AnnaBridge	167:84c0a372a020	360	* @{
AnnaBridge	167:84c0a372a020	361	*/
AnnaBridge	167:84c0a372a020	362	#define RCC_LSE_OFF ((uint32_t)0x00000000) /!< LSE clock deactivation /
AnnaBridge	167:84c0a372a020	363	#define RCC_LSE_ON RCC_CSR_LSEON /!< LSE clock activation /
AnnaBridge	167:84c0a372a020	364	#define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR_LSEBYP \| RCC_CSR_LSEON)) /!< External clock source for LSE clock /
AnnaBridge	143:86740a56073b	365
AnnaBridge	143:86740a56073b	366	/**
AnnaBridge	143:86740a56073b	367	* @}
AnnaBridge	143:86740a56073b	368	*/
AnnaBridge	143:86740a56073b	369
AnnaBridge	167:84c0a372a020	370	/** @defgroup RCC_HSI_Config HSI Config
AnnaBridge	143:86740a56073b	371	* @{
AnnaBridge	143:86740a56073b	372	*/
AnnaBridge	167:84c0a372a020	373	#define RCC_HSI_OFF ((uint32_t)0x00000000) /!< HSI clock deactivation /
AnnaBridge	167:84c0a372a020	374	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
AnnaBridge	167:84c0a372a020	375	#define RCC_HSI_DIV4 (RCC_CR_HSIDIVEN \| RCC_CR_HSION) /!< HSI_DIV4 clock activation /
AnnaBridge	167:84c0a372a020	376	#if defined(RCC_CR_HSIOUTEN)
AnnaBridge	167:84c0a372a020	377	#define RCC_HSI_OUTEN RCC_CR_HSIOUTEN /!< HSI_OUTEN clock activation /
AnnaBridge	167:84c0a372a020	378	#endif /* RCC_CR_HSIOUTEN */
AnnaBridge	143:86740a56073b	379
AnnaBridge	167:84c0a372a020	380	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
AnnaBridge	143:86740a56073b	381
AnnaBridge	143:86740a56073b	382	/**
AnnaBridge	143:86740a56073b	383	* @}
AnnaBridge	143:86740a56073b	384	*/
AnnaBridge	143:86740a56073b	385
AnnaBridge	167:84c0a372a020	386	/** @defgroup RCC_MSI_Clock_Range MSI Clock Range
AnnaBridge	143:86740a56073b	387	* @{
AnnaBridge	143:86740a56073b	388	*/
AnnaBridge	143:86740a56073b	389
AnnaBridge	143:86740a56073b	390	#define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /!< MSI = 65.536 KHz /
AnnaBridge	143:86740a56073b	391	#define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /!< MSI = 131.072 KHz /
AnnaBridge	143:86740a56073b	392	#define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /!< MSI = 262.144 KHz /
AnnaBridge	143:86740a56073b	393	#define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /!< MSI = 524.288 KHz /
AnnaBridge	143:86740a56073b	394	#define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /!< MSI = 1.048 MHz /
AnnaBridge	143:86740a56073b	395	#define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /!< MSI = 2.097 MHz /
AnnaBridge	143:86740a56073b	396	#define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /!< MSI = 4.194 MHz /
AnnaBridge	143:86740a56073b	397
AnnaBridge	167:84c0a372a020	398	/**
AnnaBridge	167:84c0a372a020	399	* @}
AnnaBridge	167:84c0a372a020	400	*/
AnnaBridge	167:84c0a372a020	401
AnnaBridge	167:84c0a372a020	402	/** @defgroup RCC_LSI_Config LSI Config
AnnaBridge	167:84c0a372a020	403	* @{
AnnaBridge	167:84c0a372a020	404	*/
AnnaBridge	167:84c0a372a020	405	#define RCC_LSI_OFF ((uint32_t)0x00000000) /!< LSI clock deactivation /
AnnaBridge	167:84c0a372a020	406	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
AnnaBridge	167:84c0a372a020	407
AnnaBridge	167:84c0a372a020	408	/**
AnnaBridge	167:84c0a372a020	409	* @}
AnnaBridge	167:84c0a372a020	410	*/
AnnaBridge	167:84c0a372a020	411
AnnaBridge	167:84c0a372a020	412	/** @defgroup RCC_MSI_Config MSI Config
AnnaBridge	167:84c0a372a020	413	* @{
AnnaBridge	167:84c0a372a020	414	*/
AnnaBridge	167:84c0a372a020	415	#define RCC_MSI_OFF ((uint32_t)0x00000000)
AnnaBridge	167:84c0a372a020	416	#define RCC_MSI_ON ((uint32_t)0x00000001)
AnnaBridge	167:84c0a372a020	417
AnnaBridge	167:84c0a372a020	418	#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0x00000000U) /* Default MSI calibration trimming value */
AnnaBridge	167:84c0a372a020	419
AnnaBridge	167:84c0a372a020	420	/**
AnnaBridge	167:84c0a372a020	421	* @}
AnnaBridge	167:84c0a372a020	422	*/
AnnaBridge	167:84c0a372a020	423
AnnaBridge	167:84c0a372a020	424	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	167:84c0a372a020	425	/** @defgroup RCC_HSI48_Config HSI48 Config
AnnaBridge	167:84c0a372a020	426	* @{
AnnaBridge	167:84c0a372a020	427	*/
AnnaBridge	167:84c0a372a020	428	#define RCC_HSI48_OFF ((uint8_t)0x00)
AnnaBridge	167:84c0a372a020	429	#define RCC_HSI48_ON ((uint8_t)0x01)
AnnaBridge	167:84c0a372a020	430
AnnaBridge	167:84c0a372a020	431	/**
AnnaBridge	167:84c0a372a020	432	* @}
AnnaBridge	167:84c0a372a020	433	*/
AnnaBridge	167:84c0a372a020	434	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	167:84c0a372a020	435
AnnaBridge	167:84c0a372a020	436	/** @defgroup RCC_PLL_Config PLL Config
AnnaBridge	167:84c0a372a020	437	* @{
AnnaBridge	167:84c0a372a020	438	*/
AnnaBridge	167:84c0a372a020	439	#define RCC_PLL_NONE ((uint32_t)0x00000000) /!< PLL is not configured /
AnnaBridge	167:84c0a372a020	440	#define RCC_PLL_OFF ((uint32_t)0x00000001) /!< PLL deactivation /
AnnaBridge	167:84c0a372a020	441	#define RCC_PLL_ON ((uint32_t)0x00000002) /!< PLL activation /
AnnaBridge	167:84c0a372a020	442
AnnaBridge	167:84c0a372a020	443	/**
AnnaBridge	167:84c0a372a020	444	* @}
AnnaBridge	167:84c0a372a020	445	*/
AnnaBridge	167:84c0a372a020	446
AnnaBridge	167:84c0a372a020	447	/** @defgroup RCC_System_Clock_Type System Clock Type
AnnaBridge	167:84c0a372a020	448	* @{
AnnaBridge	167:84c0a372a020	449	*/
AnnaBridge	167:84c0a372a020	450	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /!< SYSCLK to configure /
AnnaBridge	167:84c0a372a020	451	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /!< HCLK to configure /
AnnaBridge	167:84c0a372a020	452	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /!< PCLK1 to configure /
AnnaBridge	167:84c0a372a020	453	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /!< PCLK2 to configure /
AnnaBridge	167:84c0a372a020	454
AnnaBridge	167:84c0a372a020	455	/**
AnnaBridge	167:84c0a372a020	456	* @}
AnnaBridge	167:84c0a372a020	457	*/
AnnaBridge	167:84c0a372a020	458
AnnaBridge	167:84c0a372a020	459	/** @defgroup RCC_System_Clock_Source System Clock Source
AnnaBridge	167:84c0a372a020	460	* @{
AnnaBridge	167:84c0a372a020	461	*/
AnnaBridge	167:84c0a372a020	462	#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selected as system clock /
AnnaBridge	167:84c0a372a020	463	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selected as system clock /
AnnaBridge	167:84c0a372a020	464	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selected as system clock /
AnnaBridge	167:84c0a372a020	465	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selected as system clock /
AnnaBridge	167:84c0a372a020	466
AnnaBridge	167:84c0a372a020	467	/**
AnnaBridge	167:84c0a372a020	468	* @}
AnnaBridge	167:84c0a372a020	469	*/
AnnaBridge	167:84c0a372a020	470
AnnaBridge	167:84c0a372a020	471	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
AnnaBridge	167:84c0a372a020	472	* @{
AnnaBridge	167:84c0a372a020	473	*/
AnnaBridge	167:84c0a372a020	474	#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
AnnaBridge	167:84c0a372a020	475	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
AnnaBridge	167:84c0a372a020	476	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
AnnaBridge	167:84c0a372a020	477	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
AnnaBridge	143:86740a56073b	478
AnnaBridge	143:86740a56073b	479	/**
AnnaBridge	143:86740a56073b	480	* @}
AnnaBridge	143:86740a56073b	481	*/
AnnaBridge	143:86740a56073b	482
AnnaBridge	167:84c0a372a020	483	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
AnnaBridge	143:86740a56073b	484	* @{
AnnaBridge	143:86740a56073b	485	*/
AnnaBridge	167:84c0a372a020	486	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
AnnaBridge	167:84c0a372a020	487	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
AnnaBridge	167:84c0a372a020	488	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
AnnaBridge	167:84c0a372a020	489	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
AnnaBridge	167:84c0a372a020	490	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
AnnaBridge	167:84c0a372a020	491	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
AnnaBridge	167:84c0a372a020	492	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
AnnaBridge	167:84c0a372a020	493	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
AnnaBridge	167:84c0a372a020	494	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
AnnaBridge	143:86740a56073b	495
AnnaBridge	143:86740a56073b	496	/**
AnnaBridge	143:86740a56073b	497	* @}
AnnaBridge	143:86740a56073b	498	*/
AnnaBridge	167:84c0a372a020	499
AnnaBridge	167:84c0a372a020	500	/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
AnnaBridge	143:86740a56073b	501	* @{
AnnaBridge	143:86740a56073b	502	*/
AnnaBridge	167:84c0a372a020	503	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
AnnaBridge	167:84c0a372a020	504	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
AnnaBridge	167:84c0a372a020	505	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
AnnaBridge	167:84c0a372a020	506	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
AnnaBridge	167:84c0a372a020	507	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
AnnaBridge	143:86740a56073b	508
AnnaBridge	143:86740a56073b	509	/**
AnnaBridge	143:86740a56073b	510	* @}
AnnaBridge	143:86740a56073b	511	*/
AnnaBridge	143:86740a56073b	512
AnnaBridge	167:84c0a372a020	513	/** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler
AnnaBridge	143:86740a56073b	514	* @{
AnnaBridge	143:86740a56073b	515	*/
AnnaBridge	167:84c0a372a020	516	#define RCC_RTC_HSE_DIV_2 (uint32_t)0x00000000U /!< HSE is divided by 2 for RTC clock /
AnnaBridge	167:84c0a372a020	517	#define RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /!< HSE is divided by 4 for RTC clock /
AnnaBridge	167:84c0a372a020	518	#define RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /!< HSE is divided by 8 for RTC clock /
AnnaBridge	167:84c0a372a020	519	#define RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /!< HSE is divided by 16 for RTC clock /
AnnaBridge	167:84c0a372a020	520	/**
AnnaBridge	167:84c0a372a020	521	* @}
AnnaBridge	167:84c0a372a020	522	*/
AnnaBridge	143:86740a56073b	523
AnnaBridge	167:84c0a372a020	524	/** @defgroup RCC_RTC_LCD_Clock_Source RTC LCD Clock Source
AnnaBridge	167:84c0a372a020	525	* @{
AnnaBridge	167:84c0a372a020	526	*/
AnnaBridge	167:84c0a372a020	527	#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /!< No clock /
AnnaBridge	167:84c0a372a020	528	#define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /!< LSE oscillator clock used as RTC clock /
AnnaBridge	167:84c0a372a020	529	#define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /!< LSI oscillator clock used as RTC clock /
AnnaBridge	167:84c0a372a020	530	#define RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE /!< HSE oscillator clock divided by X used as RTC clock /
AnnaBridge	167:84c0a372a020	531	#define RCC_RTCCLKSOURCE_HSE_DIV2 (RCC_RTC_HSE_DIV_2 \| RCC_CSR_RTCSEL_HSE) /!< HSE oscillator clock divided by 2 used as RTC clock /
AnnaBridge	167:84c0a372a020	532	#define RCC_RTCCLKSOURCE_HSE_DIV4 (RCC_RTC_HSE_DIV_4 \| RCC_CSR_RTCSEL_HSE) /!< HSE oscillator clock divided by 4 used as RTC clock /
AnnaBridge	167:84c0a372a020	533	#define RCC_RTCCLKSOURCE_HSE_DIV8 (RCC_RTC_HSE_DIV_8 \| RCC_CSR_RTCSEL_HSE) /!< HSE oscillator clock divided by 8 used as RTC clock /
AnnaBridge	167:84c0a372a020	534	#define RCC_RTCCLKSOURCE_HSE_DIV16 (RCC_RTC_HSE_DIV_16 \| RCC_CSR_RTCSEL_HSE) /!< HSE oscillator clock divided by 16 used as RTC clock /
AnnaBridge	143:86740a56073b	535	/**
AnnaBridge	143:86740a56073b	536	* @}
AnnaBridge	143:86740a56073b	537	*/
AnnaBridge	143:86740a56073b	538
AnnaBridge	167:84c0a372a020	539	/** @defgroup RCC_PLL_Division_Factor PLL Division Factor
AnnaBridge	167:84c0a372a020	540	* @{
AnnaBridge	167:84c0a372a020	541	*/
AnnaBridge	167:84c0a372a020	542
AnnaBridge	167:84c0a372a020	543	#define RCC_PLL_DIV2 RCC_CFGR_PLLDIV2
AnnaBridge	167:84c0a372a020	544	#define RCC_PLL_DIV3 RCC_CFGR_PLLDIV3
AnnaBridge	167:84c0a372a020	545	#define RCC_PLL_DIV4 RCC_CFGR_PLLDIV4
AnnaBridge	167:84c0a372a020	546
AnnaBridge	167:84c0a372a020	547	/**
AnnaBridge	167:84c0a372a020	548	* @}
AnnaBridge	167:84c0a372a020	549	*/
AnnaBridge	167:84c0a372a020	550
AnnaBridge	167:84c0a372a020	551	/** @defgroup RCC_PLL_Multiplication_Factor PLL Multiplication Factor
AnnaBridge	143:86740a56073b	552	* @{
AnnaBridge	143:86740a56073b	553	*/
AnnaBridge	143:86740a56073b	554
AnnaBridge	167:84c0a372a020	555	#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
AnnaBridge	167:84c0a372a020	556	#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
AnnaBridge	167:84c0a372a020	557	#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
AnnaBridge	167:84c0a372a020	558	#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
AnnaBridge	167:84c0a372a020	559	#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
AnnaBridge	167:84c0a372a020	560	#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
AnnaBridge	167:84c0a372a020	561	#define RCC_PLL_MUL24 RCC_CFGR_PLLMUL24
AnnaBridge	167:84c0a372a020	562	#define RCC_PLL_MUL32 RCC_CFGR_PLLMUL32
AnnaBridge	167:84c0a372a020	563	#define RCC_PLL_MUL48 RCC_CFGR_PLLMUL48
AnnaBridge	143:86740a56073b	564
AnnaBridge	143:86740a56073b	565	/**
AnnaBridge	143:86740a56073b	566	* @}
AnnaBridge	167:84c0a372a020	567	*/
AnnaBridge	143:86740a56073b	568
AnnaBridge	167:84c0a372a020	569	/** @defgroup RCC_MCO_Index MCO Index
AnnaBridge	143:86740a56073b	570	* @{
AnnaBridge	143:86740a56073b	571	*/
AnnaBridge	167:84c0a372a020	572	#define RCC_MCO1 ((uint32_t)0x00000000)
AnnaBridge	167:84c0a372a020	573	#define RCC_MCO2 ((uint32_t)0x00000001)
AnnaBridge	167:84c0a372a020	574	#if defined(STM32L031xx) \|\| defined(STM32L041xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \
AnnaBridge	167:84c0a372a020	575	\|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
AnnaBridge	167:84c0a372a020	576	#define RCC_MCO3 ((uint32_t)0x00000002)
AnnaBridge	143:86740a56073b	577	#endif
AnnaBridge	143:86740a56073b	578
AnnaBridge	143:86740a56073b	579	/**
AnnaBridge	143:86740a56073b	580	* @}
AnnaBridge	143:86740a56073b	581	*/
AnnaBridge	143:86740a56073b	582
AnnaBridge	167:84c0a372a020	583	/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
AnnaBridge	143:86740a56073b	584	* @{
AnnaBridge	143:86740a56073b	585	*/
AnnaBridge	167:84c0a372a020	586	#define RCC_MCODIV_1 RCC_CFGR_MCO_PRE_1
AnnaBridge	167:84c0a372a020	587	#define RCC_MCODIV_2 RCC_CFGR_MCO_PRE_2
AnnaBridge	167:84c0a372a020	588	#define RCC_MCODIV_4 RCC_CFGR_MCO_PRE_4
AnnaBridge	167:84c0a372a020	589	#define RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8
AnnaBridge	167:84c0a372a020	590	#define RCC_MCODIV_16 RCC_CFGR_MCO_PRE_16
AnnaBridge	143:86740a56073b	591
AnnaBridge	143:86740a56073b	592	/**
AnnaBridge	143:86740a56073b	593	* @}
AnnaBridge	143:86740a56073b	594	*/
AnnaBridge	143:86740a56073b	595
AnnaBridge	167:84c0a372a020	596	/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
AnnaBridge	167:84c0a372a020	597	* @{
AnnaBridge	167:84c0a372a020	598	*/
AnnaBridge	167:84c0a372a020	599	#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
AnnaBridge	167:84c0a372a020	600	#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
AnnaBridge	167:84c0a372a020	601	#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI
AnnaBridge	167:84c0a372a020	602	#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
AnnaBridge	167:84c0a372a020	603	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
AnnaBridge	167:84c0a372a020	604	#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
AnnaBridge	167:84c0a372a020	605	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
AnnaBridge	167:84c0a372a020	606	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL
AnnaBridge	167:84c0a372a020	607	#if defined(RCC_CFGR_MCOSEL_HSI48)
AnnaBridge	167:84c0a372a020	608	#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48
AnnaBridge	167:84c0a372a020	609	#endif /* RCC_CFGR_MCOSEL_HSI48 */
AnnaBridge	167:84c0a372a020	610
AnnaBridge	167:84c0a372a020	611	/**
AnnaBridge	167:84c0a372a020	612	* @}
AnnaBridge	167:84c0a372a020	613	*/
AnnaBridge	167:84c0a372a020	614	/** @defgroup RCC_Interrupt Interrupts
AnnaBridge	167:84c0a372a020	615	* @{
AnnaBridge	167:84c0a372a020	616	*/
AnnaBridge	167:84c0a372a020	617	#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /!< LSI Ready Interrupt flag /
AnnaBridge	167:84c0a372a020	618	#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /!< LSE Ready Interrupt flag /
AnnaBridge	167:84c0a372a020	619	#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /!< HSI Ready Interrupt flag /
AnnaBridge	167:84c0a372a020	620	#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /!< HSE Ready Interrupt flag /
AnnaBridge	167:84c0a372a020	621	#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /!< PLL Ready Interrupt flag /
AnnaBridge	167:84c0a372a020	622	#define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /!< MSI Ready Interrupt flag /
AnnaBridge	167:84c0a372a020	623	#define RCC_IT_LSECSS RCC_CIFR_CSSLSEF /!< LSE Clock Security System Interrupt flag /
AnnaBridge	167:84c0a372a020	624	#if defined(RCC_HSECSS_SUPPORT)
AnnaBridge	167:84c0a372a020	625	#define RCC_IT_CSS RCC_CIFR_CSSHSEF /!< Clock Security System Interrupt flag /
AnnaBridge	167:84c0a372a020	626	#endif /* RCC_HSECSS_SUPPORT */
AnnaBridge	167:84c0a372a020	627	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	167:84c0a372a020	628	#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /!< HSI48 Ready Interrupt flag /
AnnaBridge	167:84c0a372a020	629	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	167:84c0a372a020	630	/**
AnnaBridge	167:84c0a372a020	631	* @}
AnnaBridge	167:84c0a372a020	632	*/
AnnaBridge	167:84c0a372a020	633
AnnaBridge	167:84c0a372a020	634	/** @defgroup RCC_Flag Flags
AnnaBridge	167:84c0a372a020	635	* Elements values convention: XXXYYYYYb
AnnaBridge	143:86740a56073b	636	* - YYYYY : Flag position in the register
AnnaBridge	167:84c0a372a020	637	* - XXX : Register index
AnnaBridge	167:84c0a372a020	638	* - 001: CR register
AnnaBridge	167:84c0a372a020	639	* - 010: CSR register
AnnaBridge	167:84c0a372a020	640	* - 011: CRRCR register (*)
AnnaBridge	167:84c0a372a020	641	* (*) Applicable only for STM32L052xx, STM32L053xx, (...), STM32L073xx & STM32L082xx
AnnaBridge	143:86740a56073b	642	* @{
AnnaBridge	143:86740a56073b	643	*/
AnnaBridge	143:86740a56073b	644	/* Flags in the CR register */
AnnaBridge	167:84c0a372a020	645	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| 2)) /!< Internal High Speed clock ready flag /
AnnaBridge	167:84c0a372a020	646	#define RCC_FLAG_HSIDIV ((uint8_t)((CR_REG_INDEX << 5) \| 4)) /!< HSI16 divider flag /
AnnaBridge	167:84c0a372a020	647	#define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| 9)) /!< MSI clock ready flag /
AnnaBridge	167:84c0a372a020	648	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) \| 17)) /!< External High Speed clock ready flag /
AnnaBridge	167:84c0a372a020	649	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) \| 25)) /!< PLL clock ready flag /
AnnaBridge	143:86740a56073b	650	/* Flags in the CSR register */
AnnaBridge	167:84c0a372a020	651	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) \| 1)) /!< Internal Low Speed oscillator Ready /
AnnaBridge	167:84c0a372a020	652	#define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5) \| 9)) /!< External Low Speed oscillator Ready /
AnnaBridge	167:84c0a372a020	653	#define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5) \| 14)) /!< CSS on LSE failure Detection /
AnnaBridge	167:84c0a372a020	654	#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) \| 25)) /!< Options bytes loading reset flag /
AnnaBridge	167:84c0a372a020	655	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) \| 26)) /!< PIN reset flag /
AnnaBridge	167:84c0a372a020	656	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) \| 27)) /!< POR/PDR reset flag /
AnnaBridge	167:84c0a372a020	657	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) \| 28)) /!< Software Reset flag /
AnnaBridge	167:84c0a372a020	658	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| 29)) /!< Independent Watchdog reset flag /
AnnaBridge	167:84c0a372a020	659	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| 30)) /!< Window watchdog reset flag /
AnnaBridge	167:84c0a372a020	660	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| 31)) /!< Low-Power reset flag /
AnnaBridge	167:84c0a372a020	661	#if defined(RCC_CSR_FWRSTF)
AnnaBridge	167:84c0a372a020	662	#define RCC_FLAG_FWRST ((uint8_t)((CSR_REG_INDEX << 5) \| 8)) /!< RCC flag FW reset /
AnnaBridge	167:84c0a372a020	663	#endif /* RCC_CSR_FWRSTF */
AnnaBridge	143:86740a56073b	664	/* Flags in the CRRCR register */
AnnaBridge	167:84c0a372a020	665	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	167:84c0a372a020	666	#define RCC_FLAG_HSI48RDY ((uint8_t)((CRRCR_REG_INDEX << 5) \| 1)) /!< HSI48 clock ready flag /
AnnaBridge	167:84c0a372a020	667	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	143:86740a56073b	668
AnnaBridge	143:86740a56073b	669	/**
AnnaBridge	143:86740a56073b	670	* @}
AnnaBridge	167:84c0a372a020	671	*/
AnnaBridge	143:86740a56073b	672
AnnaBridge	143:86740a56073b	673	/**
AnnaBridge	143:86740a56073b	674	* @}
AnnaBridge	167:84c0a372a020	675	*/
AnnaBridge	167:84c0a372a020	676
AnnaBridge	143:86740a56073b	677	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	167:84c0a372a020	678
AnnaBridge	143:86740a56073b	679	/** @defgroup RCC_Exported_Macros RCC Exported Macros
AnnaBridge	167:84c0a372a020	680	* @{
AnnaBridge	167:84c0a372a020	681	*/
AnnaBridge	167:84c0a372a020	682
AnnaBridge	143:86740a56073b	683	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable
AnnaBridge	143:86740a56073b	684	* @brief Enable or disable the AHB peripheral clock.
AnnaBridge	143:86740a56073b	685	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	143:86740a56073b	686	* is disabled and the application software has to enable this clock before
AnnaBridge	143:86740a56073b	687	* using it.
AnnaBridge	143:86740a56073b	688	* @{
AnnaBridge	143:86740a56073b	689	*/
AnnaBridge	143:86740a56073b	690	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
AnnaBridge	143:86740a56073b	691	__IO uint32_t tmpreg; \
AnnaBridge	143:86740a56073b	692	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
AnnaBridge	143:86740a56073b	693	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	143:86740a56073b	694	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
AnnaBridge	143:86740a56073b	695	UNUSED(tmpreg); \
AnnaBridge	143:86740a56073b	696	} while(0)
AnnaBridge	143:86740a56073b	697
AnnaBridge	143:86740a56073b	698	#define __HAL_RCC_MIF_CLK_ENABLE() do { \
AnnaBridge	143:86740a56073b	699	__IO uint32_t tmpreg; \
AnnaBridge	143:86740a56073b	700	SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
AnnaBridge	143:86740a56073b	701	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	143:86740a56073b	702	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
AnnaBridge	143:86740a56073b	703	UNUSED(tmpreg); \
AnnaBridge	143:86740a56073b	704	} while(0)
AnnaBridge	143:86740a56073b	705
AnnaBridge	143:86740a56073b	706	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	143:86740a56073b	707	__IO uint32_t tmpreg; \
AnnaBridge	143:86740a56073b	708	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
AnnaBridge	143:86740a56073b	709	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	143:86740a56073b	710	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
AnnaBridge	143:86740a56073b	711	UNUSED(tmpreg); \
AnnaBridge	143:86740a56073b	712	} while(0)
AnnaBridge	143:86740a56073b	713
AnnaBridge	143:86740a56073b	714
AnnaBridge	143:86740a56073b	715	#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
AnnaBridge	143:86740a56073b	716	#define __HAL_RCC_MIF_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN)
AnnaBridge	143:86740a56073b	717	#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
AnnaBridge	143:86740a56073b	718
AnnaBridge	143:86740a56073b	719	/**
AnnaBridge	143:86740a56073b	720	* @}
AnnaBridge	143:86740a56073b	721	*/
AnnaBridge	143:86740a56073b	722
AnnaBridge	143:86740a56073b	723	/** @defgroup RCC_IOPORT_Clock_Enable_Disable IOPORT Peripheral Clock Enable Disable
AnnaBridge	143:86740a56073b	724	* @brief Enable or disable the IOPORT peripheral clock.
AnnaBridge	143:86740a56073b	725	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	143:86740a56073b	726	* is disabled and the application software has to enable this clock before
AnnaBridge	143:86740a56073b	727	* using it.
AnnaBridge	143:86740a56073b	728	* @{
AnnaBridge	143:86740a56073b	729	*/
AnnaBridge	143:86740a56073b	730	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
AnnaBridge	143:86740a56073b	731	__IO uint32_t tmpreg; \
AnnaBridge	143:86740a56073b	732	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
AnnaBridge	143:86740a56073b	733	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	143:86740a56073b	734	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
AnnaBridge	143:86740a56073b	735	UNUSED(tmpreg); \
AnnaBridge	143:86740a56073b	736	} while(0)
AnnaBridge	143:86740a56073b	737
AnnaBridge	143:86740a56073b	738	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
AnnaBridge	143:86740a56073b	739	__IO uint32_t tmpreg; \
AnnaBridge	143:86740a56073b	740	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
AnnaBridge	143:86740a56073b	741	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	143:86740a56073b	742	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
AnnaBridge	143:86740a56073b	743	UNUSED(tmpreg); \
AnnaBridge	143:86740a56073b	744	} while(0)
AnnaBridge	143:86740a56073b	745
AnnaBridge	143:86740a56073b	746	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
AnnaBridge	143:86740a56073b	747	__IO uint32_t tmpreg; \
AnnaBridge	143:86740a56073b	748	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
AnnaBridge	143:86740a56073b	749	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	143:86740a56073b	750	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
AnnaBridge	143:86740a56073b	751	UNUSED(tmpreg); \
AnnaBridge	143:86740a56073b	752	} while(0)
AnnaBridge	143:86740a56073b	753
AnnaBridge	143:86740a56073b	754	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
AnnaBridge	143:86740a56073b	755	__IO uint32_t tmpreg; \
AnnaBridge	143:86740a56073b	756	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
AnnaBridge	143:86740a56073b	757	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	143:86740a56073b	758	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
AnnaBridge	143:86740a56073b	759	UNUSED(tmpreg); \
AnnaBridge	143:86740a56073b	760	} while(0)
AnnaBridge	143:86740a56073b	761
AnnaBridge	143:86740a56073b	762
AnnaBridge	143:86740a56073b	763	#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN)
AnnaBridge	143:86740a56073b	764	#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN)
AnnaBridge	143:86740a56073b	765	#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN)
AnnaBridge	143:86740a56073b	766	#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN)
AnnaBridge	143:86740a56073b	767
AnnaBridge	143:86740a56073b	768	/**
AnnaBridge	143:86740a56073b	769	* @}
AnnaBridge	143:86740a56073b	770	*/
AnnaBridge	143:86740a56073b	771
AnnaBridge	143:86740a56073b	772	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge	143:86740a56073b	773	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	143:86740a56073b	774	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	143:86740a56073b	775	* is disabled and the application software has to enable this clock before
AnnaBridge	143:86740a56073b	776	* using it.
AnnaBridge	143:86740a56073b	777	* @{
AnnaBridge	143:86740a56073b	778	*/
AnnaBridge	143:86740a56073b	779	#define __HAL_RCC_WWDG_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
AnnaBridge	143:86740a56073b	780	#define __HAL_RCC_PWR_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
AnnaBridge	143:86740a56073b	781
AnnaBridge	143:86740a56073b	782	#define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
AnnaBridge	143:86740a56073b	783	#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
AnnaBridge	143:86740a56073b	784	/**
AnnaBridge	143:86740a56073b	785	* @}
AnnaBridge	143:86740a56073b	786	*/
AnnaBridge	143:86740a56073b	787
AnnaBridge	143:86740a56073b	788	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge	143:86740a56073b	789	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	143:86740a56073b	790	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	143:86740a56073b	791	* is disabled and the application software has to enable this clock before
AnnaBridge	143:86740a56073b	792	* using it.
AnnaBridge	143:86740a56073b	793	* @{
AnnaBridge	143:86740a56073b	794	*/
AnnaBridge	143:86740a56073b	795	#define __HAL_RCC_SYSCFG_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
AnnaBridge	143:86740a56073b	796	#define __HAL_RCC_DBGMCU_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
AnnaBridge	143:86740a56073b	797
AnnaBridge	143:86740a56073b	798	#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
AnnaBridge	143:86740a56073b	799	#define __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
AnnaBridge	143:86740a56073b	800	/**
AnnaBridge	143:86740a56073b	801	* @}
AnnaBridge	143:86740a56073b	802	*/
AnnaBridge	143:86740a56073b	803
AnnaBridge	143:86740a56073b	804	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enabled or Disabled Status
AnnaBridge	143:86740a56073b	805	* @brief Check whether the AHB peripheral clock is enabled or not.
AnnaBridge	143:86740a56073b	806	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	143:86740a56073b	807	* is disabled and the application software has to enable this clock before
AnnaBridge	143:86740a56073b	808	* using it.
AnnaBridge	143:86740a56073b	809	* @{
AnnaBridge	143:86740a56073b	810	*/
AnnaBridge	143:86740a56073b	811
AnnaBridge	143:86740a56073b	812	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != RESET)
AnnaBridge	143:86740a56073b	813	#define __HAL_RCC_MIF_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) != RESET)
AnnaBridge	143:86740a56073b	814	#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != RESET)
AnnaBridge	167:84c0a372a020	815	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == RESET)
AnnaBridge	167:84c0a372a020	816	#define __HAL_RCC_MIF_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) == RESET)
AnnaBridge	167:84c0a372a020	817	#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == RESET)
AnnaBridge	143:86740a56073b	818
AnnaBridge	143:86740a56073b	819	/**
AnnaBridge	143:86740a56073b	820	* @}
AnnaBridge	143:86740a56073b	821	*/
AnnaBridge	143:86740a56073b	822
AnnaBridge	143:86740a56073b	823	/** @defgroup RCC_IOPORT_Peripheral_Clock_Enable_Disable_Status IOPORT Peripheral Clock Enabled or Disabled Status
AnnaBridge	143:86740a56073b	824	* @brief Check whether the IOPORT peripheral clock is enabled or not.
AnnaBridge	143:86740a56073b	825	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	143:86740a56073b	826	* is disabled and the application software has to enable this clock before
AnnaBridge	143:86740a56073b	827	* using it.
AnnaBridge	143:86740a56073b	828	* @{
AnnaBridge	143:86740a56073b	829	*/
AnnaBridge	143:86740a56073b	830
AnnaBridge	143:86740a56073b	831	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != RESET)
AnnaBridge	143:86740a56073b	832	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != RESET)
AnnaBridge	143:86740a56073b	833	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != RESET)
AnnaBridge	143:86740a56073b	834	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) != RESET)
AnnaBridge	167:84c0a372a020	835	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) == RESET)
AnnaBridge	167:84c0a372a020	836	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) == RESET)
AnnaBridge	167:84c0a372a020	837	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) == RESET)
AnnaBridge	167:84c0a372a020	838	#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) == RESET)
AnnaBridge	143:86740a56073b	839
AnnaBridge	143:86740a56073b	840	/**
AnnaBridge	143:86740a56073b	841	* @}
AnnaBridge	143:86740a56073b	842	*/
AnnaBridge	143:86740a56073b	843
AnnaBridge	143:86740a56073b	844	/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
AnnaBridge	143:86740a56073b	845	* @brief Check whether the APB1 peripheral clock is enabled or not.
AnnaBridge	143:86740a56073b	846	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	143:86740a56073b	847	* is disabled and the application software has to enable this clock before
AnnaBridge	143:86740a56073b	848	* using it.
AnnaBridge	143:86740a56073b	849	* @{
AnnaBridge	143:86740a56073b	850	*/
AnnaBridge	143:86740a56073b	851	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) != RESET)
AnnaBridge	143:86740a56073b	852	#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) != RESET)
AnnaBridge	167:84c0a372a020	853	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) == RESET)
AnnaBridge	167:84c0a372a020	854	#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) == RESET)
AnnaBridge	143:86740a56073b	855
AnnaBridge	143:86740a56073b	856	/**
AnnaBridge	143:86740a56073b	857	* @}
AnnaBridge	143:86740a56073b	858	*/
AnnaBridge	143:86740a56073b	859
AnnaBridge	143:86740a56073b	860	/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
AnnaBridge	143:86740a56073b	861	* @brief Check whether the APB2 peripheral clock is enabled or not.
AnnaBridge	143:86740a56073b	862	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	143:86740a56073b	863	* is disabled and the application software has to enable this clock before
AnnaBridge	143:86740a56073b	864	* using it.
AnnaBridge	143:86740a56073b	865	* @{
AnnaBridge	143:86740a56073b	866	*/
AnnaBridge	143:86740a56073b	867	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
AnnaBridge	143:86740a56073b	868	#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) != RESET)
AnnaBridge	167:84c0a372a020	869	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET)
AnnaBridge	167:84c0a372a020	870	#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) == RESET)
AnnaBridge	143:86740a56073b	871
AnnaBridge	143:86740a56073b	872	/**
AnnaBridge	143:86740a56073b	873	* @}
AnnaBridge	143:86740a56073b	874	*/
AnnaBridge	143:86740a56073b	875
AnnaBridge	143:86740a56073b	876	/** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset
AnnaBridge	143:86740a56073b	877	* @brief Force or release AHB peripheral reset.
AnnaBridge	143:86740a56073b	878	* @{
AnnaBridge	143:86740a56073b	879	*/
AnnaBridge	143:86740a56073b	880	#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
AnnaBridge	143:86740a56073b	881	#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
AnnaBridge	143:86740a56073b	882	#define __HAL_RCC_MIF_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
AnnaBridge	143:86740a56073b	883	#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
AnnaBridge	143:86740a56073b	884
AnnaBridge	167:84c0a372a020	885	#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)
AnnaBridge	143:86740a56073b	886	#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
AnnaBridge	143:86740a56073b	887	#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
AnnaBridge	143:86740a56073b	888	#define __HAL_RCC_MIF_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
AnnaBridge	143:86740a56073b	889	/**
AnnaBridge	143:86740a56073b	890	* @}
AnnaBridge	143:86740a56073b	891	*/
AnnaBridge	143:86740a56073b	892
AnnaBridge	143:86740a56073b	893	/** @defgroup RCC_IOPORT_Force_Release_Reset IOPORT Peripheral Force Release Reset
AnnaBridge	143:86740a56073b	894	* @brief Force or release IOPORT peripheral reset.
AnnaBridge	143:86740a56073b	895	* @{
AnnaBridge	143:86740a56073b	896	*/
AnnaBridge	143:86740a56073b	897	#define __HAL_RCC_IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFFU)
AnnaBridge	143:86740a56073b	898	#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
AnnaBridge	143:86740a56073b	899	#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
AnnaBridge	143:86740a56073b	900	#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
AnnaBridge	143:86740a56073b	901	#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))
AnnaBridge	143:86740a56073b	902
AnnaBridge	167:84c0a372a020	903	#define __HAL_RCC_IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00000000U)
AnnaBridge	143:86740a56073b	904	#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
AnnaBridge	143:86740a56073b	905	#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
AnnaBridge	143:86740a56073b	906	#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
AnnaBridge	143:86740a56073b	907	#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))
AnnaBridge	143:86740a56073b	908
AnnaBridge	143:86740a56073b	909	/**
AnnaBridge	143:86740a56073b	910	* @}
AnnaBridge	143:86740a56073b	911	*/
AnnaBridge	143:86740a56073b	912
AnnaBridge	143:86740a56073b	913	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
AnnaBridge	143:86740a56073b	914	* @brief Force or release APB1 peripheral reset.
AnnaBridge	143:86740a56073b	915	* @{
AnnaBridge	143:86740a56073b	916	*/
AnnaBridge	143:86740a56073b	917	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
AnnaBridge	143:86740a56073b	918	#define __HAL_RCC_WWDG_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
AnnaBridge	143:86740a56073b	919	#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
AnnaBridge	143:86740a56073b	920
AnnaBridge	167:84c0a372a020	921	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)
AnnaBridge	143:86740a56073b	922	#define __HAL_RCC_WWDG_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
AnnaBridge	143:86740a56073b	923	#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
AnnaBridge	143:86740a56073b	924
AnnaBridge	143:86740a56073b	925	/**
AnnaBridge	143:86740a56073b	926	* @}
AnnaBridge	143:86740a56073b	927	*/
AnnaBridge	143:86740a56073b	928
AnnaBridge	143:86740a56073b	929	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
AnnaBridge	143:86740a56073b	930	* @brief Force or release APB2 peripheral reset.
AnnaBridge	143:86740a56073b	931	* @{
AnnaBridge	143:86740a56073b	932	*/
AnnaBridge	143:86740a56073b	933	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
AnnaBridge	143:86740a56073b	934	#define __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
AnnaBridge	143:86740a56073b	935	#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
AnnaBridge	143:86740a56073b	936
AnnaBridge	167:84c0a372a020	937	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)
AnnaBridge	143:86740a56073b	938	#define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
AnnaBridge	143:86740a56073b	939	#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
AnnaBridge	143:86740a56073b	940	/**
AnnaBridge	143:86740a56073b	941	* @}
AnnaBridge	143:86740a56073b	942	*/
AnnaBridge	143:86740a56073b	943
AnnaBridge	143:86740a56073b	944
AnnaBridge	143:86740a56073b	945	/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable AHB Peripheral Clock Sleep Enable Disable
AnnaBridge	143:86740a56073b	946	* @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
AnnaBridge	143:86740a56073b	947	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	143:86740a56073b	948	* power consumption.
AnnaBridge	143:86740a56073b	949	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	143:86740a56073b	950	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
AnnaBridge	143:86740a56073b	951	* @{
AnnaBridge	143:86740a56073b	952	*/
AnnaBridge	143:86740a56073b	953	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
AnnaBridge	143:86740a56073b	954	#define __HAL_RCC_MIF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
AnnaBridge	143:86740a56073b	955	#define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
AnnaBridge	143:86740a56073b	956	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
AnnaBridge	143:86740a56073b	957
AnnaBridge	143:86740a56073b	958	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
AnnaBridge	143:86740a56073b	959	#define __HAL_RCC_MIF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
AnnaBridge	143:86740a56073b	960	#define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
AnnaBridge	143:86740a56073b	961	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
AnnaBridge	143:86740a56073b	962	/**
AnnaBridge	143:86740a56073b	963	* @}
AnnaBridge	143:86740a56073b	964	*/
AnnaBridge	143:86740a56073b	965
AnnaBridge	143:86740a56073b	966	/** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable IOPORT Peripheral Clock Sleep Enable Disable
AnnaBridge	143:86740a56073b	967	* @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
AnnaBridge	143:86740a56073b	968	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	143:86740a56073b	969	* power consumption.
AnnaBridge	143:86740a56073b	970	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	143:86740a56073b	971	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
AnnaBridge	143:86740a56073b	972	* @{
AnnaBridge	143:86740a56073b	973	*/
AnnaBridge	143:86740a56073b	974
AnnaBridge	143:86740a56073b	975	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))
AnnaBridge	143:86740a56073b	976	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))
AnnaBridge	143:86740a56073b	977	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))
AnnaBridge	143:86740a56073b	978	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))
AnnaBridge	143:86740a56073b	979
AnnaBridge	143:86740a56073b	980	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))
AnnaBridge	143:86740a56073b	981	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))
AnnaBridge	143:86740a56073b	982	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))
AnnaBridge	143:86740a56073b	983	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))
AnnaBridge	143:86740a56073b	984	/**
AnnaBridge	143:86740a56073b	985	* @}
AnnaBridge	143:86740a56073b	986	*/
AnnaBridge	143:86740a56073b	987
AnnaBridge	143:86740a56073b	988	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
AnnaBridge	143:86740a56073b	989	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	143:86740a56073b	990	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	143:86740a56073b	991	* power consumption.
AnnaBridge	143:86740a56073b	992	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	143:86740a56073b	993	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
AnnaBridge	143:86740a56073b	994	* @{
AnnaBridge	143:86740a56073b	995	*/
AnnaBridge	143:86740a56073b	996	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN))
AnnaBridge	143:86740a56073b	997	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN))
AnnaBridge	143:86740a56073b	998
AnnaBridge	143:86740a56073b	999	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN))
AnnaBridge	143:86740a56073b	1000	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN))
AnnaBridge	143:86740a56073b	1001
AnnaBridge	143:86740a56073b	1002	/**
AnnaBridge	143:86740a56073b	1003	* @}
AnnaBridge	143:86740a56073b	1004	*/
AnnaBridge	143:86740a56073b	1005
AnnaBridge	143:86740a56073b	1006	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
AnnaBridge	143:86740a56073b	1007	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	143:86740a56073b	1008	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	143:86740a56073b	1009	* power consumption.
AnnaBridge	143:86740a56073b	1010	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	143:86740a56073b	1011	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
AnnaBridge	143:86740a56073b	1012	* @{
AnnaBridge	143:86740a56073b	1013	*/
AnnaBridge	143:86740a56073b	1014	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN))
AnnaBridge	143:86740a56073b	1015	#define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN))
AnnaBridge	143:86740a56073b	1016
AnnaBridge	143:86740a56073b	1017	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN))
AnnaBridge	143:86740a56073b	1018	#define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN))
AnnaBridge	143:86740a56073b	1019
AnnaBridge	143:86740a56073b	1020	/**
AnnaBridge	143:86740a56073b	1021	* @}
AnnaBridge	143:86740a56073b	1022	*/
AnnaBridge	143:86740a56073b	1023
AnnaBridge	143:86740a56073b	1024	/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge	143:86740a56073b	1025	* @brief Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge	143:86740a56073b	1026	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	143:86740a56073b	1027	* power consumption.
AnnaBridge	143:86740a56073b	1028	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	143:86740a56073b	1029	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	143:86740a56073b	1030	* @{
AnnaBridge	143:86740a56073b	1031	*/
AnnaBridge	143:86740a56073b	1032	#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != RESET)
AnnaBridge	143:86740a56073b	1033	#define __HAL_RCC_MIF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) != RESET)
AnnaBridge	143:86740a56073b	1034	#define __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != RESET)
AnnaBridge	143:86740a56073b	1035	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != RESET)
AnnaBridge	167:84c0a372a020	1036	#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) == RESET)
AnnaBridge	167:84c0a372a020	1037	#define __HAL_RCC_MIF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) == RESET)
AnnaBridge	167:84c0a372a020	1038	#define __HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) == RESET)
AnnaBridge	167:84c0a372a020	1039	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) == RESET)
AnnaBridge	143:86740a56073b	1040
AnnaBridge	143:86740a56073b	1041	/**
AnnaBridge	143:86740a56073b	1042	* @}
AnnaBridge	143:86740a56073b	1043	*/
AnnaBridge	143:86740a56073b	1044
AnnaBridge	143:86740a56073b	1045	/** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable_Status IOPORT Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge	143:86740a56073b	1046	* @brief Check whether the IOPORT peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge	143:86740a56073b	1047	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	143:86740a56073b	1048	* power consumption.
AnnaBridge	143:86740a56073b	1049	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	143:86740a56073b	1050	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	143:86740a56073b	1051	* @{
AnnaBridge	143:86740a56073b	1052	*/
AnnaBridge	143:86740a56073b	1053	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) != RESET)
AnnaBridge	143:86740a56073b	1054	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) != RESET)
AnnaBridge	143:86740a56073b	1055	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) != RESET)
AnnaBridge	143:86740a56073b	1056	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOHSMEN) != RESET)
AnnaBridge	167:84c0a372a020	1057	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) == RESET)
AnnaBridge	167:84c0a372a020	1058	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) == RESET)
AnnaBridge	167:84c0a372a020	1059	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) == RESET)
AnnaBridge	167:84c0a372a020	1060	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOHSMEN) == RESET)
AnnaBridge	143:86740a56073b	1061
AnnaBridge	143:86740a56073b	1062	/**
AnnaBridge	143:86740a56073b	1063	* @}
AnnaBridge	143:86740a56073b	1064	*/
AnnaBridge	143:86740a56073b	1065
AnnaBridge	143:86740a56073b	1066	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge	143:86740a56073b	1067	* @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge	143:86740a56073b	1068	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	143:86740a56073b	1069	* power consumption.
AnnaBridge	143:86740a56073b	1070	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	143:86740a56073b	1071	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	143:86740a56073b	1072	* @{
AnnaBridge	143:86740a56073b	1073	*/
AnnaBridge	143:86740a56073b	1074	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_WWDGSMEN) != RESET)
AnnaBridge	143:86740a56073b	1075	#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_PWRSMEN) != RESET)
AnnaBridge	167:84c0a372a020	1076	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_WWDGSMEN) == RESET)
AnnaBridge	167:84c0a372a020	1077	#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_PWRSMEN) == RESET)
AnnaBridge	143:86740a56073b	1078
AnnaBridge	143:86740a56073b	1079	/**
AnnaBridge	143:86740a56073b	1080	* @}
AnnaBridge	143:86740a56073b	1081	*/
AnnaBridge	143:86740a56073b	1082
AnnaBridge	143:86740a56073b	1083	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge	143:86740a56073b	1084	* @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge	143:86740a56073b	1085	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	143:86740a56073b	1086	* power consumption.
AnnaBridge	143:86740a56073b	1087	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	143:86740a56073b	1088	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	143:86740a56073b	1089	* @{
AnnaBridge	143:86740a56073b	1090	*/
AnnaBridge	143:86740a56073b	1091	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
AnnaBridge	143:86740a56073b	1092	#define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DBGMCUSMEN) != RESET)
AnnaBridge	167:84c0a372a020	1093	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET)
AnnaBridge	167:84c0a372a020	1094	#define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DBGMCUSMEN) == RESET)
AnnaBridge	143:86740a56073b	1095
AnnaBridge	143:86740a56073b	1096	/**
AnnaBridge	143:86740a56073b	1097	* @}
AnnaBridge	143:86740a56073b	1098	*/
AnnaBridge	167:84c0a372a020	1099	/** @defgroup RCC_HSI_Configuration HSI Configuration
AnnaBridge	143:86740a56073b	1100	* @{
AnnaBridge	143:86740a56073b	1101	*/
AnnaBridge	143:86740a56073b	1102
AnnaBridge	167:84c0a372a020	1103	/** @brief Macro to enable or disable the Internal High Speed oscillator (HSI).
AnnaBridge	167:84c0a372a020	1104	* @note After enabling the HSI, the application software should wait on
AnnaBridge	167:84c0a372a020	1105	* HSIRDY flag to be set indicating that HSI clock is stable and can
AnnaBridge	167:84c0a372a020	1106	* be used to clock the PLL and/or system clock.
AnnaBridge	167:84c0a372a020	1107	* @note HSI can not be stopped if it is used directly or through the PLL
AnnaBridge	167:84c0a372a020	1108	* as system clock. In this case, you have to select another source
AnnaBridge	167:84c0a372a020	1109	* of the system clock then stop the HSI.
AnnaBridge	167:84c0a372a020	1110	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	167:84c0a372a020	1111	* @param __STATE__ specifies the new state of the HSI.
AnnaBridge	167:84c0a372a020	1112	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1113	* @arg @ref RCC_HSI_OFF turn OFF the HSI oscillator
AnnaBridge	167:84c0a372a020	1114	* @arg @ref RCC_HSI_ON turn ON the HSI oscillator
AnnaBridge	167:84c0a372a020	1115	* @arg @ref RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4
AnnaBridge	167:84c0a372a020	1116	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
AnnaBridge	167:84c0a372a020	1117	* clock cycles.
AnnaBridge	143:86740a56073b	1118	*/
AnnaBridge	167:84c0a372a020	1119	#define __HAL_RCC_HSI_CONFIG(__STATE__) \
AnnaBridge	167:84c0a372a020	1120	MODIFY_REG(RCC->CR, RCC_CR_HSION \| RCC_CR_HSIDIVEN , (uint32_t)(__STATE__))
AnnaBridge	143:86740a56073b	1121
AnnaBridge	143:86740a56073b	1122	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
AnnaBridge	143:86740a56073b	1123	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	143:86740a56073b	1124	* It is used (enabled by hardware) as system clock source after startup
AnnaBridge	143:86740a56073b	1125	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
AnnaBridge	143:86740a56073b	1126	* of the HSE used directly or indirectly as system clock (if the Clock
AnnaBridge	143:86740a56073b	1127	* Security System CSS is enabled).
AnnaBridge	143:86740a56073b	1128	* @note HSI can not be stopped if it is used as system clock source. In this case,
AnnaBridge	143:86740a56073b	1129	* you have to select another source of the system clock then stop the HSI.
AnnaBridge	143:86740a56073b	1130	* @note After enabling the HSI, the application software should wait on HSIRDY
AnnaBridge	143:86740a56073b	1131	* flag to be set indicating that HSI clock is stable and can be used as
AnnaBridge	167:84c0a372a020	1132	* system clock source.
AnnaBridge	143:86740a56073b	1133	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
AnnaBridge	143:86740a56073b	1134	* clock cycles.
AnnaBridge	143:86740a56073b	1135	*/
AnnaBridge	143:86740a56073b	1136	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
AnnaBridge	143:86740a56073b	1137	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
AnnaBridge	143:86740a56073b	1138
AnnaBridge	143:86740a56073b	1139	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
AnnaBridge	143:86740a56073b	1140	* @note The calibration is used to compensate for the variations in voltage
AnnaBridge	143:86740a56073b	1141	* and temperature that influence the frequency of the internal HSI RC.
AnnaBridge	167:84c0a372a020	1142	* @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
AnnaBridge	167:84c0a372a020	1143	* (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge	143:86740a56073b	1144	* This parameter must be a number between 0 and 0x1F.
AnnaBridge	167:84c0a372a020	1145	*/
AnnaBridge	167:84c0a372a020	1146	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
AnnaBridge	167:84c0a372a020	1147	(MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << 8))
AnnaBridge	143:86740a56073b	1148
AnnaBridge	143:86740a56073b	1149	/**
AnnaBridge	167:84c0a372a020	1150	* @}
AnnaBridge	143:86740a56073b	1151	*/
AnnaBridge	143:86740a56073b	1152
AnnaBridge	167:84c0a372a020	1153	/** @defgroup RCC_LSI_Configuration LSI Configuration
AnnaBridge	167:84c0a372a020	1154	* @{
AnnaBridge	143:86740a56073b	1155	*/
AnnaBridge	143:86740a56073b	1156
AnnaBridge	167:84c0a372a020	1157	/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
AnnaBridge	143:86740a56073b	1158	* @note After enabling the LSI, the application software should wait on
AnnaBridge	143:86740a56073b	1159	* LSIRDY flag to be set indicating that LSI clock is stable and can
AnnaBridge	143:86740a56073b	1160	* be used to clock the IWDG and/or the RTC.
AnnaBridge	167:84c0a372a020	1161	*/
AnnaBridge	167:84c0a372a020	1162	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
AnnaBridge	167:84c0a372a020	1163
AnnaBridge	167:84c0a372a020	1164	/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
AnnaBridge	167:84c0a372a020	1165	* @note LSI can not be disabled if the IWDG is running.
AnnaBridge	143:86740a56073b	1166	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
AnnaBridge	143:86740a56073b	1167	* clock cycles.
AnnaBridge	143:86740a56073b	1168	*/
AnnaBridge	143:86740a56073b	1169	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
AnnaBridge	143:86740a56073b	1170
AnnaBridge	143:86740a56073b	1171	/**
AnnaBridge	167:84c0a372a020	1172	* @}
AnnaBridge	167:84c0a372a020	1173	*/
AnnaBridge	167:84c0a372a020	1174
AnnaBridge	167:84c0a372a020	1175	/** @defgroup RCC_HSE_Configuration HSE Configuration
AnnaBridge	167:84c0a372a020	1176	* @{
AnnaBridge	167:84c0a372a020	1177	*/
AnnaBridge	167:84c0a372a020	1178
AnnaBridge	167:84c0a372a020	1179	/**
AnnaBridge	143:86740a56073b	1180	* @brief Macro to configure the External High Speed oscillator (HSE).
AnnaBridge	143:86740a56073b	1181	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
AnnaBridge	143:86740a56073b	1182	* supported by this macro. User should request a transition to HSE Off
AnnaBridge	143:86740a56073b	1183	* first and then HSE On or HSE Bypass.
AnnaBridge	143:86740a56073b	1184	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
AnnaBridge	143:86740a56073b	1185	* software should wait on HSERDY flag to be set indicating that HSE clock
AnnaBridge	143:86740a56073b	1186	* is stable and can be used to clock the PLL and/or system clock.
AnnaBridge	143:86740a56073b	1187	* @note HSE state can not be changed if it is used directly or through the
AnnaBridge	143:86740a56073b	1188	* PLL as system clock. In this case, you have to select another source
AnnaBridge	143:86740a56073b	1189	* of the system clock then change the HSE state (ex. disable it).
AnnaBridge	167:84c0a372a020	1190	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	143:86740a56073b	1191	* @note This function reset the CSSON bit, so if the clock security system(CSS)
AnnaBridge	143:86740a56073b	1192	* was previously enabled you have to enable it again after calling this
AnnaBridge	167:84c0a372a020	1193	* function.
AnnaBridge	167:84c0a372a020	1194	* @param __STATE__ specifies the new state of the HSE.
AnnaBridge	167:84c0a372a020	1195	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1196	* @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
AnnaBridge	143:86740a56073b	1197	* 6 HSE oscillator clock cycles.
AnnaBridge	167:84c0a372a020	1198	* @arg @ref RCC_HSE_ON turn ON the HSE oscillator
AnnaBridge	167:84c0a372a020	1199	* @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
AnnaBridge	143:86740a56073b	1200	*/
AnnaBridge	167:84c0a372a020	1201	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
AnnaBridge	167:84c0a372a020	1202	do{ \
AnnaBridge	167:84c0a372a020	1203	__IO uint32_t tmpreg; \
AnnaBridge	167:84c0a372a020	1204	if ((__STATE__) == RCC_HSE_ON) \
AnnaBridge	167:84c0a372a020	1205	{ \
AnnaBridge	167:84c0a372a020	1206	SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	167:84c0a372a020	1207	} \
AnnaBridge	167:84c0a372a020	1208	else if ((__STATE__) == RCC_HSE_BYPASS) \
AnnaBridge	167:84c0a372a020	1209	{ \
AnnaBridge	167:84c0a372a020	1210	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge	167:84c0a372a020	1211	SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	167:84c0a372a020	1212	} \
AnnaBridge	167:84c0a372a020	1213	else \
AnnaBridge	167:84c0a372a020	1214	{ \
AnnaBridge	167:84c0a372a020	1215	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	167:84c0a372a020	1216	/* Delay after an RCC peripheral clock */ \
AnnaBridge	167:84c0a372a020	1217	tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	167:84c0a372a020	1218	UNUSED(tmpreg); \
AnnaBridge	167:84c0a372a020	1219	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge	167:84c0a372a020	1220	} \
AnnaBridge	167:84c0a372a020	1221	}while(0)
AnnaBridge	167:84c0a372a020	1222
AnnaBridge	167:84c0a372a020	1223	/**
AnnaBridge	167:84c0a372a020	1224	* @}
AnnaBridge	167:84c0a372a020	1225	*/
AnnaBridge	167:84c0a372a020	1226
AnnaBridge	167:84c0a372a020	1227	/** @defgroup RCC_LSE_Configuration LSE Configuration
AnnaBridge	167:84c0a372a020	1228	* @{
AnnaBridge	167:84c0a372a020	1229	*/
AnnaBridge	143:86740a56073b	1230
AnnaBridge	143:86740a56073b	1231	/**
AnnaBridge	143:86740a56073b	1232	* @brief Macro to configure the External Low Speed oscillator (LSE).
AnnaBridge	167:84c0a372a020	1233	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
AnnaBridge	143:86740a56073b	1234	* @note As the LSE is in the Backup domain and write access is denied to
AnnaBridge	167:84c0a372a020	1235	* this domain after reset, you have to enable write access using
AnnaBridge	167:84c0a372a020	1236	* @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
AnnaBridge	167:84c0a372a020	1237	* (to be done once after reset).
AnnaBridge	143:86740a56073b	1238	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
AnnaBridge	143:86740a56073b	1239	* software should wait on LSERDY flag to be set indicating that LSE clock
AnnaBridge	143:86740a56073b	1240	* is stable and can be used to clock the RTC.
AnnaBridge	167:84c0a372a020	1241	* @param __STATE__ specifies the new state of the LSE.
AnnaBridge	143:86740a56073b	1242	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1243	* @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
AnnaBridge	143:86740a56073b	1244	* 6 LSE oscillator clock cycles.
AnnaBridge	167:84c0a372a020	1245	* @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
AnnaBridge	167:84c0a372a020	1246	* @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
AnnaBridge	143:86740a56073b	1247	*/
AnnaBridge	167:84c0a372a020	1248	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
AnnaBridge	167:84c0a372a020	1249	do{ \
AnnaBridge	167:84c0a372a020	1250	if ((__STATE__) == RCC_LSE_ON) \
AnnaBridge	167:84c0a372a020	1251	{ \
AnnaBridge	167:84c0a372a020	1252	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
AnnaBridge	167:84c0a372a020	1253	} \
AnnaBridge	167:84c0a372a020	1254	else if ((__STATE__) == RCC_LSE_OFF) \
AnnaBridge	167:84c0a372a020	1255	{ \
AnnaBridge	167:84c0a372a020	1256	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
AnnaBridge	167:84c0a372a020	1257	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
AnnaBridge	167:84c0a372a020	1258	} \
AnnaBridge	167:84c0a372a020	1259	else if ((__STATE__) == RCC_LSE_BYPASS) \
AnnaBridge	167:84c0a372a020	1260	{ \
AnnaBridge	167:84c0a372a020	1261	SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
AnnaBridge	167:84c0a372a020	1262	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
AnnaBridge	167:84c0a372a020	1263	} \
AnnaBridge	167:84c0a372a020	1264	else \
AnnaBridge	167:84c0a372a020	1265	{ \
AnnaBridge	167:84c0a372a020	1266	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
AnnaBridge	167:84c0a372a020	1267	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
AnnaBridge	167:84c0a372a020	1268	} \
AnnaBridge	167:84c0a372a020	1269	}while(0)
AnnaBridge	143:86740a56073b	1270
AnnaBridge	143:86740a56073b	1271	/**
AnnaBridge	167:84c0a372a020	1272	* @}
AnnaBridge	167:84c0a372a020	1273	*/
AnnaBridge	167:84c0a372a020	1274
AnnaBridge	167:84c0a372a020	1275	/** @defgroup RCC_MSI_Configuration MSI Configuration
AnnaBridge	167:84c0a372a020	1276	* @{
AnnaBridge	167:84c0a372a020	1277	*/
AnnaBridge	167:84c0a372a020	1278
AnnaBridge	167:84c0a372a020	1279	/** @brief Macro to enable Internal Multi Speed oscillator (MSI).
AnnaBridge	167:84c0a372a020	1280	* @note After enabling the MSI, the application software should wait on MSIRDY
AnnaBridge	167:84c0a372a020	1281	* flag to be set indicating that MSI clock is stable and can be used as
AnnaBridge	167:84c0a372a020	1282	* system clock source.
AnnaBridge	143:86740a56073b	1283	*/
AnnaBridge	167:84c0a372a020	1284	#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
AnnaBridge	167:84c0a372a020	1285
AnnaBridge	167:84c0a372a020	1286	/** @brief Macro to disable the Internal Multi Speed oscillator (MSI).
AnnaBridge	167:84c0a372a020	1287	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	167:84c0a372a020	1288	* It is used (enabled by hardware) as system clock source after startup
AnnaBridge	167:84c0a372a020	1289	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
AnnaBridge	167:84c0a372a020	1290	* of the HSE used directly or indirectly as system clock (if the Clock
AnnaBridge	167:84c0a372a020	1291	* Security System CSS is enabled).
AnnaBridge	167:84c0a372a020	1292	* @note MSI can not be stopped if it is used as system clock source. In this case,
AnnaBridge	167:84c0a372a020	1293	* you have to select another source of the system clock then stop the MSI.
AnnaBridge	167:84c0a372a020	1294	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
AnnaBridge	167:84c0a372a020	1295	* clock cycles.
AnnaBridge	167:84c0a372a020	1296	*/
AnnaBridge	167:84c0a372a020	1297	#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
AnnaBridge	143:86740a56073b	1298
AnnaBridge	167:84c0a372a020	1299	/** @brief Macro adjusts Internal Multi Speed oscillator (MSI) calibration value.
AnnaBridge	167:84c0a372a020	1300	* @note The calibration is used to compensate for the variations in voltage
AnnaBridge	167:84c0a372a020	1301	* and temperature that influence the frequency of the internal MSI RC.
AnnaBridge	167:84c0a372a020	1302	* Refer to the Application Note AN3300 for more details on how to
AnnaBridge	167:84c0a372a020	1303	* calibrate the MSI.
AnnaBridge	167:84c0a372a020	1304	* @param _MSICALIBRATIONVALUE_ specifies the calibration trimming value.
AnnaBridge	167:84c0a372a020	1305	* (default is RCC_MSICALIBRATION_DEFAULT).
AnnaBridge	167:84c0a372a020	1306	* This parameter must be a number between 0 and 0xFF.
AnnaBridge	167:84c0a372a020	1307	*/
AnnaBridge	167:84c0a372a020	1308	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \
AnnaBridge	167:84c0a372a020	1309	(MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << 24))
AnnaBridge	167:84c0a372a020	1310
AnnaBridge	167:84c0a372a020	1311	/* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
AnnaBridge	167:84c0a372a020	1312	* @note After restart from Reset or wakeup from STANDBY, the MSI clock is
AnnaBridge	167:84c0a372a020	1313	* around 2.097 MHz. The MSI clock does not change after wake-up from
AnnaBridge	167:84c0a372a020	1314	* STOP mode.
AnnaBridge	167:84c0a372a020	1315	* @note The MSI clock range can be modified on the fly.
AnnaBridge	167:84c0a372a020	1316	* @param _MSIRANGEVALUE_ specifies the MSI Clock range.
AnnaBridge	167:84c0a372a020	1317	* This parameter must be one of the following values:
AnnaBridge	167:84c0a372a020	1318	* @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz
AnnaBridge	167:84c0a372a020	1319	* @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz
AnnaBridge	167:84c0a372a020	1320	* @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz
AnnaBridge	167:84c0a372a020	1321	* @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz
AnnaBridge	167:84c0a372a020	1322	* @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz
AnnaBridge	167:84c0a372a020	1323	* @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
AnnaBridge	167:84c0a372a020	1324	* @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz
AnnaBridge	167:84c0a372a020	1325	*/
AnnaBridge	167:84c0a372a020	1326	#define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, \
AnnaBridge	167:84c0a372a020	1327	RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_)))
AnnaBridge	143:86740a56073b	1328
AnnaBridge	167:84c0a372a020	1329	/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
AnnaBridge	167:84c0a372a020	1330	* @retval MSI clock range.
AnnaBridge	167:84c0a372a020	1331	* This parameter must be one of the following values:
AnnaBridge	167:84c0a372a020	1332	* @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz
AnnaBridge	167:84c0a372a020	1333	* @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz
AnnaBridge	167:84c0a372a020	1334	* @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz
AnnaBridge	167:84c0a372a020	1335	* @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz
AnnaBridge	167:84c0a372a020	1336	* @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz
AnnaBridge	167:84c0a372a020	1337	* @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
AnnaBridge	167:84c0a372a020	1338	* @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz
AnnaBridge	143:86740a56073b	1339	*/
AnnaBridge	167:84c0a372a020	1340	#define __HAL_RCC_GET_MSI_RANGE() (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE))
AnnaBridge	167:84c0a372a020	1341
AnnaBridge	167:84c0a372a020	1342	/**
AnnaBridge	167:84c0a372a020	1343	* @}
AnnaBridge	167:84c0a372a020	1344	*/
AnnaBridge	143:86740a56073b	1345
AnnaBridge	167:84c0a372a020	1346	/** @defgroup RCC_PLL_Configuration PLL Configuration
AnnaBridge	167:84c0a372a020	1347	* @{
AnnaBridge	167:84c0a372a020	1348	*/
AnnaBridge	167:84c0a372a020	1349
AnnaBridge	167:84c0a372a020	1350	/** @brief Macro to enable the main PLL.
AnnaBridge	143:86740a56073b	1351	* @note After enabling the main PLL, the application software should wait on
AnnaBridge	143:86740a56073b	1352	* PLLRDY flag to be set indicating that PLL clock is stable and can
AnnaBridge	143:86740a56073b	1353	* be used as system clock source.
AnnaBridge	143:86740a56073b	1354	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	143:86740a56073b	1355	*/
AnnaBridge	167:84c0a372a020	1356	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
AnnaBridge	167:84c0a372a020	1357
AnnaBridge	167:84c0a372a020	1358	/** @brief Macro to disable the main PLL.
AnnaBridge	167:84c0a372a020	1359	* @note The main PLL can not be disabled if it is used as system clock source
AnnaBridge	167:84c0a372a020	1360	*/
AnnaBridge	143:86740a56073b	1361	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
AnnaBridge	143:86740a56073b	1362
AnnaBridge	167:84c0a372a020	1363	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
AnnaBridge	143:86740a56073b	1364	* @note This function must be used only when the main PLL is disabled.
AnnaBridge	167:84c0a372a020	1365	*
AnnaBridge	167:84c0a372a020	1366	* @param __RCC_PLLSOURCE__ specifies the PLL entry clock source.
AnnaBridge	167:84c0a372a020	1367	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1368	* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
AnnaBridge	167:84c0a372a020	1369	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
AnnaBridge	167:84c0a372a020	1370	* @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
AnnaBridge	167:84c0a372a020	1371	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1372	* @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3
AnnaBridge	167:84c0a372a020	1373	* @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4
AnnaBridge	167:84c0a372a020	1374	* @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6
AnnaBridge	167:84c0a372a020	1375	* @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8
AnnaBridge	167:84c0a372a020	1376	* @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12
AnnaBridge	167:84c0a372a020	1377	* @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16
AnnaBridge	167:84c0a372a020	1378	* @arg @ref RCC_PLL_MUL24 PLLVCO = PLL clock entry x 24
AnnaBridge	167:84c0a372a020	1379	* @arg @ref RCC_PLL_MUL32 PLLVCO = PLL clock entry x 32
AnnaBridge	167:84c0a372a020	1380	* @arg @ref RCC_PLL_MUL48 PLLVCO = PLL clock entry x 48
AnnaBridge	167:84c0a372a020	1381	* @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
AnnaBridge	167:84c0a372a020	1382	* Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
AnnaBridge	167:84c0a372a020	1383	* in Range 3.
AnnaBridge	167:84c0a372a020	1384	*
AnnaBridge	167:84c0a372a020	1385	* @param __PLLDIV__ specifies the division factor for PLL VCO input clock
AnnaBridge	167:84c0a372a020	1386	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1387	* @arg @ref RCC_PLL_DIV2 PLL clock output = PLLVCO / 2
AnnaBridge	167:84c0a372a020	1388	* @arg @ref RCC_PLL_DIV3 PLL clock output = PLLVCO / 3
AnnaBridge	167:84c0a372a020	1389	* @arg @ref RCC_PLL_DIV4 PLL clock output = PLLVCO / 4
AnnaBridge	167:84c0a372a020	1390	*
AnnaBridge	167:84c0a372a020	1391	*/
AnnaBridge	167:84c0a372a020	1392	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\
AnnaBridge	167:84c0a372a020	1393	MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC\|RCC_CFGR_PLLMUL\|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) \| (__PLLMUL__) \| (__PLLDIV__)))
AnnaBridge	167:84c0a372a020	1394
AnnaBridge	167:84c0a372a020	1395	/** @brief Get oscillator clock selected as PLL input clock
AnnaBridge	167:84c0a372a020	1396	* @retval The clock source used for PLL entry. The returned value can be one
AnnaBridge	167:84c0a372a020	1397	* of the following:
AnnaBridge	167:84c0a372a020	1398	* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock
AnnaBridge	167:84c0a372a020	1399	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
AnnaBridge	167:84c0a372a020	1400	*/
AnnaBridge	167:84c0a372a020	1401	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
AnnaBridge	167:84c0a372a020	1402
AnnaBridge	167:84c0a372a020	1403	/**
AnnaBridge	167:84c0a372a020	1404	* @}
AnnaBridge	143:86740a56073b	1405	*/
AnnaBridge	143:86740a56073b	1406
AnnaBridge	167:84c0a372a020	1407	/** @defgroup RCC_Get_Clock_source Get Clock source
AnnaBridge	167:84c0a372a020	1408	* @{
AnnaBridge	143:86740a56073b	1409	*/
AnnaBridge	143:86740a56073b	1410
AnnaBridge	143:86740a56073b	1411	/**
AnnaBridge	143:86740a56073b	1412	* @brief Macro to configure the system clock source.
AnnaBridge	167:84c0a372a020	1413	* @param __SYSCLKSOURCE__ specifies the system clock source.
AnnaBridge	143:86740a56073b	1414	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1415	* @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source.
AnnaBridge	167:84c0a372a020	1416	* @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
AnnaBridge	167:84c0a372a020	1417	* @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
AnnaBridge	167:84c0a372a020	1418	* @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
AnnaBridge	143:86740a56073b	1419	*/
AnnaBridge	143:86740a56073b	1420	#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
AnnaBridge	143:86740a56073b	1421	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
AnnaBridge	143:86740a56073b	1422
AnnaBridge	143:86740a56073b	1423	/** @brief Macro to get the clock source used as system clock.
AnnaBridge	143:86740a56073b	1424	* @retval The clock source used as system clock. The returned value can be one
AnnaBridge	143:86740a56073b	1425	* of the following:
AnnaBridge	167:84c0a372a020	1426	* @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock
AnnaBridge	167:84c0a372a020	1427	* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
AnnaBridge	167:84c0a372a020	1428	* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
AnnaBridge	167:84c0a372a020	1429	* @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
AnnaBridge	143:86740a56073b	1430	*/
AnnaBridge	167:84c0a372a020	1431	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
AnnaBridge	143:86740a56073b	1432
AnnaBridge	167:84c0a372a020	1433	/**
AnnaBridge	167:84c0a372a020	1434	* @}
AnnaBridge	167:84c0a372a020	1435	*/
AnnaBridge	167:84c0a372a020	1436
AnnaBridge	167:84c0a372a020	1437	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
AnnaBridge	167:84c0a372a020	1438	* @{
AnnaBridge	167:84c0a372a020	1439	*/
AnnaBridge	143:86740a56073b	1440
AnnaBridge	143:86740a56073b	1441	/** @brief Macro to configure the MCO clock.
AnnaBridge	143:86740a56073b	1442	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
AnnaBridge	143:86740a56073b	1443	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1444	* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
AnnaBridge	167:84c0a372a020	1445	* @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
AnnaBridge	167:84c0a372a020	1446	* @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock
AnnaBridge	167:84c0a372a020	1447	* @arg @ref RCC_MCO1SOURCE_MSI MSI oscillator clock selected as MCO clock
AnnaBridge	167:84c0a372a020	1448	* @arg @ref RCC_MCO1SOURCE_HSE HSE oscillator clock selected as MCO clock
AnnaBridge	167:84c0a372a020	1449	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock selected as MCO clock
AnnaBridge	167:84c0a372a020	1450	* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO clock
AnnaBridge	167:84c0a372a020	1451	* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO clock
AnnaBridge	167:84c0a372a020	1452	@if STM32L052xx
AnnaBridge	167:84c0a372a020	1453	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
AnnaBridge	167:84c0a372a020	1454	@elseif STM32L053xx
AnnaBridge	167:84c0a372a020	1455	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
AnnaBridge	167:84c0a372a020	1456	@elseif STM32L062xx
AnnaBridge	167:84c0a372a020	1457	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
AnnaBridge	167:84c0a372a020	1458	@elseif STM32L063xx
AnnaBridge	167:84c0a372a020	1459	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
AnnaBridge	167:84c0a372a020	1460	@elseif STM32L072xx
AnnaBridge	167:84c0a372a020	1461	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
AnnaBridge	167:84c0a372a020	1462	@elseif STM32L073xx
AnnaBridge	167:84c0a372a020	1463	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
AnnaBridge	167:84c0a372a020	1464	@elseif STM32L082xx
AnnaBridge	167:84c0a372a020	1465	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
AnnaBridge	167:84c0a372a020	1466	@elseif STM32L083xx
AnnaBridge	167:84c0a372a020	1467	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock
AnnaBridge	167:84c0a372a020	1468	@endif
AnnaBridge	143:86740a56073b	1469	* @param __MCODIV__ specifies the MCO clock prescaler.
AnnaBridge	143:86740a56073b	1470	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1471	* @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
AnnaBridge	167:84c0a372a020	1472	* @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
AnnaBridge	167:84c0a372a020	1473	* @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
AnnaBridge	167:84c0a372a020	1474	* @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
AnnaBridge	167:84c0a372a020	1475	* @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
AnnaBridge	143:86740a56073b	1476	*/
AnnaBridge	143:86740a56073b	1477	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
AnnaBridge	143:86740a56073b	1478	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL \| RCC_CFGR_MCO_PRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
AnnaBridge	143:86740a56073b	1479
AnnaBridge	167:84c0a372a020	1480	/**
AnnaBridge	167:84c0a372a020	1481	* @}
AnnaBridge	167:84c0a372a020	1482	*/
AnnaBridge	143:86740a56073b	1483
AnnaBridge	167:84c0a372a020	1484	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
AnnaBridge	167:84c0a372a020	1485	* @{
AnnaBridge	167:84c0a372a020	1486	*/
AnnaBridge	167:84c0a372a020	1487
AnnaBridge	167:84c0a372a020	1488	/** @brief Macro to configure the RTC clock (RTCCLK).
AnnaBridge	167:84c0a372a020	1489	* @note As the RTC clock configuration bits are in the Backup domain and write
AnnaBridge	167:84c0a372a020	1490	* access is denied to this domain after reset, you have to enable write
AnnaBridge	167:84c0a372a020	1491	* access using the Power Backup Access macro before to configure
AnnaBridge	167:84c0a372a020	1492	* the RTC clock source (to be done once after reset).
AnnaBridge	167:84c0a372a020	1493	* @note Once the RTC clock is configured it cannot be changed unless the
AnnaBridge	167:84c0a372a020	1494	* Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
AnnaBridge	167:84c0a372a020	1495	* a Power On Reset (POR).
AnnaBridge	167:84c0a372a020	1496	* @note RTC prescaler cannot be modified if HSE is enabled (HSEON = 1).
AnnaBridge	167:84c0a372a020	1497	*
AnnaBridge	167:84c0a372a020	1498	* @param __RTC_CLKSOURCE__ specifies the RTC clock source.
AnnaBridge	167:84c0a372a020	1499	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1500	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
AnnaBridge	167:84c0a372a020	1501	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
AnnaBridge	167:84c0a372a020	1502	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
AnnaBridge	167:84c0a372a020	1503	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as RTC clock
AnnaBridge	167:84c0a372a020	1504	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as RTC clock
AnnaBridge	167:84c0a372a020	1505	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock
AnnaBridge	167:84c0a372a020	1506	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as RTC clock
AnnaBridge	167:84c0a372a020	1507	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
AnnaBridge	167:84c0a372a020	1508	* work in STOP and STANDBY modes, and can be used as wakeup source.
AnnaBridge	167:84c0a372a020	1509	* However, when the HSE clock is used as RTC clock source, the RTC
AnnaBridge	167:84c0a372a020	1510	* cannot be used in STOP and STANDBY modes.
AnnaBridge	167:84c0a372a020	1511	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
AnnaBridge	167:84c0a372a020	1512	* RTC clock source).
AnnaBridge	167:84c0a372a020	1513	*/
AnnaBridge	167:84c0a372a020	1514	#define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \
AnnaBridge	167:84c0a372a020	1515	if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE) \
AnnaBridge	167:84c0a372a020	1516	{ \
AnnaBridge	167:84c0a372a020	1517	MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE)); \
AnnaBridge	167:84c0a372a020	1518	} \
AnnaBridge	167:84c0a372a020	1519	} while (0)
AnnaBridge	167:84c0a372a020	1520
AnnaBridge	167:84c0a372a020	1521	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \
AnnaBridge	167:84c0a372a020	1522	__HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \
AnnaBridge	167:84c0a372a020	1523	RCC->CSR \|= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \
AnnaBridge	167:84c0a372a020	1524	} while (0)
AnnaBridge	167:84c0a372a020	1525
AnnaBridge	167:84c0a372a020	1526	/** @brief Macro to get the RTC clock source.
AnnaBridge	167:84c0a372a020	1527	* @retval The clock source can be one of the following values:
AnnaBridge	167:84c0a372a020	1528	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
AnnaBridge	167:84c0a372a020	1529	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
AnnaBridge	167:84c0a372a020	1530	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
AnnaBridge	167:84c0a372a020	1531	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
AnnaBridge	167:84c0a372a020	1532	*/
AnnaBridge	167:84c0a372a020	1533	#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL))
AnnaBridge	167:84c0a372a020	1534
AnnaBridge	167:84c0a372a020	1535	/**
AnnaBridge	167:84c0a372a020	1536	* @brief Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK).
AnnaBridge	167:84c0a372a020	1537	*
AnnaBridge	167:84c0a372a020	1538	* @retval Returned value can be one of the following values:
AnnaBridge	167:84c0a372a020	1539	* @arg @ref RCC_RTC_HSE_DIV_2 HSE divided by 2 selected as RTC clock
AnnaBridge	167:84c0a372a020	1540	* @arg @ref RCC_RTC_HSE_DIV_4 HSE divided by 4 selected as RTC clock
AnnaBridge	167:84c0a372a020	1541	* @arg @ref RCC_RTC_HSE_DIV_8 HSE divided by 8 selected as RTC clock
AnnaBridge	167:84c0a372a020	1542	* @arg @ref RCC_RTC_HSE_DIV_16 HSE divided by 16 selected as RTC clock
AnnaBridge	167:84c0a372a020	1543	*
AnnaBridge	167:84c0a372a020	1544	*/
AnnaBridge	167:84c0a372a020	1545	#define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)))
AnnaBridge	167:84c0a372a020	1546
AnnaBridge	167:84c0a372a020	1547	/** @brief Macro to enable the the RTC clock.
AnnaBridge	167:84c0a372a020	1548	* @note These macros must be used only after the RTC clock source was selected.
AnnaBridge	167:84c0a372a020	1549	*/
AnnaBridge	167:84c0a372a020	1550	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN)
AnnaBridge	167:84c0a372a020	1551
AnnaBridge	167:84c0a372a020	1552	/** @brief Macro to disable the the RTC clock.
AnnaBridge	167:84c0a372a020	1553	* @note These macros must be used only after the RTC clock source was selected.
AnnaBridge	167:84c0a372a020	1554	*/
AnnaBridge	167:84c0a372a020	1555	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN)
AnnaBridge	167:84c0a372a020	1556
AnnaBridge	167:84c0a372a020	1557	/** @brief Macro to force the Backup domain reset.
AnnaBridge	167:84c0a372a020	1558	* @note This function resets the RTC peripheral (including the backup registers)
AnnaBridge	167:84c0a372a020	1559	* and the RTC clock source selection in RCC_CSR register.
AnnaBridge	167:84c0a372a020	1560	* @note The BKPSRAM is not affected by this reset.
AnnaBridge	167:84c0a372a020	1561	*/
AnnaBridge	167:84c0a372a020	1562	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR, RCC_CSR_RTCRST)
AnnaBridge	167:84c0a372a020	1563
AnnaBridge	167:84c0a372a020	1564	/** @brief Macros to release the Backup domain reset.
AnnaBridge	167:84c0a372a020	1565	*/
AnnaBridge	167:84c0a372a020	1566	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST)
AnnaBridge	167:84c0a372a020	1567
AnnaBridge	167:84c0a372a020	1568	/**
AnnaBridge	167:84c0a372a020	1569	* @}
AnnaBridge	167:84c0a372a020	1570	*/
AnnaBridge	167:84c0a372a020	1571
AnnaBridge	167:84c0a372a020	1572	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
AnnaBridge	143:86740a56073b	1573	* @brief macros to manage the specified RCC Flags and interrupts.
AnnaBridge	143:86740a56073b	1574	* @{
AnnaBridge	143:86740a56073b	1575	*/
AnnaBridge	143:86740a56073b	1576
AnnaBridge	167:84c0a372a020	1577	/** @brief Enable RCC interrupt.
AnnaBridge	143:86740a56073b	1578	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
AnnaBridge	143:86740a56073b	1579	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
AnnaBridge	143:86740a56073b	1580	* automatically generated. The NMI will be executed indefinitely, and
AnnaBridge	143:86740a56073b	1581	* since NMI has higher priority than any other IRQ (and main program)
AnnaBridge	143:86740a56073b	1582	* the application will be stacked in the NMI ISR unless the CSS interrupt
AnnaBridge	143:86740a56073b	1583	* pending bit is cleared.
AnnaBridge	167:84c0a372a020	1584	* @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
AnnaBridge	167:84c0a372a020	1585	* This parameter can be any combination of the following values:
AnnaBridge	167:84c0a372a020	1586	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge	167:84c0a372a020	1587	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge	167:84c0a372a020	1588	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge	167:84c0a372a020	1589	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge	167:84c0a372a020	1590	* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
AnnaBridge	167:84c0a372a020	1591	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
AnnaBridge	167:84c0a372a020	1592	* @arg @ref RCC_IT_LSECSS LSE CSS interrupt
AnnaBridge	167:84c0a372a020	1593	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (not available on all devices)
AnnaBridge	143:86740a56073b	1594	*/
AnnaBridge	143:86740a56073b	1595	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
AnnaBridge	143:86740a56073b	1596
AnnaBridge	167:84c0a372a020	1597	/** @brief Disable RCC interrupt.
AnnaBridge	143:86740a56073b	1598	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
AnnaBridge	143:86740a56073b	1599	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
AnnaBridge	143:86740a56073b	1600	* automatically generated. The NMI will be executed indefinitely, and
AnnaBridge	143:86740a56073b	1601	* since NMI has higher priority than any other IRQ (and main program)
AnnaBridge	143:86740a56073b	1602	* the application will be stacked in the NMI ISR unless the CSS interrupt
AnnaBridge	167:84c0a372a020	1603	* pending bit is cleared.
AnnaBridge	167:84c0a372a020	1604	* @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
AnnaBridge	167:84c0a372a020	1605	* This parameter can be any combination of the following values:
AnnaBridge	167:84c0a372a020	1606	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge	167:84c0a372a020	1607	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge	167:84c0a372a020	1608	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge	167:84c0a372a020	1609	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge	167:84c0a372a020	1610	* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
AnnaBridge	167:84c0a372a020	1611	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
AnnaBridge	167:84c0a372a020	1612	* @arg @ref RCC_IT_LSECSS LSE CSS interrupt
AnnaBridge	167:84c0a372a020	1613	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (not available on all devices)
AnnaBridge	143:86740a56073b	1614	*/
AnnaBridge	143:86740a56073b	1615	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
AnnaBridge	143:86740a56073b	1616
AnnaBridge	167:84c0a372a020	1617	/** @brief Clear the RCC's interrupt pending bits.
AnnaBridge	167:84c0a372a020	1618	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge	167:84c0a372a020	1619	* This parameter can be any combination of the following values:
AnnaBridge	167:84c0a372a020	1620	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
AnnaBridge	167:84c0a372a020	1621	* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
AnnaBridge	167:84c0a372a020	1622	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
AnnaBridge	167:84c0a372a020	1623	* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
AnnaBridge	167:84c0a372a020	1624	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
AnnaBridge	167:84c0a372a020	1625	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
AnnaBridge	167:84c0a372a020	1626	* @arg @ref RCC_IT_LSECSS LSE CSS interrupt
AnnaBridge	167:84c0a372a020	1627	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (not available on all devices)
AnnaBridge	167:84c0a372a020	1628	* @arg @ref RCC_IT_CSS Clock Security System interrupt
AnnaBridge	143:86740a56073b	1629	*/
AnnaBridge	167:84c0a372a020	1630	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
AnnaBridge	143:86740a56073b	1631
AnnaBridge	143:86740a56073b	1632	/** @brief Check the RCC's interrupt has occurred or not.
AnnaBridge	167:84c0a372a020	1633	* @param __INTERRUPT__ specifies the RCC interrupt source to check.
AnnaBridge	143:86740a56073b	1634	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1635	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge	167:84c0a372a020	1636	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge	167:84c0a372a020	1637	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge	167:84c0a372a020	1638	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge	167:84c0a372a020	1639	* @arg @ref RCC_IT_PLLRDY PLL ready interrupt
AnnaBridge	167:84c0a372a020	1640	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
AnnaBridge	167:84c0a372a020	1641	* @arg @ref RCC_IT_LSECSS LSE CSS interrupt
AnnaBridge	167:84c0a372a020	1642	* @arg @ref RCC_IT_CSS Clock Security System interrupt
AnnaBridge	143:86740a56073b	1643	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge	143:86740a56073b	1644	*/
AnnaBridge	143:86740a56073b	1645	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge	143:86740a56073b	1646
AnnaBridge	143:86740a56073b	1647
AnnaBridge	143:86740a56073b	1648	/** @brief Set RMVF bit to clear the reset flags.
AnnaBridge	167:84c0a372a020	1649	* The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
AnnaBridge	167:84c0a372a020	1650	* RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
AnnaBridge	143:86740a56073b	1651	*/
AnnaBridge	143:86740a56073b	1652	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
AnnaBridge	143:86740a56073b	1653
AnnaBridge	143:86740a56073b	1654	/** @brief Check RCC flag is set or not.
AnnaBridge	167:84c0a372a020	1655	* @param __FLAG__ specifies the flag to check.
AnnaBridge	143:86740a56073b	1656	* This parameter can be one of the following values:
AnnaBridge	167:84c0a372a020	1657	* @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
AnnaBridge	167:84c0a372a020	1658	* @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready (not available on all devices)
AnnaBridge	167:84c0a372a020	1659	* @arg @ref RCC_FLAG_HSIDIV HSI16 divider flag
AnnaBridge	167:84c0a372a020	1660	* @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready
AnnaBridge	167:84c0a372a020	1661	* @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
AnnaBridge	167:84c0a372a020	1662	* @arg @ref RCC_FLAG_PLLRDY PLL clock ready
AnnaBridge	167:84c0a372a020	1663	* @arg @ref RCC_FLAG_LSECSS LSE oscillator clock CSS detected
AnnaBridge	167:84c0a372a020	1664	* @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
AnnaBridge	167:84c0a372a020	1665	* @arg @ref RCC_FLAG_FWRST Firewall reset
AnnaBridge	167:84c0a372a020	1666	* @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
AnnaBridge	167:84c0a372a020	1667	* @arg @ref RCC_FLAG_OBLRST Option Byte Loader (OBL) reset
AnnaBridge	167:84c0a372a020	1668	* @arg @ref RCC_FLAG_PINRST Pin reset
AnnaBridge	167:84c0a372a020	1669	* @arg @ref RCC_FLAG_PORRST POR/PDR reset
AnnaBridge	167:84c0a372a020	1670	* @arg @ref RCC_FLAG_SFTRST Software reset
AnnaBridge	167:84c0a372a020	1671	* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
AnnaBridge	167:84c0a372a020	1672	* @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
AnnaBridge	167:84c0a372a020	1673	* @arg @ref RCC_FLAG_LPWRRST Low Power reset
AnnaBridge	143:86740a56073b	1674	* @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge	143:86740a56073b	1675	*/
AnnaBridge	167:84c0a372a020	1676	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	167:84c0a372a020	1677	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :((((__FLAG__) >> 5) == CSR_REG_INDEX) ? RCC->CSR :RCC->CRRCR)))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0 ) ? 1 : 0 )
AnnaBridge	167:84c0a372a020	1678	#else
AnnaBridge	167:84c0a372a020	1679	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : RCC->CSR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0 ) ? 1 : 0 )
AnnaBridge	167:84c0a372a020	1680	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	143:86740a56073b	1681
AnnaBridge	143:86740a56073b	1682	/**
AnnaBridge	143:86740a56073b	1683	* @}
AnnaBridge	143:86740a56073b	1684	*/
AnnaBridge	143:86740a56073b	1685
AnnaBridge	143:86740a56073b	1686	/**
AnnaBridge	143:86740a56073b	1687	* @}
AnnaBridge	143:86740a56073b	1688	*/
AnnaBridge	143:86740a56073b	1689
AnnaBridge	143:86740a56073b	1690	/* Include RCC HAL Extension module */
AnnaBridge	143:86740a56073b	1691	#include "stm32l0xx_hal_rcc_ex.h"
AnnaBridge	143:86740a56073b	1692
AnnaBridge	167:84c0a372a020	1693	/* Exported functions --------------------------------------------------------*/
AnnaBridge	167:84c0a372a020	1694	/** @addtogroup RCC_Exported_Functions
AnnaBridge	143:86740a56073b	1695	* @{
AnnaBridge	143:86740a56073b	1696	*/
AnnaBridge	143:86740a56073b	1697
AnnaBridge	167:84c0a372a020	1698	/** @addtogroup RCC_Exported_Functions_Group1
AnnaBridge	143:86740a56073b	1699	* @{
AnnaBridge	143:86740a56073b	1700	*/
AnnaBridge	143:86740a56073b	1701
AnnaBridge	167:84c0a372a020	1702	/* Initialization and de-initialization functions ******************************/
AnnaBridge	167:84c0a372a020	1703	void HAL_RCC_DeInit(void);
AnnaBridge	167:84c0a372a020	1704	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge	167:84c0a372a020	1705	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
AnnaBridge	143:86740a56073b	1706
AnnaBridge	143:86740a56073b	1707	/**
AnnaBridge	143:86740a56073b	1708	* @}
AnnaBridge	143:86740a56073b	1709	*/
AnnaBridge	143:86740a56073b	1710
AnnaBridge	167:84c0a372a020	1711	/** @addtogroup RCC_Exported_Functions_Group2
AnnaBridge	167:84c0a372a020	1712	* @{
AnnaBridge	167:84c0a372a020	1713	*/
AnnaBridge	167:84c0a372a020	1714
AnnaBridge	167:84c0a372a020	1715	/* Peripheral Control functions ************************************************/
AnnaBridge	167:84c0a372a020	1716	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
AnnaBridge	167:84c0a372a020	1717	#if defined(RCC_HSECSS_SUPPORT)
AnnaBridge	167:84c0a372a020	1718	void HAL_RCC_EnableCSS(void);
AnnaBridge	167:84c0a372a020	1719	/* CSS NMI IRQ handler */
AnnaBridge	167:84c0a372a020	1720	void HAL_RCC_NMI_IRQHandler(void);
AnnaBridge	167:84c0a372a020	1721	/* User Callbacks in non blocking mode (IT mode) */
AnnaBridge	167:84c0a372a020	1722	void HAL_RCC_CSSCallback(void);
AnnaBridge	167:84c0a372a020	1723	#endif /* RCC_HSECSS_SUPPORT */
AnnaBridge	167:84c0a372a020	1724	uint32_t HAL_RCC_GetSysClockFreq(void);
AnnaBridge	167:84c0a372a020	1725	uint32_t HAL_RCC_GetHCLKFreq(void);
AnnaBridge	167:84c0a372a020	1726	uint32_t HAL_RCC_GetPCLK1Freq(void);
AnnaBridge	167:84c0a372a020	1727	uint32_t HAL_RCC_GetPCLK2Freq(void);
AnnaBridge	167:84c0a372a020	1728	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge	167:84c0a372a020	1729	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
AnnaBridge	167:84c0a372a020	1730
AnnaBridge	167:84c0a372a020	1731	/**
AnnaBridge	167:84c0a372a020	1732	* @}
AnnaBridge	167:84c0a372a020	1733	*/
AnnaBridge	167:84c0a372a020	1734
AnnaBridge	167:84c0a372a020	1735	/**
AnnaBridge	167:84c0a372a020	1736	* @}
AnnaBridge	167:84c0a372a020	1737	*/
AnnaBridge	167:84c0a372a020	1738
AnnaBridge	167:84c0a372a020	1739	/**
AnnaBridge	167:84c0a372a020	1740	* @}
AnnaBridge	167:84c0a372a020	1741	*/
AnnaBridge	167:84c0a372a020	1742
AnnaBridge	167:84c0a372a020	1743	/**
AnnaBridge	167:84c0a372a020	1744	* @}
AnnaBridge	167:84c0a372a020	1745	*/
AnnaBridge	167:84c0a372a020	1746
AnnaBridge	143:86740a56073b	1747	#ifdef __cplusplus
AnnaBridge	143:86740a56073b	1748	}
AnnaBridge	143:86740a56073b	1749	#endif
AnnaBridge	143:86740a56073b	1750
AnnaBridge	167:84c0a372a020	1751	#endif /* __STM32L0xx_HAL_RCC_H */
AnnaBridge	143:86740a56073b	1752
AnnaBridge	143:86740a56073b	1753	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
AnnaBridge	143:86740a56073b	1754