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TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:30:20 2017 +0100
Revision:: 143:86740a56073b
Child:: 167:84c0a372a020

Release 143 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	143:86740a56073b	1	/**
AnnaBridge	143:86740a56073b	2	******************************************************************************
AnnaBridge	143:86740a56073b	3	* @file stm32l0xx_hal_rcc.h
AnnaBridge	143:86740a56073b	4	* @author MCD Application Team
AnnaBridge	143:86740a56073b	5	* @version V1.7.0
AnnaBridge	143:86740a56073b	6	* @date 31-May-2016
AnnaBridge	143:86740a56073b	7	* @brief Header file of RCC HAL module.
AnnaBridge	143:86740a56073b	8	******************************************************************************
AnnaBridge	143:86740a56073b	9	* @attention
AnnaBridge	143:86740a56073b	10	*
AnnaBridge	143:86740a56073b	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	143:86740a56073b	12	*
AnnaBridge	143:86740a56073b	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	143:86740a56073b	14	* are permitted provided that the following conditions are met:
AnnaBridge	143:86740a56073b	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	143:86740a56073b	16	* this list of conditions and the following disclaimer.
AnnaBridge	143:86740a56073b	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	143:86740a56073b	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	143:86740a56073b	19	* and/or other materials provided with the distribution.
AnnaBridge	143:86740a56073b	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	143:86740a56073b	21	* may be used to endorse or promote products derived from this software
AnnaBridge	143:86740a56073b	22	* without specific prior written permission.
AnnaBridge	143:86740a56073b	23	*
AnnaBridge	143:86740a56073b	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	143:86740a56073b	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	143:86740a56073b	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	143:86740a56073b	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	143:86740a56073b	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	143:86740a56073b	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	143:86740a56073b	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	143:86740a56073b	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	143:86740a56073b	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	143:86740a56073b	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	143:86740a56073b	34	*
AnnaBridge	143:86740a56073b	35	******************************************************************************
AnnaBridge	143:86740a56073b	36	*/
AnnaBridge	143:86740a56073b	37
AnnaBridge	143:86740a56073b	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	143:86740a56073b	39	#ifndef __STM32L0xx_HAL_RCC_H
AnnaBridge	143:86740a56073b	40	#define __STM32L0xx_HAL_RCC_H
AnnaBridge	143:86740a56073b	41
AnnaBridge	143:86740a56073b	42	#ifdef __cplusplus
AnnaBridge	143:86740a56073b	43	extern "C" {
AnnaBridge	143:86740a56073b	44	#endif
AnnaBridge	143:86740a56073b	45
AnnaBridge	143:86740a56073b	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	47	#include "stm32l0xx_hal_def.h"
AnnaBridge	143:86740a56073b	48
AnnaBridge	143:86740a56073b	49	/** @addtogroup STM32L0xx_HAL_Driver
AnnaBridge	143:86740a56073b	50	* @{
AnnaBridge	143:86740a56073b	51	*/
AnnaBridge	143:86740a56073b	52
AnnaBridge	143:86740a56073b	53	/** @defgroup RCC RCC
AnnaBridge	143:86740a56073b	54	* @{
AnnaBridge	143:86740a56073b	55	*/
AnnaBridge	143:86740a56073b	56
AnnaBridge	143:86740a56073b	57	/** @defgroup RCC_Exported_Types RCC Exported Types
AnnaBridge	143:86740a56073b	58	* @{
AnnaBridge	143:86740a56073b	59	*/
AnnaBridge	143:86740a56073b	60
AnnaBridge	143:86740a56073b	61	/**
AnnaBridge	143:86740a56073b	62	* @brief RCC PLL configuration structure definition
AnnaBridge	143:86740a56073b	63	*/
AnnaBridge	143:86740a56073b	64	typedef struct
AnnaBridge	143:86740a56073b	65	{
AnnaBridge	143:86740a56073b	66	uint32_t PLLState; /*!< The new state of the PLL.
AnnaBridge	143:86740a56073b	67	This parameter can be a value of @ref RCC_PLL_Config */
AnnaBridge	143:86740a56073b	68
AnnaBridge	143:86740a56073b	69	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
AnnaBridge	143:86740a56073b	70	This parameter must be a value of @ref RCC_PLL_Clock_Source */
AnnaBridge	143:86740a56073b	71
AnnaBridge	143:86740a56073b	72	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO output clock
AnnaBridge	143:86740a56073b	73	This parameter must of @ref RCC_PLLMultiplication_Factor */
AnnaBridge	143:86740a56073b	74
AnnaBridge	143:86740a56073b	75	uint32_t PLLDIV; /*!< PLLDIV: Division factor for main system clock (SYSCLK)
AnnaBridge	143:86740a56073b	76	This parameter must be a value of @ref RCC_PLLDivider_Factor */
AnnaBridge	143:86740a56073b	77
AnnaBridge	143:86740a56073b	78	}RCC_PLLInitTypeDef;
AnnaBridge	143:86740a56073b	79
AnnaBridge	143:86740a56073b	80	/**
AnnaBridge	143:86740a56073b	81	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
AnnaBridge	143:86740a56073b	82	*/
AnnaBridge	143:86740a56073b	83	typedef struct
AnnaBridge	143:86740a56073b	84	{
AnnaBridge	143:86740a56073b	85	uint32_t OscillatorType; /*!< The oscillators to be configured.
AnnaBridge	143:86740a56073b	86	This parameter can be a value of @ref RCC_Oscillator_Type */
AnnaBridge	143:86740a56073b	87
AnnaBridge	143:86740a56073b	88	uint32_t HSEState; /*!< The new state of the HSE.
AnnaBridge	143:86740a56073b	89	This parameter can be a value of @ref RCC_HSE_Config */
AnnaBridge	143:86740a56073b	90
AnnaBridge	143:86740a56073b	91	uint32_t LSEState; /*!< The new state of the LSE.
AnnaBridge	143:86740a56073b	92	This parameter can be a value of @ref RCC_LSE_Config */
AnnaBridge	143:86740a56073b	93
AnnaBridge	143:86740a56073b	94	uint32_t HSIState; /*!< The new state of the HSI.
AnnaBridge	143:86740a56073b	95	This parameter can be a value of @ref RCC_HSI_Config */
AnnaBridge	143:86740a56073b	96
AnnaBridge	143:86740a56073b	97	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
AnnaBridge	143:86740a56073b	98	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
AnnaBridge	143:86740a56073b	99
AnnaBridge	143:86740a56073b	100	uint32_t LSIState; /*!< The new state of the LSI.
AnnaBridge	143:86740a56073b	101	This parameter can be a value of @ref RCC_LSI_Config */
AnnaBridge	143:86740a56073b	102
AnnaBridge	143:86740a56073b	103	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \
AnnaBridge	143:86740a56073b	104	!defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge	143:86740a56073b	105	uint32_t HSI48State; /*!< The new state of the HSI48.
AnnaBridge	143:86740a56073b	106	This parameter can be a value of @ref RCC_HSI48_Config */
AnnaBridge	143:86740a56073b	107	#endif
AnnaBridge	143:86740a56073b	108
AnnaBridge	143:86740a56073b	109	uint32_t MSIState; /*!< The new state of the MSI.
AnnaBridge	143:86740a56073b	110	This parameter can be a value of @ref RCC_MSI_Config */
AnnaBridge	143:86740a56073b	111
AnnaBridge	143:86740a56073b	112	uint32_t MSICalibrationValue; /*!< The calibration trimming value.
AnnaBridge	143:86740a56073b	113	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
AnnaBridge	143:86740a56073b	114
AnnaBridge	143:86740a56073b	115	uint32_t MSIClockRange; /*!< The MSI frequency range.
AnnaBridge	143:86740a56073b	116	This parameter can be a value of @ref RCC_MSI_Clock_Range */
AnnaBridge	143:86740a56073b	117
AnnaBridge	143:86740a56073b	118	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
AnnaBridge	143:86740a56073b	119
AnnaBridge	143:86740a56073b	120	}RCC_OscInitTypeDef;
AnnaBridge	143:86740a56073b	121
AnnaBridge	143:86740a56073b	122	/**
AnnaBridge	143:86740a56073b	123	* @brief RCC System, AHB and APB busses clock configuration structure definition
AnnaBridge	143:86740a56073b	124	*/
AnnaBridge	143:86740a56073b	125	typedef struct
AnnaBridge	143:86740a56073b	126	{
AnnaBridge	143:86740a56073b	127	uint32_t ClockType; /*!< The clock to be configured.
AnnaBridge	143:86740a56073b	128	This parameter can be a value of @ref RCC_System_Clock_Type */
AnnaBridge	143:86740a56073b	129
AnnaBridge	143:86740a56073b	130	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
AnnaBridge	143:86740a56073b	131	This parameter can be a value of @ref RCC_System_Clock_Source */
AnnaBridge	143:86740a56073b	132
AnnaBridge	143:86740a56073b	133	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
AnnaBridge	143:86740a56073b	134	This parameter can be a value of @ref RCC_AHB_Clock_Source */
AnnaBridge	143:86740a56073b	135
AnnaBridge	143:86740a56073b	136	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge	143:86740a56073b	137	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge	143:86740a56073b	138
AnnaBridge	143:86740a56073b	139	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge	143:86740a56073b	140	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge	143:86740a56073b	141
AnnaBridge	143:86740a56073b	142	}RCC_ClkInitTypeDef;
AnnaBridge	143:86740a56073b	143
AnnaBridge	143:86740a56073b	144	/**
AnnaBridge	143:86740a56073b	145	* @}
AnnaBridge	143:86740a56073b	146	*/
AnnaBridge	143:86740a56073b	147
AnnaBridge	143:86740a56073b	148	/* Private constants --------------------------------------------------------*/
AnnaBridge	143:86740a56073b	149	/** @addtogroup RCC_Private
AnnaBridge	143:86740a56073b	150	* @brief RCC registers bit address in the alias region
AnnaBridge	143:86740a56073b	151	* @{
AnnaBridge	143:86740a56073b	152	*/
AnnaBridge	143:86740a56073b	153	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
AnnaBridge	143:86740a56073b	154	/* --- CR Register ---*/
AnnaBridge	143:86740a56073b	155	/* Alias word address of HSION bit */
AnnaBridge	143:86740a56073b	156	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
AnnaBridge	143:86740a56073b	157	/* --- CFGR Register ---*/
AnnaBridge	143:86740a56073b	158	/* Alias word address of I2SSRC bit */
AnnaBridge	143:86740a56073b	159	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
AnnaBridge	143:86740a56073b	160	/* --- CSR Register ---*/
AnnaBridge	143:86740a56073b	161	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
AnnaBridge	143:86740a56073b	162
AnnaBridge	143:86740a56073b	163	/* CR register byte 3 (Bits[23:16]) base address */
AnnaBridge	143:86740a56073b	164	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802U)
AnnaBridge	143:86740a56073b	165
AnnaBridge	143:86740a56073b	166	/* CIER register byte 0 (Bits[0:8]) base address */
AnnaBridge	143:86740a56073b	167	#define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10U + 0x00U))
AnnaBridge	143:86740a56073b	168
AnnaBridge	143:86740a56073b	169	/**
AnnaBridge	143:86740a56073b	170	* @}
AnnaBridge	143:86740a56073b	171	*/
AnnaBridge	143:86740a56073b	172
AnnaBridge	143:86740a56073b	173	/* Exported constants --------------------------------------------------------*/
AnnaBridge	143:86740a56073b	174	/** @defgroup RCC_Exported_Constants RCC Exported Constants
AnnaBridge	143:86740a56073b	175	* @{
AnnaBridge	143:86740a56073b	176	*/
AnnaBridge	143:86740a56073b	177
AnnaBridge	143:86740a56073b	178	/** @defgroup RCC_Timeout_Value Timeout Values
AnnaBridge	143:86740a56073b	179	* @{
AnnaBridge	143:86740a56073b	180	*/
AnnaBridge	143:86740a56073b	181	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100U) /* 100 ms */
AnnaBridge	143:86740a56073b	182	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
AnnaBridge	143:86740a56073b	183	#define RCC_HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
AnnaBridge	143:86740a56073b	184	/**
AnnaBridge	143:86740a56073b	185	* @}
AnnaBridge	143:86740a56073b	186	*/
AnnaBridge	143:86740a56073b	187
AnnaBridge	143:86740a56073b	188	/** @defgroup RCC_Oscillator_Type Oscillator Type
AnnaBridge	143:86740a56073b	189	* @{
AnnaBridge	143:86740a56073b	190	*/
AnnaBridge	143:86740a56073b	191	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) /!< Oscillator configuration unchanged /
AnnaBridge	143:86740a56073b	192	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) /!< HSE to configure /
AnnaBridge	143:86740a56073b	193	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) /!< HSI to configure /
AnnaBridge	143:86740a56073b	194	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) /!< LSE to configure /
AnnaBridge	143:86740a56073b	195	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) /!< LSI to configure /
AnnaBridge	143:86740a56073b	196	#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010U) /!< MSI to configure /
AnnaBridge	143:86740a56073b	197	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge	143:86740a56073b	198	#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020U)
AnnaBridge	143:86740a56073b	199	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
AnnaBridge	143:86740a56073b	200
AnnaBridge	143:86740a56073b	201	/**
AnnaBridge	143:86740a56073b	202	* @}
AnnaBridge	143:86740a56073b	203	*/
AnnaBridge	143:86740a56073b	204
AnnaBridge	143:86740a56073b	205	/** @defgroup RCC_HSE_Config RCC HSE Config
AnnaBridge	143:86740a56073b	206	* @{
AnnaBridge	143:86740a56073b	207	*/
AnnaBridge	143:86740a56073b	208	#define RCC_HSE_OFF ((uint32_t)0x00000000U)
AnnaBridge	143:86740a56073b	209	#define RCC_HSE_ON RCC_CR_HSEON
AnnaBridge	143:86740a56073b	210	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON))
AnnaBridge	143:86740a56073b	211
AnnaBridge	143:86740a56073b	212	/**
AnnaBridge	143:86740a56073b	213	* @}
AnnaBridge	143:86740a56073b	214	*/
AnnaBridge	143:86740a56073b	215
AnnaBridge	143:86740a56073b	216	/** @defgroup RCC_LSE_Config RCC LSE Config
AnnaBridge	143:86740a56073b	217	* @{
AnnaBridge	143:86740a56073b	218	*/
AnnaBridge	143:86740a56073b	219	#define RCC_LSE_OFF ((uint32_t)0x00000000U)
AnnaBridge	143:86740a56073b	220	#define RCC_LSE_ON RCC_CSR_LSEON
AnnaBridge	143:86740a56073b	221	#define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR_LSEBYP \| RCC_CSR_LSEON))
AnnaBridge	143:86740a56073b	222
AnnaBridge	143:86740a56073b	223	/**
AnnaBridge	143:86740a56073b	224	* @}
AnnaBridge	143:86740a56073b	225	*/
AnnaBridge	143:86740a56073b	226
AnnaBridge	143:86740a56073b	227
AnnaBridge	143:86740a56073b	228
AnnaBridge	143:86740a56073b	229	/** @defgroup RCC_LSI_Config RCC LSI Config
AnnaBridge	143:86740a56073b	230	* @{
AnnaBridge	143:86740a56073b	231	*/
AnnaBridge	143:86740a56073b	232	#define RCC_LSI_OFF ((uint8_t)0x00U)
AnnaBridge	143:86740a56073b	233	#define RCC_LSI_ON ((uint8_t)0x01U)
AnnaBridge	143:86740a56073b	234
AnnaBridge	143:86740a56073b	235	#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /* Default MSI calibration trimming value */
AnnaBridge	143:86740a56073b	236
AnnaBridge	143:86740a56073b	237	/**
AnnaBridge	143:86740a56073b	238	* @}
AnnaBridge	143:86740a56073b	239	*/
AnnaBridge	143:86740a56073b	240
AnnaBridge	143:86740a56073b	241
AnnaBridge	143:86740a56073b	242	/** @defgroup RCC_MSI_Config RCC MSI Config
AnnaBridge	143:86740a56073b	243	* @{
AnnaBridge	143:86740a56073b	244	*/
AnnaBridge	143:86740a56073b	245	#define RCC_MSI_OFF ((uint8_t)0x00U)
AnnaBridge	143:86740a56073b	246	#define RCC_MSI_ON ((uint8_t)0x01U)
AnnaBridge	143:86740a56073b	247
AnnaBridge	143:86740a56073b	248	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
AnnaBridge	143:86740a56073b	249
AnnaBridge	143:86740a56073b	250	/**
AnnaBridge	143:86740a56073b	251	* @}
AnnaBridge	143:86740a56073b	252	*/
AnnaBridge	143:86740a56073b	253
AnnaBridge	143:86740a56073b	254	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge	143:86740a56073b	255	/** @defgroup RCC_HSI48_Config RCC HSI48 Configuration
AnnaBridge	143:86740a56073b	256	* @{
AnnaBridge	143:86740a56073b	257	*/
AnnaBridge	143:86740a56073b	258	#define RCC_HSI48_OFF ((uint8_t)0x00U)
AnnaBridge	143:86740a56073b	259	#define RCC_HSI48_ON ((uint8_t)0x01U)
AnnaBridge	143:86740a56073b	260
AnnaBridge	143:86740a56073b	261	/**
AnnaBridge	143:86740a56073b	262	* @}
AnnaBridge	143:86740a56073b	263	*/
AnnaBridge	143:86740a56073b	264	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
AnnaBridge	143:86740a56073b	265
AnnaBridge	143:86740a56073b	266	/** @defgroup RCC_PLL_Config RCC PLL Config
AnnaBridge	143:86740a56073b	267	* @{
AnnaBridge	143:86740a56073b	268	*/
AnnaBridge	143:86740a56073b	269	#define RCC_PLL_NONE ((uint8_t)0x00U)
AnnaBridge	143:86740a56073b	270	#define RCC_PLL_OFF ((uint8_t)0x01U)
AnnaBridge	143:86740a56073b	271	#define RCC_PLL_ON ((uint8_t)0x02U)
AnnaBridge	143:86740a56073b	272
AnnaBridge	143:86740a56073b	273	/**
AnnaBridge	143:86740a56073b	274	* @}
AnnaBridge	143:86740a56073b	275	*/
AnnaBridge	143:86740a56073b	276
AnnaBridge	143:86740a56073b	277	/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
AnnaBridge	143:86740a56073b	278	* @{
AnnaBridge	143:86740a56073b	279	*/
AnnaBridge	143:86740a56073b	280	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI
AnnaBridge	143:86740a56073b	281	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE
AnnaBridge	143:86740a56073b	282
AnnaBridge	143:86740a56073b	283
AnnaBridge	143:86740a56073b	284	/**
AnnaBridge	143:86740a56073b	285	* @}
AnnaBridge	143:86740a56073b	286	*/
AnnaBridge	143:86740a56073b	287
AnnaBridge	143:86740a56073b	288	/** @defgroup RCC_PLLMultiplication_Factor RCC PLL Multipliers
AnnaBridge	143:86740a56073b	289	* @{
AnnaBridge	143:86740a56073b	290	*/
AnnaBridge	143:86740a56073b	291
AnnaBridge	143:86740a56073b	292	#define RCC_PLLMUL_3 RCC_CFGR_PLLMUL3
AnnaBridge	143:86740a56073b	293	#define RCC_PLLMUL_4 RCC_CFGR_PLLMUL4
AnnaBridge	143:86740a56073b	294	#define RCC_PLLMUL_6 RCC_CFGR_PLLMUL6
AnnaBridge	143:86740a56073b	295	#define RCC_PLLMUL_8 RCC_CFGR_PLLMUL8
AnnaBridge	143:86740a56073b	296	#define RCC_PLLMUL_12 RCC_CFGR_PLLMUL12
AnnaBridge	143:86740a56073b	297	#define RCC_PLLMUL_16 RCC_CFGR_PLLMUL16
AnnaBridge	143:86740a56073b	298	#define RCC_PLLMUL_24 RCC_CFGR_PLLMUL24
AnnaBridge	143:86740a56073b	299	#define RCC_PLLMUL_32 RCC_CFGR_PLLMUL32
AnnaBridge	143:86740a56073b	300	#define RCC_PLLMUL_48 RCC_CFGR_PLLMUL48
AnnaBridge	143:86740a56073b	301
AnnaBridge	143:86740a56073b	302	/**
AnnaBridge	143:86740a56073b	303	* @}
AnnaBridge	143:86740a56073b	304	*/
AnnaBridge	143:86740a56073b	305
AnnaBridge	143:86740a56073b	306	/** @defgroup RCC_PLLDivider_Factor RCC PLL Dividers
AnnaBridge	143:86740a56073b	307	* @{
AnnaBridge	143:86740a56073b	308	*/
AnnaBridge	143:86740a56073b	309
AnnaBridge	143:86740a56073b	310	#define RCC_PLLDIV_2 RCC_CFGR_PLLDIV2
AnnaBridge	143:86740a56073b	311	#define RCC_PLLDIV_3 RCC_CFGR_PLLDIV3
AnnaBridge	143:86740a56073b	312	#define RCC_PLLDIV_4 RCC_CFGR_PLLDIV4
AnnaBridge	143:86740a56073b	313
AnnaBridge	143:86740a56073b	314	/**
AnnaBridge	143:86740a56073b	315	* @}
AnnaBridge	143:86740a56073b	316	*/
AnnaBridge	143:86740a56073b	317
AnnaBridge	143:86740a56073b	318	/** @defgroup RCC_MSI_Clock_Range RCC MSI Clock Range
AnnaBridge	143:86740a56073b	319	* @{
AnnaBridge	143:86740a56073b	320	*/
AnnaBridge	143:86740a56073b	321
AnnaBridge	143:86740a56073b	322	#define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /!< MSI = 65.536 KHz /
AnnaBridge	143:86740a56073b	323	#define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /!< MSI = 131.072 KHz /
AnnaBridge	143:86740a56073b	324	#define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /!< MSI = 262.144 KHz /
AnnaBridge	143:86740a56073b	325	#define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /!< MSI = 524.288 KHz /
AnnaBridge	143:86740a56073b	326	#define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /!< MSI = 1.048 MHz /
AnnaBridge	143:86740a56073b	327	#define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /!< MSI = 2.097 MHz /
AnnaBridge	143:86740a56073b	328	#define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /!< MSI = 4.194 MHz /
AnnaBridge	143:86740a56073b	329
AnnaBridge	143:86740a56073b	330
AnnaBridge	143:86740a56073b	331	/**
AnnaBridge	143:86740a56073b	332	* @}
AnnaBridge	143:86740a56073b	333	*/
AnnaBridge	143:86740a56073b	334
AnnaBridge	143:86740a56073b	335	/** @defgroup RCC_System_Clock_Type RCC System Clock Type
AnnaBridge	143:86740a56073b	336	* @{
AnnaBridge	143:86740a56073b	337	*/
AnnaBridge	143:86740a56073b	338	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) /!< SYSCLK to configure /
AnnaBridge	143:86740a56073b	339	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) /!< HCLK to configure /
AnnaBridge	143:86740a56073b	340	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) /!< PCLK1 to configure /
AnnaBridge	143:86740a56073b	341	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) /!< PCLK2 to configure /
AnnaBridge	143:86740a56073b	342	/**
AnnaBridge	143:86740a56073b	343	* @}
AnnaBridge	143:86740a56073b	344	*/
AnnaBridge	143:86740a56073b	345
AnnaBridge	143:86740a56073b	346	/** @defgroup RCC_System_Clock_Source RCC System Clock Source
AnnaBridge	143:86740a56073b	347	* @{
AnnaBridge	143:86740a56073b	348	*/
AnnaBridge	143:86740a56073b	349	#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selection as system clock /
AnnaBridge	143:86740a56073b	350	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
AnnaBridge	143:86740a56073b	351	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
AnnaBridge	143:86740a56073b	352	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selection as system clock /
AnnaBridge	143:86740a56073b	353	/**
AnnaBridge	143:86740a56073b	354	* @}
AnnaBridge	143:86740a56073b	355	*/
AnnaBridge	143:86740a56073b	356
AnnaBridge	143:86740a56073b	357	/** @defgroup RCC_System_Clock_SOURCE_Status RCC System Clock Source Status
AnnaBridge	143:86740a56073b	358	* @{
AnnaBridge	143:86740a56073b	359	*/
AnnaBridge	143:86740a56073b	360	#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
AnnaBridge	143:86740a56073b	361	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
AnnaBridge	143:86740a56073b	362	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
AnnaBridge	143:86740a56073b	363	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
AnnaBridge	143:86740a56073b	364	/**
AnnaBridge	143:86740a56073b	365	* @}
AnnaBridge	143:86740a56073b	366	*/
AnnaBridge	143:86740a56073b	367
AnnaBridge	143:86740a56073b	368	/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
AnnaBridge	143:86740a56073b	369	* @{
AnnaBridge	143:86740a56073b	370	*/
AnnaBridge	143:86740a56073b	371	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
AnnaBridge	143:86740a56073b	372	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
AnnaBridge	143:86740a56073b	373	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
AnnaBridge	143:86740a56073b	374	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
AnnaBridge	143:86740a56073b	375	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
AnnaBridge	143:86740a56073b	376	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
AnnaBridge	143:86740a56073b	377	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
AnnaBridge	143:86740a56073b	378	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
AnnaBridge	143:86740a56073b	379	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
AnnaBridge	143:86740a56073b	380	/**
AnnaBridge	143:86740a56073b	381	* @}
AnnaBridge	143:86740a56073b	382	*/
AnnaBridge	143:86740a56073b	383
AnnaBridge	143:86740a56073b	384	/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 APB2 Clock Source
AnnaBridge	143:86740a56073b	385	* @{
AnnaBridge	143:86740a56073b	386	*/
AnnaBridge	143:86740a56073b	387	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
AnnaBridge	143:86740a56073b	388	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
AnnaBridge	143:86740a56073b	389	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
AnnaBridge	143:86740a56073b	390	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
AnnaBridge	143:86740a56073b	391	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
AnnaBridge	143:86740a56073b	392	/**
AnnaBridge	143:86740a56073b	393	* @}
AnnaBridge	143:86740a56073b	394	*/
AnnaBridge	143:86740a56073b	395
AnnaBridge	143:86740a56073b	396	/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
AnnaBridge	143:86740a56073b	397	* @{
AnnaBridge	143:86740a56073b	398	*/
AnnaBridge	143:86740a56073b	399	#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U)
AnnaBridge	143:86740a56073b	400	#define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE
AnnaBridge	143:86740a56073b	401	#define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI
AnnaBridge	143:86740a56073b	402	#define RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE
AnnaBridge	143:86740a56073b	403
AnnaBridge	143:86740a56073b	404	#define RCC_RTCCLKSOURCE_HSE_DIV2 RCC_CSR_RTCSEL_HSE
AnnaBridge	143:86740a56073b	405	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_0)
AnnaBridge	143:86740a56073b	406	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_1)
AnnaBridge	143:86740a56073b	407	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE)
AnnaBridge	143:86740a56073b	408
AnnaBridge	143:86740a56073b	409	#define RCC_RTC_HSE_DIV_2 (uint32_t)0x00000000U /!< HSE is divided by 2 for RTC clock /
AnnaBridge	143:86740a56073b	410	#define RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /!< HSE is divided by 4 for RTC clock /
AnnaBridge	143:86740a56073b	411	#define RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /!< HSE is divided by 8 for RTC clock /
AnnaBridge	143:86740a56073b	412	#define RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /!< HSE is divided by 16 for RTC clock /
AnnaBridge	143:86740a56073b	413
AnnaBridge	143:86740a56073b	414	/**
AnnaBridge	143:86740a56073b	415	* @}
AnnaBridge	143:86740a56073b	416	*/
AnnaBridge	143:86740a56073b	417
AnnaBridge	143:86740a56073b	418	/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
AnnaBridge	143:86740a56073b	419	* @{
AnnaBridge	143:86740a56073b	420	*/
AnnaBridge	143:86740a56073b	421
AnnaBridge	143:86740a56073b	422	#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
AnnaBridge	143:86740a56073b	423	#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
AnnaBridge	143:86740a56073b	424	#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
AnnaBridge	143:86740a56073b	425	#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI
AnnaBridge	143:86740a56073b	426	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
AnnaBridge	143:86740a56073b	427	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL
AnnaBridge	143:86740a56073b	428	#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
AnnaBridge	143:86740a56073b	429	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
AnnaBridge	143:86740a56073b	430	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) \
AnnaBridge	143:86740a56073b	431	&& !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge	143:86740a56073b	432	#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48
AnnaBridge	143:86740a56073b	433	#endif
AnnaBridge	143:86740a56073b	434
AnnaBridge	143:86740a56073b	435
AnnaBridge	143:86740a56073b	436	/**
AnnaBridge	143:86740a56073b	437	* @}
AnnaBridge	143:86740a56073b	438	*/
AnnaBridge	143:86740a56073b	439
AnnaBridge	143:86740a56073b	440	/** @defgroup RCC_MCOPrescaler RCC MCO Prescaler
AnnaBridge	143:86740a56073b	441	* @{
AnnaBridge	143:86740a56073b	442	*/
AnnaBridge	143:86740a56073b	443
AnnaBridge	143:86740a56073b	444	#define RCC_MCODIV_1 RCC_CFGR_MCO_PRE_1
AnnaBridge	143:86740a56073b	445	#define RCC_MCODIV_2 RCC_CFGR_MCO_PRE_2
AnnaBridge	143:86740a56073b	446	#define RCC_MCODIV_4 RCC_CFGR_MCO_PRE_4
AnnaBridge	143:86740a56073b	447	#define RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8
AnnaBridge	143:86740a56073b	448	#define RCC_MCODIV_16 RCC_CFGR_MCO_PRE_16
AnnaBridge	143:86740a56073b	449
AnnaBridge	143:86740a56073b	450	/**
AnnaBridge	143:86740a56073b	451	* @}
AnnaBridge	143:86740a56073b	452	*/
AnnaBridge	143:86740a56073b	453
AnnaBridge	143:86740a56073b	454	/** @defgroup RCC_MCO_Index RCC MCO Index
AnnaBridge	143:86740a56073b	455	* @{
AnnaBridge	143:86740a56073b	456	*/
AnnaBridge	143:86740a56073b	457	#define RCC_MCO1 ((uint32_t)0x00000000U)
AnnaBridge	143:86740a56073b	458	#define RCC_MCO2 ((uint32_t)0x00000001U)
AnnaBridge	143:86740a56073b	459	#if defined(STM32L031xx) \|\| defined(STM32L041xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
AnnaBridge	143:86740a56073b	460	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
AnnaBridge	143:86740a56073b	461	#define RCC_MCO3 ((uint32_t)0x00000002U)
AnnaBridge	143:86740a56073b	462	#endif
AnnaBridge	143:86740a56073b	463
AnnaBridge	143:86740a56073b	464	/**
AnnaBridge	143:86740a56073b	465	* @}
AnnaBridge	143:86740a56073b	466	*/
AnnaBridge	143:86740a56073b	467
AnnaBridge	143:86740a56073b	468	/** @defgroup RCC_Interrupt RCC Interruptions
AnnaBridge	143:86740a56073b	469	* @{
AnnaBridge	143:86740a56073b	470	*/
AnnaBridge	143:86740a56073b	471	#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF
AnnaBridge	143:86740a56073b	472	#define RCC_IT_LSERDY RCC_CIFR_LSERDYF
AnnaBridge	143:86740a56073b	473	#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF
AnnaBridge	143:86740a56073b	474	#define RCC_IT_HSERDY RCC_CIFR_HSERDYF
AnnaBridge	143:86740a56073b	475	#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF
AnnaBridge	143:86740a56073b	476	#define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF
AnnaBridge	143:86740a56073b	477
AnnaBridge	143:86740a56073b	478	#define RCC_IT_CSSLSE RCC_CIFR_CSSLSEF
AnnaBridge	143:86740a56073b	479	#define RCC_IT_CSSHSE RCC_CIFR_CSSHSEF
AnnaBridge	143:86740a56073b	480
AnnaBridge	143:86740a56073b	481	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge	143:86740a56073b	482	#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF
AnnaBridge	143:86740a56073b	483	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
AnnaBridge	143:86740a56073b	484	/**
AnnaBridge	143:86740a56073b	485	* @}
AnnaBridge	143:86740a56073b	486	*/
AnnaBridge	143:86740a56073b	487
AnnaBridge	143:86740a56073b	488	/** @defgroup RCC_Flag RCC Flag
AnnaBridge	143:86740a56073b	489	* Elements values convention: 0XXYYYYYb
AnnaBridge	143:86740a56073b	490	* - YYYYY : Flag position in the register
AnnaBridge	143:86740a56073b	491	* - 0XX : Register index
AnnaBridge	143:86740a56073b	492	* - 01: CR register
AnnaBridge	143:86740a56073b	493	* - 10: CSR register
AnnaBridge	143:86740a56073b	494	* - 11: CRRCR register
AnnaBridge	143:86740a56073b	495	* @{
AnnaBridge	143:86740a56073b	496	*/
AnnaBridge	143:86740a56073b	497	/* Flags in the CR register */
AnnaBridge	143:86740a56073b	498	#define RCC_FLAG_HSIRDY ((uint8_t)0x22U)
AnnaBridge	143:86740a56073b	499	#define RCC_FLAG_HSIDIV ((uint8_t)0x24U)
AnnaBridge	143:86740a56073b	500	#define RCC_FLAG_MSIRDY ((uint8_t)0x29U)
AnnaBridge	143:86740a56073b	501	#define RCC_FLAG_HSERDY ((uint8_t)0x31U)
AnnaBridge	143:86740a56073b	502	#define RCC_FLAG_PLLRDY ((uint8_t)0x39U)
AnnaBridge	143:86740a56073b	503
AnnaBridge	143:86740a56073b	504	/* Flags in the CSR register */
AnnaBridge	143:86740a56073b	505	#define RCC_FLAG_LSERDY ((uint8_t)0x49U)
AnnaBridge	143:86740a56073b	506	#define RCC_FLAG_LSECSS ((uint8_t)0x4EU)
AnnaBridge	143:86740a56073b	507	#define RCC_FLAG_LSIRDY ((uint8_t)0x41U)
AnnaBridge	143:86740a56073b	508	#define RCC_FLAG_FWRST ((uint8_t)0x58U)
AnnaBridge	143:86740a56073b	509	#define RCC_FLAG_OBLRST ((uint8_t)0x59U)
AnnaBridge	143:86740a56073b	510	#define RCC_FLAG_PINRST ((uint8_t)0x5AU)
AnnaBridge	143:86740a56073b	511	#define RCC_FLAG_PORRST ((uint8_t)0x5BU)
AnnaBridge	143:86740a56073b	512	#define RCC_FLAG_SFTRST ((uint8_t)0x5CU)
AnnaBridge	143:86740a56073b	513	#define RCC_FLAG_IWDGRST ((uint8_t)0x5DU)
AnnaBridge	143:86740a56073b	514	#define RCC_FLAG_WWDGRST ((uint8_t)0x5EU)
AnnaBridge	143:86740a56073b	515	#define RCC_FLAG_LPWRRST ((uint8_t)0x5FU)
AnnaBridge	143:86740a56073b	516
AnnaBridge	143:86740a56073b	517	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge	143:86740a56073b	518	/* Flags in the CRRCR register */
AnnaBridge	143:86740a56073b	519	#define RCC_FLAG_HSI48RDY ((uint8_t)0x61U)
AnnaBridge	143:86740a56073b	520	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
AnnaBridge	143:86740a56073b	521
AnnaBridge	143:86740a56073b	522
AnnaBridge	143:86740a56073b	523	/**
AnnaBridge	143:86740a56073b	524	* @}
AnnaBridge	143:86740a56073b	525	*/
AnnaBridge	143:86740a56073b	526
AnnaBridge	143:86740a56073b	527	/**
AnnaBridge	143:86740a56073b	528	* @}
AnnaBridge	143:86740a56073b	529	*/
AnnaBridge	143:86740a56073b	530	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	531	/** @defgroup RCC_Exported_Macros RCC Exported Macros
AnnaBridge	143:86740a56073b	532	* @{
AnnaBridge	143:86740a56073b	533	*/
AnnaBridge	143:86740a56073b	534
AnnaBridge	143:86740a56073b	535	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable
AnnaBridge	143:86740a56073b	536	* @brief Enable or disable the AHB peripheral clock.
AnnaBridge	143:86740a56073b	537	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	143:86740a56073b	538	* is disabled and the application software has to enable this clock before
AnnaBridge	143:86740a56073b	539	* using it.
AnnaBridge	143:86740a56073b	540	* @{
AnnaBridge	143:86740a56073b	541	*/
AnnaBridge	143:86740a56073b	542	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
AnnaBridge	143:86740a56073b	543	__IO uint32_t tmpreg; \
AnnaBridge	143:86740a56073b	544	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
AnnaBridge	143:86740a56073b	545	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	143:86740a56073b	546	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
AnnaBridge	143:86740a56073b	547	UNUSED(tmpreg); \
AnnaBridge	143:86740a56073b	548	} while(0)
AnnaBridge	143:86740a56073b	549
AnnaBridge	143:86740a56073b	550	#define __HAL_RCC_MIF_CLK_ENABLE() do { \
AnnaBridge	143:86740a56073b	551	__IO uint32_t tmpreg; \
AnnaBridge	143:86740a56073b	552	SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
AnnaBridge	143:86740a56073b	553	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	143:86740a56073b	554	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
AnnaBridge	143:86740a56073b	555	UNUSED(tmpreg); \
AnnaBridge	143:86740a56073b	556	} while(0)
AnnaBridge	143:86740a56073b	557
AnnaBridge	143:86740a56073b	558	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	143:86740a56073b	559	__IO uint32_t tmpreg; \
AnnaBridge	143:86740a56073b	560	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
AnnaBridge	143:86740a56073b	561	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	143:86740a56073b	562	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
AnnaBridge	143:86740a56073b	563	UNUSED(tmpreg); \
AnnaBridge	143:86740a56073b	564	} while(0)
AnnaBridge	143:86740a56073b	565
AnnaBridge	143:86740a56073b	566
AnnaBridge	143:86740a56073b	567	#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
AnnaBridge	143:86740a56073b	568	#define __HAL_RCC_MIF_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN)
AnnaBridge	143:86740a56073b	569	#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
AnnaBridge	143:86740a56073b	570
AnnaBridge	143:86740a56073b	571	/**
AnnaBridge	143:86740a56073b	572	* @}
AnnaBridge	143:86740a56073b	573	*/
AnnaBridge	143:86740a56073b	574
AnnaBridge	143:86740a56073b	575	/** @defgroup RCC_IOPORT_Clock_Enable_Disable IOPORT Peripheral Clock Enable Disable
AnnaBridge	143:86740a56073b	576	* @brief Enable or disable the IOPORT peripheral clock.
AnnaBridge	143:86740a56073b	577	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	143:86740a56073b	578	* is disabled and the application software has to enable this clock before
AnnaBridge	143:86740a56073b	579	* using it.
AnnaBridge	143:86740a56073b	580	* @{
AnnaBridge	143:86740a56073b	581	*/
AnnaBridge	143:86740a56073b	582	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
AnnaBridge	143:86740a56073b	583	__IO uint32_t tmpreg; \
AnnaBridge	143:86740a56073b	584	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
AnnaBridge	143:86740a56073b	585	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	143:86740a56073b	586	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
AnnaBridge	143:86740a56073b	587	UNUSED(tmpreg); \
AnnaBridge	143:86740a56073b	588	} while(0)
AnnaBridge	143:86740a56073b	589
AnnaBridge	143:86740a56073b	590	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
AnnaBridge	143:86740a56073b	591	__IO uint32_t tmpreg; \
AnnaBridge	143:86740a56073b	592	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
AnnaBridge	143:86740a56073b	593	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	143:86740a56073b	594	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
AnnaBridge	143:86740a56073b	595	UNUSED(tmpreg); \
AnnaBridge	143:86740a56073b	596	} while(0)
AnnaBridge	143:86740a56073b	597
AnnaBridge	143:86740a56073b	598	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
AnnaBridge	143:86740a56073b	599	__IO uint32_t tmpreg; \
AnnaBridge	143:86740a56073b	600	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
AnnaBridge	143:86740a56073b	601	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	143:86740a56073b	602	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
AnnaBridge	143:86740a56073b	603	UNUSED(tmpreg); \
AnnaBridge	143:86740a56073b	604	} while(0)
AnnaBridge	143:86740a56073b	605
AnnaBridge	143:86740a56073b	606	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
AnnaBridge	143:86740a56073b	607	__IO uint32_t tmpreg; \
AnnaBridge	143:86740a56073b	608	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
AnnaBridge	143:86740a56073b	609	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	143:86740a56073b	610	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
AnnaBridge	143:86740a56073b	611	UNUSED(tmpreg); \
AnnaBridge	143:86740a56073b	612	} while(0)
AnnaBridge	143:86740a56073b	613
AnnaBridge	143:86740a56073b	614
AnnaBridge	143:86740a56073b	615	#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN)
AnnaBridge	143:86740a56073b	616	#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN)
AnnaBridge	143:86740a56073b	617	#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN)
AnnaBridge	143:86740a56073b	618	#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN)
AnnaBridge	143:86740a56073b	619
AnnaBridge	143:86740a56073b	620	/**
AnnaBridge	143:86740a56073b	621	* @}
AnnaBridge	143:86740a56073b	622	*/
AnnaBridge	143:86740a56073b	623
AnnaBridge	143:86740a56073b	624	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge	143:86740a56073b	625	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	143:86740a56073b	626	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	143:86740a56073b	627	* is disabled and the application software has to enable this clock before
AnnaBridge	143:86740a56073b	628	* using it.
AnnaBridge	143:86740a56073b	629	* @{
AnnaBridge	143:86740a56073b	630	*/
AnnaBridge	143:86740a56073b	631	#define __HAL_RCC_WWDG_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
AnnaBridge	143:86740a56073b	632	#define __HAL_RCC_PWR_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
AnnaBridge	143:86740a56073b	633
AnnaBridge	143:86740a56073b	634	#define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
AnnaBridge	143:86740a56073b	635	#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
AnnaBridge	143:86740a56073b	636	/**
AnnaBridge	143:86740a56073b	637	* @}
AnnaBridge	143:86740a56073b	638	*/
AnnaBridge	143:86740a56073b	639
AnnaBridge	143:86740a56073b	640	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge	143:86740a56073b	641	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	143:86740a56073b	642	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	143:86740a56073b	643	* is disabled and the application software has to enable this clock before
AnnaBridge	143:86740a56073b	644	* using it.
AnnaBridge	143:86740a56073b	645	* @{
AnnaBridge	143:86740a56073b	646	*/
AnnaBridge	143:86740a56073b	647	#define __HAL_RCC_SYSCFG_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
AnnaBridge	143:86740a56073b	648	#define __HAL_RCC_DBGMCU_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
AnnaBridge	143:86740a56073b	649
AnnaBridge	143:86740a56073b	650	#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
AnnaBridge	143:86740a56073b	651	#define __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
AnnaBridge	143:86740a56073b	652	/**
AnnaBridge	143:86740a56073b	653	* @}
AnnaBridge	143:86740a56073b	654	*/
AnnaBridge	143:86740a56073b	655
AnnaBridge	143:86740a56073b	656	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enabled or Disabled Status
AnnaBridge	143:86740a56073b	657	* @brief Check whether the AHB peripheral clock is enabled or not.
AnnaBridge	143:86740a56073b	658	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	143:86740a56073b	659	* is disabled and the application software has to enable this clock before
AnnaBridge	143:86740a56073b	660	* using it.
AnnaBridge	143:86740a56073b	661	* @{
AnnaBridge	143:86740a56073b	662	*/
AnnaBridge	143:86740a56073b	663
AnnaBridge	143:86740a56073b	664	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != RESET)
AnnaBridge	143:86740a56073b	665	#define __HAL_RCC_MIF_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) != RESET)
AnnaBridge	143:86740a56073b	666	#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != RESET)
AnnaBridge	143:86740a56073b	667
AnnaBridge	143:86740a56073b	668	/**
AnnaBridge	143:86740a56073b	669	* @}
AnnaBridge	143:86740a56073b	670	*/
AnnaBridge	143:86740a56073b	671
AnnaBridge	143:86740a56073b	672	/** @defgroup RCC_IOPORT_Peripheral_Clock_Enable_Disable_Status IOPORT Peripheral Clock Enabled or Disabled Status
AnnaBridge	143:86740a56073b	673	* @brief Check whether the IOPORT peripheral clock is enabled or not.
AnnaBridge	143:86740a56073b	674	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	143:86740a56073b	675	* is disabled and the application software has to enable this clock before
AnnaBridge	143:86740a56073b	676	* using it.
AnnaBridge	143:86740a56073b	677	* @{
AnnaBridge	143:86740a56073b	678	*/
AnnaBridge	143:86740a56073b	679
AnnaBridge	143:86740a56073b	680	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != RESET)
AnnaBridge	143:86740a56073b	681	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != RESET)
AnnaBridge	143:86740a56073b	682	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != RESET)
AnnaBridge	143:86740a56073b	683	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) != RESET)
AnnaBridge	143:86740a56073b	684
AnnaBridge	143:86740a56073b	685	/**
AnnaBridge	143:86740a56073b	686	* @}
AnnaBridge	143:86740a56073b	687	*/
AnnaBridge	143:86740a56073b	688
AnnaBridge	143:86740a56073b	689	/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
AnnaBridge	143:86740a56073b	690	* @brief Check whether the APB1 peripheral clock is enabled or not.
AnnaBridge	143:86740a56073b	691	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	143:86740a56073b	692	* is disabled and the application software has to enable this clock before
AnnaBridge	143:86740a56073b	693	* using it.
AnnaBridge	143:86740a56073b	694	* @{
AnnaBridge	143:86740a56073b	695	*/
AnnaBridge	143:86740a56073b	696	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) != RESET)
AnnaBridge	143:86740a56073b	697	#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) != RESET)
AnnaBridge	143:86740a56073b	698
AnnaBridge	143:86740a56073b	699	/**
AnnaBridge	143:86740a56073b	700	* @}
AnnaBridge	143:86740a56073b	701	*/
AnnaBridge	143:86740a56073b	702
AnnaBridge	143:86740a56073b	703	/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
AnnaBridge	143:86740a56073b	704	* @brief Check whether the APB2 peripheral clock is enabled or not.
AnnaBridge	143:86740a56073b	705	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	143:86740a56073b	706	* is disabled and the application software has to enable this clock before
AnnaBridge	143:86740a56073b	707	* using it.
AnnaBridge	143:86740a56073b	708	* @{
AnnaBridge	143:86740a56073b	709	*/
AnnaBridge	143:86740a56073b	710	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
AnnaBridge	143:86740a56073b	711	#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) != RESET)
AnnaBridge	143:86740a56073b	712
AnnaBridge	143:86740a56073b	713	/**
AnnaBridge	143:86740a56073b	714	* @}
AnnaBridge	143:86740a56073b	715	*/
AnnaBridge	143:86740a56073b	716
AnnaBridge	143:86740a56073b	717	/** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset
AnnaBridge	143:86740a56073b	718	* @brief Force or release AHB peripheral reset.
AnnaBridge	143:86740a56073b	719	* @{
AnnaBridge	143:86740a56073b	720	*/
AnnaBridge	143:86740a56073b	721	#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
AnnaBridge	143:86740a56073b	722	#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
AnnaBridge	143:86740a56073b	723	#define __HAL_RCC_MIF_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
AnnaBridge	143:86740a56073b	724	#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
AnnaBridge	143:86740a56073b	725
AnnaBridge	143:86740a56073b	726	#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00U)
AnnaBridge	143:86740a56073b	727	#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
AnnaBridge	143:86740a56073b	728	#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
AnnaBridge	143:86740a56073b	729	#define __HAL_RCC_MIF_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
AnnaBridge	143:86740a56073b	730	/**
AnnaBridge	143:86740a56073b	731	* @}
AnnaBridge	143:86740a56073b	732	*/
AnnaBridge	143:86740a56073b	733
AnnaBridge	143:86740a56073b	734	/** @defgroup RCC_IOPORT_Force_Release_Reset IOPORT Peripheral Force Release Reset
AnnaBridge	143:86740a56073b	735	* @brief Force or release IOPORT peripheral reset.
AnnaBridge	143:86740a56073b	736	* @{
AnnaBridge	143:86740a56073b	737	*/
AnnaBridge	143:86740a56073b	738	#define __HAL_RCC_IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFFU)
AnnaBridge	143:86740a56073b	739	#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
AnnaBridge	143:86740a56073b	740	#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
AnnaBridge	143:86740a56073b	741	#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
AnnaBridge	143:86740a56073b	742	#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))
AnnaBridge	143:86740a56073b	743
AnnaBridge	143:86740a56073b	744	#define __HAL_RCC_IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00U)
AnnaBridge	143:86740a56073b	745	#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
AnnaBridge	143:86740a56073b	746	#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
AnnaBridge	143:86740a56073b	747	#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
AnnaBridge	143:86740a56073b	748	#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))
AnnaBridge	143:86740a56073b	749
AnnaBridge	143:86740a56073b	750	/**
AnnaBridge	143:86740a56073b	751	* @}
AnnaBridge	143:86740a56073b	752	*/
AnnaBridge	143:86740a56073b	753
AnnaBridge	143:86740a56073b	754	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
AnnaBridge	143:86740a56073b	755	* @brief Force or release APB1 peripheral reset.
AnnaBridge	143:86740a56073b	756	* @{
AnnaBridge	143:86740a56073b	757	*/
AnnaBridge	143:86740a56073b	758	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
AnnaBridge	143:86740a56073b	759	#define __HAL_RCC_WWDG_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
AnnaBridge	143:86740a56073b	760	#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
AnnaBridge	143:86740a56073b	761
AnnaBridge	143:86740a56073b	762	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
AnnaBridge	143:86740a56073b	763	#define __HAL_RCC_WWDG_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
AnnaBridge	143:86740a56073b	764	#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
AnnaBridge	143:86740a56073b	765
AnnaBridge	143:86740a56073b	766	/**
AnnaBridge	143:86740a56073b	767	* @}
AnnaBridge	143:86740a56073b	768	*/
AnnaBridge	143:86740a56073b	769
AnnaBridge	143:86740a56073b	770	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
AnnaBridge	143:86740a56073b	771	* @brief Force or release APB2 peripheral reset.
AnnaBridge	143:86740a56073b	772	* @{
AnnaBridge	143:86740a56073b	773	*/
AnnaBridge	143:86740a56073b	774	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
AnnaBridge	143:86740a56073b	775	#define __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
AnnaBridge	143:86740a56073b	776	#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
AnnaBridge	143:86740a56073b	777
AnnaBridge	143:86740a56073b	778	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
AnnaBridge	143:86740a56073b	779	#define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
AnnaBridge	143:86740a56073b	780	#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
AnnaBridge	143:86740a56073b	781	/**
AnnaBridge	143:86740a56073b	782	* @}
AnnaBridge	143:86740a56073b	783	*/
AnnaBridge	143:86740a56073b	784
AnnaBridge	143:86740a56073b	785
AnnaBridge	143:86740a56073b	786	/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable AHB Peripheral Clock Sleep Enable Disable
AnnaBridge	143:86740a56073b	787	* @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
AnnaBridge	143:86740a56073b	788	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	143:86740a56073b	789	* power consumption.
AnnaBridge	143:86740a56073b	790	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	143:86740a56073b	791	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
AnnaBridge	143:86740a56073b	792	* @{
AnnaBridge	143:86740a56073b	793	*/
AnnaBridge	143:86740a56073b	794	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
AnnaBridge	143:86740a56073b	795	#define __HAL_RCC_MIF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
AnnaBridge	143:86740a56073b	796	#define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
AnnaBridge	143:86740a56073b	797	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
AnnaBridge	143:86740a56073b	798
AnnaBridge	143:86740a56073b	799	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
AnnaBridge	143:86740a56073b	800	#define __HAL_RCC_MIF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
AnnaBridge	143:86740a56073b	801	#define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
AnnaBridge	143:86740a56073b	802	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
AnnaBridge	143:86740a56073b	803	/**
AnnaBridge	143:86740a56073b	804	* @}
AnnaBridge	143:86740a56073b	805	*/
AnnaBridge	143:86740a56073b	806
AnnaBridge	143:86740a56073b	807	/** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable IOPORT Peripheral Clock Sleep Enable Disable
AnnaBridge	143:86740a56073b	808	* @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
AnnaBridge	143:86740a56073b	809	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	143:86740a56073b	810	* power consumption.
AnnaBridge	143:86740a56073b	811	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	143:86740a56073b	812	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
AnnaBridge	143:86740a56073b	813	* @{
AnnaBridge	143:86740a56073b	814	*/
AnnaBridge	143:86740a56073b	815
AnnaBridge	143:86740a56073b	816	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))
AnnaBridge	143:86740a56073b	817	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))
AnnaBridge	143:86740a56073b	818	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))
AnnaBridge	143:86740a56073b	819	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))
AnnaBridge	143:86740a56073b	820
AnnaBridge	143:86740a56073b	821	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))
AnnaBridge	143:86740a56073b	822	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))
AnnaBridge	143:86740a56073b	823	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))
AnnaBridge	143:86740a56073b	824	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))
AnnaBridge	143:86740a56073b	825	/**
AnnaBridge	143:86740a56073b	826	* @}
AnnaBridge	143:86740a56073b	827	*/
AnnaBridge	143:86740a56073b	828
AnnaBridge	143:86740a56073b	829	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
AnnaBridge	143:86740a56073b	830	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	143:86740a56073b	831	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	143:86740a56073b	832	* power consumption.
AnnaBridge	143:86740a56073b	833	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	143:86740a56073b	834	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
AnnaBridge	143:86740a56073b	835	* @{
AnnaBridge	143:86740a56073b	836	*/
AnnaBridge	143:86740a56073b	837	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN))
AnnaBridge	143:86740a56073b	838	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN))
AnnaBridge	143:86740a56073b	839
AnnaBridge	143:86740a56073b	840	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN))
AnnaBridge	143:86740a56073b	841	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN))
AnnaBridge	143:86740a56073b	842
AnnaBridge	143:86740a56073b	843	/**
AnnaBridge	143:86740a56073b	844	* @}
AnnaBridge	143:86740a56073b	845	*/
AnnaBridge	143:86740a56073b	846
AnnaBridge	143:86740a56073b	847	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
AnnaBridge	143:86740a56073b	848	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	143:86740a56073b	849	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	143:86740a56073b	850	* power consumption.
AnnaBridge	143:86740a56073b	851	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	143:86740a56073b	852	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
AnnaBridge	143:86740a56073b	853	* @{
AnnaBridge	143:86740a56073b	854	*/
AnnaBridge	143:86740a56073b	855	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN))
AnnaBridge	143:86740a56073b	856	#define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN))
AnnaBridge	143:86740a56073b	857
AnnaBridge	143:86740a56073b	858	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN))
AnnaBridge	143:86740a56073b	859	#define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN))
AnnaBridge	143:86740a56073b	860
AnnaBridge	143:86740a56073b	861	/**
AnnaBridge	143:86740a56073b	862	* @}
AnnaBridge	143:86740a56073b	863	*/
AnnaBridge	143:86740a56073b	864
AnnaBridge	143:86740a56073b	865	/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge	143:86740a56073b	866	* @brief Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge	143:86740a56073b	867	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	143:86740a56073b	868	* power consumption.
AnnaBridge	143:86740a56073b	869	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	143:86740a56073b	870	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	143:86740a56073b	871	* @{
AnnaBridge	143:86740a56073b	872	*/
AnnaBridge	143:86740a56073b	873	#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != RESET)
AnnaBridge	143:86740a56073b	874	#define __HAL_RCC_MIF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) != RESET)
AnnaBridge	143:86740a56073b	875	#define __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != RESET)
AnnaBridge	143:86740a56073b	876	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != RESET)
AnnaBridge	143:86740a56073b	877
AnnaBridge	143:86740a56073b	878	/**
AnnaBridge	143:86740a56073b	879	* @}
AnnaBridge	143:86740a56073b	880	*/
AnnaBridge	143:86740a56073b	881
AnnaBridge	143:86740a56073b	882	/** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable_Status IOPORT Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge	143:86740a56073b	883	* @brief Check whether the IOPORT peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge	143:86740a56073b	884	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	143:86740a56073b	885	* power consumption.
AnnaBridge	143:86740a56073b	886	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	143:86740a56073b	887	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	143:86740a56073b	888	* @{
AnnaBridge	143:86740a56073b	889	*/
AnnaBridge	143:86740a56073b	890	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) != RESET)
AnnaBridge	143:86740a56073b	891	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) != RESET)
AnnaBridge	143:86740a56073b	892	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) != RESET)
AnnaBridge	143:86740a56073b	893	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOHSMEN) != RESET)
AnnaBridge	143:86740a56073b	894
AnnaBridge	143:86740a56073b	895	/**
AnnaBridge	143:86740a56073b	896	* @}
AnnaBridge	143:86740a56073b	897	*/
AnnaBridge	143:86740a56073b	898
AnnaBridge	143:86740a56073b	899	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge	143:86740a56073b	900	* @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge	143:86740a56073b	901	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	143:86740a56073b	902	* power consumption.
AnnaBridge	143:86740a56073b	903	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	143:86740a56073b	904	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	143:86740a56073b	905	* @{
AnnaBridge	143:86740a56073b	906	*/
AnnaBridge	143:86740a56073b	907	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_WWDGSMEN) != RESET)
AnnaBridge	143:86740a56073b	908	#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_PWRSMEN) != RESET)
AnnaBridge	143:86740a56073b	909
AnnaBridge	143:86740a56073b	910	/**
AnnaBridge	143:86740a56073b	911	* @}
AnnaBridge	143:86740a56073b	912	*/
AnnaBridge	143:86740a56073b	913
AnnaBridge	143:86740a56073b	914	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge	143:86740a56073b	915	* @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge	143:86740a56073b	916	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	143:86740a56073b	917	* power consumption.
AnnaBridge	143:86740a56073b	918	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	143:86740a56073b	919	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	143:86740a56073b	920	* @{
AnnaBridge	143:86740a56073b	921	*/
AnnaBridge	143:86740a56073b	922	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
AnnaBridge	143:86740a56073b	923	#define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DBGMCUSMEN) != RESET)
AnnaBridge	143:86740a56073b	924
AnnaBridge	143:86740a56073b	925	/**
AnnaBridge	143:86740a56073b	926	* @}
AnnaBridge	143:86740a56073b	927	*/
AnnaBridge	143:86740a56073b	928
AnnaBridge	143:86740a56073b	929	/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
AnnaBridge	143:86740a56073b	930	* @{
AnnaBridge	143:86740a56073b	931	*/
AnnaBridge	143:86740a56073b	932
AnnaBridge	143:86740a56073b	933	/** @brief Macros to force or release the Backup domain reset.
AnnaBridge	143:86740a56073b	934	* @note This function resets the RTC peripheral (including the backup registers)
AnnaBridge	143:86740a56073b	935	* and the RTC clock source selection in RCC_CSR register.
AnnaBridge	143:86740a56073b	936	* @note The BKPSRAM is not affected by this reset.
AnnaBridge	143:86740a56073b	937	*/
AnnaBridge	143:86740a56073b	938	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR, RCC_CSR_RTCRST)
AnnaBridge	143:86740a56073b	939	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST)
AnnaBridge	143:86740a56073b	940
AnnaBridge	143:86740a56073b	941	/**
AnnaBridge	143:86740a56073b	942	* @}
AnnaBridge	143:86740a56073b	943	*/
AnnaBridge	143:86740a56073b	944
AnnaBridge	143:86740a56073b	945	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
AnnaBridge	143:86740a56073b	946	* @{
AnnaBridge	143:86740a56073b	947	*/
AnnaBridge	143:86740a56073b	948
AnnaBridge	143:86740a56073b	949	/** @brief Macros to enable or disable the the RTC clock.
AnnaBridge	143:86740a56073b	950	* @note These macros must be used only after the RTC clock source was selected.
AnnaBridge	143:86740a56073b	951	*/
AnnaBridge	143:86740a56073b	952	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN)
AnnaBridge	143:86740a56073b	953	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN)
AnnaBridge	143:86740a56073b	954
AnnaBridge	143:86740a56073b	955	/**
AnnaBridge	143:86740a56073b	956	* @}
AnnaBridge	143:86740a56073b	957	*/
AnnaBridge	143:86740a56073b	958
AnnaBridge	143:86740a56073b	959	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
AnnaBridge	143:86740a56073b	960	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	143:86740a56073b	961	* It is used (enabled by hardware) as system clock source after startup
AnnaBridge	143:86740a56073b	962	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
AnnaBridge	143:86740a56073b	963	* of the HSE used directly or indirectly as system clock (if the Clock
AnnaBridge	143:86740a56073b	964	* Security System CSS is enabled).
AnnaBridge	143:86740a56073b	965	* @note HSI can not be stopped if it is used as system clock source. In this case,
AnnaBridge	143:86740a56073b	966	* you have to select another source of the system clock then stop the HSI.
AnnaBridge	143:86740a56073b	967	* @note After enabling the HSI, the application software should wait on HSIRDY
AnnaBridge	143:86740a56073b	968	* flag to be set indicating that HSI clock is stable and can be used as
AnnaBridge	143:86740a56073b	969	* system clock source.
AnnaBridge	143:86740a56073b	970	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
AnnaBridge	143:86740a56073b	971	* clock cycles.
AnnaBridge	143:86740a56073b	972	*/
AnnaBridge	143:86740a56073b	973	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
AnnaBridge	143:86740a56073b	974	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
AnnaBridge	143:86740a56073b	975
AnnaBridge	143:86740a56073b	976	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
AnnaBridge	143:86740a56073b	977	* @note The calibration is used to compensate for the variations in voltage
AnnaBridge	143:86740a56073b	978	* and temperature that influence the frequency of the internal HSI RC.
AnnaBridge	143:86740a56073b	979	* @param __HSICalibrationValue__: specifies the calibration trimming value.
AnnaBridge	143:86740a56073b	980	* This parameter must be a number between 0 and 0x1F.
AnnaBridge	143:86740a56073b	981	*/
AnnaBridge	143:86740a56073b	982	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
AnnaBridge	143:86740a56073b	983	RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << 8U))
AnnaBridge	143:86740a56073b	984
AnnaBridge	143:86740a56073b	985	/** @brief Macro to enable or disable the Internal High Speed oscillator (HSI).
AnnaBridge	143:86740a56073b	986	* @note After enabling the HSI, the application software should wait on
AnnaBridge	143:86740a56073b	987	* HSIRDY flag to be set indicating that HSI clock is stable and can
AnnaBridge	143:86740a56073b	988	* be used to clock the PLL and/or system clock.
AnnaBridge	143:86740a56073b	989	* @note HSI can not be stopped if it is used directly or through the PLL
AnnaBridge	143:86740a56073b	990	* as system clock. In this case, you have to select another source
AnnaBridge	143:86740a56073b	991	* of the system clock then stop the HSI.
AnnaBridge	143:86740a56073b	992	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	143:86740a56073b	993	* @param __STATE__: specifies the new state of the HSI.
AnnaBridge	143:86740a56073b	994	* This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	995	* @arg RCC_HSI_OFF: turn OFF the HSI oscillator
AnnaBridge	143:86740a56073b	996	* @arg RCC_HSI_ON: turn ON the HSI oscillator
AnnaBridge	143:86740a56073b	997	* @arg RCC_HSI_DIV4: turn ON the HSI oscillator and divide it by 4
AnnaBridge	143:86740a56073b	998	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
AnnaBridge	143:86740a56073b	999	* clock cycles.
AnnaBridge	143:86740a56073b	1000	*/
AnnaBridge	143:86740a56073b	1001	#define __HAL_RCC_HSI_CONFIG(__STATE__) \
AnnaBridge	143:86740a56073b	1002	MODIFY_REG(RCC->CR, RCC_CR_HSION \| RCC_CR_HSIDIVEN , (uint32_t)(__STATE__))
AnnaBridge	143:86740a56073b	1003
AnnaBridge	143:86740a56073b	1004	/**
AnnaBridge	143:86740a56073b	1005	* @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
AnnaBridge	143:86740a56073b	1006	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	143:86740a56073b	1007	* It is used (enabled by hardware) as system clock source after
AnnaBridge	143:86740a56073b	1008	* startup from Reset, wakeup from STOP and STANDBY mode, or in case
AnnaBridge	143:86740a56073b	1009	* of failure of the HSE used directly or indirectly as system clock
AnnaBridge	143:86740a56073b	1010	* (if the Clock Security System CSS is enabled).
AnnaBridge	143:86740a56073b	1011	* @note MSI can not be stopped if it is used as system clock source.
AnnaBridge	143:86740a56073b	1012	* In this case, you have to select another source of the system
AnnaBridge	143:86740a56073b	1013	* clock then stop the MSI.
AnnaBridge	143:86740a56073b	1014	* @note After enabling the MSI, the application software should wait on
AnnaBridge	143:86740a56073b	1015	* MSIRDY flag to be set indicating that MSI clock is stable and can
AnnaBridge	143:86740a56073b	1016	* be used as system clock source.
AnnaBridge	143:86740a56073b	1017	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
AnnaBridge	143:86740a56073b	1018	* clock cycles.
AnnaBridge	143:86740a56073b	1019	*/
AnnaBridge	143:86740a56073b	1020	#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
AnnaBridge	143:86740a56073b	1021	#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
AnnaBridge	143:86740a56073b	1022
AnnaBridge	143:86740a56073b	1023
AnnaBridge	143:86740a56073b	1024	/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
AnnaBridge	143:86740a56073b	1025	* @note The calibration is used to compensate for the variations in voltage
AnnaBridge	143:86740a56073b	1026	* and temperature that influence the frequency of the internal MSI RC.
AnnaBridge	143:86740a56073b	1027	* Refer to the Application Note AN3300 for more details on how to
AnnaBridge	143:86740a56073b	1028	* calibrate the MSI.
AnnaBridge	143:86740a56073b	1029	* @param __MSICalibrationValue__: specifies the calibration trimming value.
AnnaBridge	143:86740a56073b	1030	* This parameter must be a number between 0 and 0xFF.
AnnaBridge	143:86740a56073b	1031	*/
AnnaBridge	143:86740a56073b	1032	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
AnnaBridge	143:86740a56073b	1033	RCC_ICSCR_MSITRIM, (uint32_t)(__MSICalibrationValue__) << 24U))
AnnaBridge	143:86740a56073b	1034
AnnaBridge	143:86740a56073b	1035	/**
AnnaBridge	143:86740a56073b	1036	* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
AnnaBridge	143:86740a56073b	1037	* @note After restart from Reset or wakeup from STANDBY, the MSI clock is
AnnaBridge	143:86740a56073b	1038	* around 2.097 MHz. The MSI clock does not change after wake-up from
AnnaBridge	143:86740a56073b	1039	* STOP mode.
AnnaBridge	143:86740a56073b	1040	* @note The MSI clock range can be modified on the fly.
AnnaBridge	143:86740a56073b	1041	* @param __RCC_MSIRange__: specifies the MSI Clock range.
AnnaBridge	143:86740a56073b	1042	* This parameter must be one of the following values:
AnnaBridge	143:86740a56073b	1043	* @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
AnnaBridge	143:86740a56073b	1044	* @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
AnnaBridge	143:86740a56073b	1045	* @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
AnnaBridge	143:86740a56073b	1046	* @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
AnnaBridge	143:86740a56073b	1047	* @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
AnnaBridge	143:86740a56073b	1048	* @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
AnnaBridge	143:86740a56073b	1049	* @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
AnnaBridge	143:86740a56073b	1050	*/
AnnaBridge	143:86740a56073b	1051	#define __HAL_RCC_MSI_RANGE_CONFIG(__RCC_MSIRange__) (MODIFY_REG(RCC->ICSCR,\
AnnaBridge	143:86740a56073b	1052	RCC_ICSCR_MSIRANGE, (uint32_t)(__RCC_MSIRange__) ))
AnnaBridge	143:86740a56073b	1053
AnnaBridge	143:86740a56073b	1054	/** @brief Macro to get the Internal Multi Speed oscillator (__MSI__) clock range in run mode
AnnaBridge	143:86740a56073b	1055	* @retval MSI clock range.
AnnaBridge	143:86740a56073b	1056	* This parameter must be one of the following values:
AnnaBridge	143:86740a56073b	1057	* @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
AnnaBridge	143:86740a56073b	1058	* @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
AnnaBridge	143:86740a56073b	1059	* @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
AnnaBridge	143:86740a56073b	1060	* @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
AnnaBridge	143:86740a56073b	1061	* @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
AnnaBridge	143:86740a56073b	1062	* @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
AnnaBridge	143:86740a56073b	1063	* @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
AnnaBridge	143:86740a56073b	1064
AnnaBridge	143:86740a56073b	1065	*/
AnnaBridge	143:86740a56073b	1066	#define __HAL_RCC_GET_MSI_RANGE() \
AnnaBridge	143:86740a56073b	1067	((uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE) >> 12U))
AnnaBridge	143:86740a56073b	1068
AnnaBridge	143:86740a56073b	1069	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
AnnaBridge	143:86740a56073b	1070	* @note After enabling the LSI, the application software should wait on
AnnaBridge	143:86740a56073b	1071	* LSIRDY flag to be set indicating that LSI clock is stable and can
AnnaBridge	143:86740a56073b	1072	* be used to clock the IWDG and/or the RTC.
AnnaBridge	143:86740a56073b	1073	* @note LSI can not be disabled if the IWDG is running.
AnnaBridge	143:86740a56073b	1074	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
AnnaBridge	143:86740a56073b	1075	* clock cycles.
AnnaBridge	143:86740a56073b	1076	*/
AnnaBridge	143:86740a56073b	1077	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
AnnaBridge	143:86740a56073b	1078	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
AnnaBridge	143:86740a56073b	1079
AnnaBridge	143:86740a56073b	1080	/**
AnnaBridge	143:86740a56073b	1081	* @brief Macro to configure the External High Speed oscillator (HSE).
AnnaBridge	143:86740a56073b	1082	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
AnnaBridge	143:86740a56073b	1083	* supported by this macro. User should request a transition to HSE Off
AnnaBridge	143:86740a56073b	1084	* first and then HSE On or HSE Bypass.
AnnaBridge	143:86740a56073b	1085	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
AnnaBridge	143:86740a56073b	1086	* software should wait on HSERDY flag to be set indicating that HSE clock
AnnaBridge	143:86740a56073b	1087	* is stable and can be used to clock the PLL and/or system clock.
AnnaBridge	143:86740a56073b	1088	* @note HSE state can not be changed if it is used directly or through the
AnnaBridge	143:86740a56073b	1089	* PLL as system clock. In this case, you have to select another source
AnnaBridge	143:86740a56073b	1090	* of the system clock then change the HSE state (ex. disable it).
AnnaBridge	143:86740a56073b	1091	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	143:86740a56073b	1092	* @note This function reset the CSSON bit, so if the clock security system(CSS)
AnnaBridge	143:86740a56073b	1093	* was previously enabled you have to enable it again after calling this
AnnaBridge	143:86740a56073b	1094	* function.
AnnaBridge	143:86740a56073b	1095	* @param __STATE__: specifies the new state of the HSE.
AnnaBridge	143:86740a56073b	1096	* This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1097	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
AnnaBridge	143:86740a56073b	1098	* 6 HSE oscillator clock cycles.
AnnaBridge	143:86740a56073b	1099	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
AnnaBridge	143:86740a56073b	1100	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
AnnaBridge	143:86740a56073b	1101	*/
AnnaBridge	143:86740a56073b	1102	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
AnnaBridge	143:86740a56073b	1103	do { \
AnnaBridge	143:86740a56073b	1104	__IO uint32_t tmpreg; \
AnnaBridge	143:86740a56073b	1105	if((__STATE__) == RCC_HSE_ON) \
AnnaBridge	143:86740a56073b	1106	{ \
AnnaBridge	143:86740a56073b	1107	SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	143:86740a56073b	1108	} \
AnnaBridge	143:86740a56073b	1109	else if((__STATE__) == RCC_HSE_BYPASS) \
AnnaBridge	143:86740a56073b	1110	{ \
AnnaBridge	143:86740a56073b	1111	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	143:86740a56073b	1112	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge	143:86740a56073b	1113	SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	143:86740a56073b	1114	} \
AnnaBridge	143:86740a56073b	1115	else \
AnnaBridge	143:86740a56073b	1116	{ \
AnnaBridge	143:86740a56073b	1117	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	143:86740a56073b	1118	/* Delay after an RCC peripheral clock */ \
AnnaBridge	143:86740a56073b	1119	tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	143:86740a56073b	1120	UNUSED(tmpreg); \
AnnaBridge	143:86740a56073b	1121	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge	143:86740a56073b	1122	} \
AnnaBridge	143:86740a56073b	1123	} while(0)
AnnaBridge	143:86740a56073b	1124
AnnaBridge	143:86740a56073b	1125	/**
AnnaBridge	143:86740a56073b	1126	* @brief Macro to configure the External Low Speed oscillator (LSE).
AnnaBridge	143:86740a56073b	1127	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
AnnaBridge	143:86740a56073b	1128	* supported by this macro. User should request a transition to LSE Off
AnnaBridge	143:86740a56073b	1129	* first and then LSE On or LSE Bypass.
AnnaBridge	143:86740a56073b	1130	* @note As the LSE is in the Backup domain and write access is denied to
AnnaBridge	143:86740a56073b	1131	* this domain after reset, you have to enable write access using
AnnaBridge	143:86740a56073b	1132	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
AnnaBridge	143:86740a56073b	1133	* (to be done once after reset).
AnnaBridge	143:86740a56073b	1134	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
AnnaBridge	143:86740a56073b	1135	* software should wait on LSERDY flag to be set indicating that LSE clock
AnnaBridge	143:86740a56073b	1136	* is stable and can be used to clock the RTC.
AnnaBridge	143:86740a56073b	1137	* @param __STATE__: specifies the new state of the LSE.
AnnaBridge	143:86740a56073b	1138	* This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1139	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
AnnaBridge	143:86740a56073b	1140	* 6 LSE oscillator clock cycles.
AnnaBridge	143:86740a56073b	1141	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
AnnaBridge	143:86740a56073b	1142	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
AnnaBridge	143:86740a56073b	1143	*/
AnnaBridge	143:86740a56073b	1144	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
AnnaBridge	143:86740a56073b	1145	do { \
AnnaBridge	143:86740a56073b	1146	if((__STATE__) == RCC_LSE_ON) \
AnnaBridge	143:86740a56073b	1147	{ \
AnnaBridge	143:86740a56073b	1148	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
AnnaBridge	143:86740a56073b	1149	} \
AnnaBridge	143:86740a56073b	1150	else if((__STATE__) == RCC_LSE_OFF) \
AnnaBridge	143:86740a56073b	1151	{ \
AnnaBridge	143:86740a56073b	1152	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
AnnaBridge	143:86740a56073b	1153	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
AnnaBridge	143:86740a56073b	1154	} \
AnnaBridge	143:86740a56073b	1155	else if((__STATE__) == RCC_LSE_BYPASS) \
AnnaBridge	143:86740a56073b	1156	{ \
AnnaBridge	143:86740a56073b	1157	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
AnnaBridge	143:86740a56073b	1158	SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
AnnaBridge	143:86740a56073b	1159	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
AnnaBridge	143:86740a56073b	1160	} \
AnnaBridge	143:86740a56073b	1161	else \
AnnaBridge	143:86740a56073b	1162	{ \
AnnaBridge	143:86740a56073b	1163	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
AnnaBridge	143:86740a56073b	1164	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
AnnaBridge	143:86740a56073b	1165	} \
AnnaBridge	143:86740a56073b	1166	} while(0)
AnnaBridge	143:86740a56073b	1167
AnnaBridge	143:86740a56073b	1168
AnnaBridge	143:86740a56073b	1169
AnnaBridge	143:86740a56073b	1170	/**
AnnaBridge	143:86740a56073b	1171	* @brief Configures or Get the RTC and LCD clock (RTCCLK / LCDCLK).
AnnaBridge	143:86740a56073b	1172	* @note As the RTC clock configuration bits are in the RTC domain and write
AnnaBridge	143:86740a56073b	1173	* access is denied to this domain after reset, you have to enable write
AnnaBridge	143:86740a56073b	1174	* access using PWR_RTCAccessCmd(ENABLE) function before to configure
AnnaBridge	143:86740a56073b	1175	* the RTC clock source (to be done once after reset).
AnnaBridge	143:86740a56073b	1176	* @note Once the RTC clock is configured it cannot be changed unless the RTC
AnnaBridge	143:86740a56073b	1177	* is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)
AnnaBridge	143:86740a56073b	1178	* @note The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).
AnnaBridge	143:86740a56073b	1179	*
AnnaBridge	143:86740a56073b	1180	* @param __RTCCLKSOURCE__: specifies the RTC clock source.
AnnaBridge	143:86740a56073b	1181	* This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1182	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
AnnaBridge	143:86740a56073b	1183	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
AnnaBridge	143:86740a56073b	1184	* @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock
AnnaBridge	143:86740a56073b	1185	* @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock
AnnaBridge	143:86740a56073b	1186	* @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock
AnnaBridge	143:86740a56073b	1187	* @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock
AnnaBridge	143:86740a56073b	1188	*
AnnaBridge	143:86740a56073b	1189	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
AnnaBridge	143:86740a56073b	1190	* work in STOP and STANDBY modes, and can be used as wakeup source.
AnnaBridge	143:86740a56073b	1191	* However, when the HSE clock is used as RTC clock source, the RTC
AnnaBridge	143:86740a56073b	1192	* cannot be used in STOP and STANDBY modes.
AnnaBridge	143:86740a56073b	1193	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
AnnaBridge	143:86740a56073b	1194	* RTC clock source).
AnnaBridge	143:86740a56073b	1195	*/
AnnaBridge	143:86740a56073b	1196
AnnaBridge	143:86740a56073b	1197	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSOURCE__) (((__RTCCLKSOURCE__) & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL) ? \
AnnaBridge	143:86740a56073b	1198	MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, (uint32_t)((__RTCCLKSOURCE__) & RCC_CR_RTCPRE)) : \
AnnaBridge	143:86740a56073b	1199	CLEAR_BIT(RCC->CR, RCC_CR_RTCPRE)
AnnaBridge	143:86740a56073b	1200
AnnaBridge	143:86740a56073b	1201	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSOURCE__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSOURCE__); \
AnnaBridge	143:86740a56073b	1202	MODIFY_REG( RCC->CSR, RCC_CSR_RTCSEL, (uint32_t)((__RTCCLKSOURCE__) & RCC_CSR_RTCSEL)); \
AnnaBridge	143:86740a56073b	1203	} while (0)
AnnaBridge	143:86740a56073b	1204
AnnaBridge	143:86740a56073b	1205
AnnaBridge	143:86740a56073b	1206	/**
AnnaBridge	143:86740a56073b	1207	* @brief Get the RTC and LCD clock (RTCCLK / LCDCLK).
AnnaBridge	143:86740a56073b	1208	*
AnnaBridge	143:86740a56073b	1209	* @retval The clock source can be one of the following values:
AnnaBridge	143:86740a56073b	1210	* @arg RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock
AnnaBridge	143:86740a56073b	1211	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
AnnaBridge	143:86740a56073b	1212	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
AnnaBridge	143:86740a56073b	1213	* @arg RCC_RTCCLKSOURCE_HSE_DIVX: HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
AnnaBridge	143:86740a56073b	1214	*
AnnaBridge	143:86740a56073b	1215	*/
AnnaBridge	143:86740a56073b	1216	#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)))
AnnaBridge	143:86740a56073b	1217
AnnaBridge	143:86740a56073b	1218	/**
AnnaBridge	143:86740a56073b	1219	* @brief Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK).
AnnaBridge	143:86740a56073b	1220	*
AnnaBridge	143:86740a56073b	1221	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	1222	* @arg RCC_RTC_HSE_DIV_2: HSE divided by 2 selected as RTC clock
AnnaBridge	143:86740a56073b	1223	* @arg RCC_RTC_HSE_DIV_4: HSE divided by 4 selected as RTC clock
AnnaBridge	143:86740a56073b	1224	* @arg RCC_RTC_HSE_DIV_8: HSE divided by 8 selected as RTC clock
AnnaBridge	143:86740a56073b	1225	* @arg RCC_RTC_HSE_DIV_16: HSE divided by 16 selected as RTC clock
AnnaBridge	143:86740a56073b	1226	*
AnnaBridge	143:86740a56073b	1227	*/
AnnaBridge	143:86740a56073b	1228	#define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)))
AnnaBridge	143:86740a56073b	1229
AnnaBridge	143:86740a56073b	1230
AnnaBridge	143:86740a56073b	1231	/** @brief Macros to enable or disable the main PLL.
AnnaBridge	143:86740a56073b	1232	* @note After enabling the main PLL, the application software should wait on
AnnaBridge	143:86740a56073b	1233	* PLLRDY flag to be set indicating that PLL clock is stable and can
AnnaBridge	143:86740a56073b	1234	* be used as system clock source.
AnnaBridge	143:86740a56073b	1235	* @note The main PLL can not be disabled if it is used as system clock source
AnnaBridge	143:86740a56073b	1236	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	143:86740a56073b	1237	*/
AnnaBridge	143:86740a56073b	1238	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
AnnaBridge	143:86740a56073b	1239	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
AnnaBridge	143:86740a56073b	1240
AnnaBridge	143:86740a56073b	1241	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
AnnaBridge	143:86740a56073b	1242	* @note This function must be used only when the main PLL is disabled.
AnnaBridge	143:86740a56073b	1243	* @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
AnnaBridge	143:86740a56073b	1244	* This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1245	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
AnnaBridge	143:86740a56073b	1246	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
AnnaBridge	143:86740a56073b	1247	* @param __PLLMUL__: specifies the multiplication factor to generate the PLL VCO clock
AnnaBridge	143:86740a56073b	1248	* This parameter must be one of the following values:
AnnaBridge	143:86740a56073b	1249	* @arg RCC_CFGR_PLLMUL3: PLLVCO = PLL clock entry x 3
AnnaBridge	143:86740a56073b	1250	* @arg RCC_CFGR_PLLMUL4: PLLVCO = PLL clock entry x 4
AnnaBridge	143:86740a56073b	1251	* @arg RCC_CFGR_PLLMUL6: PLLVCO = PLL clock entry x 6
AnnaBridge	143:86740a56073b	1252	* @arg RCC_CFGR_PLLMUL8: PLLVCO = PLL clock entry x 8
AnnaBridge	143:86740a56073b	1253	* @arg RCC_CFGR_PLLMUL12: PLLVCO = PLL clock entry x 12
AnnaBridge	143:86740a56073b	1254	* @arg RCC_CFGR_PLLMUL16: PLLVCO = PLL clock entry x 16
AnnaBridge	143:86740a56073b	1255	* @arg RCC_CFGR_PLLMUL24: PLLVCO = PLL clock entry x 24
AnnaBridge	143:86740a56073b	1256	* @arg RCC_CFGR_PLLMUL32: PLLVCO = PLL clock entry x 32
AnnaBridge	143:86740a56073b	1257	* @arg RCC_CFGR_PLLMUL48: PLLVCO = PLL clock entry x 48
AnnaBridge	143:86740a56073b	1258	* @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
AnnaBridge	143:86740a56073b	1259	* Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
AnnaBridge	143:86740a56073b	1260	* in Range 3.
AnnaBridge	143:86740a56073b	1261	* @param __PLLDIV__: specifies the PLL output clock division from PLL VCO clock
AnnaBridge	143:86740a56073b	1262	* This parameter must be one of the following values:
AnnaBridge	143:86740a56073b	1263	* @arg RCC_PLLDIV_2: PLL clock output = PLLVCO / 2
AnnaBridge	143:86740a56073b	1264	* @arg RCC_PLLDIV_3: PLL clock output = PLLVCO / 3
AnnaBridge	143:86740a56073b	1265	* @arg RCC_PLLDIV_4: PLL clock output = PLLVCO / 4
AnnaBridge	143:86740a56073b	1266	*/
AnnaBridge	143:86740a56073b	1267
AnnaBridge	143:86740a56073b	1268	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PLLMUL__ ,__PLLDIV__ ) \
AnnaBridge	143:86740a56073b	1269	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLDIV \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\| (__PLLDIV__)\| (__RCC_PLLSOURCE__)))
AnnaBridge	143:86740a56073b	1270
AnnaBridge	143:86740a56073b	1271	/** @brief Macro to get the oscillator used as PLL clock source.
AnnaBridge	143:86740a56073b	1272	* @retval The oscillator used as PLL clock source. The returned value can be one
AnnaBridge	143:86740a56073b	1273	* of the following:
AnnaBridge	143:86740a56073b	1274	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
AnnaBridge	143:86740a56073b	1275	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
AnnaBridge	143:86740a56073b	1276	*/
AnnaBridge	143:86740a56073b	1277	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC))
AnnaBridge	143:86740a56073b	1278
AnnaBridge	143:86740a56073b	1279	/**
AnnaBridge	143:86740a56073b	1280	* @brief Macro to configure the system clock source.
AnnaBridge	143:86740a56073b	1281	* @param __SYSCLKSOURCE__: specifies the system clock source.
AnnaBridge	143:86740a56073b	1282	* This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1283	* - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
AnnaBridge	143:86740a56073b	1284	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
AnnaBridge	143:86740a56073b	1285	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
AnnaBridge	143:86740a56073b	1286	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
AnnaBridge	143:86740a56073b	1287	* @retval None
AnnaBridge	143:86740a56073b	1288	*/
AnnaBridge	143:86740a56073b	1289	#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
AnnaBridge	143:86740a56073b	1290	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
AnnaBridge	143:86740a56073b	1291
AnnaBridge	143:86740a56073b	1292	/** @brief Macro to get the clock source used as system clock.
AnnaBridge	143:86740a56073b	1293	* @retval The clock source used as system clock. The returned value can be one
AnnaBridge	143:86740a56073b	1294	* of the following:
AnnaBridge	143:86740a56073b	1295	* - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
AnnaBridge	143:86740a56073b	1296	* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
AnnaBridge	143:86740a56073b	1297	* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
AnnaBridge	143:86740a56073b	1298	* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
AnnaBridge	143:86740a56073b	1299	*/
AnnaBridge	143:86740a56073b	1300	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
AnnaBridge	143:86740a56073b	1301
AnnaBridge	143:86740a56073b	1302
AnnaBridge	143:86740a56073b	1303	/** @brief Macro to configure the MCO clock.
AnnaBridge	143:86740a56073b	1304	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
AnnaBridge	143:86740a56073b	1305	* This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1306	* @arg RCC_CFGR_MCO_HSI: HSI clock selected as MCO source
AnnaBridge	143:86740a56073b	1307	* @arg RCC_CFGR_MCO_MSI: MSI clock selected as MCO source
AnnaBridge	143:86740a56073b	1308	* @arg RCC_CFGR_MCO_HSE: HSE clock selected as MCO source
AnnaBridge	143:86740a56073b	1309	* @arg RCC_CFGR_MCO_PLL: PLL clock selected as MCO source
AnnaBridge	143:86740a56073b	1310	* @arg RCC_CFGR_MCO_LSI: LSI clock selected as MCO source
AnnaBridge	143:86740a56073b	1311	* @arg RCC_CFGR_MCO_LSE: LSE clock selected as MCO source
AnnaBridge	143:86740a56073b	1312	* @param __MCODIV__ specifies the MCO clock prescaler.
AnnaBridge	143:86740a56073b	1313	* This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1314	* @arg RCC_CFGR_MCO_PRE_1: no division applied to MCO clock
AnnaBridge	143:86740a56073b	1315	* @arg RCC_CFGR_MCO_PRE_2: division by 2 applied to MCO clock
AnnaBridge	143:86740a56073b	1316	* @arg RCC_CFGR_MCO_PRE_4: division by 4 applied to MCO clock
AnnaBridge	143:86740a56073b	1317	* @arg RCC_CFGR_MCO_PRE_8: division by 8 applied to MCO clock
AnnaBridge	143:86740a56073b	1318	* @arg RCC_CFGR_MCO_PRE_16: division by 16 applied to MCO clock
AnnaBridge	143:86740a56073b	1319	*/
AnnaBridge	143:86740a56073b	1320
AnnaBridge	143:86740a56073b	1321	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
AnnaBridge	143:86740a56073b	1322	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL \| RCC_CFGR_MCO_PRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
AnnaBridge	143:86740a56073b	1323
AnnaBridge	143:86740a56073b	1324
AnnaBridge	143:86740a56073b	1325	/** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management
AnnaBridge	143:86740a56073b	1326	* @brief macros to manage the specified RCC Flags and interrupts.
AnnaBridge	143:86740a56073b	1327	* @{
AnnaBridge	143:86740a56073b	1328	*/
AnnaBridge	143:86740a56073b	1329
AnnaBridge	143:86740a56073b	1330	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to enable
AnnaBridge	143:86740a56073b	1331	* the selected interrupts).
AnnaBridge	143:86740a56073b	1332	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
AnnaBridge	143:86740a56073b	1333	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
AnnaBridge	143:86740a56073b	1334	* automatically generated. The NMI will be executed indefinitely, and
AnnaBridge	143:86740a56073b	1335	* since NMI has higher priority than any other IRQ (and main program)
AnnaBridge	143:86740a56073b	1336	* the application will be stacked in the NMI ISR unless the CSS interrupt
AnnaBridge	143:86740a56073b	1337	* pending bit is cleared.
AnnaBridge	143:86740a56073b	1338	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
AnnaBridge	143:86740a56073b	1339	* This parameter can be any combination of the following values:
AnnaBridge	143:86740a56073b	1340	* @arg RCC_IT_LSIRDY: LSI ready interrupt
AnnaBridge	143:86740a56073b	1341	* @arg RCC_IT_LSERDY: LSE ready interrupt
AnnaBridge	143:86740a56073b	1342	* @arg RCC_IT_HSIRDY: HSI ready interrupt
AnnaBridge	143:86740a56073b	1343	* @arg RCC_IT_HSERDY: HSE ready interrupt
AnnaBridge	143:86740a56073b	1344	* @arg RCC_IT_PLLRDY: PLL ready interrupt
AnnaBridge	143:86740a56073b	1345	* @arg RCC_IT_MSIRDY: MSI ready interrupt
AnnaBridge	143:86740a56073b	1346	* @arg RCC_IT_CSSLSE: LSE CSS interrupt
AnnaBridge	143:86740a56073b	1347	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
AnnaBridge	143:86740a56073b	1348	*/
AnnaBridge	143:86740a56073b	1349	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
AnnaBridge	143:86740a56073b	1350
AnnaBridge	143:86740a56073b	1351	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to disable
AnnaBridge	143:86740a56073b	1352	* the selected interrupts).
AnnaBridge	143:86740a56073b	1353	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
AnnaBridge	143:86740a56073b	1354	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
AnnaBridge	143:86740a56073b	1355	* automatically generated. The NMI will be executed indefinitely, and
AnnaBridge	143:86740a56073b	1356	* since NMI has higher priority than any other IRQ (and main program)
AnnaBridge	143:86740a56073b	1357	* the application will be stacked in the NMI ISR unless the CSS interrupt
AnnaBridge	143:86740a56073b	1358	* pending bit is cleared.
AnnaBridge	143:86740a56073b	1359	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
AnnaBridge	143:86740a56073b	1360	* This parameter can be any combination of the following values:
AnnaBridge	143:86740a56073b	1361	* @arg RCC_IT_LSIRDY: LSI ready interrupt
AnnaBridge	143:86740a56073b	1362	* @arg RCC_IT_LSERDY: LSE ready interrupt
AnnaBridge	143:86740a56073b	1363	* @arg RCC_IT_HSIRDY: HSI ready interrupt
AnnaBridge	143:86740a56073b	1364	* @arg RCC_IT_HSERDY: HSE ready interrupt
AnnaBridge	143:86740a56073b	1365	* @arg RCC_IT_PLLRDY: PLL ready interrupt
AnnaBridge	143:86740a56073b	1366	* @arg RCC_IT_MSIRDY: MSI ready interrupt
AnnaBridge	143:86740a56073b	1367	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
AnnaBridge	143:86740a56073b	1368	* @arg RCC_IT_CSSLSE: LSE CSS interrupt
AnnaBridge	143:86740a56073b	1369
AnnaBridge	143:86740a56073b	1370	*/
AnnaBridge	143:86740a56073b	1371	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
AnnaBridge	143:86740a56073b	1372
AnnaBridge	143:86740a56073b	1373	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
AnnaBridge	143:86740a56073b	1374	* bits to clear the selected interrupt pending bits.
AnnaBridge	143:86740a56073b	1375	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
AnnaBridge	143:86740a56073b	1376	* This parameter can be any combination of the following values:
AnnaBridge	143:86740a56073b	1377	* @arg RCC_IT_LSIRDY: LSI ready interrupt
AnnaBridge	143:86740a56073b	1378	* @arg RCC_IT_LSERDY: LSE ready interrupt
AnnaBridge	143:86740a56073b	1379	* @arg RCC_IT_HSIRDY: HSI ready interrupt
AnnaBridge	143:86740a56073b	1380	* @arg RCC_IT_HSERDY: HSE ready interrupt
AnnaBridge	143:86740a56073b	1381	* @arg RCC_IT_PLLRDY: PLL ready interrupt
AnnaBridge	143:86740a56073b	1382	* @arg RCC_IT_MSIRDY: MSI ready interrupt
AnnaBridge	143:86740a56073b	1383	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
AnnaBridge	143:86740a56073b	1384	* @arg RCC_IT_CSSLSE: LSE CSS interrupt
AnnaBridge	143:86740a56073b	1385	* @arg RCC_IT_CSSHSE: Clock Security System interrupt
AnnaBridge	143:86740a56073b	1386	*/
AnnaBridge	143:86740a56073b	1387	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
AnnaBridge	143:86740a56073b	1388
AnnaBridge	143:86740a56073b	1389	/** @brief Check the RCC's interrupt has occurred or not.
AnnaBridge	143:86740a56073b	1390	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
AnnaBridge	143:86740a56073b	1391	* This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1392	* @arg RCC_IT_LSIRDY: LSI ready interrupt
AnnaBridge	143:86740a56073b	1393	* @arg RCC_IT_LSERDY: LSE ready interrupt
AnnaBridge	143:86740a56073b	1394	* @arg RCC_IT_HSIRDY: HSI ready interrupt
AnnaBridge	143:86740a56073b	1395	* @arg RCC_IT_HSERDY: HSE ready interrupt
AnnaBridge	143:86740a56073b	1396	* @arg RCC_IT_PLLRDY: PLL ready interrupt
AnnaBridge	143:86740a56073b	1397	* @arg RCC_IT_MSIRDY: MSI ready interrupt
AnnaBridge	143:86740a56073b	1398	* @arg RCC_IT_CSSLSE: LSE CSS interrupt
AnnaBridge	143:86740a56073b	1399	* @arg RCC_IT_CSSHSE: Clock Security System interrupt
AnnaBridge	143:86740a56073b	1400	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge	143:86740a56073b	1401	*/
AnnaBridge	143:86740a56073b	1402	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge	143:86740a56073b	1403
AnnaBridge	143:86740a56073b	1404
AnnaBridge	143:86740a56073b	1405	/** @brief Set RMVF bit to clear the reset flags.
AnnaBridge	143:86740a56073b	1406	* The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
AnnaBridge	143:86740a56073b	1407	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
AnnaBridge	143:86740a56073b	1408	*/
AnnaBridge	143:86740a56073b	1409	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
AnnaBridge	143:86740a56073b	1410
AnnaBridge	143:86740a56073b	1411	/** @brief Check RCC flag is set or not.
AnnaBridge	143:86740a56073b	1412	* @param __FLAG__: specifies the flag to check.
AnnaBridge	143:86740a56073b	1413	* This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1414	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
AnnaBridge	143:86740a56073b	1415	* @arg RCC_FLAG_HSIDIV: HSI clock divider flag
AnnaBridge	143:86740a56073b	1416	* @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
AnnaBridge	143:86740a56073b	1417	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
AnnaBridge	143:86740a56073b	1418	* @arg RCC_FLAG_PLLRDY: PLL clock ready
AnnaBridge	143:86740a56073b	1419	* @arg RCC_FLAG_LSECSS: LSE oscillator clock CSS detected
AnnaBridge	143:86740a56073b	1420	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
AnnaBridge	143:86740a56073b	1421	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
AnnaBridge	143:86740a56073b	1422	* @arg RCC_FLAG_FWRST: Firewall reset
AnnaBridge	143:86740a56073b	1423	* @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
AnnaBridge	143:86740a56073b	1424	* @arg RCC_FLAG_PINRST: Pin reset
AnnaBridge	143:86740a56073b	1425	* @arg RCC_FLAG_PORRST: POR/PDR reset
AnnaBridge	143:86740a56073b	1426	* @arg RCC_FLAG_SFTRST: Software reset
AnnaBridge	143:86740a56073b	1427	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
AnnaBridge	143:86740a56073b	1428	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
AnnaBridge	143:86740a56073b	1429	* @arg RCC_FLAG_LPWRRST: Low Power reset
AnnaBridge	143:86740a56073b	1430	* @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge	143:86740a56073b	1431	*/
AnnaBridge	143:86740a56073b	1432	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->CSR :((((__FLAG__) >> 5U) == 3U)? \
AnnaBridge	143:86740a56073b	1433	RCC->CRRCR :RCC->CIFR))) & ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U ) ? 1U : 0U )
AnnaBridge	143:86740a56073b	1434
AnnaBridge	143:86740a56073b	1435	/**
AnnaBridge	143:86740a56073b	1436	* @}
AnnaBridge	143:86740a56073b	1437	*/
AnnaBridge	143:86740a56073b	1438
AnnaBridge	143:86740a56073b	1439	/**
AnnaBridge	143:86740a56073b	1440	* @}
AnnaBridge	143:86740a56073b	1441	*/
AnnaBridge	143:86740a56073b	1442
AnnaBridge	143:86740a56073b	1443
AnnaBridge	143:86740a56073b	1444	/* Private constants ---------------------------------------------------------*/
AnnaBridge	143:86740a56073b	1445	/** @defgroup RCC_Private_Constants RCC Private Constants
AnnaBridge	143:86740a56073b	1446	* @{
AnnaBridge	143:86740a56073b	1447	*/
AnnaBridge	143:86740a56073b	1448	/* Defines used for Flags */
AnnaBridge	143:86740a56073b	1449	#define RCC_FLAG_MASK ((uint8_t)0x1FU)
AnnaBridge	143:86740a56073b	1450
AnnaBridge	143:86740a56073b	1451	/**
AnnaBridge	143:86740a56073b	1452	* @}
AnnaBridge	143:86740a56073b	1453	*/
AnnaBridge	143:86740a56073b	1454
AnnaBridge	143:86740a56073b	1455	/* Private macros ------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	1456	/** @addtogroup RCC_Private_Macros
AnnaBridge	143:86740a56073b	1457	* @{
AnnaBridge	143:86740a56073b	1458	*/
AnnaBridge	143:86740a56073b	1459
AnnaBridge	143:86740a56073b	1460	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
AnnaBridge	143:86740a56073b	1461	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x3FU)
AnnaBridge	143:86740a56073b	1462	#else
AnnaBridge	143:86740a56073b	1463	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x1FU)
AnnaBridge	143:86740a56073b	1464	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
AnnaBridge	143:86740a56073b	1465
AnnaBridge	143:86740a56073b	1466	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
AnnaBridge	143:86740a56073b	1467	((__HSE__) == RCC_HSE_BYPASS))
AnnaBridge	143:86740a56073b	1468	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
AnnaBridge	143:86740a56073b	1469	((__LSE__) == RCC_LSE_BYPASS))
AnnaBridge	143:86740a56073b	1470
AnnaBridge	143:86740a56073b	1471	#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) \|\| \
AnnaBridge	143:86740a56073b	1472	((__RANGE__) == RCC_MSIRANGE_1) \|\| \
AnnaBridge	143:86740a56073b	1473	((__RANGE__) == RCC_MSIRANGE_2) \|\| \
AnnaBridge	143:86740a56073b	1474	((__RANGE__) == RCC_MSIRANGE_3) \|\| \
AnnaBridge	143:86740a56073b	1475	((__RANGE__) == RCC_MSIRANGE_4) \|\| \
AnnaBridge	143:86740a56073b	1476	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
AnnaBridge	143:86740a56073b	1477	((__RANGE__) == RCC_MSIRANGE_6))
AnnaBridge	143:86740a56073b	1478
AnnaBridge	143:86740a56073b	1479	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
AnnaBridge	143:86740a56073b	1480	#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) \|\| ((__MSI__) == RCC_MSI_ON))
AnnaBridge	143:86740a56073b	1481	#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) \|\| ((__HSI48__) == RCC_HSI48_ON))
AnnaBridge	143:86740a56073b	1482
AnnaBridge	143:86740a56073b	1483	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\|((__PLL__) == RCC_PLL_OFF) \|\| ((__PLL__) == RCC_PLL_ON))
AnnaBridge	143:86740a56073b	1484
AnnaBridge	143:86740a56073b	1485	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
AnnaBridge	143:86740a56073b	1486	((__SOURCE__) == RCC_PLLSOURCE_HSE))
AnnaBridge	143:86740a56073b	1487
AnnaBridge	143:86740a56073b	1488	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLLMUL_3) \|\| ((__MUL__) == RCC_PLLMUL_4) \|\| \
AnnaBridge	143:86740a56073b	1489	((__MUL__) == RCC_PLLMUL_6) \|\| ((__MUL__) == RCC_PLLMUL_8) \|\| \
AnnaBridge	143:86740a56073b	1490	((__MUL__) == RCC_PLLMUL_12) \|\| ((__MUL__) == RCC_PLLMUL_16) \|\| \
AnnaBridge	143:86740a56073b	1491	((__MUL__) == RCC_PLLMUL_24) \|\| ((__MUL__) == RCC_PLLMUL_32) \|\| \
AnnaBridge	143:86740a56073b	1492	((__MUL__) == RCC_PLLMUL_48))
AnnaBridge	143:86740a56073b	1493
AnnaBridge	143:86740a56073b	1494	#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLLDIV_2) \|\| ((__DIV__) == RCC_PLLDIV_3) \|\| \
AnnaBridge	143:86740a56073b	1495	((__DIV__) == RCC_PLLDIV_4))
AnnaBridge	143:86740a56073b	1496
AnnaBridge	143:86740a56073b	1497	#define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U))
AnnaBridge	143:86740a56073b	1498
AnnaBridge	143:86740a56073b	1499	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
AnnaBridge	143:86740a56073b	1500	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
AnnaBridge	143:86740a56073b	1501	((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) \|\| \
AnnaBridge	143:86740a56073b	1502	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
AnnaBridge	143:86740a56073b	1503
AnnaBridge	143:86740a56073b	1504	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
AnnaBridge	143:86740a56073b	1505	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
AnnaBridge	143:86740a56073b	1506	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
AnnaBridge	143:86740a56073b	1507	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
AnnaBridge	143:86740a56073b	1508	((__HCLK__) == RCC_SYSCLK_DIV512))
AnnaBridge	143:86740a56073b	1509
AnnaBridge	143:86740a56073b	1510	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
AnnaBridge	143:86740a56073b	1511	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
AnnaBridge	143:86740a56073b	1512	((__PCLK__) == RCC_HCLK_DIV16))
AnnaBridge	143:86740a56073b	1513
AnnaBridge	143:86740a56073b	1514	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
AnnaBridge	143:86740a56073b	1515	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
AnnaBridge	143:86740a56073b	1516	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) \|\| \
AnnaBridge	143:86740a56073b	1517	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) \|\| \
AnnaBridge	143:86740a56073b	1518	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) \|\| \
AnnaBridge	143:86740a56073b	1519	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
AnnaBridge	143:86740a56073b	1520
AnnaBridge	143:86740a56073b	1521	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) \
AnnaBridge	143:86740a56073b	1522	&& !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge	143:86740a56073b	1523	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
AnnaBridge	143:86740a56073b	1524	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
AnnaBridge	143:86740a56073b	1525	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
AnnaBridge	143:86740a56073b	1526	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \|\| \
AnnaBridge	143:86740a56073b	1527	((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
AnnaBridge	143:86740a56073b	1528	#else
AnnaBridge	143:86740a56073b	1529	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
AnnaBridge	143:86740a56073b	1530	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
AnnaBridge	143:86740a56073b	1531	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
AnnaBridge	143:86740a56073b	1532	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
AnnaBridge	143:86740a56073b	1533	#endif
AnnaBridge	143:86740a56073b	1534
AnnaBridge	143:86740a56073b	1535	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) \|\| \
AnnaBridge	143:86740a56073b	1536	((__DIV__) == RCC_MCODIV_2) \|\| \
AnnaBridge	143:86740a56073b	1537	((__DIV__) == RCC_MCODIV_4) \|\| \
AnnaBridge	143:86740a56073b	1538	((__DIV__) == RCC_MCODIV_8) \|\| \
AnnaBridge	143:86740a56073b	1539	((__DIV__) == RCC_MCODIV_16))
AnnaBridge	143:86740a56073b	1540
AnnaBridge	143:86740a56073b	1541	#if defined(STM32L031xx) \|\| defined(STM32L041xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
AnnaBridge	143:86740a56073b	1542	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
AnnaBridge	143:86740a56073b	1543	#define IS_RCC_MCO(__MCOx__) (((__MCOx__) == RCC_MCO1) \|\| ((__MCOx__) == RCC_MCO2) \|\| ((__MCOx__) == RCC_MCO3))
AnnaBridge	143:86740a56073b	1544	#else
AnnaBridge	143:86740a56073b	1545	#define IS_RCC_MCO(__MCOx__) (((__MCOx__) == RCC_MCO1) \|\| ((__MCOx__) == RCC_MCO2))
AnnaBridge	143:86740a56073b	1546
AnnaBridge	143:86740a56073b	1547	#endif
AnnaBridge	143:86740a56073b	1548
AnnaBridge	143:86740a56073b	1549	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
AnnaBridge	143:86740a56073b	1550	#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFF)
AnnaBridge	143:86740a56073b	1551
AnnaBridge	143:86740a56073b	1552	/**
AnnaBridge	143:86740a56073b	1553	* @}
AnnaBridge	143:86740a56073b	1554	*/
AnnaBridge	143:86740a56073b	1555
AnnaBridge	143:86740a56073b	1556	/* Include RCC HAL Extension module */
AnnaBridge	143:86740a56073b	1557	#include "stm32l0xx_hal_rcc_ex.h"
AnnaBridge	143:86740a56073b	1558
AnnaBridge	143:86740a56073b	1559	/** @defgroup RCC_Exported_Functions RCC Exported Functions
AnnaBridge	143:86740a56073b	1560	* @{
AnnaBridge	143:86740a56073b	1561	*/
AnnaBridge	143:86740a56073b	1562
AnnaBridge	143:86740a56073b	1563	/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge	143:86740a56073b	1564	* @{
AnnaBridge	143:86740a56073b	1565	*/
AnnaBridge	143:86740a56073b	1566	void HAL_RCC_DeInit(void);
AnnaBridge	143:86740a56073b	1567	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge	143:86740a56073b	1568	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
AnnaBridge	143:86740a56073b	1569	/**
AnnaBridge	143:86740a56073b	1570	* @}
AnnaBridge	143:86740a56073b	1571	*/
AnnaBridge	143:86740a56073b	1572
AnnaBridge	143:86740a56073b	1573	/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
AnnaBridge	143:86740a56073b	1574	* @{
AnnaBridge	143:86740a56073b	1575	*/
AnnaBridge	143:86740a56073b	1576	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
AnnaBridge	143:86740a56073b	1577	#if !defined (STM32L011xx) && !defined (STM32L021xx)
AnnaBridge	143:86740a56073b	1578	void HAL_RCC_EnableCSS(void);
AnnaBridge	143:86740a56073b	1579	#endif
AnnaBridge	143:86740a56073b	1580	uint32_t HAL_RCC_GetSysClockFreq(void);
AnnaBridge	143:86740a56073b	1581	uint32_t HAL_RCC_GetHCLKFreq(void);
AnnaBridge	143:86740a56073b	1582	uint32_t HAL_RCC_GetPCLK1Freq(void);
AnnaBridge	143:86740a56073b	1583	uint32_t HAL_RCC_GetPCLK2Freq(void);
AnnaBridge	143:86740a56073b	1584	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge	143:86740a56073b	1585	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
AnnaBridge	143:86740a56073b	1586	/* CSS NMI IRQ handler */
AnnaBridge	143:86740a56073b	1587	void HAL_RCC_NMI_IRQHandler(void);
AnnaBridge	143:86740a56073b	1588
AnnaBridge	143:86740a56073b	1589	/* User Callbacks in non blocking mode (IT mode) */
AnnaBridge	143:86740a56073b	1590	void HAL_RCC_CSSCallback(void);
AnnaBridge	143:86740a56073b	1591	/**
AnnaBridge	143:86740a56073b	1592	* @}
AnnaBridge	143:86740a56073b	1593	*/
AnnaBridge	143:86740a56073b	1594
AnnaBridge	143:86740a56073b	1595	/**
AnnaBridge	143:86740a56073b	1596	* @}
AnnaBridge	143:86740a56073b	1597	*/
AnnaBridge	143:86740a56073b	1598
AnnaBridge	143:86740a56073b	1599
AnnaBridge	143:86740a56073b	1600	/**
AnnaBridge	143:86740a56073b	1601	* @}
AnnaBridge	143:86740a56073b	1602	*/
AnnaBridge	143:86740a56073b	1603
AnnaBridge	143:86740a56073b	1604	/**
AnnaBridge	143:86740a56073b	1605	* @}
AnnaBridge	143:86740a56073b	1606	*/
AnnaBridge	143:86740a56073b	1607
AnnaBridge	143:86740a56073b	1608	#ifdef __cplusplus
AnnaBridge	143:86740a56073b	1609	}
AnnaBridge	143:86740a56073b	1610	#endif
AnnaBridge	143:86740a56073b	1611
AnnaBridge	143:86740a56073b	1612	#endif /* __STM32l0xx_HAL_RCC_H */
AnnaBridge	143:86740a56073b	1613
AnnaBridge	143:86740a56073b	1614	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
AnnaBridge	143:86740a56073b	1615