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TARGET_NUCLEO_F334R8/TOOLCHAIN_IAR/stm32f334x8.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f334x8.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief CMSIS STM32F334x8 Devices Peripheral Access Layer Header File.
AnnaBridge 171:3a7713b1edbc 6 *
AnnaBridge 171:3a7713b1edbc 7 * This file contains:
AnnaBridge 171:3a7713b1edbc 8 * - Data structures and the address mapping for all peripherals
AnnaBridge 171:3a7713b1edbc 9 * - Peripheral's registers declarations and bits definition
AnnaBridge 171:3a7713b1edbc 10 * - Macros to access peripheral’s registers hardware
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 13 * @attention
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 16 *
AnnaBridge 171:3a7713b1edbc 17 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 18 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 19 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 20 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 22 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 23 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 25 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 26 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 38 *
AnnaBridge 171:3a7713b1edbc 39 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 40 */
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 /** @addtogroup CMSIS_Device
AnnaBridge 171:3a7713b1edbc 43 * @{
AnnaBridge 171:3a7713b1edbc 44 */
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /** @addtogroup stm32f334x8
AnnaBridge 171:3a7713b1edbc 47 * @{
AnnaBridge 171:3a7713b1edbc 48 */
AnnaBridge 171:3a7713b1edbc 49
AnnaBridge 171:3a7713b1edbc 50 #ifndef __STM32F334x8_H
AnnaBridge 171:3a7713b1edbc 51 #define __STM32F334x8_H
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 54 extern "C" {
AnnaBridge 171:3a7713b1edbc 55 #endif /* __cplusplus */
AnnaBridge 171:3a7713b1edbc 56
AnnaBridge 171:3a7713b1edbc 57 /** @addtogroup Configuration_section_for_CMSIS
AnnaBridge 171:3a7713b1edbc 58 * @{
AnnaBridge 171:3a7713b1edbc 59 */
AnnaBridge 171:3a7713b1edbc 60
AnnaBridge 171:3a7713b1edbc 61 /**
AnnaBridge 171:3a7713b1edbc 62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
AnnaBridge 171:3a7713b1edbc 63 */
AnnaBridge 171:3a7713b1edbc 64 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
AnnaBridge 171:3a7713b1edbc 65 #define __MPU_PRESENT 0U /*!< STM32F334x8 devices do not provide an MPU */
AnnaBridge 171:3a7713b1edbc 66 #define __NVIC_PRIO_BITS 4U /*!< STM32F334x8 devices use 4 Bits for the Priority Levels */
AnnaBridge 171:3a7713b1edbc 67 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 171:3a7713b1edbc 68 #ifndef __FPU_PRESENT
AnnaBridge 171:3a7713b1edbc 69 #define __FPU_PRESENT 1U /*!< STM32F334x8 devices provide an FPU */
AnnaBridge 171:3a7713b1edbc 70 #endif
AnnaBridge 171:3a7713b1edbc 71 /**
AnnaBridge 171:3a7713b1edbc 72 * @}
AnnaBridge 171:3a7713b1edbc 73 */
AnnaBridge 171:3a7713b1edbc 74
AnnaBridge 171:3a7713b1edbc 75 /** @addtogroup Peripheral_interrupt_number_definition
AnnaBridge 171:3a7713b1edbc 76 * @{
AnnaBridge 171:3a7713b1edbc 77 */
AnnaBridge 171:3a7713b1edbc 78
AnnaBridge 171:3a7713b1edbc 79 /**
AnnaBridge 171:3a7713b1edbc 80 * @brief STM32F334x8 devices Interrupt Number Definition, according to the selected device
AnnaBridge 171:3a7713b1edbc 81 * in @ref Library_configuration_section
AnnaBridge 171:3a7713b1edbc 82 */
AnnaBridge 171:3a7713b1edbc 83 typedef enum
AnnaBridge 171:3a7713b1edbc 84 {
AnnaBridge 171:3a7713b1edbc 85 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
AnnaBridge 171:3a7713b1edbc 86 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 87 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 88 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
AnnaBridge 171:3a7713b1edbc 89 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 90 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 91 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 92 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
AnnaBridge 171:3a7713b1edbc 93 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 94 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 95 /****** STM32 specific Interrupt Numbers **********************************************************************/
AnnaBridge 171:3a7713b1edbc 96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
AnnaBridge 171:3a7713b1edbc 97 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
AnnaBridge 171:3a7713b1edbc 98 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
AnnaBridge 171:3a7713b1edbc 99 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
AnnaBridge 171:3a7713b1edbc 100 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
AnnaBridge 171:3a7713b1edbc 101 RCC_IRQn = 5, /*!< RCC global Interrupt */
AnnaBridge 171:3a7713b1edbc 102 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
AnnaBridge 171:3a7713b1edbc 103 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
AnnaBridge 171:3a7713b1edbc 104 EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
AnnaBridge 171:3a7713b1edbc 105 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
AnnaBridge 171:3a7713b1edbc 106 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
AnnaBridge 171:3a7713b1edbc 107 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
AnnaBridge 171:3a7713b1edbc 108 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
AnnaBridge 171:3a7713b1edbc 109 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
AnnaBridge 171:3a7713b1edbc 110 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
AnnaBridge 171:3a7713b1edbc 111 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
AnnaBridge 171:3a7713b1edbc 112 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
AnnaBridge 171:3a7713b1edbc 113 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
AnnaBridge 171:3a7713b1edbc 114 ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
AnnaBridge 171:3a7713b1edbc 115 CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */
AnnaBridge 171:3a7713b1edbc 116 CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */
AnnaBridge 171:3a7713b1edbc 117 CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
AnnaBridge 171:3a7713b1edbc 118 CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
AnnaBridge 171:3a7713b1edbc 119 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
AnnaBridge 171:3a7713b1edbc 120 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
AnnaBridge 171:3a7713b1edbc 121 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
AnnaBridge 171:3a7713b1edbc 122 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
AnnaBridge 171:3a7713b1edbc 123 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
AnnaBridge 171:3a7713b1edbc 124 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
AnnaBridge 171:3a7713b1edbc 125 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
AnnaBridge 171:3a7713b1edbc 126 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
AnnaBridge 171:3a7713b1edbc 127 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
AnnaBridge 171:3a7713b1edbc 128 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 129 USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
AnnaBridge 171:3a7713b1edbc 130 USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
AnnaBridge 171:3a7713b1edbc 131 USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
AnnaBridge 171:3a7713b1edbc 132 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
AnnaBridge 171:3a7713b1edbc 133 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
AnnaBridge 171:3a7713b1edbc 134 TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/
AnnaBridge 171:3a7713b1edbc 135 TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */
AnnaBridge 171:3a7713b1edbc 136 COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */
AnnaBridge 171:3a7713b1edbc 137 COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
AnnaBridge 171:3a7713b1edbc 138 HRTIM1_Master_IRQn = 67, /*!< HRTIM Master Timer global Interrupts */
AnnaBridge 171:3a7713b1edbc 139 HRTIM1_TIMA_IRQn = 68, /*!< HRTIM Timer A global Interrupt */
AnnaBridge 171:3a7713b1edbc 140 HRTIM1_TIMB_IRQn = 69, /*!< HRTIM Timer B global Interrupt */
AnnaBridge 171:3a7713b1edbc 141 HRTIM1_TIMC_IRQn = 70, /*!< HRTIM Timer C global Interrupt */
AnnaBridge 171:3a7713b1edbc 142 HRTIM1_TIMD_IRQn = 71, /*!< HRTIM Timer D global Interrupt */
AnnaBridge 171:3a7713b1edbc 143 HRTIM1_TIME_IRQn = 72, /*!< HRTIM Timer E global Interrupt */
AnnaBridge 171:3a7713b1edbc 144 HRTIM1_FLT_IRQn = 73, /*!< HRTIM Fault global Interrupt */
AnnaBridge 171:3a7713b1edbc 145 FPU_IRQn = 81, /*!< Floating point Interrupt */
AnnaBridge 171:3a7713b1edbc 146 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 147
AnnaBridge 171:3a7713b1edbc 148 /**
AnnaBridge 171:3a7713b1edbc 149 * @}
AnnaBridge 171:3a7713b1edbc 150 */
AnnaBridge 171:3a7713b1edbc 151
AnnaBridge 171:3a7713b1edbc 152 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
AnnaBridge 171:3a7713b1edbc 153 #include "system_stm32f3xx.h" /* STM32F3xx System Header */
AnnaBridge 171:3a7713b1edbc 154 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 155
AnnaBridge 171:3a7713b1edbc 156 /** @addtogroup Peripheral_registers_structures
AnnaBridge 171:3a7713b1edbc 157 * @{
AnnaBridge 171:3a7713b1edbc 158 */
AnnaBridge 171:3a7713b1edbc 159
AnnaBridge 171:3a7713b1edbc 160 /**
AnnaBridge 171:3a7713b1edbc 161 * @brief Analog to Digital Converter
AnnaBridge 171:3a7713b1edbc 162 */
AnnaBridge 171:3a7713b1edbc 163
AnnaBridge 171:3a7713b1edbc 164 typedef struct
AnnaBridge 171:3a7713b1edbc 165 {
AnnaBridge 171:3a7713b1edbc 166 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 167 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 168 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 169 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 170 uint32_t RESERVED0; /*!< Reserved, 0x010 */
AnnaBridge 171:3a7713b1edbc 171 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 172 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 173 uint32_t RESERVED1; /*!< Reserved, 0x01C */
AnnaBridge 171:3a7713b1edbc 174 __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 175 __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 176 __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 177 uint32_t RESERVED2; /*!< Reserved, 0x02C */
AnnaBridge 171:3a7713b1edbc 178 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 179 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 180 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 181 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 182 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 183 uint32_t RESERVED3; /*!< Reserved, 0x044 */
AnnaBridge 171:3a7713b1edbc 184 uint32_t RESERVED4; /*!< Reserved, 0x048 */
AnnaBridge 171:3a7713b1edbc 185 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 186 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
AnnaBridge 171:3a7713b1edbc 187 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 188 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 189 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 190 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 191 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
AnnaBridge 171:3a7713b1edbc 192 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 193 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 194 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 195 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 196 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
AnnaBridge 171:3a7713b1edbc 197 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 198 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
AnnaBridge 171:3a7713b1edbc 199 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
AnnaBridge 171:3a7713b1edbc 200 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
AnnaBridge 171:3a7713b1edbc 201 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
AnnaBridge 171:3a7713b1edbc 202 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
AnnaBridge 171:3a7713b1edbc 203
AnnaBridge 171:3a7713b1edbc 204 } ADC_TypeDef;
AnnaBridge 171:3a7713b1edbc 205
AnnaBridge 171:3a7713b1edbc 206 typedef struct
AnnaBridge 171:3a7713b1edbc 207 {
AnnaBridge 171:3a7713b1edbc 208 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
AnnaBridge 171:3a7713b1edbc 209 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
AnnaBridge 171:3a7713b1edbc 210 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
AnnaBridge 171:3a7713b1edbc 211 __IO uint32_t CDR; /*!< ADC common regular data register for dual
AnnaBridge 171:3a7713b1edbc 212 AND triple modes, Address offset: ADC1/3 base address + 0x30C */
AnnaBridge 171:3a7713b1edbc 213 } ADC_Common_TypeDef;
AnnaBridge 171:3a7713b1edbc 214
AnnaBridge 171:3a7713b1edbc 215 /**
AnnaBridge 171:3a7713b1edbc 216 * @brief Controller Area Network TxMailBox
AnnaBridge 171:3a7713b1edbc 217 */
AnnaBridge 171:3a7713b1edbc 218 typedef struct
AnnaBridge 171:3a7713b1edbc 219 {
AnnaBridge 171:3a7713b1edbc 220 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
AnnaBridge 171:3a7713b1edbc 221 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
AnnaBridge 171:3a7713b1edbc 222 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
AnnaBridge 171:3a7713b1edbc 223 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
AnnaBridge 171:3a7713b1edbc 224 } CAN_TxMailBox_TypeDef;
AnnaBridge 171:3a7713b1edbc 225
AnnaBridge 171:3a7713b1edbc 226 /**
AnnaBridge 171:3a7713b1edbc 227 * @brief Controller Area Network FIFOMailBox
AnnaBridge 171:3a7713b1edbc 228 */
AnnaBridge 171:3a7713b1edbc 229 typedef struct
AnnaBridge 171:3a7713b1edbc 230 {
AnnaBridge 171:3a7713b1edbc 231 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
AnnaBridge 171:3a7713b1edbc 232 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
AnnaBridge 171:3a7713b1edbc 233 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
AnnaBridge 171:3a7713b1edbc 234 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
AnnaBridge 171:3a7713b1edbc 235 } CAN_FIFOMailBox_TypeDef;
AnnaBridge 171:3a7713b1edbc 236
AnnaBridge 171:3a7713b1edbc 237 /**
AnnaBridge 171:3a7713b1edbc 238 * @brief Controller Area Network FilterRegister
AnnaBridge 171:3a7713b1edbc 239 */
AnnaBridge 171:3a7713b1edbc 240 typedef struct
AnnaBridge 171:3a7713b1edbc 241 {
AnnaBridge 171:3a7713b1edbc 242 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
AnnaBridge 171:3a7713b1edbc 243 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
AnnaBridge 171:3a7713b1edbc 244 } CAN_FilterRegister_TypeDef;
AnnaBridge 171:3a7713b1edbc 245
AnnaBridge 171:3a7713b1edbc 246 /**
AnnaBridge 171:3a7713b1edbc 247 * @brief Controller Area Network
AnnaBridge 171:3a7713b1edbc 248 */
AnnaBridge 171:3a7713b1edbc 249 typedef struct
AnnaBridge 171:3a7713b1edbc 250 {
AnnaBridge 171:3a7713b1edbc 251 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 252 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 253 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 254 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 255 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 256 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 257 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 258 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 259 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
AnnaBridge 171:3a7713b1edbc 260 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
AnnaBridge 171:3a7713b1edbc 261 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
AnnaBridge 171:3a7713b1edbc 262 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
AnnaBridge 171:3a7713b1edbc 263 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
AnnaBridge 171:3a7713b1edbc 264 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
AnnaBridge 171:3a7713b1edbc 265 uint32_t RESERVED2; /*!< Reserved, 0x208 */
AnnaBridge 171:3a7713b1edbc 266 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
AnnaBridge 171:3a7713b1edbc 267 uint32_t RESERVED3; /*!< Reserved, 0x210 */
AnnaBridge 171:3a7713b1edbc 268 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
AnnaBridge 171:3a7713b1edbc 269 uint32_t RESERVED4; /*!< Reserved, 0x218 */
AnnaBridge 171:3a7713b1edbc 270 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
AnnaBridge 171:3a7713b1edbc 271 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
AnnaBridge 171:3a7713b1edbc 272 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
AnnaBridge 171:3a7713b1edbc 273 } CAN_TypeDef;
AnnaBridge 171:3a7713b1edbc 274
AnnaBridge 171:3a7713b1edbc 275 /**
AnnaBridge 171:3a7713b1edbc 276 * @brief Analog Comparators
AnnaBridge 171:3a7713b1edbc 277 */
AnnaBridge 171:3a7713b1edbc 278 typedef struct
AnnaBridge 171:3a7713b1edbc 279 {
AnnaBridge 171:3a7713b1edbc 280 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 281 } COMP_TypeDef;
AnnaBridge 171:3a7713b1edbc 282
AnnaBridge 171:3a7713b1edbc 283 typedef struct
AnnaBridge 171:3a7713b1edbc 284 {
AnnaBridge 171:3a7713b1edbc 285 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 286 } COMP_Common_TypeDef;
AnnaBridge 171:3a7713b1edbc 287
AnnaBridge 171:3a7713b1edbc 288 /**
AnnaBridge 171:3a7713b1edbc 289 * @brief CRC calculation unit
AnnaBridge 171:3a7713b1edbc 290 */
AnnaBridge 171:3a7713b1edbc 291
AnnaBridge 171:3a7713b1edbc 292 typedef struct
AnnaBridge 171:3a7713b1edbc 293 {
AnnaBridge 171:3a7713b1edbc 294 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 295 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 296 uint8_t RESERVED0; /*!< Reserved, 0x05 */
AnnaBridge 171:3a7713b1edbc 297 uint16_t RESERVED1; /*!< Reserved, 0x06 */
AnnaBridge 171:3a7713b1edbc 298 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 299 uint32_t RESERVED2; /*!< Reserved, 0x0C */
AnnaBridge 171:3a7713b1edbc 300 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 301 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 302 } CRC_TypeDef;
AnnaBridge 171:3a7713b1edbc 303
AnnaBridge 171:3a7713b1edbc 304 /**
AnnaBridge 171:3a7713b1edbc 305 * @brief Digital to Analog Converter
AnnaBridge 171:3a7713b1edbc 306 */
AnnaBridge 171:3a7713b1edbc 307
AnnaBridge 171:3a7713b1edbc 308 typedef struct
AnnaBridge 171:3a7713b1edbc 309 {
AnnaBridge 171:3a7713b1edbc 310 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 311 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 312 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 313 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 314 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 315 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 316 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 317 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 318 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 319 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 320 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 321 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 322 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 323 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 324 } DAC_TypeDef;
AnnaBridge 171:3a7713b1edbc 325
AnnaBridge 171:3a7713b1edbc 326 /**
AnnaBridge 171:3a7713b1edbc 327 * @brief Debug MCU
AnnaBridge 171:3a7713b1edbc 328 */
AnnaBridge 171:3a7713b1edbc 329
AnnaBridge 171:3a7713b1edbc 330 typedef struct
AnnaBridge 171:3a7713b1edbc 331 {
AnnaBridge 171:3a7713b1edbc 332 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 333 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 334 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 335 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 336 }DBGMCU_TypeDef;
AnnaBridge 171:3a7713b1edbc 337
AnnaBridge 171:3a7713b1edbc 338 /**
AnnaBridge 171:3a7713b1edbc 339 * @brief DMA Controller
AnnaBridge 171:3a7713b1edbc 340 */
AnnaBridge 171:3a7713b1edbc 341
AnnaBridge 171:3a7713b1edbc 342 typedef struct
AnnaBridge 171:3a7713b1edbc 343 {
AnnaBridge 171:3a7713b1edbc 344 __IO uint32_t CCR; /*!< DMA channel x configuration register */
AnnaBridge 171:3a7713b1edbc 345 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
AnnaBridge 171:3a7713b1edbc 346 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
AnnaBridge 171:3a7713b1edbc 347 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
AnnaBridge 171:3a7713b1edbc 348 } DMA_Channel_TypeDef;
AnnaBridge 171:3a7713b1edbc 349
AnnaBridge 171:3a7713b1edbc 350 typedef struct
AnnaBridge 171:3a7713b1edbc 351 {
AnnaBridge 171:3a7713b1edbc 352 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 353 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 354 } DMA_TypeDef;
AnnaBridge 171:3a7713b1edbc 355
AnnaBridge 171:3a7713b1edbc 356 /**
AnnaBridge 171:3a7713b1edbc 357 * @brief External Interrupt/Event Controller
AnnaBridge 171:3a7713b1edbc 358 */
AnnaBridge 171:3a7713b1edbc 359
AnnaBridge 171:3a7713b1edbc 360 typedef struct
AnnaBridge 171:3a7713b1edbc 361 {
AnnaBridge 171:3a7713b1edbc 362 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 363 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 364 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 365 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 366 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 367 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 368 uint32_t RESERVED1; /*!< Reserved, 0x18 */
AnnaBridge 171:3a7713b1edbc 369 uint32_t RESERVED2; /*!< Reserved, 0x1C */
AnnaBridge 171:3a7713b1edbc 370 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 371 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 372 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 373 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 374 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 375 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 376 }EXTI_TypeDef;
AnnaBridge 171:3a7713b1edbc 377
AnnaBridge 171:3a7713b1edbc 378 /**
AnnaBridge 171:3a7713b1edbc 379 * @brief FLASH Registers
AnnaBridge 171:3a7713b1edbc 380 */
AnnaBridge 171:3a7713b1edbc 381
AnnaBridge 171:3a7713b1edbc 382 typedef struct
AnnaBridge 171:3a7713b1edbc 383 {
AnnaBridge 171:3a7713b1edbc 384 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 385 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 386 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 387 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 388 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 389 __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 390 uint32_t RESERVED; /*!< Reserved, 0x18 */
AnnaBridge 171:3a7713b1edbc 391 __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 392 __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 393
AnnaBridge 171:3a7713b1edbc 394 } FLASH_TypeDef;
AnnaBridge 171:3a7713b1edbc 395
AnnaBridge 171:3a7713b1edbc 396 /**
AnnaBridge 171:3a7713b1edbc 397 * @brief Option Bytes Registers
AnnaBridge 171:3a7713b1edbc 398 */
AnnaBridge 171:3a7713b1edbc 399 typedef struct
AnnaBridge 171:3a7713b1edbc 400 {
AnnaBridge 171:3a7713b1edbc 401 __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 402 __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */
AnnaBridge 171:3a7713b1edbc 403 uint16_t RESERVED0; /*!< Reserved, 0x04 */
AnnaBridge 171:3a7713b1edbc 404 uint16_t RESERVED1; /*!< Reserved, 0x06 */
AnnaBridge 171:3a7713b1edbc 405 __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 406 __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 407 __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 408 __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */
AnnaBridge 171:3a7713b1edbc 409 } OB_TypeDef;
AnnaBridge 171:3a7713b1edbc 410
AnnaBridge 171:3a7713b1edbc 411 /**
AnnaBridge 171:3a7713b1edbc 412 * @brief General Purpose I/O
AnnaBridge 171:3a7713b1edbc 413 */
AnnaBridge 171:3a7713b1edbc 414
AnnaBridge 171:3a7713b1edbc 415 typedef struct
AnnaBridge 171:3a7713b1edbc 416 {
AnnaBridge 171:3a7713b1edbc 417 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 418 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 419 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 420 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 421 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 422 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 423 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
AnnaBridge 171:3a7713b1edbc 424 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 425 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
AnnaBridge 171:3a7713b1edbc 426 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 427 }GPIO_TypeDef;
AnnaBridge 171:3a7713b1edbc 428
AnnaBridge 171:3a7713b1edbc 429 /**
AnnaBridge 171:3a7713b1edbc 430 * @brief Operational Amplifier (OPAMP)
AnnaBridge 171:3a7713b1edbc 431 */
AnnaBridge 171:3a7713b1edbc 432
AnnaBridge 171:3a7713b1edbc 433 typedef struct
AnnaBridge 171:3a7713b1edbc 434 {
AnnaBridge 171:3a7713b1edbc 435 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 436 } OPAMP_TypeDef;
AnnaBridge 171:3a7713b1edbc 437
AnnaBridge 171:3a7713b1edbc 438 /**
AnnaBridge 171:3a7713b1edbc 439 * @brief High resolution Timer (HRTIM)
AnnaBridge 171:3a7713b1edbc 440 */
AnnaBridge 171:3a7713b1edbc 441 /* HRTIM master registers definition */
AnnaBridge 171:3a7713b1edbc 442 typedef struct
AnnaBridge 171:3a7713b1edbc 443 {
AnnaBridge 171:3a7713b1edbc 444 __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 445 __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 446 __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 447 __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 448 __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 449 __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 450 __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 451 __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 452 uint32_t RESERVED0; /*!< Reserved, 0x20 */
AnnaBridge 171:3a7713b1edbc 453 __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 454 __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 455 __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 456 uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */
AnnaBridge 171:3a7713b1edbc 457 }HRTIM_Master_TypeDef;
AnnaBridge 171:3a7713b1edbc 458
AnnaBridge 171:3a7713b1edbc 459 /* HRTIM Timer A to E registers definition */
AnnaBridge 171:3a7713b1edbc 460 typedef struct
AnnaBridge 171:3a7713b1edbc 461 {
AnnaBridge 171:3a7713b1edbc 462 __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 463 __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 464 __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 465 __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 466 __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 467 __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 468 __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 469 __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 470 __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 471 __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 472 __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 473 __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 474 __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 475 __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 476 __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 477 __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 478 __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 479 __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 480 __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 481 __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 482 __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 483 __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 484 __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 485 __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 486 __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 487 __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 488 __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 489 uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */
AnnaBridge 171:3a7713b1edbc 490 }HRTIM_Timerx_TypeDef;
AnnaBridge 171:3a7713b1edbc 491
AnnaBridge 171:3a7713b1edbc 492 /* HRTIM common register definition */
AnnaBridge 171:3a7713b1edbc 493 typedef struct
AnnaBridge 171:3a7713b1edbc 494 {
AnnaBridge 171:3a7713b1edbc 495 __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 496 __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 497 __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 498 __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 499 __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 500 __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 501 __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 502 __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 503 __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 504 __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 505 __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 506 __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 507 __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 508 __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 509 __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 510 __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 511 __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 512 __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 513 __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 514 __IO uint32_t DLLCR; /*!< HRTIM DLL control register, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 515 __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 516 __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 517 __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 518 __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 519 __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 520 __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 521 __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 522 __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 523 __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */
AnnaBridge 171:3a7713b1edbc 524 }HRTIM_Common_TypeDef;
AnnaBridge 171:3a7713b1edbc 525
AnnaBridge 171:3a7713b1edbc 526 /* HRTIM register definition */
AnnaBridge 171:3a7713b1edbc 527 typedef struct {
AnnaBridge 171:3a7713b1edbc 528 HRTIM_Master_TypeDef sMasterRegs;
AnnaBridge 171:3a7713b1edbc 529 HRTIM_Timerx_TypeDef sTimerxRegs[5];
AnnaBridge 171:3a7713b1edbc 530 uint32_t RESERVED0[32];
AnnaBridge 171:3a7713b1edbc 531 HRTIM_Common_TypeDef sCommonRegs;
AnnaBridge 171:3a7713b1edbc 532 }HRTIM_TypeDef;
AnnaBridge 171:3a7713b1edbc 533
AnnaBridge 171:3a7713b1edbc 534 /**
AnnaBridge 171:3a7713b1edbc 535 * @brief System configuration controller
AnnaBridge 171:3a7713b1edbc 536 */
AnnaBridge 171:3a7713b1edbc 537
AnnaBridge 171:3a7713b1edbc 538 typedef struct
AnnaBridge 171:3a7713b1edbc 539 {
AnnaBridge 171:3a7713b1edbc 540 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 541 __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 542 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
AnnaBridge 171:3a7713b1edbc 543 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 544 __IO uint32_t RESERVED0; /*!< Reserved, 0x1C */
AnnaBridge 171:3a7713b1edbc 545 __IO uint32_t RESERVED1; /*!< Reserved, 0x20 */
AnnaBridge 171:3a7713b1edbc 546 __IO uint32_t RESERVED2; /*!< Reserved, 0x24 */
AnnaBridge 171:3a7713b1edbc 547 __IO uint32_t RESERVED4; /*!< Reserved, 0x28 */
AnnaBridge 171:3a7713b1edbc 548 __IO uint32_t RESERVED5; /*!< Reserved, 0x2C */
AnnaBridge 171:3a7713b1edbc 549 __IO uint32_t RESERVED6; /*!< Reserved, 0x30 */
AnnaBridge 171:3a7713b1edbc 550 __IO uint32_t RESERVED7; /*!< Reserved, 0x34 */
AnnaBridge 171:3a7713b1edbc 551 __IO uint32_t RESERVED8; /*!< Reserved, 0x38 */
AnnaBridge 171:3a7713b1edbc 552 __IO uint32_t RESERVED9; /*!< Reserved, 0x3C */
AnnaBridge 171:3a7713b1edbc 553 __IO uint32_t RESERVED10; /*!< Reserved, 0x40 */
AnnaBridge 171:3a7713b1edbc 554 __IO uint32_t RESERVED11; /*!< Reserved, 0x44 */
AnnaBridge 171:3a7713b1edbc 555 __IO uint32_t RESERVED12; /*!< Reserved, 0x48 */
AnnaBridge 171:3a7713b1edbc 556 __IO uint32_t RESERVED13; /*!< Reserved, 0x4C */
AnnaBridge 171:3a7713b1edbc 557 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 558 } SYSCFG_TypeDef;
AnnaBridge 171:3a7713b1edbc 559
AnnaBridge 171:3a7713b1edbc 560 /**
AnnaBridge 171:3a7713b1edbc 561 * @brief Inter-integrated Circuit Interface
AnnaBridge 171:3a7713b1edbc 562 */
AnnaBridge 171:3a7713b1edbc 563
AnnaBridge 171:3a7713b1edbc 564 typedef struct
AnnaBridge 171:3a7713b1edbc 565 {
AnnaBridge 171:3a7713b1edbc 566 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 567 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 568 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 569 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 570 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 571 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 572 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 573 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 574 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 575 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 576 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 577 }I2C_TypeDef;
AnnaBridge 171:3a7713b1edbc 578
AnnaBridge 171:3a7713b1edbc 579 /**
AnnaBridge 171:3a7713b1edbc 580 * @brief Independent WATCHDOG
AnnaBridge 171:3a7713b1edbc 581 */
AnnaBridge 171:3a7713b1edbc 582
AnnaBridge 171:3a7713b1edbc 583 typedef struct
AnnaBridge 171:3a7713b1edbc 584 {
AnnaBridge 171:3a7713b1edbc 585 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 586 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 587 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 588 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 589 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 590 } IWDG_TypeDef;
AnnaBridge 171:3a7713b1edbc 591
AnnaBridge 171:3a7713b1edbc 592 /**
AnnaBridge 171:3a7713b1edbc 593 * @brief Power Control
AnnaBridge 171:3a7713b1edbc 594 */
AnnaBridge 171:3a7713b1edbc 595
AnnaBridge 171:3a7713b1edbc 596 typedef struct
AnnaBridge 171:3a7713b1edbc 597 {
AnnaBridge 171:3a7713b1edbc 598 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 599 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 600 } PWR_TypeDef;
AnnaBridge 171:3a7713b1edbc 601
AnnaBridge 171:3a7713b1edbc 602 /**
AnnaBridge 171:3a7713b1edbc 603 * @brief Reset and Clock Control
AnnaBridge 171:3a7713b1edbc 604 */
AnnaBridge 171:3a7713b1edbc 605 typedef struct
AnnaBridge 171:3a7713b1edbc 606 {
AnnaBridge 171:3a7713b1edbc 607 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 608 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 609 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 610 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 611 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 612 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 613 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 614 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 615 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 616 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 617 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 618 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 619 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 620 } RCC_TypeDef;
AnnaBridge 171:3a7713b1edbc 621
AnnaBridge 171:3a7713b1edbc 622 /**
AnnaBridge 171:3a7713b1edbc 623 * @brief Real-Time Clock
AnnaBridge 171:3a7713b1edbc 624 */
AnnaBridge 171:3a7713b1edbc 625
AnnaBridge 171:3a7713b1edbc 626 typedef struct
AnnaBridge 171:3a7713b1edbc 627 {
AnnaBridge 171:3a7713b1edbc 628 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 629 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 630 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 631 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 632 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 633 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 634 uint32_t RESERVED0; /*!< Reserved, 0x18 */
AnnaBridge 171:3a7713b1edbc 635 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 636 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 637 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 638 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 639 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 640 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 641 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 642 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 643 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 644 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 645 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 646 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 647 uint32_t RESERVED7; /*!< Reserved, 0x4C */
AnnaBridge 171:3a7713b1edbc 648 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 649 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 650 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 651 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 652 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 653 } RTC_TypeDef;
AnnaBridge 171:3a7713b1edbc 654
AnnaBridge 171:3a7713b1edbc 655
AnnaBridge 171:3a7713b1edbc 656 /**
AnnaBridge 171:3a7713b1edbc 657 * @brief Serial Peripheral Interface
AnnaBridge 171:3a7713b1edbc 658 */
AnnaBridge 171:3a7713b1edbc 659
AnnaBridge 171:3a7713b1edbc 660 typedef struct
AnnaBridge 171:3a7713b1edbc 661 {
AnnaBridge 171:3a7713b1edbc 662 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 663 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 664 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 665 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 666 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 667 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 668 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 669 } SPI_TypeDef;
AnnaBridge 171:3a7713b1edbc 670
AnnaBridge 171:3a7713b1edbc 671 /**
AnnaBridge 171:3a7713b1edbc 672 * @brief TIM
AnnaBridge 171:3a7713b1edbc 673 */
AnnaBridge 171:3a7713b1edbc 674 typedef struct
AnnaBridge 171:3a7713b1edbc 675 {
AnnaBridge 171:3a7713b1edbc 676 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 677 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 678 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 679 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 680 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 681 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 682 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 683 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 684 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 685 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 686 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 687 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 688 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 689 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 690 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 691 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 692 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 693 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 694 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 695 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 696 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 697 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 698 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 699 __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 700 } TIM_TypeDef;
AnnaBridge 171:3a7713b1edbc 701
AnnaBridge 171:3a7713b1edbc 702 /**
AnnaBridge 171:3a7713b1edbc 703 * @brief Touch Sensing Controller (TSC)
AnnaBridge 171:3a7713b1edbc 704 */
AnnaBridge 171:3a7713b1edbc 705 typedef struct
AnnaBridge 171:3a7713b1edbc 706 {
AnnaBridge 171:3a7713b1edbc 707 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 708 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 709 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 710 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 711 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 712 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 713 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 714 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 715 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 716 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 717 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 718 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 719 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 720 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
AnnaBridge 171:3a7713b1edbc 721 } TSC_TypeDef;
AnnaBridge 171:3a7713b1edbc 722
AnnaBridge 171:3a7713b1edbc 723 /**
AnnaBridge 171:3a7713b1edbc 724 * @brief Universal Synchronous Asynchronous Receiver Transmitter
AnnaBridge 171:3a7713b1edbc 725 */
AnnaBridge 171:3a7713b1edbc 726
AnnaBridge 171:3a7713b1edbc 727 typedef struct
AnnaBridge 171:3a7713b1edbc 728 {
AnnaBridge 171:3a7713b1edbc 729 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 730 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 731 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 732 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 733 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 734 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 735 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 736 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 737 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 738 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 739 uint16_t RESERVED1; /*!< Reserved, 0x26 */
AnnaBridge 171:3a7713b1edbc 740 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 741 uint16_t RESERVED2; /*!< Reserved, 0x2A */
AnnaBridge 171:3a7713b1edbc 742 } USART_TypeDef;
AnnaBridge 171:3a7713b1edbc 743
AnnaBridge 171:3a7713b1edbc 744 /**
AnnaBridge 171:3a7713b1edbc 745 * @brief Window WATCHDOG
AnnaBridge 171:3a7713b1edbc 746 */
AnnaBridge 171:3a7713b1edbc 747 typedef struct
AnnaBridge 171:3a7713b1edbc 748 {
AnnaBridge 171:3a7713b1edbc 749 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 750 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 751 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 752 } WWDG_TypeDef;
AnnaBridge 171:3a7713b1edbc 753
AnnaBridge 171:3a7713b1edbc 754 /** @addtogroup Peripheral_memory_map
AnnaBridge 171:3a7713b1edbc 755 * @{
AnnaBridge 171:3a7713b1edbc 756 */
AnnaBridge 171:3a7713b1edbc 757
AnnaBridge 171:3a7713b1edbc 758 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
AnnaBridge 171:3a7713b1edbc 759 #define CCMDATARAM_BASE ((uint32_t)0x10000000U) /*!< CCM(core coupled memory) data RAM base address in the alias region */
AnnaBridge 171:3a7713b1edbc 760 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
AnnaBridge 171:3a7713b1edbc 761 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
AnnaBridge 171:3a7713b1edbc 762 #define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM base address in the bit-band region */
AnnaBridge 171:3a7713b1edbc 763 #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
AnnaBridge 171:3a7713b1edbc 764
AnnaBridge 171:3a7713b1edbc 765
AnnaBridge 171:3a7713b1edbc 766 /*!< Peripheral memory map */
AnnaBridge 171:3a7713b1edbc 767 #define APB1PERIPH_BASE PERIPH_BASE
AnnaBridge 171:3a7713b1edbc 768 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
AnnaBridge 171:3a7713b1edbc 769 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
AnnaBridge 171:3a7713b1edbc 770 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U)
AnnaBridge 171:3a7713b1edbc 771 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000U)
AnnaBridge 171:3a7713b1edbc 772
AnnaBridge 171:3a7713b1edbc 773 /*!< APB1 peripherals */
AnnaBridge 171:3a7713b1edbc 774 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
AnnaBridge 171:3a7713b1edbc 775 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
AnnaBridge 171:3a7713b1edbc 776 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U)
AnnaBridge 171:3a7713b1edbc 777 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
AnnaBridge 171:3a7713b1edbc 778 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
AnnaBridge 171:3a7713b1edbc 779 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
AnnaBridge 171:3a7713b1edbc 780 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
AnnaBridge 171:3a7713b1edbc 781 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
AnnaBridge 171:3a7713b1edbc 782 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
AnnaBridge 171:3a7713b1edbc 783 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
AnnaBridge 171:3a7713b1edbc 784 #define CAN_BASE (APB1PERIPH_BASE + 0x00006400U)
AnnaBridge 171:3a7713b1edbc 785 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
AnnaBridge 171:3a7713b1edbc 786 #define DAC1_BASE (APB1PERIPH_BASE + 0x00007400U)
AnnaBridge 171:3a7713b1edbc 787 #define DAC2_BASE (APB1PERIPH_BASE + 0x00009800U)
AnnaBridge 171:3a7713b1edbc 788 #define DAC_BASE DAC1_BASE
AnnaBridge 171:3a7713b1edbc 789
AnnaBridge 171:3a7713b1edbc 790 /*!< APB2 peripherals */
AnnaBridge 171:3a7713b1edbc 791 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000U)
AnnaBridge 171:3a7713b1edbc 792 #define COMP2_BASE (APB2PERIPH_BASE + 0x00000020U)
AnnaBridge 171:3a7713b1edbc 793 #define COMP4_BASE (APB2PERIPH_BASE + 0x00000028U)
AnnaBridge 171:3a7713b1edbc 794 #define COMP6_BASE (APB2PERIPH_BASE + 0x00000030U)
AnnaBridge 171:3a7713b1edbc 795 #define COMP_BASE COMP2_BASE
AnnaBridge 171:3a7713b1edbc 796 #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003CU)
AnnaBridge 171:3a7713b1edbc 797 #define OPAMP_BASE OPAMP2_BASE
AnnaBridge 171:3a7713b1edbc 798 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
AnnaBridge 171:3a7713b1edbc 799 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U)
AnnaBridge 171:3a7713b1edbc 800 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
AnnaBridge 171:3a7713b1edbc 801 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
AnnaBridge 171:3a7713b1edbc 802 #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000U)
AnnaBridge 171:3a7713b1edbc 803 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400U)
AnnaBridge 171:3a7713b1edbc 804 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800U)
AnnaBridge 171:3a7713b1edbc 805 #define HRTIM1_BASE (APB2PERIPH_BASE + 0x00007400U)
AnnaBridge 171:3a7713b1edbc 806 #define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080U)
AnnaBridge 171:3a7713b1edbc 807 #define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100U)
AnnaBridge 171:3a7713b1edbc 808 #define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180U)
AnnaBridge 171:3a7713b1edbc 809 #define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200U)
AnnaBridge 171:3a7713b1edbc 810 #define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280U)
AnnaBridge 171:3a7713b1edbc 811 #define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380U)
AnnaBridge 171:3a7713b1edbc 812
AnnaBridge 171:3a7713b1edbc 813 /*!< AHB1 peripherals */
AnnaBridge 171:3a7713b1edbc 814 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000U)
AnnaBridge 171:3a7713b1edbc 815 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008U)
AnnaBridge 171:3a7713b1edbc 816 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001CU)
AnnaBridge 171:3a7713b1edbc 817 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030U)
AnnaBridge 171:3a7713b1edbc 818 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044U)
AnnaBridge 171:3a7713b1edbc 819 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058U)
AnnaBridge 171:3a7713b1edbc 820 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006CU)
AnnaBridge 171:3a7713b1edbc 821 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080U)
AnnaBridge 171:3a7713b1edbc 822 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000U)
AnnaBridge 171:3a7713b1edbc 823 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
AnnaBridge 171:3a7713b1edbc 824 #define OB_BASE ((uint32_t)0x1FFFF800U) /*!< Flash Option Bytes base address */
AnnaBridge 171:3a7713b1edbc 825 #define FLASHSIZE_BASE ((uint32_t)0x1FFFF7CCU) /*!< FLASH Size register base address */
AnnaBridge 171:3a7713b1edbc 826 #define UID_BASE ((uint32_t)0x1FFFF7ACU) /*!< Unique device ID register base address */
AnnaBridge 171:3a7713b1edbc 827 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000U)
AnnaBridge 171:3a7713b1edbc 828 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000U)
AnnaBridge 171:3a7713b1edbc 829
AnnaBridge 171:3a7713b1edbc 830 /*!< AHB2 peripherals */
AnnaBridge 171:3a7713b1edbc 831 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000U)
AnnaBridge 171:3a7713b1edbc 832 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400U)
AnnaBridge 171:3a7713b1edbc 833 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800U)
AnnaBridge 171:3a7713b1edbc 834 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00U)
AnnaBridge 171:3a7713b1edbc 835 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400U)
AnnaBridge 171:3a7713b1edbc 836
AnnaBridge 171:3a7713b1edbc 837 /*!< AHB3 peripherals */
AnnaBridge 171:3a7713b1edbc 838 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000U)
AnnaBridge 171:3a7713b1edbc 839 #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100U)
AnnaBridge 171:3a7713b1edbc 840 #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300U)
AnnaBridge 171:3a7713b1edbc 841
AnnaBridge 171:3a7713b1edbc 842 #define DBGMCU_BASE ((uint32_t)0xE0042000U) /*!< Debug MCU registers base address */
AnnaBridge 171:3a7713b1edbc 843 /**
AnnaBridge 171:3a7713b1edbc 844 * @}
AnnaBridge 171:3a7713b1edbc 845 */
AnnaBridge 171:3a7713b1edbc 846
AnnaBridge 171:3a7713b1edbc 847 /** @addtogroup Peripheral_declaration
AnnaBridge 171:3a7713b1edbc 848 * @{
AnnaBridge 171:3a7713b1edbc 849 */
AnnaBridge 171:3a7713b1edbc 850 #define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
AnnaBridge 171:3a7713b1edbc 851 #define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE)
AnnaBridge 171:3a7713b1edbc 852 #define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE)
AnnaBridge 171:3a7713b1edbc 853 #define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE)
AnnaBridge 171:3a7713b1edbc 854 #define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE)
AnnaBridge 171:3a7713b1edbc 855 #define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE)
AnnaBridge 171:3a7713b1edbc 856 #define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
AnnaBridge 171:3a7713b1edbc 857 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
AnnaBridge 171:3a7713b1edbc 858 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
AnnaBridge 171:3a7713b1edbc 859 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
AnnaBridge 171:3a7713b1edbc 860 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
AnnaBridge 171:3a7713b1edbc 861 #define RTC ((RTC_TypeDef *) RTC_BASE)
AnnaBridge 171:3a7713b1edbc 862 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
AnnaBridge 171:3a7713b1edbc 863 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
AnnaBridge 171:3a7713b1edbc 864 #define USART2 ((USART_TypeDef *) USART2_BASE)
AnnaBridge 171:3a7713b1edbc 865 #define USART3 ((USART_TypeDef *) USART3_BASE)
AnnaBridge 171:3a7713b1edbc 866 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
AnnaBridge 171:3a7713b1edbc 867 #define CAN1 ((CAN_TypeDef *) CAN_BASE)
AnnaBridge 171:3a7713b1edbc 868 #define PWR ((PWR_TypeDef *) PWR_BASE)
AnnaBridge 171:3a7713b1edbc 869 #define DAC ((DAC_TypeDef *) DAC_BASE)
AnnaBridge 171:3a7713b1edbc 870 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
AnnaBridge 171:3a7713b1edbc 871 #define DAC2 ((DAC_TypeDef *) DAC2_BASE)
AnnaBridge 171:3a7713b1edbc 872 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
AnnaBridge 171:3a7713b1edbc 873 #define COMP4 ((COMP_TypeDef *) COMP4_BASE)
AnnaBridge 171:3a7713b1edbc 874 #define COMP6 ((COMP_TypeDef *) COMP6_BASE)
AnnaBridge 171:3a7713b1edbc 875 /* Legacy define */
AnnaBridge 171:3a7713b1edbc 876 #define COMP ((COMP_TypeDef *) COMP_BASE)
AnnaBridge 171:3a7713b1edbc 877 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
AnnaBridge 171:3a7713b1edbc 878 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
AnnaBridge 171:3a7713b1edbc 879 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
AnnaBridge 171:3a7713b1edbc 880 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
AnnaBridge 171:3a7713b1edbc 881 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
AnnaBridge 171:3a7713b1edbc 882 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
AnnaBridge 171:3a7713b1edbc 883 #define USART1 ((USART_TypeDef *) USART1_BASE)
AnnaBridge 171:3a7713b1edbc 884 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
AnnaBridge 171:3a7713b1edbc 885 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
AnnaBridge 171:3a7713b1edbc 886 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
AnnaBridge 171:3a7713b1edbc 887 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
AnnaBridge 171:3a7713b1edbc 888 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
AnnaBridge 171:3a7713b1edbc 889 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
AnnaBridge 171:3a7713b1edbc 890 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
AnnaBridge 171:3a7713b1edbc 891 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
AnnaBridge 171:3a7713b1edbc 892 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
AnnaBridge 171:3a7713b1edbc 893 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
AnnaBridge 171:3a7713b1edbc 894 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
AnnaBridge 171:3a7713b1edbc 895 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
AnnaBridge 171:3a7713b1edbc 896 #define RCC ((RCC_TypeDef *) RCC_BASE)
AnnaBridge 171:3a7713b1edbc 897 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
AnnaBridge 171:3a7713b1edbc 898 #define OB ((OB_TypeDef *) OB_BASE)
AnnaBridge 171:3a7713b1edbc 899 #define CRC ((CRC_TypeDef *) CRC_BASE)
AnnaBridge 171:3a7713b1edbc 900 #define TSC ((TSC_TypeDef *) TSC_BASE)
AnnaBridge 171:3a7713b1edbc 901 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
AnnaBridge 171:3a7713b1edbc 902 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
AnnaBridge 171:3a7713b1edbc 903 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
AnnaBridge 171:3a7713b1edbc 904 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
AnnaBridge 171:3a7713b1edbc 905 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
AnnaBridge 171:3a7713b1edbc 906 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
AnnaBridge 171:3a7713b1edbc 907 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
AnnaBridge 171:3a7713b1edbc 908 #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
AnnaBridge 171:3a7713b1edbc 909 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 910 #define ADC1_2_COMMON ADC12_COMMON
AnnaBridge 171:3a7713b1edbc 911
AnnaBridge 171:3a7713b1edbc 912 /**
AnnaBridge 171:3a7713b1edbc 913 * @}
AnnaBridge 171:3a7713b1edbc 914 */
AnnaBridge 171:3a7713b1edbc 915
AnnaBridge 171:3a7713b1edbc 916 /** @addtogroup Exported_constants
AnnaBridge 171:3a7713b1edbc 917 * @{
AnnaBridge 171:3a7713b1edbc 918 */
AnnaBridge 171:3a7713b1edbc 919
AnnaBridge 171:3a7713b1edbc 920 /** @addtogroup Peripheral_Registers_Bits_Definition
AnnaBridge 171:3a7713b1edbc 921 * @{
AnnaBridge 171:3a7713b1edbc 922 */
AnnaBridge 171:3a7713b1edbc 923
AnnaBridge 171:3a7713b1edbc 924 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 925 /* Peripheral Registers_Bits_Definition */
AnnaBridge 171:3a7713b1edbc 926 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 927
AnnaBridge 171:3a7713b1edbc 928 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 929 /* */
AnnaBridge 171:3a7713b1edbc 930 /* Analog to Digital Converter SAR (ADC) */
AnnaBridge 171:3a7713b1edbc 931 /* */
AnnaBridge 171:3a7713b1edbc 932 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 933
AnnaBridge 171:3a7713b1edbc 934 #define ADC5_V1_1 /*!< ADC IP version */
AnnaBridge 171:3a7713b1edbc 935
AnnaBridge 171:3a7713b1edbc 936 /*
AnnaBridge 171:3a7713b1edbc 937 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
AnnaBridge 171:3a7713b1edbc 938 */
AnnaBridge 171:3a7713b1edbc 939 #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
AnnaBridge 171:3a7713b1edbc 940
AnnaBridge 171:3a7713b1edbc 941 /******************** Bit definition for ADC_ISR register ********************/
AnnaBridge 171:3a7713b1edbc 942 #define ADC_ISR_ADRDY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 943 #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 944 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
AnnaBridge 171:3a7713b1edbc 945 #define ADC_ISR_EOSMP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 946 #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 947 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
AnnaBridge 171:3a7713b1edbc 948 #define ADC_ISR_EOC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 949 #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 950 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
AnnaBridge 171:3a7713b1edbc 951 #define ADC_ISR_EOS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 952 #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 953 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
AnnaBridge 171:3a7713b1edbc 954 #define ADC_ISR_OVR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 955 #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 956 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
AnnaBridge 171:3a7713b1edbc 957 #define ADC_ISR_JEOC_Pos (5U)
AnnaBridge 171:3a7713b1edbc 958 #define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 959 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
AnnaBridge 171:3a7713b1edbc 960 #define ADC_ISR_JEOS_Pos (6U)
AnnaBridge 171:3a7713b1edbc 961 #define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 962 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
AnnaBridge 171:3a7713b1edbc 963 #define ADC_ISR_AWD1_Pos (7U)
AnnaBridge 171:3a7713b1edbc 964 #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 965 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
AnnaBridge 171:3a7713b1edbc 966 #define ADC_ISR_AWD2_Pos (8U)
AnnaBridge 171:3a7713b1edbc 967 #define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 968 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
AnnaBridge 171:3a7713b1edbc 969 #define ADC_ISR_AWD3_Pos (9U)
AnnaBridge 171:3a7713b1edbc 970 #define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 971 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
AnnaBridge 171:3a7713b1edbc 972 #define ADC_ISR_JQOVF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 973 #define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 974 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
AnnaBridge 171:3a7713b1edbc 975
AnnaBridge 171:3a7713b1edbc 976 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 977 #define ADC_ISR_ADRD (ADC_ISR_ADRDY)
AnnaBridge 171:3a7713b1edbc 978
AnnaBridge 171:3a7713b1edbc 979 /******************** Bit definition for ADC_IER register ********************/
AnnaBridge 171:3a7713b1edbc 980 #define ADC_IER_ADRDYIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 981 #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 982 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
AnnaBridge 171:3a7713b1edbc 983 #define ADC_IER_EOSMPIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 984 #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 985 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
AnnaBridge 171:3a7713b1edbc 986 #define ADC_IER_EOCIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 987 #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 988 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
AnnaBridge 171:3a7713b1edbc 989 #define ADC_IER_EOSIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 990 #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 991 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
AnnaBridge 171:3a7713b1edbc 992 #define ADC_IER_OVRIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 993 #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 994 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
AnnaBridge 171:3a7713b1edbc 995 #define ADC_IER_JEOCIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 996 #define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 997 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
AnnaBridge 171:3a7713b1edbc 998 #define ADC_IER_JEOSIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 999 #define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1000 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
AnnaBridge 171:3a7713b1edbc 1001 #define ADC_IER_AWD1IE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 1002 #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1003 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
AnnaBridge 171:3a7713b1edbc 1004 #define ADC_IER_AWD2IE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1005 #define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1006 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
AnnaBridge 171:3a7713b1edbc 1007 #define ADC_IER_AWD3IE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1008 #define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1009 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
AnnaBridge 171:3a7713b1edbc 1010 #define ADC_IER_JQOVFIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1011 #define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1012 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
AnnaBridge 171:3a7713b1edbc 1013
AnnaBridge 171:3a7713b1edbc 1014 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 1015 #define ADC_IER_RDY (ADC_IER_ADRDYIE)
AnnaBridge 171:3a7713b1edbc 1016 #define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
AnnaBridge 171:3a7713b1edbc 1017 #define ADC_IER_EOC (ADC_IER_EOCIE)
AnnaBridge 171:3a7713b1edbc 1018 #define ADC_IER_EOS (ADC_IER_EOSIE)
AnnaBridge 171:3a7713b1edbc 1019 #define ADC_IER_OVR (ADC_IER_OVRIE)
AnnaBridge 171:3a7713b1edbc 1020 #define ADC_IER_JEOC (ADC_IER_JEOCIE)
AnnaBridge 171:3a7713b1edbc 1021 #define ADC_IER_JEOS (ADC_IER_JEOSIE)
AnnaBridge 171:3a7713b1edbc 1022 #define ADC_IER_AWD1 (ADC_IER_AWD1IE)
AnnaBridge 171:3a7713b1edbc 1023 #define ADC_IER_AWD2 (ADC_IER_AWD2IE)
AnnaBridge 171:3a7713b1edbc 1024 #define ADC_IER_AWD3 (ADC_IER_AWD3IE)
AnnaBridge 171:3a7713b1edbc 1025 #define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
AnnaBridge 171:3a7713b1edbc 1026
AnnaBridge 171:3a7713b1edbc 1027 /******************** Bit definition for ADC_CR register ********************/
AnnaBridge 171:3a7713b1edbc 1028 #define ADC_CR_ADEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1029 #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1030 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
AnnaBridge 171:3a7713b1edbc 1031 #define ADC_CR_ADDIS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1032 #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1033 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
AnnaBridge 171:3a7713b1edbc 1034 #define ADC_CR_ADSTART_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1035 #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1036 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
AnnaBridge 171:3a7713b1edbc 1037 #define ADC_CR_JADSTART_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1038 #define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1039 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
AnnaBridge 171:3a7713b1edbc 1040 #define ADC_CR_ADSTP_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1041 #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1042 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
AnnaBridge 171:3a7713b1edbc 1043 #define ADC_CR_JADSTP_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1044 #define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1045 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
AnnaBridge 171:3a7713b1edbc 1046 #define ADC_CR_ADVREGEN_Pos (28U)
AnnaBridge 171:3a7713b1edbc 1047 #define ADC_CR_ADVREGEN_Msk (0x3U << ADC_CR_ADVREGEN_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 1048 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
AnnaBridge 171:3a7713b1edbc 1049 #define ADC_CR_ADVREGEN_0 (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1050 #define ADC_CR_ADVREGEN_1 (0x2U << ADC_CR_ADVREGEN_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1051 #define ADC_CR_ADCALDIF_Pos (30U)
AnnaBridge 171:3a7713b1edbc 1052 #define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 1053 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
AnnaBridge 171:3a7713b1edbc 1054 #define ADC_CR_ADCAL_Pos (31U)
AnnaBridge 171:3a7713b1edbc 1055 #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 1056 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
AnnaBridge 171:3a7713b1edbc 1057
AnnaBridge 171:3a7713b1edbc 1058 /******************** Bit definition for ADC_CFGR register ******************/
AnnaBridge 171:3a7713b1edbc 1059 #define ADC_CFGR_DMAEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1060 #define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1061 #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA enable */
AnnaBridge 171:3a7713b1edbc 1062 #define ADC_CFGR_DMACFG_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1063 #define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1064 #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA configuration */
AnnaBridge 171:3a7713b1edbc 1065
AnnaBridge 171:3a7713b1edbc 1066 #define ADC_CFGR_RES_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1067 #define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
AnnaBridge 171:3a7713b1edbc 1068 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
AnnaBridge 171:3a7713b1edbc 1069 #define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1070 #define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1071
AnnaBridge 171:3a7713b1edbc 1072 #define ADC_CFGR_ALIGN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1073 #define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1074 #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
AnnaBridge 171:3a7713b1edbc 1075
AnnaBridge 171:3a7713b1edbc 1076 #define ADC_CFGR_EXTSEL_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1077 #define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
AnnaBridge 171:3a7713b1edbc 1078 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
AnnaBridge 171:3a7713b1edbc 1079 #define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1080 #define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1081 #define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1082 #define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1083
AnnaBridge 171:3a7713b1edbc 1084 #define ADC_CFGR_EXTEN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1085 #define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 1086 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
AnnaBridge 171:3a7713b1edbc 1087 #define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1088 #define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1089
AnnaBridge 171:3a7713b1edbc 1090 #define ADC_CFGR_OVRMOD_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1091 #define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1092 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
AnnaBridge 171:3a7713b1edbc 1093 #define ADC_CFGR_CONT_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1094 #define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1095 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
AnnaBridge 171:3a7713b1edbc 1096 #define ADC_CFGR_AUTDLY_Pos (14U)
AnnaBridge 171:3a7713b1edbc 1097 #define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1098 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
AnnaBridge 171:3a7713b1edbc 1099
AnnaBridge 171:3a7713b1edbc 1100 #define ADC_CFGR_DISCEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1101 #define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1102 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
AnnaBridge 171:3a7713b1edbc 1103
AnnaBridge 171:3a7713b1edbc 1104 #define ADC_CFGR_DISCNUM_Pos (17U)
AnnaBridge 171:3a7713b1edbc 1105 #define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
AnnaBridge 171:3a7713b1edbc 1106 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
AnnaBridge 171:3a7713b1edbc 1107 #define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1108 #define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1109 #define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1110
AnnaBridge 171:3a7713b1edbc 1111 #define ADC_CFGR_JDISCEN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1112 #define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1113 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
AnnaBridge 171:3a7713b1edbc 1114 #define ADC_CFGR_JQM_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1115 #define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1116 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
AnnaBridge 171:3a7713b1edbc 1117 #define ADC_CFGR_AWD1SGL_Pos (22U)
AnnaBridge 171:3a7713b1edbc 1118 #define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1119 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
AnnaBridge 171:3a7713b1edbc 1120 #define ADC_CFGR_AWD1EN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 1121 #define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1122 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
AnnaBridge 171:3a7713b1edbc 1123 #define ADC_CFGR_JAWD1EN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1124 #define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1125 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
AnnaBridge 171:3a7713b1edbc 1126 #define ADC_CFGR_JAUTO_Pos (25U)
AnnaBridge 171:3a7713b1edbc 1127 #define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1128 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
AnnaBridge 171:3a7713b1edbc 1129
AnnaBridge 171:3a7713b1edbc 1130 #define ADC_CFGR_AWD1CH_Pos (26U)
AnnaBridge 171:3a7713b1edbc 1131 #define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
AnnaBridge 171:3a7713b1edbc 1132 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
AnnaBridge 171:3a7713b1edbc 1133 #define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1134 #define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1135 #define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1136 #define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1137 #define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 1138
AnnaBridge 171:3a7713b1edbc 1139 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 1140 #define ADC_CFGR_AUTOFF_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1141 #define ADC_CFGR_AUTOFF_Msk (0x1U << ADC_CFGR_AUTOFF_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1142 #define ADC_CFGR_AUTOFF ADC_CFGR_AUTOFF_Msk /*!< ADC low power auto power off */
AnnaBridge 171:3a7713b1edbc 1143
AnnaBridge 171:3a7713b1edbc 1144 /******************** Bit definition for ADC_SMPR1 register *****************/
AnnaBridge 171:3a7713b1edbc 1145 #define ADC_SMPR1_SMP0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1146 #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 1147 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1148 #define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1149 #define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1150 #define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1151
AnnaBridge 171:3a7713b1edbc 1152 #define ADC_SMPR1_SMP1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1153 #define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 1154 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1155 #define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1156 #define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1157 #define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1158
AnnaBridge 171:3a7713b1edbc 1159 #define ADC_SMPR1_SMP2_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1160 #define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
AnnaBridge 171:3a7713b1edbc 1161 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1162 #define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1163 #define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1164 #define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1165
AnnaBridge 171:3a7713b1edbc 1166 #define ADC_SMPR1_SMP3_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1167 #define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
AnnaBridge 171:3a7713b1edbc 1168 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1169 #define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1170 #define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1171 #define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1172
AnnaBridge 171:3a7713b1edbc 1173 #define ADC_SMPR1_SMP4_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1174 #define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 1175 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1176 #define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1177 #define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1178 #define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1179
AnnaBridge 171:3a7713b1edbc 1180 #define ADC_SMPR1_SMP5_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1181 #define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
AnnaBridge 171:3a7713b1edbc 1182 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1183 #define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1184 #define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1185 #define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1186
AnnaBridge 171:3a7713b1edbc 1187 #define ADC_SMPR1_SMP6_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1188 #define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
AnnaBridge 171:3a7713b1edbc 1189 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1190 #define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1191 #define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1192 #define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1193
AnnaBridge 171:3a7713b1edbc 1194 #define ADC_SMPR1_SMP7_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1195 #define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
AnnaBridge 171:3a7713b1edbc 1196 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1197 #define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1198 #define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1199 #define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1200
AnnaBridge 171:3a7713b1edbc 1201 #define ADC_SMPR1_SMP8_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1202 #define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
AnnaBridge 171:3a7713b1edbc 1203 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1204 #define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1205 #define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1206 #define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1207
AnnaBridge 171:3a7713b1edbc 1208 #define ADC_SMPR1_SMP9_Pos (27U)
AnnaBridge 171:3a7713b1edbc 1209 #define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
AnnaBridge 171:3a7713b1edbc 1210 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1211 #define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1212 #define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1213 #define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1214
AnnaBridge 171:3a7713b1edbc 1215 /******************** Bit definition for ADC_SMPR2 register *****************/
AnnaBridge 171:3a7713b1edbc 1216 #define ADC_SMPR2_SMP10_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1217 #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 1218 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1219 #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1220 #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1221 #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1222
AnnaBridge 171:3a7713b1edbc 1223 #define ADC_SMPR2_SMP11_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1224 #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 1225 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1226 #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1227 #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1228 #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1229
AnnaBridge 171:3a7713b1edbc 1230 #define ADC_SMPR2_SMP12_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1231 #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
AnnaBridge 171:3a7713b1edbc 1232 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1233 #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1234 #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1235 #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1236
AnnaBridge 171:3a7713b1edbc 1237 #define ADC_SMPR2_SMP13_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1238 #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
AnnaBridge 171:3a7713b1edbc 1239 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1240 #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1241 #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1242 #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1243
AnnaBridge 171:3a7713b1edbc 1244 #define ADC_SMPR2_SMP14_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1245 #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 1246 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1247 #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1248 #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1249 #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1250
AnnaBridge 171:3a7713b1edbc 1251 #define ADC_SMPR2_SMP15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1252 #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
AnnaBridge 171:3a7713b1edbc 1253 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1254 #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1255 #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1256 #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1257
AnnaBridge 171:3a7713b1edbc 1258 #define ADC_SMPR2_SMP16_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1259 #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
AnnaBridge 171:3a7713b1edbc 1260 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1261 #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1262 #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1263 #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1264
AnnaBridge 171:3a7713b1edbc 1265 #define ADC_SMPR2_SMP17_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1266 #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
AnnaBridge 171:3a7713b1edbc 1267 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1268 #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1269 #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1270 #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1271
AnnaBridge 171:3a7713b1edbc 1272 #define ADC_SMPR2_SMP18_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1273 #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
AnnaBridge 171:3a7713b1edbc 1274 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1275 #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1276 #define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1277 #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1278
AnnaBridge 171:3a7713b1edbc 1279 /******************** Bit definition for ADC_TR1 register *******************/
AnnaBridge 171:3a7713b1edbc 1280 #define ADC_TR1_LT1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1281 #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1282 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
AnnaBridge 171:3a7713b1edbc 1283 #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1284 #define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1285 #define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1286 #define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1287 #define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1288 #define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1289 #define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1290 #define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1291 #define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1292 #define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1293 #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1294 #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1295
AnnaBridge 171:3a7713b1edbc 1296 #define ADC_TR1_HT1_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1297 #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
AnnaBridge 171:3a7713b1edbc 1298 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
AnnaBridge 171:3a7713b1edbc 1299 #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1300 #define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1301 #define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1302 #define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1303 #define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1304 #define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1305 #define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1306 #define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1307 #define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1308 #define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1309 #define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1310 #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1311
AnnaBridge 171:3a7713b1edbc 1312 /******************** Bit definition for ADC_TR2 register *******************/
AnnaBridge 171:3a7713b1edbc 1313 #define ADC_TR2_LT2_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1314 #define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 1315 #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
AnnaBridge 171:3a7713b1edbc 1316 #define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1317 #define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1318 #define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1319 #define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1320 #define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1321 #define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1322 #define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1323 #define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1324
AnnaBridge 171:3a7713b1edbc 1325 #define ADC_TR2_HT2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1326 #define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 1327 #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
AnnaBridge 171:3a7713b1edbc 1328 #define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1329 #define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1330 #define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1331 #define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1332 #define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1333 #define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1334 #define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1335 #define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1336
AnnaBridge 171:3a7713b1edbc 1337 /******************** Bit definition for ADC_TR3 register *******************/
AnnaBridge 171:3a7713b1edbc 1338 #define ADC_TR3_LT3_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1339 #define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 1340 #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
AnnaBridge 171:3a7713b1edbc 1341 #define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1342 #define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1343 #define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1344 #define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1345 #define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1346 #define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1347 #define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1348 #define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1349
AnnaBridge 171:3a7713b1edbc 1350 #define ADC_TR3_HT3_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1351 #define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 1352 #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
AnnaBridge 171:3a7713b1edbc 1353 #define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1354 #define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1355 #define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1356 #define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1357 #define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1358 #define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1359 #define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1360 #define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1361
AnnaBridge 171:3a7713b1edbc 1362 /******************** Bit definition for ADC_SQR1 register ******************/
AnnaBridge 171:3a7713b1edbc 1363 #define ADC_SQR1_L_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1364 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 1365 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
AnnaBridge 171:3a7713b1edbc 1366 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1367 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1368 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1369 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1370
AnnaBridge 171:3a7713b1edbc 1371 #define ADC_SQR1_SQ1_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1372 #define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
AnnaBridge 171:3a7713b1edbc 1373 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
AnnaBridge 171:3a7713b1edbc 1374 #define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1375 #define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1376 #define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1377 #define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1378 #define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1379
AnnaBridge 171:3a7713b1edbc 1380 #define ADC_SQR1_SQ2_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1381 #define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
AnnaBridge 171:3a7713b1edbc 1382 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
AnnaBridge 171:3a7713b1edbc 1383 #define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1384 #define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1385 #define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1386 #define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1387 #define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1388
AnnaBridge 171:3a7713b1edbc 1389 #define ADC_SQR1_SQ3_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1390 #define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
AnnaBridge 171:3a7713b1edbc 1391 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
AnnaBridge 171:3a7713b1edbc 1392 #define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1393 #define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1394 #define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1395 #define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1396 #define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1397
AnnaBridge 171:3a7713b1edbc 1398 #define ADC_SQR1_SQ4_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1399 #define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
AnnaBridge 171:3a7713b1edbc 1400 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
AnnaBridge 171:3a7713b1edbc 1401 #define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1402 #define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1403 #define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1404 #define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1405 #define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1406
AnnaBridge 171:3a7713b1edbc 1407 /******************** Bit definition for ADC_SQR2 register ******************/
AnnaBridge 171:3a7713b1edbc 1408 #define ADC_SQR2_SQ5_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1409 #define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1410 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
AnnaBridge 171:3a7713b1edbc 1411 #define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1412 #define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1413 #define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1414 #define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1415 #define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1416
AnnaBridge 171:3a7713b1edbc 1417 #define ADC_SQR2_SQ6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1418 #define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
AnnaBridge 171:3a7713b1edbc 1419 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
AnnaBridge 171:3a7713b1edbc 1420 #define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1421 #define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1422 #define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1423 #define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1424 #define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1425
AnnaBridge 171:3a7713b1edbc 1426 #define ADC_SQR2_SQ7_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1427 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
AnnaBridge 171:3a7713b1edbc 1428 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
AnnaBridge 171:3a7713b1edbc 1429 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1430 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1431 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1432 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1433 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1434
AnnaBridge 171:3a7713b1edbc 1435 #define ADC_SQR2_SQ8_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1436 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
AnnaBridge 171:3a7713b1edbc 1437 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
AnnaBridge 171:3a7713b1edbc 1438 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1439 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1440 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1441 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1442 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1443
AnnaBridge 171:3a7713b1edbc 1444 #define ADC_SQR2_SQ9_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1445 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
AnnaBridge 171:3a7713b1edbc 1446 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
AnnaBridge 171:3a7713b1edbc 1447 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1448 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1449 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1450 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1451 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1452
AnnaBridge 171:3a7713b1edbc 1453 /******************** Bit definition for ADC_SQR3 register ******************/
AnnaBridge 171:3a7713b1edbc 1454 #define ADC_SQR3_SQ10_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1455 #define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1456 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
AnnaBridge 171:3a7713b1edbc 1457 #define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1458 #define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1459 #define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1460 #define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1461 #define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1462
AnnaBridge 171:3a7713b1edbc 1463 #define ADC_SQR3_SQ11_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1464 #define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
AnnaBridge 171:3a7713b1edbc 1465 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
AnnaBridge 171:3a7713b1edbc 1466 #define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1467 #define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1468 #define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1469 #define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1470 #define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1471
AnnaBridge 171:3a7713b1edbc 1472 #define ADC_SQR3_SQ12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1473 #define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
AnnaBridge 171:3a7713b1edbc 1474 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
AnnaBridge 171:3a7713b1edbc 1475 #define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1476 #define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1477 #define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1478 #define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1479 #define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1480
AnnaBridge 171:3a7713b1edbc 1481 #define ADC_SQR3_SQ13_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1482 #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
AnnaBridge 171:3a7713b1edbc 1483 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
AnnaBridge 171:3a7713b1edbc 1484 #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1485 #define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1486 #define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1487 #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1488 #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1489
AnnaBridge 171:3a7713b1edbc 1490 #define ADC_SQR3_SQ14_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1491 #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
AnnaBridge 171:3a7713b1edbc 1492 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
AnnaBridge 171:3a7713b1edbc 1493 #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1494 #define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1495 #define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1496 #define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1497 #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1498
AnnaBridge 171:3a7713b1edbc 1499 /******************** Bit definition for ADC_SQR4 register ******************/
AnnaBridge 171:3a7713b1edbc 1500 #define ADC_SQR4_SQ15_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1501 #define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1502 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
AnnaBridge 171:3a7713b1edbc 1503 #define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1504 #define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1505 #define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1506 #define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1507 #define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1508
AnnaBridge 171:3a7713b1edbc 1509 #define ADC_SQR4_SQ16_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1510 #define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
AnnaBridge 171:3a7713b1edbc 1511 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
AnnaBridge 171:3a7713b1edbc 1512 #define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1513 #define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1514 #define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1515 #define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1516 #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1517
AnnaBridge 171:3a7713b1edbc 1518 /******************** Bit definition for ADC_DR register ********************/
AnnaBridge 171:3a7713b1edbc 1519 #define ADC_DR_RDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1520 #define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1521 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
AnnaBridge 171:3a7713b1edbc 1522 #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1523 #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1524 #define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1525 #define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1526 #define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1527 #define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1528 #define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1529 #define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1530 #define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1531 #define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1532 #define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1533 #define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1534 #define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1535 #define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1536 #define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1537 #define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1538
AnnaBridge 171:3a7713b1edbc 1539 /******************** Bit definition for ADC_JSQR register ******************/
AnnaBridge 171:3a7713b1edbc 1540 #define ADC_JSQR_JL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1541 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 1542 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
AnnaBridge 171:3a7713b1edbc 1543 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1544 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1545
AnnaBridge 171:3a7713b1edbc 1546 #define ADC_JSQR_JEXTSEL_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1547 #define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
AnnaBridge 171:3a7713b1edbc 1548 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
AnnaBridge 171:3a7713b1edbc 1549 #define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1550 #define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1551 #define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1552 #define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1553
AnnaBridge 171:3a7713b1edbc 1554 #define ADC_JSQR_JEXTEN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1555 #define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 1556 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
AnnaBridge 171:3a7713b1edbc 1557 #define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1558 #define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1559
AnnaBridge 171:3a7713b1edbc 1560 #define ADC_JSQR_JSQ1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1561 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
AnnaBridge 171:3a7713b1edbc 1562 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
AnnaBridge 171:3a7713b1edbc 1563 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1564 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1565 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1566 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1567 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1568
AnnaBridge 171:3a7713b1edbc 1569 #define ADC_JSQR_JSQ2_Pos (14U)
AnnaBridge 171:3a7713b1edbc 1570 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
AnnaBridge 171:3a7713b1edbc 1571 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
AnnaBridge 171:3a7713b1edbc 1572 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1573 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1574 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1575 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1576 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1577
AnnaBridge 171:3a7713b1edbc 1578 #define ADC_JSQR_JSQ3_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1579 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
AnnaBridge 171:3a7713b1edbc 1580 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
AnnaBridge 171:3a7713b1edbc 1581 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1582 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1583 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1584 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1585 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1586
AnnaBridge 171:3a7713b1edbc 1587 #define ADC_JSQR_JSQ4_Pos (26U)
AnnaBridge 171:3a7713b1edbc 1588 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
AnnaBridge 171:3a7713b1edbc 1589 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
AnnaBridge 171:3a7713b1edbc 1590 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1591 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1592 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1593 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1594 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 1595
AnnaBridge 171:3a7713b1edbc 1596
AnnaBridge 171:3a7713b1edbc 1597 /******************** Bit definition for ADC_OFR1 register ******************/
AnnaBridge 171:3a7713b1edbc 1598 #define ADC_OFR1_OFFSET1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1599 #define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1600 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
AnnaBridge 171:3a7713b1edbc 1601 #define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1602 #define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1603 #define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1604 #define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1605 #define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1606 #define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1607 #define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1608 #define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1609 #define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1610 #define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1611 #define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1612 #define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1613
AnnaBridge 171:3a7713b1edbc 1614 #define ADC_OFR1_OFFSET1_CH_Pos (26U)
AnnaBridge 171:3a7713b1edbc 1615 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
AnnaBridge 171:3a7713b1edbc 1616 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
AnnaBridge 171:3a7713b1edbc 1617 #define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1618 #define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1619 #define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1620 #define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1621 #define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 1622
AnnaBridge 171:3a7713b1edbc 1623 #define ADC_OFR1_OFFSET1_EN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 1624 #define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 1625 #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
AnnaBridge 171:3a7713b1edbc 1626
AnnaBridge 171:3a7713b1edbc 1627 /******************** Bit definition for ADC_OFR2 register ******************/
AnnaBridge 171:3a7713b1edbc 1628 #define ADC_OFR2_OFFSET2_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1629 #define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1630 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
AnnaBridge 171:3a7713b1edbc 1631 #define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1632 #define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1633 #define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1634 #define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1635 #define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1636 #define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1637 #define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1638 #define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1639 #define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1640 #define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1641 #define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1642 #define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1643
AnnaBridge 171:3a7713b1edbc 1644 #define ADC_OFR2_OFFSET2_CH_Pos (26U)
AnnaBridge 171:3a7713b1edbc 1645 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
AnnaBridge 171:3a7713b1edbc 1646 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
AnnaBridge 171:3a7713b1edbc 1647 #define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1648 #define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1649 #define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1650 #define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1651 #define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 1652
AnnaBridge 171:3a7713b1edbc 1653 #define ADC_OFR2_OFFSET2_EN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 1654 #define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 1655 #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
AnnaBridge 171:3a7713b1edbc 1656
AnnaBridge 171:3a7713b1edbc 1657 /******************** Bit definition for ADC_OFR3 register ******************/
AnnaBridge 171:3a7713b1edbc 1658 #define ADC_OFR3_OFFSET3_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1659 #define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1660 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
AnnaBridge 171:3a7713b1edbc 1661 #define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1662 #define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1663 #define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1664 #define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1665 #define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1666 #define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1667 #define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1668 #define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1669 #define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1670 #define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1671 #define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1672 #define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1673
AnnaBridge 171:3a7713b1edbc 1674 #define ADC_OFR3_OFFSET3_CH_Pos (26U)
AnnaBridge 171:3a7713b1edbc 1675 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
AnnaBridge 171:3a7713b1edbc 1676 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
AnnaBridge 171:3a7713b1edbc 1677 #define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1678 #define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1679 #define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1680 #define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1681 #define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 1682
AnnaBridge 171:3a7713b1edbc 1683 #define ADC_OFR3_OFFSET3_EN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 1684 #define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 1685 #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
AnnaBridge 171:3a7713b1edbc 1686
AnnaBridge 171:3a7713b1edbc 1687 /******************** Bit definition for ADC_OFR4 register ******************/
AnnaBridge 171:3a7713b1edbc 1688 #define ADC_OFR4_OFFSET4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1689 #define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1690 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
AnnaBridge 171:3a7713b1edbc 1691 #define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1692 #define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1693 #define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1694 #define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1695 #define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1696 #define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1697 #define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1698 #define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1699 #define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1700 #define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1701 #define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1702 #define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1703
AnnaBridge 171:3a7713b1edbc 1704 #define ADC_OFR4_OFFSET4_CH_Pos (26U)
AnnaBridge 171:3a7713b1edbc 1705 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
AnnaBridge 171:3a7713b1edbc 1706 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
AnnaBridge 171:3a7713b1edbc 1707 #define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1708 #define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1709 #define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1710 #define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1711 #define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 1712
AnnaBridge 171:3a7713b1edbc 1713 #define ADC_OFR4_OFFSET4_EN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 1714 #define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 1715 #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
AnnaBridge 171:3a7713b1edbc 1716
AnnaBridge 171:3a7713b1edbc 1717 /******************** Bit definition for ADC_JDR1 register ******************/
AnnaBridge 171:3a7713b1edbc 1718 #define ADC_JDR1_JDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1719 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1720 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
AnnaBridge 171:3a7713b1edbc 1721 #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1722 #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1723 #define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1724 #define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1725 #define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1726 #define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1727 #define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1728 #define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1729 #define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1730 #define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1731 #define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1732 #define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1733 #define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1734 #define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1735 #define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1736 #define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1737
AnnaBridge 171:3a7713b1edbc 1738 /******************** Bit definition for ADC_JDR2 register ******************/
AnnaBridge 171:3a7713b1edbc 1739 #define ADC_JDR2_JDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1740 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1741 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
AnnaBridge 171:3a7713b1edbc 1742 #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1743 #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1744 #define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1745 #define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1746 #define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1747 #define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1748 #define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1749 #define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1750 #define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1751 #define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1752 #define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1753 #define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1754 #define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1755 #define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1756 #define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1757 #define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1758
AnnaBridge 171:3a7713b1edbc 1759 /******************** Bit definition for ADC_JDR3 register ******************/
AnnaBridge 171:3a7713b1edbc 1760 #define ADC_JDR3_JDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1761 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1762 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
AnnaBridge 171:3a7713b1edbc 1763 #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1764 #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1765 #define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1766 #define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1767 #define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1768 #define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1769 #define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1770 #define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1771 #define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1772 #define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1773 #define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1774 #define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1775 #define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1776 #define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1777 #define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1778 #define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1779
AnnaBridge 171:3a7713b1edbc 1780 /******************** Bit definition for ADC_JDR4 register ******************/
AnnaBridge 171:3a7713b1edbc 1781 #define ADC_JDR4_JDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1782 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1783 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
AnnaBridge 171:3a7713b1edbc 1784 #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1785 #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1786 #define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1787 #define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1788 #define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1789 #define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1790 #define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1791 #define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1792 #define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1793 #define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1794 #define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1795 #define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1796 #define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1797 #define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1798 #define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1799 #define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1800
AnnaBridge 171:3a7713b1edbc 1801 /******************** Bit definition for ADC_AWD2CR register ****************/
AnnaBridge 171:3a7713b1edbc 1802 #define ADC_AWD2CR_AWD2CH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1803 #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
AnnaBridge 171:3a7713b1edbc 1804 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
AnnaBridge 171:3a7713b1edbc 1805 #define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1806 #define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1807 #define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1808 #define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1809 #define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1810 #define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1811 #define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1812 #define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1813 #define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1814 #define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1815 #define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1816 #define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1817 #define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1818 #define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1819 #define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1820 #define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1821 #define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1822 #define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1823 #define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1824
AnnaBridge 171:3a7713b1edbc 1825 /******************** Bit definition for ADC_AWD3CR register ****************/
AnnaBridge 171:3a7713b1edbc 1826 #define ADC_AWD3CR_AWD3CH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1827 #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
AnnaBridge 171:3a7713b1edbc 1828 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
AnnaBridge 171:3a7713b1edbc 1829 #define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1830 #define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1831 #define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1832 #define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1833 #define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1834 #define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1835 #define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1836 #define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1837 #define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1838 #define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1839 #define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1840 #define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1841 #define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1842 #define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1843 #define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1844 #define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1845 #define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1846 #define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1847 #define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1848
AnnaBridge 171:3a7713b1edbc 1849 /******************** Bit definition for ADC_DIFSEL register ****************/
AnnaBridge 171:3a7713b1edbc 1850 #define ADC_DIFSEL_DIFSEL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1851 #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
AnnaBridge 171:3a7713b1edbc 1852 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
AnnaBridge 171:3a7713b1edbc 1853 #define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1854 #define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1855 #define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1856 #define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1857 #define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1858 #define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1859 #define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1860 #define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1861 #define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1862 #define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1863 #define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1864 #define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1865 #define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1866 #define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1867 #define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1868 #define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1869 #define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1870 #define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1871 #define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1872
AnnaBridge 171:3a7713b1edbc 1873 /******************** Bit definition for ADC_CALFACT register ***************/
AnnaBridge 171:3a7713b1edbc 1874 #define ADC_CALFACT_CALFACT_S_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1875 #define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
AnnaBridge 171:3a7713b1edbc 1876 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
AnnaBridge 171:3a7713b1edbc 1877 #define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1878 #define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1879 #define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1880 #define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1881 #define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1882 #define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1883 #define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1884
AnnaBridge 171:3a7713b1edbc 1885 #define ADC_CALFACT_CALFACT_D_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1886 #define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
AnnaBridge 171:3a7713b1edbc 1887 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
AnnaBridge 171:3a7713b1edbc 1888 #define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1889 #define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1890 #define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1891 #define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1892 #define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1893 #define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1894 #define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1895
AnnaBridge 171:3a7713b1edbc 1896 /************************* ADC Common registers *****************************/
AnnaBridge 171:3a7713b1edbc 1897 /*************** Bit definition for ADC12_COMMON_CSR register ***************/
AnnaBridge 171:3a7713b1edbc 1898 #define ADC12_CSR_ADRDY_MST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1899 #define ADC12_CSR_ADRDY_MST_Msk (0x1U << ADC12_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1900 #define ADC12_CSR_ADRDY_MST ADC12_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
AnnaBridge 171:3a7713b1edbc 1901 #define ADC12_CSR_ADRDY_EOSMP_MST_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1902 #define ADC12_CSR_ADRDY_EOSMP_MST_Msk (0x1U << ADC12_CSR_ADRDY_EOSMP_MST_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1903 #define ADC12_CSR_ADRDY_EOSMP_MST ADC12_CSR_ADRDY_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
AnnaBridge 171:3a7713b1edbc 1904 #define ADC12_CSR_ADRDY_EOC_MST_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1905 #define ADC12_CSR_ADRDY_EOC_MST_Msk (0x1U << ADC12_CSR_ADRDY_EOC_MST_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1906 #define ADC12_CSR_ADRDY_EOC_MST ADC12_CSR_ADRDY_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
AnnaBridge 171:3a7713b1edbc 1907 #define ADC12_CSR_ADRDY_EOS_MST_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1908 #define ADC12_CSR_ADRDY_EOS_MST_Msk (0x1U << ADC12_CSR_ADRDY_EOS_MST_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1909 #define ADC12_CSR_ADRDY_EOS_MST ADC12_CSR_ADRDY_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
AnnaBridge 171:3a7713b1edbc 1910 #define ADC12_CSR_ADRDY_OVR_MST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1911 #define ADC12_CSR_ADRDY_OVR_MST_Msk (0x1U << ADC12_CSR_ADRDY_OVR_MST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1912 #define ADC12_CSR_ADRDY_OVR_MST ADC12_CSR_ADRDY_OVR_MST_Msk /*!< Overrun flag of the master ADC */
AnnaBridge 171:3a7713b1edbc 1913 #define ADC12_CSR_ADRDY_JEOC_MST_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1914 #define ADC12_CSR_ADRDY_JEOC_MST_Msk (0x1U << ADC12_CSR_ADRDY_JEOC_MST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1915 #define ADC12_CSR_ADRDY_JEOC_MST ADC12_CSR_ADRDY_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
AnnaBridge 171:3a7713b1edbc 1916 #define ADC12_CSR_ADRDY_JEOS_MST_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1917 #define ADC12_CSR_ADRDY_JEOS_MST_Msk (0x1U << ADC12_CSR_ADRDY_JEOS_MST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1918 #define ADC12_CSR_ADRDY_JEOS_MST ADC12_CSR_ADRDY_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
AnnaBridge 171:3a7713b1edbc 1919 #define ADC12_CSR_AWD1_MST_Pos (7U)
AnnaBridge 171:3a7713b1edbc 1920 #define ADC12_CSR_AWD1_MST_Msk (0x1U << ADC12_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1921 #define ADC12_CSR_AWD1_MST ADC12_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
AnnaBridge 171:3a7713b1edbc 1922 #define ADC12_CSR_AWD2_MST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1923 #define ADC12_CSR_AWD2_MST_Msk (0x1U << ADC12_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1924 #define ADC12_CSR_AWD2_MST ADC12_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
AnnaBridge 171:3a7713b1edbc 1925 #define ADC12_CSR_AWD3_MST_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1926 #define ADC12_CSR_AWD3_MST_Msk (0x1U << ADC12_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1927 #define ADC12_CSR_AWD3_MST ADC12_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
AnnaBridge 171:3a7713b1edbc 1928 #define ADC12_CSR_JQOVF_MST_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1929 #define ADC12_CSR_JQOVF_MST_Msk (0x1U << ADC12_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1930 #define ADC12_CSR_JQOVF_MST ADC12_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
AnnaBridge 171:3a7713b1edbc 1931 #define ADC12_CSR_ADRDY_SLV_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1932 #define ADC12_CSR_ADRDY_SLV_Msk (0x1U << ADC12_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1933 #define ADC12_CSR_ADRDY_SLV ADC12_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
AnnaBridge 171:3a7713b1edbc 1934 #define ADC12_CSR_ADRDY_EOSMP_SLV_Pos (17U)
AnnaBridge 171:3a7713b1edbc 1935 #define ADC12_CSR_ADRDY_EOSMP_SLV_Msk (0x1U << ADC12_CSR_ADRDY_EOSMP_SLV_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1936 #define ADC12_CSR_ADRDY_EOSMP_SLV ADC12_CSR_ADRDY_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
AnnaBridge 171:3a7713b1edbc 1937 #define ADC12_CSR_ADRDY_EOC_SLV_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1938 #define ADC12_CSR_ADRDY_EOC_SLV_Msk (0x1U << ADC12_CSR_ADRDY_EOC_SLV_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1939 #define ADC12_CSR_ADRDY_EOC_SLV ADC12_CSR_ADRDY_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
AnnaBridge 171:3a7713b1edbc 1940 #define ADC12_CSR_ADRDY_EOS_SLV_Pos (19U)
AnnaBridge 171:3a7713b1edbc 1941 #define ADC12_CSR_ADRDY_EOS_SLV_Msk (0x1U << ADC12_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1942 #define ADC12_CSR_ADRDY_EOS_SLV ADC12_CSR_ADRDY_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
AnnaBridge 171:3a7713b1edbc 1943 #define ADC12_CSR_ADRDY_OVR_SLV_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1944 #define ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1U << ADC12_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1945 #define ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
AnnaBridge 171:3a7713b1edbc 1946 #define ADC12_CSR_ADRDY_JEOC_SLV_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1947 #define ADC12_CSR_ADRDY_JEOC_SLV_Msk (0x1U << ADC12_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1948 #define ADC12_CSR_ADRDY_JEOC_SLV ADC12_CSR_ADRDY_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
AnnaBridge 171:3a7713b1edbc 1949 #define ADC12_CSR_ADRDY_JEOS_SLV_Pos (22U)
AnnaBridge 171:3a7713b1edbc 1950 #define ADC12_CSR_ADRDY_JEOS_SLV_Msk (0x1U << ADC12_CSR_ADRDY_JEOS_SLV_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1951 #define ADC12_CSR_ADRDY_JEOS_SLV ADC12_CSR_ADRDY_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
AnnaBridge 171:3a7713b1edbc 1952 #define ADC12_CSR_AWD1_SLV_Pos (23U)
AnnaBridge 171:3a7713b1edbc 1953 #define ADC12_CSR_AWD1_SLV_Msk (0x1U << ADC12_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1954 #define ADC12_CSR_AWD1_SLV ADC12_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
AnnaBridge 171:3a7713b1edbc 1955 #define ADC12_CSR_AWD2_SLV_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1956 #define ADC12_CSR_AWD2_SLV_Msk (0x1U << ADC12_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1957 #define ADC12_CSR_AWD2_SLV ADC12_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
AnnaBridge 171:3a7713b1edbc 1958 #define ADC12_CSR_AWD3_SLV_Pos (25U)
AnnaBridge 171:3a7713b1edbc 1959 #define ADC12_CSR_AWD3_SLV_Msk (0x1U << ADC12_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1960 #define ADC12_CSR_AWD3_SLV ADC12_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
AnnaBridge 171:3a7713b1edbc 1961 #define ADC12_CSR_JQOVF_SLV_Pos (26U)
AnnaBridge 171:3a7713b1edbc 1962 #define ADC12_CSR_JQOVF_SLV_Msk (0x1U << ADC12_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1963 #define ADC12_CSR_JQOVF_SLV ADC12_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
AnnaBridge 171:3a7713b1edbc 1964
AnnaBridge 171:3a7713b1edbc 1965 /*************** Bit definition for ADC34_COMMON_CSR register ***************/
AnnaBridge 171:3a7713b1edbc 1966 #define ADC34_CSR_ADRDY_MST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1967 #define ADC34_CSR_ADRDY_MST_Msk (0x1U << ADC34_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1968 #define ADC34_CSR_ADRDY_MST ADC34_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
AnnaBridge 171:3a7713b1edbc 1969 #define ADC34_CSR_ADRDY_EOSMP_MST_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1970 #define ADC34_CSR_ADRDY_EOSMP_MST_Msk (0x1U << ADC34_CSR_ADRDY_EOSMP_MST_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1971 #define ADC34_CSR_ADRDY_EOSMP_MST ADC34_CSR_ADRDY_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
AnnaBridge 171:3a7713b1edbc 1972 #define ADC34_CSR_ADRDY_EOC_MST_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1973 #define ADC34_CSR_ADRDY_EOC_MST_Msk (0x1U << ADC34_CSR_ADRDY_EOC_MST_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1974 #define ADC34_CSR_ADRDY_EOC_MST ADC34_CSR_ADRDY_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
AnnaBridge 171:3a7713b1edbc 1975 #define ADC34_CSR_ADRDY_EOS_MST_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1976 #define ADC34_CSR_ADRDY_EOS_MST_Msk (0x1U << ADC34_CSR_ADRDY_EOS_MST_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1977 #define ADC34_CSR_ADRDY_EOS_MST ADC34_CSR_ADRDY_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
AnnaBridge 171:3a7713b1edbc 1978 #define ADC34_CSR_ADRDY_OVR_MST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1979 #define ADC34_CSR_ADRDY_OVR_MST_Msk (0x1U << ADC34_CSR_ADRDY_OVR_MST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1980 #define ADC34_CSR_ADRDY_OVR_MST ADC34_CSR_ADRDY_OVR_MST_Msk /*!< Overrun flag of the master ADC */
AnnaBridge 171:3a7713b1edbc 1981 #define ADC34_CSR_ADRDY_JEOC_MST_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1982 #define ADC34_CSR_ADRDY_JEOC_MST_Msk (0x1U << ADC34_CSR_ADRDY_JEOC_MST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1983 #define ADC34_CSR_ADRDY_JEOC_MST ADC34_CSR_ADRDY_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
AnnaBridge 171:3a7713b1edbc 1984 #define ADC34_CSR_ADRDY_JEOS_MST_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1985 #define ADC34_CSR_ADRDY_JEOS_MST_Msk (0x1U << ADC34_CSR_ADRDY_JEOS_MST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1986 #define ADC34_CSR_ADRDY_JEOS_MST ADC34_CSR_ADRDY_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
AnnaBridge 171:3a7713b1edbc 1987 #define ADC34_CSR_AWD1_MST_Pos (7U)
AnnaBridge 171:3a7713b1edbc 1988 #define ADC34_CSR_AWD1_MST_Msk (0x1U << ADC34_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1989 #define ADC34_CSR_AWD1_MST ADC34_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
AnnaBridge 171:3a7713b1edbc 1990 #define ADC34_CSR_AWD2_MST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1991 #define ADC34_CSR_AWD2_MST_Msk (0x1U << ADC34_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1992 #define ADC34_CSR_AWD2_MST ADC34_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
AnnaBridge 171:3a7713b1edbc 1993 #define ADC34_CSR_AWD3_MST_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1994 #define ADC34_CSR_AWD3_MST_Msk (0x1U << ADC34_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1995 #define ADC34_CSR_AWD3_MST ADC34_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
AnnaBridge 171:3a7713b1edbc 1996 #define ADC34_CSR_JQOVF_MST_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1997 #define ADC34_CSR_JQOVF_MST_Msk (0x1U << ADC34_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1998 #define ADC34_CSR_JQOVF_MST ADC34_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
AnnaBridge 171:3a7713b1edbc 1999 #define ADC34_CSR_ADRDY_SLV_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2000 #define ADC34_CSR_ADRDY_SLV_Msk (0x1U << ADC34_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2001 #define ADC34_CSR_ADRDY_SLV ADC34_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
AnnaBridge 171:3a7713b1edbc 2002 #define ADC34_CSR_ADRDY_EOSMP_SLV_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2003 #define ADC34_CSR_ADRDY_EOSMP_SLV_Msk (0x1U << ADC34_CSR_ADRDY_EOSMP_SLV_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2004 #define ADC34_CSR_ADRDY_EOSMP_SLV ADC34_CSR_ADRDY_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
AnnaBridge 171:3a7713b1edbc 2005 #define ADC34_CSR_ADRDY_EOC_SLV_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2006 #define ADC34_CSR_ADRDY_EOC_SLV_Msk (0x1U << ADC34_CSR_ADRDY_EOC_SLV_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2007 #define ADC34_CSR_ADRDY_EOC_SLV ADC34_CSR_ADRDY_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
AnnaBridge 171:3a7713b1edbc 2008 #define ADC34_CSR_ADRDY_EOS_SLV_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2009 #define ADC34_CSR_ADRDY_EOS_SLV_Msk (0x1U << ADC34_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2010 #define ADC34_CSR_ADRDY_EOS_SLV ADC34_CSR_ADRDY_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
AnnaBridge 171:3a7713b1edbc 2011 #define ADC12_CSR_ADRDY_OVR_SLV_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2012 #define ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1U << ADC12_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2013 #define ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
AnnaBridge 171:3a7713b1edbc 2014 #define ADC34_CSR_ADRDY_JEOC_SLV_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2015 #define ADC34_CSR_ADRDY_JEOC_SLV_Msk (0x1U << ADC34_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2016 #define ADC34_CSR_ADRDY_JEOC_SLV ADC34_CSR_ADRDY_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
AnnaBridge 171:3a7713b1edbc 2017 #define ADC34_CSR_ADRDY_JEOS_SLV_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2018 #define ADC34_CSR_ADRDY_JEOS_SLV_Msk (0x1U << ADC34_CSR_ADRDY_JEOS_SLV_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2019 #define ADC34_CSR_ADRDY_JEOS_SLV ADC34_CSR_ADRDY_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
AnnaBridge 171:3a7713b1edbc 2020 #define ADC34_CSR_AWD1_SLV_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2021 #define ADC34_CSR_AWD1_SLV_Msk (0x1U << ADC34_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2022 #define ADC34_CSR_AWD1_SLV ADC34_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
AnnaBridge 171:3a7713b1edbc 2023 #define ADC34_CSR_AWD2_SLV_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2024 #define ADC34_CSR_AWD2_SLV_Msk (0x1U << ADC34_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2025 #define ADC34_CSR_AWD2_SLV ADC34_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
AnnaBridge 171:3a7713b1edbc 2026 #define ADC34_CSR_AWD3_SLV_Pos (25U)
AnnaBridge 171:3a7713b1edbc 2027 #define ADC34_CSR_AWD3_SLV_Msk (0x1U << ADC34_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 2028 #define ADC34_CSR_AWD3_SLV ADC34_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
AnnaBridge 171:3a7713b1edbc 2029 #define ADC34_CSR_JQOVF_SLV_Pos (26U)
AnnaBridge 171:3a7713b1edbc 2030 #define ADC34_CSR_JQOVF_SLV_Msk (0x1U << ADC34_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 2031 #define ADC34_CSR_JQOVF_SLV ADC34_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
AnnaBridge 171:3a7713b1edbc 2032
AnnaBridge 171:3a7713b1edbc 2033 /*************** Bit definition for ADC12_COMMON_CCR register ***************/
AnnaBridge 171:3a7713b1edbc 2034 #define ADC12_CCR_MULTI_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2035 #define ADC12_CCR_MULTI_Msk (0x1FU << ADC12_CCR_MULTI_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 2036 #define ADC12_CCR_MULTI ADC12_CCR_MULTI_Msk /*!< Multi ADC mode selection */
AnnaBridge 171:3a7713b1edbc 2037 #define ADC12_CCR_MULTI_0 (0x01U << ADC12_CCR_MULTI_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2038 #define ADC12_CCR_MULTI_1 (0x02U << ADC12_CCR_MULTI_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2039 #define ADC12_CCR_MULTI_2 (0x04U << ADC12_CCR_MULTI_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2040 #define ADC12_CCR_MULTI_3 (0x08U << ADC12_CCR_MULTI_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2041 #define ADC12_CCR_MULTI_4 (0x10U << ADC12_CCR_MULTI_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2042 #define ADC12_CCR_DELAY_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2043 #define ADC12_CCR_DELAY_Msk (0xFU << ADC12_CCR_DELAY_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 2044 #define ADC12_CCR_DELAY ADC12_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
AnnaBridge 171:3a7713b1edbc 2045 #define ADC12_CCR_DELAY_0 (0x1U << ADC12_CCR_DELAY_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2046 #define ADC12_CCR_DELAY_1 (0x2U << ADC12_CCR_DELAY_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2047 #define ADC12_CCR_DELAY_2 (0x4U << ADC12_CCR_DELAY_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2048 #define ADC12_CCR_DELAY_3 (0x8U << ADC12_CCR_DELAY_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2049 #define ADC12_CCR_DMACFG_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2050 #define ADC12_CCR_DMACFG_Msk (0x1U << ADC12_CCR_DMACFG_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2051 #define ADC12_CCR_DMACFG ADC12_CCR_DMACFG_Msk /*!< DMA configuration for multi-ADC mode */
AnnaBridge 171:3a7713b1edbc 2052 #define ADC12_CCR_MDMA_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2053 #define ADC12_CCR_MDMA_Msk (0x3U << ADC12_CCR_MDMA_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 2054 #define ADC12_CCR_MDMA ADC12_CCR_MDMA_Msk /*!< DMA mode for multi-ADC mode */
AnnaBridge 171:3a7713b1edbc 2055 #define ADC12_CCR_MDMA_0 (0x1U << ADC12_CCR_MDMA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2056 #define ADC12_CCR_MDMA_1 (0x2U << ADC12_CCR_MDMA_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2057 #define ADC12_CCR_CKMODE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2058 #define ADC12_CCR_CKMODE_Msk (0x3U << ADC12_CCR_CKMODE_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 2059 #define ADC12_CCR_CKMODE ADC12_CCR_CKMODE_Msk /*!< ADC clock mode */
AnnaBridge 171:3a7713b1edbc 2060 #define ADC12_CCR_CKMODE_0 (0x1U << ADC12_CCR_CKMODE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2061 #define ADC12_CCR_CKMODE_1 (0x2U << ADC12_CCR_CKMODE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2062 #define ADC12_CCR_VREFEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2063 #define ADC12_CCR_VREFEN_Msk (0x1U << ADC12_CCR_VREFEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2064 #define ADC12_CCR_VREFEN ADC12_CCR_VREFEN_Msk /*!< VREFINT enable */
AnnaBridge 171:3a7713b1edbc 2065 #define ADC12_CCR_TSEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2066 #define ADC12_CCR_TSEN_Msk (0x1U << ADC12_CCR_TSEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2067 #define ADC12_CCR_TSEN ADC12_CCR_TSEN_Msk /*!< Temperature sensor enable */
AnnaBridge 171:3a7713b1edbc 2068 #define ADC12_CCR_VBATEN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2069 #define ADC12_CCR_VBATEN_Msk (0x1U << ADC12_CCR_VBATEN_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2070 #define ADC12_CCR_VBATEN ADC12_CCR_VBATEN_Msk /*!< VBAT enable */
AnnaBridge 171:3a7713b1edbc 2071
AnnaBridge 171:3a7713b1edbc 2072 /*************** Bit definition for ADC12_COMMON_CDR register ***************/
AnnaBridge 171:3a7713b1edbc 2073 #define ADC12_CDR_RDATA_MST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2074 #define ADC12_CDR_RDATA_MST_Msk (0xFFFFU << ADC12_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 2075 #define ADC12_CDR_RDATA_MST ADC12_CDR_RDATA_MST_Msk /*!< Regular Data of the master ADC */
AnnaBridge 171:3a7713b1edbc 2076 #define ADC12_CDR_RDATA_MST_0 (0x0001U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2077 #define ADC12_CDR_RDATA_MST_1 (0x0002U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2078 #define ADC12_CDR_RDATA_MST_2 (0x0004U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2079 #define ADC12_CDR_RDATA_MST_3 (0x0008U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2080 #define ADC12_CDR_RDATA_MST_4 (0x0010U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2081 #define ADC12_CDR_RDATA_MST_5 (0x0020U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2082 #define ADC12_CDR_RDATA_MST_6 (0x0040U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2083 #define ADC12_CDR_RDATA_MST_7 (0x0080U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2084 #define ADC12_CDR_RDATA_MST_8 (0x0100U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2085 #define ADC12_CDR_RDATA_MST_9 (0x0200U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2086 #define ADC12_CDR_RDATA_MST_10 (0x0400U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2087 #define ADC12_CDR_RDATA_MST_11 (0x0800U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2088 #define ADC12_CDR_RDATA_MST_12 (0x1000U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2089 #define ADC12_CDR_RDATA_MST_13 (0x2000U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2090 #define ADC12_CDR_RDATA_MST_14 (0x4000U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2091 #define ADC12_CDR_RDATA_MST_15 (0x8000U << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2092
AnnaBridge 171:3a7713b1edbc 2093 #define ADC12_CDR_RDATA_SLV_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2094 #define ADC12_CDR_RDATA_SLV_Msk (0xFFFFU << ADC12_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 2095 #define ADC12_CDR_RDATA_SLV ADC12_CDR_RDATA_SLV_Msk /*!< Regular Data of the master ADC */
AnnaBridge 171:3a7713b1edbc 2096 #define ADC12_CDR_RDATA_SLV_0 (0x0001U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2097 #define ADC12_CDR_RDATA_SLV_1 (0x0002U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2098 #define ADC12_CDR_RDATA_SLV_2 (0x0004U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2099 #define ADC12_CDR_RDATA_SLV_3 (0x0008U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2100 #define ADC12_CDR_RDATA_SLV_4 (0x0010U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2101 #define ADC12_CDR_RDATA_SLV_5 (0x0020U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2102 #define ADC12_CDR_RDATA_SLV_6 (0x0040U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2103 #define ADC12_CDR_RDATA_SLV_7 (0x0080U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2104 #define ADC12_CDR_RDATA_SLV_8 (0x0100U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2105 #define ADC12_CDR_RDATA_SLV_9 (0x0200U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 2106 #define ADC12_CDR_RDATA_SLV_10 (0x0400U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 2107 #define ADC12_CDR_RDATA_SLV_11 (0x0800U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 2108 #define ADC12_CDR_RDATA_SLV_12 (0x1000U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 2109 #define ADC12_CDR_RDATA_SLV_13 (0x2000U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 2110 #define ADC12_CDR_RDATA_SLV_14 (0x4000U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2111 #define ADC12_CDR_RDATA_SLV_15 (0x8000U << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2112
AnnaBridge 171:3a7713b1edbc 2113 /******************** Bit definition for ADC_CSR register *******************/
AnnaBridge 171:3a7713b1edbc 2114 #define ADC_CSR_ADRDY_MST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2115 #define ADC_CSR_ADRDY_MST_Msk (0x1U << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2116 #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
AnnaBridge 171:3a7713b1edbc 2117 #define ADC_CSR_EOSMP_MST_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2118 #define ADC_CSR_EOSMP_MST_Msk (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2119 #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
AnnaBridge 171:3a7713b1edbc 2120 #define ADC_CSR_EOC_MST_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2121 #define ADC_CSR_EOC_MST_Msk (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2122 #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
AnnaBridge 171:3a7713b1edbc 2123 #define ADC_CSR_EOS_MST_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2124 #define ADC_CSR_EOS_MST_Msk (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2125 #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
AnnaBridge 171:3a7713b1edbc 2126 #define ADC_CSR_OVR_MST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2127 #define ADC_CSR_OVR_MST_Msk (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2128 #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
AnnaBridge 171:3a7713b1edbc 2129 #define ADC_CSR_JEOC_MST_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2130 #define ADC_CSR_JEOC_MST_Msk (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2131 #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
AnnaBridge 171:3a7713b1edbc 2132 #define ADC_CSR_JEOS_MST_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2133 #define ADC_CSR_JEOS_MST_Msk (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2134 #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
AnnaBridge 171:3a7713b1edbc 2135 #define ADC_CSR_AWD1_MST_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2136 #define ADC_CSR_AWD1_MST_Msk (0x1U << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2137 #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
AnnaBridge 171:3a7713b1edbc 2138 #define ADC_CSR_AWD2_MST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2139 #define ADC_CSR_AWD2_MST_Msk (0x1U << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2140 #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
AnnaBridge 171:3a7713b1edbc 2141 #define ADC_CSR_AWD3_MST_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2142 #define ADC_CSR_AWD3_MST_Msk (0x1U << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2143 #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
AnnaBridge 171:3a7713b1edbc 2144 #define ADC_CSR_JQOVF_MST_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2145 #define ADC_CSR_JQOVF_MST_Msk (0x1U << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2146 #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */
AnnaBridge 171:3a7713b1edbc 2147
AnnaBridge 171:3a7713b1edbc 2148 #define ADC_CSR_ADRDY_SLV_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2149 #define ADC_CSR_ADRDY_SLV_Msk (0x1U << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2150 #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
AnnaBridge 171:3a7713b1edbc 2151 #define ADC_CSR_EOSMP_SLV_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2152 #define ADC_CSR_EOSMP_SLV_Msk (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2153 #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
AnnaBridge 171:3a7713b1edbc 2154 #define ADC_CSR_EOC_SLV_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2155 #define ADC_CSR_EOC_SLV_Msk (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2156 #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
AnnaBridge 171:3a7713b1edbc 2157 #define ADC_CSR_EOS_SLV_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2158 #define ADC_CSR_EOS_SLV_Msk (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2159 #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
AnnaBridge 171:3a7713b1edbc 2160 #define ADC_CSR_OVR_SLV_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2161 #define ADC_CSR_OVR_SLV_Msk (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2162 #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
AnnaBridge 171:3a7713b1edbc 2163 #define ADC_CSR_JEOC_SLV_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2164 #define ADC_CSR_JEOC_SLV_Msk (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2165 #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
AnnaBridge 171:3a7713b1edbc 2166 #define ADC_CSR_JEOS_SLV_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2167 #define ADC_CSR_JEOS_SLV_Msk (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2168 #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
AnnaBridge 171:3a7713b1edbc 2169 #define ADC_CSR_AWD1_SLV_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2170 #define ADC_CSR_AWD1_SLV_Msk (0x1U << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2171 #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
AnnaBridge 171:3a7713b1edbc 2172 #define ADC_CSR_AWD2_SLV_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2173 #define ADC_CSR_AWD2_SLV_Msk (0x1U << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2174 #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
AnnaBridge 171:3a7713b1edbc 2175 #define ADC_CSR_AWD3_SLV_Pos (25U)
AnnaBridge 171:3a7713b1edbc 2176 #define ADC_CSR_AWD3_SLV_Msk (0x1U << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 2177 #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
AnnaBridge 171:3a7713b1edbc 2178 #define ADC_CSR_JQOVF_SLV_Pos (26U)
AnnaBridge 171:3a7713b1edbc 2179 #define ADC_CSR_JQOVF_SLV_Msk (0x1U << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 2180 #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */
AnnaBridge 171:3a7713b1edbc 2181
AnnaBridge 171:3a7713b1edbc 2182 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 2183 #define ADC_CSR_ADRDY_EOSMP_MST ADC_CSR_EOSMP_MST
AnnaBridge 171:3a7713b1edbc 2184 #define ADC_CSR_ADRDY_EOC_MST ADC_CSR_EOC_MST
AnnaBridge 171:3a7713b1edbc 2185 #define ADC_CSR_ADRDY_EOS_MST ADC_CSR_EOS_MST
AnnaBridge 171:3a7713b1edbc 2186 #define ADC_CSR_ADRDY_OVR_MST ADC_CSR_OVR_MST
AnnaBridge 171:3a7713b1edbc 2187 #define ADC_CSR_ADRDY_JEOC_MST ADC_CSR_JEOC_MST
AnnaBridge 171:3a7713b1edbc 2188 #define ADC_CSR_ADRDY_JEOS_MST ADC_CSR_JEOS_MST
AnnaBridge 171:3a7713b1edbc 2189
AnnaBridge 171:3a7713b1edbc 2190 #define ADC_CSR_ADRDY_EOSMP_SLV ADC_CSR_EOSMP_SLV
AnnaBridge 171:3a7713b1edbc 2191 #define ADC_CSR_ADRDY_EOC_SLV ADC_CSR_EOC_SLV
AnnaBridge 171:3a7713b1edbc 2192 #define ADC_CSR_ADRDY_EOS_SLV ADC_CSR_EOS_SLV
AnnaBridge 171:3a7713b1edbc 2193 #define ADC_CSR_ADRDY_OVR_SLV ADC_CSR_OVR_SLV
AnnaBridge 171:3a7713b1edbc 2194 #define ADC_CSR_ADRDY_JEOC_SLV ADC_CSR_JEOC_SLV
AnnaBridge 171:3a7713b1edbc 2195 #define ADC_CSR_ADRDY_JEOS_SLV ADC_CSR_JEOS_SLV
AnnaBridge 171:3a7713b1edbc 2196
AnnaBridge 171:3a7713b1edbc 2197 /******************** Bit definition for ADC_CCR register *******************/
AnnaBridge 171:3a7713b1edbc 2198 #define ADC_CCR_DUAL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2199 #define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 2200 #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
AnnaBridge 171:3a7713b1edbc 2201 #define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2202 #define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2203 #define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2204 #define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2205 #define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2206
AnnaBridge 171:3a7713b1edbc 2207 #define ADC_CCR_DELAY_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2208 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 2209 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
AnnaBridge 171:3a7713b1edbc 2210 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2211 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2212 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2213 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2214
AnnaBridge 171:3a7713b1edbc 2215 #define ADC_CCR_DMACFG_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2216 #define ADC_CCR_DMACFG_Msk (0x1U << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2217 #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
AnnaBridge 171:3a7713b1edbc 2218
AnnaBridge 171:3a7713b1edbc 2219 #define ADC_CCR_MDMA_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2220 #define ADC_CCR_MDMA_Msk (0x3U << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 2221 #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
AnnaBridge 171:3a7713b1edbc 2222 #define ADC_CCR_MDMA_0 (0x1U << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2223 #define ADC_CCR_MDMA_1 (0x2U << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2224
AnnaBridge 171:3a7713b1edbc 2225 #define ADC_CCR_CKMODE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2226 #define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 2227 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
AnnaBridge 171:3a7713b1edbc 2228 #define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2229 #define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2230
AnnaBridge 171:3a7713b1edbc 2231 #define ADC_CCR_VREFEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2232 #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2233 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
AnnaBridge 171:3a7713b1edbc 2234 #define ADC_CCR_TSEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2235 #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2236 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
AnnaBridge 171:3a7713b1edbc 2237 #define ADC_CCR_VBATEN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2238 #define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2239 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
AnnaBridge 171:3a7713b1edbc 2240
AnnaBridge 171:3a7713b1edbc 2241 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 2242 #define ADC_CCR_MULTI (ADC_CCR_DUAL)
AnnaBridge 171:3a7713b1edbc 2243 #define ADC_CCR_MULTI_0 (ADC_CCR_DUAL_0)
AnnaBridge 171:3a7713b1edbc 2244 #define ADC_CCR_MULTI_1 (ADC_CCR_DUAL_1)
AnnaBridge 171:3a7713b1edbc 2245 #define ADC_CCR_MULTI_2 (ADC_CCR_DUAL_2)
AnnaBridge 171:3a7713b1edbc 2246 #define ADC_CCR_MULTI_3 (ADC_CCR_DUAL_3)
AnnaBridge 171:3a7713b1edbc 2247 #define ADC_CCR_MULTI_4 (ADC_CCR_DUAL_4)
AnnaBridge 171:3a7713b1edbc 2248
AnnaBridge 171:3a7713b1edbc 2249 /******************** Bit definition for ADC_CDR register *******************/
AnnaBridge 171:3a7713b1edbc 2250 #define ADC_CDR_RDATA_MST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2251 #define ADC_CDR_RDATA_MST_Msk (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 2252 #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
AnnaBridge 171:3a7713b1edbc 2253 #define ADC_CDR_RDATA_MST_0 (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2254 #define ADC_CDR_RDATA_MST_1 (0x0002U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2255 #define ADC_CDR_RDATA_MST_2 (0x0004U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2256 #define ADC_CDR_RDATA_MST_3 (0x0008U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2257 #define ADC_CDR_RDATA_MST_4 (0x0010U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2258 #define ADC_CDR_RDATA_MST_5 (0x0020U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2259 #define ADC_CDR_RDATA_MST_6 (0x0040U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2260 #define ADC_CDR_RDATA_MST_7 (0x0080U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2261 #define ADC_CDR_RDATA_MST_8 (0x0100U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2262 #define ADC_CDR_RDATA_MST_9 (0x0200U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2263 #define ADC_CDR_RDATA_MST_10 (0x0400U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2264 #define ADC_CDR_RDATA_MST_11 (0x0800U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2265 #define ADC_CDR_RDATA_MST_12 (0x1000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2266 #define ADC_CDR_RDATA_MST_13 (0x2000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2267 #define ADC_CDR_RDATA_MST_14 (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2268 #define ADC_CDR_RDATA_MST_15 (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2269
AnnaBridge 171:3a7713b1edbc 2270 #define ADC_CDR_RDATA_SLV_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2271 #define ADC_CDR_RDATA_SLV_Msk (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 2272 #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
AnnaBridge 171:3a7713b1edbc 2273 #define ADC_CDR_RDATA_SLV_0 (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2274 #define ADC_CDR_RDATA_SLV_1 (0x0002U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2275 #define ADC_CDR_RDATA_SLV_2 (0x0004U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2276 #define ADC_CDR_RDATA_SLV_3 (0x0008U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2277 #define ADC_CDR_RDATA_SLV_4 (0x0010U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2278 #define ADC_CDR_RDATA_SLV_5 (0x0020U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2279 #define ADC_CDR_RDATA_SLV_6 (0x0040U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2280 #define ADC_CDR_RDATA_SLV_7 (0x0080U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2281 #define ADC_CDR_RDATA_SLV_8 (0x0100U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2282 #define ADC_CDR_RDATA_SLV_9 (0x0200U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 2283 #define ADC_CDR_RDATA_SLV_10 (0x0400U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 2284 #define ADC_CDR_RDATA_SLV_11 (0x0800U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 2285 #define ADC_CDR_RDATA_SLV_12 (0x1000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 2286 #define ADC_CDR_RDATA_SLV_13 (0x2000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 2287 #define ADC_CDR_RDATA_SLV_14 (0x4000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2288 #define ADC_CDR_RDATA_SLV_15 (0x8000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2289
AnnaBridge 171:3a7713b1edbc 2290 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 2291 /* */
AnnaBridge 171:3a7713b1edbc 2292 /* Analog Comparators (COMP) */
AnnaBridge 171:3a7713b1edbc 2293 /* */
AnnaBridge 171:3a7713b1edbc 2294 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 2295
AnnaBridge 171:3a7713b1edbc 2296 #define COMP_V1_3_0_0 /*!< Comparator IP version */
AnnaBridge 171:3a7713b1edbc 2297
AnnaBridge 171:3a7713b1edbc 2298 /********************** Bit definition for COMP2_CSR register ***************/
AnnaBridge 171:3a7713b1edbc 2299 #define COMP2_CSR_COMP2EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2300 #define COMP2_CSR_COMP2EN_Msk (0x1U << COMP2_CSR_COMP2EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2301 #define COMP2_CSR_COMP2EN COMP2_CSR_COMP2EN_Msk /*!< COMP2 enable */
AnnaBridge 171:3a7713b1edbc 2302 #define COMP2_CSR_COMP2INSEL_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2303 #define COMP2_CSR_COMP2INSEL_Msk (0x40007U << COMP2_CSR_COMP2INSEL_Pos) /*!< 0x00400070 */
AnnaBridge 171:3a7713b1edbc 2304 #define COMP2_CSR_COMP2INSEL COMP2_CSR_COMP2INSEL_Msk /*!< COMP2 inverting input select */
AnnaBridge 171:3a7713b1edbc 2305 #define COMP2_CSR_COMP2INSEL_0 (0x00000010U) /*!< COMP2 inverting input select bit 0 */
AnnaBridge 171:3a7713b1edbc 2306 #define COMP2_CSR_COMP2INSEL_1 (0x00000020U) /*!< COMP2 inverting input select bit 1 */
AnnaBridge 171:3a7713b1edbc 2307 #define COMP2_CSR_COMP2INSEL_2 (0x00000040U) /*!< COMP2 inverting input select bit 2 */
AnnaBridge 171:3a7713b1edbc 2308 #define COMP2_CSR_COMP2INSEL_3 (0x00400000U) /*!< COMP2 inverting input select bit 3 */
AnnaBridge 171:3a7713b1edbc 2309 #define COMP2_CSR_COMP2OUTSEL_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2310 #define COMP2_CSR_COMP2OUTSEL_Msk (0xFU << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00003C00 */
AnnaBridge 171:3a7713b1edbc 2311 #define COMP2_CSR_COMP2OUTSEL COMP2_CSR_COMP2OUTSEL_Msk /*!< COMP2 output select */
AnnaBridge 171:3a7713b1edbc 2312 #define COMP2_CSR_COMP2OUTSEL_0 (0x1U << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2313 #define COMP2_CSR_COMP2OUTSEL_1 (0x2U << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2314 #define COMP2_CSR_COMP2OUTSEL_2 (0x4U << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2315 #define COMP2_CSR_COMP2OUTSEL_3 (0x8U << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2316 #define COMP2_CSR_COMP2POL_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2317 #define COMP2_CSR_COMP2POL_Msk (0x1U << COMP2_CSR_COMP2POL_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2318 #define COMP2_CSR_COMP2POL COMP2_CSR_COMP2POL_Msk /*!< COMP2 output polarity */
AnnaBridge 171:3a7713b1edbc 2319 #define COMP2_CSR_COMP2BLANKING_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2320 #define COMP2_CSR_COMP2BLANKING_Msk (0x3U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 2321 #define COMP2_CSR_COMP2BLANKING COMP2_CSR_COMP2BLANKING_Msk /*!< COMP2 blanking */
AnnaBridge 171:3a7713b1edbc 2322 #define COMP2_CSR_COMP2BLANKING_0 (0x1U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2323 #define COMP2_CSR_COMP2BLANKING_1 (0x2U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2324 #define COMP2_CSR_COMP2BLANKING_2 (0x4U << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2325 #define COMP2_CSR_COMP2OUT_Pos (30U)
AnnaBridge 171:3a7713b1edbc 2326 #define COMP2_CSR_COMP2OUT_Msk (0x1U << COMP2_CSR_COMP2OUT_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2327 #define COMP2_CSR_COMP2OUT COMP2_CSR_COMP2OUT_Msk /*!< COMP2 output level */
AnnaBridge 171:3a7713b1edbc 2328 #define COMP2_CSR_COMP2LOCK_Pos (31U)
AnnaBridge 171:3a7713b1edbc 2329 #define COMP2_CSR_COMP2LOCK_Msk (0x1U << COMP2_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2330 #define COMP2_CSR_COMP2LOCK COMP2_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
AnnaBridge 171:3a7713b1edbc 2331
AnnaBridge 171:3a7713b1edbc 2332 /********************** Bit definition for COMP4_CSR register ***************/
AnnaBridge 171:3a7713b1edbc 2333 #define COMP4_CSR_COMP4EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2334 #define COMP4_CSR_COMP4EN_Msk (0x1U << COMP4_CSR_COMP4EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2335 #define COMP4_CSR_COMP4EN COMP4_CSR_COMP4EN_Msk /*!< COMP4 enable */
AnnaBridge 171:3a7713b1edbc 2336 #define COMP4_CSR_COMP4INSEL_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2337 #define COMP4_CSR_COMP4INSEL_Msk (0x40007U << COMP4_CSR_COMP4INSEL_Pos) /*!< 0x00400070 */
AnnaBridge 171:3a7713b1edbc 2338 #define COMP4_CSR_COMP4INSEL COMP4_CSR_COMP4INSEL_Msk /*!< COMP4 inverting input select */
AnnaBridge 171:3a7713b1edbc 2339 #define COMP4_CSR_COMP4INSEL_0 (0x00000010U) /*!< COMP4 inverting input select bit 0 */
AnnaBridge 171:3a7713b1edbc 2340 #define COMP4_CSR_COMP4INSEL_1 (0x00000020U) /*!< COMP4 inverting input select bit 1 */
AnnaBridge 171:3a7713b1edbc 2341 #define COMP4_CSR_COMP4INSEL_2 (0x00000040U) /*!< COMP4 inverting input select bit 2 */
AnnaBridge 171:3a7713b1edbc 2342 #define COMP4_CSR_COMP4INSEL_3 (0x00400000U) /*!< COMP4 inverting input select bit 3 */
AnnaBridge 171:3a7713b1edbc 2343 #define COMP4_CSR_COMP4OUTSEL_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2344 #define COMP4_CSR_COMP4OUTSEL_Msk (0xFU << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00003C00 */
AnnaBridge 171:3a7713b1edbc 2345 #define COMP4_CSR_COMP4OUTSEL COMP4_CSR_COMP4OUTSEL_Msk /*!< COMP4 output select */
AnnaBridge 171:3a7713b1edbc 2346 #define COMP4_CSR_COMP4OUTSEL_0 (0x1U << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2347 #define COMP4_CSR_COMP4OUTSEL_1 (0x2U << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2348 #define COMP4_CSR_COMP4OUTSEL_2 (0x4U << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2349 #define COMP4_CSR_COMP4OUTSEL_3 (0x8U << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2350 #define COMP4_CSR_COMP4POL_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2351 #define COMP4_CSR_COMP4POL_Msk (0x1U << COMP4_CSR_COMP4POL_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2352 #define COMP4_CSR_COMP4POL COMP4_CSR_COMP4POL_Msk /*!< COMP4 output polarity */
AnnaBridge 171:3a7713b1edbc 2353 #define COMP4_CSR_COMP4BLANKING_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2354 #define COMP4_CSR_COMP4BLANKING_Msk (0x3U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 2355 #define COMP4_CSR_COMP4BLANKING COMP4_CSR_COMP4BLANKING_Msk /*!< COMP4 blanking */
AnnaBridge 171:3a7713b1edbc 2356 #define COMP4_CSR_COMP4BLANKING_0 (0x1U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2357 #define COMP4_CSR_COMP4BLANKING_1 (0x2U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2358 #define COMP4_CSR_COMP4BLANKING_2 (0x4U << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2359 #define COMP4_CSR_COMP4OUT_Pos (30U)
AnnaBridge 171:3a7713b1edbc 2360 #define COMP4_CSR_COMP4OUT_Msk (0x1U << COMP4_CSR_COMP4OUT_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2361 #define COMP4_CSR_COMP4OUT COMP4_CSR_COMP4OUT_Msk /*!< COMP4 output level */
AnnaBridge 171:3a7713b1edbc 2362 #define COMP4_CSR_COMP4LOCK_Pos (31U)
AnnaBridge 171:3a7713b1edbc 2363 #define COMP4_CSR_COMP4LOCK_Msk (0x1U << COMP4_CSR_COMP4LOCK_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2364 #define COMP4_CSR_COMP4LOCK COMP4_CSR_COMP4LOCK_Msk /*!< COMP4 lock */
AnnaBridge 171:3a7713b1edbc 2365
AnnaBridge 171:3a7713b1edbc 2366 /********************** Bit definition for COMP6_CSR register ***************/
AnnaBridge 171:3a7713b1edbc 2367 #define COMP6_CSR_COMP6EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2368 #define COMP6_CSR_COMP6EN_Msk (0x1U << COMP6_CSR_COMP6EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2369 #define COMP6_CSR_COMP6EN COMP6_CSR_COMP6EN_Msk /*!< COMP6 enable */
AnnaBridge 171:3a7713b1edbc 2370 #define COMP6_CSR_COMP6INSEL_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2371 #define COMP6_CSR_COMP6INSEL_Msk (0x40007U << COMP6_CSR_COMP6INSEL_Pos) /*!< 0x00400070 */
AnnaBridge 171:3a7713b1edbc 2372 #define COMP6_CSR_COMP6INSEL COMP6_CSR_COMP6INSEL_Msk /*!< COMP6 inverting input select */
AnnaBridge 171:3a7713b1edbc 2373 #define COMP6_CSR_COMP6INSEL_0 (0x00000010U) /*!< COMP6 inverting input select bit 0 */
AnnaBridge 171:3a7713b1edbc 2374 #define COMP6_CSR_COMP6INSEL_1 (0x00000020U) /*!< COMP6 inverting input select bit 1 */
AnnaBridge 171:3a7713b1edbc 2375 #define COMP6_CSR_COMP6INSEL_2 (0x00000040U) /*!< COMP6 inverting input select bit 2 */
AnnaBridge 171:3a7713b1edbc 2376 #define COMP6_CSR_COMP6INSEL_3 (0x00400000U) /*!< COMP6 inverting input select bit 3 */
AnnaBridge 171:3a7713b1edbc 2377 #define COMP6_CSR_COMP6OUTSEL_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2378 #define COMP6_CSR_COMP6OUTSEL_Msk (0xFU << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00003C00 */
AnnaBridge 171:3a7713b1edbc 2379 #define COMP6_CSR_COMP6OUTSEL COMP6_CSR_COMP6OUTSEL_Msk /*!< COMP6 output select */
AnnaBridge 171:3a7713b1edbc 2380 #define COMP6_CSR_COMP6OUTSEL_0 (0x1U << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2381 #define COMP6_CSR_COMP6OUTSEL_1 (0x2U << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2382 #define COMP6_CSR_COMP6OUTSEL_2 (0x4U << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2383 #define COMP6_CSR_COMP6OUTSEL_3 (0x8U << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2384 #define COMP6_CSR_COMP6POL_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2385 #define COMP6_CSR_COMP6POL_Msk (0x1U << COMP6_CSR_COMP6POL_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2386 #define COMP6_CSR_COMP6POL COMP6_CSR_COMP6POL_Msk /*!< COMP6 output polarity */
AnnaBridge 171:3a7713b1edbc 2387 #define COMP6_CSR_COMP6BLANKING_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2388 #define COMP6_CSR_COMP6BLANKING_Msk (0x3U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 2389 #define COMP6_CSR_COMP6BLANKING COMP6_CSR_COMP6BLANKING_Msk /*!< COMP6 blanking */
AnnaBridge 171:3a7713b1edbc 2390 #define COMP6_CSR_COMP6BLANKING_0 (0x1U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2391 #define COMP6_CSR_COMP6BLANKING_1 (0x2U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2392 #define COMP6_CSR_COMP6BLANKING_2 (0x4U << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2393 #define COMP6_CSR_COMP6OUT_Pos (30U)
AnnaBridge 171:3a7713b1edbc 2394 #define COMP6_CSR_COMP6OUT_Msk (0x1U << COMP6_CSR_COMP6OUT_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2395 #define COMP6_CSR_COMP6OUT COMP6_CSR_COMP6OUT_Msk /*!< COMP6 output level */
AnnaBridge 171:3a7713b1edbc 2396 #define COMP6_CSR_COMP6LOCK_Pos (31U)
AnnaBridge 171:3a7713b1edbc 2397 #define COMP6_CSR_COMP6LOCK_Msk (0x1U << COMP6_CSR_COMP6LOCK_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2398 #define COMP6_CSR_COMP6LOCK COMP6_CSR_COMP6LOCK_Msk /*!< COMP6 lock */
AnnaBridge 171:3a7713b1edbc 2399
AnnaBridge 171:3a7713b1edbc 2400 /********************** Bit definition for COMP_CSR register ****************/
AnnaBridge 171:3a7713b1edbc 2401 #define COMP_CSR_COMPxEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2402 #define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2403 #define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
AnnaBridge 171:3a7713b1edbc 2404 #define COMP_CSR_COMPxINSEL_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2405 #define COMP_CSR_COMPxINSEL_Msk (0x40007U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00400070 */
AnnaBridge 171:3a7713b1edbc 2406 #define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk /*!< COMPx inverting input select */
AnnaBridge 171:3a7713b1edbc 2407 #define COMP_CSR_COMPxINSEL_0 (0x00000010U) /*!< COMPx inverting input select bit 0 */
AnnaBridge 171:3a7713b1edbc 2408 #define COMP_CSR_COMPxINSEL_1 (0x00000020U) /*!< COMPx inverting input select bit 1 */
AnnaBridge 171:3a7713b1edbc 2409 #define COMP_CSR_COMPxINSEL_2 (0x00000040U) /*!< COMPx inverting input select bit 2 */
AnnaBridge 171:3a7713b1edbc 2410 #define COMP_CSR_COMPxINSEL_3 (0x00400000U) /*!< COMPx inverting input select bit 3 */
AnnaBridge 171:3a7713b1edbc 2411 #define COMP_CSR_COMPxOUTSEL_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2412 #define COMP_CSR_COMPxOUTSEL_Msk (0xFU << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00003C00 */
AnnaBridge 171:3a7713b1edbc 2413 #define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk /*!< COMPx output select */
AnnaBridge 171:3a7713b1edbc 2414 #define COMP_CSR_COMPxOUTSEL_0 (0x1U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2415 #define COMP_CSR_COMPxOUTSEL_1 (0x2U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2416 #define COMP_CSR_COMPxOUTSEL_2 (0x4U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2417 #define COMP_CSR_COMPxOUTSEL_3 (0x8U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2418 #define COMP_CSR_COMPxPOL_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2419 #define COMP_CSR_COMPxPOL_Msk (0x1U << COMP_CSR_COMPxPOL_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2420 #define COMP_CSR_COMPxPOL COMP_CSR_COMPxPOL_Msk /*!< COMPx output polarity */
AnnaBridge 171:3a7713b1edbc 2421 #define COMP_CSR_COMPxBLANKING_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2422 #define COMP_CSR_COMPxBLANKING_Msk (0x3U << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 2423 #define COMP_CSR_COMPxBLANKING COMP_CSR_COMPxBLANKING_Msk /*!< COMPx blanking */
AnnaBridge 171:3a7713b1edbc 2424 #define COMP_CSR_COMPxBLANKING_0 (0x1U << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2425 #define COMP_CSR_COMPxBLANKING_1 (0x2U << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2426 #define COMP_CSR_COMPxBLANKING_2 (0x4U << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2427 #define COMP_CSR_COMPxOUT_Pos (30U)
AnnaBridge 171:3a7713b1edbc 2428 #define COMP_CSR_COMPxOUT_Msk (0x1U << COMP_CSR_COMPxOUT_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2429 #define COMP_CSR_COMPxOUT COMP_CSR_COMPxOUT_Msk /*!< COMPx output level */
AnnaBridge 171:3a7713b1edbc 2430 #define COMP_CSR_COMPxLOCK_Pos (31U)
AnnaBridge 171:3a7713b1edbc 2431 #define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2432 #define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
AnnaBridge 171:3a7713b1edbc 2433
AnnaBridge 171:3a7713b1edbc 2434 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 2435 /* */
AnnaBridge 171:3a7713b1edbc 2436 /* Operational Amplifier (OPAMP) */
AnnaBridge 171:3a7713b1edbc 2437 /* */
AnnaBridge 171:3a7713b1edbc 2438 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 2439 /********************* Bit definition for OPAMP2_CSR register ***************/
AnnaBridge 171:3a7713b1edbc 2440 #define OPAMP2_CSR_OPAMP2EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2441 #define OPAMP2_CSR_OPAMP2EN_Msk (0x1U << OPAMP2_CSR_OPAMP2EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2442 #define OPAMP2_CSR_OPAMP2EN OPAMP2_CSR_OPAMP2EN_Msk /*!< OPAMP2 enable */
AnnaBridge 171:3a7713b1edbc 2443 #define OPAMP2_CSR_FORCEVP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2444 #define OPAMP2_CSR_FORCEVP_Msk (0x1U << OPAMP2_CSR_FORCEVP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2445 #define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
AnnaBridge 171:3a7713b1edbc 2446 #define OPAMP2_CSR_VPSEL_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2447 #define OPAMP2_CSR_VPSEL_Msk (0x3U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 2448 #define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverting input selection */
AnnaBridge 171:3a7713b1edbc 2449 #define OPAMP2_CSR_VPSEL_0 (0x1U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2450 #define OPAMP2_CSR_VPSEL_1 (0x2U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2451 #define OPAMP2_CSR_VMSEL_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2452 #define OPAMP2_CSR_VMSEL_Msk (0x3U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000060 */
AnnaBridge 171:3a7713b1edbc 2453 #define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
AnnaBridge 171:3a7713b1edbc 2454 #define OPAMP2_CSR_VMSEL_0 (0x1U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2455 #define OPAMP2_CSR_VMSEL_1 (0x2U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2456 #define OPAMP2_CSR_TCMEN_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2457 #define OPAMP2_CSR_TCMEN_Msk (0x1U << OPAMP2_CSR_TCMEN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2458 #define OPAMP2_CSR_TCMEN OPAMP2_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */
AnnaBridge 171:3a7713b1edbc 2459 #define OPAMP2_CSR_VMSSEL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2460 #define OPAMP2_CSR_VMSSEL_Msk (0x1U << OPAMP2_CSR_VMSSEL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2461 #define OPAMP2_CSR_VMSSEL OPAMP2_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */
AnnaBridge 171:3a7713b1edbc 2462 #define OPAMP2_CSR_VPSSEL_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2463 #define OPAMP2_CSR_VPSSEL_Msk (0x3U << OPAMP2_CSR_VPSSEL_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 2464 #define OPAMP2_CSR_VPSSEL OPAMP2_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */
AnnaBridge 171:3a7713b1edbc 2465 #define OPAMP2_CSR_VPSSEL_0 (0x1U << OPAMP2_CSR_VPSSEL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2466 #define OPAMP2_CSR_VPSSEL_1 (0x2U << OPAMP2_CSR_VPSSEL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2467 #define OPAMP2_CSR_CALON_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2468 #define OPAMP2_CSR_CALON_Msk (0x1U << OPAMP2_CSR_CALON_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2469 #define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
AnnaBridge 171:3a7713b1edbc 2470 #define OPAMP2_CSR_CALSEL_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2471 #define OPAMP2_CSR_CALSEL_Msk (0x3U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 2472 #define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
AnnaBridge 171:3a7713b1edbc 2473 #define OPAMP2_CSR_CALSEL_0 (0x1U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2474 #define OPAMP2_CSR_CALSEL_1 (0x2U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2475 #define OPAMP2_CSR_PGGAIN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2476 #define OPAMP2_CSR_PGGAIN_Msk (0xFU << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
AnnaBridge 171:3a7713b1edbc 2477 #define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
AnnaBridge 171:3a7713b1edbc 2478 #define OPAMP2_CSR_PGGAIN_0 (0x1U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2479 #define OPAMP2_CSR_PGGAIN_1 (0x2U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2480 #define OPAMP2_CSR_PGGAIN_2 (0x4U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2481 #define OPAMP2_CSR_PGGAIN_3 (0x8U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2482 #define OPAMP2_CSR_USERTRIM_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2483 #define OPAMP2_CSR_USERTRIM_Msk (0x1U << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2484 #define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
AnnaBridge 171:3a7713b1edbc 2485 #define OPAMP2_CSR_TRIMOFFSETP_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2486 #define OPAMP2_CSR_TRIMOFFSETP_Msk (0x1FU << OPAMP2_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
AnnaBridge 171:3a7713b1edbc 2487 #define OPAMP2_CSR_TRIMOFFSETP OPAMP2_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
AnnaBridge 171:3a7713b1edbc 2488 #define OPAMP2_CSR_TRIMOFFSETN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2489 #define OPAMP2_CSR_TRIMOFFSETN_Msk (0x1FU << OPAMP2_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
AnnaBridge 171:3a7713b1edbc 2490 #define OPAMP2_CSR_TRIMOFFSETN OPAMP2_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
AnnaBridge 171:3a7713b1edbc 2491 #define OPAMP2_CSR_TSTREF_Pos (29U)
AnnaBridge 171:3a7713b1edbc 2492 #define OPAMP2_CSR_TSTREF_Msk (0x1U << OPAMP2_CSR_TSTREF_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 2493 #define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */
AnnaBridge 171:3a7713b1edbc 2494 #define OPAMP2_CSR_OUTCAL_Pos (30U)
AnnaBridge 171:3a7713b1edbc 2495 #define OPAMP2_CSR_OUTCAL_Msk (0x1U << OPAMP2_CSR_OUTCAL_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2496 #define OPAMP2_CSR_OUTCAL OPAMP2_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
AnnaBridge 171:3a7713b1edbc 2497 #define OPAMP2_CSR_LOCK_Pos (31U)
AnnaBridge 171:3a7713b1edbc 2498 #define OPAMP2_CSR_LOCK_Msk (0x1U << OPAMP2_CSR_LOCK_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2499 #define OPAMP2_CSR_LOCK OPAMP2_CSR_LOCK_Msk /*!< OPAMP lock */
AnnaBridge 171:3a7713b1edbc 2500
AnnaBridge 171:3a7713b1edbc 2501 /********************* Bit definition for OPAMPx_CSR register ***************/
AnnaBridge 171:3a7713b1edbc 2502 #define OPAMP_CSR_OPAMPxEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2503 #define OPAMP_CSR_OPAMPxEN_Msk (0x1U << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2504 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
AnnaBridge 171:3a7713b1edbc 2505 #define OPAMP_CSR_FORCEVP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2506 #define OPAMP_CSR_FORCEVP_Msk (0x1U << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2507 #define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
AnnaBridge 171:3a7713b1edbc 2508 #define OPAMP_CSR_VPSEL_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2509 #define OPAMP_CSR_VPSEL_Msk (0x3U << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 2510 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverting input selection */
AnnaBridge 171:3a7713b1edbc 2511 #define OPAMP_CSR_VPSEL_0 (0x1U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2512 #define OPAMP_CSR_VPSEL_1 (0x2U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2513 #define OPAMP_CSR_VMSEL_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2514 #define OPAMP_CSR_VMSEL_Msk (0x3U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
AnnaBridge 171:3a7713b1edbc 2515 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
AnnaBridge 171:3a7713b1edbc 2516 #define OPAMP_CSR_VMSEL_0 (0x1U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2517 #define OPAMP_CSR_VMSEL_1 (0x2U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2518 #define OPAMP_CSR_TCMEN_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2519 #define OPAMP_CSR_TCMEN_Msk (0x1U << OPAMP_CSR_TCMEN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2520 #define OPAMP_CSR_TCMEN OPAMP_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */
AnnaBridge 171:3a7713b1edbc 2521 #define OPAMP_CSR_VMSSEL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2522 #define OPAMP_CSR_VMSSEL_Msk (0x1U << OPAMP_CSR_VMSSEL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2523 #define OPAMP_CSR_VMSSEL OPAMP_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */
AnnaBridge 171:3a7713b1edbc 2524 #define OPAMP_CSR_VPSSEL_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2525 #define OPAMP_CSR_VPSSEL_Msk (0x3U << OPAMP_CSR_VPSSEL_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 2526 #define OPAMP_CSR_VPSSEL OPAMP_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */
AnnaBridge 171:3a7713b1edbc 2527 #define OPAMP_CSR_VPSSEL_0 (0x1U << OPAMP_CSR_VPSSEL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2528 #define OPAMP_CSR_VPSSEL_1 (0x2U << OPAMP_CSR_VPSSEL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2529 #define OPAMP_CSR_CALON_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2530 #define OPAMP_CSR_CALON_Msk (0x1U << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2531 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
AnnaBridge 171:3a7713b1edbc 2532 #define OPAMP_CSR_CALSEL_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2533 #define OPAMP_CSR_CALSEL_Msk (0x3U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 2534 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
AnnaBridge 171:3a7713b1edbc 2535 #define OPAMP_CSR_CALSEL_0 (0x1U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2536 #define OPAMP_CSR_CALSEL_1 (0x2U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2537 #define OPAMP_CSR_PGGAIN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2538 #define OPAMP_CSR_PGGAIN_Msk (0xFU << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
AnnaBridge 171:3a7713b1edbc 2539 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
AnnaBridge 171:3a7713b1edbc 2540 #define OPAMP_CSR_PGGAIN_0 (0x1U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2541 #define OPAMP_CSR_PGGAIN_1 (0x2U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2542 #define OPAMP_CSR_PGGAIN_2 (0x4U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2543 #define OPAMP_CSR_PGGAIN_3 (0x8U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2544 #define OPAMP_CSR_USERTRIM_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2545 #define OPAMP_CSR_USERTRIM_Msk (0x1U << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2546 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
AnnaBridge 171:3a7713b1edbc 2547 #define OPAMP_CSR_TRIMOFFSETP_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2548 #define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FU << OPAMP_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
AnnaBridge 171:3a7713b1edbc 2549 #define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
AnnaBridge 171:3a7713b1edbc 2550 #define OPAMP_CSR_TRIMOFFSETN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2551 #define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FU << OPAMP_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
AnnaBridge 171:3a7713b1edbc 2552 #define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
AnnaBridge 171:3a7713b1edbc 2553 #define OPAMP_CSR_TSTREF_Pos (29U)
AnnaBridge 171:3a7713b1edbc 2554 #define OPAMP_CSR_TSTREF_Msk (0x1U << OPAMP_CSR_TSTREF_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 2555 #define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */
AnnaBridge 171:3a7713b1edbc 2556 #define OPAMP_CSR_OUTCAL_Pos (30U)
AnnaBridge 171:3a7713b1edbc 2557 #define OPAMP_CSR_OUTCAL_Msk (0x1U << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2558 #define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
AnnaBridge 171:3a7713b1edbc 2559 #define OPAMP_CSR_LOCK_Pos (31U)
AnnaBridge 171:3a7713b1edbc 2560 #define OPAMP_CSR_LOCK_Msk (0x1U << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2561 #define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP lock */
AnnaBridge 171:3a7713b1edbc 2562
AnnaBridge 171:3a7713b1edbc 2563 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 2564 /* */
AnnaBridge 171:3a7713b1edbc 2565 /* Controller Area Network (CAN ) */
AnnaBridge 171:3a7713b1edbc 2566 /* */
AnnaBridge 171:3a7713b1edbc 2567 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 2568 /******************* Bit definition for CAN_MCR register ********************/
AnnaBridge 171:3a7713b1edbc 2569 #define CAN_MCR_INRQ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2570 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2571 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
AnnaBridge 171:3a7713b1edbc 2572 #define CAN_MCR_SLEEP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2573 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2574 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
AnnaBridge 171:3a7713b1edbc 2575 #define CAN_MCR_TXFP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2576 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2577 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
AnnaBridge 171:3a7713b1edbc 2578 #define CAN_MCR_RFLM_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2579 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2580 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
AnnaBridge 171:3a7713b1edbc 2581 #define CAN_MCR_NART_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2582 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2583 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
AnnaBridge 171:3a7713b1edbc 2584 #define CAN_MCR_AWUM_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2585 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2586 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
AnnaBridge 171:3a7713b1edbc 2587 #define CAN_MCR_ABOM_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2588 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2589 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
AnnaBridge 171:3a7713b1edbc 2590 #define CAN_MCR_TTCM_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2591 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2592 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
AnnaBridge 171:3a7713b1edbc 2593 #define CAN_MCR_RESET_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2594 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2595 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
AnnaBridge 171:3a7713b1edbc 2596
AnnaBridge 171:3a7713b1edbc 2597 /******************* Bit definition for CAN_MSR register ********************/
AnnaBridge 171:3a7713b1edbc 2598 #define CAN_MSR_INAK_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2599 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2600 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
AnnaBridge 171:3a7713b1edbc 2601 #define CAN_MSR_SLAK_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2602 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2603 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
AnnaBridge 171:3a7713b1edbc 2604 #define CAN_MSR_ERRI_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2605 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2606 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
AnnaBridge 171:3a7713b1edbc 2607 #define CAN_MSR_WKUI_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2608 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2609 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
AnnaBridge 171:3a7713b1edbc 2610 #define CAN_MSR_SLAKI_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2611 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2612 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
AnnaBridge 171:3a7713b1edbc 2613 #define CAN_MSR_TXM_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2614 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2615 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
AnnaBridge 171:3a7713b1edbc 2616 #define CAN_MSR_RXM_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2617 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2618 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
AnnaBridge 171:3a7713b1edbc 2619 #define CAN_MSR_SAMP_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2620 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2621 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
AnnaBridge 171:3a7713b1edbc 2622 #define CAN_MSR_RX_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2623 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2624 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
AnnaBridge 171:3a7713b1edbc 2625
AnnaBridge 171:3a7713b1edbc 2626 /******************* Bit definition for CAN_TSR register ********************/
AnnaBridge 171:3a7713b1edbc 2627 #define CAN_TSR_RQCP0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2628 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2629 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
AnnaBridge 171:3a7713b1edbc 2630 #define CAN_TSR_TXOK0_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2631 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2632 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
AnnaBridge 171:3a7713b1edbc 2633 #define CAN_TSR_ALST0_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2634 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2635 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
AnnaBridge 171:3a7713b1edbc 2636 #define CAN_TSR_TERR0_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2637 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2638 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
AnnaBridge 171:3a7713b1edbc 2639 #define CAN_TSR_ABRQ0_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2640 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2641 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
AnnaBridge 171:3a7713b1edbc 2642 #define CAN_TSR_RQCP1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2643 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2644 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
AnnaBridge 171:3a7713b1edbc 2645 #define CAN_TSR_TXOK1_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2646 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2647 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
AnnaBridge 171:3a7713b1edbc 2648 #define CAN_TSR_ALST1_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2649 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2650 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
AnnaBridge 171:3a7713b1edbc 2651 #define CAN_TSR_TERR1_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2652 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2653 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
AnnaBridge 171:3a7713b1edbc 2654 #define CAN_TSR_ABRQ1_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2655 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2656 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
AnnaBridge 171:3a7713b1edbc 2657 #define CAN_TSR_RQCP2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2658 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2659 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
AnnaBridge 171:3a7713b1edbc 2660 #define CAN_TSR_TXOK2_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2661 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2662 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
AnnaBridge 171:3a7713b1edbc 2663 #define CAN_TSR_ALST2_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2664 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2665 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
AnnaBridge 171:3a7713b1edbc 2666 #define CAN_TSR_TERR2_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2667 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2668 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
AnnaBridge 171:3a7713b1edbc 2669 #define CAN_TSR_ABRQ2_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2670 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2671 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
AnnaBridge 171:3a7713b1edbc 2672 #define CAN_TSR_CODE_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2673 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 2674 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
AnnaBridge 171:3a7713b1edbc 2675
AnnaBridge 171:3a7713b1edbc 2676 #define CAN_TSR_TME_Pos (26U)
AnnaBridge 171:3a7713b1edbc 2677 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
AnnaBridge 171:3a7713b1edbc 2678 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
AnnaBridge 171:3a7713b1edbc 2679 #define CAN_TSR_TME0_Pos (26U)
AnnaBridge 171:3a7713b1edbc 2680 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 2681 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
AnnaBridge 171:3a7713b1edbc 2682 #define CAN_TSR_TME1_Pos (27U)
AnnaBridge 171:3a7713b1edbc 2683 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 2684 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
AnnaBridge 171:3a7713b1edbc 2685 #define CAN_TSR_TME2_Pos (28U)
AnnaBridge 171:3a7713b1edbc 2686 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 2687 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
AnnaBridge 171:3a7713b1edbc 2688
AnnaBridge 171:3a7713b1edbc 2689 #define CAN_TSR_LOW_Pos (29U)
AnnaBridge 171:3a7713b1edbc 2690 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
AnnaBridge 171:3a7713b1edbc 2691 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
AnnaBridge 171:3a7713b1edbc 2692 #define CAN_TSR_LOW0_Pos (29U)
AnnaBridge 171:3a7713b1edbc 2693 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 2694 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
AnnaBridge 171:3a7713b1edbc 2695 #define CAN_TSR_LOW1_Pos (30U)
AnnaBridge 171:3a7713b1edbc 2696 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2697 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
AnnaBridge 171:3a7713b1edbc 2698 #define CAN_TSR_LOW2_Pos (31U)
AnnaBridge 171:3a7713b1edbc 2699 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2700 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
AnnaBridge 171:3a7713b1edbc 2701
AnnaBridge 171:3a7713b1edbc 2702 /******************* Bit definition for CAN_RF0R register *******************/
AnnaBridge 171:3a7713b1edbc 2703 #define CAN_RF0R_FMP0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2704 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 2705 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
AnnaBridge 171:3a7713b1edbc 2706 #define CAN_RF0R_FULL0_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2707 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2708 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
AnnaBridge 171:3a7713b1edbc 2709 #define CAN_RF0R_FOVR0_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2710 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2711 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
AnnaBridge 171:3a7713b1edbc 2712 #define CAN_RF0R_RFOM0_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2713 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2714 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
AnnaBridge 171:3a7713b1edbc 2715
AnnaBridge 171:3a7713b1edbc 2716 /******************* Bit definition for CAN_RF1R register *******************/
AnnaBridge 171:3a7713b1edbc 2717 #define CAN_RF1R_FMP1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2718 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 2719 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
AnnaBridge 171:3a7713b1edbc 2720 #define CAN_RF1R_FULL1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2721 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2722 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
AnnaBridge 171:3a7713b1edbc 2723 #define CAN_RF1R_FOVR1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2724 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2725 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
AnnaBridge 171:3a7713b1edbc 2726 #define CAN_RF1R_RFOM1_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2727 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2728 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
AnnaBridge 171:3a7713b1edbc 2729
AnnaBridge 171:3a7713b1edbc 2730 /******************** Bit definition for CAN_IER register *******************/
AnnaBridge 171:3a7713b1edbc 2731 #define CAN_IER_TMEIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2732 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2733 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2734 #define CAN_IER_FMPIE0_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2735 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2736 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2737 #define CAN_IER_FFIE0_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2738 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2739 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2740 #define CAN_IER_FOVIE0_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2741 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2742 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2743 #define CAN_IER_FMPIE1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2744 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2745 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2746 #define CAN_IER_FFIE1_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2747 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2748 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2749 #define CAN_IER_FOVIE1_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2750 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2751 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2752 #define CAN_IER_EWGIE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2753 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2754 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2755 #define CAN_IER_EPVIE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2756 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2757 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2758 #define CAN_IER_BOFIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2759 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2760 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2761 #define CAN_IER_LECIE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2762 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2763 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2764 #define CAN_IER_ERRIE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2765 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2766 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2767 #define CAN_IER_WKUIE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2768 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2769 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2770 #define CAN_IER_SLKIE_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2771 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2772 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2773
AnnaBridge 171:3a7713b1edbc 2774 /******************** Bit definition for CAN_ESR register *******************/
AnnaBridge 171:3a7713b1edbc 2775 #define CAN_ESR_EWGF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2776 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2777 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
AnnaBridge 171:3a7713b1edbc 2778 #define CAN_ESR_EPVF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2779 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2780 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
AnnaBridge 171:3a7713b1edbc 2781 #define CAN_ESR_BOFF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2782 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2783 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
AnnaBridge 171:3a7713b1edbc 2784
AnnaBridge 171:3a7713b1edbc 2785 #define CAN_ESR_LEC_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2786 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 2787 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
AnnaBridge 171:3a7713b1edbc 2788 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2789 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2790 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2791
AnnaBridge 171:3a7713b1edbc 2792 #define CAN_ESR_TEC_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2793 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2794 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
AnnaBridge 171:3a7713b1edbc 2795 #define CAN_ESR_REC_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2796 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2797 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
AnnaBridge 171:3a7713b1edbc 2798
AnnaBridge 171:3a7713b1edbc 2799 /******************* Bit definition for CAN_BTR register ********************/
AnnaBridge 171:3a7713b1edbc 2800 #define CAN_BTR_BRP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2801 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 2802 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
AnnaBridge 171:3a7713b1edbc 2803 #define CAN_BTR_TS1_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2804 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 2805 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
AnnaBridge 171:3a7713b1edbc 2806 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2807 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2808 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2809 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2810 #define CAN_BTR_TS2_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2811 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
AnnaBridge 171:3a7713b1edbc 2812 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
AnnaBridge 171:3a7713b1edbc 2813 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2814 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2815 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2816 #define CAN_BTR_SJW_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2817 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 2818 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
AnnaBridge 171:3a7713b1edbc 2819 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2820 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 2821 #define CAN_BTR_LBKM_Pos (30U)
AnnaBridge 171:3a7713b1edbc 2822 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2823 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
AnnaBridge 171:3a7713b1edbc 2824 #define CAN_BTR_SILM_Pos (31U)
AnnaBridge 171:3a7713b1edbc 2825 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2826 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
AnnaBridge 171:3a7713b1edbc 2827
AnnaBridge 171:3a7713b1edbc 2828 /*!<Mailbox registers */
AnnaBridge 171:3a7713b1edbc 2829 /****************** Bit definition for CAN_TI0R register ********************/
AnnaBridge 171:3a7713b1edbc 2830 #define CAN_TI0R_TXRQ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2831 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2832 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
AnnaBridge 171:3a7713b1edbc 2833 #define CAN_TI0R_RTR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2834 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2835 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 171:3a7713b1edbc 2836 #define CAN_TI0R_IDE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2837 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2838 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 171:3a7713b1edbc 2839 #define CAN_TI0R_EXID_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2840 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 171:3a7713b1edbc 2841 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
AnnaBridge 171:3a7713b1edbc 2842 #define CAN_TI0R_STID_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2843 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 171:3a7713b1edbc 2844 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 171:3a7713b1edbc 2845
AnnaBridge 171:3a7713b1edbc 2846 /****************** Bit definition for CAN_TDT0R register *******************/
AnnaBridge 171:3a7713b1edbc 2847 #define CAN_TDT0R_DLC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2848 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 2849 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
AnnaBridge 171:3a7713b1edbc 2850 #define CAN_TDT0R_TGT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2851 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2852 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
AnnaBridge 171:3a7713b1edbc 2853 #define CAN_TDT0R_TIME_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2854 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 2855 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 171:3a7713b1edbc 2856
AnnaBridge 171:3a7713b1edbc 2857 /****************** Bit definition for CAN_TDL0R register *******************/
AnnaBridge 171:3a7713b1edbc 2858 #define CAN_TDL0R_DATA0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2859 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2860 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 171:3a7713b1edbc 2861 #define CAN_TDL0R_DATA1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2862 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2863 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 171:3a7713b1edbc 2864 #define CAN_TDL0R_DATA2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2865 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2866 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 171:3a7713b1edbc 2867 #define CAN_TDL0R_DATA3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2868 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2869 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 171:3a7713b1edbc 2870
AnnaBridge 171:3a7713b1edbc 2871 /****************** Bit definition for CAN_TDH0R register *******************/
AnnaBridge 171:3a7713b1edbc 2872 #define CAN_TDH0R_DATA4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2873 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2874 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 171:3a7713b1edbc 2875 #define CAN_TDH0R_DATA5_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2876 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2877 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 171:3a7713b1edbc 2878 #define CAN_TDH0R_DATA6_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2879 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2880 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 171:3a7713b1edbc 2881 #define CAN_TDH0R_DATA7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2882 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2883 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 171:3a7713b1edbc 2884
AnnaBridge 171:3a7713b1edbc 2885 /******************* Bit definition for CAN_TI1R register *******************/
AnnaBridge 171:3a7713b1edbc 2886 #define CAN_TI1R_TXRQ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2887 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2888 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
AnnaBridge 171:3a7713b1edbc 2889 #define CAN_TI1R_RTR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2890 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2891 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 171:3a7713b1edbc 2892 #define CAN_TI1R_IDE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2893 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2894 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 171:3a7713b1edbc 2895 #define CAN_TI1R_EXID_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2896 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 171:3a7713b1edbc 2897 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
AnnaBridge 171:3a7713b1edbc 2898 #define CAN_TI1R_STID_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2899 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 171:3a7713b1edbc 2900 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 171:3a7713b1edbc 2901
AnnaBridge 171:3a7713b1edbc 2902 /******************* Bit definition for CAN_TDT1R register ******************/
AnnaBridge 171:3a7713b1edbc 2903 #define CAN_TDT1R_DLC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2904 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 2905 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
AnnaBridge 171:3a7713b1edbc 2906 #define CAN_TDT1R_TGT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2907 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2908 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
AnnaBridge 171:3a7713b1edbc 2909 #define CAN_TDT1R_TIME_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2910 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 2911 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 171:3a7713b1edbc 2912
AnnaBridge 171:3a7713b1edbc 2913 /******************* Bit definition for CAN_TDL1R register ******************/
AnnaBridge 171:3a7713b1edbc 2914 #define CAN_TDL1R_DATA0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2915 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2916 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 171:3a7713b1edbc 2917 #define CAN_TDL1R_DATA1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2918 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2919 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 171:3a7713b1edbc 2920 #define CAN_TDL1R_DATA2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2921 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2922 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 171:3a7713b1edbc 2923 #define CAN_TDL1R_DATA3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2924 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2925 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 171:3a7713b1edbc 2926
AnnaBridge 171:3a7713b1edbc 2927 /******************* Bit definition for CAN_TDH1R register ******************/
AnnaBridge 171:3a7713b1edbc 2928 #define CAN_TDH1R_DATA4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2929 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2930 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 171:3a7713b1edbc 2931 #define CAN_TDH1R_DATA5_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2932 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2933 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 171:3a7713b1edbc 2934 #define CAN_TDH1R_DATA6_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2935 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2936 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 171:3a7713b1edbc 2937 #define CAN_TDH1R_DATA7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2938 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2939 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 171:3a7713b1edbc 2940
AnnaBridge 171:3a7713b1edbc 2941 /******************* Bit definition for CAN_TI2R register *******************/
AnnaBridge 171:3a7713b1edbc 2942 #define CAN_TI2R_TXRQ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2943 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2944 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
AnnaBridge 171:3a7713b1edbc 2945 #define CAN_TI2R_RTR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2946 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2947 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 171:3a7713b1edbc 2948 #define CAN_TI2R_IDE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2949 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2950 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 171:3a7713b1edbc 2951 #define CAN_TI2R_EXID_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2952 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 171:3a7713b1edbc 2953 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
AnnaBridge 171:3a7713b1edbc 2954 #define CAN_TI2R_STID_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2955 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 171:3a7713b1edbc 2956 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 171:3a7713b1edbc 2957
AnnaBridge 171:3a7713b1edbc 2958 /******************* Bit definition for CAN_TDT2R register ******************/
AnnaBridge 171:3a7713b1edbc 2959 #define CAN_TDT2R_DLC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2960 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 2961 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
AnnaBridge 171:3a7713b1edbc 2962 #define CAN_TDT2R_TGT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2963 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2964 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
AnnaBridge 171:3a7713b1edbc 2965 #define CAN_TDT2R_TIME_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2966 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 2967 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 171:3a7713b1edbc 2968
AnnaBridge 171:3a7713b1edbc 2969 /******************* Bit definition for CAN_TDL2R register ******************/
AnnaBridge 171:3a7713b1edbc 2970 #define CAN_TDL2R_DATA0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2971 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2972 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 171:3a7713b1edbc 2973 #define CAN_TDL2R_DATA1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2974 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2975 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 171:3a7713b1edbc 2976 #define CAN_TDL2R_DATA2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2977 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2978 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 171:3a7713b1edbc 2979 #define CAN_TDL2R_DATA3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2980 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2981 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 171:3a7713b1edbc 2982
AnnaBridge 171:3a7713b1edbc 2983 /******************* Bit definition for CAN_TDH2R register ******************/
AnnaBridge 171:3a7713b1edbc 2984 #define CAN_TDH2R_DATA4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2985 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2986 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 171:3a7713b1edbc 2987 #define CAN_TDH2R_DATA5_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2988 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2989 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 171:3a7713b1edbc 2990 #define CAN_TDH2R_DATA6_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2991 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2992 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 171:3a7713b1edbc 2993 #define CAN_TDH2R_DATA7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2994 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 2995 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 171:3a7713b1edbc 2996
AnnaBridge 171:3a7713b1edbc 2997 /******************* Bit definition for CAN_RI0R register *******************/
AnnaBridge 171:3a7713b1edbc 2998 #define CAN_RI0R_RTR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2999 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3000 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 171:3a7713b1edbc 3001 #define CAN_RI0R_IDE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3002 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3003 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 171:3a7713b1edbc 3004 #define CAN_RI0R_EXID_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3005 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 171:3a7713b1edbc 3006 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
AnnaBridge 171:3a7713b1edbc 3007 #define CAN_RI0R_STID_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3008 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 171:3a7713b1edbc 3009 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 171:3a7713b1edbc 3010
AnnaBridge 171:3a7713b1edbc 3011 /******************* Bit definition for CAN_RDT0R register ******************/
AnnaBridge 171:3a7713b1edbc 3012 #define CAN_RDT0R_DLC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3013 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 3014 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
AnnaBridge 171:3a7713b1edbc 3015 #define CAN_RDT0R_FMI_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3016 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 3017 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
AnnaBridge 171:3a7713b1edbc 3018 #define CAN_RDT0R_TIME_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3019 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 3020 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 171:3a7713b1edbc 3021
AnnaBridge 171:3a7713b1edbc 3022 /******************* Bit definition for CAN_RDL0R register ******************/
AnnaBridge 171:3a7713b1edbc 3023 #define CAN_RDL0R_DATA0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3024 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 3025 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 171:3a7713b1edbc 3026 #define CAN_RDL0R_DATA1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3027 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 3028 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 171:3a7713b1edbc 3029 #define CAN_RDL0R_DATA2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3030 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 3031 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 171:3a7713b1edbc 3032 #define CAN_RDL0R_DATA3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3033 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 3034 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 171:3a7713b1edbc 3035
AnnaBridge 171:3a7713b1edbc 3036 /******************* Bit definition for CAN_RDH0R register ******************/
AnnaBridge 171:3a7713b1edbc 3037 #define CAN_RDH0R_DATA4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3038 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 3039 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 171:3a7713b1edbc 3040 #define CAN_RDH0R_DATA5_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3041 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 3042 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 171:3a7713b1edbc 3043 #define CAN_RDH0R_DATA6_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3044 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 3045 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 171:3a7713b1edbc 3046 #define CAN_RDH0R_DATA7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3047 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 3048 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 171:3a7713b1edbc 3049
AnnaBridge 171:3a7713b1edbc 3050 /******************* Bit definition for CAN_RI1R register *******************/
AnnaBridge 171:3a7713b1edbc 3051 #define CAN_RI1R_RTR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3052 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3053 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 171:3a7713b1edbc 3054 #define CAN_RI1R_IDE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3055 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3056 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 171:3a7713b1edbc 3057 #define CAN_RI1R_EXID_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3058 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 171:3a7713b1edbc 3059 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
AnnaBridge 171:3a7713b1edbc 3060 #define CAN_RI1R_STID_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3061 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 171:3a7713b1edbc 3062 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 171:3a7713b1edbc 3063
AnnaBridge 171:3a7713b1edbc 3064 /******************* Bit definition for CAN_RDT1R register ******************/
AnnaBridge 171:3a7713b1edbc 3065 #define CAN_RDT1R_DLC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3066 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 3067 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
AnnaBridge 171:3a7713b1edbc 3068 #define CAN_RDT1R_FMI_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3069 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 3070 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
AnnaBridge 171:3a7713b1edbc 3071 #define CAN_RDT1R_TIME_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3072 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 3073 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 171:3a7713b1edbc 3074
AnnaBridge 171:3a7713b1edbc 3075 /******************* Bit definition for CAN_RDL1R register ******************/
AnnaBridge 171:3a7713b1edbc 3076 #define CAN_RDL1R_DATA0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3077 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 3078 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 171:3a7713b1edbc 3079 #define CAN_RDL1R_DATA1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3080 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 3081 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 171:3a7713b1edbc 3082 #define CAN_RDL1R_DATA2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3083 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 3084 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 171:3a7713b1edbc 3085 #define CAN_RDL1R_DATA3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3086 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 3087 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 171:3a7713b1edbc 3088
AnnaBridge 171:3a7713b1edbc 3089 /******************* Bit definition for CAN_RDH1R register ******************/
AnnaBridge 171:3a7713b1edbc 3090 #define CAN_RDH1R_DATA4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3091 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 3092 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 171:3a7713b1edbc 3093 #define CAN_RDH1R_DATA5_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3094 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 3095 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 171:3a7713b1edbc 3096 #define CAN_RDH1R_DATA6_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3097 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 3098 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 171:3a7713b1edbc 3099 #define CAN_RDH1R_DATA7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3100 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 3101 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 171:3a7713b1edbc 3102
AnnaBridge 171:3a7713b1edbc 3103 /*!<CAN filter registers */
AnnaBridge 171:3a7713b1edbc 3104 /******************* Bit definition for CAN_FMR register ********************/
AnnaBridge 171:3a7713b1edbc 3105 #define CAN_FMR_FINIT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3106 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3107 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
AnnaBridge 171:3a7713b1edbc 3108
AnnaBridge 171:3a7713b1edbc 3109 /******************* Bit definition for CAN_FM1R register *******************/
AnnaBridge 171:3a7713b1edbc 3110 #define CAN_FM1R_FBM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3111 #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
AnnaBridge 171:3a7713b1edbc 3112 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
AnnaBridge 171:3a7713b1edbc 3113 #define CAN_FM1R_FBM0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3114 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3115 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
AnnaBridge 171:3a7713b1edbc 3116 #define CAN_FM1R_FBM1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3117 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3118 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
AnnaBridge 171:3a7713b1edbc 3119 #define CAN_FM1R_FBM2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3120 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3121 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
AnnaBridge 171:3a7713b1edbc 3122 #define CAN_FM1R_FBM3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3123 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3124 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
AnnaBridge 171:3a7713b1edbc 3125 #define CAN_FM1R_FBM4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3126 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3127 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
AnnaBridge 171:3a7713b1edbc 3128 #define CAN_FM1R_FBM5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3129 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3130 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
AnnaBridge 171:3a7713b1edbc 3131 #define CAN_FM1R_FBM6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3132 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3133 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
AnnaBridge 171:3a7713b1edbc 3134 #define CAN_FM1R_FBM7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3135 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3136 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
AnnaBridge 171:3a7713b1edbc 3137 #define CAN_FM1R_FBM8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3138 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3139 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
AnnaBridge 171:3a7713b1edbc 3140 #define CAN_FM1R_FBM9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3141 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3142 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
AnnaBridge 171:3a7713b1edbc 3143 #define CAN_FM1R_FBM10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3144 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3145 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
AnnaBridge 171:3a7713b1edbc 3146 #define CAN_FM1R_FBM11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3147 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3148 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
AnnaBridge 171:3a7713b1edbc 3149 #define CAN_FM1R_FBM12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3150 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3151 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
AnnaBridge 171:3a7713b1edbc 3152 #define CAN_FM1R_FBM13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3153 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3154 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
AnnaBridge 171:3a7713b1edbc 3155
AnnaBridge 171:3a7713b1edbc 3156 /******************* Bit definition for CAN_FS1R register *******************/
AnnaBridge 171:3a7713b1edbc 3157 #define CAN_FS1R_FSC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3158 #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
AnnaBridge 171:3a7713b1edbc 3159 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
AnnaBridge 171:3a7713b1edbc 3160 #define CAN_FS1R_FSC0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3161 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3162 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
AnnaBridge 171:3a7713b1edbc 3163 #define CAN_FS1R_FSC1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3164 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3165 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
AnnaBridge 171:3a7713b1edbc 3166 #define CAN_FS1R_FSC2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3167 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3168 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
AnnaBridge 171:3a7713b1edbc 3169 #define CAN_FS1R_FSC3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3170 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3171 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
AnnaBridge 171:3a7713b1edbc 3172 #define CAN_FS1R_FSC4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3173 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3174 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
AnnaBridge 171:3a7713b1edbc 3175 #define CAN_FS1R_FSC5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3176 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3177 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
AnnaBridge 171:3a7713b1edbc 3178 #define CAN_FS1R_FSC6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3179 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3180 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
AnnaBridge 171:3a7713b1edbc 3181 #define CAN_FS1R_FSC7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3182 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3183 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
AnnaBridge 171:3a7713b1edbc 3184 #define CAN_FS1R_FSC8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3185 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3186 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
AnnaBridge 171:3a7713b1edbc 3187 #define CAN_FS1R_FSC9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3188 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3189 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
AnnaBridge 171:3a7713b1edbc 3190 #define CAN_FS1R_FSC10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3191 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3192 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
AnnaBridge 171:3a7713b1edbc 3193 #define CAN_FS1R_FSC11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3194 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3195 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
AnnaBridge 171:3a7713b1edbc 3196 #define CAN_FS1R_FSC12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3197 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3198 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
AnnaBridge 171:3a7713b1edbc 3199 #define CAN_FS1R_FSC13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3200 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3201 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
AnnaBridge 171:3a7713b1edbc 3202
AnnaBridge 171:3a7713b1edbc 3203 /****************** Bit definition for CAN_FFA1R register *******************/
AnnaBridge 171:3a7713b1edbc 3204 #define CAN_FFA1R_FFA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3205 #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
AnnaBridge 171:3a7713b1edbc 3206 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
AnnaBridge 171:3a7713b1edbc 3207 #define CAN_FFA1R_FFA0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3208 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3209 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
AnnaBridge 171:3a7713b1edbc 3210 #define CAN_FFA1R_FFA1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3211 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3212 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
AnnaBridge 171:3a7713b1edbc 3213 #define CAN_FFA1R_FFA2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3214 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3215 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
AnnaBridge 171:3a7713b1edbc 3216 #define CAN_FFA1R_FFA3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3217 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3218 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
AnnaBridge 171:3a7713b1edbc 3219 #define CAN_FFA1R_FFA4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3220 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3221 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
AnnaBridge 171:3a7713b1edbc 3222 #define CAN_FFA1R_FFA5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3223 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3224 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
AnnaBridge 171:3a7713b1edbc 3225 #define CAN_FFA1R_FFA6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3226 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3227 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
AnnaBridge 171:3a7713b1edbc 3228 #define CAN_FFA1R_FFA7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3229 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3230 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
AnnaBridge 171:3a7713b1edbc 3231 #define CAN_FFA1R_FFA8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3232 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3233 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
AnnaBridge 171:3a7713b1edbc 3234 #define CAN_FFA1R_FFA9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3235 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3236 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
AnnaBridge 171:3a7713b1edbc 3237 #define CAN_FFA1R_FFA10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3238 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3239 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
AnnaBridge 171:3a7713b1edbc 3240 #define CAN_FFA1R_FFA11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3241 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3242 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
AnnaBridge 171:3a7713b1edbc 3243 #define CAN_FFA1R_FFA12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3244 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3245 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
AnnaBridge 171:3a7713b1edbc 3246 #define CAN_FFA1R_FFA13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3247 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3248 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
AnnaBridge 171:3a7713b1edbc 3249
AnnaBridge 171:3a7713b1edbc 3250 /******************* Bit definition for CAN_FA1R register *******************/
AnnaBridge 171:3a7713b1edbc 3251 #define CAN_FA1R_FACT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3252 #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
AnnaBridge 171:3a7713b1edbc 3253 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
AnnaBridge 171:3a7713b1edbc 3254 #define CAN_FA1R_FACT0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3255 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3256 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
AnnaBridge 171:3a7713b1edbc 3257 #define CAN_FA1R_FACT1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3258 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3259 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
AnnaBridge 171:3a7713b1edbc 3260 #define CAN_FA1R_FACT2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3261 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3262 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
AnnaBridge 171:3a7713b1edbc 3263 #define CAN_FA1R_FACT3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3264 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3265 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
AnnaBridge 171:3a7713b1edbc 3266 #define CAN_FA1R_FACT4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3267 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3268 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
AnnaBridge 171:3a7713b1edbc 3269 #define CAN_FA1R_FACT5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3270 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3271 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
AnnaBridge 171:3a7713b1edbc 3272 #define CAN_FA1R_FACT6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3273 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3274 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
AnnaBridge 171:3a7713b1edbc 3275 #define CAN_FA1R_FACT7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3276 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3277 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
AnnaBridge 171:3a7713b1edbc 3278 #define CAN_FA1R_FACT8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3279 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3280 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
AnnaBridge 171:3a7713b1edbc 3281 #define CAN_FA1R_FACT9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3282 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3283 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
AnnaBridge 171:3a7713b1edbc 3284 #define CAN_FA1R_FACT10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3285 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3286 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
AnnaBridge 171:3a7713b1edbc 3287 #define CAN_FA1R_FACT11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3288 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3289 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
AnnaBridge 171:3a7713b1edbc 3290 #define CAN_FA1R_FACT12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3291 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3292 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
AnnaBridge 171:3a7713b1edbc 3293 #define CAN_FA1R_FACT13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3294 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3295 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
AnnaBridge 171:3a7713b1edbc 3296
AnnaBridge 171:3a7713b1edbc 3297 /******************* Bit definition for CAN_F0R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3298 #define CAN_F0R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3299 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3300 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3301 #define CAN_F0R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3302 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3303 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3304 #define CAN_F0R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3305 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3306 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3307 #define CAN_F0R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3308 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3309 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3310 #define CAN_F0R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3311 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3312 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3313 #define CAN_F0R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3314 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3315 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3316 #define CAN_F0R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3317 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3318 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3319 #define CAN_F0R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3320 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3321 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3322 #define CAN_F0R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3323 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3324 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3325 #define CAN_F0R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3326 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3327 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3328 #define CAN_F0R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3329 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3330 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3331 #define CAN_F0R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3332 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3333 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3334 #define CAN_F0R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3335 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3336 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3337 #define CAN_F0R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3338 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3339 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3340 #define CAN_F0R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3341 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3342 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3343 #define CAN_F0R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3344 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3345 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3346 #define CAN_F0R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3347 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3348 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3349 #define CAN_F0R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3350 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3351 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3352 #define CAN_F0R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3353 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3354 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3355 #define CAN_F0R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3356 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3357 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3358 #define CAN_F0R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3359 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3360 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3361 #define CAN_F0R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3362 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3363 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3364 #define CAN_F0R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3365 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3366 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3367 #define CAN_F0R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3368 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3369 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3370 #define CAN_F0R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3371 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3372 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3373 #define CAN_F0R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3374 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3375 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3376 #define CAN_F0R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3377 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3378 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3379 #define CAN_F0R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3380 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3381 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3382 #define CAN_F0R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3383 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3384 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3385 #define CAN_F0R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3386 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3387 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3388 #define CAN_F0R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3389 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3390 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3391 #define CAN_F0R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3392 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3393 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3394
AnnaBridge 171:3a7713b1edbc 3395 /******************* Bit definition for CAN_F1R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3396 #define CAN_F1R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3397 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3398 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3399 #define CAN_F1R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3400 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3401 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3402 #define CAN_F1R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3403 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3404 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3405 #define CAN_F1R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3406 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3407 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3408 #define CAN_F1R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3409 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3410 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3411 #define CAN_F1R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3412 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3413 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3414 #define CAN_F1R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3415 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3416 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3417 #define CAN_F1R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3418 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3419 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3420 #define CAN_F1R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3421 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3422 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3423 #define CAN_F1R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3424 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3425 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3426 #define CAN_F1R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3427 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3428 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3429 #define CAN_F1R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3430 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3431 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3432 #define CAN_F1R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3433 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3434 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3435 #define CAN_F1R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3436 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3437 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3438 #define CAN_F1R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3439 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3440 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3441 #define CAN_F1R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3442 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3443 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3444 #define CAN_F1R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3445 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3446 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3447 #define CAN_F1R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3448 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3449 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3450 #define CAN_F1R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3451 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3452 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3453 #define CAN_F1R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3454 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3455 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3456 #define CAN_F1R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3457 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3458 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3459 #define CAN_F1R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3460 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3461 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3462 #define CAN_F1R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3463 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3464 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3465 #define CAN_F1R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3466 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3467 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3468 #define CAN_F1R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3469 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3470 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3471 #define CAN_F1R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3472 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3473 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3474 #define CAN_F1R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3475 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3476 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3477 #define CAN_F1R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3478 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3479 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3480 #define CAN_F1R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3481 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3482 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3483 #define CAN_F1R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3484 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3485 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3486 #define CAN_F1R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3487 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3488 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3489 #define CAN_F1R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3490 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3491 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3492
AnnaBridge 171:3a7713b1edbc 3493 /******************* Bit definition for CAN_F2R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3494 #define CAN_F2R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3495 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3496 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3497 #define CAN_F2R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3498 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3499 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3500 #define CAN_F2R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3501 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3502 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3503 #define CAN_F2R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3504 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3505 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3506 #define CAN_F2R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3507 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3508 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3509 #define CAN_F2R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3510 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3511 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3512 #define CAN_F2R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3513 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3514 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3515 #define CAN_F2R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3516 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3517 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3518 #define CAN_F2R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3519 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3520 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3521 #define CAN_F2R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3522 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3523 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3524 #define CAN_F2R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3525 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3526 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3527 #define CAN_F2R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3528 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3529 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3530 #define CAN_F2R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3531 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3532 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3533 #define CAN_F2R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3534 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3535 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3536 #define CAN_F2R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3537 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3538 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3539 #define CAN_F2R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3540 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3541 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3542 #define CAN_F2R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3543 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3544 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3545 #define CAN_F2R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3546 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3547 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3548 #define CAN_F2R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3549 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3550 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3551 #define CAN_F2R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3552 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3553 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3554 #define CAN_F2R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3555 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3556 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3557 #define CAN_F2R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3558 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3559 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3560 #define CAN_F2R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3561 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3562 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3563 #define CAN_F2R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3564 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3565 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3566 #define CAN_F2R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3567 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3568 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3569 #define CAN_F2R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3570 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3571 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3572 #define CAN_F2R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3573 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3574 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3575 #define CAN_F2R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3576 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3577 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3578 #define CAN_F2R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3579 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3580 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3581 #define CAN_F2R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3582 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3583 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3584 #define CAN_F2R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3585 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3586 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3587 #define CAN_F2R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3588 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3589 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3590
AnnaBridge 171:3a7713b1edbc 3591 /******************* Bit definition for CAN_F3R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3592 #define CAN_F3R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3593 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3594 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3595 #define CAN_F3R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3596 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3597 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3598 #define CAN_F3R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3599 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3600 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3601 #define CAN_F3R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3602 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3603 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3604 #define CAN_F3R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3605 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3606 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3607 #define CAN_F3R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3608 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3609 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3610 #define CAN_F3R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3611 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3612 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3613 #define CAN_F3R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3614 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3615 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3616 #define CAN_F3R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3617 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3618 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3619 #define CAN_F3R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3620 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3621 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3622 #define CAN_F3R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3623 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3624 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3625 #define CAN_F3R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3626 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3627 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3628 #define CAN_F3R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3629 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3630 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3631 #define CAN_F3R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3632 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3633 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3634 #define CAN_F3R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3635 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3636 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3637 #define CAN_F3R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3638 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3639 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3640 #define CAN_F3R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3641 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3642 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3643 #define CAN_F3R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3644 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3645 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3646 #define CAN_F3R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3647 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3648 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3649 #define CAN_F3R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3650 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3651 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3652 #define CAN_F3R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3653 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3654 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3655 #define CAN_F3R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3656 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3657 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3658 #define CAN_F3R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3659 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3660 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3661 #define CAN_F3R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3662 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3663 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3664 #define CAN_F3R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3665 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3666 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3667 #define CAN_F3R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3668 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3669 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3670 #define CAN_F3R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3671 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3672 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3673 #define CAN_F3R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3674 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3675 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3676 #define CAN_F3R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3677 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3678 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3679 #define CAN_F3R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3680 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3681 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3682 #define CAN_F3R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3683 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3684 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3685 #define CAN_F3R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3686 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3687 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3688
AnnaBridge 171:3a7713b1edbc 3689 /******************* Bit definition for CAN_F4R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3690 #define CAN_F4R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3691 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3692 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3693 #define CAN_F4R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3694 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3695 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3696 #define CAN_F4R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3697 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3698 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3699 #define CAN_F4R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3700 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3701 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3702 #define CAN_F4R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3703 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3704 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3705 #define CAN_F4R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3706 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3707 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3708 #define CAN_F4R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3709 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3710 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3711 #define CAN_F4R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3712 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3713 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3714 #define CAN_F4R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3715 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3716 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3717 #define CAN_F4R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3718 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3719 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3720 #define CAN_F4R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3721 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3722 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3723 #define CAN_F4R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3724 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3725 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3726 #define CAN_F4R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3727 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3728 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3729 #define CAN_F4R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3730 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3731 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3732 #define CAN_F4R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3733 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3734 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3735 #define CAN_F4R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3736 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3737 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3738 #define CAN_F4R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3739 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3740 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3741 #define CAN_F4R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3742 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3743 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3744 #define CAN_F4R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3745 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3746 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3747 #define CAN_F4R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3748 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3749 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3750 #define CAN_F4R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3751 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3752 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3753 #define CAN_F4R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3754 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3755 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3756 #define CAN_F4R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3757 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3758 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3759 #define CAN_F4R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3760 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3761 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3762 #define CAN_F4R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3763 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3764 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3765 #define CAN_F4R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3766 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3767 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3768 #define CAN_F4R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3769 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3770 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3771 #define CAN_F4R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3772 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3773 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3774 #define CAN_F4R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3775 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3776 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3777 #define CAN_F4R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3778 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3779 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3780 #define CAN_F4R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3781 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3782 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3783 #define CAN_F4R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3784 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3785 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3786
AnnaBridge 171:3a7713b1edbc 3787 /******************* Bit definition for CAN_F5R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3788 #define CAN_F5R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3789 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3790 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3791 #define CAN_F5R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3792 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3793 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3794 #define CAN_F5R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3795 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3796 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3797 #define CAN_F5R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3798 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3799 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3800 #define CAN_F5R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3801 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3802 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3803 #define CAN_F5R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3804 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3805 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3806 #define CAN_F5R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3807 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3808 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3809 #define CAN_F5R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3810 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3811 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3812 #define CAN_F5R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3813 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3814 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3815 #define CAN_F5R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3816 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3817 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3818 #define CAN_F5R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3819 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3820 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3821 #define CAN_F5R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3822 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3823 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3824 #define CAN_F5R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3825 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3826 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3827 #define CAN_F5R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3828 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3829 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3830 #define CAN_F5R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3831 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3832 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3833 #define CAN_F5R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3834 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3835 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3836 #define CAN_F5R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3837 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3838 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3839 #define CAN_F5R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3840 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3841 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3842 #define CAN_F5R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3843 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3844 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3845 #define CAN_F5R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3846 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3847 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3848 #define CAN_F5R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3849 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3850 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3851 #define CAN_F5R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3852 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3853 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3854 #define CAN_F5R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3855 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3856 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3857 #define CAN_F5R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3858 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3859 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3860 #define CAN_F5R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3861 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3862 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3863 #define CAN_F5R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3864 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3865 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3866 #define CAN_F5R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3867 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3868 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3869 #define CAN_F5R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3870 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3871 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3872 #define CAN_F5R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3873 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3874 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3875 #define CAN_F5R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3876 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3877 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3878 #define CAN_F5R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3879 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3880 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3881 #define CAN_F5R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3882 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3883 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3884
AnnaBridge 171:3a7713b1edbc 3885 /******************* Bit definition for CAN_F6R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3886 #define CAN_F6R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3887 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3888 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3889 #define CAN_F6R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3890 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3891 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3892 #define CAN_F6R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3893 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3894 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3895 #define CAN_F6R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3896 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3897 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3898 #define CAN_F6R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3899 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3900 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3901 #define CAN_F6R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3902 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3903 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 3904 #define CAN_F6R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3905 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3906 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 3907 #define CAN_F6R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3908 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3909 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 3910 #define CAN_F6R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3911 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3912 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 3913 #define CAN_F6R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3914 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3915 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 3916 #define CAN_F6R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3917 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3918 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 3919 #define CAN_F6R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3920 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3921 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 3922 #define CAN_F6R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3923 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3924 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 3925 #define CAN_F6R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3926 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3927 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 3928 #define CAN_F6R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3929 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3930 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 3931 #define CAN_F6R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3932 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3933 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 3934 #define CAN_F6R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3935 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3936 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 3937 #define CAN_F6R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3938 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3939 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 3940 #define CAN_F6R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3941 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3942 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 3943 #define CAN_F6R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3944 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3945 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 3946 #define CAN_F6R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3947 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3948 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 3949 #define CAN_F6R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3950 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3951 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 3952 #define CAN_F6R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3953 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3954 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 3955 #define CAN_F6R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3956 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3957 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 3958 #define CAN_F6R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3959 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3960 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 3961 #define CAN_F6R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3962 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3963 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 3964 #define CAN_F6R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3965 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3966 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 3967 #define CAN_F6R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3968 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3969 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 3970 #define CAN_F6R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3971 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3972 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 3973 #define CAN_F6R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3974 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3975 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 3976 #define CAN_F6R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3977 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3978 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 3979 #define CAN_F6R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3980 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3981 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 3982
AnnaBridge 171:3a7713b1edbc 3983 /******************* Bit definition for CAN_F7R1 register *******************/
AnnaBridge 171:3a7713b1edbc 3984 #define CAN_F7R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3985 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3986 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 3987 #define CAN_F7R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3988 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3989 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 3990 #define CAN_F7R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3991 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3992 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 3993 #define CAN_F7R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3994 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3995 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 3996 #define CAN_F7R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3997 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3998 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 3999 #define CAN_F7R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4000 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4001 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4002 #define CAN_F7R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4003 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4004 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4005 #define CAN_F7R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4006 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4007 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4008 #define CAN_F7R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4009 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4010 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4011 #define CAN_F7R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4012 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4013 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4014 #define CAN_F7R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4015 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4016 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4017 #define CAN_F7R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4018 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4019 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4020 #define CAN_F7R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4021 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4022 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4023 #define CAN_F7R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4024 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4025 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4026 #define CAN_F7R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4027 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4028 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4029 #define CAN_F7R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4030 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4031 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4032 #define CAN_F7R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4033 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4034 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4035 #define CAN_F7R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4036 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4037 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4038 #define CAN_F7R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4039 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4040 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4041 #define CAN_F7R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4042 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4043 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4044 #define CAN_F7R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4045 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4046 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4047 #define CAN_F7R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4048 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4049 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4050 #define CAN_F7R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4051 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4052 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4053 #define CAN_F7R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4054 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4055 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4056 #define CAN_F7R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4057 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4058 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4059 #define CAN_F7R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4060 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4061 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4062 #define CAN_F7R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4063 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4064 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4065 #define CAN_F7R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4066 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4067 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4068 #define CAN_F7R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4069 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4070 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4071 #define CAN_F7R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4072 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4073 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4074 #define CAN_F7R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4075 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4076 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4077 #define CAN_F7R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4078 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4079 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4080
AnnaBridge 171:3a7713b1edbc 4081 /******************* Bit definition for CAN_F8R1 register *******************/
AnnaBridge 171:3a7713b1edbc 4082 #define CAN_F8R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4083 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4084 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4085 #define CAN_F8R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4086 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4087 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4088 #define CAN_F8R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4089 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4090 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4091 #define CAN_F8R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4092 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4093 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4094 #define CAN_F8R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4095 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4096 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4097 #define CAN_F8R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4098 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4099 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4100 #define CAN_F8R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4101 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4102 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4103 #define CAN_F8R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4104 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4105 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4106 #define CAN_F8R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4107 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4108 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4109 #define CAN_F8R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4110 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4111 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4112 #define CAN_F8R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4113 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4114 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4115 #define CAN_F8R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4116 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4117 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4118 #define CAN_F8R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4119 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4120 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4121 #define CAN_F8R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4122 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4123 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4124 #define CAN_F8R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4125 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4126 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4127 #define CAN_F8R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4128 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4129 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4130 #define CAN_F8R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4131 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4132 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4133 #define CAN_F8R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4134 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4135 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4136 #define CAN_F8R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4137 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4138 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4139 #define CAN_F8R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4140 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4141 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4142 #define CAN_F8R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4143 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4144 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4145 #define CAN_F8R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4146 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4147 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4148 #define CAN_F8R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4149 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4150 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4151 #define CAN_F8R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4152 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4153 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4154 #define CAN_F8R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4155 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4156 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4157 #define CAN_F8R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4158 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4159 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4160 #define CAN_F8R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4161 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4162 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4163 #define CAN_F8R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4164 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4165 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4166 #define CAN_F8R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4167 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4168 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4169 #define CAN_F8R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4170 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4171 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4172 #define CAN_F8R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4173 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4174 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4175 #define CAN_F8R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4176 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4177 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4178
AnnaBridge 171:3a7713b1edbc 4179 /******************* Bit definition for CAN_F9R1 register *******************/
AnnaBridge 171:3a7713b1edbc 4180 #define CAN_F9R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4181 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4182 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4183 #define CAN_F9R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4184 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4185 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4186 #define CAN_F9R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4187 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4188 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4189 #define CAN_F9R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4190 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4191 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4192 #define CAN_F9R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4193 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4194 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4195 #define CAN_F9R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4196 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4197 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4198 #define CAN_F9R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4199 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4200 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4201 #define CAN_F9R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4202 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4203 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4204 #define CAN_F9R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4205 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4206 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4207 #define CAN_F9R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4208 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4209 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4210 #define CAN_F9R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4211 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4212 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4213 #define CAN_F9R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4214 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4215 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4216 #define CAN_F9R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4217 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4218 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4219 #define CAN_F9R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4220 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4221 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4222 #define CAN_F9R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4223 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4224 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4225 #define CAN_F9R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4226 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4227 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4228 #define CAN_F9R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4229 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4230 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4231 #define CAN_F9R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4232 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4233 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4234 #define CAN_F9R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4235 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4236 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4237 #define CAN_F9R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4238 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4239 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4240 #define CAN_F9R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4241 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4242 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4243 #define CAN_F9R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4244 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4245 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4246 #define CAN_F9R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4247 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4248 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4249 #define CAN_F9R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4250 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4251 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4252 #define CAN_F9R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4253 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4254 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4255 #define CAN_F9R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4256 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4257 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4258 #define CAN_F9R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4259 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4260 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4261 #define CAN_F9R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4262 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4263 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4264 #define CAN_F9R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4265 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4266 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4267 #define CAN_F9R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4268 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4269 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4270 #define CAN_F9R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4271 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4272 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4273 #define CAN_F9R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4274 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4275 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4276
AnnaBridge 171:3a7713b1edbc 4277 /******************* Bit definition for CAN_F10R1 register ******************/
AnnaBridge 171:3a7713b1edbc 4278 #define CAN_F10R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4279 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4280 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4281 #define CAN_F10R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4282 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4283 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4284 #define CAN_F10R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4285 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4286 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4287 #define CAN_F10R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4288 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4289 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4290 #define CAN_F10R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4291 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4292 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4293 #define CAN_F10R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4294 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4295 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4296 #define CAN_F10R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4297 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4298 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4299 #define CAN_F10R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4300 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4301 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4302 #define CAN_F10R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4303 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4304 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4305 #define CAN_F10R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4306 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4307 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4308 #define CAN_F10R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4309 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4310 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4311 #define CAN_F10R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4312 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4313 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4314 #define CAN_F10R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4315 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4316 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4317 #define CAN_F10R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4318 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4319 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4320 #define CAN_F10R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4321 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4322 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4323 #define CAN_F10R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4324 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4325 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4326 #define CAN_F10R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4327 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4328 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4329 #define CAN_F10R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4330 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4331 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4332 #define CAN_F10R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4333 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4334 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4335 #define CAN_F10R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4336 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4337 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4338 #define CAN_F10R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4339 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4340 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4341 #define CAN_F10R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4342 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4343 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4344 #define CAN_F10R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4345 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4346 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4347 #define CAN_F10R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4348 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4349 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4350 #define CAN_F10R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4351 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4352 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4353 #define CAN_F10R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4354 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4355 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4356 #define CAN_F10R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4357 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4358 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4359 #define CAN_F10R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4360 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4361 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4362 #define CAN_F10R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4363 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4364 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4365 #define CAN_F10R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4366 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4367 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4368 #define CAN_F10R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4369 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4370 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4371 #define CAN_F10R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4372 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4373 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4374
AnnaBridge 171:3a7713b1edbc 4375 /******************* Bit definition for CAN_F11R1 register ******************/
AnnaBridge 171:3a7713b1edbc 4376 #define CAN_F11R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4377 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4378 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4379 #define CAN_F11R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4380 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4381 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4382 #define CAN_F11R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4383 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4384 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4385 #define CAN_F11R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4386 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4387 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4388 #define CAN_F11R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4389 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4390 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4391 #define CAN_F11R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4392 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4393 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4394 #define CAN_F11R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4395 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4396 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4397 #define CAN_F11R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4398 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4399 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4400 #define CAN_F11R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4401 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4402 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4403 #define CAN_F11R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4404 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4405 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4406 #define CAN_F11R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4407 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4408 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4409 #define CAN_F11R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4410 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4411 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4412 #define CAN_F11R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4413 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4414 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4415 #define CAN_F11R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4416 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4417 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4418 #define CAN_F11R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4419 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4420 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4421 #define CAN_F11R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4422 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4423 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4424 #define CAN_F11R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4425 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4426 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4427 #define CAN_F11R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4428 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4429 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4430 #define CAN_F11R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4431 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4432 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4433 #define CAN_F11R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4434 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4435 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4436 #define CAN_F11R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4437 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4438 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4439 #define CAN_F11R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4440 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4441 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4442 #define CAN_F11R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4443 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4444 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4445 #define CAN_F11R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4446 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4447 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4448 #define CAN_F11R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4449 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4450 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4451 #define CAN_F11R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4452 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4453 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4454 #define CAN_F11R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4455 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4456 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4457 #define CAN_F11R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4458 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4459 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4460 #define CAN_F11R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4461 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4462 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4463 #define CAN_F11R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4464 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4465 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4466 #define CAN_F11R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4467 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4468 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4469 #define CAN_F11R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4470 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4471 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4472
AnnaBridge 171:3a7713b1edbc 4473 /******************* Bit definition for CAN_F12R1 register ******************/
AnnaBridge 171:3a7713b1edbc 4474 #define CAN_F12R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4475 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4476 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4477 #define CAN_F12R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4478 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4479 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4480 #define CAN_F12R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4481 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4482 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4483 #define CAN_F12R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4484 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4485 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4486 #define CAN_F12R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4487 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4488 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4489 #define CAN_F12R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4490 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4491 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4492 #define CAN_F12R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4493 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4494 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4495 #define CAN_F12R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4496 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4497 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4498 #define CAN_F12R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4499 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4500 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4501 #define CAN_F12R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4502 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4503 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4504 #define CAN_F12R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4505 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4506 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4507 #define CAN_F12R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4508 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4509 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4510 #define CAN_F12R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4511 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4512 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4513 #define CAN_F12R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4514 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4515 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4516 #define CAN_F12R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4517 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4518 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4519 #define CAN_F12R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4520 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4521 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4522 #define CAN_F12R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4523 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4524 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4525 #define CAN_F12R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4526 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4527 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4528 #define CAN_F12R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4529 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4530 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4531 #define CAN_F12R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4532 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4533 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4534 #define CAN_F12R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4535 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4536 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4537 #define CAN_F12R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4538 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4539 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4540 #define CAN_F12R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4541 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4542 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4543 #define CAN_F12R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4544 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4545 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4546 #define CAN_F12R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4547 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4548 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4549 #define CAN_F12R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4550 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4551 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4552 #define CAN_F12R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4553 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4554 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4555 #define CAN_F12R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4556 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4557 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4558 #define CAN_F12R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4559 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4560 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4561 #define CAN_F12R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4562 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4563 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4564 #define CAN_F12R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4565 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4566 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4567 #define CAN_F12R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4568 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4569 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4570
AnnaBridge 171:3a7713b1edbc 4571 /******************* Bit definition for CAN_F13R1 register ******************/
AnnaBridge 171:3a7713b1edbc 4572 #define CAN_F13R1_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4573 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4574 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4575 #define CAN_F13R1_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4576 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4577 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4578 #define CAN_F13R1_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4579 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4580 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4581 #define CAN_F13R1_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4582 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4583 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4584 #define CAN_F13R1_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4585 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4586 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4587 #define CAN_F13R1_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4588 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4589 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4590 #define CAN_F13R1_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4591 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4592 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4593 #define CAN_F13R1_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4594 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4595 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4596 #define CAN_F13R1_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4597 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4598 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4599 #define CAN_F13R1_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4600 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4601 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4602 #define CAN_F13R1_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4603 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4604 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4605 #define CAN_F13R1_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4606 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4607 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4608 #define CAN_F13R1_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4609 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4610 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4611 #define CAN_F13R1_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4612 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4613 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4614 #define CAN_F13R1_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4615 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4616 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4617 #define CAN_F13R1_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4618 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4619 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4620 #define CAN_F13R1_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4621 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4622 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4623 #define CAN_F13R1_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4624 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4625 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4626 #define CAN_F13R1_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4627 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4628 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4629 #define CAN_F13R1_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4630 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4631 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4632 #define CAN_F13R1_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4633 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4634 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4635 #define CAN_F13R1_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4636 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4637 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4638 #define CAN_F13R1_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4639 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4640 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4641 #define CAN_F13R1_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4642 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4643 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4644 #define CAN_F13R1_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4645 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4646 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4647 #define CAN_F13R1_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4648 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4649 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4650 #define CAN_F13R1_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4651 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4652 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4653 #define CAN_F13R1_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4654 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4655 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4656 #define CAN_F13R1_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4657 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4658 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4659 #define CAN_F13R1_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4660 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4661 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4662 #define CAN_F13R1_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4663 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4664 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4665 #define CAN_F13R1_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4666 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4667 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4668
AnnaBridge 171:3a7713b1edbc 4669 /******************* Bit definition for CAN_F0R2 register *******************/
AnnaBridge 171:3a7713b1edbc 4670 #define CAN_F0R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4671 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4672 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4673 #define CAN_F0R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4674 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4675 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4676 #define CAN_F0R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4677 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4678 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4679 #define CAN_F0R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4680 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4681 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4682 #define CAN_F0R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4683 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4684 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4685 #define CAN_F0R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4686 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4687 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4688 #define CAN_F0R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4689 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4690 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4691 #define CAN_F0R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4692 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4693 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4694 #define CAN_F0R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4695 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4696 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4697 #define CAN_F0R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4698 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4699 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4700 #define CAN_F0R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4701 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4702 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4703 #define CAN_F0R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4704 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4705 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4706 #define CAN_F0R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4707 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4708 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4709 #define CAN_F0R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4710 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4711 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4712 #define CAN_F0R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4713 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4714 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4715 #define CAN_F0R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4716 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4717 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4718 #define CAN_F0R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4719 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4720 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4721 #define CAN_F0R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4722 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4723 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4724 #define CAN_F0R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4725 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4726 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4727 #define CAN_F0R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4728 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4729 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4730 #define CAN_F0R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4731 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4732 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4733 #define CAN_F0R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4734 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4735 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4736 #define CAN_F0R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4737 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4738 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4739 #define CAN_F0R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4740 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4741 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4742 #define CAN_F0R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4743 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4744 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4745 #define CAN_F0R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4746 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4747 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4748 #define CAN_F0R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4749 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4750 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4751 #define CAN_F0R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4752 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4753 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4754 #define CAN_F0R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4755 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4756 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4757 #define CAN_F0R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4758 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4759 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4760 #define CAN_F0R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4761 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4762 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4763 #define CAN_F0R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4764 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4765 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4766
AnnaBridge 171:3a7713b1edbc 4767 /******************* Bit definition for CAN_F1R2 register *******************/
AnnaBridge 171:3a7713b1edbc 4768 #define CAN_F1R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4769 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4770 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4771 #define CAN_F1R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4772 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4773 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4774 #define CAN_F1R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4775 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4776 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4777 #define CAN_F1R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4778 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4779 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4780 #define CAN_F1R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4781 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4782 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4783 #define CAN_F1R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4784 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4785 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4786 #define CAN_F1R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4787 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4788 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4789 #define CAN_F1R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4790 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4791 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4792 #define CAN_F1R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4793 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4794 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4795 #define CAN_F1R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4796 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4797 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4798 #define CAN_F1R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4799 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4800 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4801 #define CAN_F1R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4802 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4803 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4804 #define CAN_F1R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4805 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4806 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4807 #define CAN_F1R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4808 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4809 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4810 #define CAN_F1R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4811 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4812 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4813 #define CAN_F1R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4814 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4815 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4816 #define CAN_F1R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4817 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4818 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4819 #define CAN_F1R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4820 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4821 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4822 #define CAN_F1R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4823 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4824 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4825 #define CAN_F1R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4826 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4827 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4828 #define CAN_F1R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4829 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4830 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4831 #define CAN_F1R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4832 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4833 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4834 #define CAN_F1R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4835 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4836 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4837 #define CAN_F1R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4838 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4839 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4840 #define CAN_F1R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4841 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4842 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4843 #define CAN_F1R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4844 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4845 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4846 #define CAN_F1R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4847 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4848 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4849 #define CAN_F1R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4850 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4851 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4852 #define CAN_F1R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4853 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4854 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4855 #define CAN_F1R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4856 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4857 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4858 #define CAN_F1R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4859 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4860 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4861 #define CAN_F1R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4862 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4863 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4864
AnnaBridge 171:3a7713b1edbc 4865 /******************* Bit definition for CAN_F2R2 register *******************/
AnnaBridge 171:3a7713b1edbc 4866 #define CAN_F2R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4867 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4868 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4869 #define CAN_F2R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4870 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4871 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4872 #define CAN_F2R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4873 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4874 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4875 #define CAN_F2R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4876 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4877 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4878 #define CAN_F2R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4879 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4880 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4881 #define CAN_F2R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4882 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4883 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4884 #define CAN_F2R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4885 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4886 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4887 #define CAN_F2R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4888 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4889 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4890 #define CAN_F2R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4891 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4892 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4893 #define CAN_F2R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4894 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4895 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4896 #define CAN_F2R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4897 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4898 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4899 #define CAN_F2R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4900 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4901 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 4902 #define CAN_F2R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4903 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4904 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 4905 #define CAN_F2R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4906 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4907 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 4908 #define CAN_F2R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4909 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4910 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 4911 #define CAN_F2R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4912 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4913 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 4914 #define CAN_F2R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4915 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4916 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 4917 #define CAN_F2R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4918 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4919 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 4920 #define CAN_F2R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4921 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4922 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 4923 #define CAN_F2R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4924 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4925 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 4926 #define CAN_F2R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4927 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4928 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 4929 #define CAN_F2R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4930 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4931 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 4932 #define CAN_F2R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4933 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4934 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 4935 #define CAN_F2R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4936 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4937 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 4938 #define CAN_F2R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4939 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4940 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 4941 #define CAN_F2R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4942 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4943 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 4944 #define CAN_F2R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4945 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4946 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 4947 #define CAN_F2R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4948 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4949 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 4950 #define CAN_F2R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4951 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4952 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 4953 #define CAN_F2R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4954 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4955 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 4956 #define CAN_F2R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4957 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4958 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 4959 #define CAN_F2R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4960 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4961 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 4962
AnnaBridge 171:3a7713b1edbc 4963 /******************* Bit definition for CAN_F3R2 register *******************/
AnnaBridge 171:3a7713b1edbc 4964 #define CAN_F3R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4965 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4966 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 4967 #define CAN_F3R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4968 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4969 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 4970 #define CAN_F3R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4971 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4972 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 4973 #define CAN_F3R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4974 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4975 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 4976 #define CAN_F3R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4977 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4978 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 4979 #define CAN_F3R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4980 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4981 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 4982 #define CAN_F3R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4983 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4984 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 4985 #define CAN_F3R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4986 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4987 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 4988 #define CAN_F3R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4989 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4990 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 4991 #define CAN_F3R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4992 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4993 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 4994 #define CAN_F3R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4995 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4996 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 4997 #define CAN_F3R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4998 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4999 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5000 #define CAN_F3R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5001 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5002 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5003 #define CAN_F3R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5004 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5005 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5006 #define CAN_F3R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5007 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5008 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5009 #define CAN_F3R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5010 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5011 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5012 #define CAN_F3R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5013 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5014 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5015 #define CAN_F3R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5016 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5017 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5018 #define CAN_F3R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5019 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5020 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5021 #define CAN_F3R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5022 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5023 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5024 #define CAN_F3R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5025 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5026 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5027 #define CAN_F3R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5028 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5029 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5030 #define CAN_F3R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5031 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5032 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5033 #define CAN_F3R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5034 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5035 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5036 #define CAN_F3R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5037 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5038 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5039 #define CAN_F3R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5040 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5041 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5042 #define CAN_F3R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5043 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5044 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5045 #define CAN_F3R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5046 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5047 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5048 #define CAN_F3R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5049 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5050 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5051 #define CAN_F3R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5052 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5053 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5054 #define CAN_F3R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5055 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5056 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5057 #define CAN_F3R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5058 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5059 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5060
AnnaBridge 171:3a7713b1edbc 5061 /******************* Bit definition for CAN_F4R2 register *******************/
AnnaBridge 171:3a7713b1edbc 5062 #define CAN_F4R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5063 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5064 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 5065 #define CAN_F4R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5066 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5067 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 5068 #define CAN_F4R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5069 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5070 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 5071 #define CAN_F4R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5072 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5073 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 5074 #define CAN_F4R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5075 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5076 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 5077 #define CAN_F4R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5078 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5079 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 5080 #define CAN_F4R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5081 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5082 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 5083 #define CAN_F4R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5084 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5085 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 5086 #define CAN_F4R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5087 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5088 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 5089 #define CAN_F4R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5090 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5091 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 5092 #define CAN_F4R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5093 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5094 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 5095 #define CAN_F4R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5096 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5097 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5098 #define CAN_F4R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5099 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5100 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5101 #define CAN_F4R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5102 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5103 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5104 #define CAN_F4R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5105 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5106 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5107 #define CAN_F4R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5108 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5109 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5110 #define CAN_F4R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5111 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5112 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5113 #define CAN_F4R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5114 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5115 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5116 #define CAN_F4R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5117 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5118 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5119 #define CAN_F4R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5120 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5121 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5122 #define CAN_F4R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5123 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5124 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5125 #define CAN_F4R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5126 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5127 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5128 #define CAN_F4R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5129 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5130 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5131 #define CAN_F4R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5132 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5133 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5134 #define CAN_F4R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5135 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5136 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5137 #define CAN_F4R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5138 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5139 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5140 #define CAN_F4R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5141 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5142 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5143 #define CAN_F4R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5144 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5145 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5146 #define CAN_F4R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5147 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5148 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5149 #define CAN_F4R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5150 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5151 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5152 #define CAN_F4R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5153 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5154 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5155 #define CAN_F4R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5156 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5157 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5158
AnnaBridge 171:3a7713b1edbc 5159 /******************* Bit definition for CAN_F5R2 register *******************/
AnnaBridge 171:3a7713b1edbc 5160 #define CAN_F5R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5161 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5162 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 5163 #define CAN_F5R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5164 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5165 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 5166 #define CAN_F5R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5167 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5168 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 5169 #define CAN_F5R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5170 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5171 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 5172 #define CAN_F5R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5173 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5174 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 5175 #define CAN_F5R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5176 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5177 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 5178 #define CAN_F5R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5179 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5180 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 5181 #define CAN_F5R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5182 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5183 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 5184 #define CAN_F5R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5185 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5186 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 5187 #define CAN_F5R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5188 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5189 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 5190 #define CAN_F5R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5191 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5192 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 5193 #define CAN_F5R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5194 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5195 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5196 #define CAN_F5R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5197 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5198 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5199 #define CAN_F5R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5200 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5201 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5202 #define CAN_F5R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5203 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5204 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5205 #define CAN_F5R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5206 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5207 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5208 #define CAN_F5R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5209 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5210 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5211 #define CAN_F5R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5212 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5213 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5214 #define CAN_F5R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5215 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5216 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5217 #define CAN_F5R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5218 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5219 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5220 #define CAN_F5R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5221 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5222 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5223 #define CAN_F5R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5224 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5225 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5226 #define CAN_F5R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5227 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5228 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5229 #define CAN_F5R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5230 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5231 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5232 #define CAN_F5R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5233 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5234 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5235 #define CAN_F5R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5236 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5237 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5238 #define CAN_F5R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5239 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5240 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5241 #define CAN_F5R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5242 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5243 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5244 #define CAN_F5R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5245 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5246 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5247 #define CAN_F5R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5248 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5249 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5250 #define CAN_F5R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5251 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5252 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5253 #define CAN_F5R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5254 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5255 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5256
AnnaBridge 171:3a7713b1edbc 5257 /******************* Bit definition for CAN_F6R2 register *******************/
AnnaBridge 171:3a7713b1edbc 5258 #define CAN_F6R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5259 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5260 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 5261 #define CAN_F6R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5262 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5263 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 5264 #define CAN_F6R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5265 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5266 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 5267 #define CAN_F6R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5268 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5269 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 5270 #define CAN_F6R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5271 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5272 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 5273 #define CAN_F6R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5274 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5275 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 5276 #define CAN_F6R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5277 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5278 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 5279 #define CAN_F6R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5280 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5281 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 5282 #define CAN_F6R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5283 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5284 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 5285 #define CAN_F6R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5286 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5287 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 5288 #define CAN_F6R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5289 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5290 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 5291 #define CAN_F6R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5292 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5293 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5294 #define CAN_F6R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5295 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5296 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5297 #define CAN_F6R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5298 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5299 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5300 #define CAN_F6R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5301 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5302 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5303 #define CAN_F6R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5304 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5305 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5306 #define CAN_F6R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5307 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5308 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5309 #define CAN_F6R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5310 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5311 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5312 #define CAN_F6R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5313 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5314 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5315 #define CAN_F6R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5316 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5317 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5318 #define CAN_F6R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5319 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5320 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5321 #define CAN_F6R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5322 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5323 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5324 #define CAN_F6R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5325 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5326 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5327 #define CAN_F6R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5328 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5329 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5330 #define CAN_F6R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5331 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5332 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5333 #define CAN_F6R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5334 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5335 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5336 #define CAN_F6R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5337 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5338 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5339 #define CAN_F6R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5340 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5341 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5342 #define CAN_F6R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5343 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5344 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5345 #define CAN_F6R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5346 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5347 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5348 #define CAN_F6R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5349 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5350 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5351 #define CAN_F6R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5352 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5353 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5354
AnnaBridge 171:3a7713b1edbc 5355 /******************* Bit definition for CAN_F7R2 register *******************/
AnnaBridge 171:3a7713b1edbc 5356 #define CAN_F7R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5357 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5358 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 5359 #define CAN_F7R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5360 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5361 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 5362 #define CAN_F7R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5363 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5364 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 5365 #define CAN_F7R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5366 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5367 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 5368 #define CAN_F7R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5369 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5370 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 5371 #define CAN_F7R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5372 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5373 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 5374 #define CAN_F7R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5375 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5376 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 5377 #define CAN_F7R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5378 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5379 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 5380 #define CAN_F7R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5381 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5382 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 5383 #define CAN_F7R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5384 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5385 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 5386 #define CAN_F7R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5387 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5388 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 5389 #define CAN_F7R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5390 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5391 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5392 #define CAN_F7R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5393 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5394 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5395 #define CAN_F7R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5396 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5397 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5398 #define CAN_F7R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5399 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5400 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5401 #define CAN_F7R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5402 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5403 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5404 #define CAN_F7R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5405 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5406 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5407 #define CAN_F7R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5408 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5409 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5410 #define CAN_F7R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5411 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5412 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5413 #define CAN_F7R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5414 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5415 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5416 #define CAN_F7R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5417 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5418 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5419 #define CAN_F7R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5420 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5421 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5422 #define CAN_F7R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5423 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5424 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5425 #define CAN_F7R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5426 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5427 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5428 #define CAN_F7R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5429 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5430 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5431 #define CAN_F7R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5432 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5433 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5434 #define CAN_F7R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5435 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5436 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5437 #define CAN_F7R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5438 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5439 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5440 #define CAN_F7R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5441 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5442 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5443 #define CAN_F7R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5444 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5445 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5446 #define CAN_F7R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5447 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5448 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5449 #define CAN_F7R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5450 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5451 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5452
AnnaBridge 171:3a7713b1edbc 5453 /******************* Bit definition for CAN_F8R2 register *******************/
AnnaBridge 171:3a7713b1edbc 5454 #define CAN_F8R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5455 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5456 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 5457 #define CAN_F8R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5458 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5459 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 5460 #define CAN_F8R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5461 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5462 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 5463 #define CAN_F8R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5464 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5465 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 5466 #define CAN_F8R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5467 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5468 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 5469 #define CAN_F8R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5470 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5471 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 5472 #define CAN_F8R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5473 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5474 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 5475 #define CAN_F8R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5476 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5477 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 5478 #define CAN_F8R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5479 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5480 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 5481 #define CAN_F8R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5482 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5483 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 5484 #define CAN_F8R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5485 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5486 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 5487 #define CAN_F8R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5488 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5489 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5490 #define CAN_F8R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5491 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5492 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5493 #define CAN_F8R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5494 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5495 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5496 #define CAN_F8R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5497 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5498 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5499 #define CAN_F8R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5500 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5501 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5502 #define CAN_F8R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5503 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5504 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5505 #define CAN_F8R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5506 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5507 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5508 #define CAN_F8R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5509 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5510 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5511 #define CAN_F8R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5512 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5513 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5514 #define CAN_F8R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5515 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5516 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5517 #define CAN_F8R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5518 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5519 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5520 #define CAN_F8R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5521 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5522 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5523 #define CAN_F8R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5524 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5525 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5526 #define CAN_F8R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5527 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5528 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5529 #define CAN_F8R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5530 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5531 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5532 #define CAN_F8R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5533 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5534 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5535 #define CAN_F8R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5536 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5537 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5538 #define CAN_F8R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5539 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5540 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5541 #define CAN_F8R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5542 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5543 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5544 #define CAN_F8R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5545 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5546 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5547 #define CAN_F8R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5548 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5549 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5550
AnnaBridge 171:3a7713b1edbc 5551 /******************* Bit definition for CAN_F9R2 register *******************/
AnnaBridge 171:3a7713b1edbc 5552 #define CAN_F9R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5553 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5554 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 5555 #define CAN_F9R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5556 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5557 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 5558 #define CAN_F9R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5559 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5560 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 5561 #define CAN_F9R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5562 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5563 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 5564 #define CAN_F9R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5565 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5566 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 5567 #define CAN_F9R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5568 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5569 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 5570 #define CAN_F9R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5571 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5572 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 5573 #define CAN_F9R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5574 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5575 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 5576 #define CAN_F9R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5577 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5578 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 5579 #define CAN_F9R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5580 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5581 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 5582 #define CAN_F9R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5583 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5584 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 5585 #define CAN_F9R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5586 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5587 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5588 #define CAN_F9R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5589 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5590 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5591 #define CAN_F9R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5592 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5593 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5594 #define CAN_F9R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5595 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5596 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5597 #define CAN_F9R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5598 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5599 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5600 #define CAN_F9R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5601 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5602 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5603 #define CAN_F9R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5604 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5605 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5606 #define CAN_F9R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5607 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5608 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5609 #define CAN_F9R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5610 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5611 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5612 #define CAN_F9R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5613 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5614 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5615 #define CAN_F9R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5616 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5617 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5618 #define CAN_F9R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5619 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5620 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5621 #define CAN_F9R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5622 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5623 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5624 #define CAN_F9R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5625 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5626 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5627 #define CAN_F9R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5628 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5629 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5630 #define CAN_F9R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5631 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5632 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5633 #define CAN_F9R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5634 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5635 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5636 #define CAN_F9R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5637 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5638 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5639 #define CAN_F9R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5640 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5641 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5642 #define CAN_F9R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5643 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5644 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5645 #define CAN_F9R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5646 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5647 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5648
AnnaBridge 171:3a7713b1edbc 5649 /******************* Bit definition for CAN_F10R2 register ******************/
AnnaBridge 171:3a7713b1edbc 5650 #define CAN_F10R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5651 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5652 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 5653 #define CAN_F10R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5654 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5655 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 5656 #define CAN_F10R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5657 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5658 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 5659 #define CAN_F10R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5660 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5661 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 5662 #define CAN_F10R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5663 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5664 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 5665 #define CAN_F10R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5666 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5667 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 5668 #define CAN_F10R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5669 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5670 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 5671 #define CAN_F10R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5672 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5673 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 5674 #define CAN_F10R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5675 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5676 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 5677 #define CAN_F10R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5678 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5679 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 5680 #define CAN_F10R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5681 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5682 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 5683 #define CAN_F10R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5684 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5685 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5686 #define CAN_F10R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5687 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5688 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5689 #define CAN_F10R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5690 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5691 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5692 #define CAN_F10R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5693 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5694 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5695 #define CAN_F10R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5696 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5697 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5698 #define CAN_F10R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5699 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5700 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5701 #define CAN_F10R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5702 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5703 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5704 #define CAN_F10R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5705 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5706 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5707 #define CAN_F10R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5708 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5709 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5710 #define CAN_F10R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5711 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5712 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5713 #define CAN_F10R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5714 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5715 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5716 #define CAN_F10R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5717 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5718 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5719 #define CAN_F10R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5720 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5721 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5722 #define CAN_F10R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5723 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5724 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5725 #define CAN_F10R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5726 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5727 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5728 #define CAN_F10R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5729 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5730 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5731 #define CAN_F10R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5732 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5733 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5734 #define CAN_F10R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5735 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5736 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5737 #define CAN_F10R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5738 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5739 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5740 #define CAN_F10R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5741 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5742 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5743 #define CAN_F10R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5744 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5745 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5746
AnnaBridge 171:3a7713b1edbc 5747 /******************* Bit definition for CAN_F11R2 register ******************/
AnnaBridge 171:3a7713b1edbc 5748 #define CAN_F11R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5749 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5750 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 5751 #define CAN_F11R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5752 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5753 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 5754 #define CAN_F11R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5755 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5756 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 5757 #define CAN_F11R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5758 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5759 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 5760 #define CAN_F11R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5761 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5762 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 5763 #define CAN_F11R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5764 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5765 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 5766 #define CAN_F11R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5767 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5768 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 5769 #define CAN_F11R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5770 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5771 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 5772 #define CAN_F11R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5773 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5774 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 5775 #define CAN_F11R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5776 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5777 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 5778 #define CAN_F11R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5779 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5780 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 5781 #define CAN_F11R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5782 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5783 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5784 #define CAN_F11R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5785 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5786 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5787 #define CAN_F11R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5788 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5789 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5790 #define CAN_F11R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5791 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5792 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5793 #define CAN_F11R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5794 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5795 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5796 #define CAN_F11R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5797 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5798 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5799 #define CAN_F11R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5800 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5801 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5802 #define CAN_F11R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5803 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5804 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5805 #define CAN_F11R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5806 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5807 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5808 #define CAN_F11R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5809 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5810 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5811 #define CAN_F11R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5812 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5813 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5814 #define CAN_F11R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5815 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5816 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5817 #define CAN_F11R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5818 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5819 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5820 #define CAN_F11R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5821 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5822 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5823 #define CAN_F11R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5824 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5825 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5826 #define CAN_F11R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5827 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5828 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5829 #define CAN_F11R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5830 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5831 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5832 #define CAN_F11R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5833 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5834 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5835 #define CAN_F11R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5836 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5837 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5838 #define CAN_F11R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5839 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5840 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5841 #define CAN_F11R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5842 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5843 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5844
AnnaBridge 171:3a7713b1edbc 5845 /******************* Bit definition for CAN_F12R2 register ******************/
AnnaBridge 171:3a7713b1edbc 5846 #define CAN_F12R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5847 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5848 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 5849 #define CAN_F12R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5850 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5851 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 5852 #define CAN_F12R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5853 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5854 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 5855 #define CAN_F12R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5856 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5857 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 5858 #define CAN_F12R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5859 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5860 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 5861 #define CAN_F12R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5862 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5863 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 5864 #define CAN_F12R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5865 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5866 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 5867 #define CAN_F12R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5868 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5869 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 5870 #define CAN_F12R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5871 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5872 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 5873 #define CAN_F12R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5874 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5875 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 5876 #define CAN_F12R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5877 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5878 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 5879 #define CAN_F12R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5880 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5881 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5882 #define CAN_F12R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5883 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5884 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5885 #define CAN_F12R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5886 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5887 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5888 #define CAN_F12R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5889 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5890 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5891 #define CAN_F12R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5892 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5893 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5894 #define CAN_F12R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5895 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5896 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5897 #define CAN_F12R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5898 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5899 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5900 #define CAN_F12R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5901 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5902 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 5903 #define CAN_F12R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5904 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5905 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 5906 #define CAN_F12R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5907 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5908 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 5909 #define CAN_F12R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5910 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5911 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 5912 #define CAN_F12R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5913 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5914 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 5915 #define CAN_F12R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5916 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5917 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 5918 #define CAN_F12R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5919 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5920 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 5921 #define CAN_F12R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 5922 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5923 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 5924 #define CAN_F12R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5925 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5926 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 5927 #define CAN_F12R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5928 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5929 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 5930 #define CAN_F12R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5931 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5932 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 5933 #define CAN_F12R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 5934 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5935 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 5936 #define CAN_F12R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5937 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5938 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 5939 #define CAN_F12R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5940 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5941 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 5942
AnnaBridge 171:3a7713b1edbc 5943 /******************* Bit definition for CAN_F13R2 register ******************/
AnnaBridge 171:3a7713b1edbc 5944 #define CAN_F13R2_FB0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5945 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5946 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 171:3a7713b1edbc 5947 #define CAN_F13R2_FB1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5948 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5949 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 171:3a7713b1edbc 5950 #define CAN_F13R2_FB2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5951 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5952 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 171:3a7713b1edbc 5953 #define CAN_F13R2_FB3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5954 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5955 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 171:3a7713b1edbc 5956 #define CAN_F13R2_FB4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5957 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5958 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 171:3a7713b1edbc 5959 #define CAN_F13R2_FB5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5960 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5961 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 171:3a7713b1edbc 5962 #define CAN_F13R2_FB6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5963 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5964 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 171:3a7713b1edbc 5965 #define CAN_F13R2_FB7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5966 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5967 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 171:3a7713b1edbc 5968 #define CAN_F13R2_FB8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5969 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5970 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 171:3a7713b1edbc 5971 #define CAN_F13R2_FB9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5972 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5973 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 171:3a7713b1edbc 5974 #define CAN_F13R2_FB10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5975 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5976 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 171:3a7713b1edbc 5977 #define CAN_F13R2_FB11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5978 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5979 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 171:3a7713b1edbc 5980 #define CAN_F13R2_FB12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5981 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5982 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 171:3a7713b1edbc 5983 #define CAN_F13R2_FB13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5984 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5985 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 171:3a7713b1edbc 5986 #define CAN_F13R2_FB14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5987 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5988 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 171:3a7713b1edbc 5989 #define CAN_F13R2_FB15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5990 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5991 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 171:3a7713b1edbc 5992 #define CAN_F13R2_FB16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5993 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5994 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 171:3a7713b1edbc 5995 #define CAN_F13R2_FB17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5996 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5997 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 171:3a7713b1edbc 5998 #define CAN_F13R2_FB18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5999 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6000 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 171:3a7713b1edbc 6001 #define CAN_F13R2_FB19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6002 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6003 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 171:3a7713b1edbc 6004 #define CAN_F13R2_FB20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6005 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6006 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 171:3a7713b1edbc 6007 #define CAN_F13R2_FB21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6008 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6009 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 171:3a7713b1edbc 6010 #define CAN_F13R2_FB22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6011 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6012 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 171:3a7713b1edbc 6013 #define CAN_F13R2_FB23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 6014 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 6015 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 171:3a7713b1edbc 6016 #define CAN_F13R2_FB24_Pos (24U)
AnnaBridge 171:3a7713b1edbc 6017 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 6018 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 171:3a7713b1edbc 6019 #define CAN_F13R2_FB25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 6020 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 6021 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 171:3a7713b1edbc 6022 #define CAN_F13R2_FB26_Pos (26U)
AnnaBridge 171:3a7713b1edbc 6023 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 6024 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 171:3a7713b1edbc 6025 #define CAN_F13R2_FB27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 6026 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 6027 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 171:3a7713b1edbc 6028 #define CAN_F13R2_FB28_Pos (28U)
AnnaBridge 171:3a7713b1edbc 6029 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 6030 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 171:3a7713b1edbc 6031 #define CAN_F13R2_FB29_Pos (29U)
AnnaBridge 171:3a7713b1edbc 6032 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 6033 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 171:3a7713b1edbc 6034 #define CAN_F13R2_FB30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 6035 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 6036 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 171:3a7713b1edbc 6037 #define CAN_F13R2_FB31_Pos (31U)
AnnaBridge 171:3a7713b1edbc 6038 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 6039 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 171:3a7713b1edbc 6040
AnnaBridge 171:3a7713b1edbc 6041 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6042 /* */
AnnaBridge 171:3a7713b1edbc 6043 /* CRC calculation unit (CRC) */
AnnaBridge 171:3a7713b1edbc 6044 /* */
AnnaBridge 171:3a7713b1edbc 6045 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6046 /******************* Bit definition for CRC_DR register *********************/
AnnaBridge 171:3a7713b1edbc 6047 #define CRC_DR_DR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6048 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 6049 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
AnnaBridge 171:3a7713b1edbc 6050
AnnaBridge 171:3a7713b1edbc 6051 /******************* Bit definition for CRC_IDR register ********************/
AnnaBridge 171:3a7713b1edbc 6052 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
AnnaBridge 171:3a7713b1edbc 6053
AnnaBridge 171:3a7713b1edbc 6054 /******************** Bit definition for CRC_CR register ********************/
AnnaBridge 171:3a7713b1edbc 6055 #define CRC_CR_RESET_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6056 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6057 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
AnnaBridge 171:3a7713b1edbc 6058 #define CRC_CR_POLYSIZE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6059 #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
AnnaBridge 171:3a7713b1edbc 6060 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
AnnaBridge 171:3a7713b1edbc 6061 #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6062 #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6063 #define CRC_CR_REV_IN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6064 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
AnnaBridge 171:3a7713b1edbc 6065 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
AnnaBridge 171:3a7713b1edbc 6066 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6067 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6068 #define CRC_CR_REV_OUT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6069 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6070 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
AnnaBridge 171:3a7713b1edbc 6071
AnnaBridge 171:3a7713b1edbc 6072 /******************* Bit definition for CRC_INIT register *******************/
AnnaBridge 171:3a7713b1edbc 6073 #define CRC_INIT_INIT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6074 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 6075 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
AnnaBridge 171:3a7713b1edbc 6076
AnnaBridge 171:3a7713b1edbc 6077 /******************* Bit definition for CRC_POL register ********************/
AnnaBridge 171:3a7713b1edbc 6078 #define CRC_POL_POL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6079 #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 6080 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
AnnaBridge 171:3a7713b1edbc 6081
AnnaBridge 171:3a7713b1edbc 6082 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6083 /* */
AnnaBridge 171:3a7713b1edbc 6084 /* Digital to Analog Converter (DAC) */
AnnaBridge 171:3a7713b1edbc 6085 /* */
AnnaBridge 171:3a7713b1edbc 6086 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6087
AnnaBridge 171:3a7713b1edbc 6088 /*
AnnaBridge 171:3a7713b1edbc 6089 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
AnnaBridge 171:3a7713b1edbc 6090 */
AnnaBridge 171:3a7713b1edbc 6091 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available (may not be available on all DAC instances DACx) */
AnnaBridge 171:3a7713b1edbc 6092
AnnaBridge 171:3a7713b1edbc 6093
AnnaBridge 171:3a7713b1edbc 6094 /******************** Bit definition for DAC_CR register ********************/
AnnaBridge 171:3a7713b1edbc 6095 #define DAC_CR_EN1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6096 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6097 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
AnnaBridge 171:3a7713b1edbc 6098 #define DAC_CR_BOFF1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6099 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6100 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
AnnaBridge 171:3a7713b1edbc 6101 #define DAC_CR_OUTEN1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6102 #define DAC_CR_OUTEN1_Msk (0x1U << DAC_CR_OUTEN1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6103 #define DAC_CR_OUTEN1 DAC_CR_OUTEN1_Msk /*!< DAC channel1 output switch enable (only for DAC instance: DAC2) */
AnnaBridge 171:3a7713b1edbc 6104 #define DAC_CR_TEN1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6105 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6106 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
AnnaBridge 171:3a7713b1edbc 6107
AnnaBridge 171:3a7713b1edbc 6108 #define DAC_CR_TSEL1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6109 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 6110 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
AnnaBridge 171:3a7713b1edbc 6111 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6112 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6113 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6114
AnnaBridge 171:3a7713b1edbc 6115 #define DAC_CR_WAVE1_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6116 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 6117 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
AnnaBridge 171:3a7713b1edbc 6118 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6119 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6120
AnnaBridge 171:3a7713b1edbc 6121 #define DAC_CR_MAMP1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6122 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 6123 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
AnnaBridge 171:3a7713b1edbc 6124 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6125 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6126 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6127 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6128
AnnaBridge 171:3a7713b1edbc 6129 #define DAC_CR_DMAEN1_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6130 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6131 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
AnnaBridge 171:3a7713b1edbc 6132 #define DAC_CR_DMAUDRIE1_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6133 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6134 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA underrun IT enable */
AnnaBridge 171:3a7713b1edbc 6135 #define DAC_CR_EN2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6136 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6137 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */
AnnaBridge 171:3a7713b1edbc 6138 #define DAC_CR_BOFF2_Pos (17U)
AnnaBridge 171:3a7713b1edbc 6139 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6140 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */
AnnaBridge 171:3a7713b1edbc 6141 #define DAC_CR_OUTEN2_Pos (17U)
AnnaBridge 171:3a7713b1edbc 6142 #define DAC_CR_OUTEN2_Msk (0x1U << DAC_CR_OUTEN2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6143 #define DAC_CR_OUTEN2 DAC_CR_OUTEN2_Msk /*!< DAC channel2 output switch enable (only for DAC instance: DAC2) */
AnnaBridge 171:3a7713b1edbc 6144 #define DAC_CR_TEN2_Pos (18U)
AnnaBridge 171:3a7713b1edbc 6145 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6146 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */
AnnaBridge 171:3a7713b1edbc 6147
AnnaBridge 171:3a7713b1edbc 6148 #define DAC_CR_TSEL2_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6149 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
AnnaBridge 171:3a7713b1edbc 6150 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
AnnaBridge 171:3a7713b1edbc 6151 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6152 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6153 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6154
AnnaBridge 171:3a7713b1edbc 6155 #define DAC_CR_WAVE2_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6156 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 6157 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
AnnaBridge 171:3a7713b1edbc 6158 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6159 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 6160
AnnaBridge 171:3a7713b1edbc 6161 #define DAC_CR_MAMP2_Pos (24U)
AnnaBridge 171:3a7713b1edbc 6162 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 6163 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
AnnaBridge 171:3a7713b1edbc 6164 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 6165 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 6166 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 6167 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 6168
AnnaBridge 171:3a7713b1edbc 6169 #define DAC_CR_DMAEN2_Pos (28U)
AnnaBridge 171:3a7713b1edbc 6170 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 6171 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */
AnnaBridge 171:3a7713b1edbc 6172 #define DAC_CR_DMAUDRIE2_Pos (29U)
AnnaBridge 171:3a7713b1edbc 6173 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 6174 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel2 DMA underrun IT enable */
AnnaBridge 171:3a7713b1edbc 6175
AnnaBridge 171:3a7713b1edbc 6176 /***************** Bit definition for DAC_SWTRIGR register ******************/
AnnaBridge 171:3a7713b1edbc 6177 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6178 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6179 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
AnnaBridge 171:3a7713b1edbc 6180 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6181 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6182 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */
AnnaBridge 171:3a7713b1edbc 6183
AnnaBridge 171:3a7713b1edbc 6184 /***************** Bit definition for DAC_DHR12R1 register ******************/
AnnaBridge 171:3a7713b1edbc 6185 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6186 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 6187 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 6188
AnnaBridge 171:3a7713b1edbc 6189 /***************** Bit definition for DAC_DHR12L1 register ******************/
AnnaBridge 171:3a7713b1edbc 6190 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6191 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 171:3a7713b1edbc 6192 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
AnnaBridge 171:3a7713b1edbc 6193
AnnaBridge 171:3a7713b1edbc 6194 /****************** Bit definition for DAC_DHR8R1 register ******************/
AnnaBridge 171:3a7713b1edbc 6195 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6196 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 6197 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 6198
AnnaBridge 171:3a7713b1edbc 6199 /***************** Bit definition for DAC_DHR12R2 register ******************/
AnnaBridge 171:3a7713b1edbc 6200 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6201 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 6202 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 6203
AnnaBridge 171:3a7713b1edbc 6204 /***************** Bit definition for DAC_DHR12L2 register ******************/
AnnaBridge 171:3a7713b1edbc 6205 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6206 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 171:3a7713b1edbc 6207 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
AnnaBridge 171:3a7713b1edbc 6208
AnnaBridge 171:3a7713b1edbc 6209 /****************** Bit definition for DAC_DHR8R2 register ******************/
AnnaBridge 171:3a7713b1edbc 6210 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6211 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 6212 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 6213
AnnaBridge 171:3a7713b1edbc 6214 /***************** Bit definition for DAC_DHR12RD register ******************/
AnnaBridge 171:3a7713b1edbc 6215 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6216 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 6217 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 6218 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6219 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
AnnaBridge 171:3a7713b1edbc 6220 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 6221
AnnaBridge 171:3a7713b1edbc 6222 /***************** Bit definition for DAC_DHR12LD register ******************/
AnnaBridge 171:3a7713b1edbc 6223 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6224 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 171:3a7713b1edbc 6225 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
AnnaBridge 171:3a7713b1edbc 6226 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6227 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
AnnaBridge 171:3a7713b1edbc 6228 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
AnnaBridge 171:3a7713b1edbc 6229
AnnaBridge 171:3a7713b1edbc 6230 /****************** Bit definition for DAC_DHR8RD register ******************/
AnnaBridge 171:3a7713b1edbc 6231 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6232 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 6233 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 6234 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6235 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 6236 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 6237
AnnaBridge 171:3a7713b1edbc 6238 /******************* Bit definition for DAC_DOR1 register *******************/
AnnaBridge 171:3a7713b1edbc 6239 #define DAC_DOR1_DACC1DOR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6240 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 6241 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */
AnnaBridge 171:3a7713b1edbc 6242
AnnaBridge 171:3a7713b1edbc 6243 /******************* Bit definition for DAC_DOR2 register *******************/
AnnaBridge 171:3a7713b1edbc 6244 #define DAC_DOR2_DACC2DOR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6245 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 6246 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */
AnnaBridge 171:3a7713b1edbc 6247
AnnaBridge 171:3a7713b1edbc 6248 /******************** Bit definition for DAC_SR register ********************/
AnnaBridge 171:3a7713b1edbc 6249 #define DAC_SR_DMAUDR1_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6250 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6251 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */
AnnaBridge 171:3a7713b1edbc 6252 #define DAC_SR_DMAUDR2_Pos (29U)
AnnaBridge 171:3a7713b1edbc 6253 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 6254 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */
AnnaBridge 171:3a7713b1edbc 6255
AnnaBridge 171:3a7713b1edbc 6256 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6257 /* */
AnnaBridge 171:3a7713b1edbc 6258 /* Debug MCU (DBGMCU) */
AnnaBridge 171:3a7713b1edbc 6259 /* */
AnnaBridge 171:3a7713b1edbc 6260 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6261 /******************** Bit definition for DBGMCU_IDCODE register *************/
AnnaBridge 171:3a7713b1edbc 6262 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6263 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 6264 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
AnnaBridge 171:3a7713b1edbc 6265 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6266 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 6267 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
AnnaBridge 171:3a7713b1edbc 6268
AnnaBridge 171:3a7713b1edbc 6269 /******************** Bit definition for DBGMCU_CR register *****************/
AnnaBridge 171:3a7713b1edbc 6270 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6271 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6272 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
AnnaBridge 171:3a7713b1edbc 6273 #define DBGMCU_CR_DBG_STOP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6274 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6275 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
AnnaBridge 171:3a7713b1edbc 6276 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6277 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6278 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
AnnaBridge 171:3a7713b1edbc 6279 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6280 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6281 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
AnnaBridge 171:3a7713b1edbc 6282
AnnaBridge 171:3a7713b1edbc 6283 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6284 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 6285 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
AnnaBridge 171:3a7713b1edbc 6286 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6287 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6288
AnnaBridge 171:3a7713b1edbc 6289 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
AnnaBridge 171:3a7713b1edbc 6290 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6291 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6292 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
AnnaBridge 171:3a7713b1edbc 6293 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6294 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6295 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
AnnaBridge 171:3a7713b1edbc 6296 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6297 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6298 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
AnnaBridge 171:3a7713b1edbc 6299 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6300 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6301 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
AnnaBridge 171:3a7713b1edbc 6302 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6303 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6304 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
AnnaBridge 171:3a7713b1edbc 6305 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6306 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6307 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
AnnaBridge 171:3a7713b1edbc 6308 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6309 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6310 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
AnnaBridge 171:3a7713b1edbc 6311 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6312 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6313 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
AnnaBridge 171:3a7713b1edbc 6314 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos (25U)
AnnaBridge 171:3a7713b1edbc 6315 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 6316 #define DBGMCU_APB1_FZ_DBG_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk
AnnaBridge 171:3a7713b1edbc 6317
AnnaBridge 171:3a7713b1edbc 6318 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
AnnaBridge 171:3a7713b1edbc 6319 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6320 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6321 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
AnnaBridge 171:3a7713b1edbc 6322 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6323 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6324 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk
AnnaBridge 171:3a7713b1edbc 6325 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6326 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6327 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk
AnnaBridge 171:3a7713b1edbc 6328 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6329 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6330 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk
AnnaBridge 171:3a7713b1edbc 6331 #define DBGMCU_APB2_FZ_DBG_HRTIM1_STOP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6332 #define DBGMCU_APB2_FZ_DBG_HRTIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_HRTIM1_STOP_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6333 #define DBGMCU_APB2_FZ_DBG_HRTIM1_STOP DBGMCU_APB2_FZ_DBG_HRTIM1_STOP_Msk
AnnaBridge 171:3a7713b1edbc 6334
AnnaBridge 171:3a7713b1edbc 6335 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6336 /* */
AnnaBridge 171:3a7713b1edbc 6337 /* DMA Controller (DMA) */
AnnaBridge 171:3a7713b1edbc 6338 /* */
AnnaBridge 171:3a7713b1edbc 6339 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6340 /******************* Bit definition for DMA_ISR register ********************/
AnnaBridge 171:3a7713b1edbc 6341 #define DMA_ISR_GIF1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6342 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6343 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 6344 #define DMA_ISR_TCIF1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6345 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6346 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 6347 #define DMA_ISR_HTIF1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6348 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6349 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 6350 #define DMA_ISR_TEIF1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6351 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6352 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 6353 #define DMA_ISR_GIF2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6354 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6355 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 6356 #define DMA_ISR_TCIF2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6357 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6358 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 6359 #define DMA_ISR_HTIF2_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6360 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6361 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 6362 #define DMA_ISR_TEIF2_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6363 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6364 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 6365 #define DMA_ISR_GIF3_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6366 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6367 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 6368 #define DMA_ISR_TCIF3_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6369 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6370 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 6371 #define DMA_ISR_HTIF3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6372 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6373 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 6374 #define DMA_ISR_TEIF3_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6375 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6376 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 6377 #define DMA_ISR_GIF4_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6378 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6379 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 6380 #define DMA_ISR_TCIF4_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6381 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6382 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 6383 #define DMA_ISR_HTIF4_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6384 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6385 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 6386 #define DMA_ISR_TEIF4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6387 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6388 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 6389 #define DMA_ISR_GIF5_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6390 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6391 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 6392 #define DMA_ISR_TCIF5_Pos (17U)
AnnaBridge 171:3a7713b1edbc 6393 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6394 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 6395 #define DMA_ISR_HTIF5_Pos (18U)
AnnaBridge 171:3a7713b1edbc 6396 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6397 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 6398 #define DMA_ISR_TEIF5_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6399 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6400 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 6401 #define DMA_ISR_GIF6_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6402 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6403 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 6404 #define DMA_ISR_TCIF6_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6405 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6406 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 6407 #define DMA_ISR_HTIF6_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6408 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6409 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 6410 #define DMA_ISR_TEIF6_Pos (23U)
AnnaBridge 171:3a7713b1edbc 6411 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 6412 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 6413 #define DMA_ISR_GIF7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 6414 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 6415 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 6416 #define DMA_ISR_TCIF7_Pos (25U)
AnnaBridge 171:3a7713b1edbc 6417 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 6418 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 6419 #define DMA_ISR_HTIF7_Pos (26U)
AnnaBridge 171:3a7713b1edbc 6420 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 6421 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 6422 #define DMA_ISR_TEIF7_Pos (27U)
AnnaBridge 171:3a7713b1edbc 6423 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 6424 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 6425
AnnaBridge 171:3a7713b1edbc 6426 /******************* Bit definition for DMA_IFCR register *******************/
AnnaBridge 171:3a7713b1edbc 6427 #define DMA_IFCR_CGIF1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6428 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6429 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 6430 #define DMA_IFCR_CTCIF1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6431 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6432 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 6433 #define DMA_IFCR_CHTIF1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6434 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6435 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 6436 #define DMA_IFCR_CTEIF1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6437 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6438 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 6439 #define DMA_IFCR_CGIF2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6440 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6441 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 6442 #define DMA_IFCR_CTCIF2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6443 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6444 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 6445 #define DMA_IFCR_CHTIF2_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6446 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6447 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 6448 #define DMA_IFCR_CTEIF2_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6449 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6450 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 6451 #define DMA_IFCR_CGIF3_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6452 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6453 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 6454 #define DMA_IFCR_CTCIF3_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6455 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6456 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 6457 #define DMA_IFCR_CHTIF3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6458 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6459 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 6460 #define DMA_IFCR_CTEIF3_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6461 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6462 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 6463 #define DMA_IFCR_CGIF4_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6464 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6465 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 6466 #define DMA_IFCR_CTCIF4_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6467 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6468 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 6469 #define DMA_IFCR_CHTIF4_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6470 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6471 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 6472 #define DMA_IFCR_CTEIF4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6473 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6474 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 6475 #define DMA_IFCR_CGIF5_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6476 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6477 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 6478 #define DMA_IFCR_CTCIF5_Pos (17U)
AnnaBridge 171:3a7713b1edbc 6479 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6480 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 6481 #define DMA_IFCR_CHTIF5_Pos (18U)
AnnaBridge 171:3a7713b1edbc 6482 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6483 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 6484 #define DMA_IFCR_CTEIF5_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6485 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6486 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 6487 #define DMA_IFCR_CGIF6_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6488 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6489 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 6490 #define DMA_IFCR_CTCIF6_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6491 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6492 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 6493 #define DMA_IFCR_CHTIF6_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6494 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6495 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 6496 #define DMA_IFCR_CTEIF6_Pos (23U)
AnnaBridge 171:3a7713b1edbc 6497 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 6498 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 6499 #define DMA_IFCR_CGIF7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 6500 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 6501 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 6502 #define DMA_IFCR_CTCIF7_Pos (25U)
AnnaBridge 171:3a7713b1edbc 6503 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 6504 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 6505 #define DMA_IFCR_CHTIF7_Pos (26U)
AnnaBridge 171:3a7713b1edbc 6506 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 6507 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 6508 #define DMA_IFCR_CTEIF7_Pos (27U)
AnnaBridge 171:3a7713b1edbc 6509 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 6510 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 6511
AnnaBridge 171:3a7713b1edbc 6512 /******************* Bit definition for DMA_CCR register ********************/
AnnaBridge 171:3a7713b1edbc 6513 #define DMA_CCR_EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6514 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6515 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
AnnaBridge 171:3a7713b1edbc 6516 #define DMA_CCR_TCIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6517 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6518 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
AnnaBridge 171:3a7713b1edbc 6519 #define DMA_CCR_HTIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6520 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6521 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
AnnaBridge 171:3a7713b1edbc 6522 #define DMA_CCR_TEIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6523 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6524 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
AnnaBridge 171:3a7713b1edbc 6525 #define DMA_CCR_DIR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6526 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6527 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
AnnaBridge 171:3a7713b1edbc 6528 #define DMA_CCR_CIRC_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6529 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6530 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
AnnaBridge 171:3a7713b1edbc 6531 #define DMA_CCR_PINC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6532 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6533 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
AnnaBridge 171:3a7713b1edbc 6534 #define DMA_CCR_MINC_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6535 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6536 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
AnnaBridge 171:3a7713b1edbc 6537
AnnaBridge 171:3a7713b1edbc 6538 #define DMA_CCR_PSIZE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6539 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 6540 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
AnnaBridge 171:3a7713b1edbc 6541 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6542 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6543
AnnaBridge 171:3a7713b1edbc 6544 #define DMA_CCR_MSIZE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6545 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 6546 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
AnnaBridge 171:3a7713b1edbc 6547 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6548 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6549
AnnaBridge 171:3a7713b1edbc 6550 #define DMA_CCR_PL_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6551 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 6552 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
AnnaBridge 171:3a7713b1edbc 6553 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6554 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6555
AnnaBridge 171:3a7713b1edbc 6556 #define DMA_CCR_MEM2MEM_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6557 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6558 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
AnnaBridge 171:3a7713b1edbc 6559
AnnaBridge 171:3a7713b1edbc 6560 /****************** Bit definition for DMA_CNDTR register *******************/
AnnaBridge 171:3a7713b1edbc 6561 #define DMA_CNDTR_NDT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6562 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6563 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
AnnaBridge 171:3a7713b1edbc 6564
AnnaBridge 171:3a7713b1edbc 6565 /****************** Bit definition for DMA_CPAR register ********************/
AnnaBridge 171:3a7713b1edbc 6566 #define DMA_CPAR_PA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6567 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 6568 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
AnnaBridge 171:3a7713b1edbc 6569
AnnaBridge 171:3a7713b1edbc 6570 /****************** Bit definition for DMA_CMAR register ********************/
AnnaBridge 171:3a7713b1edbc 6571 #define DMA_CMAR_MA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6572 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 6573 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
AnnaBridge 171:3a7713b1edbc 6574
AnnaBridge 171:3a7713b1edbc 6575 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6576 /* */
AnnaBridge 171:3a7713b1edbc 6577 /* External Interrupt/Event Controller (EXTI) */
AnnaBridge 171:3a7713b1edbc 6578 /* */
AnnaBridge 171:3a7713b1edbc 6579 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6580 /******************* Bit definition for EXTI_IMR register *******************/
AnnaBridge 171:3a7713b1edbc 6581 #define EXTI_IMR_MR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6582 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6583 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
AnnaBridge 171:3a7713b1edbc 6584 #define EXTI_IMR_MR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6585 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6586 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
AnnaBridge 171:3a7713b1edbc 6587 #define EXTI_IMR_MR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6588 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6589 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
AnnaBridge 171:3a7713b1edbc 6590 #define EXTI_IMR_MR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6591 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6592 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
AnnaBridge 171:3a7713b1edbc 6593 #define EXTI_IMR_MR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6594 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6595 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
AnnaBridge 171:3a7713b1edbc 6596 #define EXTI_IMR_MR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6597 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6598 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
AnnaBridge 171:3a7713b1edbc 6599 #define EXTI_IMR_MR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6600 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6601 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
AnnaBridge 171:3a7713b1edbc 6602 #define EXTI_IMR_MR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6603 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6604 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
AnnaBridge 171:3a7713b1edbc 6605 #define EXTI_IMR_MR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6606 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6607 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
AnnaBridge 171:3a7713b1edbc 6608 #define EXTI_IMR_MR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6609 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6610 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
AnnaBridge 171:3a7713b1edbc 6611 #define EXTI_IMR_MR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6612 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6613 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
AnnaBridge 171:3a7713b1edbc 6614 #define EXTI_IMR_MR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6615 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6616 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
AnnaBridge 171:3a7713b1edbc 6617 #define EXTI_IMR_MR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6618 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6619 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
AnnaBridge 171:3a7713b1edbc 6620 #define EXTI_IMR_MR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6621 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6622 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
AnnaBridge 171:3a7713b1edbc 6623 #define EXTI_IMR_MR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6624 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6625 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
AnnaBridge 171:3a7713b1edbc 6626 #define EXTI_IMR_MR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6627 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6628 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
AnnaBridge 171:3a7713b1edbc 6629 #define EXTI_IMR_MR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6630 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6631 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
AnnaBridge 171:3a7713b1edbc 6632 #define EXTI_IMR_MR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 6633 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6634 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
AnnaBridge 171:3a7713b1edbc 6635 #define EXTI_IMR_MR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6636 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6637 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
AnnaBridge 171:3a7713b1edbc 6638 #define EXTI_IMR_MR20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6639 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6640 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
AnnaBridge 171:3a7713b1edbc 6641 #define EXTI_IMR_MR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6642 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6643 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
AnnaBridge 171:3a7713b1edbc 6644 #define EXTI_IMR_MR23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 6645 #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 6646 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
AnnaBridge 171:3a7713b1edbc 6647 #define EXTI_IMR_MR25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 6648 #define EXTI_IMR_MR25_Msk (0x1U << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 6649 #define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */
AnnaBridge 171:3a7713b1edbc 6650 #define EXTI_IMR_MR30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 6651 #define EXTI_IMR_MR30_Msk (0x1U << EXTI_IMR_MR30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 6652 #define EXTI_IMR_MR30 EXTI_IMR_MR30_Msk /*!< Interrupt Mask on line 30 */
AnnaBridge 171:3a7713b1edbc 6653
AnnaBridge 171:3a7713b1edbc 6654 /* References Defines */
AnnaBridge 171:3a7713b1edbc 6655 #define EXTI_IMR_IM0 EXTI_IMR_MR0
AnnaBridge 171:3a7713b1edbc 6656 #define EXTI_IMR_IM1 EXTI_IMR_MR1
AnnaBridge 171:3a7713b1edbc 6657 #define EXTI_IMR_IM2 EXTI_IMR_MR2
AnnaBridge 171:3a7713b1edbc 6658 #define EXTI_IMR_IM3 EXTI_IMR_MR3
AnnaBridge 171:3a7713b1edbc 6659 #define EXTI_IMR_IM4 EXTI_IMR_MR4
AnnaBridge 171:3a7713b1edbc 6660 #define EXTI_IMR_IM5 EXTI_IMR_MR5
AnnaBridge 171:3a7713b1edbc 6661 #define EXTI_IMR_IM6 EXTI_IMR_MR6
AnnaBridge 171:3a7713b1edbc 6662 #define EXTI_IMR_IM7 EXTI_IMR_MR7
AnnaBridge 171:3a7713b1edbc 6663 #define EXTI_IMR_IM8 EXTI_IMR_MR8
AnnaBridge 171:3a7713b1edbc 6664 #define EXTI_IMR_IM9 EXTI_IMR_MR9
AnnaBridge 171:3a7713b1edbc 6665 #define EXTI_IMR_IM10 EXTI_IMR_MR10
AnnaBridge 171:3a7713b1edbc 6666 #define EXTI_IMR_IM11 EXTI_IMR_MR11
AnnaBridge 171:3a7713b1edbc 6667 #define EXTI_IMR_IM12 EXTI_IMR_MR12
AnnaBridge 171:3a7713b1edbc 6668 #define EXTI_IMR_IM13 EXTI_IMR_MR13
AnnaBridge 171:3a7713b1edbc 6669 #define EXTI_IMR_IM14 EXTI_IMR_MR14
AnnaBridge 171:3a7713b1edbc 6670 #define EXTI_IMR_IM15 EXTI_IMR_MR15
AnnaBridge 171:3a7713b1edbc 6671 #define EXTI_IMR_IM16 EXTI_IMR_MR16
AnnaBridge 171:3a7713b1edbc 6672 #define EXTI_IMR_IM17 EXTI_IMR_MR17
AnnaBridge 171:3a7713b1edbc 6673 #if defined(EXTI_IMR_MR18)
AnnaBridge 171:3a7713b1edbc 6674 #define EXTI_IMR_IM18 EXTI_IMR_MR18
AnnaBridge 171:3a7713b1edbc 6675 #endif
AnnaBridge 171:3a7713b1edbc 6676 #define EXTI_IMR_IM19 EXTI_IMR_MR19
AnnaBridge 171:3a7713b1edbc 6677 #define EXTI_IMR_IM20 EXTI_IMR_MR20
AnnaBridge 171:3a7713b1edbc 6678 #if defined(EXTI_IMR_MR21)
AnnaBridge 171:3a7713b1edbc 6679 #define EXTI_IMR_IM21 EXTI_IMR_MR21
AnnaBridge 171:3a7713b1edbc 6680 #endif
AnnaBridge 171:3a7713b1edbc 6681 #define EXTI_IMR_IM22 EXTI_IMR_MR22
AnnaBridge 171:3a7713b1edbc 6682 #define EXTI_IMR_IM23 EXTI_IMR_MR23
AnnaBridge 171:3a7713b1edbc 6683 #if defined(EXTI_IMR_MR24)
AnnaBridge 171:3a7713b1edbc 6684 #define EXTI_IMR_IM24 EXTI_IMR_MR24
AnnaBridge 171:3a7713b1edbc 6685 #endif
AnnaBridge 171:3a7713b1edbc 6686 #define EXTI_IMR_IM25 EXTI_IMR_MR25
AnnaBridge 171:3a7713b1edbc 6687 #if defined(EXTI_IMR_MR26)
AnnaBridge 171:3a7713b1edbc 6688 #define EXTI_IMR_IM26 EXTI_IMR_MR26
AnnaBridge 171:3a7713b1edbc 6689 #endif
AnnaBridge 171:3a7713b1edbc 6690 #if defined(EXTI_IMR_MR27)
AnnaBridge 171:3a7713b1edbc 6691 #define EXTI_IMR_IM27 EXTI_IMR_MR27
AnnaBridge 171:3a7713b1edbc 6692 #endif
AnnaBridge 171:3a7713b1edbc 6693 #if defined(EXTI_IMR_MR28)
AnnaBridge 171:3a7713b1edbc 6694 #define EXTI_IMR_IM28 EXTI_IMR_MR28
AnnaBridge 171:3a7713b1edbc 6695 #endif
AnnaBridge 171:3a7713b1edbc 6696 #if defined(EXTI_IMR_MR29)
AnnaBridge 171:3a7713b1edbc 6697 #define EXTI_IMR_IM29 EXTI_IMR_MR29
AnnaBridge 171:3a7713b1edbc 6698 #endif
AnnaBridge 171:3a7713b1edbc 6699 #define EXTI_IMR_IM30 EXTI_IMR_MR30
AnnaBridge 171:3a7713b1edbc 6700 #if defined(EXTI_IMR_MR31)
AnnaBridge 171:3a7713b1edbc 6701 #define EXTI_IMR_IM31 EXTI_IMR_MR31
AnnaBridge 171:3a7713b1edbc 6702 #endif
AnnaBridge 171:3a7713b1edbc 6703
AnnaBridge 171:3a7713b1edbc 6704 #define EXTI_IMR_IM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6705 #define EXTI_IMR_IM_Msk (0xFFFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 6706 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
AnnaBridge 171:3a7713b1edbc 6707
AnnaBridge 171:3a7713b1edbc 6708 /******************* Bit definition for EXTI_EMR register *******************/
AnnaBridge 171:3a7713b1edbc 6709 #define EXTI_EMR_MR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6710 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6711 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
AnnaBridge 171:3a7713b1edbc 6712 #define EXTI_EMR_MR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6713 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6714 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
AnnaBridge 171:3a7713b1edbc 6715 #define EXTI_EMR_MR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6716 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6717 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
AnnaBridge 171:3a7713b1edbc 6718 #define EXTI_EMR_MR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6719 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6720 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
AnnaBridge 171:3a7713b1edbc 6721 #define EXTI_EMR_MR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6722 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6723 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
AnnaBridge 171:3a7713b1edbc 6724 #define EXTI_EMR_MR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6725 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6726 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
AnnaBridge 171:3a7713b1edbc 6727 #define EXTI_EMR_MR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6728 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6729 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
AnnaBridge 171:3a7713b1edbc 6730 #define EXTI_EMR_MR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6731 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6732 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
AnnaBridge 171:3a7713b1edbc 6733 #define EXTI_EMR_MR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6734 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6735 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
AnnaBridge 171:3a7713b1edbc 6736 #define EXTI_EMR_MR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6737 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6738 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
AnnaBridge 171:3a7713b1edbc 6739 #define EXTI_EMR_MR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6740 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6741 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
AnnaBridge 171:3a7713b1edbc 6742 #define EXTI_EMR_MR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6743 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6744 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
AnnaBridge 171:3a7713b1edbc 6745 #define EXTI_EMR_MR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6746 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6747 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
AnnaBridge 171:3a7713b1edbc 6748 #define EXTI_EMR_MR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6749 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6750 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
AnnaBridge 171:3a7713b1edbc 6751 #define EXTI_EMR_MR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6752 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6753 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
AnnaBridge 171:3a7713b1edbc 6754 #define EXTI_EMR_MR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6755 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6756 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
AnnaBridge 171:3a7713b1edbc 6757 #define EXTI_EMR_MR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6758 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6759 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
AnnaBridge 171:3a7713b1edbc 6760 #define EXTI_EMR_MR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 6761 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6762 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
AnnaBridge 171:3a7713b1edbc 6763 #define EXTI_EMR_MR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6764 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6765 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
AnnaBridge 171:3a7713b1edbc 6766 #define EXTI_EMR_MR20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6767 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6768 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
AnnaBridge 171:3a7713b1edbc 6769 #define EXTI_EMR_MR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6770 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6771 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
AnnaBridge 171:3a7713b1edbc 6772 #define EXTI_EMR_MR23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 6773 #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 6774 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
AnnaBridge 171:3a7713b1edbc 6775 #define EXTI_EMR_MR25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 6776 #define EXTI_EMR_MR25_Msk (0x1U << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 6777 #define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */
AnnaBridge 171:3a7713b1edbc 6778 #define EXTI_EMR_MR30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 6779 #define EXTI_EMR_MR30_Msk (0x1U << EXTI_EMR_MR30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 6780 #define EXTI_EMR_MR30 EXTI_EMR_MR30_Msk /*!< Event Mask on line 30 */
AnnaBridge 171:3a7713b1edbc 6781
AnnaBridge 171:3a7713b1edbc 6782 /* References Defines */
AnnaBridge 171:3a7713b1edbc 6783 #define EXTI_EMR_EM0 EXTI_EMR_MR0
AnnaBridge 171:3a7713b1edbc 6784 #define EXTI_EMR_EM1 EXTI_EMR_MR1
AnnaBridge 171:3a7713b1edbc 6785 #define EXTI_EMR_EM2 EXTI_EMR_MR2
AnnaBridge 171:3a7713b1edbc 6786 #define EXTI_EMR_EM3 EXTI_EMR_MR3
AnnaBridge 171:3a7713b1edbc 6787 #define EXTI_EMR_EM4 EXTI_EMR_MR4
AnnaBridge 171:3a7713b1edbc 6788 #define EXTI_EMR_EM5 EXTI_EMR_MR5
AnnaBridge 171:3a7713b1edbc 6789 #define EXTI_EMR_EM6 EXTI_EMR_MR6
AnnaBridge 171:3a7713b1edbc 6790 #define EXTI_EMR_EM7 EXTI_EMR_MR7
AnnaBridge 171:3a7713b1edbc 6791 #define EXTI_EMR_EM8 EXTI_EMR_MR8
AnnaBridge 171:3a7713b1edbc 6792 #define EXTI_EMR_EM9 EXTI_EMR_MR9
AnnaBridge 171:3a7713b1edbc 6793 #define EXTI_EMR_EM10 EXTI_EMR_MR10
AnnaBridge 171:3a7713b1edbc 6794 #define EXTI_EMR_EM11 EXTI_EMR_MR11
AnnaBridge 171:3a7713b1edbc 6795 #define EXTI_EMR_EM12 EXTI_EMR_MR12
AnnaBridge 171:3a7713b1edbc 6796 #define EXTI_EMR_EM13 EXTI_EMR_MR13
AnnaBridge 171:3a7713b1edbc 6797 #define EXTI_EMR_EM14 EXTI_EMR_MR14
AnnaBridge 171:3a7713b1edbc 6798 #define EXTI_EMR_EM15 EXTI_EMR_MR15
AnnaBridge 171:3a7713b1edbc 6799 #define EXTI_EMR_EM16 EXTI_EMR_MR16
AnnaBridge 171:3a7713b1edbc 6800 #define EXTI_EMR_EM17 EXTI_EMR_MR17
AnnaBridge 171:3a7713b1edbc 6801 #if defined(EXTI_EMR_MR18)
AnnaBridge 171:3a7713b1edbc 6802 #define EXTI_EMR_EM18 EXTI_EMR_MR18
AnnaBridge 171:3a7713b1edbc 6803 #endif
AnnaBridge 171:3a7713b1edbc 6804 #define EXTI_EMR_EM19 EXTI_EMR_MR19
AnnaBridge 171:3a7713b1edbc 6805 #define EXTI_EMR_EM20 EXTI_EMR_MR20
AnnaBridge 171:3a7713b1edbc 6806 #if defined(EXTI_EMR_MR21)
AnnaBridge 171:3a7713b1edbc 6807 #define EXTI_EMR_EM21 EXTI_EMR_MR21
AnnaBridge 171:3a7713b1edbc 6808 #endif
AnnaBridge 171:3a7713b1edbc 6809 #define EXTI_EMR_EM22 EXTI_EMR_MR22
AnnaBridge 171:3a7713b1edbc 6810 #define EXTI_EMR_EM23 EXTI_EMR_MR23
AnnaBridge 171:3a7713b1edbc 6811 #if defined(EXTI_EMR_MR24)
AnnaBridge 171:3a7713b1edbc 6812 #define EXTI_EMR_EM24 EXTI_EMR_MR24
AnnaBridge 171:3a7713b1edbc 6813 #endif
AnnaBridge 171:3a7713b1edbc 6814 #define EXTI_EMR_EM25 EXTI_EMR_MR25
AnnaBridge 171:3a7713b1edbc 6815 #if defined(EXTI_EMR_MR26)
AnnaBridge 171:3a7713b1edbc 6816 #define EXTI_EMR_EM26 EXTI_EMR_MR26
AnnaBridge 171:3a7713b1edbc 6817 #endif
AnnaBridge 171:3a7713b1edbc 6818 #if defined(EXTI_EMR_MR27)
AnnaBridge 171:3a7713b1edbc 6819 #define EXTI_EMR_EM27 EXTI_EMR_MR27
AnnaBridge 171:3a7713b1edbc 6820 #endif
AnnaBridge 171:3a7713b1edbc 6821 #if defined(EXTI_EMR_MR28)
AnnaBridge 171:3a7713b1edbc 6822 #define EXTI_EMR_EM28 EXTI_EMR_MR28
AnnaBridge 171:3a7713b1edbc 6823 #endif
AnnaBridge 171:3a7713b1edbc 6824 #if defined(EXTI_EMR_MR29)
AnnaBridge 171:3a7713b1edbc 6825 #define EXTI_EMR_EM29 EXTI_EMR_MR29
AnnaBridge 171:3a7713b1edbc 6826 #endif
AnnaBridge 171:3a7713b1edbc 6827 #define EXTI_EMR_EM30 EXTI_EMR_MR30
AnnaBridge 171:3a7713b1edbc 6828 #if defined(EXTI_EMR_MR31)
AnnaBridge 171:3a7713b1edbc 6829 #define EXTI_EMR_EM31 EXTI_EMR_MR31
AnnaBridge 171:3a7713b1edbc 6830 #endif
AnnaBridge 171:3a7713b1edbc 6831
AnnaBridge 171:3a7713b1edbc 6832 /****************** Bit definition for EXTI_RTSR register *******************/
AnnaBridge 171:3a7713b1edbc 6833 #define EXTI_RTSR_TR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6834 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6835 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
AnnaBridge 171:3a7713b1edbc 6836 #define EXTI_RTSR_TR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6837 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6838 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
AnnaBridge 171:3a7713b1edbc 6839 #define EXTI_RTSR_TR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6840 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6841 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
AnnaBridge 171:3a7713b1edbc 6842 #define EXTI_RTSR_TR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6843 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6844 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
AnnaBridge 171:3a7713b1edbc 6845 #define EXTI_RTSR_TR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6846 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6847 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
AnnaBridge 171:3a7713b1edbc 6848 #define EXTI_RTSR_TR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6849 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6850 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
AnnaBridge 171:3a7713b1edbc 6851 #define EXTI_RTSR_TR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6852 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6853 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
AnnaBridge 171:3a7713b1edbc 6854 #define EXTI_RTSR_TR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6855 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6856 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
AnnaBridge 171:3a7713b1edbc 6857 #define EXTI_RTSR_TR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6858 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6859 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
AnnaBridge 171:3a7713b1edbc 6860 #define EXTI_RTSR_TR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6861 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6862 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
AnnaBridge 171:3a7713b1edbc 6863 #define EXTI_RTSR_TR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6864 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6865 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
AnnaBridge 171:3a7713b1edbc 6866 #define EXTI_RTSR_TR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6867 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6868 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
AnnaBridge 171:3a7713b1edbc 6869 #define EXTI_RTSR_TR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6870 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6871 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
AnnaBridge 171:3a7713b1edbc 6872 #define EXTI_RTSR_TR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6873 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6874 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
AnnaBridge 171:3a7713b1edbc 6875 #define EXTI_RTSR_TR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6876 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6877 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
AnnaBridge 171:3a7713b1edbc 6878 #define EXTI_RTSR_TR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6879 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6880 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
AnnaBridge 171:3a7713b1edbc 6881 #define EXTI_RTSR_TR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6882 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6883 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
AnnaBridge 171:3a7713b1edbc 6884 #define EXTI_RTSR_TR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 6885 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6886 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
AnnaBridge 171:3a7713b1edbc 6887 #define EXTI_RTSR_TR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6888 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6889 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
AnnaBridge 171:3a7713b1edbc 6890 #define EXTI_RTSR_TR20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6891 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6892 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
AnnaBridge 171:3a7713b1edbc 6893 #define EXTI_RTSR_TR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 6894 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6895 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
AnnaBridge 171:3a7713b1edbc 6896 #define EXTI_RTSR_TR30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 6897 #define EXTI_RTSR_TR30_Msk (0x1U << EXTI_RTSR_TR30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 6898 #define EXTI_RTSR_TR30 EXTI_RTSR_TR30_Msk /*!< Rising trigger event configuration bit of line 30 */
AnnaBridge 171:3a7713b1edbc 6899
AnnaBridge 171:3a7713b1edbc 6900 /* References Defines */
AnnaBridge 171:3a7713b1edbc 6901 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
AnnaBridge 171:3a7713b1edbc 6902 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
AnnaBridge 171:3a7713b1edbc 6903 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
AnnaBridge 171:3a7713b1edbc 6904 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
AnnaBridge 171:3a7713b1edbc 6905 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
AnnaBridge 171:3a7713b1edbc 6906 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
AnnaBridge 171:3a7713b1edbc 6907 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
AnnaBridge 171:3a7713b1edbc 6908 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
AnnaBridge 171:3a7713b1edbc 6909 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
AnnaBridge 171:3a7713b1edbc 6910 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
AnnaBridge 171:3a7713b1edbc 6911 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
AnnaBridge 171:3a7713b1edbc 6912 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
AnnaBridge 171:3a7713b1edbc 6913 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
AnnaBridge 171:3a7713b1edbc 6914 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
AnnaBridge 171:3a7713b1edbc 6915 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
AnnaBridge 171:3a7713b1edbc 6916 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
AnnaBridge 171:3a7713b1edbc 6917 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
AnnaBridge 171:3a7713b1edbc 6918 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
AnnaBridge 171:3a7713b1edbc 6919 #if defined(EXTI_RTSR_TR18)
AnnaBridge 171:3a7713b1edbc 6920 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18
AnnaBridge 171:3a7713b1edbc 6921 #endif
AnnaBridge 171:3a7713b1edbc 6922 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
AnnaBridge 171:3a7713b1edbc 6923 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20
AnnaBridge 171:3a7713b1edbc 6924 #if defined(EXTI_RTSR_TR21)
AnnaBridge 171:3a7713b1edbc 6925 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21
AnnaBridge 171:3a7713b1edbc 6926 #endif
AnnaBridge 171:3a7713b1edbc 6927 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22
AnnaBridge 171:3a7713b1edbc 6928 #if defined(EXTI_RTSR_TR23)
AnnaBridge 171:3a7713b1edbc 6929 #define EXTI_RTSR_RT23 EXTI_RTSR_TR23
AnnaBridge 171:3a7713b1edbc 6930 #endif
AnnaBridge 171:3a7713b1edbc 6931 #if defined(EXTI_RTSR_TR24)
AnnaBridge 171:3a7713b1edbc 6932 #define EXTI_RTSR_RT24 EXTI_RTSR_TR24
AnnaBridge 171:3a7713b1edbc 6933 #endif
AnnaBridge 171:3a7713b1edbc 6934 #if defined(EXTI_RTSR_TR25)
AnnaBridge 171:3a7713b1edbc 6935 #define EXTI_RTSR_RT25 EXTI_RTSR_TR25
AnnaBridge 171:3a7713b1edbc 6936 #endif
AnnaBridge 171:3a7713b1edbc 6937 #if defined(EXTI_RTSR_TR26)
AnnaBridge 171:3a7713b1edbc 6938 #define EXTI_RTSR_RT26 EXTI_RTSR_TR26
AnnaBridge 171:3a7713b1edbc 6939 #endif
AnnaBridge 171:3a7713b1edbc 6940 #if defined(EXTI_RTSR_TR27)
AnnaBridge 171:3a7713b1edbc 6941 #define EXTI_RTSR_RT27 EXTI_RTSR_TR27
AnnaBridge 171:3a7713b1edbc 6942 #endif
AnnaBridge 171:3a7713b1edbc 6943 #if defined(EXTI_RTSR_TR28)
AnnaBridge 171:3a7713b1edbc 6944 #define EXTI_RTSR_RT28 EXTI_RTSR_TR28
AnnaBridge 171:3a7713b1edbc 6945 #endif
AnnaBridge 171:3a7713b1edbc 6946 #if defined(EXTI_RTSR_TR29)
AnnaBridge 171:3a7713b1edbc 6947 #define EXTI_RTSR_RT29 EXTI_RTSR_TR29
AnnaBridge 171:3a7713b1edbc 6948 #endif
AnnaBridge 171:3a7713b1edbc 6949 #define EXTI_RTSR_RT30 EXTI_RTSR_TR30
AnnaBridge 171:3a7713b1edbc 6950 #if defined(EXTI_RTSR_TR31)
AnnaBridge 171:3a7713b1edbc 6951 #define EXTI_RTSR_RT31 EXTI_RTSR_TR31
AnnaBridge 171:3a7713b1edbc 6952 #endif
AnnaBridge 171:3a7713b1edbc 6953
AnnaBridge 171:3a7713b1edbc 6954 /****************** Bit definition for EXTI_FTSR register *******************/
AnnaBridge 171:3a7713b1edbc 6955 #define EXTI_FTSR_TR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6956 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6957 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
AnnaBridge 171:3a7713b1edbc 6958 #define EXTI_FTSR_TR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6959 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6960 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
AnnaBridge 171:3a7713b1edbc 6961 #define EXTI_FTSR_TR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6962 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6963 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
AnnaBridge 171:3a7713b1edbc 6964 #define EXTI_FTSR_TR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6965 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6966 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
AnnaBridge 171:3a7713b1edbc 6967 #define EXTI_FTSR_TR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6968 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6969 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
AnnaBridge 171:3a7713b1edbc 6970 #define EXTI_FTSR_TR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6971 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6972 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
AnnaBridge 171:3a7713b1edbc 6973 #define EXTI_FTSR_TR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6974 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6975 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
AnnaBridge 171:3a7713b1edbc 6976 #define EXTI_FTSR_TR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6977 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6978 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
AnnaBridge 171:3a7713b1edbc 6979 #define EXTI_FTSR_TR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6980 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6981 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
AnnaBridge 171:3a7713b1edbc 6982 #define EXTI_FTSR_TR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6983 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6984 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
AnnaBridge 171:3a7713b1edbc 6985 #define EXTI_FTSR_TR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6986 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6987 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
AnnaBridge 171:3a7713b1edbc 6988 #define EXTI_FTSR_TR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6989 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6990 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
AnnaBridge 171:3a7713b1edbc 6991 #define EXTI_FTSR_TR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6992 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6993 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
AnnaBridge 171:3a7713b1edbc 6994 #define EXTI_FTSR_TR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 6995 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6996 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
AnnaBridge 171:3a7713b1edbc 6997 #define EXTI_FTSR_TR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6998 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6999 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
AnnaBridge 171:3a7713b1edbc 7000 #define EXTI_FTSR_TR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7001 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7002 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
AnnaBridge 171:3a7713b1edbc 7003 #define EXTI_FTSR_TR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7004 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7005 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
AnnaBridge 171:3a7713b1edbc 7006 #define EXTI_FTSR_TR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 7007 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7008 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
AnnaBridge 171:3a7713b1edbc 7009 #define EXTI_FTSR_TR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 7010 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7011 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
AnnaBridge 171:3a7713b1edbc 7012 #define EXTI_FTSR_TR20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 7013 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 7014 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
AnnaBridge 171:3a7713b1edbc 7015 #define EXTI_FTSR_TR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 7016 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 7017 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
AnnaBridge 171:3a7713b1edbc 7018 #define EXTI_FTSR_TR30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 7019 #define EXTI_FTSR_TR30_Msk (0x1U << EXTI_FTSR_TR30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 7020 #define EXTI_FTSR_TR30 EXTI_FTSR_TR30_Msk /*!< Falling trigger event configuration bit of line 30 */
AnnaBridge 171:3a7713b1edbc 7021
AnnaBridge 171:3a7713b1edbc 7022 /* References Defines */
AnnaBridge 171:3a7713b1edbc 7023 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
AnnaBridge 171:3a7713b1edbc 7024 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
AnnaBridge 171:3a7713b1edbc 7025 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
AnnaBridge 171:3a7713b1edbc 7026 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
AnnaBridge 171:3a7713b1edbc 7027 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
AnnaBridge 171:3a7713b1edbc 7028 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
AnnaBridge 171:3a7713b1edbc 7029 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
AnnaBridge 171:3a7713b1edbc 7030 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
AnnaBridge 171:3a7713b1edbc 7031 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
AnnaBridge 171:3a7713b1edbc 7032 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
AnnaBridge 171:3a7713b1edbc 7033 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
AnnaBridge 171:3a7713b1edbc 7034 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
AnnaBridge 171:3a7713b1edbc 7035 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
AnnaBridge 171:3a7713b1edbc 7036 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
AnnaBridge 171:3a7713b1edbc 7037 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
AnnaBridge 171:3a7713b1edbc 7038 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
AnnaBridge 171:3a7713b1edbc 7039 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
AnnaBridge 171:3a7713b1edbc 7040 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
AnnaBridge 171:3a7713b1edbc 7041 #if defined(EXTI_FTSR_TR18)
AnnaBridge 171:3a7713b1edbc 7042 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18
AnnaBridge 171:3a7713b1edbc 7043 #endif
AnnaBridge 171:3a7713b1edbc 7044 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
AnnaBridge 171:3a7713b1edbc 7045 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20
AnnaBridge 171:3a7713b1edbc 7046 #if defined(EXTI_FTSR_TR21)
AnnaBridge 171:3a7713b1edbc 7047 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21
AnnaBridge 171:3a7713b1edbc 7048 #endif
AnnaBridge 171:3a7713b1edbc 7049 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22
AnnaBridge 171:3a7713b1edbc 7050 #if defined(EXTI_FTSR_TR23)
AnnaBridge 171:3a7713b1edbc 7051 #define EXTI_FTSR_FT23 EXTI_FTSR_TR23
AnnaBridge 171:3a7713b1edbc 7052 #endif
AnnaBridge 171:3a7713b1edbc 7053 #if defined(EXTI_FTSR_TR24)
AnnaBridge 171:3a7713b1edbc 7054 #define EXTI_FTSR_FT24 EXTI_FTSR_TR24
AnnaBridge 171:3a7713b1edbc 7055 #endif
AnnaBridge 171:3a7713b1edbc 7056 #if defined(EXTI_FTSR_TR25)
AnnaBridge 171:3a7713b1edbc 7057 #define EXTI_FTSR_FT25 EXTI_FTSR_TR25
AnnaBridge 171:3a7713b1edbc 7058 #endif
AnnaBridge 171:3a7713b1edbc 7059 #if defined(EXTI_FTSR_TR26)
AnnaBridge 171:3a7713b1edbc 7060 #define EXTI_FTSR_FT26 EXTI_FTSR_TR26
AnnaBridge 171:3a7713b1edbc 7061 #endif
AnnaBridge 171:3a7713b1edbc 7062 #if defined(EXTI_FTSR_TR27)
AnnaBridge 171:3a7713b1edbc 7063 #define EXTI_FTSR_FT27 EXTI_FTSR_TR27
AnnaBridge 171:3a7713b1edbc 7064 #endif
AnnaBridge 171:3a7713b1edbc 7065 #if defined(EXTI_FTSR_TR28)
AnnaBridge 171:3a7713b1edbc 7066 #define EXTI_FTSR_FT28 EXTI_FTSR_TR28
AnnaBridge 171:3a7713b1edbc 7067 #endif
AnnaBridge 171:3a7713b1edbc 7068 #if defined(EXTI_FTSR_TR29)
AnnaBridge 171:3a7713b1edbc 7069 #define EXTI_FTSR_FT29 EXTI_FTSR_TR29
AnnaBridge 171:3a7713b1edbc 7070 #endif
AnnaBridge 171:3a7713b1edbc 7071 #define EXTI_FTSR_FT30 EXTI_FTSR_TR30
AnnaBridge 171:3a7713b1edbc 7072 #if defined(EXTI_FTSR_TR31)
AnnaBridge 171:3a7713b1edbc 7073 #define EXTI_FTSR_FT31 EXTI_FTSR_TR31
AnnaBridge 171:3a7713b1edbc 7074 #endif
AnnaBridge 171:3a7713b1edbc 7075
AnnaBridge 171:3a7713b1edbc 7076 /****************** Bit definition for EXTI_SWIER register ******************/
AnnaBridge 171:3a7713b1edbc 7077 #define EXTI_SWIER_SWIER0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7078 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7079 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
AnnaBridge 171:3a7713b1edbc 7080 #define EXTI_SWIER_SWIER1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7081 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7082 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
AnnaBridge 171:3a7713b1edbc 7083 #define EXTI_SWIER_SWIER2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7084 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7085 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
AnnaBridge 171:3a7713b1edbc 7086 #define EXTI_SWIER_SWIER3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7087 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7088 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
AnnaBridge 171:3a7713b1edbc 7089 #define EXTI_SWIER_SWIER4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7090 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7091 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
AnnaBridge 171:3a7713b1edbc 7092 #define EXTI_SWIER_SWIER5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7093 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7094 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
AnnaBridge 171:3a7713b1edbc 7095 #define EXTI_SWIER_SWIER6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7096 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7097 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
AnnaBridge 171:3a7713b1edbc 7098 #define EXTI_SWIER_SWIER7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7099 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7100 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
AnnaBridge 171:3a7713b1edbc 7101 #define EXTI_SWIER_SWIER8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7102 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7103 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
AnnaBridge 171:3a7713b1edbc 7104 #define EXTI_SWIER_SWIER9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7105 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7106 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
AnnaBridge 171:3a7713b1edbc 7107 #define EXTI_SWIER_SWIER10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7108 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7109 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
AnnaBridge 171:3a7713b1edbc 7110 #define EXTI_SWIER_SWIER11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7111 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7112 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
AnnaBridge 171:3a7713b1edbc 7113 #define EXTI_SWIER_SWIER12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7114 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7115 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
AnnaBridge 171:3a7713b1edbc 7116 #define EXTI_SWIER_SWIER13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 7117 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7118 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
AnnaBridge 171:3a7713b1edbc 7119 #define EXTI_SWIER_SWIER14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7120 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7121 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
AnnaBridge 171:3a7713b1edbc 7122 #define EXTI_SWIER_SWIER15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7123 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7124 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
AnnaBridge 171:3a7713b1edbc 7125 #define EXTI_SWIER_SWIER16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7126 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7127 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
AnnaBridge 171:3a7713b1edbc 7128 #define EXTI_SWIER_SWIER17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 7129 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7130 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
AnnaBridge 171:3a7713b1edbc 7131 #define EXTI_SWIER_SWIER19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 7132 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7133 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
AnnaBridge 171:3a7713b1edbc 7134 #define EXTI_SWIER_SWIER20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 7135 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 7136 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
AnnaBridge 171:3a7713b1edbc 7137 #define EXTI_SWIER_SWIER22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 7138 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 7139 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
AnnaBridge 171:3a7713b1edbc 7140 #define EXTI_SWIER_SWIER30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 7141 #define EXTI_SWIER_SWIER30_Msk (0x1U << EXTI_SWIER_SWIER30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 7142 #define EXTI_SWIER_SWIER30 EXTI_SWIER_SWIER30_Msk /*!< Software Interrupt on line 30 */
AnnaBridge 171:3a7713b1edbc 7143
AnnaBridge 171:3a7713b1edbc 7144 /* References Defines */
AnnaBridge 171:3a7713b1edbc 7145 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
AnnaBridge 171:3a7713b1edbc 7146 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
AnnaBridge 171:3a7713b1edbc 7147 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
AnnaBridge 171:3a7713b1edbc 7148 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
AnnaBridge 171:3a7713b1edbc 7149 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
AnnaBridge 171:3a7713b1edbc 7150 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
AnnaBridge 171:3a7713b1edbc 7151 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
AnnaBridge 171:3a7713b1edbc 7152 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
AnnaBridge 171:3a7713b1edbc 7153 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
AnnaBridge 171:3a7713b1edbc 7154 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
AnnaBridge 171:3a7713b1edbc 7155 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
AnnaBridge 171:3a7713b1edbc 7156 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
AnnaBridge 171:3a7713b1edbc 7157 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
AnnaBridge 171:3a7713b1edbc 7158 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
AnnaBridge 171:3a7713b1edbc 7159 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
AnnaBridge 171:3a7713b1edbc 7160 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
AnnaBridge 171:3a7713b1edbc 7161 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
AnnaBridge 171:3a7713b1edbc 7162 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
AnnaBridge 171:3a7713b1edbc 7163 #if defined(EXTI_SWIER_SWIER18)
AnnaBridge 171:3a7713b1edbc 7164 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
AnnaBridge 171:3a7713b1edbc 7165 #endif
AnnaBridge 171:3a7713b1edbc 7166 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
AnnaBridge 171:3a7713b1edbc 7167 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
AnnaBridge 171:3a7713b1edbc 7168 #if defined(EXTI_SWIER_SWIER21)
AnnaBridge 171:3a7713b1edbc 7169 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
AnnaBridge 171:3a7713b1edbc 7170 #endif
AnnaBridge 171:3a7713b1edbc 7171 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
AnnaBridge 171:3a7713b1edbc 7172 #if defined(EXTI_SWIER_SWIER23)
AnnaBridge 171:3a7713b1edbc 7173 #define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
AnnaBridge 171:3a7713b1edbc 7174 #endif
AnnaBridge 171:3a7713b1edbc 7175 #if defined(EXTI_SWIER_SWIER24)
AnnaBridge 171:3a7713b1edbc 7176 #define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24
AnnaBridge 171:3a7713b1edbc 7177 #endif
AnnaBridge 171:3a7713b1edbc 7178 #if defined(EXTI_SWIER_SWIER25)
AnnaBridge 171:3a7713b1edbc 7179 #define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25
AnnaBridge 171:3a7713b1edbc 7180 #endif
AnnaBridge 171:3a7713b1edbc 7181 #if defined(EXTI_SWIER_SWIER26)
AnnaBridge 171:3a7713b1edbc 7182 #define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26
AnnaBridge 171:3a7713b1edbc 7183 #endif
AnnaBridge 171:3a7713b1edbc 7184 #if defined(EXTI_SWIER_SWIER27)
AnnaBridge 171:3a7713b1edbc 7185 #define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27
AnnaBridge 171:3a7713b1edbc 7186 #endif
AnnaBridge 171:3a7713b1edbc 7187 #if defined(EXTI_SWIER_SWIER28)
AnnaBridge 171:3a7713b1edbc 7188 #define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28
AnnaBridge 171:3a7713b1edbc 7189 #endif
AnnaBridge 171:3a7713b1edbc 7190 #if defined(EXTI_SWIER_SWIER29)
AnnaBridge 171:3a7713b1edbc 7191 #define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
AnnaBridge 171:3a7713b1edbc 7192 #endif
AnnaBridge 171:3a7713b1edbc 7193 #define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
AnnaBridge 171:3a7713b1edbc 7194 #if defined(EXTI_SWIER_SWIER31)
AnnaBridge 171:3a7713b1edbc 7195 #define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
AnnaBridge 171:3a7713b1edbc 7196 #endif
AnnaBridge 171:3a7713b1edbc 7197
AnnaBridge 171:3a7713b1edbc 7198 /******************* Bit definition for EXTI_PR register ********************/
AnnaBridge 171:3a7713b1edbc 7199 #define EXTI_PR_PR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7200 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7201 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
AnnaBridge 171:3a7713b1edbc 7202 #define EXTI_PR_PR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7203 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7204 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
AnnaBridge 171:3a7713b1edbc 7205 #define EXTI_PR_PR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7206 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7207 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
AnnaBridge 171:3a7713b1edbc 7208 #define EXTI_PR_PR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7209 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7210 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
AnnaBridge 171:3a7713b1edbc 7211 #define EXTI_PR_PR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7212 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7213 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
AnnaBridge 171:3a7713b1edbc 7214 #define EXTI_PR_PR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7215 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7216 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
AnnaBridge 171:3a7713b1edbc 7217 #define EXTI_PR_PR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7218 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7219 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
AnnaBridge 171:3a7713b1edbc 7220 #define EXTI_PR_PR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7221 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7222 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
AnnaBridge 171:3a7713b1edbc 7223 #define EXTI_PR_PR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7224 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7225 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
AnnaBridge 171:3a7713b1edbc 7226 #define EXTI_PR_PR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7227 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7228 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
AnnaBridge 171:3a7713b1edbc 7229 #define EXTI_PR_PR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7230 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7231 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
AnnaBridge 171:3a7713b1edbc 7232 #define EXTI_PR_PR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7233 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7234 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
AnnaBridge 171:3a7713b1edbc 7235 #define EXTI_PR_PR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7236 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7237 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
AnnaBridge 171:3a7713b1edbc 7238 #define EXTI_PR_PR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 7239 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7240 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
AnnaBridge 171:3a7713b1edbc 7241 #define EXTI_PR_PR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7242 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7243 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
AnnaBridge 171:3a7713b1edbc 7244 #define EXTI_PR_PR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7245 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7246 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
AnnaBridge 171:3a7713b1edbc 7247 #define EXTI_PR_PR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7248 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7249 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
AnnaBridge 171:3a7713b1edbc 7250 #define EXTI_PR_PR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 7251 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7252 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
AnnaBridge 171:3a7713b1edbc 7253 #define EXTI_PR_PR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 7254 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7255 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
AnnaBridge 171:3a7713b1edbc 7256 #define EXTI_PR_PR20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 7257 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 7258 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
AnnaBridge 171:3a7713b1edbc 7259 #define EXTI_PR_PR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 7260 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 7261 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
AnnaBridge 171:3a7713b1edbc 7262 #define EXTI_PR_PR30_Pos (30U)
AnnaBridge 171:3a7713b1edbc 7263 #define EXTI_PR_PR30_Msk (0x1U << EXTI_PR_PR30_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 7264 #define EXTI_PR_PR30 EXTI_PR_PR30_Msk /*!< Pending bit for line 30 */
AnnaBridge 171:3a7713b1edbc 7265
AnnaBridge 171:3a7713b1edbc 7266 /* References Defines */
AnnaBridge 171:3a7713b1edbc 7267 #define EXTI_PR_PIF0 EXTI_PR_PR0
AnnaBridge 171:3a7713b1edbc 7268 #define EXTI_PR_PIF1 EXTI_PR_PR1
AnnaBridge 171:3a7713b1edbc 7269 #define EXTI_PR_PIF2 EXTI_PR_PR2
AnnaBridge 171:3a7713b1edbc 7270 #define EXTI_PR_PIF3 EXTI_PR_PR3
AnnaBridge 171:3a7713b1edbc 7271 #define EXTI_PR_PIF4 EXTI_PR_PR4
AnnaBridge 171:3a7713b1edbc 7272 #define EXTI_PR_PIF5 EXTI_PR_PR5
AnnaBridge 171:3a7713b1edbc 7273 #define EXTI_PR_PIF6 EXTI_PR_PR6
AnnaBridge 171:3a7713b1edbc 7274 #define EXTI_PR_PIF6 EXTI_PR_PR6
AnnaBridge 171:3a7713b1edbc 7275 #define EXTI_PR_PIF7 EXTI_PR_PR7
AnnaBridge 171:3a7713b1edbc 7276 #define EXTI_PR_PIF8 EXTI_PR_PR8
AnnaBridge 171:3a7713b1edbc 7277 #define EXTI_PR_PIF9 EXTI_PR_PR9
AnnaBridge 171:3a7713b1edbc 7278 #define EXTI_PR_PIF10 EXTI_PR_PR10
AnnaBridge 171:3a7713b1edbc 7279 #define EXTI_PR_PIF11 EXTI_PR_PR11
AnnaBridge 171:3a7713b1edbc 7280 #define EXTI_PR_PIF12 EXTI_PR_PR12
AnnaBridge 171:3a7713b1edbc 7281 #define EXTI_PR_PIF13 EXTI_PR_PR13
AnnaBridge 171:3a7713b1edbc 7282 #define EXTI_PR_PIF14 EXTI_PR_PR14
AnnaBridge 171:3a7713b1edbc 7283 #define EXTI_PR_PIF15 EXTI_PR_PR15
AnnaBridge 171:3a7713b1edbc 7284 #define EXTI_PR_PIF16 EXTI_PR_PR16
AnnaBridge 171:3a7713b1edbc 7285 #define EXTI_PR_PIF17 EXTI_PR_PR17
AnnaBridge 171:3a7713b1edbc 7286 #if defined(EXTI_PR_PR18)
AnnaBridge 171:3a7713b1edbc 7287 #define EXTI_PR_PIF18 EXTI_PR_PR18
AnnaBridge 171:3a7713b1edbc 7288 #endif
AnnaBridge 171:3a7713b1edbc 7289 #define EXTI_PR_PIF19 EXTI_PR_PR19
AnnaBridge 171:3a7713b1edbc 7290 #define EXTI_PR_PIF20 EXTI_PR_PR20
AnnaBridge 171:3a7713b1edbc 7291 #if defined(EXTI_PR_PR21)
AnnaBridge 171:3a7713b1edbc 7292 #define EXTI_PR_PIF21 EXTI_PR_PR21
AnnaBridge 171:3a7713b1edbc 7293 #endif
AnnaBridge 171:3a7713b1edbc 7294 #define EXTI_PR_PIF22 EXTI_PR_PR22
AnnaBridge 171:3a7713b1edbc 7295 #if defined(EXTI_PR_PR23)
AnnaBridge 171:3a7713b1edbc 7296 #define EXTI_PR_PIF23 EXTI_PR_PR23
AnnaBridge 171:3a7713b1edbc 7297 #endif
AnnaBridge 171:3a7713b1edbc 7298 #if defined(EXTI_PR_PR24)
AnnaBridge 171:3a7713b1edbc 7299 #define EXTI_PR_PIF24 EXTI_PR_PR24
AnnaBridge 171:3a7713b1edbc 7300 #endif
AnnaBridge 171:3a7713b1edbc 7301 #if defined(EXTI_PR_PR25)
AnnaBridge 171:3a7713b1edbc 7302 #define EXTI_PR_PIF25 EXTI_PR_PR25
AnnaBridge 171:3a7713b1edbc 7303 #endif
AnnaBridge 171:3a7713b1edbc 7304 #if defined(EXTI_PR_PR26)
AnnaBridge 171:3a7713b1edbc 7305 #define EXTI_PR_PIF26 EXTI_PR_PR26
AnnaBridge 171:3a7713b1edbc 7306 #endif
AnnaBridge 171:3a7713b1edbc 7307 #if defined(EXTI_PR_PR27)
AnnaBridge 171:3a7713b1edbc 7308 #define EXTI_PR_PIF27 EXTI_PR_PR27
AnnaBridge 171:3a7713b1edbc 7309 #endif
AnnaBridge 171:3a7713b1edbc 7310 #if defined(EXTI_PR_PR28)
AnnaBridge 171:3a7713b1edbc 7311 #define EXTI_PR_PIF28 EXTI_PR_PR28
AnnaBridge 171:3a7713b1edbc 7312 #endif
AnnaBridge 171:3a7713b1edbc 7313 #if defined(EXTI_PR_PR29)
AnnaBridge 171:3a7713b1edbc 7314 #define EXTI_PR_PIF29 EXTI_PR_PR29
AnnaBridge 171:3a7713b1edbc 7315 #endif
AnnaBridge 171:3a7713b1edbc 7316 #define EXTI_PR_PIF30 EXTI_PR_PR30
AnnaBridge 171:3a7713b1edbc 7317 #if defined(EXTI_PR_PR31)
AnnaBridge 171:3a7713b1edbc 7318 #define EXTI_PR_PIF31 EXTI_PR_PR31
AnnaBridge 171:3a7713b1edbc 7319 #endif
AnnaBridge 171:3a7713b1edbc 7320
AnnaBridge 171:3a7713b1edbc 7321 #define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */
AnnaBridge 171:3a7713b1edbc 7322
AnnaBridge 171:3a7713b1edbc 7323 /******************* Bit definition for EXTI_IMR2 register ******************/
AnnaBridge 171:3a7713b1edbc 7324 #define EXTI_IMR2_MR32_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7325 #define EXTI_IMR2_MR32_Msk (0x1U << EXTI_IMR2_MR32_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7326 #define EXTI_IMR2_MR32 EXTI_IMR2_MR32_Msk /*!< Interrupt Mask on line 32 */
AnnaBridge 171:3a7713b1edbc 7327
AnnaBridge 171:3a7713b1edbc 7328 /* References Defines */
AnnaBridge 171:3a7713b1edbc 7329
AnnaBridge 171:3a7713b1edbc 7330 #define EXTI_IMR2_IM32 EXTI_IMR2_MR32
AnnaBridge 171:3a7713b1edbc 7331 #if defined(EXTI_IMR2_MR33)
AnnaBridge 171:3a7713b1edbc 7332 #define EXTI_IMR2_IM33 EXTI_IMR2_MR33
AnnaBridge 171:3a7713b1edbc 7333 #endif
AnnaBridge 171:3a7713b1edbc 7334 #if defined(EXTI_IMR2_MR34)
AnnaBridge 171:3a7713b1edbc 7335 #define EXTI_IMR2_IM34 EXTI_IMR2_MR34
AnnaBridge 171:3a7713b1edbc 7336 #endif
AnnaBridge 171:3a7713b1edbc 7337 #if defined(EXTI_IMR2_MR35)
AnnaBridge 171:3a7713b1edbc 7338 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35
AnnaBridge 171:3a7713b1edbc 7339 #endif
AnnaBridge 171:3a7713b1edbc 7340
AnnaBridge 171:3a7713b1edbc 7341 #if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
AnnaBridge 171:3a7713b1edbc 7342 #define EXTI_IMR2_IM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7343 #define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7344 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
AnnaBridge 171:3a7713b1edbc 7345 #elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
AnnaBridge 171:3a7713b1edbc 7346 #define EXTI_IMR2_IM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7347 #define EXTI_IMR2_IM_Msk (0xDU << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */
AnnaBridge 171:3a7713b1edbc 7348 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
AnnaBridge 171:3a7713b1edbc 7349 #else
AnnaBridge 171:3a7713b1edbc 7350 #define EXTI_IMR2_IM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7351 #define EXTI_IMR2_IM_Msk (0x1U << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7352 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
AnnaBridge 171:3a7713b1edbc 7353 #endif
AnnaBridge 171:3a7713b1edbc 7354
AnnaBridge 171:3a7713b1edbc 7355 /******************* Bit definition for EXTI_EMR2 ****************************/
AnnaBridge 171:3a7713b1edbc 7356 #define EXTI_EMR2_MR32_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7357 #define EXTI_EMR2_MR32_Msk (0x1U << EXTI_EMR2_MR32_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7358 #define EXTI_EMR2_MR32 EXTI_EMR2_MR32_Msk /*!< Event Mask on line 32 */
AnnaBridge 171:3a7713b1edbc 7359
AnnaBridge 171:3a7713b1edbc 7360 /* References Defines */
AnnaBridge 171:3a7713b1edbc 7361 #define EXTI_EMR2_EM32 EXTI_EMR2_MR32
AnnaBridge 171:3a7713b1edbc 7362 #if defined(EXTI_EMR2_MR33)
AnnaBridge 171:3a7713b1edbc 7363 #define EXTI_EMR2_EM33 EXTI_EMR2_MR33
AnnaBridge 171:3a7713b1edbc 7364 #endif
AnnaBridge 171:3a7713b1edbc 7365 #if defined(EXTI_EMR2_MR34)
AnnaBridge 171:3a7713b1edbc 7366 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34
AnnaBridge 171:3a7713b1edbc 7367 #endif
AnnaBridge 171:3a7713b1edbc 7368 #if defined(EXTI_EMR2_MR35)
AnnaBridge 171:3a7713b1edbc 7369 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
AnnaBridge 171:3a7713b1edbc 7370 #endif
AnnaBridge 171:3a7713b1edbc 7371
AnnaBridge 171:3a7713b1edbc 7372 #if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
AnnaBridge 171:3a7713b1edbc 7373 #define EXTI_EMR2_EM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7374 #define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7375 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
AnnaBridge 171:3a7713b1edbc 7376 #elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
AnnaBridge 171:3a7713b1edbc 7377 #define EXTI_EMR2_EM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7378 #define EXTI_EMR2_EM_Msk (0xDU << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */
AnnaBridge 171:3a7713b1edbc 7379 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
AnnaBridge 171:3a7713b1edbc 7380 #else
AnnaBridge 171:3a7713b1edbc 7381 #define EXTI_EMR2_EM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7382 #define EXTI_EMR2_EM_Msk (0x1U << EXTI_EMR2_EM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7383 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
AnnaBridge 171:3a7713b1edbc 7384 #endif
AnnaBridge 171:3a7713b1edbc 7385
AnnaBridge 171:3a7713b1edbc 7386 /****************** Bit definition for EXTI_RTSR2 register ********************/
AnnaBridge 171:3a7713b1edbc 7387 #define EXTI_RTSR2_TR32_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7388 #define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7389 #define EXTI_RTSR2_TR32 EXTI_RTSR2_TR32_Msk /*!< Rising trigger event configuration bit of line 32 */
AnnaBridge 171:3a7713b1edbc 7390
AnnaBridge 171:3a7713b1edbc 7391 /* References Defines */
AnnaBridge 171:3a7713b1edbc 7392 #define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
AnnaBridge 171:3a7713b1edbc 7393 #if defined(EXTI_RTSR2_TR33)
AnnaBridge 171:3a7713b1edbc 7394 #define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
AnnaBridge 171:3a7713b1edbc 7395 #endif
AnnaBridge 171:3a7713b1edbc 7396 #if defined(EXTI_RTSR2_TR34)
AnnaBridge 171:3a7713b1edbc 7397 #define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34
AnnaBridge 171:3a7713b1edbc 7398 #endif
AnnaBridge 171:3a7713b1edbc 7399 #if defined(EXTI_RTSR2_TR35)
AnnaBridge 171:3a7713b1edbc 7400 #define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35
AnnaBridge 171:3a7713b1edbc 7401 #endif
AnnaBridge 171:3a7713b1edbc 7402
AnnaBridge 171:3a7713b1edbc 7403 /****************** Bit definition for EXTI_FTSR2 register ******************/
AnnaBridge 171:3a7713b1edbc 7404 #define EXTI_FTSR2_TR32_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7405 #define EXTI_FTSR2_TR32_Msk (0x1U << EXTI_FTSR2_TR32_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7406 #define EXTI_FTSR2_TR32 EXTI_FTSR2_TR32_Msk /*!< Falling trigger event configuration bit of line 32 */
AnnaBridge 171:3a7713b1edbc 7407
AnnaBridge 171:3a7713b1edbc 7408 /* References Defines */
AnnaBridge 171:3a7713b1edbc 7409 #define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
AnnaBridge 171:3a7713b1edbc 7410 #if defined(EXTI_FTSR2_TR33)
AnnaBridge 171:3a7713b1edbc 7411 #define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
AnnaBridge 171:3a7713b1edbc 7412 #endif
AnnaBridge 171:3a7713b1edbc 7413 #if defined(EXTI_FTSR2_TR34)
AnnaBridge 171:3a7713b1edbc 7414 #define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34
AnnaBridge 171:3a7713b1edbc 7415 #endif
AnnaBridge 171:3a7713b1edbc 7416 #if defined(EXTI_FTSR2_TR35)
AnnaBridge 171:3a7713b1edbc 7417 #define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35
AnnaBridge 171:3a7713b1edbc 7418 #endif
AnnaBridge 171:3a7713b1edbc 7419
AnnaBridge 171:3a7713b1edbc 7420 /****************** Bit definition for EXTI_SWIER2 register *****************/
AnnaBridge 171:3a7713b1edbc 7421 #define EXTI_SWIER2_SWIER32_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7422 #define EXTI_SWIER2_SWIER32_Msk (0x1U << EXTI_SWIER2_SWIER32_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7423 #define EXTI_SWIER2_SWIER32 EXTI_SWIER2_SWIER32_Msk /*!< Software Interrupt on line 32 */
AnnaBridge 171:3a7713b1edbc 7424
AnnaBridge 171:3a7713b1edbc 7425 /* References Defines */
AnnaBridge 171:3a7713b1edbc 7426 #define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
AnnaBridge 171:3a7713b1edbc 7427 #if defined(EXTI_SWIER2_SWIER33)
AnnaBridge 171:3a7713b1edbc 7428 #define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
AnnaBridge 171:3a7713b1edbc 7429 #endif
AnnaBridge 171:3a7713b1edbc 7430 #if defined(EXTI_SWIER2_SWIER34)
AnnaBridge 171:3a7713b1edbc 7431 #define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34
AnnaBridge 171:3a7713b1edbc 7432 #endif
AnnaBridge 171:3a7713b1edbc 7433 #if defined(EXTI_SWIER2_SWIER35)
AnnaBridge 171:3a7713b1edbc 7434 #define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35
AnnaBridge 171:3a7713b1edbc 7435 #endif
AnnaBridge 171:3a7713b1edbc 7436
AnnaBridge 171:3a7713b1edbc 7437 /******************* Bit definition for EXTI_PR2 register *******************/
AnnaBridge 171:3a7713b1edbc 7438 #define EXTI_PR2_PR32_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7439 #define EXTI_PR2_PR32_Msk (0x1U << EXTI_PR2_PR32_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7440 #define EXTI_PR2_PR32 EXTI_PR2_PR32_Msk /*!< Pending bit for line 32 */
AnnaBridge 171:3a7713b1edbc 7441
AnnaBridge 171:3a7713b1edbc 7442 /* References Defines */
AnnaBridge 171:3a7713b1edbc 7443 #define EXTI_PR2_PIF32 EXTI_PR2_PR32
AnnaBridge 171:3a7713b1edbc 7444 #if defined(EXTI_PR2_PR33)
AnnaBridge 171:3a7713b1edbc 7445 #define EXTI_PR2_PIF33 EXTI_PR2_PR33
AnnaBridge 171:3a7713b1edbc 7446 #endif
AnnaBridge 171:3a7713b1edbc 7447 #if defined(EXTI_PR2_PR34)
AnnaBridge 171:3a7713b1edbc 7448 #define EXTI_PR2_PIF34 EXTI_PR2_PR34
AnnaBridge 171:3a7713b1edbc 7449 #endif
AnnaBridge 171:3a7713b1edbc 7450 #if defined(EXTI_PR2_PR35)
AnnaBridge 171:3a7713b1edbc 7451 #define EXTI_PR2_PIF35 EXTI_PR2_PR35
AnnaBridge 171:3a7713b1edbc 7452 #endif
AnnaBridge 171:3a7713b1edbc 7453
AnnaBridge 171:3a7713b1edbc 7454
AnnaBridge 171:3a7713b1edbc 7455 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 7456 /* */
AnnaBridge 171:3a7713b1edbc 7457 /* FLASH */
AnnaBridge 171:3a7713b1edbc 7458 /* */
AnnaBridge 171:3a7713b1edbc 7459 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 7460 /******************* Bit definition for FLASH_ACR register ******************/
AnnaBridge 171:3a7713b1edbc 7461 #define FLASH_ACR_LATENCY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7462 #define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 7463 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
AnnaBridge 171:3a7713b1edbc 7464 #define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7465 #define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7466 #define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7467
AnnaBridge 171:3a7713b1edbc 7468 #define FLASH_ACR_HLFCYA_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7469 #define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7470 #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
AnnaBridge 171:3a7713b1edbc 7471 #define FLASH_ACR_PRFTBE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7472 #define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7473 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
AnnaBridge 171:3a7713b1edbc 7474 #define FLASH_ACR_PRFTBS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7475 #define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7476 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
AnnaBridge 171:3a7713b1edbc 7477
AnnaBridge 171:3a7713b1edbc 7478 /****************** Bit definition for FLASH_KEYR register ******************/
AnnaBridge 171:3a7713b1edbc 7479 #define FLASH_KEYR_FKEYR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7480 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 7481 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
AnnaBridge 171:3a7713b1edbc 7482
AnnaBridge 171:3a7713b1edbc 7483 #define RDP_KEY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7484 #define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
AnnaBridge 171:3a7713b1edbc 7485 #define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
AnnaBridge 171:3a7713b1edbc 7486 #define FLASH_KEY1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7487 #define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
AnnaBridge 171:3a7713b1edbc 7488 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
AnnaBridge 171:3a7713b1edbc 7489 #define FLASH_KEY2_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7490 #define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
AnnaBridge 171:3a7713b1edbc 7491 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
AnnaBridge 171:3a7713b1edbc 7492
AnnaBridge 171:3a7713b1edbc 7493 /***************** Bit definition for FLASH_OPTKEYR register ****************/
AnnaBridge 171:3a7713b1edbc 7494 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7495 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 7496 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
AnnaBridge 171:3a7713b1edbc 7497
AnnaBridge 171:3a7713b1edbc 7498 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
AnnaBridge 171:3a7713b1edbc 7499 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
AnnaBridge 171:3a7713b1edbc 7500
AnnaBridge 171:3a7713b1edbc 7501 /****************** Bit definition for FLASH_SR register *******************/
AnnaBridge 171:3a7713b1edbc 7502 #define FLASH_SR_BSY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7503 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7504 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
AnnaBridge 171:3a7713b1edbc 7505 #define FLASH_SR_PGERR_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7506 #define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7507 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
AnnaBridge 171:3a7713b1edbc 7508 #define FLASH_SR_WRPERR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7509 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7510 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write Protection Error */
AnnaBridge 171:3a7713b1edbc 7511 #define FLASH_SR_EOP_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7512 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7513 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
AnnaBridge 171:3a7713b1edbc 7514
AnnaBridge 171:3a7713b1edbc 7515 /******************* Bit definition for FLASH_CR register *******************/
AnnaBridge 171:3a7713b1edbc 7516 #define FLASH_CR_PG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7517 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7518 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
AnnaBridge 171:3a7713b1edbc 7519 #define FLASH_CR_PER_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7520 #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7521 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
AnnaBridge 171:3a7713b1edbc 7522 #define FLASH_CR_MER_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7523 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7524 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
AnnaBridge 171:3a7713b1edbc 7525 #define FLASH_CR_OPTPG_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7526 #define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7527 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
AnnaBridge 171:3a7713b1edbc 7528 #define FLASH_CR_OPTER_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7529 #define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7530 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
AnnaBridge 171:3a7713b1edbc 7531 #define FLASH_CR_STRT_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7532 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7533 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
AnnaBridge 171:3a7713b1edbc 7534 #define FLASH_CR_LOCK_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7535 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7536 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
AnnaBridge 171:3a7713b1edbc 7537 #define FLASH_CR_OPTWRE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7538 #define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7539 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
AnnaBridge 171:3a7713b1edbc 7540 #define FLASH_CR_ERRIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7541 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7542 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 7543 #define FLASH_CR_EOPIE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7544 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7545 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
AnnaBridge 171:3a7713b1edbc 7546 #define FLASH_CR_OBL_LAUNCH_Pos (13U)
AnnaBridge 171:3a7713b1edbc 7547 #define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7548 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< OptionBytes Loader Launch */
AnnaBridge 171:3a7713b1edbc 7549
AnnaBridge 171:3a7713b1edbc 7550 /******************* Bit definition for FLASH_AR register *******************/
AnnaBridge 171:3a7713b1edbc 7551 #define FLASH_AR_FAR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7552 #define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 7553 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
AnnaBridge 171:3a7713b1edbc 7554
AnnaBridge 171:3a7713b1edbc 7555 /****************** Bit definition for FLASH_OBR register *******************/
AnnaBridge 171:3a7713b1edbc 7556 #define FLASH_OBR_OPTERR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7557 #define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7558 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
AnnaBridge 171:3a7713b1edbc 7559 #define FLASH_OBR_RDPRT_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7560 #define FLASH_OBR_RDPRT_Msk (0x3U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000006 */
AnnaBridge 171:3a7713b1edbc 7561 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
AnnaBridge 171:3a7713b1edbc 7562 #define FLASH_OBR_RDPRT_1 (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7563 #define FLASH_OBR_RDPRT_2 (0x3U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000006 */
AnnaBridge 171:3a7713b1edbc 7564
AnnaBridge 171:3a7713b1edbc 7565 #define FLASH_OBR_USER_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7566 #define FLASH_OBR_USER_Msk (0x77U << FLASH_OBR_USER_Pos) /*!< 0x00007700 */
AnnaBridge 171:3a7713b1edbc 7567 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
AnnaBridge 171:3a7713b1edbc 7568 #define FLASH_OBR_IWDG_SW_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7569 #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7570 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
AnnaBridge 171:3a7713b1edbc 7571 #define FLASH_OBR_nRST_STOP_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7572 #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7573 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
AnnaBridge 171:3a7713b1edbc 7574 #define FLASH_OBR_nRST_STDBY_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7575 #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7576 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
AnnaBridge 171:3a7713b1edbc 7577 #define FLASH_OBR_nBOOT1_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7578 #define FLASH_OBR_nBOOT1_Msk (0x1U << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7579 #define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */
AnnaBridge 171:3a7713b1edbc 7580 #define FLASH_OBR_VDDA_MONITOR_Pos (13U)
AnnaBridge 171:3a7713b1edbc 7581 #define FLASH_OBR_VDDA_MONITOR_Msk (0x1U << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7582 #define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA_MONITOR */
AnnaBridge 171:3a7713b1edbc 7583 #define FLASH_OBR_SRAM_PE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7584 #define FLASH_OBR_SRAM_PE_Msk (0x1U << FLASH_OBR_SRAM_PE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7585 #define FLASH_OBR_SRAM_PE FLASH_OBR_SRAM_PE_Msk /*!< SRAM_PE */
AnnaBridge 171:3a7713b1edbc 7586 #define FLASH_OBR_DATA0_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7587 #define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 7588 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
AnnaBridge 171:3a7713b1edbc 7589 #define FLASH_OBR_DATA1_Pos (24U)
AnnaBridge 171:3a7713b1edbc 7590 #define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 7591 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
AnnaBridge 171:3a7713b1edbc 7592
AnnaBridge 171:3a7713b1edbc 7593 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 7594 #define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
AnnaBridge 171:3a7713b1edbc 7595
AnnaBridge 171:3a7713b1edbc 7596 /****************** Bit definition for FLASH_WRPR register ******************/
AnnaBridge 171:3a7713b1edbc 7597 #define FLASH_WRPR_WRP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7598 #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 7599 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
AnnaBridge 171:3a7713b1edbc 7600
AnnaBridge 171:3a7713b1edbc 7601 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 7602
AnnaBridge 171:3a7713b1edbc 7603 /****************** Bit definition for OB_RDP register **********************/
AnnaBridge 171:3a7713b1edbc 7604 #define OB_RDP_RDP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7605 #define OB_RDP_RDP_Msk (0xFFU << OB_RDP_RDP_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 7606 #define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */
AnnaBridge 171:3a7713b1edbc 7607 #define OB_RDP_nRDP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7608 #define OB_RDP_nRDP_Msk (0xFFU << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 7609 #define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */
AnnaBridge 171:3a7713b1edbc 7610
AnnaBridge 171:3a7713b1edbc 7611 /****************** Bit definition for OB_USER register *********************/
AnnaBridge 171:3a7713b1edbc 7612 #define OB_USER_USER_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7613 #define OB_USER_USER_Msk (0xFFU << OB_USER_USER_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 7614 #define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */
AnnaBridge 171:3a7713b1edbc 7615 #define OB_USER_nUSER_Pos (24U)
AnnaBridge 171:3a7713b1edbc 7616 #define OB_USER_nUSER_Msk (0xFFU << OB_USER_nUSER_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 7617 #define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */
AnnaBridge 171:3a7713b1edbc 7618
AnnaBridge 171:3a7713b1edbc 7619 /****************** Bit definition for FLASH_WRP0 register ******************/
AnnaBridge 171:3a7713b1edbc 7620 #define OB_WRP0_WRP0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7621 #define OB_WRP0_WRP0_Msk (0xFFU << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 7622 #define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
AnnaBridge 171:3a7713b1edbc 7623 #define OB_WRP0_nWRP0_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7624 #define OB_WRP0_nWRP0_Msk (0xFFU << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 7625 #define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
AnnaBridge 171:3a7713b1edbc 7626
AnnaBridge 171:3a7713b1edbc 7627 /****************** Bit definition for FLASH_WRP1 register ******************/
AnnaBridge 171:3a7713b1edbc 7628 #define OB_WRP1_WRP1_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7629 #define OB_WRP1_WRP1_Msk (0xFFU << OB_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 7630 #define OB_WRP1_WRP1 OB_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
AnnaBridge 171:3a7713b1edbc 7631 #define OB_WRP1_nWRP1_Pos (24U)
AnnaBridge 171:3a7713b1edbc 7632 #define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 7633 #define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
AnnaBridge 171:3a7713b1edbc 7634
AnnaBridge 171:3a7713b1edbc 7635
AnnaBridge 171:3a7713b1edbc 7636 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 7637 /* */
AnnaBridge 171:3a7713b1edbc 7638 /* General Purpose I/O (GPIO) */
AnnaBridge 171:3a7713b1edbc 7639 /* */
AnnaBridge 171:3a7713b1edbc 7640 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 7641 /******************* Bit definition for GPIO_MODER register *****************/
AnnaBridge 171:3a7713b1edbc 7642 #define GPIO_MODER_MODER0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7643 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 7644 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
AnnaBridge 171:3a7713b1edbc 7645 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7646 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7647 #define GPIO_MODER_MODER1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7648 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 7649 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
AnnaBridge 171:3a7713b1edbc 7650 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7651 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7652 #define GPIO_MODER_MODER2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7653 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 7654 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
AnnaBridge 171:3a7713b1edbc 7655 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7656 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7657 #define GPIO_MODER_MODER3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7658 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 7659 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
AnnaBridge 171:3a7713b1edbc 7660 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7661 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7662 #define GPIO_MODER_MODER4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7663 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 7664 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
AnnaBridge 171:3a7713b1edbc 7665 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7666 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7667 #define GPIO_MODER_MODER5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7668 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 7669 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
AnnaBridge 171:3a7713b1edbc 7670 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7671 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7672 #define GPIO_MODER_MODER6_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7673 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 7674 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
AnnaBridge 171:3a7713b1edbc 7675 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7676 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7677 #define GPIO_MODER_MODER7_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7678 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 7679 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
AnnaBridge 171:3a7713b1edbc 7680 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7681 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7682 #define GPIO_MODER_MODER8_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7683 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 7684 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
AnnaBridge 171:3a7713b1edbc 7685 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7686 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7687 #define GPIO_MODER_MODER9_Pos (18U)
AnnaBridge 171:3a7713b1edbc 7688 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 7689 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
AnnaBridge 171:3a7713b1edbc 7690 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7691 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7692 #define GPIO_MODER_MODER10_Pos (20U)
AnnaBridge 171:3a7713b1edbc 7693 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 7694 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
AnnaBridge 171:3a7713b1edbc 7695 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 7696 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 7697 #define GPIO_MODER_MODER11_Pos (22U)
AnnaBridge 171:3a7713b1edbc 7698 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 7699 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
AnnaBridge 171:3a7713b1edbc 7700 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 7701 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 7702 #define GPIO_MODER_MODER12_Pos (24U)
AnnaBridge 171:3a7713b1edbc 7703 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 7704 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
AnnaBridge 171:3a7713b1edbc 7705 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 7706 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 7707 #define GPIO_MODER_MODER13_Pos (26U)
AnnaBridge 171:3a7713b1edbc 7708 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 7709 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
AnnaBridge 171:3a7713b1edbc 7710 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 7711 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 7712 #define GPIO_MODER_MODER14_Pos (28U)
AnnaBridge 171:3a7713b1edbc 7713 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 7714 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
AnnaBridge 171:3a7713b1edbc 7715 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 7716 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 7717 #define GPIO_MODER_MODER15_Pos (30U)
AnnaBridge 171:3a7713b1edbc 7718 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 7719 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
AnnaBridge 171:3a7713b1edbc 7720 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 7721 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 7722
AnnaBridge 171:3a7713b1edbc 7723 /****************** Bit definition for GPIO_OTYPER register *****************/
AnnaBridge 171:3a7713b1edbc 7724 #define GPIO_OTYPER_OT_0 (0x00000001U)
AnnaBridge 171:3a7713b1edbc 7725 #define GPIO_OTYPER_OT_1 (0x00000002U)
AnnaBridge 171:3a7713b1edbc 7726 #define GPIO_OTYPER_OT_2 (0x00000004U)
AnnaBridge 171:3a7713b1edbc 7727 #define GPIO_OTYPER_OT_3 (0x00000008U)
AnnaBridge 171:3a7713b1edbc 7728 #define GPIO_OTYPER_OT_4 (0x00000010U)
AnnaBridge 171:3a7713b1edbc 7729 #define GPIO_OTYPER_OT_5 (0x00000020U)
AnnaBridge 171:3a7713b1edbc 7730 #define GPIO_OTYPER_OT_6 (0x00000040U)
AnnaBridge 171:3a7713b1edbc 7731 #define GPIO_OTYPER_OT_7 (0x00000080U)
AnnaBridge 171:3a7713b1edbc 7732 #define GPIO_OTYPER_OT_8 (0x00000100U)
AnnaBridge 171:3a7713b1edbc 7733 #define GPIO_OTYPER_OT_9 (0x00000200U)
AnnaBridge 171:3a7713b1edbc 7734 #define GPIO_OTYPER_OT_10 (0x00000400U)
AnnaBridge 171:3a7713b1edbc 7735 #define GPIO_OTYPER_OT_11 (0x00000800U)
AnnaBridge 171:3a7713b1edbc 7736 #define GPIO_OTYPER_OT_12 (0x00001000U)
AnnaBridge 171:3a7713b1edbc 7737 #define GPIO_OTYPER_OT_13 (0x00002000U)
AnnaBridge 171:3a7713b1edbc 7738 #define GPIO_OTYPER_OT_14 (0x00004000U)
AnnaBridge 171:3a7713b1edbc 7739 #define GPIO_OTYPER_OT_15 (0x00008000U)
AnnaBridge 171:3a7713b1edbc 7740
AnnaBridge 171:3a7713b1edbc 7741 /**************** Bit definition for GPIO_OSPEEDR register ******************/
AnnaBridge 171:3a7713b1edbc 7742 #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7743 #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 7744 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
AnnaBridge 171:3a7713b1edbc 7745 #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7746 #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7747 #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7748 #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 7749 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
AnnaBridge 171:3a7713b1edbc 7750 #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7751 #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7752 #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7753 #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 7754 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
AnnaBridge 171:3a7713b1edbc 7755 #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7756 #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7757 #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7758 #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 7759 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
AnnaBridge 171:3a7713b1edbc 7760 #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7761 #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7762 #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7763 #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 7764 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
AnnaBridge 171:3a7713b1edbc 7765 #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7766 #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7767 #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7768 #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 7769 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
AnnaBridge 171:3a7713b1edbc 7770 #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7771 #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7772 #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7773 #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 7774 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
AnnaBridge 171:3a7713b1edbc 7775 #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7776 #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7777 #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7778 #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 7779 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
AnnaBridge 171:3a7713b1edbc 7780 #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7781 #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7782 #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7783 #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 7784 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
AnnaBridge 171:3a7713b1edbc 7785 #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7786 #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7787 #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
AnnaBridge 171:3a7713b1edbc 7788 #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 7789 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
AnnaBridge 171:3a7713b1edbc 7790 #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7791 #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7792 #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
AnnaBridge 171:3a7713b1edbc 7793 #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 7794 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
AnnaBridge 171:3a7713b1edbc 7795 #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 7796 #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 7797 #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
AnnaBridge 171:3a7713b1edbc 7798 #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 7799 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
AnnaBridge 171:3a7713b1edbc 7800 #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 7801 #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 7802 #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
AnnaBridge 171:3a7713b1edbc 7803 #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 7804 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
AnnaBridge 171:3a7713b1edbc 7805 #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 7806 #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 7807 #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
AnnaBridge 171:3a7713b1edbc 7808 #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 7809 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
AnnaBridge 171:3a7713b1edbc 7810 #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 7811 #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 7812 #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
AnnaBridge 171:3a7713b1edbc 7813 #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 7814 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
AnnaBridge 171:3a7713b1edbc 7815 #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 7816 #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 7817 #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
AnnaBridge 171:3a7713b1edbc 7818 #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 7819 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
AnnaBridge 171:3a7713b1edbc 7820 #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 7821 #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 7822
AnnaBridge 171:3a7713b1edbc 7823 /******************* Bit definition for GPIO_PUPDR register ******************/
AnnaBridge 171:3a7713b1edbc 7824 #define GPIO_PUPDR_PUPDR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7825 #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 7826 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
AnnaBridge 171:3a7713b1edbc 7827 #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7828 #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7829 #define GPIO_PUPDR_PUPDR1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7830 #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 7831 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
AnnaBridge 171:3a7713b1edbc 7832 #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7833 #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7834 #define GPIO_PUPDR_PUPDR2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7835 #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 7836 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
AnnaBridge 171:3a7713b1edbc 7837 #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7838 #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7839 #define GPIO_PUPDR_PUPDR3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7840 #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 7841 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
AnnaBridge 171:3a7713b1edbc 7842 #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7843 #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7844 #define GPIO_PUPDR_PUPDR4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7845 #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 7846 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
AnnaBridge 171:3a7713b1edbc 7847 #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7848 #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7849 #define GPIO_PUPDR_PUPDR5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7850 #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 7851 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
AnnaBridge 171:3a7713b1edbc 7852 #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7853 #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7854 #define GPIO_PUPDR_PUPDR6_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7855 #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 7856 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
AnnaBridge 171:3a7713b1edbc 7857 #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7858 #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7859 #define GPIO_PUPDR_PUPDR7_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7860 #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 7861 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
AnnaBridge 171:3a7713b1edbc 7862 #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7863 #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7864 #define GPIO_PUPDR_PUPDR8_Pos (16U)
AnnaBridge 171:3a7713b1edbc 7865 #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 7866 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
AnnaBridge 171:3a7713b1edbc 7867 #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 7868 #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 7869 #define GPIO_PUPDR_PUPDR9_Pos (18U)
AnnaBridge 171:3a7713b1edbc 7870 #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 7871 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
AnnaBridge 171:3a7713b1edbc 7872 #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 7873 #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 7874 #define GPIO_PUPDR_PUPDR10_Pos (20U)
AnnaBridge 171:3a7713b1edbc 7875 #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 7876 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
AnnaBridge 171:3a7713b1edbc 7877 #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 7878 #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 7879 #define GPIO_PUPDR_PUPDR11_Pos (22U)
AnnaBridge 171:3a7713b1edbc 7880 #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 7881 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
AnnaBridge 171:3a7713b1edbc 7882 #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 7883 #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 7884 #define GPIO_PUPDR_PUPDR12_Pos (24U)
AnnaBridge 171:3a7713b1edbc 7885 #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 7886 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
AnnaBridge 171:3a7713b1edbc 7887 #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 7888 #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 7889 #define GPIO_PUPDR_PUPDR13_Pos (26U)
AnnaBridge 171:3a7713b1edbc 7890 #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 7891 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
AnnaBridge 171:3a7713b1edbc 7892 #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 7893 #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 7894 #define GPIO_PUPDR_PUPDR14_Pos (28U)
AnnaBridge 171:3a7713b1edbc 7895 #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 7896 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
AnnaBridge 171:3a7713b1edbc 7897 #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 7898 #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 7899 #define GPIO_PUPDR_PUPDR15_Pos (30U)
AnnaBridge 171:3a7713b1edbc 7900 #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 7901 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
AnnaBridge 171:3a7713b1edbc 7902 #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 7903 #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 7904
AnnaBridge 171:3a7713b1edbc 7905 /******************* Bit definition for GPIO_IDR register *******************/
AnnaBridge 171:3a7713b1edbc 7906 #define GPIO_IDR_0 (0x00000001U)
AnnaBridge 171:3a7713b1edbc 7907 #define GPIO_IDR_1 (0x00000002U)
AnnaBridge 171:3a7713b1edbc 7908 #define GPIO_IDR_2 (0x00000004U)
AnnaBridge 171:3a7713b1edbc 7909 #define GPIO_IDR_3 (0x00000008U)
AnnaBridge 171:3a7713b1edbc 7910 #define GPIO_IDR_4 (0x00000010U)
AnnaBridge 171:3a7713b1edbc 7911 #define GPIO_IDR_5 (0x00000020U)
AnnaBridge 171:3a7713b1edbc 7912 #define GPIO_IDR_6 (0x00000040U)
AnnaBridge 171:3a7713b1edbc 7913 #define GPIO_IDR_7 (0x00000080U)
AnnaBridge 171:3a7713b1edbc 7914 #define GPIO_IDR_8 (0x00000100U)
AnnaBridge 171:3a7713b1edbc 7915 #define GPIO_IDR_9 (0x00000200U)
AnnaBridge 171:3a7713b1edbc 7916 #define GPIO_IDR_10 (0x00000400U)
AnnaBridge 171:3a7713b1edbc 7917 #define GPIO_IDR_11 (0x00000800U)
AnnaBridge 171:3a7713b1edbc 7918 #define GPIO_IDR_12 (0x00001000U)
AnnaBridge 171:3a7713b1edbc 7919 #define GPIO_IDR_13 (0x00002000U)
AnnaBridge 171:3a7713b1edbc 7920 #define GPIO_IDR_14 (0x00004000U)
AnnaBridge 171:3a7713b1edbc 7921 #define GPIO_IDR_15 (0x00008000U)
AnnaBridge 171:3a7713b1edbc 7922
AnnaBridge 171:3a7713b1edbc 7923 /****************** Bit definition for GPIO_ODR register ********************/
AnnaBridge 171:3a7713b1edbc 7924 #define GPIO_ODR_0 (0x00000001U)
AnnaBridge 171:3a7713b1edbc 7925 #define GPIO_ODR_1 (0x00000002U)
AnnaBridge 171:3a7713b1edbc 7926 #define GPIO_ODR_2 (0x00000004U)
AnnaBridge 171:3a7713b1edbc 7927 #define GPIO_ODR_3 (0x00000008U)
AnnaBridge 171:3a7713b1edbc 7928 #define GPIO_ODR_4 (0x00000010U)
AnnaBridge 171:3a7713b1edbc 7929 #define GPIO_ODR_5 (0x00000020U)
AnnaBridge 171:3a7713b1edbc 7930 #define GPIO_ODR_6 (0x00000040U)
AnnaBridge 171:3a7713b1edbc 7931 #define GPIO_ODR_7 (0x00000080U)
AnnaBridge 171:3a7713b1edbc 7932 #define GPIO_ODR_8 (0x00000100U)
AnnaBridge 171:3a7713b1edbc 7933 #define GPIO_ODR_9 (0x00000200U)
AnnaBridge 171:3a7713b1edbc 7934 #define GPIO_ODR_10 (0x00000400U)
AnnaBridge 171:3a7713b1edbc 7935 #define GPIO_ODR_11 (0x00000800U)
AnnaBridge 171:3a7713b1edbc 7936 #define GPIO_ODR_12 (0x00001000U)
AnnaBridge 171:3a7713b1edbc 7937 #define GPIO_ODR_13 (0x00002000U)
AnnaBridge 171:3a7713b1edbc 7938 #define GPIO_ODR_14 (0x00004000U)
AnnaBridge 171:3a7713b1edbc 7939 #define GPIO_ODR_15 (0x00008000U)
AnnaBridge 171:3a7713b1edbc 7940
AnnaBridge 171:3a7713b1edbc 7941 /****************** Bit definition for GPIO_BSRR register ********************/
AnnaBridge 171:3a7713b1edbc 7942 #define GPIO_BSRR_BS_0 (0x00000001U)
AnnaBridge 171:3a7713b1edbc 7943 #define GPIO_BSRR_BS_1 (0x00000002U)
AnnaBridge 171:3a7713b1edbc 7944 #define GPIO_BSRR_BS_2 (0x00000004U)
AnnaBridge 171:3a7713b1edbc 7945 #define GPIO_BSRR_BS_3 (0x00000008U)
AnnaBridge 171:3a7713b1edbc 7946 #define GPIO_BSRR_BS_4 (0x00000010U)
AnnaBridge 171:3a7713b1edbc 7947 #define GPIO_BSRR_BS_5 (0x00000020U)
AnnaBridge 171:3a7713b1edbc 7948 #define GPIO_BSRR_BS_6 (0x00000040U)
AnnaBridge 171:3a7713b1edbc 7949 #define GPIO_BSRR_BS_7 (0x00000080U)
AnnaBridge 171:3a7713b1edbc 7950 #define GPIO_BSRR_BS_8 (0x00000100U)
AnnaBridge 171:3a7713b1edbc 7951 #define GPIO_BSRR_BS_9 (0x00000200U)
AnnaBridge 171:3a7713b1edbc 7952 #define GPIO_BSRR_BS_10 (0x00000400U)
AnnaBridge 171:3a7713b1edbc 7953 #define GPIO_BSRR_BS_11 (0x00000800U)
AnnaBridge 171:3a7713b1edbc 7954 #define GPIO_BSRR_BS_12 (0x00001000U)
AnnaBridge 171:3a7713b1edbc 7955 #define GPIO_BSRR_BS_13 (0x00002000U)
AnnaBridge 171:3a7713b1edbc 7956 #define GPIO_BSRR_BS_14 (0x00004000U)
AnnaBridge 171:3a7713b1edbc 7957 #define GPIO_BSRR_BS_15 (0x00008000U)
AnnaBridge 171:3a7713b1edbc 7958 #define GPIO_BSRR_BR_0 (0x00010000U)
AnnaBridge 171:3a7713b1edbc 7959 #define GPIO_BSRR_BR_1 (0x00020000U)
AnnaBridge 171:3a7713b1edbc 7960 #define GPIO_BSRR_BR_2 (0x00040000U)
AnnaBridge 171:3a7713b1edbc 7961 #define GPIO_BSRR_BR_3 (0x00080000U)
AnnaBridge 171:3a7713b1edbc 7962 #define GPIO_BSRR_BR_4 (0x00100000U)
AnnaBridge 171:3a7713b1edbc 7963 #define GPIO_BSRR_BR_5 (0x00200000U)
AnnaBridge 171:3a7713b1edbc 7964 #define GPIO_BSRR_BR_6 (0x00400000U)
AnnaBridge 171:3a7713b1edbc 7965 #define GPIO_BSRR_BR_7 (0x00800000U)
AnnaBridge 171:3a7713b1edbc 7966 #define GPIO_BSRR_BR_8 (0x01000000U)
AnnaBridge 171:3a7713b1edbc 7967 #define GPIO_BSRR_BR_9 (0x02000000U)
AnnaBridge 171:3a7713b1edbc 7968 #define GPIO_BSRR_BR_10 (0x04000000U)
AnnaBridge 171:3a7713b1edbc 7969 #define GPIO_BSRR_BR_11 (0x08000000U)
AnnaBridge 171:3a7713b1edbc 7970 #define GPIO_BSRR_BR_12 (0x10000000U)
AnnaBridge 171:3a7713b1edbc 7971 #define GPIO_BSRR_BR_13 (0x20000000U)
AnnaBridge 171:3a7713b1edbc 7972 #define GPIO_BSRR_BR_14 (0x40000000U)
AnnaBridge 171:3a7713b1edbc 7973 #define GPIO_BSRR_BR_15 (0x80000000U)
AnnaBridge 171:3a7713b1edbc 7974
AnnaBridge 171:3a7713b1edbc 7975 /****************** Bit definition for GPIO_LCKR register ********************/
AnnaBridge 171:3a7713b1edbc 7976 #define GPIO_LCKR_LCK0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7977 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7978 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
AnnaBridge 171:3a7713b1edbc 7979 #define GPIO_LCKR_LCK1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7980 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7981 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
AnnaBridge 171:3a7713b1edbc 7982 #define GPIO_LCKR_LCK2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7983 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7984 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
AnnaBridge 171:3a7713b1edbc 7985 #define GPIO_LCKR_LCK3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7986 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7987 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
AnnaBridge 171:3a7713b1edbc 7988 #define GPIO_LCKR_LCK4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7989 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7990 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
AnnaBridge 171:3a7713b1edbc 7991 #define GPIO_LCKR_LCK5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7992 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7993 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
AnnaBridge 171:3a7713b1edbc 7994 #define GPIO_LCKR_LCK6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7995 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7996 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
AnnaBridge 171:3a7713b1edbc 7997 #define GPIO_LCKR_LCK7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7998 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7999 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
AnnaBridge 171:3a7713b1edbc 8000 #define GPIO_LCKR_LCK8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8001 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8002 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
AnnaBridge 171:3a7713b1edbc 8003 #define GPIO_LCKR_LCK9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8004 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8005 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
AnnaBridge 171:3a7713b1edbc 8006 #define GPIO_LCKR_LCK10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8007 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8008 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
AnnaBridge 171:3a7713b1edbc 8009 #define GPIO_LCKR_LCK11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 8010 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8011 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
AnnaBridge 171:3a7713b1edbc 8012 #define GPIO_LCKR_LCK12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8013 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8014 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
AnnaBridge 171:3a7713b1edbc 8015 #define GPIO_LCKR_LCK13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 8016 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8017 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
AnnaBridge 171:3a7713b1edbc 8018 #define GPIO_LCKR_LCK14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8019 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8020 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
AnnaBridge 171:3a7713b1edbc 8021 #define GPIO_LCKR_LCK15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8022 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8023 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
AnnaBridge 171:3a7713b1edbc 8024 #define GPIO_LCKR_LCKK_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8025 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8026 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
AnnaBridge 171:3a7713b1edbc 8027
AnnaBridge 171:3a7713b1edbc 8028 /****************** Bit definition for GPIO_AFRL register ********************/
AnnaBridge 171:3a7713b1edbc 8029 #define GPIO_AFRL_AFRL0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8030 #define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 8031 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
AnnaBridge 171:3a7713b1edbc 8032 #define GPIO_AFRL_AFRL1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8033 #define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 8034 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
AnnaBridge 171:3a7713b1edbc 8035 #define GPIO_AFRL_AFRL2_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8036 #define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 8037 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
AnnaBridge 171:3a7713b1edbc 8038 #define GPIO_AFRL_AFRL3_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8039 #define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 8040 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
AnnaBridge 171:3a7713b1edbc 8041 #define GPIO_AFRL_AFRL4_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8042 #define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 8043 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
AnnaBridge 171:3a7713b1edbc 8044 #define GPIO_AFRL_AFRL5_Pos (20U)
AnnaBridge 171:3a7713b1edbc 8045 #define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 8046 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
AnnaBridge 171:3a7713b1edbc 8047 #define GPIO_AFRL_AFRL6_Pos (24U)
AnnaBridge 171:3a7713b1edbc 8048 #define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 8049 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
AnnaBridge 171:3a7713b1edbc 8050 #define GPIO_AFRL_AFRL7_Pos (28U)
AnnaBridge 171:3a7713b1edbc 8051 #define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
AnnaBridge 171:3a7713b1edbc 8052 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
AnnaBridge 171:3a7713b1edbc 8053
AnnaBridge 171:3a7713b1edbc 8054 /****************** Bit definition for GPIO_AFRH register ********************/
AnnaBridge 171:3a7713b1edbc 8055 #define GPIO_AFRH_AFRH0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8056 #define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 8057 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
AnnaBridge 171:3a7713b1edbc 8058 #define GPIO_AFRH_AFRH1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8059 #define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 8060 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
AnnaBridge 171:3a7713b1edbc 8061 #define GPIO_AFRH_AFRH2_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8062 #define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 8063 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
AnnaBridge 171:3a7713b1edbc 8064 #define GPIO_AFRH_AFRH3_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8065 #define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 8066 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
AnnaBridge 171:3a7713b1edbc 8067 #define GPIO_AFRH_AFRH4_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8068 #define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 8069 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
AnnaBridge 171:3a7713b1edbc 8070 #define GPIO_AFRH_AFRH5_Pos (20U)
AnnaBridge 171:3a7713b1edbc 8071 #define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 8072 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
AnnaBridge 171:3a7713b1edbc 8073 #define GPIO_AFRH_AFRH6_Pos (24U)
AnnaBridge 171:3a7713b1edbc 8074 #define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 8075 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
AnnaBridge 171:3a7713b1edbc 8076 #define GPIO_AFRH_AFRH7_Pos (28U)
AnnaBridge 171:3a7713b1edbc 8077 #define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
AnnaBridge 171:3a7713b1edbc 8078 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
AnnaBridge 171:3a7713b1edbc 8079
AnnaBridge 171:3a7713b1edbc 8080 /****************** Bit definition for GPIO_BRR register *********************/
AnnaBridge 171:3a7713b1edbc 8081 #define GPIO_BRR_BR_0 (0x00000001U)
AnnaBridge 171:3a7713b1edbc 8082 #define GPIO_BRR_BR_1 (0x00000002U)
AnnaBridge 171:3a7713b1edbc 8083 #define GPIO_BRR_BR_2 (0x00000004U)
AnnaBridge 171:3a7713b1edbc 8084 #define GPIO_BRR_BR_3 (0x00000008U)
AnnaBridge 171:3a7713b1edbc 8085 #define GPIO_BRR_BR_4 (0x00000010U)
AnnaBridge 171:3a7713b1edbc 8086 #define GPIO_BRR_BR_5 (0x00000020U)
AnnaBridge 171:3a7713b1edbc 8087 #define GPIO_BRR_BR_6 (0x00000040U)
AnnaBridge 171:3a7713b1edbc 8088 #define GPIO_BRR_BR_7 (0x00000080U)
AnnaBridge 171:3a7713b1edbc 8089 #define GPIO_BRR_BR_8 (0x00000100U)
AnnaBridge 171:3a7713b1edbc 8090 #define GPIO_BRR_BR_9 (0x00000200U)
AnnaBridge 171:3a7713b1edbc 8091 #define GPIO_BRR_BR_10 (0x00000400U)
AnnaBridge 171:3a7713b1edbc 8092 #define GPIO_BRR_BR_11 (0x00000800U)
AnnaBridge 171:3a7713b1edbc 8093 #define GPIO_BRR_BR_12 (0x00001000U)
AnnaBridge 171:3a7713b1edbc 8094 #define GPIO_BRR_BR_13 (0x00002000U)
AnnaBridge 171:3a7713b1edbc 8095 #define GPIO_BRR_BR_14 (0x00004000U)
AnnaBridge 171:3a7713b1edbc 8096 #define GPIO_BRR_BR_15 (0x00008000U)
AnnaBridge 171:3a7713b1edbc 8097
AnnaBridge 171:3a7713b1edbc 8098 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8099 /* */
AnnaBridge 171:3a7713b1edbc 8100 /* High Resolution Timer (HRTIM) */
AnnaBridge 171:3a7713b1edbc 8101 /* */
AnnaBridge 171:3a7713b1edbc 8102 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8103 /******************** Master Timer control register ***************************/
AnnaBridge 171:3a7713b1edbc 8104 #define HRTIM_MCR_CK_PSC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8105 #define HRTIM_MCR_CK_PSC_Msk (0x7U << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 8106 #define HRTIM_MCR_CK_PSC HRTIM_MCR_CK_PSC_Msk /*!< Prescaler mask */
AnnaBridge 171:3a7713b1edbc 8107 #define HRTIM_MCR_CK_PSC_0 (0x1U << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8108 #define HRTIM_MCR_CK_PSC_1 (0x2U << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8109 #define HRTIM_MCR_CK_PSC_2 (0x4U << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8110
AnnaBridge 171:3a7713b1edbc 8111 #define HRTIM_MCR_CONT_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8112 #define HRTIM_MCR_CONT_Msk (0x1U << HRTIM_MCR_CONT_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8113 #define HRTIM_MCR_CONT HRTIM_MCR_CONT_Msk /*!< Continuous mode */
AnnaBridge 171:3a7713b1edbc 8114 #define HRTIM_MCR_RETRIG_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8115 #define HRTIM_MCR_RETRIG_Msk (0x1U << HRTIM_MCR_RETRIG_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8116 #define HRTIM_MCR_RETRIG HRTIM_MCR_RETRIG_Msk /*!< Rettrigreable mode */
AnnaBridge 171:3a7713b1edbc 8117 #define HRTIM_MCR_HALF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 8118 #define HRTIM_MCR_HALF_Msk (0x1U << HRTIM_MCR_HALF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8119 #define HRTIM_MCR_HALF HRTIM_MCR_HALF_Msk /*!< Half mode */
AnnaBridge 171:3a7713b1edbc 8120
AnnaBridge 171:3a7713b1edbc 8121 #define HRTIM_MCR_SYNC_IN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8122 #define HRTIM_MCR_SYNC_IN_Msk (0x3U << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 8123 #define HRTIM_MCR_SYNC_IN HRTIM_MCR_SYNC_IN_Msk /*!< Synchronization input master */
AnnaBridge 171:3a7713b1edbc 8124 #define HRTIM_MCR_SYNC_IN_0 (0x1U << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8125 #define HRTIM_MCR_SYNC_IN_1 (0x2U << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8126 #define HRTIM_MCR_SYNCRSTM_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8127 #define HRTIM_MCR_SYNCRSTM_Msk (0x1U << HRTIM_MCR_SYNCRSTM_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8128 #define HRTIM_MCR_SYNCRSTM HRTIM_MCR_SYNCRSTM_Msk /*!< Synchronization reset master */
AnnaBridge 171:3a7713b1edbc 8129 #define HRTIM_MCR_SYNCSTRTM_Pos (11U)
AnnaBridge 171:3a7713b1edbc 8130 #define HRTIM_MCR_SYNCSTRTM_Msk (0x1U << HRTIM_MCR_SYNCSTRTM_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8131 #define HRTIM_MCR_SYNCSTRTM HRTIM_MCR_SYNCSTRTM_Msk /*!< Synchronization start master */
AnnaBridge 171:3a7713b1edbc 8132 #define HRTIM_MCR_SYNC_OUT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8133 #define HRTIM_MCR_SYNC_OUT_Msk (0x3U << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 8134 #define HRTIM_MCR_SYNC_OUT HRTIM_MCR_SYNC_OUT_Msk /*!< Synchronization output master */
AnnaBridge 171:3a7713b1edbc 8135 #define HRTIM_MCR_SYNC_OUT_0 (0x1U << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8136 #define HRTIM_MCR_SYNC_OUT_1 (0x2U << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8137 #define HRTIM_MCR_SYNC_SRC_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8138 #define HRTIM_MCR_SYNC_SRC_Msk (0x3U << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 8139 #define HRTIM_MCR_SYNC_SRC HRTIM_MCR_SYNC_SRC_Msk /*!< Synchronization source */
AnnaBridge 171:3a7713b1edbc 8140 #define HRTIM_MCR_SYNC_SRC_0 (0x1U << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8141 #define HRTIM_MCR_SYNC_SRC_1 (0x2U << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8142
AnnaBridge 171:3a7713b1edbc 8143 #define HRTIM_MCR_MCEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8144 #define HRTIM_MCR_MCEN_Msk (0x1U << HRTIM_MCR_MCEN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8145 #define HRTIM_MCR_MCEN HRTIM_MCR_MCEN_Msk /*!< Master counter enable */
AnnaBridge 171:3a7713b1edbc 8146 #define HRTIM_MCR_TACEN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 8147 #define HRTIM_MCR_TACEN_Msk (0x1U << HRTIM_MCR_TACEN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8148 #define HRTIM_MCR_TACEN HRTIM_MCR_TACEN_Msk /*!< Timer A counter enable */
AnnaBridge 171:3a7713b1edbc 8149 #define HRTIM_MCR_TBCEN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 8150 #define HRTIM_MCR_TBCEN_Msk (0x1U << HRTIM_MCR_TBCEN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8151 #define HRTIM_MCR_TBCEN HRTIM_MCR_TBCEN_Msk /*!< Timer B counter enable */
AnnaBridge 171:3a7713b1edbc 8152 #define HRTIM_MCR_TCCEN_Pos (19U)
AnnaBridge 171:3a7713b1edbc 8153 #define HRTIM_MCR_TCCEN_Msk (0x1U << HRTIM_MCR_TCCEN_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8154 #define HRTIM_MCR_TCCEN HRTIM_MCR_TCCEN_Msk /*!< Timer C counter enable */
AnnaBridge 171:3a7713b1edbc 8155 #define HRTIM_MCR_TDCEN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 8156 #define HRTIM_MCR_TDCEN_Msk (0x1U << HRTIM_MCR_TDCEN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8157 #define HRTIM_MCR_TDCEN HRTIM_MCR_TDCEN_Msk /*!< Timer D counter enable */
AnnaBridge 171:3a7713b1edbc 8158 #define HRTIM_MCR_TECEN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 8159 #define HRTIM_MCR_TECEN_Msk (0x1U << HRTIM_MCR_TECEN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8160 #define HRTIM_MCR_TECEN HRTIM_MCR_TECEN_Msk /*!< Timer E counter enable */
AnnaBridge 171:3a7713b1edbc 8161
AnnaBridge 171:3a7713b1edbc 8162 #define HRTIM_MCR_DACSYNC_Pos (25U)
AnnaBridge 171:3a7713b1edbc 8163 #define HRTIM_MCR_DACSYNC_Msk (0x3U << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */
AnnaBridge 171:3a7713b1edbc 8164 #define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */
AnnaBridge 171:3a7713b1edbc 8165 #define HRTIM_MCR_DACSYNC_0 (0x1U << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8166 #define HRTIM_MCR_DACSYNC_1 (0x2U << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8167
AnnaBridge 171:3a7713b1edbc 8168 #define HRTIM_MCR_PREEN_Pos (27U)
AnnaBridge 171:3a7713b1edbc 8169 #define HRTIM_MCR_PREEN_Msk (0x1U << HRTIM_MCR_PREEN_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 8170 #define HRTIM_MCR_PREEN HRTIM_MCR_PREEN_Msk /*!< Master preload enable */
AnnaBridge 171:3a7713b1edbc 8171 #define HRTIM_MCR_MREPU_Pos (29U)
AnnaBridge 171:3a7713b1edbc 8172 #define HRTIM_MCR_MREPU_Msk (0x1U << HRTIM_MCR_MREPU_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 8173 #define HRTIM_MCR_MREPU HRTIM_MCR_MREPU_Msk /*!< Master repetition update */
AnnaBridge 171:3a7713b1edbc 8174
AnnaBridge 171:3a7713b1edbc 8175 #define HRTIM_MCR_BRSTDMA_Pos (30U)
AnnaBridge 171:3a7713b1edbc 8176 #define HRTIM_MCR_BRSTDMA_Msk (0x3U << HRTIM_MCR_BRSTDMA_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 8177 #define HRTIM_MCR_BRSTDMA HRTIM_MCR_BRSTDMA_Msk /*!< Burst DMA update */
AnnaBridge 171:3a7713b1edbc 8178 #define HRTIM_MCR_BRSTDMA_0 (0x1U << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 8179 #define HRTIM_MCR_BRSTDMA_1 (0x2U << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 8180
AnnaBridge 171:3a7713b1edbc 8181 /******************** Master Timer Interrupt status register ******************/
AnnaBridge 171:3a7713b1edbc 8182 #define HRTIM_MISR_MCMP1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8183 #define HRTIM_MISR_MCMP1_Msk (0x1U << HRTIM_MISR_MCMP1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8184 #define HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1_Msk /*!< Master compare 1 interrupt flag */
AnnaBridge 171:3a7713b1edbc 8185 #define HRTIM_MISR_MCMP2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8186 #define HRTIM_MISR_MCMP2_Msk (0x1U << HRTIM_MISR_MCMP2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8187 #define HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2_Msk /*!< Master compare 2 interrupt flag */
AnnaBridge 171:3a7713b1edbc 8188 #define HRTIM_MISR_MCMP3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8189 #define HRTIM_MISR_MCMP3_Msk (0x1U << HRTIM_MISR_MCMP3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8190 #define HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3_Msk /*!< Master compare 3 interrupt flag */
AnnaBridge 171:3a7713b1edbc 8191 #define HRTIM_MISR_MCMP4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8192 #define HRTIM_MISR_MCMP4_Msk (0x1U << HRTIM_MISR_MCMP4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8193 #define HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4_Msk /*!< Master compare 4 interrupt flag */
AnnaBridge 171:3a7713b1edbc 8194 #define HRTIM_MISR_MREP_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8195 #define HRTIM_MISR_MREP_Msk (0x1U << HRTIM_MISR_MREP_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8196 #define HRTIM_MISR_MREP HRTIM_MISR_MREP_Msk /*!< Master Repetition interrupt flag */
AnnaBridge 171:3a7713b1edbc 8197 #define HRTIM_MISR_SYNC_Pos (5U)
AnnaBridge 171:3a7713b1edbc 8198 #define HRTIM_MISR_SYNC_Msk (0x1U << HRTIM_MISR_SYNC_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8199 #define HRTIM_MISR_SYNC HRTIM_MISR_SYNC_Msk /*!< Synchronization input interrupt flag */
AnnaBridge 171:3a7713b1edbc 8200 #define HRTIM_MISR_MUPD_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8201 #define HRTIM_MISR_MUPD_Msk (0x1U << HRTIM_MISR_MUPD_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8202 #define HRTIM_MISR_MUPD HRTIM_MISR_MUPD_Msk /*!< Master update interrupt flag */
AnnaBridge 171:3a7713b1edbc 8203
AnnaBridge 171:3a7713b1edbc 8204 /******************** Master Timer Interrupt clear register *******************/
AnnaBridge 171:3a7713b1edbc 8205 #define HRTIM_MICR_MCMP1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8206 #define HRTIM_MICR_MCMP1_Msk (0x1U << HRTIM_MICR_MCMP1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8207 #define HRTIM_MICR_MCMP1 HRTIM_MICR_MCMP1_Msk /*!< Master compare 1 interrupt flag clear */
AnnaBridge 171:3a7713b1edbc 8208 #define HRTIM_MICR_MCMP2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8209 #define HRTIM_MICR_MCMP2_Msk (0x1U << HRTIM_MICR_MCMP2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8210 #define HRTIM_MICR_MCMP2 HRTIM_MICR_MCMP2_Msk /*!< Master compare 2 interrupt flag clear */
AnnaBridge 171:3a7713b1edbc 8211 #define HRTIM_MICR_MCMP3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8212 #define HRTIM_MICR_MCMP3_Msk (0x1U << HRTIM_MICR_MCMP3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8213 #define HRTIM_MICR_MCMP3 HRTIM_MICR_MCMP3_Msk /*!< Master compare 3 interrupt flag clear */
AnnaBridge 171:3a7713b1edbc 8214 #define HRTIM_MICR_MCMP4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8215 #define HRTIM_MICR_MCMP4_Msk (0x1U << HRTIM_MICR_MCMP4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8216 #define HRTIM_MICR_MCMP4 HRTIM_MICR_MCMP4_Msk /*!< Master compare 4 interrupt flag clear */
AnnaBridge 171:3a7713b1edbc 8217 #define HRTIM_MICR_MREP_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8218 #define HRTIM_MICR_MREP_Msk (0x1U << HRTIM_MICR_MREP_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8219 #define HRTIM_MICR_MREP HRTIM_MICR_MREP_Msk /*!< Master Repetition interrupt flag clear */
AnnaBridge 171:3a7713b1edbc 8220 #define HRTIM_MICR_SYNC_Pos (5U)
AnnaBridge 171:3a7713b1edbc 8221 #define HRTIM_MICR_SYNC_Msk (0x1U << HRTIM_MICR_SYNC_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8222 #define HRTIM_MICR_SYNC HRTIM_MICR_SYNC_Msk /*!< Synchronization input interrupt flag clear */
AnnaBridge 171:3a7713b1edbc 8223 #define HRTIM_MICR_MUPD_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8224 #define HRTIM_MICR_MUPD_Msk (0x1U << HRTIM_MICR_MUPD_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8225 #define HRTIM_MICR_MUPD HRTIM_MICR_MUPD_Msk /*!< Master update interrupt flag clear */
AnnaBridge 171:3a7713b1edbc 8226
AnnaBridge 171:3a7713b1edbc 8227 /******************** Master Timer DMA/Interrupt enable register **************/
AnnaBridge 171:3a7713b1edbc 8228 #define HRTIM_MDIER_MCMP1IE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8229 #define HRTIM_MDIER_MCMP1IE_Msk (0x1U << HRTIM_MDIER_MCMP1IE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8230 #define HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE_Msk /*!< Master compare 1 interrupt enable */
AnnaBridge 171:3a7713b1edbc 8231 #define HRTIM_MDIER_MCMP2IE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8232 #define HRTIM_MDIER_MCMP2IE_Msk (0x1U << HRTIM_MDIER_MCMP2IE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8233 #define HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE_Msk /*!< Master compare 2 interrupt enable */
AnnaBridge 171:3a7713b1edbc 8234 #define HRTIM_MDIER_MCMP3IE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8235 #define HRTIM_MDIER_MCMP3IE_Msk (0x1U << HRTIM_MDIER_MCMP3IE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8236 #define HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE_Msk /*!< Master compare 3 interrupt enable */
AnnaBridge 171:3a7713b1edbc 8237 #define HRTIM_MDIER_MCMP4IE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8238 #define HRTIM_MDIER_MCMP4IE_Msk (0x1U << HRTIM_MDIER_MCMP4IE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8239 #define HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE_Msk /*!< Master compare 4 interrupt enable */
AnnaBridge 171:3a7713b1edbc 8240 #define HRTIM_MDIER_MREPIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8241 #define HRTIM_MDIER_MREPIE_Msk (0x1U << HRTIM_MDIER_MREPIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8242 #define HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE_Msk /*!< Master Repetition interrupt enable */
AnnaBridge 171:3a7713b1edbc 8243 #define HRTIM_MDIER_SYNCIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 8244 #define HRTIM_MDIER_SYNCIE_Msk (0x1U << HRTIM_MDIER_SYNCIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8245 #define HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE_Msk /*!< Synchronization input interrupt enable */
AnnaBridge 171:3a7713b1edbc 8246 #define HRTIM_MDIER_MUPDIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8247 #define HRTIM_MDIER_MUPDIE_Msk (0x1U << HRTIM_MDIER_MUPDIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8248 #define HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE_Msk /*!< Master update interrupt enable */
AnnaBridge 171:3a7713b1edbc 8249
AnnaBridge 171:3a7713b1edbc 8250 #define HRTIM_MDIER_MCMP1DE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8251 #define HRTIM_MDIER_MCMP1DE_Msk (0x1U << HRTIM_MDIER_MCMP1DE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8252 #define HRTIM_MDIER_MCMP1DE HRTIM_MDIER_MCMP1DE_Msk /*!< Master compare 1 DMA enable */
AnnaBridge 171:3a7713b1edbc 8253 #define HRTIM_MDIER_MCMP2DE_Pos (17U)
AnnaBridge 171:3a7713b1edbc 8254 #define HRTIM_MDIER_MCMP2DE_Msk (0x1U << HRTIM_MDIER_MCMP2DE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8255 #define HRTIM_MDIER_MCMP2DE HRTIM_MDIER_MCMP2DE_Msk /*!< Master compare 2 DMA enable */
AnnaBridge 171:3a7713b1edbc 8256 #define HRTIM_MDIER_MCMP3DE_Pos (18U)
AnnaBridge 171:3a7713b1edbc 8257 #define HRTIM_MDIER_MCMP3DE_Msk (0x1U << HRTIM_MDIER_MCMP3DE_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8258 #define HRTIM_MDIER_MCMP3DE HRTIM_MDIER_MCMP3DE_Msk /*!< Master compare 3 DMA enable */
AnnaBridge 171:3a7713b1edbc 8259 #define HRTIM_MDIER_MCMP4DE_Pos (19U)
AnnaBridge 171:3a7713b1edbc 8260 #define HRTIM_MDIER_MCMP4DE_Msk (0x1U << HRTIM_MDIER_MCMP4DE_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8261 #define HRTIM_MDIER_MCMP4DE HRTIM_MDIER_MCMP4DE_Msk /*!< Master compare 4 DMA enable */
AnnaBridge 171:3a7713b1edbc 8262 #define HRTIM_MDIER_MREPDE_Pos (20U)
AnnaBridge 171:3a7713b1edbc 8263 #define HRTIM_MDIER_MREPDE_Msk (0x1U << HRTIM_MDIER_MREPDE_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8264 #define HRTIM_MDIER_MREPDE HRTIM_MDIER_MREPDE_Msk /*!< Master Repetition DMA enable */
AnnaBridge 171:3a7713b1edbc 8265 #define HRTIM_MDIER_SYNCDE_Pos (21U)
AnnaBridge 171:3a7713b1edbc 8266 #define HRTIM_MDIER_SYNCDE_Msk (0x1U << HRTIM_MDIER_SYNCDE_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8267 #define HRTIM_MDIER_SYNCDE HRTIM_MDIER_SYNCDE_Msk /*!< Synchronization input DMA enable */
AnnaBridge 171:3a7713b1edbc 8268 #define HRTIM_MDIER_MUPDDE_Pos (22U)
AnnaBridge 171:3a7713b1edbc 8269 #define HRTIM_MDIER_MUPDDE_Msk (0x1U << HRTIM_MDIER_MUPDDE_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8270 #define HRTIM_MDIER_MUPDDE HRTIM_MDIER_MUPDDE_Msk /*!< Master update DMA enable */
AnnaBridge 171:3a7713b1edbc 8271
AnnaBridge 171:3a7713b1edbc 8272 /******************* Bit definition for HRTIM_MCNTR register ****************/
AnnaBridge 171:3a7713b1edbc 8273 #define HRTIM_MCNTR_MCNTR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8274 #define HRTIM_MCNTR_MCNTR_Msk (0xFFFFFFFFU << HRTIM_MCNTR_MCNTR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8275 #define HRTIM_MCNTR_MCNTR HRTIM_MCNTR_MCNTR_Msk /*!<Counter Value */
AnnaBridge 171:3a7713b1edbc 8276
AnnaBridge 171:3a7713b1edbc 8277 /******************* Bit definition for HRTIM_MPER register *****************/
AnnaBridge 171:3a7713b1edbc 8278 #define HRTIM_MPER_MPER_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8279 #define HRTIM_MPER_MPER_Msk (0xFFFFFFFFU << HRTIM_MPER_MPER_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8280 #define HRTIM_MPER_MPER HRTIM_MPER_MPER_Msk /*!< Period Value */
AnnaBridge 171:3a7713b1edbc 8281
AnnaBridge 171:3a7713b1edbc 8282 /******************* Bit definition for HRTIM_MREP register *****************/
AnnaBridge 171:3a7713b1edbc 8283 #define HRTIM_MREP_MREP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8284 #define HRTIM_MREP_MREP_Msk (0xFFFFFFFFU << HRTIM_MREP_MREP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8285 #define HRTIM_MREP_MREP HRTIM_MREP_MREP_Msk /*!<Repetition Value */
AnnaBridge 171:3a7713b1edbc 8286
AnnaBridge 171:3a7713b1edbc 8287 /******************* Bit definition for HRTIM_MCMP1R register *****************/
AnnaBridge 171:3a7713b1edbc 8288 #define HRTIM_MCMP1R_MCMP1R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8289 #define HRTIM_MCMP1R_MCMP1R_Msk (0xFFFFFFFFU << HRTIM_MCMP1R_MCMP1R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8290 #define HRTIM_MCMP1R_MCMP1R HRTIM_MCMP1R_MCMP1R_Msk /*!<Compare Value */
AnnaBridge 171:3a7713b1edbc 8291
AnnaBridge 171:3a7713b1edbc 8292 /******************* Bit definition for HRTIM_MCMP2R register *****************/
AnnaBridge 171:3a7713b1edbc 8293 #define HRTIM_MCMP2R_MCMP2R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8294 #define HRTIM_MCMP2R_MCMP2R_Msk (0xFFFFFFFFU << HRTIM_MCMP2R_MCMP2R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8295 #define HRTIM_MCMP2R_MCMP2R HRTIM_MCMP2R_MCMP2R_Msk /*!<Compare Value */
AnnaBridge 171:3a7713b1edbc 8296
AnnaBridge 171:3a7713b1edbc 8297 /******************* Bit definition for HRTIM_MCMP3R register *****************/
AnnaBridge 171:3a7713b1edbc 8298 #define HRTIM_MCMP3R_MCMP3R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8299 #define HRTIM_MCMP3R_MCMP3R_Msk (0xFFFFFFFFU << HRTIM_MCMP3R_MCMP3R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8300 #define HRTIM_MCMP3R_MCMP3R HRTIM_MCMP3R_MCMP3R_Msk /*!<Compare Value */
AnnaBridge 171:3a7713b1edbc 8301
AnnaBridge 171:3a7713b1edbc 8302 /******************* Bit definition for HRTIM_MCMP4R register *****************/
AnnaBridge 171:3a7713b1edbc 8303 #define HRTIM_MCMP4R_MCMP4R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8304 #define HRTIM_MCMP4R_MCMP4R_Msk (0xFFFFFFFFU << HRTIM_MCMP4R_MCMP4R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8305 #define HRTIM_MCMP4R_MCMP4R HRTIM_MCMP4R_MCMP4R_Msk /*!<Compare Value */
AnnaBridge 171:3a7713b1edbc 8306
AnnaBridge 171:3a7713b1edbc 8307 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 8308 #define HRTIM_MCMP1R_MCMP2R HRTIM_MCMP2R_MCMP2R
AnnaBridge 171:3a7713b1edbc 8309 #define HRTIM_MCMP1R_MCMP3R HRTIM_MCMP3R_MCMP3R
AnnaBridge 171:3a7713b1edbc 8310 #define HRTIM_MCMP1R_MCMP4R HRTIM_MCMP4R_MCMP4R
AnnaBridge 171:3a7713b1edbc 8311
AnnaBridge 171:3a7713b1edbc 8312 /******************** Slave control register **********************************/
AnnaBridge 171:3a7713b1edbc 8313 #define HRTIM_TIMCR_CK_PSC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8314 #define HRTIM_TIMCR_CK_PSC_Msk (0x7U << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 8315 #define HRTIM_TIMCR_CK_PSC HRTIM_TIMCR_CK_PSC_Msk /*!< Slave prescaler mask*/
AnnaBridge 171:3a7713b1edbc 8316 #define HRTIM_TIMCR_CK_PSC_0 (0x1U << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8317 #define HRTIM_TIMCR_CK_PSC_1 (0x2U << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8318 #define HRTIM_TIMCR_CK_PSC_2 (0x4U << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8319
AnnaBridge 171:3a7713b1edbc 8320 #define HRTIM_TIMCR_CONT_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8321 #define HRTIM_TIMCR_CONT_Msk (0x1U << HRTIM_TIMCR_CONT_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8322 #define HRTIM_TIMCR_CONT HRTIM_TIMCR_CONT_Msk /*!< Slave continuous mode */
AnnaBridge 171:3a7713b1edbc 8323 #define HRTIM_TIMCR_RETRIG_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8324 #define HRTIM_TIMCR_RETRIG_Msk (0x1U << HRTIM_TIMCR_RETRIG_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8325 #define HRTIM_TIMCR_RETRIG HRTIM_TIMCR_RETRIG_Msk /*!< Slave Retrigreable mode */
AnnaBridge 171:3a7713b1edbc 8326 #define HRTIM_TIMCR_HALF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 8327 #define HRTIM_TIMCR_HALF_Msk (0x1U << HRTIM_TIMCR_HALF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8328 #define HRTIM_TIMCR_HALF HRTIM_TIMCR_HALF_Msk /*!< Slave Half mode */
AnnaBridge 171:3a7713b1edbc 8329 #define HRTIM_TIMCR_PSHPLL_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8330 #define HRTIM_TIMCR_PSHPLL_Msk (0x1U << HRTIM_TIMCR_PSHPLL_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8331 #define HRTIM_TIMCR_PSHPLL HRTIM_TIMCR_PSHPLL_Msk /*!< Slave push-pull mode */
AnnaBridge 171:3a7713b1edbc 8332
AnnaBridge 171:3a7713b1edbc 8333 #define HRTIM_TIMCR_SYNCRST_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8334 #define HRTIM_TIMCR_SYNCRST_Msk (0x1U << HRTIM_TIMCR_SYNCRST_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8335 #define HRTIM_TIMCR_SYNCRST HRTIM_TIMCR_SYNCRST_Msk /*!< Slave synchronization resets */
AnnaBridge 171:3a7713b1edbc 8336 #define HRTIM_TIMCR_SYNCSTRT_Pos (11U)
AnnaBridge 171:3a7713b1edbc 8337 #define HRTIM_TIMCR_SYNCSTRT_Msk (0x1U << HRTIM_TIMCR_SYNCSTRT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8338 #define HRTIM_TIMCR_SYNCSTRT HRTIM_TIMCR_SYNCSTRT_Msk /*!< Slave synchronization starts */
AnnaBridge 171:3a7713b1edbc 8339
AnnaBridge 171:3a7713b1edbc 8340 #define HRTIM_TIMCR_DELCMP2_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8341 #define HRTIM_TIMCR_DELCMP2_Msk (0x3U << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 8342 #define HRTIM_TIMCR_DELCMP2 HRTIM_TIMCR_DELCMP2_Msk /*!< Slave delayed compartor 2 mode mask */
AnnaBridge 171:3a7713b1edbc 8343 #define HRTIM_TIMCR_DELCMP2_0 (0x1U << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8344 #define HRTIM_TIMCR_DELCMP2_1 (0x2U << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8345 #define HRTIM_TIMCR_DELCMP4_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8346 #define HRTIM_TIMCR_DELCMP4_Msk (0x3U << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 8347 #define HRTIM_TIMCR_DELCMP4 HRTIM_TIMCR_DELCMP4_Msk /*!< Slave delayed compartor 4 mode mask */
AnnaBridge 171:3a7713b1edbc 8348 #define HRTIM_TIMCR_DELCMP4_0 (0x1U << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8349 #define HRTIM_TIMCR_DELCMP4_1 (0x2U << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8350
AnnaBridge 171:3a7713b1edbc 8351 #define HRTIM_TIMCR_TREPU_Pos (17U)
AnnaBridge 171:3a7713b1edbc 8352 #define HRTIM_TIMCR_TREPU_Msk (0x1U << HRTIM_TIMCR_TREPU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8353 #define HRTIM_TIMCR_TREPU HRTIM_TIMCR_TREPU_Msk /*!< Slave repetition update */
AnnaBridge 171:3a7713b1edbc 8354 #define HRTIM_TIMCR_TRSTU_Pos (18U)
AnnaBridge 171:3a7713b1edbc 8355 #define HRTIM_TIMCR_TRSTU_Msk (0x1U << HRTIM_TIMCR_TRSTU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8356 #define HRTIM_TIMCR_TRSTU HRTIM_TIMCR_TRSTU_Msk /*!< Slave reset update */
AnnaBridge 171:3a7713b1edbc 8357 #define HRTIM_TIMCR_TAU_Pos (19U)
AnnaBridge 171:3a7713b1edbc 8358 #define HRTIM_TIMCR_TAU_Msk (0x1U << HRTIM_TIMCR_TAU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8359 #define HRTIM_TIMCR_TAU HRTIM_TIMCR_TAU_Msk /*!< Slave Timer A update reserved for TIM A */
AnnaBridge 171:3a7713b1edbc 8360 #define HRTIM_TIMCR_TBU_Pos (20U)
AnnaBridge 171:3a7713b1edbc 8361 #define HRTIM_TIMCR_TBU_Msk (0x1U << HRTIM_TIMCR_TBU_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8362 #define HRTIM_TIMCR_TBU HRTIM_TIMCR_TBU_Msk /*!< Slave Timer B update reserved for TIM B */
AnnaBridge 171:3a7713b1edbc 8363 #define HRTIM_TIMCR_TCU_Pos (21U)
AnnaBridge 171:3a7713b1edbc 8364 #define HRTIM_TIMCR_TCU_Msk (0x1U << HRTIM_TIMCR_TCU_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8365 #define HRTIM_TIMCR_TCU HRTIM_TIMCR_TCU_Msk /*!< Slave Timer C update reserved for TIM C */
AnnaBridge 171:3a7713b1edbc 8366 #define HRTIM_TIMCR_TDU_Pos (22U)
AnnaBridge 171:3a7713b1edbc 8367 #define HRTIM_TIMCR_TDU_Msk (0x1U << HRTIM_TIMCR_TDU_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8368 #define HRTIM_TIMCR_TDU HRTIM_TIMCR_TDU_Msk /*!< Slave Timer D update reserved for TIM D */
AnnaBridge 171:3a7713b1edbc 8369 #define HRTIM_TIMCR_TEU_Pos (23U)
AnnaBridge 171:3a7713b1edbc 8370 #define HRTIM_TIMCR_TEU_Msk (0x1U << HRTIM_TIMCR_TEU_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 8371 #define HRTIM_TIMCR_TEU HRTIM_TIMCR_TEU_Msk /*!< Slave Timer E update reserved for TIM E */
AnnaBridge 171:3a7713b1edbc 8372 #define HRTIM_TIMCR_MSTU_Pos (24U)
AnnaBridge 171:3a7713b1edbc 8373 #define HRTIM_TIMCR_MSTU_Msk (0x1U << HRTIM_TIMCR_MSTU_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8374 #define HRTIM_TIMCR_MSTU HRTIM_TIMCR_MSTU_Msk /*!< Master Update */
AnnaBridge 171:3a7713b1edbc 8375
AnnaBridge 171:3a7713b1edbc 8376 #define HRTIM_TIMCR_DACSYNC_Pos (25U)
AnnaBridge 171:3a7713b1edbc 8377 #define HRTIM_TIMCR_DACSYNC_Msk (0x3U << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */
AnnaBridge 171:3a7713b1edbc 8378 #define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */
AnnaBridge 171:3a7713b1edbc 8379 #define HRTIM_TIMCR_DACSYNC_0 (0x1U << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8380 #define HRTIM_TIMCR_DACSYNC_1 (0x2U << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8381 #define HRTIM_TIMCR_PREEN_Pos (27U)
AnnaBridge 171:3a7713b1edbc 8382 #define HRTIM_TIMCR_PREEN_Msk (0x1U << HRTIM_TIMCR_PREEN_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 8383 #define HRTIM_TIMCR_PREEN HRTIM_TIMCR_PREEN_Msk /*!< Slave preload enable */
AnnaBridge 171:3a7713b1edbc 8384
AnnaBridge 171:3a7713b1edbc 8385 #define HRTIM_TIMCR_UPDGAT_Pos (28U)
AnnaBridge 171:3a7713b1edbc 8386 #define HRTIM_TIMCR_UPDGAT_Msk (0xFU << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0xF0000000 */
AnnaBridge 171:3a7713b1edbc 8387 #define HRTIM_TIMCR_UPDGAT HRTIM_TIMCR_UPDGAT_Msk /*!< Slave update gating mask */
AnnaBridge 171:3a7713b1edbc 8388 #define HRTIM_TIMCR_UPDGAT_0 (0x1U << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 8389 #define HRTIM_TIMCR_UPDGAT_1 (0x2U << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 8390 #define HRTIM_TIMCR_UPDGAT_2 (0x4U << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 8391 #define HRTIM_TIMCR_UPDGAT_3 (0x8U << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 8392
AnnaBridge 171:3a7713b1edbc 8393 /******************** Slave Interrupt status register **************************/
AnnaBridge 171:3a7713b1edbc 8394 #define HRTIM_TIMISR_CMP1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8395 #define HRTIM_TIMISR_CMP1_Msk (0x1U << HRTIM_TIMISR_CMP1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8396 #define HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1_Msk /*!< Slave compare 1 interrupt flag */
AnnaBridge 171:3a7713b1edbc 8397 #define HRTIM_TIMISR_CMP2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8398 #define HRTIM_TIMISR_CMP2_Msk (0x1U << HRTIM_TIMISR_CMP2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8399 #define HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2_Msk /*!< Slave compare 2 interrupt flag */
AnnaBridge 171:3a7713b1edbc 8400 #define HRTIM_TIMISR_CMP3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8401 #define HRTIM_TIMISR_CMP3_Msk (0x1U << HRTIM_TIMISR_CMP3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8402 #define HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3_Msk /*!< Slave compare 3 interrupt flag */
AnnaBridge 171:3a7713b1edbc 8403 #define HRTIM_TIMISR_CMP4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8404 #define HRTIM_TIMISR_CMP4_Msk (0x1U << HRTIM_TIMISR_CMP4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8405 #define HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4_Msk /*!< Slave compare 4 interrupt flag */
AnnaBridge 171:3a7713b1edbc 8406 #define HRTIM_TIMISR_REP_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8407 #define HRTIM_TIMISR_REP_Msk (0x1U << HRTIM_TIMISR_REP_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8408 #define HRTIM_TIMISR_REP HRTIM_TIMISR_REP_Msk /*!< Slave repetition interrupt flag */
AnnaBridge 171:3a7713b1edbc 8409 #define HRTIM_TIMISR_UPD_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8410 #define HRTIM_TIMISR_UPD_Msk (0x1U << HRTIM_TIMISR_UPD_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8411 #define HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD_Msk /*!< Slave update interrupt flag */
AnnaBridge 171:3a7713b1edbc 8412 #define HRTIM_TIMISR_CPT1_Pos (7U)
AnnaBridge 171:3a7713b1edbc 8413 #define HRTIM_TIMISR_CPT1_Msk (0x1U << HRTIM_TIMISR_CPT1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8414 #define HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1_Msk /*!< Slave capture 1 interrupt flag */
AnnaBridge 171:3a7713b1edbc 8415 #define HRTIM_TIMISR_CPT2_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8416 #define HRTIM_TIMISR_CPT2_Msk (0x1U << HRTIM_TIMISR_CPT2_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8417 #define HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2_Msk /*!< Slave capture 2 interrupt flag */
AnnaBridge 171:3a7713b1edbc 8418 #define HRTIM_TIMISR_SET1_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8419 #define HRTIM_TIMISR_SET1_Msk (0x1U << HRTIM_TIMISR_SET1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8420 #define HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1_Msk /*!< Slave output 1 set interrupt flag */
AnnaBridge 171:3a7713b1edbc 8421 #define HRTIM_TIMISR_RST1_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8422 #define HRTIM_TIMISR_RST1_Msk (0x1U << HRTIM_TIMISR_RST1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8423 #define HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1_Msk /*!< Slave output 1 reset interrupt flag */
AnnaBridge 171:3a7713b1edbc 8424 #define HRTIM_TIMISR_SET2_Pos (11U)
AnnaBridge 171:3a7713b1edbc 8425 #define HRTIM_TIMISR_SET2_Msk (0x1U << HRTIM_TIMISR_SET2_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8426 #define HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2_Msk /*!< Slave output 2 set interrupt flag */
AnnaBridge 171:3a7713b1edbc 8427 #define HRTIM_TIMISR_RST2_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8428 #define HRTIM_TIMISR_RST2_Msk (0x1U << HRTIM_TIMISR_RST2_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8429 #define HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2_Msk /*!< Slave output 2 reset interrupt flag */
AnnaBridge 171:3a7713b1edbc 8430 #define HRTIM_TIMISR_RST_Pos (13U)
AnnaBridge 171:3a7713b1edbc 8431 #define HRTIM_TIMISR_RST_Msk (0x1U << HRTIM_TIMISR_RST_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8432 #define HRTIM_TIMISR_RST HRTIM_TIMISR_RST_Msk /*!< Slave reset interrupt flag */
AnnaBridge 171:3a7713b1edbc 8433 #define HRTIM_TIMISR_DLYPRT_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8434 #define HRTIM_TIMISR_DLYPRT_Msk (0x1U << HRTIM_TIMISR_DLYPRT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8435 #define HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT_Msk /*!< Slave output 1 delay protection interrupt flag */
AnnaBridge 171:3a7713b1edbc 8436 #define HRTIM_TIMISR_CPPSTAT_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8437 #define HRTIM_TIMISR_CPPSTAT_Msk (0x1U << HRTIM_TIMISR_CPPSTAT_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8438 #define HRTIM_TIMISR_CPPSTAT HRTIM_TIMISR_CPPSTAT_Msk /*!< Slave current push-pull flag */
AnnaBridge 171:3a7713b1edbc 8439 #define HRTIM_TIMISR_IPPSTAT_Pos (17U)
AnnaBridge 171:3a7713b1edbc 8440 #define HRTIM_TIMISR_IPPSTAT_Msk (0x1U << HRTIM_TIMISR_IPPSTAT_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8441 #define HRTIM_TIMISR_IPPSTAT HRTIM_TIMISR_IPPSTAT_Msk /*!< Slave idle push-pull flag */
AnnaBridge 171:3a7713b1edbc 8442 #define HRTIM_TIMISR_O1STAT_Pos (18U)
AnnaBridge 171:3a7713b1edbc 8443 #define HRTIM_TIMISR_O1STAT_Msk (0x1U << HRTIM_TIMISR_O1STAT_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8444 #define HRTIM_TIMISR_O1STAT HRTIM_TIMISR_O1STAT_Msk /*!< Slave output 1 state flag */
AnnaBridge 171:3a7713b1edbc 8445 #define HRTIM_TIMISR_O2STAT_Pos (19U)
AnnaBridge 171:3a7713b1edbc 8446 #define HRTIM_TIMISR_O2STAT_Msk (0x1U << HRTIM_TIMISR_O2STAT_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8447 #define HRTIM_TIMISR_O2STAT HRTIM_TIMISR_O2STAT_Msk /*!< Slave output 2 state flag */
AnnaBridge 171:3a7713b1edbc 8448 #define HRTIM_TIMISR_O1CPY_Pos (20U)
AnnaBridge 171:3a7713b1edbc 8449 #define HRTIM_TIMISR_O1CPY_Msk (0x1U << HRTIM_TIMISR_O1CPY_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8450 #define HRTIM_TIMISR_O1CPY HRTIM_TIMISR_O1CPY_Msk /*!< Slave output 1 copy flag */
AnnaBridge 171:3a7713b1edbc 8451 #define HRTIM_TIMISR_O2CPY_Pos (21U)
AnnaBridge 171:3a7713b1edbc 8452 #define HRTIM_TIMISR_O2CPY_Msk (0x1U << HRTIM_TIMISR_O2CPY_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8453 #define HRTIM_TIMISR_O2CPY HRTIM_TIMISR_O2CPY_Msk /*!< Slave output 2 copy flag */
AnnaBridge 171:3a7713b1edbc 8454
AnnaBridge 171:3a7713b1edbc 8455 /******************** Slave Interrupt clear register **************************/
AnnaBridge 171:3a7713b1edbc 8456 #define HRTIM_TIMICR_CMP1C_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8457 #define HRTIM_TIMICR_CMP1C_Msk (0x1U << HRTIM_TIMICR_CMP1C_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8458 #define HRTIM_TIMICR_CMP1C HRTIM_TIMICR_CMP1C_Msk /*!< Slave compare 1 clear flag */
AnnaBridge 171:3a7713b1edbc 8459 #define HRTIM_TIMICR_CMP2C_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8460 #define HRTIM_TIMICR_CMP2C_Msk (0x1U << HRTIM_TIMICR_CMP2C_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8461 #define HRTIM_TIMICR_CMP2C HRTIM_TIMICR_CMP2C_Msk /*!< Slave compare 2 clear flag */
AnnaBridge 171:3a7713b1edbc 8462 #define HRTIM_TIMICR_CMP3C_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8463 #define HRTIM_TIMICR_CMP3C_Msk (0x1U << HRTIM_TIMICR_CMP3C_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8464 #define HRTIM_TIMICR_CMP3C HRTIM_TIMICR_CMP3C_Msk /*!< Slave compare 3 clear flag */
AnnaBridge 171:3a7713b1edbc 8465 #define HRTIM_TIMICR_CMP4C_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8466 #define HRTIM_TIMICR_CMP4C_Msk (0x1U << HRTIM_TIMICR_CMP4C_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8467 #define HRTIM_TIMICR_CMP4C HRTIM_TIMICR_CMP4C_Msk /*!< Slave compare 4 clear flag */
AnnaBridge 171:3a7713b1edbc 8468 #define HRTIM_TIMICR_REPC_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8469 #define HRTIM_TIMICR_REPC_Msk (0x1U << HRTIM_TIMICR_REPC_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8470 #define HRTIM_TIMICR_REPC HRTIM_TIMICR_REPC_Msk /*!< Slave repetition clear flag */
AnnaBridge 171:3a7713b1edbc 8471 #define HRTIM_TIMICR_UPDC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8472 #define HRTIM_TIMICR_UPDC_Msk (0x1U << HRTIM_TIMICR_UPDC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8473 #define HRTIM_TIMICR_UPDC HRTIM_TIMICR_UPDC_Msk /*!< Slave update clear flag */
AnnaBridge 171:3a7713b1edbc 8474 #define HRTIM_TIMICR_CPT1C_Pos (7U)
AnnaBridge 171:3a7713b1edbc 8475 #define HRTIM_TIMICR_CPT1C_Msk (0x1U << HRTIM_TIMICR_CPT1C_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8476 #define HRTIM_TIMICR_CPT1C HRTIM_TIMICR_CPT1C_Msk /*!< Slave capture 1 clear flag */
AnnaBridge 171:3a7713b1edbc 8477 #define HRTIM_TIMICR_CPT2C_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8478 #define HRTIM_TIMICR_CPT2C_Msk (0x1U << HRTIM_TIMICR_CPT2C_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8479 #define HRTIM_TIMICR_CPT2C HRTIM_TIMICR_CPT2C_Msk /*!< Slave capture 2 clear flag */
AnnaBridge 171:3a7713b1edbc 8480 #define HRTIM_TIMICR_SET1C_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8481 #define HRTIM_TIMICR_SET1C_Msk (0x1U << HRTIM_TIMICR_SET1C_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8482 #define HRTIM_TIMICR_SET1C HRTIM_TIMICR_SET1C_Msk /*!< Slave output 1 set clear flag */
AnnaBridge 171:3a7713b1edbc 8483 #define HRTIM_TIMICR_RST1C_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8484 #define HRTIM_TIMICR_RST1C_Msk (0x1U << HRTIM_TIMICR_RST1C_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8485 #define HRTIM_TIMICR_RST1C HRTIM_TIMICR_RST1C_Msk /*!< Slave output 1 reset clear flag */
AnnaBridge 171:3a7713b1edbc 8486 #define HRTIM_TIMICR_SET2C_Pos (11U)
AnnaBridge 171:3a7713b1edbc 8487 #define HRTIM_TIMICR_SET2C_Msk (0x1U << HRTIM_TIMICR_SET2C_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8488 #define HRTIM_TIMICR_SET2C HRTIM_TIMICR_SET2C_Msk /*!< Slave output 2 set clear flag */
AnnaBridge 171:3a7713b1edbc 8489 #define HRTIM_TIMICR_RST2C_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8490 #define HRTIM_TIMICR_RST2C_Msk (0x1U << HRTIM_TIMICR_RST2C_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8491 #define HRTIM_TIMICR_RST2C HRTIM_TIMICR_RST2C_Msk /*!< Slave output 2 reset clear flag */
AnnaBridge 171:3a7713b1edbc 8492 #define HRTIM_TIMICR_RSTC_Pos (13U)
AnnaBridge 171:3a7713b1edbc 8493 #define HRTIM_TIMICR_RSTC_Msk (0x1U << HRTIM_TIMICR_RSTC_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8494 #define HRTIM_TIMICR_RSTC HRTIM_TIMICR_RSTC_Msk /*!< Slave reset clear flag */
AnnaBridge 171:3a7713b1edbc 8495 #define HRTIM_TIMICR_DLYPRT1C_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8496 #define HRTIM_TIMICR_DLYPRT1C_Msk (0x1U << HRTIM_TIMICR_DLYPRT1C_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8497 #define HRTIM_TIMICR_DLYPRT1C HRTIM_TIMICR_DLYPRT1C_Msk /*!< Slave output 1 delay protection clear flag */
AnnaBridge 171:3a7713b1edbc 8498 #define HRTIM_TIMICR_DLYPRT2C_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8499 #define HRTIM_TIMICR_DLYPRT2C_Msk (0x1U << HRTIM_TIMICR_DLYPRT2C_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8500 #define HRTIM_TIMICR_DLYPRT2C HRTIM_TIMICR_DLYPRT2C_Msk /*!< Slave output 2 delay protection clear flag */
AnnaBridge 171:3a7713b1edbc 8501
AnnaBridge 171:3a7713b1edbc 8502 /******************** Slave DMA/Interrupt enable register *********************/
AnnaBridge 171:3a7713b1edbc 8503 #define HRTIM_TIMDIER_CMP1IE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8504 #define HRTIM_TIMDIER_CMP1IE_Msk (0x1U << HRTIM_TIMDIER_CMP1IE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8505 #define HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE_Msk /*!< Slave compare 1 interrupt enable */
AnnaBridge 171:3a7713b1edbc 8506 #define HRTIM_TIMDIER_CMP2IE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8507 #define HRTIM_TIMDIER_CMP2IE_Msk (0x1U << HRTIM_TIMDIER_CMP2IE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8508 #define HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE_Msk /*!< Slave compare 2 interrupt enable */
AnnaBridge 171:3a7713b1edbc 8509 #define HRTIM_TIMDIER_CMP3IE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8510 #define HRTIM_TIMDIER_CMP3IE_Msk (0x1U << HRTIM_TIMDIER_CMP3IE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8511 #define HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE_Msk /*!< Slave compare 3 interrupt enable */
AnnaBridge 171:3a7713b1edbc 8512 #define HRTIM_TIMDIER_CMP4IE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8513 #define HRTIM_TIMDIER_CMP4IE_Msk (0x1U << HRTIM_TIMDIER_CMP4IE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8514 #define HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE_Msk /*!< Slave compare 4 interrupt enable */
AnnaBridge 171:3a7713b1edbc 8515 #define HRTIM_TIMDIER_REPIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8516 #define HRTIM_TIMDIER_REPIE_Msk (0x1U << HRTIM_TIMDIER_REPIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8517 #define HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE_Msk /*!< Slave repetition interrupt enable */
AnnaBridge 171:3a7713b1edbc 8518 #define HRTIM_TIMDIER_UPDIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8519 #define HRTIM_TIMDIER_UPDIE_Msk (0x1U << HRTIM_TIMDIER_UPDIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8520 #define HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE_Msk /*!< Slave update interrupt enable */
AnnaBridge 171:3a7713b1edbc 8521 #define HRTIM_TIMDIER_CPT1IE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 8522 #define HRTIM_TIMDIER_CPT1IE_Msk (0x1U << HRTIM_TIMDIER_CPT1IE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8523 #define HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE_Msk /*!< Slave capture 1 interrupt enable */
AnnaBridge 171:3a7713b1edbc 8524 #define HRTIM_TIMDIER_CPT2IE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8525 #define HRTIM_TIMDIER_CPT2IE_Msk (0x1U << HRTIM_TIMDIER_CPT2IE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8526 #define HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE_Msk /*!< Slave capture 2 interrupt enable */
AnnaBridge 171:3a7713b1edbc 8527 #define HRTIM_TIMDIER_SET1IE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8528 #define HRTIM_TIMDIER_SET1IE_Msk (0x1U << HRTIM_TIMDIER_SET1IE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8529 #define HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE_Msk /*!< Slave output 1 set interrupt enable */
AnnaBridge 171:3a7713b1edbc 8530 #define HRTIM_TIMDIER_RST1IE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8531 #define HRTIM_TIMDIER_RST1IE_Msk (0x1U << HRTIM_TIMDIER_RST1IE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8532 #define HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE_Msk /*!< Slave output 1 reset interrupt enable */
AnnaBridge 171:3a7713b1edbc 8533 #define HRTIM_TIMDIER_SET2IE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 8534 #define HRTIM_TIMDIER_SET2IE_Msk (0x1U << HRTIM_TIMDIER_SET2IE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8535 #define HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE_Msk /*!< Slave output 2 set interrupt enable */
AnnaBridge 171:3a7713b1edbc 8536 #define HRTIM_TIMDIER_RST2IE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8537 #define HRTIM_TIMDIER_RST2IE_Msk (0x1U << HRTIM_TIMDIER_RST2IE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8538 #define HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE_Msk /*!< Slave output 2 reset interrupt enable */
AnnaBridge 171:3a7713b1edbc 8539 #define HRTIM_TIMDIER_RSTIE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 8540 #define HRTIM_TIMDIER_RSTIE_Msk (0x1U << HRTIM_TIMDIER_RSTIE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8541 #define HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE_Msk /*!< Slave reset interrupt enable */
AnnaBridge 171:3a7713b1edbc 8542 #define HRTIM_TIMDIER_DLYPRTIE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8543 #define HRTIM_TIMDIER_DLYPRTIE_Msk (0x1U << HRTIM_TIMDIER_DLYPRTIE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8544 #define HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE_Msk /*!< Slave delay protection interrupt enable */
AnnaBridge 171:3a7713b1edbc 8545
AnnaBridge 171:3a7713b1edbc 8546 #define HRTIM_TIMDIER_CMP1DE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8547 #define HRTIM_TIMDIER_CMP1DE_Msk (0x1U << HRTIM_TIMDIER_CMP1DE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8548 #define HRTIM_TIMDIER_CMP1DE HRTIM_TIMDIER_CMP1DE_Msk /*!< Slave compare 1 request enable */
AnnaBridge 171:3a7713b1edbc 8549 #define HRTIM_TIMDIER_CMP2DE_Pos (17U)
AnnaBridge 171:3a7713b1edbc 8550 #define HRTIM_TIMDIER_CMP2DE_Msk (0x1U << HRTIM_TIMDIER_CMP2DE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8551 #define HRTIM_TIMDIER_CMP2DE HRTIM_TIMDIER_CMP2DE_Msk /*!< Slave compare 2 request enable */
AnnaBridge 171:3a7713b1edbc 8552 #define HRTIM_TIMDIER_CMP3DE_Pos (18U)
AnnaBridge 171:3a7713b1edbc 8553 #define HRTIM_TIMDIER_CMP3DE_Msk (0x1U << HRTIM_TIMDIER_CMP3DE_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8554 #define HRTIM_TIMDIER_CMP3DE HRTIM_TIMDIER_CMP3DE_Msk /*!< Slave compare 3 request enable */
AnnaBridge 171:3a7713b1edbc 8555 #define HRTIM_TIMDIER_CMP4DE_Pos (19U)
AnnaBridge 171:3a7713b1edbc 8556 #define HRTIM_TIMDIER_CMP4DE_Msk (0x1U << HRTIM_TIMDIER_CMP4DE_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8557 #define HRTIM_TIMDIER_CMP4DE HRTIM_TIMDIER_CMP4DE_Msk /*!< Slave compare 4 request enable */
AnnaBridge 171:3a7713b1edbc 8558 #define HRTIM_TIMDIER_REPDE_Pos (20U)
AnnaBridge 171:3a7713b1edbc 8559 #define HRTIM_TIMDIER_REPDE_Msk (0x1U << HRTIM_TIMDIER_REPDE_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8560 #define HRTIM_TIMDIER_REPDE HRTIM_TIMDIER_REPDE_Msk /*!< Slave repetition request enable */
AnnaBridge 171:3a7713b1edbc 8561 #define HRTIM_TIMDIER_UPDDE_Pos (22U)
AnnaBridge 171:3a7713b1edbc 8562 #define HRTIM_TIMDIER_UPDDE_Msk (0x1U << HRTIM_TIMDIER_UPDDE_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8563 #define HRTIM_TIMDIER_UPDDE HRTIM_TIMDIER_UPDDE_Msk /*!< Slave update request enable */
AnnaBridge 171:3a7713b1edbc 8564 #define HRTIM_TIMDIER_CPT1DE_Pos (23U)
AnnaBridge 171:3a7713b1edbc 8565 #define HRTIM_TIMDIER_CPT1DE_Msk (0x1U << HRTIM_TIMDIER_CPT1DE_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 8566 #define HRTIM_TIMDIER_CPT1DE HRTIM_TIMDIER_CPT1DE_Msk /*!< Slave capture 1 request enable */
AnnaBridge 171:3a7713b1edbc 8567 #define HRTIM_TIMDIER_CPT2DE_Pos (24U)
AnnaBridge 171:3a7713b1edbc 8568 #define HRTIM_TIMDIER_CPT2DE_Msk (0x1U << HRTIM_TIMDIER_CPT2DE_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8569 #define HRTIM_TIMDIER_CPT2DE HRTIM_TIMDIER_CPT2DE_Msk /*!< Slave capture 2 request enable */
AnnaBridge 171:3a7713b1edbc 8570 #define HRTIM_TIMDIER_SET1DE_Pos (25U)
AnnaBridge 171:3a7713b1edbc 8571 #define HRTIM_TIMDIER_SET1DE_Msk (0x1U << HRTIM_TIMDIER_SET1DE_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8572 #define HRTIM_TIMDIER_SET1DE HRTIM_TIMDIER_SET1DE_Msk /*!< Slave output 1 set request enable */
AnnaBridge 171:3a7713b1edbc 8573 #define HRTIM_TIMDIER_RST1DE_Pos (26U)
AnnaBridge 171:3a7713b1edbc 8574 #define HRTIM_TIMDIER_RST1DE_Msk (0x1U << HRTIM_TIMDIER_RST1DE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8575 #define HRTIM_TIMDIER_RST1DE HRTIM_TIMDIER_RST1DE_Msk /*!< Slave output 1 reset request enable */
AnnaBridge 171:3a7713b1edbc 8576 #define HRTIM_TIMDIER_SET2DE_Pos (27U)
AnnaBridge 171:3a7713b1edbc 8577 #define HRTIM_TIMDIER_SET2DE_Msk (0x1U << HRTIM_TIMDIER_SET2DE_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 8578 #define HRTIM_TIMDIER_SET2DE HRTIM_TIMDIER_SET2DE_Msk /*!< Slave output 2 set request enable */
AnnaBridge 171:3a7713b1edbc 8579 #define HRTIM_TIMDIER_RST2DE_Pos (28U)
AnnaBridge 171:3a7713b1edbc 8580 #define HRTIM_TIMDIER_RST2DE_Msk (0x1U << HRTIM_TIMDIER_RST2DE_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 8581 #define HRTIM_TIMDIER_RST2DE HRTIM_TIMDIER_RST2DE_Msk /*!< Slave output 2 reset request enable */
AnnaBridge 171:3a7713b1edbc 8582 #define HRTIM_TIMDIER_RSTDE_Pos (29U)
AnnaBridge 171:3a7713b1edbc 8583 #define HRTIM_TIMDIER_RSTDE_Msk (0x1U << HRTIM_TIMDIER_RSTDE_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 8584 #define HRTIM_TIMDIER_RSTDE HRTIM_TIMDIER_RSTDE_Msk /*!< Slave reset request enable */
AnnaBridge 171:3a7713b1edbc 8585 #define HRTIM_TIMDIER_DLYPRTDE_Pos (30U)
AnnaBridge 171:3a7713b1edbc 8586 #define HRTIM_TIMDIER_DLYPRTDE_Msk (0x1U << HRTIM_TIMDIER_DLYPRTDE_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 8587 #define HRTIM_TIMDIER_DLYPRTDE HRTIM_TIMDIER_DLYPRTDE_Msk /*!< Slavedelay protection request enable */
AnnaBridge 171:3a7713b1edbc 8588
AnnaBridge 171:3a7713b1edbc 8589 /****************** Bit definition for HRTIM_CNTR register ****************/
AnnaBridge 171:3a7713b1edbc 8590 #define HRTIM_CNTR_CNTR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8591 #define HRTIM_CNTR_CNTR_Msk (0xFFFFFFFFU << HRTIM_CNTR_CNTR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8592 #define HRTIM_CNTR_CNTR HRTIM_CNTR_CNTR_Msk /*!< Counter Value */
AnnaBridge 171:3a7713b1edbc 8593
AnnaBridge 171:3a7713b1edbc 8594 /******************* Bit definition for HRTIM_PER register *****************/
AnnaBridge 171:3a7713b1edbc 8595 #define HRTIM_PER_PER_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8596 #define HRTIM_PER_PER_Msk (0xFFFFFFFFU << HRTIM_PER_PER_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8597 #define HRTIM_PER_PER HRTIM_PER_PER_Msk /*!< Period Value */
AnnaBridge 171:3a7713b1edbc 8598
AnnaBridge 171:3a7713b1edbc 8599 /******************* Bit definition for HRTIM_REP register *****************/
AnnaBridge 171:3a7713b1edbc 8600 #define HRTIM_REP_REP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8601 #define HRTIM_REP_REP_Msk (0xFFFFFFFFU << HRTIM_REP_REP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8602 #define HRTIM_REP_REP HRTIM_REP_REP_Msk /*!< Repetition Value */
AnnaBridge 171:3a7713b1edbc 8603
AnnaBridge 171:3a7713b1edbc 8604 /******************* Bit definition for HRTIM_CMP1R register *****************/
AnnaBridge 171:3a7713b1edbc 8605 #define HRTIM_CMP1R_CMP1R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8606 #define HRTIM_CMP1R_CMP1R_Msk (0xFFFFFFFFU << HRTIM_CMP1R_CMP1R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8607 #define HRTIM_CMP1R_CMP1R HRTIM_CMP1R_CMP1R_Msk /*!< Compare Value */
AnnaBridge 171:3a7713b1edbc 8608
AnnaBridge 171:3a7713b1edbc 8609 /******************* Bit definition for HRTIM_CMP1CR register *****************/
AnnaBridge 171:3a7713b1edbc 8610 #define HRTIM_CMP1CR_CMP1CR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8611 #define HRTIM_CMP1CR_CMP1CR_Msk (0xFFFFFFFFU << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8612 #define HRTIM_CMP1CR_CMP1CR HRTIM_CMP1CR_CMP1CR_Msk /*!< Compare Value */
AnnaBridge 171:3a7713b1edbc 8613
AnnaBridge 171:3a7713b1edbc 8614 /******************* Bit definition for HRTIM_CMP2R register *****************/
AnnaBridge 171:3a7713b1edbc 8615 #define HRTIM_CMP2R_CMP2R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8616 #define HRTIM_CMP2R_CMP2R_Msk (0xFFFFFFFFU << HRTIM_CMP2R_CMP2R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8617 #define HRTIM_CMP2R_CMP2R HRTIM_CMP2R_CMP2R_Msk /*!< Compare Value */
AnnaBridge 171:3a7713b1edbc 8618
AnnaBridge 171:3a7713b1edbc 8619 /******************* Bit definition for HRTIM_CMP3R register *****************/
AnnaBridge 171:3a7713b1edbc 8620 #define HRTIM_CMP3R_CMP3R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8621 #define HRTIM_CMP3R_CMP3R_Msk (0xFFFFFFFFU << HRTIM_CMP3R_CMP3R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8622 #define HRTIM_CMP3R_CMP3R HRTIM_CMP3R_CMP3R_Msk /*!< Compare Value */
AnnaBridge 171:3a7713b1edbc 8623
AnnaBridge 171:3a7713b1edbc 8624 /******************* Bit definition for HRTIM_CMP4R register *****************/
AnnaBridge 171:3a7713b1edbc 8625 #define HRTIM_CMP4R_CMP4R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8626 #define HRTIM_CMP4R_CMP4R_Msk (0xFFFFFFFFU << HRTIM_CMP4R_CMP4R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8627 #define HRTIM_CMP4R_CMP4R HRTIM_CMP4R_CMP4R_Msk /*!< Compare Value */
AnnaBridge 171:3a7713b1edbc 8628
AnnaBridge 171:3a7713b1edbc 8629 /******************* Bit definition for HRTIM_CPT1R register ****************/
AnnaBridge 171:3a7713b1edbc 8630 #define HRTIM_CPT1R_CPT1R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8631 #define HRTIM_CPT1R_CPT1R_Msk (0xFFFFFFFFU << HRTIM_CPT1R_CPT1R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8632 #define HRTIM_CPT1R_CPT1R HRTIM_CPT1R_CPT1R_Msk /*!< Capture Value */
AnnaBridge 171:3a7713b1edbc 8633
AnnaBridge 171:3a7713b1edbc 8634 /******************* Bit definition for HRTIM_CPT2R register ****************/
AnnaBridge 171:3a7713b1edbc 8635 #define HRTIM_CPT2R_CPT2R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8636 #define HRTIM_CPT2R_CPT2R_Msk (0xFFFFFFFFU << HRTIM_CPT2R_CPT2R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8637 #define HRTIM_CPT2R_CPT2R HRTIM_CPT2R_CPT2R_Msk /*!< Capture Value */
AnnaBridge 171:3a7713b1edbc 8638
AnnaBridge 171:3a7713b1edbc 8639 /******************** Bit definition for Slave Deadtime register **************/
AnnaBridge 171:3a7713b1edbc 8640 #define HRTIM_DTR_DTR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8641 #define HRTIM_DTR_DTR_Msk (0x1FFU << HRTIM_DTR_DTR_Pos) /*!< 0x000001FF */
AnnaBridge 171:3a7713b1edbc 8642 #define HRTIM_DTR_DTR HRTIM_DTR_DTR_Msk /*!< Dead time rising value */
AnnaBridge 171:3a7713b1edbc 8643 #define HRTIM_DTR_DTR_0 (0x001U << HRTIM_DTR_DTR_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8644 #define HRTIM_DTR_DTR_1 (0x002U << HRTIM_DTR_DTR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8645 #define HRTIM_DTR_DTR_2 (0x004U << HRTIM_DTR_DTR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8646 #define HRTIM_DTR_DTR_3 (0x008U << HRTIM_DTR_DTR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8647 #define HRTIM_DTR_DTR_4 (0x010U << HRTIM_DTR_DTR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8648 #define HRTIM_DTR_DTR_5 (0x020U << HRTIM_DTR_DTR_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8649 #define HRTIM_DTR_DTR_6 (0x040U << HRTIM_DTR_DTR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8650 #define HRTIM_DTR_DTR_7 (0x080U << HRTIM_DTR_DTR_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8651 #define HRTIM_DTR_DTR_8 (0x100U << HRTIM_DTR_DTR_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8652 #define HRTIM_DTR_SDTR_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8653 #define HRTIM_DTR_SDTR_Msk (0x1U << HRTIM_DTR_SDTR_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8654 #define HRTIM_DTR_SDTR HRTIM_DTR_SDTR_Msk /*!< Sign dead time rising value */
AnnaBridge 171:3a7713b1edbc 8655 #define HRTIM_DTR_DTPRSC_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8656 #define HRTIM_DTR_DTPRSC_Msk (0x7U << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001C00 */
AnnaBridge 171:3a7713b1edbc 8657 #define HRTIM_DTR_DTPRSC HRTIM_DTR_DTPRSC_Msk /*!< Dead time prescaler */
AnnaBridge 171:3a7713b1edbc 8658 #define HRTIM_DTR_DTPRSC_0 (0x1U << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8659 #define HRTIM_DTR_DTPRSC_1 (0x2U << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8660 #define HRTIM_DTR_DTPRSC_2 (0x4U << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8661 #define HRTIM_DTR_DTRSLK_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8662 #define HRTIM_DTR_DTRSLK_Msk (0x1U << HRTIM_DTR_DTRSLK_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8663 #define HRTIM_DTR_DTRSLK HRTIM_DTR_DTRSLK_Msk /*!< Dead time rising sign lock */
AnnaBridge 171:3a7713b1edbc 8664 #define HRTIM_DTR_DTRLK_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8665 #define HRTIM_DTR_DTRLK_Msk (0x1U << HRTIM_DTR_DTRLK_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8666 #define HRTIM_DTR_DTRLK HRTIM_DTR_DTRLK_Msk /*!< Dead time rising lock */
AnnaBridge 171:3a7713b1edbc 8667 #define HRTIM_DTR_DTF_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8668 #define HRTIM_DTR_DTF_Msk (0x1FFU << HRTIM_DTR_DTF_Pos) /*!< 0x01FF0000 */
AnnaBridge 171:3a7713b1edbc 8669 #define HRTIM_DTR_DTF HRTIM_DTR_DTF_Msk /*!< Dead time falling value */
AnnaBridge 171:3a7713b1edbc 8670 #define HRTIM_DTR_DTF_0 (0x001U << HRTIM_DTR_DTF_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8671 #define HRTIM_DTR_DTF_1 (0x002U << HRTIM_DTR_DTF_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8672 #define HRTIM_DTR_DTF_2 (0x004U << HRTIM_DTR_DTF_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8673 #define HRTIM_DTR_DTF_3 (0x008U << HRTIM_DTR_DTF_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8674 #define HRTIM_DTR_DTF_4 (0x010U << HRTIM_DTR_DTF_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8675 #define HRTIM_DTR_DTF_5 (0x020U << HRTIM_DTR_DTF_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8676 #define HRTIM_DTR_DTF_6 (0x040U << HRTIM_DTR_DTF_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8677 #define HRTIM_DTR_DTF_7 (0x080U << HRTIM_DTR_DTF_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 8678 #define HRTIM_DTR_DTF_8 (0x100U << HRTIM_DTR_DTF_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8679 #define HRTIM_DTR_SDTF_Pos (25U)
AnnaBridge 171:3a7713b1edbc 8680 #define HRTIM_DTR_SDTF_Msk (0x1U << HRTIM_DTR_SDTF_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8681 #define HRTIM_DTR_SDTF HRTIM_DTR_SDTF_Msk /*!< Sign dead time falling value */
AnnaBridge 171:3a7713b1edbc 8682 #define HRTIM_DTR_DTFSLK_Pos (30U)
AnnaBridge 171:3a7713b1edbc 8683 #define HRTIM_DTR_DTFSLK_Msk (0x1U << HRTIM_DTR_DTFSLK_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 8684 #define HRTIM_DTR_DTFSLK HRTIM_DTR_DTFSLK_Msk /*!< Dead time falling sign lock */
AnnaBridge 171:3a7713b1edbc 8685 #define HRTIM_DTR_DTFLK_Pos (31U)
AnnaBridge 171:3a7713b1edbc 8686 #define HRTIM_DTR_DTFLK_Msk (0x1U << HRTIM_DTR_DTFLK_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 8687 #define HRTIM_DTR_DTFLK HRTIM_DTR_DTFLK_Msk /*!< Dead time falling lock */
AnnaBridge 171:3a7713b1edbc 8688
AnnaBridge 171:3a7713b1edbc 8689 /**** Bit definition for Slave Output 1 set register **************************/
AnnaBridge 171:3a7713b1edbc 8690 #define HRTIM_SET1R_SST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8691 #define HRTIM_SET1R_SST_Msk (0x1U << HRTIM_SET1R_SST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8692 #define HRTIM_SET1R_SST HRTIM_SET1R_SST_Msk /*!< software set trigger */
AnnaBridge 171:3a7713b1edbc 8693 #define HRTIM_SET1R_RESYNC_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8694 #define HRTIM_SET1R_RESYNC_Msk (0x1U << HRTIM_SET1R_RESYNC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8695 #define HRTIM_SET1R_RESYNC HRTIM_SET1R_RESYNC_Msk /*!< Timer A resynchronization */
AnnaBridge 171:3a7713b1edbc 8696 #define HRTIM_SET1R_PER_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8697 #define HRTIM_SET1R_PER_Msk (0x1U << HRTIM_SET1R_PER_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8698 #define HRTIM_SET1R_PER HRTIM_SET1R_PER_Msk /*!< Timer A period */
AnnaBridge 171:3a7713b1edbc 8699 #define HRTIM_SET1R_CMP1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8700 #define HRTIM_SET1R_CMP1_Msk (0x1U << HRTIM_SET1R_CMP1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8701 #define HRTIM_SET1R_CMP1 HRTIM_SET1R_CMP1_Msk /*!< Timer A compare 1 */
AnnaBridge 171:3a7713b1edbc 8702 #define HRTIM_SET1R_CMP2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8703 #define HRTIM_SET1R_CMP2_Msk (0x1U << HRTIM_SET1R_CMP2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8704 #define HRTIM_SET1R_CMP2 HRTIM_SET1R_CMP2_Msk /*!< Timer A compare 2 */
AnnaBridge 171:3a7713b1edbc 8705 #define HRTIM_SET1R_CMP3_Pos (5U)
AnnaBridge 171:3a7713b1edbc 8706 #define HRTIM_SET1R_CMP3_Msk (0x1U << HRTIM_SET1R_CMP3_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8707 #define HRTIM_SET1R_CMP3 HRTIM_SET1R_CMP3_Msk /*!< Timer A compare 3 */
AnnaBridge 171:3a7713b1edbc 8708 #define HRTIM_SET1R_CMP4_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8709 #define HRTIM_SET1R_CMP4_Msk (0x1U << HRTIM_SET1R_CMP4_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8710 #define HRTIM_SET1R_CMP4 HRTIM_SET1R_CMP4_Msk /*!< Timer A compare 4 */
AnnaBridge 171:3a7713b1edbc 8711
AnnaBridge 171:3a7713b1edbc 8712 #define HRTIM_SET1R_MSTPER_Pos (7U)
AnnaBridge 171:3a7713b1edbc 8713 #define HRTIM_SET1R_MSTPER_Msk (0x1U << HRTIM_SET1R_MSTPER_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8714 #define HRTIM_SET1R_MSTPER HRTIM_SET1R_MSTPER_Msk /*!< Master period */
AnnaBridge 171:3a7713b1edbc 8715 #define HRTIM_SET1R_MSTCMP1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8716 #define HRTIM_SET1R_MSTCMP1_Msk (0x1U << HRTIM_SET1R_MSTCMP1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8717 #define HRTIM_SET1R_MSTCMP1 HRTIM_SET1R_MSTCMP1_Msk /*!< Master compare 1 */
AnnaBridge 171:3a7713b1edbc 8718 #define HRTIM_SET1R_MSTCMP2_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8719 #define HRTIM_SET1R_MSTCMP2_Msk (0x1U << HRTIM_SET1R_MSTCMP2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8720 #define HRTIM_SET1R_MSTCMP2 HRTIM_SET1R_MSTCMP2_Msk /*!< Master compare 2 */
AnnaBridge 171:3a7713b1edbc 8721 #define HRTIM_SET1R_MSTCMP3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8722 #define HRTIM_SET1R_MSTCMP3_Msk (0x1U << HRTIM_SET1R_MSTCMP3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8723 #define HRTIM_SET1R_MSTCMP3 HRTIM_SET1R_MSTCMP3_Msk /*!< Master compare 3 */
AnnaBridge 171:3a7713b1edbc 8724 #define HRTIM_SET1R_MSTCMP4_Pos (11U)
AnnaBridge 171:3a7713b1edbc 8725 #define HRTIM_SET1R_MSTCMP4_Msk (0x1U << HRTIM_SET1R_MSTCMP4_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8726 #define HRTIM_SET1R_MSTCMP4 HRTIM_SET1R_MSTCMP4_Msk /*!< Master compare 4 */
AnnaBridge 171:3a7713b1edbc 8727
AnnaBridge 171:3a7713b1edbc 8728 #define HRTIM_SET1R_TIMEVNT1_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8729 #define HRTIM_SET1R_TIMEVNT1_Msk (0x1U << HRTIM_SET1R_TIMEVNT1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8730 #define HRTIM_SET1R_TIMEVNT1 HRTIM_SET1R_TIMEVNT1_Msk /*!< Timer event 1 */
AnnaBridge 171:3a7713b1edbc 8731 #define HRTIM_SET1R_TIMEVNT2_Pos (13U)
AnnaBridge 171:3a7713b1edbc 8732 #define HRTIM_SET1R_TIMEVNT2_Msk (0x1U << HRTIM_SET1R_TIMEVNT2_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8733 #define HRTIM_SET1R_TIMEVNT2 HRTIM_SET1R_TIMEVNT2_Msk /*!< Timer event 2 */
AnnaBridge 171:3a7713b1edbc 8734 #define HRTIM_SET1R_TIMEVNT3_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8735 #define HRTIM_SET1R_TIMEVNT3_Msk (0x1U << HRTIM_SET1R_TIMEVNT3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8736 #define HRTIM_SET1R_TIMEVNT3 HRTIM_SET1R_TIMEVNT3_Msk /*!< Timer event 3 */
AnnaBridge 171:3a7713b1edbc 8737 #define HRTIM_SET1R_TIMEVNT4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8738 #define HRTIM_SET1R_TIMEVNT4_Msk (0x1U << HRTIM_SET1R_TIMEVNT4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8739 #define HRTIM_SET1R_TIMEVNT4 HRTIM_SET1R_TIMEVNT4_Msk /*!< Timer event 4 */
AnnaBridge 171:3a7713b1edbc 8740 #define HRTIM_SET1R_TIMEVNT5_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8741 #define HRTIM_SET1R_TIMEVNT5_Msk (0x1U << HRTIM_SET1R_TIMEVNT5_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8742 #define HRTIM_SET1R_TIMEVNT5 HRTIM_SET1R_TIMEVNT5_Msk /*!< Timer event 5 */
AnnaBridge 171:3a7713b1edbc 8743 #define HRTIM_SET1R_TIMEVNT6_Pos (17U)
AnnaBridge 171:3a7713b1edbc 8744 #define HRTIM_SET1R_TIMEVNT6_Msk (0x1U << HRTIM_SET1R_TIMEVNT6_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8745 #define HRTIM_SET1R_TIMEVNT6 HRTIM_SET1R_TIMEVNT6_Msk /*!< Timer event 6 */
AnnaBridge 171:3a7713b1edbc 8746 #define HRTIM_SET1R_TIMEVNT7_Pos (18U)
AnnaBridge 171:3a7713b1edbc 8747 #define HRTIM_SET1R_TIMEVNT7_Msk (0x1U << HRTIM_SET1R_TIMEVNT7_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8748 #define HRTIM_SET1R_TIMEVNT7 HRTIM_SET1R_TIMEVNT7_Msk /*!< Timer event 7 */
AnnaBridge 171:3a7713b1edbc 8749 #define HRTIM_SET1R_TIMEVNT8_Pos (19U)
AnnaBridge 171:3a7713b1edbc 8750 #define HRTIM_SET1R_TIMEVNT8_Msk (0x1U << HRTIM_SET1R_TIMEVNT8_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8751 #define HRTIM_SET1R_TIMEVNT8 HRTIM_SET1R_TIMEVNT8_Msk /*!< Timer event 8 */
AnnaBridge 171:3a7713b1edbc 8752 #define HRTIM_SET1R_TIMEVNT9_Pos (20U)
AnnaBridge 171:3a7713b1edbc 8753 #define HRTIM_SET1R_TIMEVNT9_Msk (0x1U << HRTIM_SET1R_TIMEVNT9_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8754 #define HRTIM_SET1R_TIMEVNT9 HRTIM_SET1R_TIMEVNT9_Msk /*!< Timer event 9 */
AnnaBridge 171:3a7713b1edbc 8755
AnnaBridge 171:3a7713b1edbc 8756 #define HRTIM_SET1R_EXTVNT1_Pos (21U)
AnnaBridge 171:3a7713b1edbc 8757 #define HRTIM_SET1R_EXTVNT1_Msk (0x1U << HRTIM_SET1R_EXTVNT1_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8758 #define HRTIM_SET1R_EXTVNT1 HRTIM_SET1R_EXTVNT1_Msk /*!< External event 1 */
AnnaBridge 171:3a7713b1edbc 8759 #define HRTIM_SET1R_EXTVNT2_Pos (22U)
AnnaBridge 171:3a7713b1edbc 8760 #define HRTIM_SET1R_EXTVNT2_Msk (0x1U << HRTIM_SET1R_EXTVNT2_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8761 #define HRTIM_SET1R_EXTVNT2 HRTIM_SET1R_EXTVNT2_Msk /*!< External event 2 */
AnnaBridge 171:3a7713b1edbc 8762 #define HRTIM_SET1R_EXTVNT3_Pos (23U)
AnnaBridge 171:3a7713b1edbc 8763 #define HRTIM_SET1R_EXTVNT3_Msk (0x1U << HRTIM_SET1R_EXTVNT3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 8764 #define HRTIM_SET1R_EXTVNT3 HRTIM_SET1R_EXTVNT3_Msk /*!< External event 3 */
AnnaBridge 171:3a7713b1edbc 8765 #define HRTIM_SET1R_EXTVNT4_Pos (24U)
AnnaBridge 171:3a7713b1edbc 8766 #define HRTIM_SET1R_EXTVNT4_Msk (0x1U << HRTIM_SET1R_EXTVNT4_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8767 #define HRTIM_SET1R_EXTVNT4 HRTIM_SET1R_EXTVNT4_Msk /*!< External event 4 */
AnnaBridge 171:3a7713b1edbc 8768 #define HRTIM_SET1R_EXTVNT5_Pos (25U)
AnnaBridge 171:3a7713b1edbc 8769 #define HRTIM_SET1R_EXTVNT5_Msk (0x1U << HRTIM_SET1R_EXTVNT5_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8770 #define HRTIM_SET1R_EXTVNT5 HRTIM_SET1R_EXTVNT5_Msk /*!< External event 5 */
AnnaBridge 171:3a7713b1edbc 8771 #define HRTIM_SET1R_EXTVNT6_Pos (26U)
AnnaBridge 171:3a7713b1edbc 8772 #define HRTIM_SET1R_EXTVNT6_Msk (0x1U << HRTIM_SET1R_EXTVNT6_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8773 #define HRTIM_SET1R_EXTVNT6 HRTIM_SET1R_EXTVNT6_Msk /*!< External event 6 */
AnnaBridge 171:3a7713b1edbc 8774 #define HRTIM_SET1R_EXTVNT7_Pos (27U)
AnnaBridge 171:3a7713b1edbc 8775 #define HRTIM_SET1R_EXTVNT7_Msk (0x1U << HRTIM_SET1R_EXTVNT7_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 8776 #define HRTIM_SET1R_EXTVNT7 HRTIM_SET1R_EXTVNT7_Msk /*!< External event 7 */
AnnaBridge 171:3a7713b1edbc 8777 #define HRTIM_SET1R_EXTVNT8_Pos (28U)
AnnaBridge 171:3a7713b1edbc 8778 #define HRTIM_SET1R_EXTVNT8_Msk (0x1U << HRTIM_SET1R_EXTVNT8_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 8779 #define HRTIM_SET1R_EXTVNT8 HRTIM_SET1R_EXTVNT8_Msk /*!< External event 8 */
AnnaBridge 171:3a7713b1edbc 8780 #define HRTIM_SET1R_EXTVNT9_Pos (29U)
AnnaBridge 171:3a7713b1edbc 8781 #define HRTIM_SET1R_EXTVNT9_Msk (0x1U << HRTIM_SET1R_EXTVNT9_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 8782 #define HRTIM_SET1R_EXTVNT9 HRTIM_SET1R_EXTVNT9_Msk /*!< External event 9 */
AnnaBridge 171:3a7713b1edbc 8783 #define HRTIM_SET1R_EXTVNT10_Pos (30U)
AnnaBridge 171:3a7713b1edbc 8784 #define HRTIM_SET1R_EXTVNT10_Msk (0x1U << HRTIM_SET1R_EXTVNT10_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 8785 #define HRTIM_SET1R_EXTVNT10 HRTIM_SET1R_EXTVNT10_Msk /*!< External event 10 */
AnnaBridge 171:3a7713b1edbc 8786
AnnaBridge 171:3a7713b1edbc 8787 #define HRTIM_SET1R_UPDATE_Pos (31U)
AnnaBridge 171:3a7713b1edbc 8788 #define HRTIM_SET1R_UPDATE_Msk (0x1U << HRTIM_SET1R_UPDATE_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 8789 #define HRTIM_SET1R_UPDATE HRTIM_SET1R_UPDATE_Msk /*!< Register update (transfer preload to active) */
AnnaBridge 171:3a7713b1edbc 8790
AnnaBridge 171:3a7713b1edbc 8791 /**** Bit definition for Slave Output 1 reset register ************************/
AnnaBridge 171:3a7713b1edbc 8792 #define HRTIM_RST1R_SRT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8793 #define HRTIM_RST1R_SRT_Msk (0x1U << HRTIM_RST1R_SRT_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8794 #define HRTIM_RST1R_SRT HRTIM_RST1R_SRT_Msk /*!< software reset trigger */
AnnaBridge 171:3a7713b1edbc 8795 #define HRTIM_RST1R_RESYNC_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8796 #define HRTIM_RST1R_RESYNC_Msk (0x1U << HRTIM_RST1R_RESYNC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8797 #define HRTIM_RST1R_RESYNC HRTIM_RST1R_RESYNC_Msk /*!< Timer A resynchronization */
AnnaBridge 171:3a7713b1edbc 8798 #define HRTIM_RST1R_PER_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8799 #define HRTIM_RST1R_PER_Msk (0x1U << HRTIM_RST1R_PER_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8800 #define HRTIM_RST1R_PER HRTIM_RST1R_PER_Msk /*!< Timer A period */
AnnaBridge 171:3a7713b1edbc 8801 #define HRTIM_RST1R_CMP1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8802 #define HRTIM_RST1R_CMP1_Msk (0x1U << HRTIM_RST1R_CMP1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8803 #define HRTIM_RST1R_CMP1 HRTIM_RST1R_CMP1_Msk /*!< Timer A compare 1 */
AnnaBridge 171:3a7713b1edbc 8804 #define HRTIM_RST1R_CMP2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8805 #define HRTIM_RST1R_CMP2_Msk (0x1U << HRTIM_RST1R_CMP2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8806 #define HRTIM_RST1R_CMP2 HRTIM_RST1R_CMP2_Msk /*!< Timer A compare 2 */
AnnaBridge 171:3a7713b1edbc 8807 #define HRTIM_RST1R_CMP3_Pos (5U)
AnnaBridge 171:3a7713b1edbc 8808 #define HRTIM_RST1R_CMP3_Msk (0x1U << HRTIM_RST1R_CMP3_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8809 #define HRTIM_RST1R_CMP3 HRTIM_RST1R_CMP3_Msk /*!< Timer A compare 3 */
AnnaBridge 171:3a7713b1edbc 8810 #define HRTIM_RST1R_CMP4_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8811 #define HRTIM_RST1R_CMP4_Msk (0x1U << HRTIM_RST1R_CMP4_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8812 #define HRTIM_RST1R_CMP4 HRTIM_RST1R_CMP4_Msk /*!< Timer A compare 4 */
AnnaBridge 171:3a7713b1edbc 8813
AnnaBridge 171:3a7713b1edbc 8814 #define HRTIM_RST1R_MSTPER_Pos (7U)
AnnaBridge 171:3a7713b1edbc 8815 #define HRTIM_RST1R_MSTPER_Msk (0x1U << HRTIM_RST1R_MSTPER_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8816 #define HRTIM_RST1R_MSTPER HRTIM_RST1R_MSTPER_Msk /*!< Master period */
AnnaBridge 171:3a7713b1edbc 8817 #define HRTIM_RST1R_MSTCMP1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8818 #define HRTIM_RST1R_MSTCMP1_Msk (0x1U << HRTIM_RST1R_MSTCMP1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8819 #define HRTIM_RST1R_MSTCMP1 HRTIM_RST1R_MSTCMP1_Msk /*!< Master compare 1 */
AnnaBridge 171:3a7713b1edbc 8820 #define HRTIM_RST1R_MSTCMP2_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8821 #define HRTIM_RST1R_MSTCMP2_Msk (0x1U << HRTIM_RST1R_MSTCMP2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8822 #define HRTIM_RST1R_MSTCMP2 HRTIM_RST1R_MSTCMP2_Msk /*!< Master compare 2 */
AnnaBridge 171:3a7713b1edbc 8823 #define HRTIM_RST1R_MSTCMP3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8824 #define HRTIM_RST1R_MSTCMP3_Msk (0x1U << HRTIM_RST1R_MSTCMP3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8825 #define HRTIM_RST1R_MSTCMP3 HRTIM_RST1R_MSTCMP3_Msk /*!< Master compare 3 */
AnnaBridge 171:3a7713b1edbc 8826 #define HRTIM_RST1R_MSTCMP4_Pos (11U)
AnnaBridge 171:3a7713b1edbc 8827 #define HRTIM_RST1R_MSTCMP4_Msk (0x1U << HRTIM_RST1R_MSTCMP4_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8828 #define HRTIM_RST1R_MSTCMP4 HRTIM_RST1R_MSTCMP4_Msk /*!< Master compare 4 */
AnnaBridge 171:3a7713b1edbc 8829
AnnaBridge 171:3a7713b1edbc 8830 #define HRTIM_RST1R_TIMEVNT1_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8831 #define HRTIM_RST1R_TIMEVNT1_Msk (0x1U << HRTIM_RST1R_TIMEVNT1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8832 #define HRTIM_RST1R_TIMEVNT1 HRTIM_RST1R_TIMEVNT1_Msk /*!< Timer event 1 */
AnnaBridge 171:3a7713b1edbc 8833 #define HRTIM_RST1R_TIMEVNT2_Pos (13U)
AnnaBridge 171:3a7713b1edbc 8834 #define HRTIM_RST1R_TIMEVNT2_Msk (0x1U << HRTIM_RST1R_TIMEVNT2_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8835 #define HRTIM_RST1R_TIMEVNT2 HRTIM_RST1R_TIMEVNT2_Msk /*!< Timer event 2 */
AnnaBridge 171:3a7713b1edbc 8836 #define HRTIM_RST1R_TIMEVNT3_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8837 #define HRTIM_RST1R_TIMEVNT3_Msk (0x1U << HRTIM_RST1R_TIMEVNT3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8838 #define HRTIM_RST1R_TIMEVNT3 HRTIM_RST1R_TIMEVNT3_Msk /*!< Timer event 3 */
AnnaBridge 171:3a7713b1edbc 8839 #define HRTIM_RST1R_TIMEVNT4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8840 #define HRTIM_RST1R_TIMEVNT4_Msk (0x1U << HRTIM_RST1R_TIMEVNT4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8841 #define HRTIM_RST1R_TIMEVNT4 HRTIM_RST1R_TIMEVNT4_Msk /*!< Timer event 4 */
AnnaBridge 171:3a7713b1edbc 8842 #define HRTIM_RST1R_TIMEVNT5_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8843 #define HRTIM_RST1R_TIMEVNT5_Msk (0x1U << HRTIM_RST1R_TIMEVNT5_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8844 #define HRTIM_RST1R_TIMEVNT5 HRTIM_RST1R_TIMEVNT5_Msk /*!< Timer event 5 */
AnnaBridge 171:3a7713b1edbc 8845 #define HRTIM_RST1R_TIMEVNT6_Pos (17U)
AnnaBridge 171:3a7713b1edbc 8846 #define HRTIM_RST1R_TIMEVNT6_Msk (0x1U << HRTIM_RST1R_TIMEVNT6_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8847 #define HRTIM_RST1R_TIMEVNT6 HRTIM_RST1R_TIMEVNT6_Msk /*!< Timer event 6 */
AnnaBridge 171:3a7713b1edbc 8848 #define HRTIM_RST1R_TIMEVNT7_Pos (18U)
AnnaBridge 171:3a7713b1edbc 8849 #define HRTIM_RST1R_TIMEVNT7_Msk (0x1U << HRTIM_RST1R_TIMEVNT7_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8850 #define HRTIM_RST1R_TIMEVNT7 HRTIM_RST1R_TIMEVNT7_Msk /*!< Timer event 7 */
AnnaBridge 171:3a7713b1edbc 8851 #define HRTIM_RST1R_TIMEVNT8_Pos (19U)
AnnaBridge 171:3a7713b1edbc 8852 #define HRTIM_RST1R_TIMEVNT8_Msk (0x1U << HRTIM_RST1R_TIMEVNT8_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8853 #define HRTIM_RST1R_TIMEVNT8 HRTIM_RST1R_TIMEVNT8_Msk /*!< Timer event 8 */
AnnaBridge 171:3a7713b1edbc 8854 #define HRTIM_RST1R_TIMEVNT9_Pos (20U)
AnnaBridge 171:3a7713b1edbc 8855 #define HRTIM_RST1R_TIMEVNT9_Msk (0x1U << HRTIM_RST1R_TIMEVNT9_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8856 #define HRTIM_RST1R_TIMEVNT9 HRTIM_RST1R_TIMEVNT9_Msk /*!< Timer event 9 */
AnnaBridge 171:3a7713b1edbc 8857
AnnaBridge 171:3a7713b1edbc 8858 #define HRTIM_RST1R_EXTVNT1_Pos (21U)
AnnaBridge 171:3a7713b1edbc 8859 #define HRTIM_RST1R_EXTVNT1_Msk (0x1U << HRTIM_RST1R_EXTVNT1_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8860 #define HRTIM_RST1R_EXTVNT1 HRTIM_RST1R_EXTVNT1_Msk /*!< External event 1 */
AnnaBridge 171:3a7713b1edbc 8861 #define HRTIM_RST1R_EXTVNT2_Pos (22U)
AnnaBridge 171:3a7713b1edbc 8862 #define HRTIM_RST1R_EXTVNT2_Msk (0x1U << HRTIM_RST1R_EXTVNT2_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8863 #define HRTIM_RST1R_EXTVNT2 HRTIM_RST1R_EXTVNT2_Msk /*!< External event 2 */
AnnaBridge 171:3a7713b1edbc 8864 #define HRTIM_RST1R_EXTVNT3_Pos (23U)
AnnaBridge 171:3a7713b1edbc 8865 #define HRTIM_RST1R_EXTVNT3_Msk (0x1U << HRTIM_RST1R_EXTVNT3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 8866 #define HRTIM_RST1R_EXTVNT3 HRTIM_RST1R_EXTVNT3_Msk /*!< External event 3 */
AnnaBridge 171:3a7713b1edbc 8867 #define HRTIM_RST1R_EXTVNT4_Pos (24U)
AnnaBridge 171:3a7713b1edbc 8868 #define HRTIM_RST1R_EXTVNT4_Msk (0x1U << HRTIM_RST1R_EXTVNT4_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8869 #define HRTIM_RST1R_EXTVNT4 HRTIM_RST1R_EXTVNT4_Msk /*!< External event 4 */
AnnaBridge 171:3a7713b1edbc 8870 #define HRTIM_RST1R_EXTVNT5_Pos (25U)
AnnaBridge 171:3a7713b1edbc 8871 #define HRTIM_RST1R_EXTVNT5_Msk (0x1U << HRTIM_RST1R_EXTVNT5_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8872 #define HRTIM_RST1R_EXTVNT5 HRTIM_RST1R_EXTVNT5_Msk /*!< External event 5 */
AnnaBridge 171:3a7713b1edbc 8873 #define HRTIM_RST1R_EXTVNT6_Pos (26U)
AnnaBridge 171:3a7713b1edbc 8874 #define HRTIM_RST1R_EXTVNT6_Msk (0x1U << HRTIM_RST1R_EXTVNT6_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8875 #define HRTIM_RST1R_EXTVNT6 HRTIM_RST1R_EXTVNT6_Msk /*!< External event 6 */
AnnaBridge 171:3a7713b1edbc 8876 #define HRTIM_RST1R_EXTVNT7_Pos (27U)
AnnaBridge 171:3a7713b1edbc 8877 #define HRTIM_RST1R_EXTVNT7_Msk (0x1U << HRTIM_RST1R_EXTVNT7_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 8878 #define HRTIM_RST1R_EXTVNT7 HRTIM_RST1R_EXTVNT7_Msk /*!< External event 7 */
AnnaBridge 171:3a7713b1edbc 8879 #define HRTIM_RST1R_EXTVNT8_Pos (28U)
AnnaBridge 171:3a7713b1edbc 8880 #define HRTIM_RST1R_EXTVNT8_Msk (0x1U << HRTIM_RST1R_EXTVNT8_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 8881 #define HRTIM_RST1R_EXTVNT8 HRTIM_RST1R_EXTVNT8_Msk /*!< External event 8 */
AnnaBridge 171:3a7713b1edbc 8882 #define HRTIM_RST1R_EXTVNT9_Pos (29U)
AnnaBridge 171:3a7713b1edbc 8883 #define HRTIM_RST1R_EXTVNT9_Msk (0x1U << HRTIM_RST1R_EXTVNT9_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 8884 #define HRTIM_RST1R_EXTVNT9 HRTIM_RST1R_EXTVNT9_Msk /*!< External event 9 */
AnnaBridge 171:3a7713b1edbc 8885 #define HRTIM_RST1R_EXTVNT10_Pos (30U)
AnnaBridge 171:3a7713b1edbc 8886 #define HRTIM_RST1R_EXTVNT10_Msk (0x1U << HRTIM_RST1R_EXTVNT10_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 8887 #define HRTIM_RST1R_EXTVNT10 HRTIM_RST1R_EXTVNT10_Msk /*!< External event 10 */
AnnaBridge 171:3a7713b1edbc 8888
AnnaBridge 171:3a7713b1edbc 8889 #define HRTIM_RST1R_UPDATE_Pos (31U)
AnnaBridge 171:3a7713b1edbc 8890 #define HRTIM_RST1R_UPDATE_Msk (0x1U << HRTIM_RST1R_UPDATE_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 8891 #define HRTIM_RST1R_UPDATE HRTIM_RST1R_UPDATE_Msk /*!< Register update (transfer preload to active) */
AnnaBridge 171:3a7713b1edbc 8892
AnnaBridge 171:3a7713b1edbc 8893
AnnaBridge 171:3a7713b1edbc 8894 /**** Bit definition for Slave Output 2 set register **************************/
AnnaBridge 171:3a7713b1edbc 8895 #define HRTIM_SET2R_SST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8896 #define HRTIM_SET2R_SST_Msk (0x1U << HRTIM_SET2R_SST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8897 #define HRTIM_SET2R_SST HRTIM_SET2R_SST_Msk /*!< software set trigger */
AnnaBridge 171:3a7713b1edbc 8898 #define HRTIM_SET2R_RESYNC_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8899 #define HRTIM_SET2R_RESYNC_Msk (0x1U << HRTIM_SET2R_RESYNC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8900 #define HRTIM_SET2R_RESYNC HRTIM_SET2R_RESYNC_Msk /*!< Timer A resynchronization */
AnnaBridge 171:3a7713b1edbc 8901 #define HRTIM_SET2R_PER_Pos (2U)
AnnaBridge 171:3a7713b1edbc 8902 #define HRTIM_SET2R_PER_Msk (0x1U << HRTIM_SET2R_PER_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8903 #define HRTIM_SET2R_PER HRTIM_SET2R_PER_Msk /*!< Timer A period */
AnnaBridge 171:3a7713b1edbc 8904 #define HRTIM_SET2R_CMP1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 8905 #define HRTIM_SET2R_CMP1_Msk (0x1U << HRTIM_SET2R_CMP1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8906 #define HRTIM_SET2R_CMP1 HRTIM_SET2R_CMP1_Msk /*!< Timer A compare 1 */
AnnaBridge 171:3a7713b1edbc 8907 #define HRTIM_SET2R_CMP2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 8908 #define HRTIM_SET2R_CMP2_Msk (0x1U << HRTIM_SET2R_CMP2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8909 #define HRTIM_SET2R_CMP2 HRTIM_SET2R_CMP2_Msk /*!< Timer A compare 2 */
AnnaBridge 171:3a7713b1edbc 8910 #define HRTIM_SET2R_CMP3_Pos (5U)
AnnaBridge 171:3a7713b1edbc 8911 #define HRTIM_SET2R_CMP3_Msk (0x1U << HRTIM_SET2R_CMP3_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8912 #define HRTIM_SET2R_CMP3 HRTIM_SET2R_CMP3_Msk /*!< Timer A compare 3 */
AnnaBridge 171:3a7713b1edbc 8913 #define HRTIM_SET2R_CMP4_Pos (6U)
AnnaBridge 171:3a7713b1edbc 8914 #define HRTIM_SET2R_CMP4_Msk (0x1U << HRTIM_SET2R_CMP4_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8915 #define HRTIM_SET2R_CMP4 HRTIM_SET2R_CMP4_Msk /*!< Timer A compare 4 */
AnnaBridge 171:3a7713b1edbc 8916
AnnaBridge 171:3a7713b1edbc 8917 #define HRTIM_SET2R_MSTPER_Pos (7U)
AnnaBridge 171:3a7713b1edbc 8918 #define HRTIM_SET2R_MSTPER_Msk (0x1U << HRTIM_SET2R_MSTPER_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8919 #define HRTIM_SET2R_MSTPER HRTIM_SET2R_MSTPER_Msk /*!< Master period */
AnnaBridge 171:3a7713b1edbc 8920 #define HRTIM_SET2R_MSTCMP1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8921 #define HRTIM_SET2R_MSTCMP1_Msk (0x1U << HRTIM_SET2R_MSTCMP1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8922 #define HRTIM_SET2R_MSTCMP1 HRTIM_SET2R_MSTCMP1_Msk /*!< Master compare 1 */
AnnaBridge 171:3a7713b1edbc 8923 #define HRTIM_SET2R_MSTCMP2_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8924 #define HRTIM_SET2R_MSTCMP2_Msk (0x1U << HRTIM_SET2R_MSTCMP2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8925 #define HRTIM_SET2R_MSTCMP2 HRTIM_SET2R_MSTCMP2_Msk /*!< Master compare 2 */
AnnaBridge 171:3a7713b1edbc 8926 #define HRTIM_SET2R_MSTCMP3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8927 #define HRTIM_SET2R_MSTCMP3_Msk (0x1U << HRTIM_SET2R_MSTCMP3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8928 #define HRTIM_SET2R_MSTCMP3 HRTIM_SET2R_MSTCMP3_Msk /*!< Master compare 3 */
AnnaBridge 171:3a7713b1edbc 8929 #define HRTIM_SET2R_MSTCMP4_Pos (11U)
AnnaBridge 171:3a7713b1edbc 8930 #define HRTIM_SET2R_MSTCMP4_Msk (0x1U << HRTIM_SET2R_MSTCMP4_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8931 #define HRTIM_SET2R_MSTCMP4 HRTIM_SET2R_MSTCMP4_Msk /*!< Master compare 4 */
AnnaBridge 171:3a7713b1edbc 8932
AnnaBridge 171:3a7713b1edbc 8933 #define HRTIM_SET2R_TIMEVNT1_Pos (12U)
AnnaBridge 171:3a7713b1edbc 8934 #define HRTIM_SET2R_TIMEVNT1_Msk (0x1U << HRTIM_SET2R_TIMEVNT1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8935 #define HRTIM_SET2R_TIMEVNT1 HRTIM_SET2R_TIMEVNT1_Msk /*!< Timer event 1 */
AnnaBridge 171:3a7713b1edbc 8936 #define HRTIM_SET2R_TIMEVNT2_Pos (13U)
AnnaBridge 171:3a7713b1edbc 8937 #define HRTIM_SET2R_TIMEVNT2_Msk (0x1U << HRTIM_SET2R_TIMEVNT2_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8938 #define HRTIM_SET2R_TIMEVNT2 HRTIM_SET2R_TIMEVNT2_Msk /*!< Timer event 2 */
AnnaBridge 171:3a7713b1edbc 8939 #define HRTIM_SET2R_TIMEVNT3_Pos (14U)
AnnaBridge 171:3a7713b1edbc 8940 #define HRTIM_SET2R_TIMEVNT3_Msk (0x1U << HRTIM_SET2R_TIMEVNT3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8941 #define HRTIM_SET2R_TIMEVNT3 HRTIM_SET2R_TIMEVNT3_Msk /*!< Timer event 3 */
AnnaBridge 171:3a7713b1edbc 8942 #define HRTIM_SET2R_TIMEVNT4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8943 #define HRTIM_SET2R_TIMEVNT4_Msk (0x1U << HRTIM_SET2R_TIMEVNT4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8944 #define HRTIM_SET2R_TIMEVNT4 HRTIM_SET2R_TIMEVNT4_Msk /*!< Timer event 4 */
AnnaBridge 171:3a7713b1edbc 8945 #define HRTIM_SET2R_TIMEVNT5_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8946 #define HRTIM_SET2R_TIMEVNT5_Msk (0x1U << HRTIM_SET2R_TIMEVNT5_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8947 #define HRTIM_SET2R_TIMEVNT5 HRTIM_SET2R_TIMEVNT5_Msk /*!< Timer event 5 */
AnnaBridge 171:3a7713b1edbc 8948 #define HRTIM_SET2R_TIMEVNT6_Pos (17U)
AnnaBridge 171:3a7713b1edbc 8949 #define HRTIM_SET2R_TIMEVNT6_Msk (0x1U << HRTIM_SET2R_TIMEVNT6_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8950 #define HRTIM_SET2R_TIMEVNT6 HRTIM_SET2R_TIMEVNT6_Msk /*!< Timer event 6 */
AnnaBridge 171:3a7713b1edbc 8951 #define HRTIM_SET2R_TIMEVNT7_Pos (18U)
AnnaBridge 171:3a7713b1edbc 8952 #define HRTIM_SET2R_TIMEVNT7_Msk (0x1U << HRTIM_SET2R_TIMEVNT7_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8953 #define HRTIM_SET2R_TIMEVNT7 HRTIM_SET2R_TIMEVNT7_Msk /*!< Timer event 7 */
AnnaBridge 171:3a7713b1edbc 8954 #define HRTIM_SET2R_TIMEVNT8_Pos (19U)
AnnaBridge 171:3a7713b1edbc 8955 #define HRTIM_SET2R_TIMEVNT8_Msk (0x1U << HRTIM_SET2R_TIMEVNT8_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8956 #define HRTIM_SET2R_TIMEVNT8 HRTIM_SET2R_TIMEVNT8_Msk /*!< Timer event 8 */
AnnaBridge 171:3a7713b1edbc 8957 #define HRTIM_SET2R_TIMEVNT9_Pos (20U)
AnnaBridge 171:3a7713b1edbc 8958 #define HRTIM_SET2R_TIMEVNT9_Msk (0x1U << HRTIM_SET2R_TIMEVNT9_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8959 #define HRTIM_SET2R_TIMEVNT9 HRTIM_SET2R_TIMEVNT9_Msk /*!< Timer event 9 */
AnnaBridge 171:3a7713b1edbc 8960
AnnaBridge 171:3a7713b1edbc 8961 #define HRTIM_SET2R_EXTVNT1_Pos (21U)
AnnaBridge 171:3a7713b1edbc 8962 #define HRTIM_SET2R_EXTVNT1_Msk (0x1U << HRTIM_SET2R_EXTVNT1_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8963 #define HRTIM_SET2R_EXTVNT1 HRTIM_SET2R_EXTVNT1_Msk /*!< External event 1 */
AnnaBridge 171:3a7713b1edbc 8964 #define HRTIM_SET2R_EXTVNT2_Pos (22U)
AnnaBridge 171:3a7713b1edbc 8965 #define HRTIM_SET2R_EXTVNT2_Msk (0x1U << HRTIM_SET2R_EXTVNT2_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8966 #define HRTIM_SET2R_EXTVNT2 HRTIM_SET2R_EXTVNT2_Msk /*!< External event 2 */
AnnaBridge 171:3a7713b1edbc 8967 #define HRTIM_SET2R_EXTVNT3_Pos (23U)
AnnaBridge 171:3a7713b1edbc 8968 #define HRTIM_SET2R_EXTVNT3_Msk (0x1U << HRTIM_SET2R_EXTVNT3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 8969 #define HRTIM_SET2R_EXTVNT3 HRTIM_SET2R_EXTVNT3_Msk /*!< External event 3 */
AnnaBridge 171:3a7713b1edbc 8970 #define HRTIM_SET2R_EXTVNT4_Pos (24U)
AnnaBridge 171:3a7713b1edbc 8971 #define HRTIM_SET2R_EXTVNT4_Msk (0x1U << HRTIM_SET2R_EXTVNT4_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8972 #define HRTIM_SET2R_EXTVNT4 HRTIM_SET2R_EXTVNT4_Msk /*!< External event 4 */
AnnaBridge 171:3a7713b1edbc 8973 #define HRTIM_SET2R_EXTVNT5_Pos (25U)
AnnaBridge 171:3a7713b1edbc 8974 #define HRTIM_SET2R_EXTVNT5_Msk (0x1U << HRTIM_SET2R_EXTVNT5_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8975 #define HRTIM_SET2R_EXTVNT5 HRTIM_SET2R_EXTVNT5_Msk /*!< External event 5 */
AnnaBridge 171:3a7713b1edbc 8976 #define HRTIM_SET2R_EXTVNT6_Pos (26U)
AnnaBridge 171:3a7713b1edbc 8977 #define HRTIM_SET2R_EXTVNT6_Msk (0x1U << HRTIM_SET2R_EXTVNT6_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8978 #define HRTIM_SET2R_EXTVNT6 HRTIM_SET2R_EXTVNT6_Msk /*!< External event 6 */
AnnaBridge 171:3a7713b1edbc 8979 #define HRTIM_SET2R_EXTVNT7_Pos (27U)
AnnaBridge 171:3a7713b1edbc 8980 #define HRTIM_SET2R_EXTVNT7_Msk (0x1U << HRTIM_SET2R_EXTVNT7_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 8981 #define HRTIM_SET2R_EXTVNT7 HRTIM_SET2R_EXTVNT7_Msk /*!< External event 7 */
AnnaBridge 171:3a7713b1edbc 8982 #define HRTIM_SET2R_EXTVNT8_Pos (28U)
AnnaBridge 171:3a7713b1edbc 8983 #define HRTIM_SET2R_EXTVNT8_Msk (0x1U << HRTIM_SET2R_EXTVNT8_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 8984 #define HRTIM_SET2R_EXTVNT8 HRTIM_SET2R_EXTVNT8_Msk /*!< External event 8 */
AnnaBridge 171:3a7713b1edbc 8985 #define HRTIM_SET2R_EXTVNT9_Pos (29U)
AnnaBridge 171:3a7713b1edbc 8986 #define HRTIM_SET2R_EXTVNT9_Msk (0x1U << HRTIM_SET2R_EXTVNT9_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 8987 #define HRTIM_SET2R_EXTVNT9 HRTIM_SET2R_EXTVNT9_Msk /*!< External event 9 */
AnnaBridge 171:3a7713b1edbc 8988 #define HRTIM_SET2R_EXTVNT10_Pos (30U)
AnnaBridge 171:3a7713b1edbc 8989 #define HRTIM_SET2R_EXTVNT10_Msk (0x1U << HRTIM_SET2R_EXTVNT10_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 8990 #define HRTIM_SET2R_EXTVNT10 HRTIM_SET2R_EXTVNT10_Msk /*!< External event 10 */
AnnaBridge 171:3a7713b1edbc 8991
AnnaBridge 171:3a7713b1edbc 8992 #define HRTIM_SET2R_UPDATE_Pos (31U)
AnnaBridge 171:3a7713b1edbc 8993 #define HRTIM_SET2R_UPDATE_Msk (0x1U << HRTIM_SET2R_UPDATE_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 8994 #define HRTIM_SET2R_UPDATE HRTIM_SET2R_UPDATE_Msk /*!< Register update (transfer preload to active) */
AnnaBridge 171:3a7713b1edbc 8995
AnnaBridge 171:3a7713b1edbc 8996 /**** Bit definition for Slave Output 2 reset register ************************/
AnnaBridge 171:3a7713b1edbc 8997 #define HRTIM_RST2R_SRT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8998 #define HRTIM_RST2R_SRT_Msk (0x1U << HRTIM_RST2R_SRT_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8999 #define HRTIM_RST2R_SRT HRTIM_RST2R_SRT_Msk /*!< software reset trigger */
AnnaBridge 171:3a7713b1edbc 9000 #define HRTIM_RST2R_RESYNC_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9001 #define HRTIM_RST2R_RESYNC_Msk (0x1U << HRTIM_RST2R_RESYNC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9002 #define HRTIM_RST2R_RESYNC HRTIM_RST2R_RESYNC_Msk /*!< Timer A resynchronization */
AnnaBridge 171:3a7713b1edbc 9003 #define HRTIM_RST2R_PER_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9004 #define HRTIM_RST2R_PER_Msk (0x1U << HRTIM_RST2R_PER_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9005 #define HRTIM_RST2R_PER HRTIM_RST2R_PER_Msk /*!< Timer A period */
AnnaBridge 171:3a7713b1edbc 9006 #define HRTIM_RST2R_CMP1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9007 #define HRTIM_RST2R_CMP1_Msk (0x1U << HRTIM_RST2R_CMP1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9008 #define HRTIM_RST2R_CMP1 HRTIM_RST2R_CMP1_Msk /*!< Timer A compare 1 */
AnnaBridge 171:3a7713b1edbc 9009 #define HRTIM_RST2R_CMP2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9010 #define HRTIM_RST2R_CMP2_Msk (0x1U << HRTIM_RST2R_CMP2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9011 #define HRTIM_RST2R_CMP2 HRTIM_RST2R_CMP2_Msk /*!< Timer A compare 2 */
AnnaBridge 171:3a7713b1edbc 9012 #define HRTIM_RST2R_CMP3_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9013 #define HRTIM_RST2R_CMP3_Msk (0x1U << HRTIM_RST2R_CMP3_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9014 #define HRTIM_RST2R_CMP3 HRTIM_RST2R_CMP3_Msk /*!< Timer A compare 3 */
AnnaBridge 171:3a7713b1edbc 9015 #define HRTIM_RST2R_CMP4_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9016 #define HRTIM_RST2R_CMP4_Msk (0x1U << HRTIM_RST2R_CMP4_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9017 #define HRTIM_RST2R_CMP4 HRTIM_RST2R_CMP4_Msk /*!< Timer A compare 4 */
AnnaBridge 171:3a7713b1edbc 9018
AnnaBridge 171:3a7713b1edbc 9019 #define HRTIM_RST2R_MSTPER_Pos (7U)
AnnaBridge 171:3a7713b1edbc 9020 #define HRTIM_RST2R_MSTPER_Msk (0x1U << HRTIM_RST2R_MSTPER_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9021 #define HRTIM_RST2R_MSTPER HRTIM_RST2R_MSTPER_Msk /*!< Master period */
AnnaBridge 171:3a7713b1edbc 9022 #define HRTIM_RST2R_MSTCMP1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9023 #define HRTIM_RST2R_MSTCMP1_Msk (0x1U << HRTIM_RST2R_MSTCMP1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9024 #define HRTIM_RST2R_MSTCMP1 HRTIM_RST2R_MSTCMP1_Msk /*!< Master compare 1 */
AnnaBridge 171:3a7713b1edbc 9025 #define HRTIM_RST2R_MSTCMP2_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9026 #define HRTIM_RST2R_MSTCMP2_Msk (0x1U << HRTIM_RST2R_MSTCMP2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9027 #define HRTIM_RST2R_MSTCMP2 HRTIM_RST2R_MSTCMP2_Msk /*!< Master compare 2 */
AnnaBridge 171:3a7713b1edbc 9028 #define HRTIM_RST2R_MSTCMP3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9029 #define HRTIM_RST2R_MSTCMP3_Msk (0x1U << HRTIM_RST2R_MSTCMP3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9030 #define HRTIM_RST2R_MSTCMP3 HRTIM_RST2R_MSTCMP3_Msk /*!< Master compare 3 */
AnnaBridge 171:3a7713b1edbc 9031 #define HRTIM_RST2R_MSTCMP4_Pos (11U)
AnnaBridge 171:3a7713b1edbc 9032 #define HRTIM_RST2R_MSTCMP4_Msk (0x1U << HRTIM_RST2R_MSTCMP4_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9033 #define HRTIM_RST2R_MSTCMP4 HRTIM_RST2R_MSTCMP4_Msk /*!< Master compare 4 */
AnnaBridge 171:3a7713b1edbc 9034
AnnaBridge 171:3a7713b1edbc 9035 #define HRTIM_RST2R_TIMEVNT1_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9036 #define HRTIM_RST2R_TIMEVNT1_Msk (0x1U << HRTIM_RST2R_TIMEVNT1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9037 #define HRTIM_RST2R_TIMEVNT1 HRTIM_RST2R_TIMEVNT1_Msk /*!< Timer event 1 */
AnnaBridge 171:3a7713b1edbc 9038 #define HRTIM_RST2R_TIMEVNT2_Pos (13U)
AnnaBridge 171:3a7713b1edbc 9039 #define HRTIM_RST2R_TIMEVNT2_Msk (0x1U << HRTIM_RST2R_TIMEVNT2_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9040 #define HRTIM_RST2R_TIMEVNT2 HRTIM_RST2R_TIMEVNT2_Msk /*!< Timer event 2 */
AnnaBridge 171:3a7713b1edbc 9041 #define HRTIM_RST2R_TIMEVNT3_Pos (14U)
AnnaBridge 171:3a7713b1edbc 9042 #define HRTIM_RST2R_TIMEVNT3_Msk (0x1U << HRTIM_RST2R_TIMEVNT3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 9043 #define HRTIM_RST2R_TIMEVNT3 HRTIM_RST2R_TIMEVNT3_Msk /*!< Timer event 3 */
AnnaBridge 171:3a7713b1edbc 9044 #define HRTIM_RST2R_TIMEVNT4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 9045 #define HRTIM_RST2R_TIMEVNT4_Msk (0x1U << HRTIM_RST2R_TIMEVNT4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 9046 #define HRTIM_RST2R_TIMEVNT4 HRTIM_RST2R_TIMEVNT4_Msk /*!< Timer event 4 */
AnnaBridge 171:3a7713b1edbc 9047 #define HRTIM_RST2R_TIMEVNT5_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9048 #define HRTIM_RST2R_TIMEVNT5_Msk (0x1U << HRTIM_RST2R_TIMEVNT5_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9049 #define HRTIM_RST2R_TIMEVNT5 HRTIM_RST2R_TIMEVNT5_Msk /*!< Timer event 5 */
AnnaBridge 171:3a7713b1edbc 9050 #define HRTIM_RST2R_TIMEVNT6_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9051 #define HRTIM_RST2R_TIMEVNT6_Msk (0x1U << HRTIM_RST2R_TIMEVNT6_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9052 #define HRTIM_RST2R_TIMEVNT6 HRTIM_RST2R_TIMEVNT6_Msk /*!< Timer event 6 */
AnnaBridge 171:3a7713b1edbc 9053 #define HRTIM_RST2R_TIMEVNT7_Pos (18U)
AnnaBridge 171:3a7713b1edbc 9054 #define HRTIM_RST2R_TIMEVNT7_Msk (0x1U << HRTIM_RST2R_TIMEVNT7_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9055 #define HRTIM_RST2R_TIMEVNT7 HRTIM_RST2R_TIMEVNT7_Msk /*!< Timer event 7 */
AnnaBridge 171:3a7713b1edbc 9056 #define HRTIM_RST2R_TIMEVNT8_Pos (19U)
AnnaBridge 171:3a7713b1edbc 9057 #define HRTIM_RST2R_TIMEVNT8_Msk (0x1U << HRTIM_RST2R_TIMEVNT8_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 9058 #define HRTIM_RST2R_TIMEVNT8 HRTIM_RST2R_TIMEVNT8_Msk /*!< Timer event 8 */
AnnaBridge 171:3a7713b1edbc 9059 #define HRTIM_RST2R_TIMEVNT9_Pos (20U)
AnnaBridge 171:3a7713b1edbc 9060 #define HRTIM_RST2R_TIMEVNT9_Msk (0x1U << HRTIM_RST2R_TIMEVNT9_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 9061 #define HRTIM_RST2R_TIMEVNT9 HRTIM_RST2R_TIMEVNT9_Msk /*!< Timer event 9 */
AnnaBridge 171:3a7713b1edbc 9062
AnnaBridge 171:3a7713b1edbc 9063 #define HRTIM_RST2R_EXTVNT1_Pos (21U)
AnnaBridge 171:3a7713b1edbc 9064 #define HRTIM_RST2R_EXTVNT1_Msk (0x1U << HRTIM_RST2R_EXTVNT1_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9065 #define HRTIM_RST2R_EXTVNT1 HRTIM_RST2R_EXTVNT1_Msk /*!< External event 1 */
AnnaBridge 171:3a7713b1edbc 9066 #define HRTIM_RST2R_EXTVNT2_Pos (22U)
AnnaBridge 171:3a7713b1edbc 9067 #define HRTIM_RST2R_EXTVNT2_Msk (0x1U << HRTIM_RST2R_EXTVNT2_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 9068 #define HRTIM_RST2R_EXTVNT2 HRTIM_RST2R_EXTVNT2_Msk /*!< External event 2 */
AnnaBridge 171:3a7713b1edbc 9069 #define HRTIM_RST2R_EXTVNT3_Pos (23U)
AnnaBridge 171:3a7713b1edbc 9070 #define HRTIM_RST2R_EXTVNT3_Msk (0x1U << HRTIM_RST2R_EXTVNT3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 9071 #define HRTIM_RST2R_EXTVNT3 HRTIM_RST2R_EXTVNT3_Msk /*!< External event 3 */
AnnaBridge 171:3a7713b1edbc 9072 #define HRTIM_RST2R_EXTVNT4_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9073 #define HRTIM_RST2R_EXTVNT4_Msk (0x1U << HRTIM_RST2R_EXTVNT4_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 9074 #define HRTIM_RST2R_EXTVNT4 HRTIM_RST2R_EXTVNT4_Msk /*!< External event 4 */
AnnaBridge 171:3a7713b1edbc 9075 #define HRTIM_RST2R_EXTVNT5_Pos (25U)
AnnaBridge 171:3a7713b1edbc 9076 #define HRTIM_RST2R_EXTVNT5_Msk (0x1U << HRTIM_RST2R_EXTVNT5_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 9077 #define HRTIM_RST2R_EXTVNT5 HRTIM_RST2R_EXTVNT5_Msk /*!< External event 5 */
AnnaBridge 171:3a7713b1edbc 9078 #define HRTIM_RST2R_EXTVNT6_Pos (26U)
AnnaBridge 171:3a7713b1edbc 9079 #define HRTIM_RST2R_EXTVNT6_Msk (0x1U << HRTIM_RST2R_EXTVNT6_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 9080 #define HRTIM_RST2R_EXTVNT6 HRTIM_RST2R_EXTVNT6_Msk /*!< External event 6 */
AnnaBridge 171:3a7713b1edbc 9081 #define HRTIM_RST2R_EXTVNT7_Pos (27U)
AnnaBridge 171:3a7713b1edbc 9082 #define HRTIM_RST2R_EXTVNT7_Msk (0x1U << HRTIM_RST2R_EXTVNT7_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 9083 #define HRTIM_RST2R_EXTVNT7 HRTIM_RST2R_EXTVNT7_Msk /*!< External event 7 */
AnnaBridge 171:3a7713b1edbc 9084 #define HRTIM_RST2R_EXTVNT8_Pos (28U)
AnnaBridge 171:3a7713b1edbc 9085 #define HRTIM_RST2R_EXTVNT8_Msk (0x1U << HRTIM_RST2R_EXTVNT8_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 9086 #define HRTIM_RST2R_EXTVNT8 HRTIM_RST2R_EXTVNT8_Msk /*!< External event 8 */
AnnaBridge 171:3a7713b1edbc 9087 #define HRTIM_RST2R_EXTVNT9_Pos (29U)
AnnaBridge 171:3a7713b1edbc 9088 #define HRTIM_RST2R_EXTVNT9_Msk (0x1U << HRTIM_RST2R_EXTVNT9_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 9089 #define HRTIM_RST2R_EXTVNT9 HRTIM_RST2R_EXTVNT9_Msk /*!< External event 9 */
AnnaBridge 171:3a7713b1edbc 9090 #define HRTIM_RST2R_EXTVNT10_Pos (30U)
AnnaBridge 171:3a7713b1edbc 9091 #define HRTIM_RST2R_EXTVNT10_Msk (0x1U << HRTIM_RST2R_EXTVNT10_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 9092 #define HRTIM_RST2R_EXTVNT10 HRTIM_RST2R_EXTVNT10_Msk /*!< External event 10 */
AnnaBridge 171:3a7713b1edbc 9093
AnnaBridge 171:3a7713b1edbc 9094 #define HRTIM_RST2R_UPDATE_Pos (31U)
AnnaBridge 171:3a7713b1edbc 9095 #define HRTIM_RST2R_UPDATE_Msk (0x1U << HRTIM_RST2R_UPDATE_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 9096 #define HRTIM_RST2R_UPDATE HRTIM_RST2R_UPDATE_Msk /*!< Register update (transfer preload to active) */
AnnaBridge 171:3a7713b1edbc 9097
AnnaBridge 171:3a7713b1edbc 9098 /**** Bit definition for Slave external event filtering register 1 ***********/
AnnaBridge 171:3a7713b1edbc 9099 #define HRTIM_EEFR1_EE1LTCH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9100 #define HRTIM_EEFR1_EE1LTCH_Msk (0x1U << HRTIM_EEFR1_EE1LTCH_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9101 #define HRTIM_EEFR1_EE1LTCH HRTIM_EEFR1_EE1LTCH_Msk /*!< External Event 1 latch */
AnnaBridge 171:3a7713b1edbc 9102 #define HRTIM_EEFR1_EE1FLTR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9103 #define HRTIM_EEFR1_EE1FLTR_Msk (0xFU << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x0000001E */
AnnaBridge 171:3a7713b1edbc 9104 #define HRTIM_EEFR1_EE1FLTR HRTIM_EEFR1_EE1FLTR_Msk /*!< External Event 1 filter mask */
AnnaBridge 171:3a7713b1edbc 9105 #define HRTIM_EEFR1_EE1FLTR_0 (0x1U << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9106 #define HRTIM_EEFR1_EE1FLTR_1 (0x2U << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9107 #define HRTIM_EEFR1_EE1FLTR_2 (0x4U << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9108 #define HRTIM_EEFR1_EE1FLTR_3 (0x8U << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9109
AnnaBridge 171:3a7713b1edbc 9110 #define HRTIM_EEFR1_EE2LTCH_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9111 #define HRTIM_EEFR1_EE2LTCH_Msk (0x1U << HRTIM_EEFR1_EE2LTCH_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9112 #define HRTIM_EEFR1_EE2LTCH HRTIM_EEFR1_EE2LTCH_Msk /*!< External Event 2 latch */
AnnaBridge 171:3a7713b1edbc 9113 #define HRTIM_EEFR1_EE2FLTR_Pos (7U)
AnnaBridge 171:3a7713b1edbc 9114 #define HRTIM_EEFR1_EE2FLTR_Msk (0xFU << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000780 */
AnnaBridge 171:3a7713b1edbc 9115 #define HRTIM_EEFR1_EE2FLTR HRTIM_EEFR1_EE2FLTR_Msk /*!< External Event 2 filter mask */
AnnaBridge 171:3a7713b1edbc 9116 #define HRTIM_EEFR1_EE2FLTR_0 (0x1U << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9117 #define HRTIM_EEFR1_EE2FLTR_1 (0x2U << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9118 #define HRTIM_EEFR1_EE2FLTR_2 (0x4U << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9119 #define HRTIM_EEFR1_EE2FLTR_3 (0x8U << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9120
AnnaBridge 171:3a7713b1edbc 9121 #define HRTIM_EEFR1_EE3LTCH_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9122 #define HRTIM_EEFR1_EE3LTCH_Msk (0x1U << HRTIM_EEFR1_EE3LTCH_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9123 #define HRTIM_EEFR1_EE3LTCH HRTIM_EEFR1_EE3LTCH_Msk /*!< External Event 3 latch */
AnnaBridge 171:3a7713b1edbc 9124 #define HRTIM_EEFR1_EE3FLTR_Pos (13U)
AnnaBridge 171:3a7713b1edbc 9125 #define HRTIM_EEFR1_EE3FLTR_Msk (0xFU << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x0001E000 */
AnnaBridge 171:3a7713b1edbc 9126 #define HRTIM_EEFR1_EE3FLTR HRTIM_EEFR1_EE3FLTR_Msk /*!< External Event 3 filter mask */
AnnaBridge 171:3a7713b1edbc 9127 #define HRTIM_EEFR1_EE3FLTR_0 (0x1U << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9128 #define HRTIM_EEFR1_EE3FLTR_1 (0x2U << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 9129 #define HRTIM_EEFR1_EE3FLTR_2 (0x4U << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 9130 #define HRTIM_EEFR1_EE3FLTR_3 (0x8U << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9131
AnnaBridge 171:3a7713b1edbc 9132 #define HRTIM_EEFR1_EE4LTCH_Pos (18U)
AnnaBridge 171:3a7713b1edbc 9133 #define HRTIM_EEFR1_EE4LTCH_Msk (0x1U << HRTIM_EEFR1_EE4LTCH_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9134 #define HRTIM_EEFR1_EE4LTCH HRTIM_EEFR1_EE4LTCH_Msk /*!< External Event 4 latch */
AnnaBridge 171:3a7713b1edbc 9135 #define HRTIM_EEFR1_EE4FLTR_Pos (19U)
AnnaBridge 171:3a7713b1edbc 9136 #define HRTIM_EEFR1_EE4FLTR_Msk (0xFU << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00780000 */
AnnaBridge 171:3a7713b1edbc 9137 #define HRTIM_EEFR1_EE4FLTR HRTIM_EEFR1_EE4FLTR_Msk /*!< External Event 4 filter mask */
AnnaBridge 171:3a7713b1edbc 9138 #define HRTIM_EEFR1_EE4FLTR_0 (0x1U << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 9139 #define HRTIM_EEFR1_EE4FLTR_1 (0x2U << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 9140 #define HRTIM_EEFR1_EE4FLTR_2 (0x4U << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9141 #define HRTIM_EEFR1_EE4FLTR_3 (0x8U << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 9142
AnnaBridge 171:3a7713b1edbc 9143 #define HRTIM_EEFR1_EE5LTCH_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9144 #define HRTIM_EEFR1_EE5LTCH_Msk (0x1U << HRTIM_EEFR1_EE5LTCH_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 9145 #define HRTIM_EEFR1_EE5LTCH HRTIM_EEFR1_EE5LTCH_Msk /*!< External Event 5 latch */
AnnaBridge 171:3a7713b1edbc 9146 #define HRTIM_EEFR1_EE5FLTR_Pos (25U)
AnnaBridge 171:3a7713b1edbc 9147 #define HRTIM_EEFR1_EE5FLTR_Msk (0xFU << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x1E000000 */
AnnaBridge 171:3a7713b1edbc 9148 #define HRTIM_EEFR1_EE5FLTR HRTIM_EEFR1_EE5FLTR_Msk /*!< External Event 5 filter mask */
AnnaBridge 171:3a7713b1edbc 9149 #define HRTIM_EEFR1_EE5FLTR_0 (0x1U << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 9150 #define HRTIM_EEFR1_EE5FLTR_1 (0x2U << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 9151 #define HRTIM_EEFR1_EE5FLTR_2 (0x4U << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 9152 #define HRTIM_EEFR1_EE5FLTR_3 (0x8U << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 9153
AnnaBridge 171:3a7713b1edbc 9154 /**** Bit definition for Slave external event filtering register 2 ***********/
AnnaBridge 171:3a7713b1edbc 9155 #define HRTIM_EEFR2_EE6LTCH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9156 #define HRTIM_EEFR2_EE6LTCH_Msk (0x1U << HRTIM_EEFR2_EE6LTCH_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9157 #define HRTIM_EEFR2_EE6LTCH HRTIM_EEFR2_EE6LTCH_Msk /*!< External Event 6 latch */
AnnaBridge 171:3a7713b1edbc 9158 #define HRTIM_EEFR2_EE6FLTR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9159 #define HRTIM_EEFR2_EE6FLTR_Msk (0xFU << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x0000001E */
AnnaBridge 171:3a7713b1edbc 9160 #define HRTIM_EEFR2_EE6FLTR HRTIM_EEFR2_EE6FLTR_Msk /*!< External Event 6 filter mask */
AnnaBridge 171:3a7713b1edbc 9161 #define HRTIM_EEFR2_EE6FLTR_0 (0x1U << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9162 #define HRTIM_EEFR2_EE6FLTR_1 (0x2U << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9163 #define HRTIM_EEFR2_EE6FLTR_2 (0x4U << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9164 #define HRTIM_EEFR2_EE6FLTR_3 (0x8U << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9165
AnnaBridge 171:3a7713b1edbc 9166 #define HRTIM_EEFR2_EE7LTCH_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9167 #define HRTIM_EEFR2_EE7LTCH_Msk (0x1U << HRTIM_EEFR2_EE7LTCH_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9168 #define HRTIM_EEFR2_EE7LTCH HRTIM_EEFR2_EE7LTCH_Msk /*!< External Event 7 latch */
AnnaBridge 171:3a7713b1edbc 9169 #define HRTIM_EEFR2_EE7FLTR_Pos (7U)
AnnaBridge 171:3a7713b1edbc 9170 #define HRTIM_EEFR2_EE7FLTR_Msk (0xFU << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000780 */
AnnaBridge 171:3a7713b1edbc 9171 #define HRTIM_EEFR2_EE7FLTR HRTIM_EEFR2_EE7FLTR_Msk /*!< External Event 7 filter mask */
AnnaBridge 171:3a7713b1edbc 9172 #define HRTIM_EEFR2_EE7FLTR_0 (0x1U << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9173 #define HRTIM_EEFR2_EE7FLTR_1 (0x2U << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9174 #define HRTIM_EEFR2_EE7FLTR_2 (0x4U << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9175 #define HRTIM_EEFR2_EE7FLTR_3 (0x8U << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9176
AnnaBridge 171:3a7713b1edbc 9177 #define HRTIM_EEFR2_EE8LTCH_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9178 #define HRTIM_EEFR2_EE8LTCH_Msk (0x1U << HRTIM_EEFR2_EE8LTCH_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9179 #define HRTIM_EEFR2_EE8LTCH HRTIM_EEFR2_EE8LTCH_Msk /*!< External Event 8 latch */
AnnaBridge 171:3a7713b1edbc 9180 #define HRTIM_EEFR2_EE8FLTR_Pos (13U)
AnnaBridge 171:3a7713b1edbc 9181 #define HRTIM_EEFR2_EE8FLTR_Msk (0xFU << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x0001E000 */
AnnaBridge 171:3a7713b1edbc 9182 #define HRTIM_EEFR2_EE8FLTR HRTIM_EEFR2_EE8FLTR_Msk /*!< External Event 8 filter mask */
AnnaBridge 171:3a7713b1edbc 9183 #define HRTIM_EEFR2_EE8FLTR_0 (0x1U << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9184 #define HRTIM_EEFR2_EE8FLTR_1 (0x2U << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 9185 #define HRTIM_EEFR2_EE8FLTR_2 (0x4U << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 9186 #define HRTIM_EEFR2_EE8FLTR_3 (0x8U << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9187
AnnaBridge 171:3a7713b1edbc 9188 #define HRTIM_EEFR2_EE9LTCH_Pos (18U)
AnnaBridge 171:3a7713b1edbc 9189 #define HRTIM_EEFR2_EE9LTCH_Msk (0x1U << HRTIM_EEFR2_EE9LTCH_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9190 #define HRTIM_EEFR2_EE9LTCH HRTIM_EEFR2_EE9LTCH_Msk /*!< External Event 9 latch */
AnnaBridge 171:3a7713b1edbc 9191 #define HRTIM_EEFR2_EE9FLTR_Pos (19U)
AnnaBridge 171:3a7713b1edbc 9192 #define HRTIM_EEFR2_EE9FLTR_Msk (0xFU << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00780000 */
AnnaBridge 171:3a7713b1edbc 9193 #define HRTIM_EEFR2_EE9FLTR HRTIM_EEFR2_EE9FLTR_Msk /*!< External Event 9 filter mask */
AnnaBridge 171:3a7713b1edbc 9194 #define HRTIM_EEFR2_EE9FLTR_0 (0x1U << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 9195 #define HRTIM_EEFR2_EE9FLTR_1 (0x2U << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 9196 #define HRTIM_EEFR2_EE9FLTR_2 (0x4U << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9197 #define HRTIM_EEFR2_EE9FLTR_3 (0x8U << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 9198
AnnaBridge 171:3a7713b1edbc 9199 #define HRTIM_EEFR2_EE10LTCH_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9200 #define HRTIM_EEFR2_EE10LTCH_Msk (0x1U << HRTIM_EEFR2_EE10LTCH_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 9201 #define HRTIM_EEFR2_EE10LTCH HRTIM_EEFR2_EE10LTCH_Msk /*!< External Event 10 latch */
AnnaBridge 171:3a7713b1edbc 9202 #define HRTIM_EEFR2_EE10FLTR_Pos (25U)
AnnaBridge 171:3a7713b1edbc 9203 #define HRTIM_EEFR2_EE10FLTR_Msk (0xFU << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x1E000000 */
AnnaBridge 171:3a7713b1edbc 9204 #define HRTIM_EEFR2_EE10FLTR HRTIM_EEFR2_EE10FLTR_Msk /*!< External Event 10 filter mask */
AnnaBridge 171:3a7713b1edbc 9205 #define HRTIM_EEFR2_EE10FLTR_0 (0x1U << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 9206 #define HRTIM_EEFR2_EE10FLTR_1 (0x2U << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 9207 #define HRTIM_EEFR2_EE10FLTR_2 (0x4U << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 9208 #define HRTIM_EEFR2_EE10FLTR_3 (0x8U << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 9209
AnnaBridge 171:3a7713b1edbc 9210 /**** Bit definition for Slave Timer reset register ***************************/
AnnaBridge 171:3a7713b1edbc 9211 #define HRTIM_RSTR_UPDATE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9212 #define HRTIM_RSTR_UPDATE_Msk (0x1U << HRTIM_RSTR_UPDATE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9213 #define HRTIM_RSTR_UPDATE HRTIM_RSTR_UPDATE_Msk /*!< Timer update */
AnnaBridge 171:3a7713b1edbc 9214 #define HRTIM_RSTR_CMP2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9215 #define HRTIM_RSTR_CMP2_Msk (0x1U << HRTIM_RSTR_CMP2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9216 #define HRTIM_RSTR_CMP2 HRTIM_RSTR_CMP2_Msk /*!< Timer compare2 */
AnnaBridge 171:3a7713b1edbc 9217 #define HRTIM_RSTR_CMP4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9218 #define HRTIM_RSTR_CMP4_Msk (0x1U << HRTIM_RSTR_CMP4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9219 #define HRTIM_RSTR_CMP4 HRTIM_RSTR_CMP4_Msk /*!< Timer compare4 */
AnnaBridge 171:3a7713b1edbc 9220
AnnaBridge 171:3a7713b1edbc 9221 #define HRTIM_RSTR_MSTPER_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9222 #define HRTIM_RSTR_MSTPER_Msk (0x1U << HRTIM_RSTR_MSTPER_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9223 #define HRTIM_RSTR_MSTPER HRTIM_RSTR_MSTPER_Msk /*!< Master period */
AnnaBridge 171:3a7713b1edbc 9224 #define HRTIM_RSTR_MSTCMP1_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9225 #define HRTIM_RSTR_MSTCMP1_Msk (0x1U << HRTIM_RSTR_MSTCMP1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9226 #define HRTIM_RSTR_MSTCMP1 HRTIM_RSTR_MSTCMP1_Msk /*!< Master compare1 */
AnnaBridge 171:3a7713b1edbc 9227 #define HRTIM_RSTR_MSTCMP2_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9228 #define HRTIM_RSTR_MSTCMP2_Msk (0x1U << HRTIM_RSTR_MSTCMP2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9229 #define HRTIM_RSTR_MSTCMP2 HRTIM_RSTR_MSTCMP2_Msk /*!< Master compare2 */
AnnaBridge 171:3a7713b1edbc 9230 #define HRTIM_RSTR_MSTCMP3_Pos (7U)
AnnaBridge 171:3a7713b1edbc 9231 #define HRTIM_RSTR_MSTCMP3_Msk (0x1U << HRTIM_RSTR_MSTCMP3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9232 #define HRTIM_RSTR_MSTCMP3 HRTIM_RSTR_MSTCMP3_Msk /*!< Master compare3 */
AnnaBridge 171:3a7713b1edbc 9233 #define HRTIM_RSTR_MSTCMP4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9234 #define HRTIM_RSTR_MSTCMP4_Msk (0x1U << HRTIM_RSTR_MSTCMP4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9235 #define HRTIM_RSTR_MSTCMP4 HRTIM_RSTR_MSTCMP4_Msk /*!< Master compare4 */
AnnaBridge 171:3a7713b1edbc 9236
AnnaBridge 171:3a7713b1edbc 9237 #define HRTIM_RSTR_EXTEVNT1_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9238 #define HRTIM_RSTR_EXTEVNT1_Msk (0x1U << HRTIM_RSTR_EXTEVNT1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9239 #define HRTIM_RSTR_EXTEVNT1 HRTIM_RSTR_EXTEVNT1_Msk /*!< External event 1 */
AnnaBridge 171:3a7713b1edbc 9240 #define HRTIM_RSTR_EXTEVNT2_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9241 #define HRTIM_RSTR_EXTEVNT2_Msk (0x1U << HRTIM_RSTR_EXTEVNT2_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9242 #define HRTIM_RSTR_EXTEVNT2 HRTIM_RSTR_EXTEVNT2_Msk /*!< External event 2 */
AnnaBridge 171:3a7713b1edbc 9243 #define HRTIM_RSTR_EXTEVNT3_Pos (11U)
AnnaBridge 171:3a7713b1edbc 9244 #define HRTIM_RSTR_EXTEVNT3_Msk (0x1U << HRTIM_RSTR_EXTEVNT3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9245 #define HRTIM_RSTR_EXTEVNT3 HRTIM_RSTR_EXTEVNT3_Msk /*!< External event 3 */
AnnaBridge 171:3a7713b1edbc 9246 #define HRTIM_RSTR_EXTEVNT4_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9247 #define HRTIM_RSTR_EXTEVNT4_Msk (0x1U << HRTIM_RSTR_EXTEVNT4_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9248 #define HRTIM_RSTR_EXTEVNT4 HRTIM_RSTR_EXTEVNT4_Msk /*!< External event 4 */
AnnaBridge 171:3a7713b1edbc 9249 #define HRTIM_RSTR_EXTEVNT5_Pos (13U)
AnnaBridge 171:3a7713b1edbc 9250 #define HRTIM_RSTR_EXTEVNT5_Msk (0x1U << HRTIM_RSTR_EXTEVNT5_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9251 #define HRTIM_RSTR_EXTEVNT5 HRTIM_RSTR_EXTEVNT5_Msk /*!< External event 5 */
AnnaBridge 171:3a7713b1edbc 9252 #define HRTIM_RSTR_EXTEVNT6_Pos (14U)
AnnaBridge 171:3a7713b1edbc 9253 #define HRTIM_RSTR_EXTEVNT6_Msk (0x1U << HRTIM_RSTR_EXTEVNT6_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 9254 #define HRTIM_RSTR_EXTEVNT6 HRTIM_RSTR_EXTEVNT6_Msk /*!< External event 6 */
AnnaBridge 171:3a7713b1edbc 9255 #define HRTIM_RSTR_EXTEVNT7_Pos (15U)
AnnaBridge 171:3a7713b1edbc 9256 #define HRTIM_RSTR_EXTEVNT7_Msk (0x1U << HRTIM_RSTR_EXTEVNT7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 9257 #define HRTIM_RSTR_EXTEVNT7 HRTIM_RSTR_EXTEVNT7_Msk /*!< External event 7 */
AnnaBridge 171:3a7713b1edbc 9258 #define HRTIM_RSTR_EXTEVNT8_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9259 #define HRTIM_RSTR_EXTEVNT8_Msk (0x1U << HRTIM_RSTR_EXTEVNT8_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9260 #define HRTIM_RSTR_EXTEVNT8 HRTIM_RSTR_EXTEVNT8_Msk /*!< External event 8 */
AnnaBridge 171:3a7713b1edbc 9261 #define HRTIM_RSTR_EXTEVNT9_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9262 #define HRTIM_RSTR_EXTEVNT9_Msk (0x1U << HRTIM_RSTR_EXTEVNT9_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9263 #define HRTIM_RSTR_EXTEVNT9 HRTIM_RSTR_EXTEVNT9_Msk /*!< External event 9 */
AnnaBridge 171:3a7713b1edbc 9264 #define HRTIM_RSTR_EXTEVNT10_Pos (18U)
AnnaBridge 171:3a7713b1edbc 9265 #define HRTIM_RSTR_EXTEVNT10_Msk (0x1U << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9266 #define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
AnnaBridge 171:3a7713b1edbc 9267
AnnaBridge 171:3a7713b1edbc 9268 #define HRTIM_RSTR_TIMBCMP1_Pos (19U)
AnnaBridge 171:3a7713b1edbc 9269 #define HRTIM_RSTR_TIMBCMP1_Msk (0x1U << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 9270 #define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
AnnaBridge 171:3a7713b1edbc 9271 #define HRTIM_RSTR_TIMBCMP2_Pos (20U)
AnnaBridge 171:3a7713b1edbc 9272 #define HRTIM_RSTR_TIMBCMP2_Msk (0x1U << HRTIM_RSTR_TIMBCMP2_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 9273 #define HRTIM_RSTR_TIMBCMP2 HRTIM_RSTR_TIMBCMP2_Msk /*!< Timer B compare 2 */
AnnaBridge 171:3a7713b1edbc 9274 #define HRTIM_RSTR_TIMBCMP4_Pos (21U)
AnnaBridge 171:3a7713b1edbc 9275 #define HRTIM_RSTR_TIMBCMP4_Msk (0x1U << HRTIM_RSTR_TIMBCMP4_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9276 #define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk /*!< Timer B compare 4 */
AnnaBridge 171:3a7713b1edbc 9277
AnnaBridge 171:3a7713b1edbc 9278 #define HRTIM_RSTR_TIMCCMP1_Pos (22U)
AnnaBridge 171:3a7713b1edbc 9279 #define HRTIM_RSTR_TIMCCMP1_Msk (0x1U << HRTIM_RSTR_TIMCCMP1_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 9280 #define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk /*!< Timer C compare 1 */
AnnaBridge 171:3a7713b1edbc 9281 #define HRTIM_RSTR_TIMCCMP2_Pos (23U)
AnnaBridge 171:3a7713b1edbc 9282 #define HRTIM_RSTR_TIMCCMP2_Msk (0x1U << HRTIM_RSTR_TIMCCMP2_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 9283 #define HRTIM_RSTR_TIMCCMP2 HRTIM_RSTR_TIMCCMP2_Msk /*!< Timer C compare 2 */
AnnaBridge 171:3a7713b1edbc 9284 #define HRTIM_RSTR_TIMCCMP4_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9285 #define HRTIM_RSTR_TIMCCMP4_Msk (0x1U << HRTIM_RSTR_TIMCCMP4_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 9286 #define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk /*!< Timer C compare 4 */
AnnaBridge 171:3a7713b1edbc 9287
AnnaBridge 171:3a7713b1edbc 9288 #define HRTIM_RSTR_TIMDCMP1_Pos (25U)
AnnaBridge 171:3a7713b1edbc 9289 #define HRTIM_RSTR_TIMDCMP1_Msk (0x1U << HRTIM_RSTR_TIMDCMP1_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 9290 #define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk /*!< Timer D compare 1 */
AnnaBridge 171:3a7713b1edbc 9291 #define HRTIM_RSTR_TIMDCMP2_Pos (26U)
AnnaBridge 171:3a7713b1edbc 9292 #define HRTIM_RSTR_TIMDCMP2_Msk (0x1U << HRTIM_RSTR_TIMDCMP2_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 9293 #define HRTIM_RSTR_TIMDCMP2 HRTIM_RSTR_TIMDCMP2_Msk /*!< Timer D compare 2 */
AnnaBridge 171:3a7713b1edbc 9294 #define HRTIM_RSTR_TIMDCMP4_Pos (27U)
AnnaBridge 171:3a7713b1edbc 9295 #define HRTIM_RSTR_TIMDCMP4_Msk (0x1U << HRTIM_RSTR_TIMDCMP4_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 9296 #define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk /*!< Timer D compare 4 */
AnnaBridge 171:3a7713b1edbc 9297
AnnaBridge 171:3a7713b1edbc 9298 #define HRTIM_RSTR_TIMECMP1_Pos (28U)
AnnaBridge 171:3a7713b1edbc 9299 #define HRTIM_RSTR_TIMECMP1_Msk (0x1U << HRTIM_RSTR_TIMECMP1_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 9300 #define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk /*!< Timer E compare 1 */
AnnaBridge 171:3a7713b1edbc 9301 #define HRTIM_RSTR_TIMECMP2_Pos (29U)
AnnaBridge 171:3a7713b1edbc 9302 #define HRTIM_RSTR_TIMECMP2_Msk (0x1U << HRTIM_RSTR_TIMECMP2_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 9303 #define HRTIM_RSTR_TIMECMP2 HRTIM_RSTR_TIMECMP2_Msk /*!< Timer E compare 2 */
AnnaBridge 171:3a7713b1edbc 9304 #define HRTIM_RSTR_TIMECMP4_Pos (30U)
AnnaBridge 171:3a7713b1edbc 9305 #define HRTIM_RSTR_TIMECMP4_Msk (0x1U << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 9306 #define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
AnnaBridge 171:3a7713b1edbc 9307
AnnaBridge 171:3a7713b1edbc 9308 /**** Bit definition for Slave Timer Chopper register *************************/
AnnaBridge 171:3a7713b1edbc 9309 #define HRTIM_CHPR_CARFRQ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9310 #define HRTIM_CHPR_CARFRQ_Msk (0xFU << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 9311 #define HRTIM_CHPR_CARFRQ HRTIM_CHPR_CARFRQ_Msk /*!< Timer carrier frequency value */
AnnaBridge 171:3a7713b1edbc 9312 #define HRTIM_CHPR_CARFRQ_0 (0x1U << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9313 #define HRTIM_CHPR_CARFRQ_1 (0x2U << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9314 #define HRTIM_CHPR_CARFRQ_2 (0x4U << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9315 #define HRTIM_CHPR_CARFRQ_3 (0x8U << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9316
AnnaBridge 171:3a7713b1edbc 9317 #define HRTIM_CHPR_CARDTY_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9318 #define HRTIM_CHPR_CARDTY_Msk (0x7U << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 9319 #define HRTIM_CHPR_CARDTY HRTIM_CHPR_CARDTY_Msk /*!< Timer chopper duty cycle value */
AnnaBridge 171:3a7713b1edbc 9320 #define HRTIM_CHPR_CARDTY_0 (0x1U << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9321 #define HRTIM_CHPR_CARDTY_1 (0x2U << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9322 #define HRTIM_CHPR_CARDTY_2 (0x4U << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9323
AnnaBridge 171:3a7713b1edbc 9324 #define HRTIM_CHPR_STRPW_Pos (7U)
AnnaBridge 171:3a7713b1edbc 9325 #define HRTIM_CHPR_STRPW_Msk (0xFU << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000780 */
AnnaBridge 171:3a7713b1edbc 9326 #define HRTIM_CHPR_STRPW HRTIM_CHPR_STRPW_Msk /*!< Timer start pulse width value */
AnnaBridge 171:3a7713b1edbc 9327 #define HRTIM_CHPR_STRPW_0 (0x1U << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9328 #define HRTIM_CHPR_STRPW_1 (0x2U << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9329 #define HRTIM_CHPR_STRPW_2 (0x4U << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9330 #define HRTIM_CHPR_STRPW_3 (0x8U << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9331
AnnaBridge 171:3a7713b1edbc 9332 /**** Bit definition for Slave Timer Capture 1 control register ***************/
AnnaBridge 171:3a7713b1edbc 9333 #define HRTIM_CPT1CR_SWCPT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9334 #define HRTIM_CPT1CR_SWCPT_Msk (0x1U << HRTIM_CPT1CR_SWCPT_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9335 #define HRTIM_CPT1CR_SWCPT HRTIM_CPT1CR_SWCPT_Msk /*!< Software capture */
AnnaBridge 171:3a7713b1edbc 9336 #define HRTIM_CPT1CR_UPDCPT_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9337 #define HRTIM_CPT1CR_UPDCPT_Msk (0x1U << HRTIM_CPT1CR_UPDCPT_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9338 #define HRTIM_CPT1CR_UPDCPT HRTIM_CPT1CR_UPDCPT_Msk /*!< Update capture */
AnnaBridge 171:3a7713b1edbc 9339 #define HRTIM_CPT1CR_EXEV1CPT_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9340 #define HRTIM_CPT1CR_EXEV1CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV1CPT_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9341 #define HRTIM_CPT1CR_EXEV1CPT HRTIM_CPT1CR_EXEV1CPT_Msk /*!< External event 1 capture */
AnnaBridge 171:3a7713b1edbc 9342 #define HRTIM_CPT1CR_EXEV2CPT_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9343 #define HRTIM_CPT1CR_EXEV2CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV2CPT_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9344 #define HRTIM_CPT1CR_EXEV2CPT HRTIM_CPT1CR_EXEV2CPT_Msk /*!< External event 2 capture */
AnnaBridge 171:3a7713b1edbc 9345 #define HRTIM_CPT1CR_EXEV3CPT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9346 #define HRTIM_CPT1CR_EXEV3CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV3CPT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9347 #define HRTIM_CPT1CR_EXEV3CPT HRTIM_CPT1CR_EXEV3CPT_Msk /*!< External event 3 capture */
AnnaBridge 171:3a7713b1edbc 9348 #define HRTIM_CPT1CR_EXEV4CPT_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9349 #define HRTIM_CPT1CR_EXEV4CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV4CPT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9350 #define HRTIM_CPT1CR_EXEV4CPT HRTIM_CPT1CR_EXEV4CPT_Msk /*!< External event 4 capture */
AnnaBridge 171:3a7713b1edbc 9351 #define HRTIM_CPT1CR_EXEV5CPT_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9352 #define HRTIM_CPT1CR_EXEV5CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV5CPT_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9353 #define HRTIM_CPT1CR_EXEV5CPT HRTIM_CPT1CR_EXEV5CPT_Msk /*!< External event 5 capture */
AnnaBridge 171:3a7713b1edbc 9354 #define HRTIM_CPT1CR_EXEV6CPT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 9355 #define HRTIM_CPT1CR_EXEV6CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV6CPT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9356 #define HRTIM_CPT1CR_EXEV6CPT HRTIM_CPT1CR_EXEV6CPT_Msk /*!< External event 6 capture */
AnnaBridge 171:3a7713b1edbc 9357 #define HRTIM_CPT1CR_EXEV7CPT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9358 #define HRTIM_CPT1CR_EXEV7CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV7CPT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9359 #define HRTIM_CPT1CR_EXEV7CPT HRTIM_CPT1CR_EXEV7CPT_Msk /*!< External event 7 capture */
AnnaBridge 171:3a7713b1edbc 9360 #define HRTIM_CPT1CR_EXEV8CPT_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9361 #define HRTIM_CPT1CR_EXEV8CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV8CPT_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9362 #define HRTIM_CPT1CR_EXEV8CPT HRTIM_CPT1CR_EXEV8CPT_Msk /*!< External event 8 capture */
AnnaBridge 171:3a7713b1edbc 9363 #define HRTIM_CPT1CR_EXEV9CPT_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9364 #define HRTIM_CPT1CR_EXEV9CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV9CPT_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9365 #define HRTIM_CPT1CR_EXEV9CPT HRTIM_CPT1CR_EXEV9CPT_Msk /*!< External event 9 capture */
AnnaBridge 171:3a7713b1edbc 9366 #define HRTIM_CPT1CR_EXEV10CPT_Pos (11U)
AnnaBridge 171:3a7713b1edbc 9367 #define HRTIM_CPT1CR_EXEV10CPT_Msk (0x1U << HRTIM_CPT1CR_EXEV10CPT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9368 #define HRTIM_CPT1CR_EXEV10CPT HRTIM_CPT1CR_EXEV10CPT_Msk /*!< External event 10 capture */
AnnaBridge 171:3a7713b1edbc 9369
AnnaBridge 171:3a7713b1edbc 9370 #define HRTIM_CPT1CR_TA1SET_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9371 #define HRTIM_CPT1CR_TA1SET_Msk (0x1U << HRTIM_CPT1CR_TA1SET_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9372 #define HRTIM_CPT1CR_TA1SET HRTIM_CPT1CR_TA1SET_Msk /*!< Timer A output 1 set */
AnnaBridge 171:3a7713b1edbc 9373 #define HRTIM_CPT1CR_TA1RST_Pos (13U)
AnnaBridge 171:3a7713b1edbc 9374 #define HRTIM_CPT1CR_TA1RST_Msk (0x1U << HRTIM_CPT1CR_TA1RST_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9375 #define HRTIM_CPT1CR_TA1RST HRTIM_CPT1CR_TA1RST_Msk /*!< Timer A output 1 reset */
AnnaBridge 171:3a7713b1edbc 9376 #define HRTIM_CPT1CR_TIMACMP1_Pos (14U)
AnnaBridge 171:3a7713b1edbc 9377 #define HRTIM_CPT1CR_TIMACMP1_Msk (0x1U << HRTIM_CPT1CR_TIMACMP1_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 9378 #define HRTIM_CPT1CR_TIMACMP1 HRTIM_CPT1CR_TIMACMP1_Msk /*!< Timer A compare 1 */
AnnaBridge 171:3a7713b1edbc 9379 #define HRTIM_CPT1CR_TIMACMP2_Pos (15U)
AnnaBridge 171:3a7713b1edbc 9380 #define HRTIM_CPT1CR_TIMACMP2_Msk (0x1U << HRTIM_CPT1CR_TIMACMP2_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 9381 #define HRTIM_CPT1CR_TIMACMP2 HRTIM_CPT1CR_TIMACMP2_Msk /*!< Timer A compare 2 */
AnnaBridge 171:3a7713b1edbc 9382
AnnaBridge 171:3a7713b1edbc 9383 #define HRTIM_CPT1CR_TB1SET_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9384 #define HRTIM_CPT1CR_TB1SET_Msk (0x1U << HRTIM_CPT1CR_TB1SET_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9385 #define HRTIM_CPT1CR_TB1SET HRTIM_CPT1CR_TB1SET_Msk /*!< Timer B output 1 set */
AnnaBridge 171:3a7713b1edbc 9386 #define HRTIM_CPT1CR_TB1RST_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9387 #define HRTIM_CPT1CR_TB1RST_Msk (0x1U << HRTIM_CPT1CR_TB1RST_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9388 #define HRTIM_CPT1CR_TB1RST HRTIM_CPT1CR_TB1RST_Msk /*!< Timer B output 1 reset */
AnnaBridge 171:3a7713b1edbc 9389 #define HRTIM_CPT1CR_TIMBCMP1_Pos (18U)
AnnaBridge 171:3a7713b1edbc 9390 #define HRTIM_CPT1CR_TIMBCMP1_Msk (0x1U << HRTIM_CPT1CR_TIMBCMP1_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9391 #define HRTIM_CPT1CR_TIMBCMP1 HRTIM_CPT1CR_TIMBCMP1_Msk /*!< Timer B compare 1 */
AnnaBridge 171:3a7713b1edbc 9392 #define HRTIM_CPT1CR_TIMBCMP2_Pos (19U)
AnnaBridge 171:3a7713b1edbc 9393 #define HRTIM_CPT1CR_TIMBCMP2_Msk (0x1U << HRTIM_CPT1CR_TIMBCMP2_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 9394 #define HRTIM_CPT1CR_TIMBCMP2 HRTIM_CPT1CR_TIMBCMP2_Msk /*!< Timer B compare 2 */
AnnaBridge 171:3a7713b1edbc 9395
AnnaBridge 171:3a7713b1edbc 9396 #define HRTIM_CPT1CR_TC1SET_Pos (20U)
AnnaBridge 171:3a7713b1edbc 9397 #define HRTIM_CPT1CR_TC1SET_Msk (0x1U << HRTIM_CPT1CR_TC1SET_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 9398 #define HRTIM_CPT1CR_TC1SET HRTIM_CPT1CR_TC1SET_Msk /*!< Timer C output 1 set */
AnnaBridge 171:3a7713b1edbc 9399 #define HRTIM_CPT1CR_TC1RST_Pos (21U)
AnnaBridge 171:3a7713b1edbc 9400 #define HRTIM_CPT1CR_TC1RST_Msk (0x1U << HRTIM_CPT1CR_TC1RST_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9401 #define HRTIM_CPT1CR_TC1RST HRTIM_CPT1CR_TC1RST_Msk /*!< Timer C output 1 reset */
AnnaBridge 171:3a7713b1edbc 9402 #define HRTIM_CPT1CR_TIMCCMP1_Pos (22U)
AnnaBridge 171:3a7713b1edbc 9403 #define HRTIM_CPT1CR_TIMCCMP1_Msk (0x1U << HRTIM_CPT1CR_TIMCCMP1_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 9404 #define HRTIM_CPT1CR_TIMCCMP1 HRTIM_CPT1CR_TIMCCMP1_Msk /*!< Timer C compare 1 */
AnnaBridge 171:3a7713b1edbc 9405 #define HRTIM_CPT1CR_TIMCCMP2_Pos (23U)
AnnaBridge 171:3a7713b1edbc 9406 #define HRTIM_CPT1CR_TIMCCMP2_Msk (0x1U << HRTIM_CPT1CR_TIMCCMP2_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 9407 #define HRTIM_CPT1CR_TIMCCMP2 HRTIM_CPT1CR_TIMCCMP2_Msk /*!< Timer C compare 2 */
AnnaBridge 171:3a7713b1edbc 9408
AnnaBridge 171:3a7713b1edbc 9409 #define HRTIM_CPT1CR_TD1SET_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9410 #define HRTIM_CPT1CR_TD1SET_Msk (0x1U << HRTIM_CPT1CR_TD1SET_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 9411 #define HRTIM_CPT1CR_TD1SET HRTIM_CPT1CR_TD1SET_Msk /*!< Timer D output 1 set */
AnnaBridge 171:3a7713b1edbc 9412 #define HRTIM_CPT1CR_TD1RST_Pos (25U)
AnnaBridge 171:3a7713b1edbc 9413 #define HRTIM_CPT1CR_TD1RST_Msk (0x1U << HRTIM_CPT1CR_TD1RST_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 9414 #define HRTIM_CPT1CR_TD1RST HRTIM_CPT1CR_TD1RST_Msk /*!< Timer D output 1 reset */
AnnaBridge 171:3a7713b1edbc 9415 #define HRTIM_CPT1CR_TIMDCMP1_Pos (26U)
AnnaBridge 171:3a7713b1edbc 9416 #define HRTIM_CPT1CR_TIMDCMP1_Msk (0x1U << HRTIM_CPT1CR_TIMDCMP1_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 9417 #define HRTIM_CPT1CR_TIMDCMP1 HRTIM_CPT1CR_TIMDCMP1_Msk /*!< Timer D compare 1 */
AnnaBridge 171:3a7713b1edbc 9418 #define HRTIM_CPT1CR_TIMDCMP2_Pos (27U)
AnnaBridge 171:3a7713b1edbc 9419 #define HRTIM_CPT1CR_TIMDCMP2_Msk (0x1U << HRTIM_CPT1CR_TIMDCMP2_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 9420 #define HRTIM_CPT1CR_TIMDCMP2 HRTIM_CPT1CR_TIMDCMP2_Msk /*!< Timer D compare 2 */
AnnaBridge 171:3a7713b1edbc 9421
AnnaBridge 171:3a7713b1edbc 9422 #define HRTIM_CPT1CR_TE1SET_Pos (28U)
AnnaBridge 171:3a7713b1edbc 9423 #define HRTIM_CPT1CR_TE1SET_Msk (0x1U << HRTIM_CPT1CR_TE1SET_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 9424 #define HRTIM_CPT1CR_TE1SET HRTIM_CPT1CR_TE1SET_Msk /*!< Timer E output 1 set */
AnnaBridge 171:3a7713b1edbc 9425 #define HRTIM_CPT1CR_TE1RST_Pos (29U)
AnnaBridge 171:3a7713b1edbc 9426 #define HRTIM_CPT1CR_TE1RST_Msk (0x1U << HRTIM_CPT1CR_TE1RST_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 9427 #define HRTIM_CPT1CR_TE1RST HRTIM_CPT1CR_TE1RST_Msk /*!< Timer E output 1 reset */
AnnaBridge 171:3a7713b1edbc 9428 #define HRTIM_CPT1CR_TIMECMP1_Pos (30U)
AnnaBridge 171:3a7713b1edbc 9429 #define HRTIM_CPT1CR_TIMECMP1_Msk (0x1U << HRTIM_CPT1CR_TIMECMP1_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 9430 #define HRTIM_CPT1CR_TIMECMP1 HRTIM_CPT1CR_TIMECMP1_Msk /*!< Timer E compare 1 */
AnnaBridge 171:3a7713b1edbc 9431 #define HRTIM_CPT1CR_TIMECMP2_Pos (31U)
AnnaBridge 171:3a7713b1edbc 9432 #define HRTIM_CPT1CR_TIMECMP2_Msk (0x1U << HRTIM_CPT1CR_TIMECMP2_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 9433 #define HRTIM_CPT1CR_TIMECMP2 HRTIM_CPT1CR_TIMECMP2_Msk /*!< Timer E compare 2 */
AnnaBridge 171:3a7713b1edbc 9434
AnnaBridge 171:3a7713b1edbc 9435 /**** Bit definition for Slave Timer Capture 2 control register ***************/
AnnaBridge 171:3a7713b1edbc 9436 #define HRTIM_CPT2CR_SWCPT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9437 #define HRTIM_CPT2CR_SWCPT_Msk (0x1U << HRTIM_CPT2CR_SWCPT_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9438 #define HRTIM_CPT2CR_SWCPT HRTIM_CPT2CR_SWCPT_Msk /*!< Software capture */
AnnaBridge 171:3a7713b1edbc 9439 #define HRTIM_CPT2CR_UPDCPT_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9440 #define HRTIM_CPT2CR_UPDCPT_Msk (0x1U << HRTIM_CPT2CR_UPDCPT_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9441 #define HRTIM_CPT2CR_UPDCPT HRTIM_CPT2CR_UPDCPT_Msk /*!< Update capture */
AnnaBridge 171:3a7713b1edbc 9442 #define HRTIM_CPT2CR_EXEV1CPT_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9443 #define HRTIM_CPT2CR_EXEV1CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV1CPT_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9444 #define HRTIM_CPT2CR_EXEV1CPT HRTIM_CPT2CR_EXEV1CPT_Msk /*!< External event 1 capture */
AnnaBridge 171:3a7713b1edbc 9445 #define HRTIM_CPT2CR_EXEV2CPT_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9446 #define HRTIM_CPT2CR_EXEV2CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV2CPT_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9447 #define HRTIM_CPT2CR_EXEV2CPT HRTIM_CPT2CR_EXEV2CPT_Msk /*!< External event 2 capture */
AnnaBridge 171:3a7713b1edbc 9448 #define HRTIM_CPT2CR_EXEV3CPT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9449 #define HRTIM_CPT2CR_EXEV3CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV3CPT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9450 #define HRTIM_CPT2CR_EXEV3CPT HRTIM_CPT2CR_EXEV3CPT_Msk /*!< External event 3 capture */
AnnaBridge 171:3a7713b1edbc 9451 #define HRTIM_CPT2CR_EXEV4CPT_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9452 #define HRTIM_CPT2CR_EXEV4CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV4CPT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9453 #define HRTIM_CPT2CR_EXEV4CPT HRTIM_CPT2CR_EXEV4CPT_Msk /*!< External event 4 capture */
AnnaBridge 171:3a7713b1edbc 9454 #define HRTIM_CPT2CR_EXEV5CPT_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9455 #define HRTIM_CPT2CR_EXEV5CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV5CPT_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9456 #define HRTIM_CPT2CR_EXEV5CPT HRTIM_CPT2CR_EXEV5CPT_Msk /*!< External event 5 capture */
AnnaBridge 171:3a7713b1edbc 9457 #define HRTIM_CPT2CR_EXEV6CPT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 9458 #define HRTIM_CPT2CR_EXEV6CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV6CPT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9459 #define HRTIM_CPT2CR_EXEV6CPT HRTIM_CPT2CR_EXEV6CPT_Msk /*!< External event 6 capture */
AnnaBridge 171:3a7713b1edbc 9460 #define HRTIM_CPT2CR_EXEV7CPT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9461 #define HRTIM_CPT2CR_EXEV7CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV7CPT_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9462 #define HRTIM_CPT2CR_EXEV7CPT HRTIM_CPT2CR_EXEV7CPT_Msk /*!< External event 7 capture */
AnnaBridge 171:3a7713b1edbc 9463 #define HRTIM_CPT2CR_EXEV8CPT_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9464 #define HRTIM_CPT2CR_EXEV8CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV8CPT_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9465 #define HRTIM_CPT2CR_EXEV8CPT HRTIM_CPT2CR_EXEV8CPT_Msk /*!< External event 8 capture */
AnnaBridge 171:3a7713b1edbc 9466 #define HRTIM_CPT2CR_EXEV9CPT_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9467 #define HRTIM_CPT2CR_EXEV9CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV9CPT_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9468 #define HRTIM_CPT2CR_EXEV9CPT HRTIM_CPT2CR_EXEV9CPT_Msk /*!< External event 9 capture */
AnnaBridge 171:3a7713b1edbc 9469 #define HRTIM_CPT2CR_EXEV10CPT_Pos (11U)
AnnaBridge 171:3a7713b1edbc 9470 #define HRTIM_CPT2CR_EXEV10CPT_Msk (0x1U << HRTIM_CPT2CR_EXEV10CPT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9471 #define HRTIM_CPT2CR_EXEV10CPT HRTIM_CPT2CR_EXEV10CPT_Msk /*!< External event 10 capture */
AnnaBridge 171:3a7713b1edbc 9472
AnnaBridge 171:3a7713b1edbc 9473 #define HRTIM_CPT2CR_TA1SET_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9474 #define HRTIM_CPT2CR_TA1SET_Msk (0x1U << HRTIM_CPT2CR_TA1SET_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9475 #define HRTIM_CPT2CR_TA1SET HRTIM_CPT2CR_TA1SET_Msk /*!< Timer A output 1 set */
AnnaBridge 171:3a7713b1edbc 9476 #define HRTIM_CPT2CR_TA1RST_Pos (13U)
AnnaBridge 171:3a7713b1edbc 9477 #define HRTIM_CPT2CR_TA1RST_Msk (0x1U << HRTIM_CPT2CR_TA1RST_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9478 #define HRTIM_CPT2CR_TA1RST HRTIM_CPT2CR_TA1RST_Msk /*!< Timer A output 1 reset */
AnnaBridge 171:3a7713b1edbc 9479 #define HRTIM_CPT2CR_TIMACMP1_Pos (14U)
AnnaBridge 171:3a7713b1edbc 9480 #define HRTIM_CPT2CR_TIMACMP1_Msk (0x1U << HRTIM_CPT2CR_TIMACMP1_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 9481 #define HRTIM_CPT2CR_TIMACMP1 HRTIM_CPT2CR_TIMACMP1_Msk /*!< Timer A compare 1 */
AnnaBridge 171:3a7713b1edbc 9482 #define HRTIM_CPT2CR_TIMACMP2_Pos (15U)
AnnaBridge 171:3a7713b1edbc 9483 #define HRTIM_CPT2CR_TIMACMP2_Msk (0x1U << HRTIM_CPT2CR_TIMACMP2_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 9484 #define HRTIM_CPT2CR_TIMACMP2 HRTIM_CPT2CR_TIMACMP2_Msk /*!< Timer A compare 2 */
AnnaBridge 171:3a7713b1edbc 9485
AnnaBridge 171:3a7713b1edbc 9486 #define HRTIM_CPT2CR_TB1SET_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9487 #define HRTIM_CPT2CR_TB1SET_Msk (0x1U << HRTIM_CPT2CR_TB1SET_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9488 #define HRTIM_CPT2CR_TB1SET HRTIM_CPT2CR_TB1SET_Msk /*!< Timer B output 1 set */
AnnaBridge 171:3a7713b1edbc 9489 #define HRTIM_CPT2CR_TB1RST_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9490 #define HRTIM_CPT2CR_TB1RST_Msk (0x1U << HRTIM_CPT2CR_TB1RST_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9491 #define HRTIM_CPT2CR_TB1RST HRTIM_CPT2CR_TB1RST_Msk /*!< Timer B output 1 reset */
AnnaBridge 171:3a7713b1edbc 9492 #define HRTIM_CPT2CR_TIMBCMP1_Pos (18U)
AnnaBridge 171:3a7713b1edbc 9493 #define HRTIM_CPT2CR_TIMBCMP1_Msk (0x1U << HRTIM_CPT2CR_TIMBCMP1_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9494 #define HRTIM_CPT2CR_TIMBCMP1 HRTIM_CPT2CR_TIMBCMP1_Msk /*!< Timer B compare 1 */
AnnaBridge 171:3a7713b1edbc 9495 #define HRTIM_CPT2CR_TIMBCMP2_Pos (19U)
AnnaBridge 171:3a7713b1edbc 9496 #define HRTIM_CPT2CR_TIMBCMP2_Msk (0x1U << HRTIM_CPT2CR_TIMBCMP2_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 9497 #define HRTIM_CPT2CR_TIMBCMP2 HRTIM_CPT2CR_TIMBCMP2_Msk /*!< Timer B compare 2 */
AnnaBridge 171:3a7713b1edbc 9498
AnnaBridge 171:3a7713b1edbc 9499 #define HRTIM_CPT2CR_TC1SET_Pos (20U)
AnnaBridge 171:3a7713b1edbc 9500 #define HRTIM_CPT2CR_TC1SET_Msk (0x1U << HRTIM_CPT2CR_TC1SET_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 9501 #define HRTIM_CPT2CR_TC1SET HRTIM_CPT2CR_TC1SET_Msk /*!< Timer C output 1 set */
AnnaBridge 171:3a7713b1edbc 9502 #define HRTIM_CPT2CR_TC1RST_Pos (21U)
AnnaBridge 171:3a7713b1edbc 9503 #define HRTIM_CPT2CR_TC1RST_Msk (0x1U << HRTIM_CPT2CR_TC1RST_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9504 #define HRTIM_CPT2CR_TC1RST HRTIM_CPT2CR_TC1RST_Msk /*!< Timer C output 1 reset */
AnnaBridge 171:3a7713b1edbc 9505 #define HRTIM_CPT2CR_TIMCCMP1_Pos (22U)
AnnaBridge 171:3a7713b1edbc 9506 #define HRTIM_CPT2CR_TIMCCMP1_Msk (0x1U << HRTIM_CPT2CR_TIMCCMP1_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 9507 #define HRTIM_CPT2CR_TIMCCMP1 HRTIM_CPT2CR_TIMCCMP1_Msk /*!< Timer C compare 1 */
AnnaBridge 171:3a7713b1edbc 9508 #define HRTIM_CPT2CR_TIMCCMP2_Pos (23U)
AnnaBridge 171:3a7713b1edbc 9509 #define HRTIM_CPT2CR_TIMCCMP2_Msk (0x1U << HRTIM_CPT2CR_TIMCCMP2_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 9510 #define HRTIM_CPT2CR_TIMCCMP2 HRTIM_CPT2CR_TIMCCMP2_Msk /*!< Timer C compare 2 */
AnnaBridge 171:3a7713b1edbc 9511
AnnaBridge 171:3a7713b1edbc 9512 #define HRTIM_CPT2CR_TD1SET_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9513 #define HRTIM_CPT2CR_TD1SET_Msk (0x1U << HRTIM_CPT2CR_TD1SET_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 9514 #define HRTIM_CPT2CR_TD1SET HRTIM_CPT2CR_TD1SET_Msk /*!< Timer D output 1 set */
AnnaBridge 171:3a7713b1edbc 9515 #define HRTIM_CPT2CR_TD1RST_Pos (25U)
AnnaBridge 171:3a7713b1edbc 9516 #define HRTIM_CPT2CR_TD1RST_Msk (0x1U << HRTIM_CPT2CR_TD1RST_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 9517 #define HRTIM_CPT2CR_TD1RST HRTIM_CPT2CR_TD1RST_Msk /*!< Timer D output 1 reset */
AnnaBridge 171:3a7713b1edbc 9518 #define HRTIM_CPT2CR_TIMDCMP1_Pos (26U)
AnnaBridge 171:3a7713b1edbc 9519 #define HRTIM_CPT2CR_TIMDCMP1_Msk (0x1U << HRTIM_CPT2CR_TIMDCMP1_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 9520 #define HRTIM_CPT2CR_TIMDCMP1 HRTIM_CPT2CR_TIMDCMP1_Msk /*!< Timer D compare 1 */
AnnaBridge 171:3a7713b1edbc 9521 #define HRTIM_CPT2CR_TIMDCMP2_Pos (27U)
AnnaBridge 171:3a7713b1edbc 9522 #define HRTIM_CPT2CR_TIMDCMP2_Msk (0x1U << HRTIM_CPT2CR_TIMDCMP2_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 9523 #define HRTIM_CPT2CR_TIMDCMP2 HRTIM_CPT2CR_TIMDCMP2_Msk /*!< Timer D compare 2 */
AnnaBridge 171:3a7713b1edbc 9524
AnnaBridge 171:3a7713b1edbc 9525 #define HRTIM_CPT2CR_TE1SET_Pos (28U)
AnnaBridge 171:3a7713b1edbc 9526 #define HRTIM_CPT2CR_TE1SET_Msk (0x1U << HRTIM_CPT2CR_TE1SET_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 9527 #define HRTIM_CPT2CR_TE1SET HRTIM_CPT2CR_TE1SET_Msk /*!< Timer E output 1 set */
AnnaBridge 171:3a7713b1edbc 9528 #define HRTIM_CPT2CR_TE1RST_Pos (29U)
AnnaBridge 171:3a7713b1edbc 9529 #define HRTIM_CPT2CR_TE1RST_Msk (0x1U << HRTIM_CPT2CR_TE1RST_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 9530 #define HRTIM_CPT2CR_TE1RST HRTIM_CPT2CR_TE1RST_Msk /*!< Timer E output 1 reset */
AnnaBridge 171:3a7713b1edbc 9531 #define HRTIM_CPT2CR_TIMECMP1_Pos (30U)
AnnaBridge 171:3a7713b1edbc 9532 #define HRTIM_CPT2CR_TIMECMP1_Msk (0x1U << HRTIM_CPT2CR_TIMECMP1_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 9533 #define HRTIM_CPT2CR_TIMECMP1 HRTIM_CPT2CR_TIMECMP1_Msk /*!< Timer E compare 1 */
AnnaBridge 171:3a7713b1edbc 9534 #define HRTIM_CPT2CR_TIMECMP2_Pos (31U)
AnnaBridge 171:3a7713b1edbc 9535 #define HRTIM_CPT2CR_TIMECMP2_Msk (0x1U << HRTIM_CPT2CR_TIMECMP2_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 9536 #define HRTIM_CPT2CR_TIMECMP2 HRTIM_CPT2CR_TIMECMP2_Msk /*!< Timer E compare 2 */
AnnaBridge 171:3a7713b1edbc 9537
AnnaBridge 171:3a7713b1edbc 9538 /**** Bit definition for Slave Timer Output register **************************/
AnnaBridge 171:3a7713b1edbc 9539 #define HRTIM_OUTR_POL1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9540 #define HRTIM_OUTR_POL1_Msk (0x1U << HRTIM_OUTR_POL1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9541 #define HRTIM_OUTR_POL1 HRTIM_OUTR_POL1_Msk /*!< Slave output 1 polarity */
AnnaBridge 171:3a7713b1edbc 9542 #define HRTIM_OUTR_IDLM1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9543 #define HRTIM_OUTR_IDLM1_Msk (0x1U << HRTIM_OUTR_IDLM1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9544 #define HRTIM_OUTR_IDLM1 HRTIM_OUTR_IDLM1_Msk /*!< Slave output 1 idle mode */
AnnaBridge 171:3a7713b1edbc 9545 #define HRTIM_OUTR_IDLES1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9546 #define HRTIM_OUTR_IDLES1_Msk (0x1U << HRTIM_OUTR_IDLES1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9547 #define HRTIM_OUTR_IDLES1 HRTIM_OUTR_IDLES1_Msk /*!< Slave output 1 idle state */
AnnaBridge 171:3a7713b1edbc 9548 #define HRTIM_OUTR_FAULT1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9549 #define HRTIM_OUTR_FAULT1_Msk (0x3U << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 9550 #define HRTIM_OUTR_FAULT1 HRTIM_OUTR_FAULT1_Msk /*!< Slave output 1 fault state */
AnnaBridge 171:3a7713b1edbc 9551 #define HRTIM_OUTR_FAULT1_0 (0x1U << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9552 #define HRTIM_OUTR_FAULT1_1 (0x2U << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9553 #define HRTIM_OUTR_CHP1_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9554 #define HRTIM_OUTR_CHP1_Msk (0x1U << HRTIM_OUTR_CHP1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9555 #define HRTIM_OUTR_CHP1 HRTIM_OUTR_CHP1_Msk /*!< Slave output 1 chopper enable */
AnnaBridge 171:3a7713b1edbc 9556 #define HRTIM_OUTR_DIDL1_Pos (7U)
AnnaBridge 171:3a7713b1edbc 9557 #define HRTIM_OUTR_DIDL1_Msk (0x1U << HRTIM_OUTR_DIDL1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9558 #define HRTIM_OUTR_DIDL1 HRTIM_OUTR_DIDL1_Msk /*!< Slave output 1 dead time idle */
AnnaBridge 171:3a7713b1edbc 9559
AnnaBridge 171:3a7713b1edbc 9560 #define HRTIM_OUTR_DTEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9561 #define HRTIM_OUTR_DTEN_Msk (0x1U << HRTIM_OUTR_DTEN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9562 #define HRTIM_OUTR_DTEN HRTIM_OUTR_DTEN_Msk /*!< Slave output deadtime enable */
AnnaBridge 171:3a7713b1edbc 9563 #define HRTIM_OUTR_DLYPRTEN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9564 #define HRTIM_OUTR_DLYPRTEN_Msk (0x1U << HRTIM_OUTR_DLYPRTEN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9565 #define HRTIM_OUTR_DLYPRTEN HRTIM_OUTR_DLYPRTEN_Msk /*!< Slave output delay protection enable */
AnnaBridge 171:3a7713b1edbc 9566 #define HRTIM_OUTR_DLYPRT_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9567 #define HRTIM_OUTR_DLYPRT_Msk (0x7U << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001C00 */
AnnaBridge 171:3a7713b1edbc 9568 #define HRTIM_OUTR_DLYPRT HRTIM_OUTR_DLYPRT_Msk /*!< Slave output delay protection */
AnnaBridge 171:3a7713b1edbc 9569 #define HRTIM_OUTR_DLYPRT_0 (0x1U << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9570 #define HRTIM_OUTR_DLYPRT_1 (0x2U << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9571 #define HRTIM_OUTR_DLYPRT_2 (0x4U << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9572
AnnaBridge 171:3a7713b1edbc 9573 #define HRTIM_OUTR_POL2_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9574 #define HRTIM_OUTR_POL2_Msk (0x1U << HRTIM_OUTR_POL2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9575 #define HRTIM_OUTR_POL2 HRTIM_OUTR_POL2_Msk /*!< Slave output 2 polarity */
AnnaBridge 171:3a7713b1edbc 9576 #define HRTIM_OUTR_IDLM2_Pos (18U)
AnnaBridge 171:3a7713b1edbc 9577 #define HRTIM_OUTR_IDLM2_Msk (0x1U << HRTIM_OUTR_IDLM2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9578 #define HRTIM_OUTR_IDLM2 HRTIM_OUTR_IDLM2_Msk /*!< Slave output 2 idle mode */
AnnaBridge 171:3a7713b1edbc 9579 #define HRTIM_OUTR_IDLES2_Pos (19U)
AnnaBridge 171:3a7713b1edbc 9580 #define HRTIM_OUTR_IDLES2_Msk (0x1U << HRTIM_OUTR_IDLES2_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 9581 #define HRTIM_OUTR_IDLES2 HRTIM_OUTR_IDLES2_Msk /*!< Slave output 2 idle state */
AnnaBridge 171:3a7713b1edbc 9582 #define HRTIM_OUTR_FAULT2_Pos (20U)
AnnaBridge 171:3a7713b1edbc 9583 #define HRTIM_OUTR_FAULT2_Msk (0x3U << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 9584 #define HRTIM_OUTR_FAULT2 HRTIM_OUTR_FAULT2_Msk /*!< Slave output 2 fault state */
AnnaBridge 171:3a7713b1edbc 9585 #define HRTIM_OUTR_FAULT2_0 (0x1U << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 9586 #define HRTIM_OUTR_FAULT2_1 (0x2U << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9587 #define HRTIM_OUTR_CHP2_Pos (22U)
AnnaBridge 171:3a7713b1edbc 9588 #define HRTIM_OUTR_CHP2_Msk (0x1U << HRTIM_OUTR_CHP2_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 9589 #define HRTIM_OUTR_CHP2 HRTIM_OUTR_CHP2_Msk /*!< Slave output 2 chopper enable */
AnnaBridge 171:3a7713b1edbc 9590 #define HRTIM_OUTR_DIDL2_Pos (23U)
AnnaBridge 171:3a7713b1edbc 9591 #define HRTIM_OUTR_DIDL2_Msk (0x1U << HRTIM_OUTR_DIDL2_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 9592 #define HRTIM_OUTR_DIDL2 HRTIM_OUTR_DIDL2_Msk /*!< Slave output 2 dead time idle */
AnnaBridge 171:3a7713b1edbc 9593
AnnaBridge 171:3a7713b1edbc 9594 /**** Bit definition for Slave Timer Fault register ***************************/
AnnaBridge 171:3a7713b1edbc 9595 #define HRTIM_FLTR_FLT1EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9596 #define HRTIM_FLTR_FLT1EN_Msk (0x1U << HRTIM_FLTR_FLT1EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9597 #define HRTIM_FLTR_FLT1EN HRTIM_FLTR_FLT1EN_Msk /*!< Fault 1 enable */
AnnaBridge 171:3a7713b1edbc 9598 #define HRTIM_FLTR_FLT2EN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9599 #define HRTIM_FLTR_FLT2EN_Msk (0x1U << HRTIM_FLTR_FLT2EN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9600 #define HRTIM_FLTR_FLT2EN HRTIM_FLTR_FLT2EN_Msk /*!< Fault 2 enable */
AnnaBridge 171:3a7713b1edbc 9601 #define HRTIM_FLTR_FLT3EN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9602 #define HRTIM_FLTR_FLT3EN_Msk (0x1U << HRTIM_FLTR_FLT3EN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9603 #define HRTIM_FLTR_FLT3EN HRTIM_FLTR_FLT3EN_Msk /*!< Fault 3 enable */
AnnaBridge 171:3a7713b1edbc 9604 #define HRTIM_FLTR_FLT4EN_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9605 #define HRTIM_FLTR_FLT4EN_Msk (0x1U << HRTIM_FLTR_FLT4EN_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9606 #define HRTIM_FLTR_FLT4EN HRTIM_FLTR_FLT4EN_Msk /*!< Fault 4 enable */
AnnaBridge 171:3a7713b1edbc 9607 #define HRTIM_FLTR_FLT5EN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9608 #define HRTIM_FLTR_FLT5EN_Msk (0x1U << HRTIM_FLTR_FLT5EN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9609 #define HRTIM_FLTR_FLT5EN HRTIM_FLTR_FLT5EN_Msk /*!< Fault 5 enable */
AnnaBridge 171:3a7713b1edbc 9610 #define HRTIM_FLTR_FLTLCK_Pos (31U)
AnnaBridge 171:3a7713b1edbc 9611 #define HRTIM_FLTR_FLTLCK_Msk (0x1U << HRTIM_FLTR_FLTLCK_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 9612 #define HRTIM_FLTR_FLTLCK HRTIM_FLTR_FLTLCK_Msk /*!< Fault sources lock */
AnnaBridge 171:3a7713b1edbc 9613
AnnaBridge 171:3a7713b1edbc 9614 /**** Bit definition for Common HRTIM Timer control register 1 ****************/
AnnaBridge 171:3a7713b1edbc 9615 #define HRTIM_CR1_MUDIS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9616 #define HRTIM_CR1_MUDIS_Msk (0x1U << HRTIM_CR1_MUDIS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9617 #define HRTIM_CR1_MUDIS HRTIM_CR1_MUDIS_Msk /*!< Master update disable*/
AnnaBridge 171:3a7713b1edbc 9618 #define HRTIM_CR1_TAUDIS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9619 #define HRTIM_CR1_TAUDIS_Msk (0x1U << HRTIM_CR1_TAUDIS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9620 #define HRTIM_CR1_TAUDIS HRTIM_CR1_TAUDIS_Msk /*!< Timer A update disable*/
AnnaBridge 171:3a7713b1edbc 9621 #define HRTIM_CR1_TBUDIS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9622 #define HRTIM_CR1_TBUDIS_Msk (0x1U << HRTIM_CR1_TBUDIS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9623 #define HRTIM_CR1_TBUDIS HRTIM_CR1_TBUDIS_Msk /*!< Timer B update disable*/
AnnaBridge 171:3a7713b1edbc 9624 #define HRTIM_CR1_TCUDIS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9625 #define HRTIM_CR1_TCUDIS_Msk (0x1U << HRTIM_CR1_TCUDIS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9626 #define HRTIM_CR1_TCUDIS HRTIM_CR1_TCUDIS_Msk /*!< Timer C update disable*/
AnnaBridge 171:3a7713b1edbc 9627 #define HRTIM_CR1_TDUDIS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9628 #define HRTIM_CR1_TDUDIS_Msk (0x1U << HRTIM_CR1_TDUDIS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9629 #define HRTIM_CR1_TDUDIS HRTIM_CR1_TDUDIS_Msk /*!< Timer D update disable*/
AnnaBridge 171:3a7713b1edbc 9630 #define HRTIM_CR1_TEUDIS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9631 #define HRTIM_CR1_TEUDIS_Msk (0x1U << HRTIM_CR1_TEUDIS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9632 #define HRTIM_CR1_TEUDIS HRTIM_CR1_TEUDIS_Msk /*!< Timer E update disable*/
AnnaBridge 171:3a7713b1edbc 9633 #define HRTIM_CR1_ADC1USRC_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9634 #define HRTIM_CR1_ADC1USRC_Msk (0x7U << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00070000 */
AnnaBridge 171:3a7713b1edbc 9635 #define HRTIM_CR1_ADC1USRC HRTIM_CR1_ADC1USRC_Msk /*!< ADC Trigger 1 update source */
AnnaBridge 171:3a7713b1edbc 9636 #define HRTIM_CR1_ADC1USRC_0 (0x1U << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9637 #define HRTIM_CR1_ADC1USRC_1 (0x2U << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9638 #define HRTIM_CR1_ADC1USRC_2 (0x4U << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9639 #define HRTIM_CR1_ADC2USRC_Pos (19U)
AnnaBridge 171:3a7713b1edbc 9640 #define HRTIM_CR1_ADC2USRC_Msk (0x7U << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00380000 */
AnnaBridge 171:3a7713b1edbc 9641 #define HRTIM_CR1_ADC2USRC HRTIM_CR1_ADC2USRC_Msk /*!< ADC Trigger 2 update source */
AnnaBridge 171:3a7713b1edbc 9642 #define HRTIM_CR1_ADC2USRC_0 (0x1U << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 9643 #define HRTIM_CR1_ADC2USRC_1 (0x2U << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 9644 #define HRTIM_CR1_ADC2USRC_2 (0x4U << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9645 #define HRTIM_CR1_ADC3USRC_Pos (22U)
AnnaBridge 171:3a7713b1edbc 9646 #define HRTIM_CR1_ADC3USRC_Msk (0x7U << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01C00000 */
AnnaBridge 171:3a7713b1edbc 9647 #define HRTIM_CR1_ADC3USRC HRTIM_CR1_ADC3USRC_Msk /*!< ADC Trigger 3 update source */
AnnaBridge 171:3a7713b1edbc 9648 #define HRTIM_CR1_ADC3USRC_0 (0x1U << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 9649 #define HRTIM_CR1_ADC3USRC_1 (0x2U << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 9650 #define HRTIM_CR1_ADC3USRC_2 (0x4U << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 9651 #define HRTIM_CR1_ADC4USRC_Pos (25U)
AnnaBridge 171:3a7713b1edbc 9652 #define HRTIM_CR1_ADC4USRC_Msk (0x7U << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0E000000 */
AnnaBridge 171:3a7713b1edbc 9653 #define HRTIM_CR1_ADC4USRC HRTIM_CR1_ADC4USRC_Msk /*!< ADC Trigger 4 update source */
AnnaBridge 171:3a7713b1edbc 9654 #define HRTIM_CR1_ADC4USRC_0 (0x1U << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 9655 #define HRTIM_CR1_ADC4USRC_1 (0x2U << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 9656 #define HRTIM_CR1_ADC4USRC_2 (0x0U << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0800000 */
AnnaBridge 171:3a7713b1edbc 9657
AnnaBridge 171:3a7713b1edbc 9658 /**** Bit definition for Common HRTIM Timer control register 2 ****************/
AnnaBridge 171:3a7713b1edbc 9659 #define HRTIM_CR2_MSWU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9660 #define HRTIM_CR2_MSWU_Msk (0x1U << HRTIM_CR2_MSWU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9661 #define HRTIM_CR2_MSWU HRTIM_CR2_MSWU_Msk /*!< Master software update */
AnnaBridge 171:3a7713b1edbc 9662 #define HRTIM_CR2_TASWU_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9663 #define HRTIM_CR2_TASWU_Msk (0x1U << HRTIM_CR2_TASWU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9664 #define HRTIM_CR2_TASWU HRTIM_CR2_TASWU_Msk /*!< Timer A software update */
AnnaBridge 171:3a7713b1edbc 9665 #define HRTIM_CR2_TBSWU_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9666 #define HRTIM_CR2_TBSWU_Msk (0x1U << HRTIM_CR2_TBSWU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9667 #define HRTIM_CR2_TBSWU HRTIM_CR2_TBSWU_Msk /*!< Timer B software update */
AnnaBridge 171:3a7713b1edbc 9668 #define HRTIM_CR2_TCSWU_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9669 #define HRTIM_CR2_TCSWU_Msk (0x1U << HRTIM_CR2_TCSWU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9670 #define HRTIM_CR2_TCSWU HRTIM_CR2_TCSWU_Msk /*!< Timer C software update */
AnnaBridge 171:3a7713b1edbc 9671 #define HRTIM_CR2_TDSWU_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9672 #define HRTIM_CR2_TDSWU_Msk (0x1U << HRTIM_CR2_TDSWU_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9673 #define HRTIM_CR2_TDSWU HRTIM_CR2_TDSWU_Msk /*!< Timer D software update */
AnnaBridge 171:3a7713b1edbc 9674 #define HRTIM_CR2_TESWU_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9675 #define HRTIM_CR2_TESWU_Msk (0x1U << HRTIM_CR2_TESWU_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9676 #define HRTIM_CR2_TESWU HRTIM_CR2_TESWU_Msk /*!< Timer E software update */
AnnaBridge 171:3a7713b1edbc 9677 #define HRTIM_CR2_MRST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9678 #define HRTIM_CR2_MRST_Msk (0x1U << HRTIM_CR2_MRST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9679 #define HRTIM_CR2_MRST HRTIM_CR2_MRST_Msk /*!< Master count software reset */
AnnaBridge 171:3a7713b1edbc 9680 #define HRTIM_CR2_TARST_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9681 #define HRTIM_CR2_TARST_Msk (0x1U << HRTIM_CR2_TARST_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9682 #define HRTIM_CR2_TARST HRTIM_CR2_TARST_Msk /*!< Timer A count software reset */
AnnaBridge 171:3a7713b1edbc 9683 #define HRTIM_CR2_TBRST_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9684 #define HRTIM_CR2_TBRST_Msk (0x1U << HRTIM_CR2_TBRST_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9685 #define HRTIM_CR2_TBRST HRTIM_CR2_TBRST_Msk /*!< Timer B count software reset */
AnnaBridge 171:3a7713b1edbc 9686 #define HRTIM_CR2_TCRST_Pos (11U)
AnnaBridge 171:3a7713b1edbc 9687 #define HRTIM_CR2_TCRST_Msk (0x1U << HRTIM_CR2_TCRST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9688 #define HRTIM_CR2_TCRST HRTIM_CR2_TCRST_Msk /*!< Timer C count software reset */
AnnaBridge 171:3a7713b1edbc 9689 #define HRTIM_CR2_TDRST_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9690 #define HRTIM_CR2_TDRST_Msk (0x1U << HRTIM_CR2_TDRST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9691 #define HRTIM_CR2_TDRST HRTIM_CR2_TDRST_Msk /*!< Timer D count software reset */
AnnaBridge 171:3a7713b1edbc 9692 #define HRTIM_CR2_TERST_Pos (13U)
AnnaBridge 171:3a7713b1edbc 9693 #define HRTIM_CR2_TERST_Msk (0x1U << HRTIM_CR2_TERST_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9694 #define HRTIM_CR2_TERST HRTIM_CR2_TERST_Msk /*!< Timer E count software reset */
AnnaBridge 171:3a7713b1edbc 9695
AnnaBridge 171:3a7713b1edbc 9696 /**** Bit definition for Common HRTIM Timer interrupt status register *********/
AnnaBridge 171:3a7713b1edbc 9697 #define HRTIM_ISR_FLT1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9698 #define HRTIM_ISR_FLT1_Msk (0x1U << HRTIM_ISR_FLT1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9699 #define HRTIM_ISR_FLT1 HRTIM_ISR_FLT1_Msk /*!< Fault 1 interrupt flag */
AnnaBridge 171:3a7713b1edbc 9700 #define HRTIM_ISR_FLT2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9701 #define HRTIM_ISR_FLT2_Msk (0x1U << HRTIM_ISR_FLT2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9702 #define HRTIM_ISR_FLT2 HRTIM_ISR_FLT2_Msk /*!< Fault 2 interrupt flag */
AnnaBridge 171:3a7713b1edbc 9703 #define HRTIM_ISR_FLT3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9704 #define HRTIM_ISR_FLT3_Msk (0x1U << HRTIM_ISR_FLT3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9705 #define HRTIM_ISR_FLT3 HRTIM_ISR_FLT3_Msk /*!< Fault 3 interrupt flag */
AnnaBridge 171:3a7713b1edbc 9706 #define HRTIM_ISR_FLT4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9707 #define HRTIM_ISR_FLT4_Msk (0x1U << HRTIM_ISR_FLT4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9708 #define HRTIM_ISR_FLT4 HRTIM_ISR_FLT4_Msk /*!< Fault 4 interrupt flag */
AnnaBridge 171:3a7713b1edbc 9709 #define HRTIM_ISR_FLT5_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9710 #define HRTIM_ISR_FLT5_Msk (0x1U << HRTIM_ISR_FLT5_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9711 #define HRTIM_ISR_FLT5 HRTIM_ISR_FLT5_Msk /*!< Fault 5 interrupt flag */
AnnaBridge 171:3a7713b1edbc 9712 #define HRTIM_ISR_SYSFLT_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9713 #define HRTIM_ISR_SYSFLT_Msk (0x1U << HRTIM_ISR_SYSFLT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9714 #define HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT_Msk /*!< System Fault interrupt flag */
AnnaBridge 171:3a7713b1edbc 9715 #define HRTIM_ISR_DLLRDY_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9716 #define HRTIM_ISR_DLLRDY_Msk (0x1U << HRTIM_ISR_DLLRDY_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9717 #define HRTIM_ISR_DLLRDY HRTIM_ISR_DLLRDY_Msk /*!< DLL ready interrupt flag */
AnnaBridge 171:3a7713b1edbc 9718 #define HRTIM_ISR_BMPER_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9719 #define HRTIM_ISR_BMPER_Msk (0x1U << HRTIM_ISR_BMPER_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9720 #define HRTIM_ISR_BMPER HRTIM_ISR_BMPER_Msk /*!< Burst mode period interrupt flag */
AnnaBridge 171:3a7713b1edbc 9721
AnnaBridge 171:3a7713b1edbc 9722 /**** Bit definition for Common HRTIM Timer interrupt clear register **********/
AnnaBridge 171:3a7713b1edbc 9723 #define HRTIM_ICR_FLT1C_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9724 #define HRTIM_ICR_FLT1C_Msk (0x1U << HRTIM_ICR_FLT1C_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9725 #define HRTIM_ICR_FLT1C HRTIM_ICR_FLT1C_Msk /*!< Fault 1 interrupt flag clear */
AnnaBridge 171:3a7713b1edbc 9726 #define HRTIM_ICR_FLT2C_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9727 #define HRTIM_ICR_FLT2C_Msk (0x1U << HRTIM_ICR_FLT2C_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9728 #define HRTIM_ICR_FLT2C HRTIM_ICR_FLT2C_Msk /*!< Fault 2 interrupt flag clear */
AnnaBridge 171:3a7713b1edbc 9729 #define HRTIM_ICR_FLT3C_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9730 #define HRTIM_ICR_FLT3C_Msk (0x1U << HRTIM_ICR_FLT3C_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9731 #define HRTIM_ICR_FLT3C HRTIM_ICR_FLT3C_Msk /*!< Fault 3 interrupt flag clear */
AnnaBridge 171:3a7713b1edbc 9732 #define HRTIM_ICR_FLT4C_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9733 #define HRTIM_ICR_FLT4C_Msk (0x1U << HRTIM_ICR_FLT4C_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9734 #define HRTIM_ICR_FLT4C HRTIM_ICR_FLT4C_Msk /*!< Fault 4 interrupt flag clear */
AnnaBridge 171:3a7713b1edbc 9735 #define HRTIM_ICR_FLT5C_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9736 #define HRTIM_ICR_FLT5C_Msk (0x1U << HRTIM_ICR_FLT5C_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9737 #define HRTIM_ICR_FLT5C HRTIM_ICR_FLT5C_Msk /*!< Fault 5 interrupt flag clear */
AnnaBridge 171:3a7713b1edbc 9738 #define HRTIM_ICR_SYSFLTC_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9739 #define HRTIM_ICR_SYSFLTC_Msk (0x1U << HRTIM_ICR_SYSFLTC_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9740 #define HRTIM_ICR_SYSFLTC HRTIM_ICR_SYSFLTC_Msk /*!< System Fault interrupt flag clear */
AnnaBridge 171:3a7713b1edbc 9741 #define HRTIM_ICR_DLLRDYC_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9742 #define HRTIM_ICR_DLLRDYC_Msk (0x1U << HRTIM_ICR_DLLRDYC_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9743 #define HRTIM_ICR_DLLRDYC HRTIM_ICR_DLLRDYC_Msk /*!< DLL ready interrupt flag clear */
AnnaBridge 171:3a7713b1edbc 9744 #define HRTIM_ICR_BMPERC_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9745 #define HRTIM_ICR_BMPERC_Msk (0x1U << HRTIM_ICR_BMPERC_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9746 #define HRTIM_ICR_BMPERC HRTIM_ICR_BMPERC_Msk /*!< Burst mode period interrupt flag clear */
AnnaBridge 171:3a7713b1edbc 9747
AnnaBridge 171:3a7713b1edbc 9748 /**** Bit definition for Common HRTIM Timer interrupt enable register *********/
AnnaBridge 171:3a7713b1edbc 9749 #define HRTIM_IER_FLT1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9750 #define HRTIM_IER_FLT1_Msk (0x1U << HRTIM_IER_FLT1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9751 #define HRTIM_IER_FLT1 HRTIM_IER_FLT1_Msk /*!< Fault 1 interrupt enable */
AnnaBridge 171:3a7713b1edbc 9752 #define HRTIM_IER_FLT2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9753 #define HRTIM_IER_FLT2_Msk (0x1U << HRTIM_IER_FLT2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9754 #define HRTIM_IER_FLT2 HRTIM_IER_FLT2_Msk /*!< Fault 2 interrupt enable */
AnnaBridge 171:3a7713b1edbc 9755 #define HRTIM_IER_FLT3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9756 #define HRTIM_IER_FLT3_Msk (0x1U << HRTIM_IER_FLT3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9757 #define HRTIM_IER_FLT3 HRTIM_IER_FLT3_Msk /*!< Fault 3 interrupt enable */
AnnaBridge 171:3a7713b1edbc 9758 #define HRTIM_IER_FLT4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9759 #define HRTIM_IER_FLT4_Msk (0x1U << HRTIM_IER_FLT4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9760 #define HRTIM_IER_FLT4 HRTIM_IER_FLT4_Msk /*!< Fault 4 interrupt enable */
AnnaBridge 171:3a7713b1edbc 9761 #define HRTIM_IER_FLT5_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9762 #define HRTIM_IER_FLT5_Msk (0x1U << HRTIM_IER_FLT5_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9763 #define HRTIM_IER_FLT5 HRTIM_IER_FLT5_Msk /*!< Fault 5 interrupt enable */
AnnaBridge 171:3a7713b1edbc 9764 #define HRTIM_IER_SYSFLT_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9765 #define HRTIM_IER_SYSFLT_Msk (0x1U << HRTIM_IER_SYSFLT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9766 #define HRTIM_IER_SYSFLT HRTIM_IER_SYSFLT_Msk /*!< System Fault interrupt enable */
AnnaBridge 171:3a7713b1edbc 9767 #define HRTIM_IER_DLLRDY_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9768 #define HRTIM_IER_DLLRDY_Msk (0x1U << HRTIM_IER_DLLRDY_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9769 #define HRTIM_IER_DLLRDY HRTIM_IER_DLLRDY_Msk /*!< DLL ready interrupt enable */
AnnaBridge 171:3a7713b1edbc 9770 #define HRTIM_IER_BMPER_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9771 #define HRTIM_IER_BMPER_Msk (0x1U << HRTIM_IER_BMPER_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9772 #define HRTIM_IER_BMPER HRTIM_IER_BMPER_Msk /*!< Burst mode period interrupt enable */
AnnaBridge 171:3a7713b1edbc 9773
AnnaBridge 171:3a7713b1edbc 9774 /**** Bit definition for Common HRTIM Timer output enable register ************/
AnnaBridge 171:3a7713b1edbc 9775 #define HRTIM_OENR_TA1OEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9776 #define HRTIM_OENR_TA1OEN_Msk (0x1U << HRTIM_OENR_TA1OEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9777 #define HRTIM_OENR_TA1OEN HRTIM_OENR_TA1OEN_Msk /*!< Timer A Output 1 enable */
AnnaBridge 171:3a7713b1edbc 9778 #define HRTIM_OENR_TA2OEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9779 #define HRTIM_OENR_TA2OEN_Msk (0x1U << HRTIM_OENR_TA2OEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9780 #define HRTIM_OENR_TA2OEN HRTIM_OENR_TA2OEN_Msk /*!< Timer A Output 2 enable */
AnnaBridge 171:3a7713b1edbc 9781 #define HRTIM_OENR_TB1OEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9782 #define HRTIM_OENR_TB1OEN_Msk (0x1U << HRTIM_OENR_TB1OEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9783 #define HRTIM_OENR_TB1OEN HRTIM_OENR_TB1OEN_Msk /*!< Timer B Output 1 enable */
AnnaBridge 171:3a7713b1edbc 9784 #define HRTIM_OENR_TB2OEN_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9785 #define HRTIM_OENR_TB2OEN_Msk (0x1U << HRTIM_OENR_TB2OEN_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9786 #define HRTIM_OENR_TB2OEN HRTIM_OENR_TB2OEN_Msk /*!< Timer B Output 2 enable */
AnnaBridge 171:3a7713b1edbc 9787 #define HRTIM_OENR_TC1OEN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9788 #define HRTIM_OENR_TC1OEN_Msk (0x1U << HRTIM_OENR_TC1OEN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9789 #define HRTIM_OENR_TC1OEN HRTIM_OENR_TC1OEN_Msk /*!< Timer C Output 1 enable */
AnnaBridge 171:3a7713b1edbc 9790 #define HRTIM_OENR_TC2OEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9791 #define HRTIM_OENR_TC2OEN_Msk (0x1U << HRTIM_OENR_TC2OEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9792 #define HRTIM_OENR_TC2OEN HRTIM_OENR_TC2OEN_Msk /*!< Timer C Output 2 enable */
AnnaBridge 171:3a7713b1edbc 9793 #define HRTIM_OENR_TD1OEN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9794 #define HRTIM_OENR_TD1OEN_Msk (0x1U << HRTIM_OENR_TD1OEN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9795 #define HRTIM_OENR_TD1OEN HRTIM_OENR_TD1OEN_Msk /*!< Timer D Output 1 enable */
AnnaBridge 171:3a7713b1edbc 9796 #define HRTIM_OENR_TD2OEN_Pos (7U)
AnnaBridge 171:3a7713b1edbc 9797 #define HRTIM_OENR_TD2OEN_Msk (0x1U << HRTIM_OENR_TD2OEN_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9798 #define HRTIM_OENR_TD2OEN HRTIM_OENR_TD2OEN_Msk /*!< Timer D Output 2 enable */
AnnaBridge 171:3a7713b1edbc 9799 #define HRTIM_OENR_TE1OEN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9800 #define HRTIM_OENR_TE1OEN_Msk (0x1U << HRTIM_OENR_TE1OEN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9801 #define HRTIM_OENR_TE1OEN HRTIM_OENR_TE1OEN_Msk /*!< Timer E Output 1 enable */
AnnaBridge 171:3a7713b1edbc 9802 #define HRTIM_OENR_TE2OEN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9803 #define HRTIM_OENR_TE2OEN_Msk (0x1U << HRTIM_OENR_TE2OEN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9804 #define HRTIM_OENR_TE2OEN HRTIM_OENR_TE2OEN_Msk /*!< Timer E Output 2 enable */
AnnaBridge 171:3a7713b1edbc 9805
AnnaBridge 171:3a7713b1edbc 9806 /**** Bit definition for Common HRTIM Timer output disable register ***********/
AnnaBridge 171:3a7713b1edbc 9807 #define HRTIM_ODISR_TA1ODIS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9808 #define HRTIM_ODISR_TA1ODIS_Msk (0x1U << HRTIM_ODISR_TA1ODIS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9809 #define HRTIM_ODISR_TA1ODIS HRTIM_ODISR_TA1ODIS_Msk /*!< Timer A Output 1 disable */
AnnaBridge 171:3a7713b1edbc 9810 #define HRTIM_ODISR_TA2ODIS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9811 #define HRTIM_ODISR_TA2ODIS_Msk (0x1U << HRTIM_ODISR_TA2ODIS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9812 #define HRTIM_ODISR_TA2ODIS HRTIM_ODISR_TA2ODIS_Msk /*!< Timer A Output 2 disable */
AnnaBridge 171:3a7713b1edbc 9813 #define HRTIM_ODISR_TB1ODIS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9814 #define HRTIM_ODISR_TB1ODIS_Msk (0x1U << HRTIM_ODISR_TB1ODIS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9815 #define HRTIM_ODISR_TB1ODIS HRTIM_ODISR_TB1ODIS_Msk /*!< Timer B Output 1 disable */
AnnaBridge 171:3a7713b1edbc 9816 #define HRTIM_ODISR_TB2ODIS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9817 #define HRTIM_ODISR_TB2ODIS_Msk (0x1U << HRTIM_ODISR_TB2ODIS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9818 #define HRTIM_ODISR_TB2ODIS HRTIM_ODISR_TB2ODIS_Msk /*!< Timer B Output 2 disable */
AnnaBridge 171:3a7713b1edbc 9819 #define HRTIM_ODISR_TC1ODIS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9820 #define HRTIM_ODISR_TC1ODIS_Msk (0x1U << HRTIM_ODISR_TC1ODIS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9821 #define HRTIM_ODISR_TC1ODIS HRTIM_ODISR_TC1ODIS_Msk /*!< Timer C Output 1 disable */
AnnaBridge 171:3a7713b1edbc 9822 #define HRTIM_ODISR_TC2ODIS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9823 #define HRTIM_ODISR_TC2ODIS_Msk (0x1U << HRTIM_ODISR_TC2ODIS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9824 #define HRTIM_ODISR_TC2ODIS HRTIM_ODISR_TC2ODIS_Msk /*!< Timer C Output 2 disable */
AnnaBridge 171:3a7713b1edbc 9825 #define HRTIM_ODISR_TD1ODIS_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9826 #define HRTIM_ODISR_TD1ODIS_Msk (0x1U << HRTIM_ODISR_TD1ODIS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9827 #define HRTIM_ODISR_TD1ODIS HRTIM_ODISR_TD1ODIS_Msk /*!< Timer D Output 1 disable */
AnnaBridge 171:3a7713b1edbc 9828 #define HRTIM_ODISR_TD2ODIS_Pos (7U)
AnnaBridge 171:3a7713b1edbc 9829 #define HRTIM_ODISR_TD2ODIS_Msk (0x1U << HRTIM_ODISR_TD2ODIS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9830 #define HRTIM_ODISR_TD2ODIS HRTIM_ODISR_TD2ODIS_Msk /*!< Timer D Output 2 disable */
AnnaBridge 171:3a7713b1edbc 9831 #define HRTIM_ODISR_TE1ODIS_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9832 #define HRTIM_ODISR_TE1ODIS_Msk (0x1U << HRTIM_ODISR_TE1ODIS_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9833 #define HRTIM_ODISR_TE1ODIS HRTIM_ODISR_TE1ODIS_Msk /*!< Timer E Output 1 disable */
AnnaBridge 171:3a7713b1edbc 9834 #define HRTIM_ODISR_TE2ODIS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9835 #define HRTIM_ODISR_TE2ODIS_Msk (0x1U << HRTIM_ODISR_TE2ODIS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9836 #define HRTIM_ODISR_TE2ODIS HRTIM_ODISR_TE2ODIS_Msk /*!< Timer E Output 2 disable */
AnnaBridge 171:3a7713b1edbc 9837
AnnaBridge 171:3a7713b1edbc 9838 /**** Bit definition for Common HRTIM Timer output disable status register *****/
AnnaBridge 171:3a7713b1edbc 9839 #define HRTIM_ODSR_TA1ODS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9840 #define HRTIM_ODSR_TA1ODS_Msk (0x1U << HRTIM_ODSR_TA1ODS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9841 #define HRTIM_ODSR_TA1ODS HRTIM_ODSR_TA1ODS_Msk /*!< Timer A Output 1 disable status */
AnnaBridge 171:3a7713b1edbc 9842 #define HRTIM_ODSR_TA2ODS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9843 #define HRTIM_ODSR_TA2ODS_Msk (0x1U << HRTIM_ODSR_TA2ODS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9844 #define HRTIM_ODSR_TA2ODS HRTIM_ODSR_TA2ODS_Msk /*!< Timer A Output 2 disable status */
AnnaBridge 171:3a7713b1edbc 9845 #define HRTIM_ODSR_TB1ODS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9846 #define HRTIM_ODSR_TB1ODS_Msk (0x1U << HRTIM_ODSR_TB1ODS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9847 #define HRTIM_ODSR_TB1ODS HRTIM_ODSR_TB1ODS_Msk /*!< Timer B Output 1 disable status */
AnnaBridge 171:3a7713b1edbc 9848 #define HRTIM_ODSR_TB2ODS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9849 #define HRTIM_ODSR_TB2ODS_Msk (0x1U << HRTIM_ODSR_TB2ODS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9850 #define HRTIM_ODSR_TB2ODS HRTIM_ODSR_TB2ODS_Msk /*!< Timer B Output 2 disable status */
AnnaBridge 171:3a7713b1edbc 9851 #define HRTIM_ODSR_TC1ODS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9852 #define HRTIM_ODSR_TC1ODS_Msk (0x1U << HRTIM_ODSR_TC1ODS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9853 #define HRTIM_ODSR_TC1ODS HRTIM_ODSR_TC1ODS_Msk /*!< Timer C Output 1 disable status */
AnnaBridge 171:3a7713b1edbc 9854 #define HRTIM_ODSR_TC2ODS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9855 #define HRTIM_ODSR_TC2ODS_Msk (0x1U << HRTIM_ODSR_TC2ODS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9856 #define HRTIM_ODSR_TC2ODS HRTIM_ODSR_TC2ODS_Msk /*!< Timer C Output 2 disable status */
AnnaBridge 171:3a7713b1edbc 9857 #define HRTIM_ODSR_TD1ODS_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9858 #define HRTIM_ODSR_TD1ODS_Msk (0x1U << HRTIM_ODSR_TD1ODS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9859 #define HRTIM_ODSR_TD1ODS HRTIM_ODSR_TD1ODS_Msk /*!< Timer D Output 1 disable status */
AnnaBridge 171:3a7713b1edbc 9860 #define HRTIM_ODSR_TD2ODS_Pos (7U)
AnnaBridge 171:3a7713b1edbc 9861 #define HRTIM_ODSR_TD2ODS_Msk (0x1U << HRTIM_ODSR_TD2ODS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9862 #define HRTIM_ODSR_TD2ODS HRTIM_ODSR_TD2ODS_Msk /*!< Timer D Output 2 disable status */
AnnaBridge 171:3a7713b1edbc 9863 #define HRTIM_ODSR_TE1ODS_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9864 #define HRTIM_ODSR_TE1ODS_Msk (0x1U << HRTIM_ODSR_TE1ODS_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9865 #define HRTIM_ODSR_TE1ODS HRTIM_ODSR_TE1ODS_Msk /*!< Timer E Output 1 disable status */
AnnaBridge 171:3a7713b1edbc 9866 #define HRTIM_ODSR_TE2ODS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9867 #define HRTIM_ODSR_TE2ODS_Msk (0x1U << HRTIM_ODSR_TE2ODS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9868 #define HRTIM_ODSR_TE2ODS HRTIM_ODSR_TE2ODS_Msk /*!< Timer E Output 2 disable status */
AnnaBridge 171:3a7713b1edbc 9869
AnnaBridge 171:3a7713b1edbc 9870 /**** Bit definition for Common HRTIM Timer Burst mode control register ********/
AnnaBridge 171:3a7713b1edbc 9871 #define HRTIM_BMCR_BME_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9872 #define HRTIM_BMCR_BME_Msk (0x1U << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9873 #define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */
AnnaBridge 171:3a7713b1edbc 9874 #define HRTIM_BMCR_BMOM_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9875 #define HRTIM_BMCR_BMOM_Msk (0x1U << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9876 #define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */
AnnaBridge 171:3a7713b1edbc 9877 #define HRTIM_BMCR_BMCLK_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9878 #define HRTIM_BMCR_BMCLK_Msk (0xFU << HRTIM_BMCR_BMCLK_Pos) /*!< 0x0000003C */
AnnaBridge 171:3a7713b1edbc 9879 #define HRTIM_BMCR_BMCLK HRTIM_BMCR_BMCLK_Msk /*!< Burst mode clock source */
AnnaBridge 171:3a7713b1edbc 9880 #define HRTIM_BMCR_BMCLK_0 (0x1U << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9881 #define HRTIM_BMCR_BMCLK_1 (0x2U << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9882 #define HRTIM_BMCR_BMCLK_2 (0x4U << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9883 #define HRTIM_BMCR_BMCLK_3 (0x8U << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9884 #define HRTIM_BMCR_BMPRSC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9885 #define HRTIM_BMCR_BMPRSC_Msk (0xFU << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x000003C0 */
AnnaBridge 171:3a7713b1edbc 9886 #define HRTIM_BMCR_BMPRSC HRTIM_BMCR_BMPRSC_Msk /*!< Burst mode prescaler */
AnnaBridge 171:3a7713b1edbc 9887 #define HRTIM_BMCR_BMPRSC_0 (0x1U << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9888 #define HRTIM_BMCR_BMPRSC_1 (0x2U << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9889 #define HRTIM_BMCR_BMPRSC_2 (0x4U << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9890 #define HRTIM_BMCR_BMPRSC_3 (0x8U << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9891 #define HRTIM_BMCR_BMPREN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9892 #define HRTIM_BMCR_BMPREN_Msk (0x1U << HRTIM_BMCR_BMPREN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9893 #define HRTIM_BMCR_BMPREN HRTIM_BMCR_BMPREN_Msk /*!< Burst mode Preload bit */
AnnaBridge 171:3a7713b1edbc 9894 #define HRTIM_BMCR_MTBM_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9895 #define HRTIM_BMCR_MTBM_Msk (0x1U << HRTIM_BMCR_MTBM_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9896 #define HRTIM_BMCR_MTBM HRTIM_BMCR_MTBM_Msk /*!< Master Timer Burst mode */
AnnaBridge 171:3a7713b1edbc 9897 #define HRTIM_BMCR_TABM_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9898 #define HRTIM_BMCR_TABM_Msk (0x1U << HRTIM_BMCR_TABM_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9899 #define HRTIM_BMCR_TABM HRTIM_BMCR_TABM_Msk /*!< Timer A Burst mode */
AnnaBridge 171:3a7713b1edbc 9900 #define HRTIM_BMCR_TBBM_Pos (18U)
AnnaBridge 171:3a7713b1edbc 9901 #define HRTIM_BMCR_TBBM_Msk (0x1U << HRTIM_BMCR_TBBM_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9902 #define HRTIM_BMCR_TBBM HRTIM_BMCR_TBBM_Msk /*!< Timer B Burst mode */
AnnaBridge 171:3a7713b1edbc 9903 #define HRTIM_BMCR_TCBM_Pos (19U)
AnnaBridge 171:3a7713b1edbc 9904 #define HRTIM_BMCR_TCBM_Msk (0x1U << HRTIM_BMCR_TCBM_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 9905 #define HRTIM_BMCR_TCBM HRTIM_BMCR_TCBM_Msk /*!< Timer C Burst mode */
AnnaBridge 171:3a7713b1edbc 9906 #define HRTIM_BMCR_TDBM_Pos (20U)
AnnaBridge 171:3a7713b1edbc 9907 #define HRTIM_BMCR_TDBM_Msk (0x1U << HRTIM_BMCR_TDBM_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 9908 #define HRTIM_BMCR_TDBM HRTIM_BMCR_TDBM_Msk /*!< Timer D Burst mode */
AnnaBridge 171:3a7713b1edbc 9909 #define HRTIM_BMCR_TEBM_Pos (21U)
AnnaBridge 171:3a7713b1edbc 9910 #define HRTIM_BMCR_TEBM_Msk (0x1U << HRTIM_BMCR_TEBM_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9911 #define HRTIM_BMCR_TEBM HRTIM_BMCR_TEBM_Msk /*!< Timer E Burst mode */
AnnaBridge 171:3a7713b1edbc 9912 #define HRTIM_BMCR_BMSTAT_Pos (31U)
AnnaBridge 171:3a7713b1edbc 9913 #define HRTIM_BMCR_BMSTAT_Msk (0x1U << HRTIM_BMCR_BMSTAT_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 9914 #define HRTIM_BMCR_BMSTAT HRTIM_BMCR_BMSTAT_Msk /*!< Burst mode status */
AnnaBridge 171:3a7713b1edbc 9915
AnnaBridge 171:3a7713b1edbc 9916 /**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
AnnaBridge 171:3a7713b1edbc 9917 #define HRTIM_BMTRGR_SW_Pos (0U)
AnnaBridge 171:3a7713b1edbc 9918 #define HRTIM_BMTRGR_SW_Msk (0x1U << HRTIM_BMTRGR_SW_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 9919 #define HRTIM_BMTRGR_SW HRTIM_BMTRGR_SW_Msk /*!< Software start */
AnnaBridge 171:3a7713b1edbc 9920 #define HRTIM_BMTRGR_MSTRST_Pos (1U)
AnnaBridge 171:3a7713b1edbc 9921 #define HRTIM_BMTRGR_MSTRST_Msk (0x1U << HRTIM_BMTRGR_MSTRST_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 9922 #define HRTIM_BMTRGR_MSTRST HRTIM_BMTRGR_MSTRST_Msk /*!< Master reset */
AnnaBridge 171:3a7713b1edbc 9923 #define HRTIM_BMTRGR_MSTREP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 9924 #define HRTIM_BMTRGR_MSTREP_Msk (0x1U << HRTIM_BMTRGR_MSTREP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 9925 #define HRTIM_BMTRGR_MSTREP HRTIM_BMTRGR_MSTREP_Msk /*!< Master repetition */
AnnaBridge 171:3a7713b1edbc 9926 #define HRTIM_BMTRGR_MSTCMP1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 9927 #define HRTIM_BMTRGR_MSTCMP1_Msk (0x1U << HRTIM_BMTRGR_MSTCMP1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 9928 #define HRTIM_BMTRGR_MSTCMP1 HRTIM_BMTRGR_MSTCMP1_Msk /*!< Master compare 1 */
AnnaBridge 171:3a7713b1edbc 9929 #define HRTIM_BMTRGR_MSTCMP2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 9930 #define HRTIM_BMTRGR_MSTCMP2_Msk (0x1U << HRTIM_BMTRGR_MSTCMP2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 9931 #define HRTIM_BMTRGR_MSTCMP2 HRTIM_BMTRGR_MSTCMP2_Msk /*!< Master compare 2 */
AnnaBridge 171:3a7713b1edbc 9932 #define HRTIM_BMTRGR_MSTCMP3_Pos (5U)
AnnaBridge 171:3a7713b1edbc 9933 #define HRTIM_BMTRGR_MSTCMP3_Msk (0x1U << HRTIM_BMTRGR_MSTCMP3_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 9934 #define HRTIM_BMTRGR_MSTCMP3 HRTIM_BMTRGR_MSTCMP3_Msk /*!< Master compare 3 */
AnnaBridge 171:3a7713b1edbc 9935 #define HRTIM_BMTRGR_MSTCMP4_Pos (6U)
AnnaBridge 171:3a7713b1edbc 9936 #define HRTIM_BMTRGR_MSTCMP4_Msk (0x1U << HRTIM_BMTRGR_MSTCMP4_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 9937 #define HRTIM_BMTRGR_MSTCMP4 HRTIM_BMTRGR_MSTCMP4_Msk /*!< Master compare 4 */
AnnaBridge 171:3a7713b1edbc 9938 #define HRTIM_BMTRGR_TARST_Pos (7U)
AnnaBridge 171:3a7713b1edbc 9939 #define HRTIM_BMTRGR_TARST_Msk (0x1U << HRTIM_BMTRGR_TARST_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 9940 #define HRTIM_BMTRGR_TARST HRTIM_BMTRGR_TARST_Msk /*!< Timer A reset */
AnnaBridge 171:3a7713b1edbc 9941 #define HRTIM_BMTRGR_TAREP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 9942 #define HRTIM_BMTRGR_TAREP_Msk (0x1U << HRTIM_BMTRGR_TAREP_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 9943 #define HRTIM_BMTRGR_TAREP HRTIM_BMTRGR_TAREP_Msk /*!< Timer A repetition */
AnnaBridge 171:3a7713b1edbc 9944 #define HRTIM_BMTRGR_TACMP1_Pos (9U)
AnnaBridge 171:3a7713b1edbc 9945 #define HRTIM_BMTRGR_TACMP1_Msk (0x1U << HRTIM_BMTRGR_TACMP1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 9946 #define HRTIM_BMTRGR_TACMP1 HRTIM_BMTRGR_TACMP1_Msk /*!< Timer A compare 1 */
AnnaBridge 171:3a7713b1edbc 9947 #define HRTIM_BMTRGR_TACMP2_Pos (10U)
AnnaBridge 171:3a7713b1edbc 9948 #define HRTIM_BMTRGR_TACMP2_Msk (0x1U << HRTIM_BMTRGR_TACMP2_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 9949 #define HRTIM_BMTRGR_TACMP2 HRTIM_BMTRGR_TACMP2_Msk /*!< Timer A compare 2 */
AnnaBridge 171:3a7713b1edbc 9950 #define HRTIM_BMTRGR_TBRST_Pos (11U)
AnnaBridge 171:3a7713b1edbc 9951 #define HRTIM_BMTRGR_TBRST_Msk (0x1U << HRTIM_BMTRGR_TBRST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 9952 #define HRTIM_BMTRGR_TBRST HRTIM_BMTRGR_TBRST_Msk /*!< Timer B reset */
AnnaBridge 171:3a7713b1edbc 9953 #define HRTIM_BMTRGR_TBREP_Pos (12U)
AnnaBridge 171:3a7713b1edbc 9954 #define HRTIM_BMTRGR_TBREP_Msk (0x1U << HRTIM_BMTRGR_TBREP_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 9955 #define HRTIM_BMTRGR_TBREP HRTIM_BMTRGR_TBREP_Msk /*!< Timer B repetition */
AnnaBridge 171:3a7713b1edbc 9956 #define HRTIM_BMTRGR_TBCMP1_Pos (13U)
AnnaBridge 171:3a7713b1edbc 9957 #define HRTIM_BMTRGR_TBCMP1_Msk (0x1U << HRTIM_BMTRGR_TBCMP1_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 9958 #define HRTIM_BMTRGR_TBCMP1 HRTIM_BMTRGR_TBCMP1_Msk /*!< Timer B compare 1 */
AnnaBridge 171:3a7713b1edbc 9959 #define HRTIM_BMTRGR_TBCMP2_Pos (14U)
AnnaBridge 171:3a7713b1edbc 9960 #define HRTIM_BMTRGR_TBCMP2_Msk (0x1U << HRTIM_BMTRGR_TBCMP2_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 9961 #define HRTIM_BMTRGR_TBCMP2 HRTIM_BMTRGR_TBCMP2_Msk /*!< Timer B compare 2 */
AnnaBridge 171:3a7713b1edbc 9962 #define HRTIM_BMTRGR_TCRST_Pos (15U)
AnnaBridge 171:3a7713b1edbc 9963 #define HRTIM_BMTRGR_TCRST_Msk (0x1U << HRTIM_BMTRGR_TCRST_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 9964 #define HRTIM_BMTRGR_TCRST HRTIM_BMTRGR_TCRST_Msk /*!< Timer C reset */
AnnaBridge 171:3a7713b1edbc 9965 #define HRTIM_BMTRGR_TCREP_Pos (16U)
AnnaBridge 171:3a7713b1edbc 9966 #define HRTIM_BMTRGR_TCREP_Msk (0x1U << HRTIM_BMTRGR_TCREP_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 9967 #define HRTIM_BMTRGR_TCREP HRTIM_BMTRGR_TCREP_Msk /*!< Timer C repetition */
AnnaBridge 171:3a7713b1edbc 9968 #define HRTIM_BMTRGR_TCCMP1_Pos (17U)
AnnaBridge 171:3a7713b1edbc 9969 #define HRTIM_BMTRGR_TCCMP1_Msk (0x1U << HRTIM_BMTRGR_TCCMP1_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 9970 #define HRTIM_BMTRGR_TCCMP1 HRTIM_BMTRGR_TCCMP1_Msk /*!< Timer C compare 1 */
AnnaBridge 171:3a7713b1edbc 9971 #define HRTIM_BMTRGR_TCCMP2_Pos (18U)
AnnaBridge 171:3a7713b1edbc 9972 #define HRTIM_BMTRGR_TCCMP2_Msk (0x1U << HRTIM_BMTRGR_TCCMP2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 9973 #define HRTIM_BMTRGR_TCCMP2 HRTIM_BMTRGR_TCCMP2_Msk /*!< Timer C compare 2 */
AnnaBridge 171:3a7713b1edbc 9974 #define HRTIM_BMTRGR_TDRST_Pos (19U)
AnnaBridge 171:3a7713b1edbc 9975 #define HRTIM_BMTRGR_TDRST_Msk (0x1U << HRTIM_BMTRGR_TDRST_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 9976 #define HRTIM_BMTRGR_TDRST HRTIM_BMTRGR_TDRST_Msk /*!< Timer D reset */
AnnaBridge 171:3a7713b1edbc 9977 #define HRTIM_BMTRGR_TDREP_Pos (20U)
AnnaBridge 171:3a7713b1edbc 9978 #define HRTIM_BMTRGR_TDREP_Msk (0x1U << HRTIM_BMTRGR_TDREP_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 9979 #define HRTIM_BMTRGR_TDREP HRTIM_BMTRGR_TDREP_Msk /*!< Timer D repetition */
AnnaBridge 171:3a7713b1edbc 9980 #define HRTIM_BMTRGR_TDCMP1_Pos (21U)
AnnaBridge 171:3a7713b1edbc 9981 #define HRTIM_BMTRGR_TDCMP1_Msk (0x1U << HRTIM_BMTRGR_TDCMP1_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 9982 #define HRTIM_BMTRGR_TDCMP1 HRTIM_BMTRGR_TDCMP1_Msk /*!< Timer D compare 1 */
AnnaBridge 171:3a7713b1edbc 9983 #define HRTIM_BMTRGR_TDCMP2_Pos (22U)
AnnaBridge 171:3a7713b1edbc 9984 #define HRTIM_BMTRGR_TDCMP2_Msk (0x1U << HRTIM_BMTRGR_TDCMP2_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 9985 #define HRTIM_BMTRGR_TDCMP2 HRTIM_BMTRGR_TDCMP2_Msk /*!< Timer D compare 2 */
AnnaBridge 171:3a7713b1edbc 9986 #define HRTIM_BMTRGR_TERST_Pos (23U)
AnnaBridge 171:3a7713b1edbc 9987 #define HRTIM_BMTRGR_TERST_Msk (0x1U << HRTIM_BMTRGR_TERST_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 9988 #define HRTIM_BMTRGR_TERST HRTIM_BMTRGR_TERST_Msk /*!< Timer E reset */
AnnaBridge 171:3a7713b1edbc 9989 #define HRTIM_BMTRGR_TEREP_Pos (24U)
AnnaBridge 171:3a7713b1edbc 9990 #define HRTIM_BMTRGR_TEREP_Msk (0x1U << HRTIM_BMTRGR_TEREP_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 9991 #define HRTIM_BMTRGR_TEREP HRTIM_BMTRGR_TEREP_Msk /*!< Timer E repetition */
AnnaBridge 171:3a7713b1edbc 9992 #define HRTIM_BMTRGR_TECMP1_Pos (25U)
AnnaBridge 171:3a7713b1edbc 9993 #define HRTIM_BMTRGR_TECMP1_Msk (0x1U << HRTIM_BMTRGR_TECMP1_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 9994 #define HRTIM_BMTRGR_TECMP1 HRTIM_BMTRGR_TECMP1_Msk /*!< Timer E compare 1 */
AnnaBridge 171:3a7713b1edbc 9995 #define HRTIM_BMTRGR_TECMP2_Pos (26U)
AnnaBridge 171:3a7713b1edbc 9996 #define HRTIM_BMTRGR_TECMP2_Msk (0x1U << HRTIM_BMTRGR_TECMP2_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 9997 #define HRTIM_BMTRGR_TECMP2 HRTIM_BMTRGR_TECMP2_Msk /*!< Timer E compare 2 */
AnnaBridge 171:3a7713b1edbc 9998 #define HRTIM_BMTRGR_TAEEV7_Pos (27U)
AnnaBridge 171:3a7713b1edbc 9999 #define HRTIM_BMTRGR_TAEEV7_Msk (0x1U << HRTIM_BMTRGR_TAEEV7_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10000 #define HRTIM_BMTRGR_TAEEV7 HRTIM_BMTRGR_TAEEV7_Msk /*!< Timer A period following External Event7 */
AnnaBridge 171:3a7713b1edbc 10001 #define HRTIM_BMTRGR_TDEEV8_Pos (28U)
AnnaBridge 171:3a7713b1edbc 10002 #define HRTIM_BMTRGR_TDEEV8_Msk (0x1U << HRTIM_BMTRGR_TDEEV8_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 10003 #define HRTIM_BMTRGR_TDEEV8 HRTIM_BMTRGR_TDEEV8_Msk /*!< Timer D period following External Event8 */
AnnaBridge 171:3a7713b1edbc 10004 #define HRTIM_BMTRGR_EEV7_Pos (29U)
AnnaBridge 171:3a7713b1edbc 10005 #define HRTIM_BMTRGR_EEV7_Msk (0x1U << HRTIM_BMTRGR_EEV7_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 10006 #define HRTIM_BMTRGR_EEV7 HRTIM_BMTRGR_EEV7_Msk /*!< External Event 7 */
AnnaBridge 171:3a7713b1edbc 10007 #define HRTIM_BMTRGR_EEV8_Pos (30U)
AnnaBridge 171:3a7713b1edbc 10008 #define HRTIM_BMTRGR_EEV8_Msk (0x1U << HRTIM_BMTRGR_EEV8_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 10009 #define HRTIM_BMTRGR_EEV8 HRTIM_BMTRGR_EEV8_Msk /*!< External Event 8 */
AnnaBridge 171:3a7713b1edbc 10010 #define HRTIM_BMTRGR_OCHPEV_Pos (31U)
AnnaBridge 171:3a7713b1edbc 10011 #define HRTIM_BMTRGR_OCHPEV_Msk (0x1U << HRTIM_BMTRGR_OCHPEV_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 10012 #define HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk /*!< on-chip Event */
AnnaBridge 171:3a7713b1edbc 10013
AnnaBridge 171:3a7713b1edbc 10014 /******************* Bit definition for HRTIM_BMCMPR register ***************/
AnnaBridge 171:3a7713b1edbc 10015 #define HRTIM_BMCMPR_BMCMPR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10016 #define HRTIM_BMCMPR_BMCMPR_Msk (0xFFFFU << HRTIM_BMCMPR_BMCMPR_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 10017 #define HRTIM_BMCMPR_BMCMPR HRTIM_BMCMPR_BMCMPR_Msk /*!<!<Burst Compare Value */
AnnaBridge 171:3a7713b1edbc 10018
AnnaBridge 171:3a7713b1edbc 10019 /******************* Bit definition for HRTIM_BMPER register ****************/
AnnaBridge 171:3a7713b1edbc 10020 #define HRTIM_BMPER_BMPER_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10021 #define HRTIM_BMPER_BMPER_Msk (0xFFFFU << HRTIM_BMPER_BMPER_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 10022 #define HRTIM_BMPER_BMPER HRTIM_BMPER_BMPER_Msk /*!<!<Burst period Value */
AnnaBridge 171:3a7713b1edbc 10023
AnnaBridge 171:3a7713b1edbc 10024 /******************* Bit definition for HRTIM_EECR1 register ****************/
AnnaBridge 171:3a7713b1edbc 10025 #define HRTIM_EECR1_EE1SRC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10026 #define HRTIM_EECR1_EE1SRC_Msk (0x3U << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 10027 #define HRTIM_EECR1_EE1SRC HRTIM_EECR1_EE1SRC_Msk /*!< External event 1 source */
AnnaBridge 171:3a7713b1edbc 10028 #define HRTIM_EECR1_EE1SRC_0 (0x1U << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10029 #define HRTIM_EECR1_EE1SRC_1 (0x2U << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10030 #define HRTIM_EECR1_EE1POL_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10031 #define HRTIM_EECR1_EE1POL_Msk (0x1U << HRTIM_EECR1_EE1POL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10032 #define HRTIM_EECR1_EE1POL HRTIM_EECR1_EE1POL_Msk /*!< External event 1 Polarity */
AnnaBridge 171:3a7713b1edbc 10033 #define HRTIM_EECR1_EE1SNS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10034 #define HRTIM_EECR1_EE1SNS_Msk (0x3U << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000018 */
AnnaBridge 171:3a7713b1edbc 10035 #define HRTIM_EECR1_EE1SNS HRTIM_EECR1_EE1SNS_Msk /*!< External event 1 sensitivity */
AnnaBridge 171:3a7713b1edbc 10036 #define HRTIM_EECR1_EE1SNS_0 (0x1U << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10037 #define HRTIM_EECR1_EE1SNS_1 (0x2U << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10038 #define HRTIM_EECR1_EE1FAST_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10039 #define HRTIM_EECR1_EE1FAST_Msk (0x1U << HRTIM_EECR1_EE1FAST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10040 #define HRTIM_EECR1_EE1FAST HRTIM_EECR1_EE1FAST_Msk /*!< External event 1 Fast mode */
AnnaBridge 171:3a7713b1edbc 10041
AnnaBridge 171:3a7713b1edbc 10042 #define HRTIM_EECR1_EE2SRC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10043 #define HRTIM_EECR1_EE2SRC_Msk (0x3U << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 10044 #define HRTIM_EECR1_EE2SRC HRTIM_EECR1_EE2SRC_Msk /*!< External event 2 source */
AnnaBridge 171:3a7713b1edbc 10045 #define HRTIM_EECR1_EE2SRC_0 (0x1U << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10046 #define HRTIM_EECR1_EE2SRC_1 (0x2U << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10047 #define HRTIM_EECR1_EE2POL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10048 #define HRTIM_EECR1_EE2POL_Msk (0x1U << HRTIM_EECR1_EE2POL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10049 #define HRTIM_EECR1_EE2POL HRTIM_EECR1_EE2POL_Msk /*!< External event 2 Polarity */
AnnaBridge 171:3a7713b1edbc 10050 #define HRTIM_EECR1_EE2SNS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10051 #define HRTIM_EECR1_EE2SNS_Msk (0x3U << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 10052 #define HRTIM_EECR1_EE2SNS HRTIM_EECR1_EE2SNS_Msk /*!< External event 2 sensitivity */
AnnaBridge 171:3a7713b1edbc 10053 #define HRTIM_EECR1_EE2SNS_0 (0x1U << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10054 #define HRTIM_EECR1_EE2SNS_1 (0x2U << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10055 #define HRTIM_EECR1_EE2FAST_Pos (11U)
AnnaBridge 171:3a7713b1edbc 10056 #define HRTIM_EECR1_EE2FAST_Msk (0x1U << HRTIM_EECR1_EE2FAST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10057 #define HRTIM_EECR1_EE2FAST HRTIM_EECR1_EE2FAST_Msk /*!< External event 2 Fast mode */
AnnaBridge 171:3a7713b1edbc 10058
AnnaBridge 171:3a7713b1edbc 10059 #define HRTIM_EECR1_EE3SRC_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10060 #define HRTIM_EECR1_EE3SRC_Msk (0x3U << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 10061 #define HRTIM_EECR1_EE3SRC HRTIM_EECR1_EE3SRC_Msk /*!< External event 3 source */
AnnaBridge 171:3a7713b1edbc 10062 #define HRTIM_EECR1_EE3SRC_0 (0x1U << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10063 #define HRTIM_EECR1_EE3SRC_1 (0x2U << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10064 #define HRTIM_EECR1_EE3POL_Pos (14U)
AnnaBridge 171:3a7713b1edbc 10065 #define HRTIM_EECR1_EE3POL_Msk (0x1U << HRTIM_EECR1_EE3POL_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10066 #define HRTIM_EECR1_EE3POL HRTIM_EECR1_EE3POL_Msk /*!< External event 3 Polarity */
AnnaBridge 171:3a7713b1edbc 10067 #define HRTIM_EECR1_EE3SNS_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10068 #define HRTIM_EECR1_EE3SNS_Msk (0x3U << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00018000 */
AnnaBridge 171:3a7713b1edbc 10069 #define HRTIM_EECR1_EE3SNS HRTIM_EECR1_EE3SNS_Msk /*!< External event 3 sensitivity */
AnnaBridge 171:3a7713b1edbc 10070 #define HRTIM_EECR1_EE3SNS_0 (0x1U << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10071 #define HRTIM_EECR1_EE3SNS_1 (0x2U << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10072 #define HRTIM_EECR1_EE3FAST_Pos (17U)
AnnaBridge 171:3a7713b1edbc 10073 #define HRTIM_EECR1_EE3FAST_Msk (0x1U << HRTIM_EECR1_EE3FAST_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10074 #define HRTIM_EECR1_EE3FAST HRTIM_EECR1_EE3FAST_Msk /*!< External event 3 Fast mode */
AnnaBridge 171:3a7713b1edbc 10075
AnnaBridge 171:3a7713b1edbc 10076 #define HRTIM_EECR1_EE4SRC_Pos (18U)
AnnaBridge 171:3a7713b1edbc 10077 #define HRTIM_EECR1_EE4SRC_Msk (0x3U << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 10078 #define HRTIM_EECR1_EE4SRC HRTIM_EECR1_EE4SRC_Msk /*!< External event 4 source */
AnnaBridge 171:3a7713b1edbc 10079 #define HRTIM_EECR1_EE4SRC_0 (0x1U << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10080 #define HRTIM_EECR1_EE4SRC_1 (0x2U << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 10081 #define HRTIM_EECR1_EE4POL_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10082 #define HRTIM_EECR1_EE4POL_Msk (0x1U << HRTIM_EECR1_EE4POL_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10083 #define HRTIM_EECR1_EE4POL HRTIM_EECR1_EE4POL_Msk /*!< External event 4 Polarity */
AnnaBridge 171:3a7713b1edbc 10084 #define HRTIM_EECR1_EE4SNS_Pos (21U)
AnnaBridge 171:3a7713b1edbc 10085 #define HRTIM_EECR1_EE4SNS_Msk (0x3U << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00600000 */
AnnaBridge 171:3a7713b1edbc 10086 #define HRTIM_EECR1_EE4SNS HRTIM_EECR1_EE4SNS_Msk /*!< External event 4 sensitivity */
AnnaBridge 171:3a7713b1edbc 10087 #define HRTIM_EECR1_EE4SNS_0 (0x1U << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10088 #define HRTIM_EECR1_EE4SNS_1 (0x2U << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10089 #define HRTIM_EECR1_EE4FAST_Pos (23U)
AnnaBridge 171:3a7713b1edbc 10090 #define HRTIM_EECR1_EE4FAST_Msk (0x1U << HRTIM_EECR1_EE4FAST_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 10091 #define HRTIM_EECR1_EE4FAST HRTIM_EECR1_EE4FAST_Msk /*!< External event 4 Fast mode */
AnnaBridge 171:3a7713b1edbc 10092
AnnaBridge 171:3a7713b1edbc 10093 #define HRTIM_EECR1_EE5SRC_Pos (24U)
AnnaBridge 171:3a7713b1edbc 10094 #define HRTIM_EECR1_EE5SRC_Msk (0x3U << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 10095 #define HRTIM_EECR1_EE5SRC HRTIM_EECR1_EE5SRC_Msk /*!< External event 5 source */
AnnaBridge 171:3a7713b1edbc 10096 #define HRTIM_EECR1_EE5SRC_0 (0x1U << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 10097 #define HRTIM_EECR1_EE5SRC_1 (0x2U << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10098 #define HRTIM_EECR1_EE5POL_Pos (26U)
AnnaBridge 171:3a7713b1edbc 10099 #define HRTIM_EECR1_EE5POL_Msk (0x1U << HRTIM_EECR1_EE5POL_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10100 #define HRTIM_EECR1_EE5POL HRTIM_EECR1_EE5POL_Msk /*!< External event 5 Polarity */
AnnaBridge 171:3a7713b1edbc 10101 #define HRTIM_EECR1_EE5SNS_Pos (27U)
AnnaBridge 171:3a7713b1edbc 10102 #define HRTIM_EECR1_EE5SNS_Msk (0x3U << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x18000000 */
AnnaBridge 171:3a7713b1edbc 10103 #define HRTIM_EECR1_EE5SNS HRTIM_EECR1_EE5SNS_Msk /*!< External event 5 sensitivity */
AnnaBridge 171:3a7713b1edbc 10104 #define HRTIM_EECR1_EE5SNS_0 (0x1U << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10105 #define HRTIM_EECR1_EE5SNS_1 (0x2U << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 10106 #define HRTIM_EECR1_EE5FAST_Pos (29U)
AnnaBridge 171:3a7713b1edbc 10107 #define HRTIM_EECR1_EE5FAST_Msk (0x1U << HRTIM_EECR1_EE5FAST_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 10108 #define HRTIM_EECR1_EE5FAST HRTIM_EECR1_EE5FAST_Msk /*!< External event 5 Fast mode */
AnnaBridge 171:3a7713b1edbc 10109
AnnaBridge 171:3a7713b1edbc 10110 /******************* Bit definition for HRTIM_EECR2 register ****************/
AnnaBridge 171:3a7713b1edbc 10111 #define HRTIM_EECR2_EE6SRC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10112 #define HRTIM_EECR2_EE6SRC_Msk (0x3U << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 10113 #define HRTIM_EECR2_EE6SRC HRTIM_EECR2_EE6SRC_Msk /*!< External event 6 source */
AnnaBridge 171:3a7713b1edbc 10114 #define HRTIM_EECR2_EE6SRC_0 (0x1U << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10115 #define HRTIM_EECR2_EE6SRC_1 (0x2U << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10116 #define HRTIM_EECR2_EE6POL_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10117 #define HRTIM_EECR2_EE6POL_Msk (0x1U << HRTIM_EECR2_EE6POL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10118 #define HRTIM_EECR2_EE6POL HRTIM_EECR2_EE6POL_Msk /*!< External event 6 Polarity */
AnnaBridge 171:3a7713b1edbc 10119 #define HRTIM_EECR2_EE6SNS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10120 #define HRTIM_EECR2_EE6SNS_Msk (0x3U << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000018 */
AnnaBridge 171:3a7713b1edbc 10121 #define HRTIM_EECR2_EE6SNS HRTIM_EECR2_EE6SNS_Msk /*!< External event 6 sensitivity */
AnnaBridge 171:3a7713b1edbc 10122 #define HRTIM_EECR2_EE6SNS_0 (0x1U << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10123 #define HRTIM_EECR2_EE6SNS_1 (0x2U << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10124
AnnaBridge 171:3a7713b1edbc 10125 #define HRTIM_EECR2_EE7SRC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10126 #define HRTIM_EECR2_EE7SRC_Msk (0x3U << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 10127 #define HRTIM_EECR2_EE7SRC HRTIM_EECR2_EE7SRC_Msk /*!< External event 7 source */
AnnaBridge 171:3a7713b1edbc 10128 #define HRTIM_EECR2_EE7SRC_0 (0x1U << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10129 #define HRTIM_EECR2_EE7SRC_1 (0x2U << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10130 #define HRTIM_EECR2_EE7POL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10131 #define HRTIM_EECR2_EE7POL_Msk (0x1U << HRTIM_EECR2_EE7POL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10132 #define HRTIM_EECR2_EE7POL HRTIM_EECR2_EE7POL_Msk /*!< External event 7 Polarity */
AnnaBridge 171:3a7713b1edbc 10133 #define HRTIM_EECR2_EE7SNS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10134 #define HRTIM_EECR2_EE7SNS_Msk (0x3U << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 10135 #define HRTIM_EECR2_EE7SNS HRTIM_EECR2_EE7SNS_Msk /*!< External event 7 sensitivity */
AnnaBridge 171:3a7713b1edbc 10136 #define HRTIM_EECR2_EE7SNS_0 (0x1U << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10137 #define HRTIM_EECR2_EE7SNS_1 (0x2U << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10138
AnnaBridge 171:3a7713b1edbc 10139 #define HRTIM_EECR2_EE8SRC_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10140 #define HRTIM_EECR2_EE8SRC_Msk (0x3U << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 10141 #define HRTIM_EECR2_EE8SRC HRTIM_EECR2_EE8SRC_Msk /*!< External event 8 source */
AnnaBridge 171:3a7713b1edbc 10142 #define HRTIM_EECR2_EE8SRC_0 (0x1U << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10143 #define HRTIM_EECR2_EE8SRC_1 (0x2U << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10144 #define HRTIM_EECR2_EE8POL_Pos (14U)
AnnaBridge 171:3a7713b1edbc 10145 #define HRTIM_EECR2_EE8POL_Msk (0x1U << HRTIM_EECR2_EE8POL_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10146 #define HRTIM_EECR2_EE8POL HRTIM_EECR2_EE8POL_Msk /*!< External event 8 Polarity */
AnnaBridge 171:3a7713b1edbc 10147 #define HRTIM_EECR2_EE8SNS_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10148 #define HRTIM_EECR2_EE8SNS_Msk (0x3U << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00018000 */
AnnaBridge 171:3a7713b1edbc 10149 #define HRTIM_EECR2_EE8SNS HRTIM_EECR2_EE8SNS_Msk /*!< External event 8 sensitivity */
AnnaBridge 171:3a7713b1edbc 10150 #define HRTIM_EECR2_EE8SNS_0 (0x1U << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10151 #define HRTIM_EECR2_EE8SNS_1 (0x2U << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10152
AnnaBridge 171:3a7713b1edbc 10153 #define HRTIM_EECR2_EE9SRC_Pos (18U)
AnnaBridge 171:3a7713b1edbc 10154 #define HRTIM_EECR2_EE9SRC_Msk (0x3U << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 10155 #define HRTIM_EECR2_EE9SRC HRTIM_EECR2_EE9SRC_Msk /*!< External event 9 source */
AnnaBridge 171:3a7713b1edbc 10156 #define HRTIM_EECR2_EE9SRC_0 (0x1U << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10157 #define HRTIM_EECR2_EE9SRC_1 (0x2U << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 10158 #define HRTIM_EECR2_EE9POL_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10159 #define HRTIM_EECR2_EE9POL_Msk (0x1U << HRTIM_EECR2_EE9POL_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10160 #define HRTIM_EECR2_EE9POL HRTIM_EECR2_EE9POL_Msk /*!< External event 9 Polarity */
AnnaBridge 171:3a7713b1edbc 10161 #define HRTIM_EECR2_EE9SNS_Pos (21U)
AnnaBridge 171:3a7713b1edbc 10162 #define HRTIM_EECR2_EE9SNS_Msk (0x3U << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00600000 */
AnnaBridge 171:3a7713b1edbc 10163 #define HRTIM_EECR2_EE9SNS HRTIM_EECR2_EE9SNS_Msk /*!< External event 9 sensitivity */
AnnaBridge 171:3a7713b1edbc 10164 #define HRTIM_EECR2_EE9SNS_0 (0x1U << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10165 #define HRTIM_EECR2_EE9SNS_1 (0x2U << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10166
AnnaBridge 171:3a7713b1edbc 10167 #define HRTIM_EECR2_EE10SRC_Pos (24U)
AnnaBridge 171:3a7713b1edbc 10168 #define HRTIM_EECR2_EE10SRC_Msk (0x3U << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 10169 #define HRTIM_EECR2_EE10SRC HRTIM_EECR2_EE10SRC_Msk /*!< External event 10 source */
AnnaBridge 171:3a7713b1edbc 10170 #define HRTIM_EECR2_EE10SRC_0 (0x1U << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 10171 #define HRTIM_EECR2_EE10SRC_1 (0x2U << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10172 #define HRTIM_EECR2_EE10POL_Pos (26U)
AnnaBridge 171:3a7713b1edbc 10173 #define HRTIM_EECR2_EE10POL_Msk (0x1U << HRTIM_EECR2_EE10POL_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10174 #define HRTIM_EECR2_EE10POL HRTIM_EECR2_EE10POL_Msk /*!< External event 10 Polarity */
AnnaBridge 171:3a7713b1edbc 10175 #define HRTIM_EECR2_EE10SNS_Pos (27U)
AnnaBridge 171:3a7713b1edbc 10176 #define HRTIM_EECR2_EE10SNS_Msk (0x3U << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x18000000 */
AnnaBridge 171:3a7713b1edbc 10177 #define HRTIM_EECR2_EE10SNS HRTIM_EECR2_EE10SNS_Msk /*!< External event 10 sensitivity */
AnnaBridge 171:3a7713b1edbc 10178 #define HRTIM_EECR2_EE10SNS_0 (0x1U << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10179 #define HRTIM_EECR2_EE10SNS_1 (0x2U << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 10180
AnnaBridge 171:3a7713b1edbc 10181 /******************* Bit definition for HRTIM_EECR3 register ****************/
AnnaBridge 171:3a7713b1edbc 10182 #define HRTIM_EECR3_EE6F_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10183 #define HRTIM_EECR3_EE6F_Msk (0xFU << HRTIM_EECR3_EE6F_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 10184 #define HRTIM_EECR3_EE6F HRTIM_EECR3_EE6F_Msk /*!< External event 6 filter */
AnnaBridge 171:3a7713b1edbc 10185 #define HRTIM_EECR3_EE6F_0 (0x1U << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10186 #define HRTIM_EECR3_EE6F_1 (0x2U << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10187 #define HRTIM_EECR3_EE6F_2 (0x4U << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10188 #define HRTIM_EECR3_EE6F_3 (0x8U << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10189 #define HRTIM_EECR3_EE7F_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10190 #define HRTIM_EECR3_EE7F_Msk (0xFU << HRTIM_EECR3_EE7F_Pos) /*!< 0x000003C0 */
AnnaBridge 171:3a7713b1edbc 10191 #define HRTIM_EECR3_EE7F HRTIM_EECR3_EE7F_Msk /*!< External event 7 filter */
AnnaBridge 171:3a7713b1edbc 10192 #define HRTIM_EECR3_EE7F_0 (0x1U << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10193 #define HRTIM_EECR3_EE7F_1 (0x2U << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10194 #define HRTIM_EECR3_EE7F_2 (0x4U << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10195 #define HRTIM_EECR3_EE7F_3 (0x8U << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10196 #define HRTIM_EECR3_EE8F_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10197 #define HRTIM_EECR3_EE8F_Msk (0xFU << HRTIM_EECR3_EE8F_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 10198 #define HRTIM_EECR3_EE8F HRTIM_EECR3_EE8F_Msk /*!< External event 8 filter */
AnnaBridge 171:3a7713b1edbc 10199 #define HRTIM_EECR3_EE8F_0 (0x1U << HRTIM_EECR3_EE8F_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10200 #define HRTIM_EECR3_EE8F_1 (0x2U << HRTIM_EECR3_EE8F_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10201 #define HRTIM_EECR3_EE8F_2 (0x4U << HRTIM_EECR3_EE8F_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10202 #define HRTIM_EECR3_EE8F_3 (0x8U << HRTIM_EECR3_EE8F_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10203 #define HRTIM_EECR3_EE9F_Pos (18U)
AnnaBridge 171:3a7713b1edbc 10204 #define HRTIM_EECR3_EE9F_Msk (0xFU << HRTIM_EECR3_EE9F_Pos) /*!< 0x003C0000 */
AnnaBridge 171:3a7713b1edbc 10205 #define HRTIM_EECR3_EE9F HRTIM_EECR3_EE9F_Msk /*!< External event 9 filter */
AnnaBridge 171:3a7713b1edbc 10206 #define HRTIM_EECR3_EE9F_0 (0x1U << HRTIM_EECR3_EE9F_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10207 #define HRTIM_EECR3_EE9F_1 (0x2U << HRTIM_EECR3_EE9F_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 10208 #define HRTIM_EECR3_EE9F_2 (0x4U << HRTIM_EECR3_EE9F_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10209 #define HRTIM_EECR3_EE9F_3 (0x8U << HRTIM_EECR3_EE9F_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10210 #define HRTIM_EECR3_EE10F_Pos (24U)
AnnaBridge 171:3a7713b1edbc 10211 #define HRTIM_EECR3_EE10F_Msk (0xFU << HRTIM_EECR3_EE10F_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 10212 #define HRTIM_EECR3_EE10F HRTIM_EECR3_EE10F_Msk /*!< External event 10 filter */
AnnaBridge 171:3a7713b1edbc 10213 #define HRTIM_EECR3_EE10F_0 (0x1U << HRTIM_EECR3_EE10F_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 10214 #define HRTIM_EECR3_EE10F_1 (0x2U << HRTIM_EECR3_EE10F_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10215 #define HRTIM_EECR3_EE10F_2 (0x4U << HRTIM_EECR3_EE10F_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10216 #define HRTIM_EECR3_EE10F_3 (0x8U << HRTIM_EECR3_EE10F_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10217 #define HRTIM_EECR3_EEVSD_Pos (30U)
AnnaBridge 171:3a7713b1edbc 10218 #define HRTIM_EECR3_EEVSD_Msk (0x3U << HRTIM_EECR3_EEVSD_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 10219 #define HRTIM_EECR3_EEVSD HRTIM_EECR3_EEVSD_Msk /*!< External event sampling clock division */
AnnaBridge 171:3a7713b1edbc 10220 #define HRTIM_EECR3_EEVSD_0 (0x1U << HRTIM_EECR3_EEVSD_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 10221 #define HRTIM_EECR3_EEVSD_1 (0x2U << HRTIM_EECR3_EEVSD_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 10222
AnnaBridge 171:3a7713b1edbc 10223 /******************* Bit definition for HRTIM_ADC1R register ****************/
AnnaBridge 171:3a7713b1edbc 10224 #define HRTIM_ADC1R_AD1MC1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10225 #define HRTIM_ADC1R_AD1MC1_Msk (0x1U << HRTIM_ADC1R_AD1MC1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10226 #define HRTIM_ADC1R_AD1MC1 HRTIM_ADC1R_AD1MC1_Msk /*!< ADC Trigger 1 on master compare 1 */
AnnaBridge 171:3a7713b1edbc 10227 #define HRTIM_ADC1R_AD1MC2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10228 #define HRTIM_ADC1R_AD1MC2_Msk (0x1U << HRTIM_ADC1R_AD1MC2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10229 #define HRTIM_ADC1R_AD1MC2 HRTIM_ADC1R_AD1MC2_Msk /*!< ADC Trigger 1 on master compare 2 */
AnnaBridge 171:3a7713b1edbc 10230 #define HRTIM_ADC1R_AD1MC3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10231 #define HRTIM_ADC1R_AD1MC3_Msk (0x1U << HRTIM_ADC1R_AD1MC3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10232 #define HRTIM_ADC1R_AD1MC3 HRTIM_ADC1R_AD1MC3_Msk /*!< ADC Trigger 1 on master compare 3 */
AnnaBridge 171:3a7713b1edbc 10233 #define HRTIM_ADC1R_AD1MC4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10234 #define HRTIM_ADC1R_AD1MC4_Msk (0x1U << HRTIM_ADC1R_AD1MC4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10235 #define HRTIM_ADC1R_AD1MC4 HRTIM_ADC1R_AD1MC4_Msk /*!< ADC Trigger 1 on master compare 4 */
AnnaBridge 171:3a7713b1edbc 10236 #define HRTIM_ADC1R_AD1MPER_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10237 #define HRTIM_ADC1R_AD1MPER_Msk (0x1U << HRTIM_ADC1R_AD1MPER_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10238 #define HRTIM_ADC1R_AD1MPER HRTIM_ADC1R_AD1MPER_Msk /*!< ADC Trigger 1 on master period */
AnnaBridge 171:3a7713b1edbc 10239 #define HRTIM_ADC1R_AD1EEV1_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10240 #define HRTIM_ADC1R_AD1EEV1_Msk (0x1U << HRTIM_ADC1R_AD1EEV1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10241 #define HRTIM_ADC1R_AD1EEV1 HRTIM_ADC1R_AD1EEV1_Msk /*!< ADC Trigger 1 on external event 1 */
AnnaBridge 171:3a7713b1edbc 10242 #define HRTIM_ADC1R_AD1EEV2_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10243 #define HRTIM_ADC1R_AD1EEV2_Msk (0x1U << HRTIM_ADC1R_AD1EEV2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10244 #define HRTIM_ADC1R_AD1EEV2 HRTIM_ADC1R_AD1EEV2_Msk /*!< ADC Trigger 1 on external event 2 */
AnnaBridge 171:3a7713b1edbc 10245 #define HRTIM_ADC1R_AD1EEV3_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10246 #define HRTIM_ADC1R_AD1EEV3_Msk (0x1U << HRTIM_ADC1R_AD1EEV3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10247 #define HRTIM_ADC1R_AD1EEV3 HRTIM_ADC1R_AD1EEV3_Msk /*!< ADC Trigger 1 on external event 3 */
AnnaBridge 171:3a7713b1edbc 10248 #define HRTIM_ADC1R_AD1EEV4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10249 #define HRTIM_ADC1R_AD1EEV4_Msk (0x1U << HRTIM_ADC1R_AD1EEV4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10250 #define HRTIM_ADC1R_AD1EEV4 HRTIM_ADC1R_AD1EEV4_Msk /*!< ADC Trigger 1 on external event 4 */
AnnaBridge 171:3a7713b1edbc 10251 #define HRTIM_ADC1R_AD1EEV5_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10252 #define HRTIM_ADC1R_AD1EEV5_Msk (0x1U << HRTIM_ADC1R_AD1EEV5_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10253 #define HRTIM_ADC1R_AD1EEV5 HRTIM_ADC1R_AD1EEV5_Msk /*!< ADC Trigger 1 on external event 5 */
AnnaBridge 171:3a7713b1edbc 10254 #define HRTIM_ADC1R_AD1TAC2_Pos (10U)
AnnaBridge 171:3a7713b1edbc 10255 #define HRTIM_ADC1R_AD1TAC2_Msk (0x1U << HRTIM_ADC1R_AD1TAC2_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10256 #define HRTIM_ADC1R_AD1TAC2 HRTIM_ADC1R_AD1TAC2_Msk /*!< ADC Trigger 1 on Timer A compare 2 */
AnnaBridge 171:3a7713b1edbc 10257 #define HRTIM_ADC1R_AD1TAC3_Pos (11U)
AnnaBridge 171:3a7713b1edbc 10258 #define HRTIM_ADC1R_AD1TAC3_Msk (0x1U << HRTIM_ADC1R_AD1TAC3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10259 #define HRTIM_ADC1R_AD1TAC3 HRTIM_ADC1R_AD1TAC3_Msk /*!< ADC Trigger 1 on Timer A compare 3 */
AnnaBridge 171:3a7713b1edbc 10260 #define HRTIM_ADC1R_AD1TAC4_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10261 #define HRTIM_ADC1R_AD1TAC4_Msk (0x1U << HRTIM_ADC1R_AD1TAC4_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10262 #define HRTIM_ADC1R_AD1TAC4 HRTIM_ADC1R_AD1TAC4_Msk /*!< ADC Trigger 1 on Timer A compare 4 */
AnnaBridge 171:3a7713b1edbc 10263 #define HRTIM_ADC1R_AD1TAPER_Pos (13U)
AnnaBridge 171:3a7713b1edbc 10264 #define HRTIM_ADC1R_AD1TAPER_Msk (0x1U << HRTIM_ADC1R_AD1TAPER_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10265 #define HRTIM_ADC1R_AD1TAPER HRTIM_ADC1R_AD1TAPER_Msk /*!< ADC Trigger 1 on Timer A period */
AnnaBridge 171:3a7713b1edbc 10266 #define HRTIM_ADC1R_AD1TARST_Pos (14U)
AnnaBridge 171:3a7713b1edbc 10267 #define HRTIM_ADC1R_AD1TARST_Msk (0x1U << HRTIM_ADC1R_AD1TARST_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10268 #define HRTIM_ADC1R_AD1TARST HRTIM_ADC1R_AD1TARST_Msk /*!< ADC Trigger 1 on Timer A reset */
AnnaBridge 171:3a7713b1edbc 10269 #define HRTIM_ADC1R_AD1TBC2_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10270 #define HRTIM_ADC1R_AD1TBC2_Msk (0x1U << HRTIM_ADC1R_AD1TBC2_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10271 #define HRTIM_ADC1R_AD1TBC2 HRTIM_ADC1R_AD1TBC2_Msk /*!< ADC Trigger 1 on Timer B compare 2 */
AnnaBridge 171:3a7713b1edbc 10272 #define HRTIM_ADC1R_AD1TBC3_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10273 #define HRTIM_ADC1R_AD1TBC3_Msk (0x1U << HRTIM_ADC1R_AD1TBC3_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10274 #define HRTIM_ADC1R_AD1TBC3 HRTIM_ADC1R_AD1TBC3_Msk /*!< ADC Trigger 1 on Timer B compare 3 */
AnnaBridge 171:3a7713b1edbc 10275 #define HRTIM_ADC1R_AD1TBC4_Pos (17U)
AnnaBridge 171:3a7713b1edbc 10276 #define HRTIM_ADC1R_AD1TBC4_Msk (0x1U << HRTIM_ADC1R_AD1TBC4_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10277 #define HRTIM_ADC1R_AD1TBC4 HRTIM_ADC1R_AD1TBC4_Msk /*!< ADC Trigger 1 on Timer B compare 4 */
AnnaBridge 171:3a7713b1edbc 10278 #define HRTIM_ADC1R_AD1TBPER_Pos (18U)
AnnaBridge 171:3a7713b1edbc 10279 #define HRTIM_ADC1R_AD1TBPER_Msk (0x1U << HRTIM_ADC1R_AD1TBPER_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10280 #define HRTIM_ADC1R_AD1TBPER HRTIM_ADC1R_AD1TBPER_Msk /*!< ADC Trigger 1 on Timer B period */
AnnaBridge 171:3a7713b1edbc 10281 #define HRTIM_ADC1R_AD1TBRST_Pos (19U)
AnnaBridge 171:3a7713b1edbc 10282 #define HRTIM_ADC1R_AD1TBRST_Msk (0x1U << HRTIM_ADC1R_AD1TBRST_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 10283 #define HRTIM_ADC1R_AD1TBRST HRTIM_ADC1R_AD1TBRST_Msk /*!< ADC Trigger 1 on Timer B reset */
AnnaBridge 171:3a7713b1edbc 10284 #define HRTIM_ADC1R_AD1TCC2_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10285 #define HRTIM_ADC1R_AD1TCC2_Msk (0x1U << HRTIM_ADC1R_AD1TCC2_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10286 #define HRTIM_ADC1R_AD1TCC2 HRTIM_ADC1R_AD1TCC2_Msk /*!< ADC Trigger 1 on Timer C compare 2 */
AnnaBridge 171:3a7713b1edbc 10287 #define HRTIM_ADC1R_AD1TCC3_Pos (21U)
AnnaBridge 171:3a7713b1edbc 10288 #define HRTIM_ADC1R_AD1TCC3_Msk (0x1U << HRTIM_ADC1R_AD1TCC3_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10289 #define HRTIM_ADC1R_AD1TCC3 HRTIM_ADC1R_AD1TCC3_Msk /*!< ADC Trigger 1 on Timer C compare 3 */
AnnaBridge 171:3a7713b1edbc 10290 #define HRTIM_ADC1R_AD1TCC4_Pos (22U)
AnnaBridge 171:3a7713b1edbc 10291 #define HRTIM_ADC1R_AD1TCC4_Msk (0x1U << HRTIM_ADC1R_AD1TCC4_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10292 #define HRTIM_ADC1R_AD1TCC4 HRTIM_ADC1R_AD1TCC4_Msk /*!< ADC Trigger 1 on Timer C compare 4 */
AnnaBridge 171:3a7713b1edbc 10293 #define HRTIM_ADC1R_AD1TCPER_Pos (23U)
AnnaBridge 171:3a7713b1edbc 10294 #define HRTIM_ADC1R_AD1TCPER_Msk (0x1U << HRTIM_ADC1R_AD1TCPER_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 10295 #define HRTIM_ADC1R_AD1TCPER HRTIM_ADC1R_AD1TCPER_Msk /*!< ADC Trigger 1 on Timer C period */
AnnaBridge 171:3a7713b1edbc 10296 #define HRTIM_ADC1R_AD1TDC2_Pos (24U)
AnnaBridge 171:3a7713b1edbc 10297 #define HRTIM_ADC1R_AD1TDC2_Msk (0x1U << HRTIM_ADC1R_AD1TDC2_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 10298 #define HRTIM_ADC1R_AD1TDC2 HRTIM_ADC1R_AD1TDC2_Msk /*!< ADC Trigger 1 on Timer D compare 2 */
AnnaBridge 171:3a7713b1edbc 10299 #define HRTIM_ADC1R_AD1TDC3_Pos (25U)
AnnaBridge 171:3a7713b1edbc 10300 #define HRTIM_ADC1R_AD1TDC3_Msk (0x1U << HRTIM_ADC1R_AD1TDC3_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10301 #define HRTIM_ADC1R_AD1TDC3 HRTIM_ADC1R_AD1TDC3_Msk /*!< ADC Trigger 1 on Timer D compare 3 */
AnnaBridge 171:3a7713b1edbc 10302 #define HRTIM_ADC1R_AD1TDC4_Pos (26U)
AnnaBridge 171:3a7713b1edbc 10303 #define HRTIM_ADC1R_AD1TDC4_Msk (0x1U << HRTIM_ADC1R_AD1TDC4_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10304 #define HRTIM_ADC1R_AD1TDC4 HRTIM_ADC1R_AD1TDC4_Msk /*!< ADC Trigger 1 on Timer D compare 4 */
AnnaBridge 171:3a7713b1edbc 10305 #define HRTIM_ADC1R_AD1TDPER_Pos (27U)
AnnaBridge 171:3a7713b1edbc 10306 #define HRTIM_ADC1R_AD1TDPER_Msk (0x1U << HRTIM_ADC1R_AD1TDPER_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10307 #define HRTIM_ADC1R_AD1TDPER HRTIM_ADC1R_AD1TDPER_Msk /*!< ADC Trigger 1 on Timer D period */
AnnaBridge 171:3a7713b1edbc 10308 #define HRTIM_ADC1R_AD1TEC2_Pos (28U)
AnnaBridge 171:3a7713b1edbc 10309 #define HRTIM_ADC1R_AD1TEC2_Msk (0x1U << HRTIM_ADC1R_AD1TEC2_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 10310 #define HRTIM_ADC1R_AD1TEC2 HRTIM_ADC1R_AD1TEC2_Msk /*!< ADC Trigger 1 on Timer E compare 2 */
AnnaBridge 171:3a7713b1edbc 10311 #define HRTIM_ADC1R_AD1TEC3_Pos (29U)
AnnaBridge 171:3a7713b1edbc 10312 #define HRTIM_ADC1R_AD1TEC3_Msk (0x1U << HRTIM_ADC1R_AD1TEC3_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 10313 #define HRTIM_ADC1R_AD1TEC3 HRTIM_ADC1R_AD1TEC3_Msk /*!< ADC Trigger 1 on Timer E compare 3 */
AnnaBridge 171:3a7713b1edbc 10314 #define HRTIM_ADC1R_AD1TEC4_Pos (30U)
AnnaBridge 171:3a7713b1edbc 10315 #define HRTIM_ADC1R_AD1TEC4_Msk (0x1U << HRTIM_ADC1R_AD1TEC4_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 10316 #define HRTIM_ADC1R_AD1TEC4 HRTIM_ADC1R_AD1TEC4_Msk /*!< ADC Trigger 1 on Timer E compare 4 */
AnnaBridge 171:3a7713b1edbc 10317 #define HRTIM_ADC1R_AD1TEPER_Pos (31U)
AnnaBridge 171:3a7713b1edbc 10318 #define HRTIM_ADC1R_AD1TEPER_Msk (0x1U << HRTIM_ADC1R_AD1TEPER_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 10319 #define HRTIM_ADC1R_AD1TEPER HRTIM_ADC1R_AD1TEPER_Msk /*!< ADC Trigger 1 on Timer E period */
AnnaBridge 171:3a7713b1edbc 10320
AnnaBridge 171:3a7713b1edbc 10321 /******************* Bit definition for HRTIM_ADC2R register ****************/
AnnaBridge 171:3a7713b1edbc 10322 #define HRTIM_ADC2R_AD2MC1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10323 #define HRTIM_ADC2R_AD2MC1_Msk (0x1U << HRTIM_ADC2R_AD2MC1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10324 #define HRTIM_ADC2R_AD2MC1 HRTIM_ADC2R_AD2MC1_Msk /*!< ADC Trigger 2 on master compare 1 */
AnnaBridge 171:3a7713b1edbc 10325 #define HRTIM_ADC2R_AD2MC2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10326 #define HRTIM_ADC2R_AD2MC2_Msk (0x1U << HRTIM_ADC2R_AD2MC2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10327 #define HRTIM_ADC2R_AD2MC2 HRTIM_ADC2R_AD2MC2_Msk /*!< ADC Trigger 2 on master compare 2 */
AnnaBridge 171:3a7713b1edbc 10328 #define HRTIM_ADC2R_AD2MC3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10329 #define HRTIM_ADC2R_AD2MC3_Msk (0x1U << HRTIM_ADC2R_AD2MC3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10330 #define HRTIM_ADC2R_AD2MC3 HRTIM_ADC2R_AD2MC3_Msk /*!< ADC Trigger 2 on master compare 3 */
AnnaBridge 171:3a7713b1edbc 10331 #define HRTIM_ADC2R_AD2MC4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10332 #define HRTIM_ADC2R_AD2MC4_Msk (0x1U << HRTIM_ADC2R_AD2MC4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10333 #define HRTIM_ADC2R_AD2MC4 HRTIM_ADC2R_AD2MC4_Msk /*!< ADC Trigger 2 on master compare 4 */
AnnaBridge 171:3a7713b1edbc 10334 #define HRTIM_ADC2R_AD2MPER_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10335 #define HRTIM_ADC2R_AD2MPER_Msk (0x1U << HRTIM_ADC2R_AD2MPER_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10336 #define HRTIM_ADC2R_AD2MPER HRTIM_ADC2R_AD2MPER_Msk /*!< ADC Trigger 2 on master period */
AnnaBridge 171:3a7713b1edbc 10337 #define HRTIM_ADC2R_AD2EEV6_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10338 #define HRTIM_ADC2R_AD2EEV6_Msk (0x1U << HRTIM_ADC2R_AD2EEV6_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10339 #define HRTIM_ADC2R_AD2EEV6 HRTIM_ADC2R_AD2EEV6_Msk /*!< ADC Trigger 2 on external event 6 */
AnnaBridge 171:3a7713b1edbc 10340 #define HRTIM_ADC2R_AD2EEV7_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10341 #define HRTIM_ADC2R_AD2EEV7_Msk (0x1U << HRTIM_ADC2R_AD2EEV7_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10342 #define HRTIM_ADC2R_AD2EEV7 HRTIM_ADC2R_AD2EEV7_Msk /*!< ADC Trigger 2 on external event 7 */
AnnaBridge 171:3a7713b1edbc 10343 #define HRTIM_ADC2R_AD2EEV8_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10344 #define HRTIM_ADC2R_AD2EEV8_Msk (0x1U << HRTIM_ADC2R_AD2EEV8_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10345 #define HRTIM_ADC2R_AD2EEV8 HRTIM_ADC2R_AD2EEV8_Msk /*!< ADC Trigger 2 on external event 8 */
AnnaBridge 171:3a7713b1edbc 10346 #define HRTIM_ADC2R_AD2EEV9_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10347 #define HRTIM_ADC2R_AD2EEV9_Msk (0x1U << HRTIM_ADC2R_AD2EEV9_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10348 #define HRTIM_ADC2R_AD2EEV9 HRTIM_ADC2R_AD2EEV9_Msk /*!< ADC Trigger 2 on external event 9 */
AnnaBridge 171:3a7713b1edbc 10349 #define HRTIM_ADC2R_AD2EEV10_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10350 #define HRTIM_ADC2R_AD2EEV10_Msk (0x1U << HRTIM_ADC2R_AD2EEV10_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10351 #define HRTIM_ADC2R_AD2EEV10 HRTIM_ADC2R_AD2EEV10_Msk /*!< ADC Trigger 2 on external event 10 */
AnnaBridge 171:3a7713b1edbc 10352 #define HRTIM_ADC2R_AD2TAC2_Pos (10U)
AnnaBridge 171:3a7713b1edbc 10353 #define HRTIM_ADC2R_AD2TAC2_Msk (0x1U << HRTIM_ADC2R_AD2TAC2_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10354 #define HRTIM_ADC2R_AD2TAC2 HRTIM_ADC2R_AD2TAC2_Msk /*!< ADC Trigger 2 on Timer A compare 2 */
AnnaBridge 171:3a7713b1edbc 10355 #define HRTIM_ADC2R_AD2TAC3_Pos (11U)
AnnaBridge 171:3a7713b1edbc 10356 #define HRTIM_ADC2R_AD2TAC3_Msk (0x1U << HRTIM_ADC2R_AD2TAC3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10357 #define HRTIM_ADC2R_AD2TAC3 HRTIM_ADC2R_AD2TAC3_Msk /*!< ADC Trigger 2 on Timer A compare 3 */
AnnaBridge 171:3a7713b1edbc 10358 #define HRTIM_ADC2R_AD2TAC4_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10359 #define HRTIM_ADC2R_AD2TAC4_Msk (0x1U << HRTIM_ADC2R_AD2TAC4_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10360 #define HRTIM_ADC2R_AD2TAC4 HRTIM_ADC2R_AD2TAC4_Msk /*!< ADC Trigger 2 on Timer A compare 4*/
AnnaBridge 171:3a7713b1edbc 10361 #define HRTIM_ADC2R_AD2TAPER_Pos (13U)
AnnaBridge 171:3a7713b1edbc 10362 #define HRTIM_ADC2R_AD2TAPER_Msk (0x1U << HRTIM_ADC2R_AD2TAPER_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10363 #define HRTIM_ADC2R_AD2TAPER HRTIM_ADC2R_AD2TAPER_Msk /*!< ADC Trigger 2 on Timer A period */
AnnaBridge 171:3a7713b1edbc 10364 #define HRTIM_ADC2R_AD2TBC2_Pos (14U)
AnnaBridge 171:3a7713b1edbc 10365 #define HRTIM_ADC2R_AD2TBC2_Msk (0x1U << HRTIM_ADC2R_AD2TBC2_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10366 #define HRTIM_ADC2R_AD2TBC2 HRTIM_ADC2R_AD2TBC2_Msk /*!< ADC Trigger 2 on Timer B compare 2 */
AnnaBridge 171:3a7713b1edbc 10367 #define HRTIM_ADC2R_AD2TBC3_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10368 #define HRTIM_ADC2R_AD2TBC3_Msk (0x1U << HRTIM_ADC2R_AD2TBC3_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10369 #define HRTIM_ADC2R_AD2TBC3 HRTIM_ADC2R_AD2TBC3_Msk /*!< ADC Trigger 2 on Timer B compare 3 */
AnnaBridge 171:3a7713b1edbc 10370 #define HRTIM_ADC2R_AD2TBC4_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10371 #define HRTIM_ADC2R_AD2TBC4_Msk (0x1U << HRTIM_ADC2R_AD2TBC4_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10372 #define HRTIM_ADC2R_AD2TBC4 HRTIM_ADC2R_AD2TBC4_Msk /*!< ADC Trigger 2 on Timer B compare 4 */
AnnaBridge 171:3a7713b1edbc 10373 #define HRTIM_ADC2R_AD2TBPER_Pos (17U)
AnnaBridge 171:3a7713b1edbc 10374 #define HRTIM_ADC2R_AD2TBPER_Msk (0x1U << HRTIM_ADC2R_AD2TBPER_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10375 #define HRTIM_ADC2R_AD2TBPER HRTIM_ADC2R_AD2TBPER_Msk /*!< ADC Trigger 2 on Timer B period */
AnnaBridge 171:3a7713b1edbc 10376 #define HRTIM_ADC2R_AD2TCC2_Pos (18U)
AnnaBridge 171:3a7713b1edbc 10377 #define HRTIM_ADC2R_AD2TCC2_Msk (0x1U << HRTIM_ADC2R_AD2TCC2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10378 #define HRTIM_ADC2R_AD2TCC2 HRTIM_ADC2R_AD2TCC2_Msk /*!< ADC Trigger 2 on Timer C compare 2 */
AnnaBridge 171:3a7713b1edbc 10379 #define HRTIM_ADC2R_AD2TCC3_Pos (19U)
AnnaBridge 171:3a7713b1edbc 10380 #define HRTIM_ADC2R_AD2TCC3_Msk (0x1U << HRTIM_ADC2R_AD2TCC3_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 10381 #define HRTIM_ADC2R_AD2TCC3 HRTIM_ADC2R_AD2TCC3_Msk /*!< ADC Trigger 2 on Timer C compare 3 */
AnnaBridge 171:3a7713b1edbc 10382 #define HRTIM_ADC2R_AD2TCC4_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10383 #define HRTIM_ADC2R_AD2TCC4_Msk (0x1U << HRTIM_ADC2R_AD2TCC4_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10384 #define HRTIM_ADC2R_AD2TCC4 HRTIM_ADC2R_AD2TCC4_Msk /*!< ADC Trigger 2 on Timer C compare 4 */
AnnaBridge 171:3a7713b1edbc 10385 #define HRTIM_ADC2R_AD2TCPER_Pos (21U)
AnnaBridge 171:3a7713b1edbc 10386 #define HRTIM_ADC2R_AD2TCPER_Msk (0x1U << HRTIM_ADC2R_AD2TCPER_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10387 #define HRTIM_ADC2R_AD2TCPER HRTIM_ADC2R_AD2TCPER_Msk /*!< ADC Trigger 2 on Timer C period */
AnnaBridge 171:3a7713b1edbc 10388 #define HRTIM_ADC2R_AD2TCRST_Pos (22U)
AnnaBridge 171:3a7713b1edbc 10389 #define HRTIM_ADC2R_AD2TCRST_Msk (0x1U << HRTIM_ADC2R_AD2TCRST_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10390 #define HRTIM_ADC2R_AD2TCRST HRTIM_ADC2R_AD2TCRST_Msk /*!< ADC Trigger 2 on Timer C reset */
AnnaBridge 171:3a7713b1edbc 10391 #define HRTIM_ADC2R_AD2TDC2_Pos (23U)
AnnaBridge 171:3a7713b1edbc 10392 #define HRTIM_ADC2R_AD2TDC2_Msk (0x1U << HRTIM_ADC2R_AD2TDC2_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 10393 #define HRTIM_ADC2R_AD2TDC2 HRTIM_ADC2R_AD2TDC2_Msk /*!< ADC Trigger 2 on Timer D compare 2 */
AnnaBridge 171:3a7713b1edbc 10394 #define HRTIM_ADC2R_AD2TDC3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 10395 #define HRTIM_ADC2R_AD2TDC3_Msk (0x1U << HRTIM_ADC2R_AD2TDC3_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 10396 #define HRTIM_ADC2R_AD2TDC3 HRTIM_ADC2R_AD2TDC3_Msk /*!< ADC Trigger 2 on Timer D compare 3 */
AnnaBridge 171:3a7713b1edbc 10397 #define HRTIM_ADC2R_AD2TDC4_Pos (25U)
AnnaBridge 171:3a7713b1edbc 10398 #define HRTIM_ADC2R_AD2TDC4_Msk (0x1U << HRTIM_ADC2R_AD2TDC4_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10399 #define HRTIM_ADC2R_AD2TDC4 HRTIM_ADC2R_AD2TDC4_Msk /*!< ADC Trigger 2 on Timer D compare 4*/
AnnaBridge 171:3a7713b1edbc 10400 #define HRTIM_ADC2R_AD2TDPER_Pos (26U)
AnnaBridge 171:3a7713b1edbc 10401 #define HRTIM_ADC2R_AD2TDPER_Msk (0x1U << HRTIM_ADC2R_AD2TDPER_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10402 #define HRTIM_ADC2R_AD2TDPER HRTIM_ADC2R_AD2TDPER_Msk /*!< ADC Trigger 2 on Timer D period */
AnnaBridge 171:3a7713b1edbc 10403 #define HRTIM_ADC2R_AD2TDRST_Pos (27U)
AnnaBridge 171:3a7713b1edbc 10404 #define HRTIM_ADC2R_AD2TDRST_Msk (0x1U << HRTIM_ADC2R_AD2TDRST_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10405 #define HRTIM_ADC2R_AD2TDRST HRTIM_ADC2R_AD2TDRST_Msk /*!< ADC Trigger 2 on Timer D reset */
AnnaBridge 171:3a7713b1edbc 10406 #define HRTIM_ADC2R_AD2TEC2_Pos (28U)
AnnaBridge 171:3a7713b1edbc 10407 #define HRTIM_ADC2R_AD2TEC2_Msk (0x1U << HRTIM_ADC2R_AD2TEC2_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 10408 #define HRTIM_ADC2R_AD2TEC2 HRTIM_ADC2R_AD2TEC2_Msk /*!< ADC Trigger 2 on Timer E compare 2 */
AnnaBridge 171:3a7713b1edbc 10409 #define HRTIM_ADC2R_AD2TEC3_Pos (29U)
AnnaBridge 171:3a7713b1edbc 10410 #define HRTIM_ADC2R_AD2TEC3_Msk (0x1U << HRTIM_ADC2R_AD2TEC3_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 10411 #define HRTIM_ADC2R_AD2TEC3 HRTIM_ADC2R_AD2TEC3_Msk /*!< ADC Trigger 2 on Timer E compare 3 */
AnnaBridge 171:3a7713b1edbc 10412 #define HRTIM_ADC2R_AD2TEC4_Pos (30U)
AnnaBridge 171:3a7713b1edbc 10413 #define HRTIM_ADC2R_AD2TEC4_Msk (0x1U << HRTIM_ADC2R_AD2TEC4_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 10414 #define HRTIM_ADC2R_AD2TEC4 HRTIM_ADC2R_AD2TEC4_Msk /*!< ADC Trigger 2 on Timer E compare 4 */
AnnaBridge 171:3a7713b1edbc 10415 #define HRTIM_ADC2R_AD2TERST_Pos (31U)
AnnaBridge 171:3a7713b1edbc 10416 #define HRTIM_ADC2R_AD2TERST_Msk (0x1U << HRTIM_ADC2R_AD2TERST_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 10417 #define HRTIM_ADC2R_AD2TERST HRTIM_ADC2R_AD2TERST_Msk /*!< ADC Trigger 2 on Timer E reset */
AnnaBridge 171:3a7713b1edbc 10418
AnnaBridge 171:3a7713b1edbc 10419 /******************* Bit definition for HRTIM_ADC3R register ****************/
AnnaBridge 171:3a7713b1edbc 10420 #define HRTIM_ADC3R_AD3MC1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10421 #define HRTIM_ADC3R_AD3MC1_Msk (0x1U << HRTIM_ADC3R_AD3MC1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10422 #define HRTIM_ADC3R_AD3MC1 HRTIM_ADC3R_AD3MC1_Msk /*!< ADC Trigger 3 on master compare 1 */
AnnaBridge 171:3a7713b1edbc 10423 #define HRTIM_ADC3R_AD3MC2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10424 #define HRTIM_ADC3R_AD3MC2_Msk (0x1U << HRTIM_ADC3R_AD3MC2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10425 #define HRTIM_ADC3R_AD3MC2 HRTIM_ADC3R_AD3MC2_Msk /*!< ADC Trigger 3 on master compare 2 */
AnnaBridge 171:3a7713b1edbc 10426 #define HRTIM_ADC3R_AD3MC3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10427 #define HRTIM_ADC3R_AD3MC3_Msk (0x1U << HRTIM_ADC3R_AD3MC3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10428 #define HRTIM_ADC3R_AD3MC3 HRTIM_ADC3R_AD3MC3_Msk /*!< ADC Trigger 3 on master compare 3 */
AnnaBridge 171:3a7713b1edbc 10429 #define HRTIM_ADC3R_AD3MC4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10430 #define HRTIM_ADC3R_AD3MC4_Msk (0x1U << HRTIM_ADC3R_AD3MC4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10431 #define HRTIM_ADC3R_AD3MC4 HRTIM_ADC3R_AD3MC4_Msk /*!< ADC Trigger 3 on master compare 4 */
AnnaBridge 171:3a7713b1edbc 10432 #define HRTIM_ADC3R_AD3MPER_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10433 #define HRTIM_ADC3R_AD3MPER_Msk (0x1U << HRTIM_ADC3R_AD3MPER_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10434 #define HRTIM_ADC3R_AD3MPER HRTIM_ADC3R_AD3MPER_Msk /*!< ADC Trigger 3 on master period */
AnnaBridge 171:3a7713b1edbc 10435 #define HRTIM_ADC3R_AD3EEV1_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10436 #define HRTIM_ADC3R_AD3EEV1_Msk (0x1U << HRTIM_ADC3R_AD3EEV1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10437 #define HRTIM_ADC3R_AD3EEV1 HRTIM_ADC3R_AD3EEV1_Msk /*!< ADC Trigger 3 on external event 1 */
AnnaBridge 171:3a7713b1edbc 10438 #define HRTIM_ADC3R_AD3EEV2_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10439 #define HRTIM_ADC3R_AD3EEV2_Msk (0x1U << HRTIM_ADC3R_AD3EEV2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10440 #define HRTIM_ADC3R_AD3EEV2 HRTIM_ADC3R_AD3EEV2_Msk /*!< ADC Trigger 3 on external event 2 */
AnnaBridge 171:3a7713b1edbc 10441 #define HRTIM_ADC3R_AD3EEV3_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10442 #define HRTIM_ADC3R_AD3EEV3_Msk (0x1U << HRTIM_ADC3R_AD3EEV3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10443 #define HRTIM_ADC3R_AD3EEV3 HRTIM_ADC3R_AD3EEV3_Msk /*!< ADC Trigger 3 on external event 3 */
AnnaBridge 171:3a7713b1edbc 10444 #define HRTIM_ADC3R_AD3EEV4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10445 #define HRTIM_ADC3R_AD3EEV4_Msk (0x1U << HRTIM_ADC3R_AD3EEV4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10446 #define HRTIM_ADC3R_AD3EEV4 HRTIM_ADC3R_AD3EEV4_Msk /*!< ADC Trigger 3 on external event 4 */
AnnaBridge 171:3a7713b1edbc 10447 #define HRTIM_ADC3R_AD3EEV5_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10448 #define HRTIM_ADC3R_AD3EEV5_Msk (0x1U << HRTIM_ADC3R_AD3EEV5_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10449 #define HRTIM_ADC3R_AD3EEV5 HRTIM_ADC3R_AD3EEV5_Msk /*!< ADC Trigger 3 on external event 5 */
AnnaBridge 171:3a7713b1edbc 10450 #define HRTIM_ADC3R_AD3TAC2_Pos (10U)
AnnaBridge 171:3a7713b1edbc 10451 #define HRTIM_ADC3R_AD3TAC2_Msk (0x1U << HRTIM_ADC3R_AD3TAC2_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10452 #define HRTIM_ADC3R_AD3TAC2 HRTIM_ADC3R_AD3TAC2_Msk /*!< ADC Trigger 3 on Timer A compare 2 */
AnnaBridge 171:3a7713b1edbc 10453 #define HRTIM_ADC3R_AD3TAC3_Pos (11U)
AnnaBridge 171:3a7713b1edbc 10454 #define HRTIM_ADC3R_AD3TAC3_Msk (0x1U << HRTIM_ADC3R_AD3TAC3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10455 #define HRTIM_ADC3R_AD3TAC3 HRTIM_ADC3R_AD3TAC3_Msk /*!< ADC Trigger 3 on Timer A compare 3 */
AnnaBridge 171:3a7713b1edbc 10456 #define HRTIM_ADC3R_AD3TAC4_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10457 #define HRTIM_ADC3R_AD3TAC4_Msk (0x1U << HRTIM_ADC3R_AD3TAC4_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10458 #define HRTIM_ADC3R_AD3TAC4 HRTIM_ADC3R_AD3TAC4_Msk /*!< ADC Trigger 3 on Timer A compare 4 */
AnnaBridge 171:3a7713b1edbc 10459 #define HRTIM_ADC3R_AD3TAPER_Pos (13U)
AnnaBridge 171:3a7713b1edbc 10460 #define HRTIM_ADC3R_AD3TAPER_Msk (0x1U << HRTIM_ADC3R_AD3TAPER_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10461 #define HRTIM_ADC3R_AD3TAPER HRTIM_ADC3R_AD3TAPER_Msk /*!< ADC Trigger 3 on Timer A period */
AnnaBridge 171:3a7713b1edbc 10462 #define HRTIM_ADC3R_AD3TARST_Pos (14U)
AnnaBridge 171:3a7713b1edbc 10463 #define HRTIM_ADC3R_AD3TARST_Msk (0x1U << HRTIM_ADC3R_AD3TARST_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10464 #define HRTIM_ADC3R_AD3TARST HRTIM_ADC3R_AD3TARST_Msk /*!< ADC Trigger 3 on Timer A reset */
AnnaBridge 171:3a7713b1edbc 10465 #define HRTIM_ADC3R_AD3TBC2_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10466 #define HRTIM_ADC3R_AD3TBC2_Msk (0x1U << HRTIM_ADC3R_AD3TBC2_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10467 #define HRTIM_ADC3R_AD3TBC2 HRTIM_ADC3R_AD3TBC2_Msk /*!< ADC Trigger 3 on Timer B compare 2 */
AnnaBridge 171:3a7713b1edbc 10468 #define HRTIM_ADC3R_AD3TBC3_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10469 #define HRTIM_ADC3R_AD3TBC3_Msk (0x1U << HRTIM_ADC3R_AD3TBC3_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10470 #define HRTIM_ADC3R_AD3TBC3 HRTIM_ADC3R_AD3TBC3_Msk /*!< ADC Trigger 3 on Timer B compare 3 */
AnnaBridge 171:3a7713b1edbc 10471 #define HRTIM_ADC3R_AD3TBC4_Pos (17U)
AnnaBridge 171:3a7713b1edbc 10472 #define HRTIM_ADC3R_AD3TBC4_Msk (0x1U << HRTIM_ADC3R_AD3TBC4_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10473 #define HRTIM_ADC3R_AD3TBC4 HRTIM_ADC3R_AD3TBC4_Msk /*!< ADC Trigger 3 on Timer B compare 4 */
AnnaBridge 171:3a7713b1edbc 10474 #define HRTIM_ADC3R_AD3TBPER_Pos (18U)
AnnaBridge 171:3a7713b1edbc 10475 #define HRTIM_ADC3R_AD3TBPER_Msk (0x1U << HRTIM_ADC3R_AD3TBPER_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10476 #define HRTIM_ADC3R_AD3TBPER HRTIM_ADC3R_AD3TBPER_Msk /*!< ADC Trigger 3 on Timer B period */
AnnaBridge 171:3a7713b1edbc 10477 #define HRTIM_ADC3R_AD3TBRST_Pos (19U)
AnnaBridge 171:3a7713b1edbc 10478 #define HRTIM_ADC3R_AD3TBRST_Msk (0x1U << HRTIM_ADC3R_AD3TBRST_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 10479 #define HRTIM_ADC3R_AD3TBRST HRTIM_ADC3R_AD3TBRST_Msk /*!< ADC Trigger 3 on Timer B reset */
AnnaBridge 171:3a7713b1edbc 10480 #define HRTIM_ADC3R_AD3TCC2_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10481 #define HRTIM_ADC3R_AD3TCC2_Msk (0x1U << HRTIM_ADC3R_AD3TCC2_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10482 #define HRTIM_ADC3R_AD3TCC2 HRTIM_ADC3R_AD3TCC2_Msk /*!< ADC Trigger 3 on Timer C compare 2 */
AnnaBridge 171:3a7713b1edbc 10483 #define HRTIM_ADC3R_AD3TCC3_Pos (21U)
AnnaBridge 171:3a7713b1edbc 10484 #define HRTIM_ADC3R_AD3TCC3_Msk (0x1U << HRTIM_ADC3R_AD3TCC3_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10485 #define HRTIM_ADC3R_AD3TCC3 HRTIM_ADC3R_AD3TCC3_Msk /*!< ADC Trigger 3 on Timer C compare 3 */
AnnaBridge 171:3a7713b1edbc 10486 #define HRTIM_ADC3R_AD3TCC4_Pos (22U)
AnnaBridge 171:3a7713b1edbc 10487 #define HRTIM_ADC3R_AD3TCC4_Msk (0x1U << HRTIM_ADC3R_AD3TCC4_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10488 #define HRTIM_ADC3R_AD3TCC4 HRTIM_ADC3R_AD3TCC4_Msk /*!< ADC Trigger 3 on Timer C compare 4 */
AnnaBridge 171:3a7713b1edbc 10489 #define HRTIM_ADC3R_AD3TCPER_Pos (23U)
AnnaBridge 171:3a7713b1edbc 10490 #define HRTIM_ADC3R_AD3TCPER_Msk (0x1U << HRTIM_ADC3R_AD3TCPER_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 10491 #define HRTIM_ADC3R_AD3TCPER HRTIM_ADC3R_AD3TCPER_Msk /*!< ADC Trigger 3 on Timer C period */
AnnaBridge 171:3a7713b1edbc 10492 #define HRTIM_ADC3R_AD3TDC2_Pos (24U)
AnnaBridge 171:3a7713b1edbc 10493 #define HRTIM_ADC3R_AD3TDC2_Msk (0x1U << HRTIM_ADC3R_AD3TDC2_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 10494 #define HRTIM_ADC3R_AD3TDC2 HRTIM_ADC3R_AD3TDC2_Msk /*!< ADC Trigger 3 on Timer D compare 2 */
AnnaBridge 171:3a7713b1edbc 10495 #define HRTIM_ADC3R_AD3TDC3_Pos (25U)
AnnaBridge 171:3a7713b1edbc 10496 #define HRTIM_ADC3R_AD3TDC3_Msk (0x1U << HRTIM_ADC3R_AD3TDC3_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10497 #define HRTIM_ADC3R_AD3TDC3 HRTIM_ADC3R_AD3TDC3_Msk /*!< ADC Trigger 3 on Timer D compare 3 */
AnnaBridge 171:3a7713b1edbc 10498 #define HRTIM_ADC3R_AD3TDC4_Pos (26U)
AnnaBridge 171:3a7713b1edbc 10499 #define HRTIM_ADC3R_AD3TDC4_Msk (0x1U << HRTIM_ADC3R_AD3TDC4_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10500 #define HRTIM_ADC3R_AD3TDC4 HRTIM_ADC3R_AD3TDC4_Msk /*!< ADC Trigger 3 on Timer D compare 4 */
AnnaBridge 171:3a7713b1edbc 10501 #define HRTIM_ADC3R_AD3TDPER_Pos (27U)
AnnaBridge 171:3a7713b1edbc 10502 #define HRTIM_ADC3R_AD3TDPER_Msk (0x1U << HRTIM_ADC3R_AD3TDPER_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10503 #define HRTIM_ADC3R_AD3TDPER HRTIM_ADC3R_AD3TDPER_Msk /*!< ADC Trigger 3 on Timer D period */
AnnaBridge 171:3a7713b1edbc 10504 #define HRTIM_ADC3R_AD3TEC2_Pos (28U)
AnnaBridge 171:3a7713b1edbc 10505 #define HRTIM_ADC3R_AD3TEC2_Msk (0x1U << HRTIM_ADC3R_AD3TEC2_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 10506 #define HRTIM_ADC3R_AD3TEC2 HRTIM_ADC3R_AD3TEC2_Msk /*!< ADC Trigger 3 on Timer E compare 2 */
AnnaBridge 171:3a7713b1edbc 10507 #define HRTIM_ADC3R_AD3TEC3_Pos (29U)
AnnaBridge 171:3a7713b1edbc 10508 #define HRTIM_ADC3R_AD3TEC3_Msk (0x1U << HRTIM_ADC3R_AD3TEC3_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 10509 #define HRTIM_ADC3R_AD3TEC3 HRTIM_ADC3R_AD3TEC3_Msk /*!< ADC Trigger 3 on Timer E compare 3 */
AnnaBridge 171:3a7713b1edbc 10510 #define HRTIM_ADC3R_AD3TEC4_Pos (30U)
AnnaBridge 171:3a7713b1edbc 10511 #define HRTIM_ADC3R_AD3TEC4_Msk (0x1U << HRTIM_ADC3R_AD3TEC4_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 10512 #define HRTIM_ADC3R_AD3TEC4 HRTIM_ADC3R_AD3TEC4_Msk /*!< ADC Trigger 3 on Timer E compare 4 */
AnnaBridge 171:3a7713b1edbc 10513 #define HRTIM_ADC3R_AD3TEPER_Pos (31U)
AnnaBridge 171:3a7713b1edbc 10514 #define HRTIM_ADC3R_AD3TEPER_Msk (0x1U << HRTIM_ADC3R_AD3TEPER_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 10515 #define HRTIM_ADC3R_AD3TEPER HRTIM_ADC3R_AD3TEPER_Msk /*!< ADC Trigger 3 on Timer E period */
AnnaBridge 171:3a7713b1edbc 10516
AnnaBridge 171:3a7713b1edbc 10517 /******************* Bit definition for HRTIM_ADC4R register ****************/
AnnaBridge 171:3a7713b1edbc 10518 #define HRTIM_ADC4R_AD4MC1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10519 #define HRTIM_ADC4R_AD4MC1_Msk (0x1U << HRTIM_ADC4R_AD4MC1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10520 #define HRTIM_ADC4R_AD4MC1 HRTIM_ADC4R_AD4MC1_Msk /*!< ADC Trigger 4 on master compare 1 */
AnnaBridge 171:3a7713b1edbc 10521 #define HRTIM_ADC4R_AD4MC2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10522 #define HRTIM_ADC4R_AD4MC2_Msk (0x1U << HRTIM_ADC4R_AD4MC2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10523 #define HRTIM_ADC4R_AD4MC2 HRTIM_ADC4R_AD4MC2_Msk /*!< ADC Trigger 4 on master compare 2 */
AnnaBridge 171:3a7713b1edbc 10524 #define HRTIM_ADC4R_AD4MC3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10525 #define HRTIM_ADC4R_AD4MC3_Msk (0x1U << HRTIM_ADC4R_AD4MC3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10526 #define HRTIM_ADC4R_AD4MC3 HRTIM_ADC4R_AD4MC3_Msk /*!< ADC Trigger 4 on master compare 3 */
AnnaBridge 171:3a7713b1edbc 10527 #define HRTIM_ADC4R_AD4MC4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10528 #define HRTIM_ADC4R_AD4MC4_Msk (0x1U << HRTIM_ADC4R_AD4MC4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10529 #define HRTIM_ADC4R_AD4MC4 HRTIM_ADC4R_AD4MC4_Msk /*!< ADC Trigger 4 on master compare 4 */
AnnaBridge 171:3a7713b1edbc 10530 #define HRTIM_ADC4R_AD4MPER_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10531 #define HRTIM_ADC4R_AD4MPER_Msk (0x1U << HRTIM_ADC4R_AD4MPER_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10532 #define HRTIM_ADC4R_AD4MPER HRTIM_ADC4R_AD4MPER_Msk /*!< ADC Trigger 4 on master period */
AnnaBridge 171:3a7713b1edbc 10533 #define HRTIM_ADC4R_AD4EEV6_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10534 #define HRTIM_ADC4R_AD4EEV6_Msk (0x1U << HRTIM_ADC4R_AD4EEV6_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10535 #define HRTIM_ADC4R_AD4EEV6 HRTIM_ADC4R_AD4EEV6_Msk /*!< ADC Trigger 4 on external event 6 */
AnnaBridge 171:3a7713b1edbc 10536 #define HRTIM_ADC4R_AD4EEV7_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10537 #define HRTIM_ADC4R_AD4EEV7_Msk (0x1U << HRTIM_ADC4R_AD4EEV7_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10538 #define HRTIM_ADC4R_AD4EEV7 HRTIM_ADC4R_AD4EEV7_Msk /*!< ADC Trigger 4 on external event 7 */
AnnaBridge 171:3a7713b1edbc 10539 #define HRTIM_ADC4R_AD4EEV8_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10540 #define HRTIM_ADC4R_AD4EEV8_Msk (0x1U << HRTIM_ADC4R_AD4EEV8_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10541 #define HRTIM_ADC4R_AD4EEV8 HRTIM_ADC4R_AD4EEV8_Msk /*!< ADC Trigger 4 on external event 8 */
AnnaBridge 171:3a7713b1edbc 10542 #define HRTIM_ADC4R_AD4EEV9_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10543 #define HRTIM_ADC4R_AD4EEV9_Msk (0x1U << HRTIM_ADC4R_AD4EEV9_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10544 #define HRTIM_ADC4R_AD4EEV9 HRTIM_ADC4R_AD4EEV9_Msk /*!< ADC Trigger 4 on external event 9 */
AnnaBridge 171:3a7713b1edbc 10545 #define HRTIM_ADC4R_AD4EEV10_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10546 #define HRTIM_ADC4R_AD4EEV10_Msk (0x1U << HRTIM_ADC4R_AD4EEV10_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10547 #define HRTIM_ADC4R_AD4EEV10 HRTIM_ADC4R_AD4EEV10_Msk /*!< ADC Trigger 4 on external event 10 */
AnnaBridge 171:3a7713b1edbc 10548 #define HRTIM_ADC4R_AD4TAC2_Pos (10U)
AnnaBridge 171:3a7713b1edbc 10549 #define HRTIM_ADC4R_AD4TAC2_Msk (0x1U << HRTIM_ADC4R_AD4TAC2_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10550 #define HRTIM_ADC4R_AD4TAC2 HRTIM_ADC4R_AD4TAC2_Msk /*!< ADC Trigger 4 on Timer A compare 2 */
AnnaBridge 171:3a7713b1edbc 10551 #define HRTIM_ADC4R_AD4TAC3_Pos (11U)
AnnaBridge 171:3a7713b1edbc 10552 #define HRTIM_ADC4R_AD4TAC3_Msk (0x1U << HRTIM_ADC4R_AD4TAC3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10553 #define HRTIM_ADC4R_AD4TAC3 HRTIM_ADC4R_AD4TAC3_Msk /*!< ADC Trigger 4 on Timer A compare 3 */
AnnaBridge 171:3a7713b1edbc 10554 #define HRTIM_ADC4R_AD4TAC4_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10555 #define HRTIM_ADC4R_AD4TAC4_Msk (0x1U << HRTIM_ADC4R_AD4TAC4_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10556 #define HRTIM_ADC4R_AD4TAC4 HRTIM_ADC4R_AD4TAC4_Msk /*!< ADC Trigger 4 on Timer A compare 4*/
AnnaBridge 171:3a7713b1edbc 10557 #define HRTIM_ADC4R_AD4TAPER_Pos (13U)
AnnaBridge 171:3a7713b1edbc 10558 #define HRTIM_ADC4R_AD4TAPER_Msk (0x1U << HRTIM_ADC4R_AD4TAPER_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10559 #define HRTIM_ADC4R_AD4TAPER HRTIM_ADC4R_AD4TAPER_Msk /*!< ADC Trigger 4 on Timer A period */
AnnaBridge 171:3a7713b1edbc 10560 #define HRTIM_ADC4R_AD4TBC2_Pos (14U)
AnnaBridge 171:3a7713b1edbc 10561 #define HRTIM_ADC4R_AD4TBC2_Msk (0x1U << HRTIM_ADC4R_AD4TBC2_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10562 #define HRTIM_ADC4R_AD4TBC2 HRTIM_ADC4R_AD4TBC2_Msk /*!< ADC Trigger 4 on Timer B compare 2 */
AnnaBridge 171:3a7713b1edbc 10563 #define HRTIM_ADC4R_AD4TBC3_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10564 #define HRTIM_ADC4R_AD4TBC3_Msk (0x1U << HRTIM_ADC4R_AD4TBC3_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10565 #define HRTIM_ADC4R_AD4TBC3 HRTIM_ADC4R_AD4TBC3_Msk /*!< ADC Trigger 4 on Timer B compare 3 */
AnnaBridge 171:3a7713b1edbc 10566 #define HRTIM_ADC4R_AD4TBC4_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10567 #define HRTIM_ADC4R_AD4TBC4_Msk (0x1U << HRTIM_ADC4R_AD4TBC4_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10568 #define HRTIM_ADC4R_AD4TBC4 HRTIM_ADC4R_AD4TBC4_Msk /*!< ADC Trigger 4 on Timer B compare 4 */
AnnaBridge 171:3a7713b1edbc 10569 #define HRTIM_ADC4R_AD4TBPER_Pos (17U)
AnnaBridge 171:3a7713b1edbc 10570 #define HRTIM_ADC4R_AD4TBPER_Msk (0x1U << HRTIM_ADC4R_AD4TBPER_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10571 #define HRTIM_ADC4R_AD4TBPER HRTIM_ADC4R_AD4TBPER_Msk /*!< ADC Trigger 4 on Timer B period */
AnnaBridge 171:3a7713b1edbc 10572 #define HRTIM_ADC4R_AD4TCC2_Pos (18U)
AnnaBridge 171:3a7713b1edbc 10573 #define HRTIM_ADC4R_AD4TCC2_Msk (0x1U << HRTIM_ADC4R_AD4TCC2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10574 #define HRTIM_ADC4R_AD4TCC2 HRTIM_ADC4R_AD4TCC2_Msk /*!< ADC Trigger 4 on Timer C compare 2 */
AnnaBridge 171:3a7713b1edbc 10575 #define HRTIM_ADC4R_AD4TCC3_Pos (19U)
AnnaBridge 171:3a7713b1edbc 10576 #define HRTIM_ADC4R_AD4TCC3_Msk (0x1U << HRTIM_ADC4R_AD4TCC3_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 10577 #define HRTIM_ADC4R_AD4TCC3 HRTIM_ADC4R_AD4TCC3_Msk /*!< ADC Trigger 4 on Timer C compare 3 */
AnnaBridge 171:3a7713b1edbc 10578 #define HRTIM_ADC4R_AD4TCC4_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10579 #define HRTIM_ADC4R_AD4TCC4_Msk (0x1U << HRTIM_ADC4R_AD4TCC4_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10580 #define HRTIM_ADC4R_AD4TCC4 HRTIM_ADC4R_AD4TCC4_Msk /*!< ADC Trigger 4 on Timer C compare 4 */
AnnaBridge 171:3a7713b1edbc 10581 #define HRTIM_ADC4R_AD4TCPER_Pos (21U)
AnnaBridge 171:3a7713b1edbc 10582 #define HRTIM_ADC4R_AD4TCPER_Msk (0x1U << HRTIM_ADC4R_AD4TCPER_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10583 #define HRTIM_ADC4R_AD4TCPER HRTIM_ADC4R_AD4TCPER_Msk /*!< ADC Trigger 4 on Timer C period */
AnnaBridge 171:3a7713b1edbc 10584 #define HRTIM_ADC4R_AD4TCRST_Pos (22U)
AnnaBridge 171:3a7713b1edbc 10585 #define HRTIM_ADC4R_AD4TCRST_Msk (0x1U << HRTIM_ADC4R_AD4TCRST_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10586 #define HRTIM_ADC4R_AD4TCRST HRTIM_ADC4R_AD4TCRST_Msk /*!< ADC Trigger 4 on Timer C reset */
AnnaBridge 171:3a7713b1edbc 10587 #define HRTIM_ADC4R_AD4TDC2_Pos (23U)
AnnaBridge 171:3a7713b1edbc 10588 #define HRTIM_ADC4R_AD4TDC2_Msk (0x1U << HRTIM_ADC4R_AD4TDC2_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 10589 #define HRTIM_ADC4R_AD4TDC2 HRTIM_ADC4R_AD4TDC2_Msk /*!< ADC Trigger 4 on Timer D compare 2 */
AnnaBridge 171:3a7713b1edbc 10590 #define HRTIM_ADC4R_AD4TDC3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 10591 #define HRTIM_ADC4R_AD4TDC3_Msk (0x1U << HRTIM_ADC4R_AD4TDC3_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 10592 #define HRTIM_ADC4R_AD4TDC3 HRTIM_ADC4R_AD4TDC3_Msk /*!< ADC Trigger 4 on Timer D compare 3 */
AnnaBridge 171:3a7713b1edbc 10593 #define HRTIM_ADC4R_AD4TDC4_Pos (25U)
AnnaBridge 171:3a7713b1edbc 10594 #define HRTIM_ADC4R_AD4TDC4_Msk (0x1U << HRTIM_ADC4R_AD4TDC4_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10595 #define HRTIM_ADC4R_AD4TDC4 HRTIM_ADC4R_AD4TDC4_Msk /*!< ADC Trigger 4 on Timer D compare 4*/
AnnaBridge 171:3a7713b1edbc 10596 #define HRTIM_ADC4R_AD4TDPER_Pos (26U)
AnnaBridge 171:3a7713b1edbc 10597 #define HRTIM_ADC4R_AD4TDPER_Msk (0x1U << HRTIM_ADC4R_AD4TDPER_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10598 #define HRTIM_ADC4R_AD4TDPER HRTIM_ADC4R_AD4TDPER_Msk /*!< ADC Trigger 4 on Timer D period */
AnnaBridge 171:3a7713b1edbc 10599 #define HRTIM_ADC4R_AD4TDRST_Pos (27U)
AnnaBridge 171:3a7713b1edbc 10600 #define HRTIM_ADC4R_AD4TDRST_Msk (0x1U << HRTIM_ADC4R_AD4TDRST_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10601 #define HRTIM_ADC4R_AD4TDRST HRTIM_ADC4R_AD4TDRST_Msk /*!< ADC Trigger 4 on Timer D reset */
AnnaBridge 171:3a7713b1edbc 10602 #define HRTIM_ADC4R_AD4TEC2_Pos (28U)
AnnaBridge 171:3a7713b1edbc 10603 #define HRTIM_ADC4R_AD4TEC2_Msk (0x1U << HRTIM_ADC4R_AD4TEC2_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 10604 #define HRTIM_ADC4R_AD4TEC2 HRTIM_ADC4R_AD4TEC2_Msk /*!< ADC Trigger 4 on Timer E compare 2 */
AnnaBridge 171:3a7713b1edbc 10605 #define HRTIM_ADC4R_AD4TEC3_Pos (29U)
AnnaBridge 171:3a7713b1edbc 10606 #define HRTIM_ADC4R_AD4TEC3_Msk (0x1U << HRTIM_ADC4R_AD4TEC3_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 10607 #define HRTIM_ADC4R_AD4TEC3 HRTIM_ADC4R_AD4TEC3_Msk /*!< ADC Trigger 4 on Timer E compare 3 */
AnnaBridge 171:3a7713b1edbc 10608 #define HRTIM_ADC4R_AD4TEC4_Pos (30U)
AnnaBridge 171:3a7713b1edbc 10609 #define HRTIM_ADC4R_AD4TEC4_Msk (0x1U << HRTIM_ADC4R_AD4TEC4_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 10610 #define HRTIM_ADC4R_AD4TEC4 HRTIM_ADC4R_AD4TEC4_Msk /*!< ADC Trigger 4 on Timer E compare 4 */
AnnaBridge 171:3a7713b1edbc 10611 #define HRTIM_ADC4R_AD4TERST_Pos (31U)
AnnaBridge 171:3a7713b1edbc 10612 #define HRTIM_ADC4R_AD4TERST_Msk (0x1U << HRTIM_ADC4R_AD4TERST_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 10613 #define HRTIM_ADC4R_AD4TERST HRTIM_ADC4R_AD4TERST_Msk /*!< ADC Trigger 4 on Timer E reset */
AnnaBridge 171:3a7713b1edbc 10614
AnnaBridge 171:3a7713b1edbc 10615 /******************* Bit definition for HRTIM_DLLCR register ****************/
AnnaBridge 171:3a7713b1edbc 10616 #define HRTIM_DLLCR_CAL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10617 #define HRTIM_DLLCR_CAL_Msk (0x1U << HRTIM_DLLCR_CAL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10618 #define HRTIM_DLLCR_CAL HRTIM_DLLCR_CAL_Msk /*!< DLL calibration start */
AnnaBridge 171:3a7713b1edbc 10619 #define HRTIM_DLLCR_CALEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10620 #define HRTIM_DLLCR_CALEN_Msk (0x1U << HRTIM_DLLCR_CALEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10621 #define HRTIM_DLLCR_CALEN HRTIM_DLLCR_CALEN_Msk /*!< DLL calibration enable */
AnnaBridge 171:3a7713b1edbc 10622 #define HRTIM_DLLCR_CALRTE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10623 #define HRTIM_DLLCR_CALRTE_Msk (0x3U << HRTIM_DLLCR_CALRTE_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 10624 #define HRTIM_DLLCR_CALRTE HRTIM_DLLCR_CALRTE_Msk /*!< DLL calibration rate */
AnnaBridge 171:3a7713b1edbc 10625 #define HRTIM_DLLCR_CALRTE_0 (0x1U << HRTIM_DLLCR_CALRTE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10626 #define HRTIM_DLLCR_CALRTE_1 (0x2U << HRTIM_DLLCR_CALRTE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10627
AnnaBridge 171:3a7713b1edbc 10628 /******************* Bit definition for HRTIM_FLTINR1 register ***************/
AnnaBridge 171:3a7713b1edbc 10629 #define HRTIM_FLTINR1_FLT1E_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10630 #define HRTIM_FLTINR1_FLT1E_Msk (0x1U << HRTIM_FLTINR1_FLT1E_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10631 #define HRTIM_FLTINR1_FLT1E HRTIM_FLTINR1_FLT1E_Msk /*!< Fault 1 enable */
AnnaBridge 171:3a7713b1edbc 10632 #define HRTIM_FLTINR1_FLT1P_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10633 #define HRTIM_FLTINR1_FLT1P_Msk (0x1U << HRTIM_FLTINR1_FLT1P_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10634 #define HRTIM_FLTINR1_FLT1P HRTIM_FLTINR1_FLT1P_Msk /*!< Fault 1 polarity */
AnnaBridge 171:3a7713b1edbc 10635 #define HRTIM_FLTINR1_FLT1SRC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10636 #define HRTIM_FLTINR1_FLT1SRC_Msk (0x1U << HRTIM_FLTINR1_FLT1SRC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10637 #define HRTIM_FLTINR1_FLT1SRC HRTIM_FLTINR1_FLT1SRC_Msk /*!< Fault 1 source */
AnnaBridge 171:3a7713b1edbc 10638 #define HRTIM_FLTINR1_FLT1F_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10639 #define HRTIM_FLTINR1_FLT1F_Msk (0xFU << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000078 */
AnnaBridge 171:3a7713b1edbc 10640 #define HRTIM_FLTINR1_FLT1F HRTIM_FLTINR1_FLT1F_Msk /*!< Fault 1 filter */
AnnaBridge 171:3a7713b1edbc 10641 #define HRTIM_FLTINR1_FLT1F_0 (0x1U << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10642 #define HRTIM_FLTINR1_FLT1F_1 (0x2U << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10643 #define HRTIM_FLTINR1_FLT1F_2 (0x4U << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10644 #define HRTIM_FLTINR1_FLT1F_3 (0x8U << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10645 #define HRTIM_FLTINR1_FLT1LCK_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10646 #define HRTIM_FLTINR1_FLT1LCK_Msk (0x1U << HRTIM_FLTINR1_FLT1LCK_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10647 #define HRTIM_FLTINR1_FLT1LCK HRTIM_FLTINR1_FLT1LCK_Msk /*!< Fault 1 lock */
AnnaBridge 171:3a7713b1edbc 10648
AnnaBridge 171:3a7713b1edbc 10649 #define HRTIM_FLTINR1_FLT2E_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10650 #define HRTIM_FLTINR1_FLT2E_Msk (0x1U << HRTIM_FLTINR1_FLT2E_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10651 #define HRTIM_FLTINR1_FLT2E HRTIM_FLTINR1_FLT2E_Msk /*!< Fault 2 enable */
AnnaBridge 171:3a7713b1edbc 10652 #define HRTIM_FLTINR1_FLT2P_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10653 #define HRTIM_FLTINR1_FLT2P_Msk (0x1U << HRTIM_FLTINR1_FLT2P_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10654 #define HRTIM_FLTINR1_FLT2P HRTIM_FLTINR1_FLT2P_Msk /*!< Fault 2 polarity */
AnnaBridge 171:3a7713b1edbc 10655 #define HRTIM_FLTINR1_FLT2SRC_Pos (10U)
AnnaBridge 171:3a7713b1edbc 10656 #define HRTIM_FLTINR1_FLT2SRC_Msk (0x1U << HRTIM_FLTINR1_FLT2SRC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10657 #define HRTIM_FLTINR1_FLT2SRC HRTIM_FLTINR1_FLT2SRC_Msk /*!< Fault 2 source */
AnnaBridge 171:3a7713b1edbc 10658 #define HRTIM_FLTINR1_FLT2F_Pos (11U)
AnnaBridge 171:3a7713b1edbc 10659 #define HRTIM_FLTINR1_FLT2F_Msk (0xFU << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00007800 */
AnnaBridge 171:3a7713b1edbc 10660 #define HRTIM_FLTINR1_FLT2F HRTIM_FLTINR1_FLT2F_Msk /*!< Fault 2 filter */
AnnaBridge 171:3a7713b1edbc 10661 #define HRTIM_FLTINR1_FLT2F_0 (0x1U << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10662 #define HRTIM_FLTINR1_FLT2F_1 (0x2U << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10663 #define HRTIM_FLTINR1_FLT2F_2 (0x4U << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10664 #define HRTIM_FLTINR1_FLT2F_3 (0x8U << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10665 #define HRTIM_FLTINR1_FLT2LCK_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10666 #define HRTIM_FLTINR1_FLT2LCK_Msk (0x1U << HRTIM_FLTINR1_FLT2LCK_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10667 #define HRTIM_FLTINR1_FLT2LCK HRTIM_FLTINR1_FLT2LCK_Msk /*!< Fault 2 lock */
AnnaBridge 171:3a7713b1edbc 10668
AnnaBridge 171:3a7713b1edbc 10669 #define HRTIM_FLTINR1_FLT3E_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10670 #define HRTIM_FLTINR1_FLT3E_Msk (0x1U << HRTIM_FLTINR1_FLT3E_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10671 #define HRTIM_FLTINR1_FLT3E HRTIM_FLTINR1_FLT3E_Msk /*!< Fault 3 enable */
AnnaBridge 171:3a7713b1edbc 10672 #define HRTIM_FLTINR1_FLT3P_Pos (17U)
AnnaBridge 171:3a7713b1edbc 10673 #define HRTIM_FLTINR1_FLT3P_Msk (0x1U << HRTIM_FLTINR1_FLT3P_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10674 #define HRTIM_FLTINR1_FLT3P HRTIM_FLTINR1_FLT3P_Msk /*!< Fault 3 polarity */
AnnaBridge 171:3a7713b1edbc 10675 #define HRTIM_FLTINR1_FLT3SRC_Pos (18U)
AnnaBridge 171:3a7713b1edbc 10676 #define HRTIM_FLTINR1_FLT3SRC_Msk (0x1U << HRTIM_FLTINR1_FLT3SRC_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10677 #define HRTIM_FLTINR1_FLT3SRC HRTIM_FLTINR1_FLT3SRC_Msk /*!< Fault 3 source */
AnnaBridge 171:3a7713b1edbc 10678 #define HRTIM_FLTINR1_FLT3F_Pos (19U)
AnnaBridge 171:3a7713b1edbc 10679 #define HRTIM_FLTINR1_FLT3F_Msk (0xFU << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00780000 */
AnnaBridge 171:3a7713b1edbc 10680 #define HRTIM_FLTINR1_FLT3F HRTIM_FLTINR1_FLT3F_Msk /*!< Fault 3 filter */
AnnaBridge 171:3a7713b1edbc 10681 #define HRTIM_FLTINR1_FLT3F_0 (0x1U << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 10682 #define HRTIM_FLTINR1_FLT3F_1 (0x2U << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10683 #define HRTIM_FLTINR1_FLT3F_2 (0x4U << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10684 #define HRTIM_FLTINR1_FLT3F_3 (0x8U << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10685 #define HRTIM_FLTINR1_FLT3LCK_Pos (23U)
AnnaBridge 171:3a7713b1edbc 10686 #define HRTIM_FLTINR1_FLT3LCK_Msk (0x1U << HRTIM_FLTINR1_FLT3LCK_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 10687 #define HRTIM_FLTINR1_FLT3LCK HRTIM_FLTINR1_FLT3LCK_Msk /*!< Fault 3 lock */
AnnaBridge 171:3a7713b1edbc 10688
AnnaBridge 171:3a7713b1edbc 10689 #define HRTIM_FLTINR1_FLT4E_Pos (24U)
AnnaBridge 171:3a7713b1edbc 10690 #define HRTIM_FLTINR1_FLT4E_Msk (0x1U << HRTIM_FLTINR1_FLT4E_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 10691 #define HRTIM_FLTINR1_FLT4E HRTIM_FLTINR1_FLT4E_Msk /*!< Fault 4 enable */
AnnaBridge 171:3a7713b1edbc 10692 #define HRTIM_FLTINR1_FLT4P_Pos (25U)
AnnaBridge 171:3a7713b1edbc 10693 #define HRTIM_FLTINR1_FLT4P_Msk (0x1U << HRTIM_FLTINR1_FLT4P_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10694 #define HRTIM_FLTINR1_FLT4P HRTIM_FLTINR1_FLT4P_Msk /*!< Fault 4 polarity */
AnnaBridge 171:3a7713b1edbc 10695 #define HRTIM_FLTINR1_FLT4SRC_Pos (26U)
AnnaBridge 171:3a7713b1edbc 10696 #define HRTIM_FLTINR1_FLT4SRC_Msk (0x1U << HRTIM_FLTINR1_FLT4SRC_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10697 #define HRTIM_FLTINR1_FLT4SRC HRTIM_FLTINR1_FLT4SRC_Msk /*!< Fault 4 source */
AnnaBridge 171:3a7713b1edbc 10698 #define HRTIM_FLTINR1_FLT4F_Pos (27U)
AnnaBridge 171:3a7713b1edbc 10699 #define HRTIM_FLTINR1_FLT4F_Msk (0xFU << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x78000000 */
AnnaBridge 171:3a7713b1edbc 10700 #define HRTIM_FLTINR1_FLT4F HRTIM_FLTINR1_FLT4F_Msk /*!< Fault 4 filter */
AnnaBridge 171:3a7713b1edbc 10701 #define HRTIM_FLTINR1_FLT4F_0 (0x1U << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 10702 #define HRTIM_FLTINR1_FLT4F_1 (0x2U << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 10703 #define HRTIM_FLTINR1_FLT4F_2 (0x4U << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 10704 #define HRTIM_FLTINR1_FLT4F_3 (0x8U << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 10705 #define HRTIM_FLTINR1_FLT4LCK_Pos (31U)
AnnaBridge 171:3a7713b1edbc 10706 #define HRTIM_FLTINR1_FLT4LCK_Msk (0x1U << HRTIM_FLTINR1_FLT4LCK_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 10707 #define HRTIM_FLTINR1_FLT4LCK HRTIM_FLTINR1_FLT4LCK_Msk /*!< Fault 4 lock */
AnnaBridge 171:3a7713b1edbc 10708
AnnaBridge 171:3a7713b1edbc 10709 /******************* Bit definition for HRTIM_FLTINR2 register ***************/
AnnaBridge 171:3a7713b1edbc 10710 #define HRTIM_FLTINR2_FLT5E_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10711 #define HRTIM_FLTINR2_FLT5E_Msk (0x1U << HRTIM_FLTINR2_FLT5E_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10712 #define HRTIM_FLTINR2_FLT5E HRTIM_FLTINR2_FLT5E_Msk /*!< Fault 5 enable */
AnnaBridge 171:3a7713b1edbc 10713 #define HRTIM_FLTINR2_FLT5P_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10714 #define HRTIM_FLTINR2_FLT5P_Msk (0x1U << HRTIM_FLTINR2_FLT5P_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10715 #define HRTIM_FLTINR2_FLT5P HRTIM_FLTINR2_FLT5P_Msk /*!< Fault 5 polarity */
AnnaBridge 171:3a7713b1edbc 10716 #define HRTIM_FLTINR2_FLT5SRC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10717 #define HRTIM_FLTINR2_FLT5SRC_Msk (0x1U << HRTIM_FLTINR2_FLT5SRC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10718 #define HRTIM_FLTINR2_FLT5SRC HRTIM_FLTINR2_FLT5SRC_Msk /*!< Fault 5 source */
AnnaBridge 171:3a7713b1edbc 10719 #define HRTIM_FLTINR2_FLT5F_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10720 #define HRTIM_FLTINR2_FLT5F_Msk (0xFU << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000078 */
AnnaBridge 171:3a7713b1edbc 10721 #define HRTIM_FLTINR2_FLT5F HRTIM_FLTINR2_FLT5F_Msk /*!< Fault 5 filter */
AnnaBridge 171:3a7713b1edbc 10722 #define HRTIM_FLTINR2_FLT5F_0 (0x1U << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10723 #define HRTIM_FLTINR2_FLT5F_1 (0x2U << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10724 #define HRTIM_FLTINR2_FLT5F_2 (0x4U << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10725 #define HRTIM_FLTINR2_FLT5F_3 (0x8U << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10726 #define HRTIM_FLTINR2_FLT5LCK_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10727 #define HRTIM_FLTINR2_FLT5LCK_Msk (0x1U << HRTIM_FLTINR2_FLT5LCK_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10728 #define HRTIM_FLTINR2_FLT5LCK HRTIM_FLTINR2_FLT5LCK_Msk /*!< Fault 5 lock */
AnnaBridge 171:3a7713b1edbc 10729 #define HRTIM_FLTINR2_FLTSD_Pos (24U)
AnnaBridge 171:3a7713b1edbc 10730 #define HRTIM_FLTINR2_FLTSD_Msk (0x3U << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 10731 #define HRTIM_FLTINR2_FLTSD HRTIM_FLTINR2_FLTSD_Msk /*!< Fault sampling clock division */
AnnaBridge 171:3a7713b1edbc 10732 #define HRTIM_FLTINR2_FLTSD_0 (0x1U << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 10733 #define HRTIM_FLTINR2_FLTSD_1 (0x2U << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10734
AnnaBridge 171:3a7713b1edbc 10735 /******************* Bit definition for HRTIM_BDMUPR register ***************/
AnnaBridge 171:3a7713b1edbc 10736 #define HRTIM_BDMUPR_MCR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10737 #define HRTIM_BDMUPR_MCR_Msk (0x1U << HRTIM_BDMUPR_MCR_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10738 #define HRTIM_BDMUPR_MCR HRTIM_BDMUPR_MCR_Msk /*!< MCR register update enable */
AnnaBridge 171:3a7713b1edbc 10739 #define HRTIM_BDMUPR_MICR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10740 #define HRTIM_BDMUPR_MICR_Msk (0x1U << HRTIM_BDMUPR_MICR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10741 #define HRTIM_BDMUPR_MICR HRTIM_BDMUPR_MICR_Msk /*!< MICR register update enable */
AnnaBridge 171:3a7713b1edbc 10742 #define HRTIM_BDMUPR_MDIER_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10743 #define HRTIM_BDMUPR_MDIER_Msk (0x1U << HRTIM_BDMUPR_MDIER_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10744 #define HRTIM_BDMUPR_MDIER HRTIM_BDMUPR_MDIER_Msk /*!< MDIER register update enable */
AnnaBridge 171:3a7713b1edbc 10745 #define HRTIM_BDMUPR_MCNT_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10746 #define HRTIM_BDMUPR_MCNT_Msk (0x1U << HRTIM_BDMUPR_MCNT_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10747 #define HRTIM_BDMUPR_MCNT HRTIM_BDMUPR_MCNT_Msk /*!< MCNT register update enable */
AnnaBridge 171:3a7713b1edbc 10748 #define HRTIM_BDMUPR_MPER_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10749 #define HRTIM_BDMUPR_MPER_Msk (0x1U << HRTIM_BDMUPR_MPER_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10750 #define HRTIM_BDMUPR_MPER HRTIM_BDMUPR_MPER_Msk /*!< MPER register update enable */
AnnaBridge 171:3a7713b1edbc 10751 #define HRTIM_BDMUPR_MREP_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10752 #define HRTIM_BDMUPR_MREP_Msk (0x1U << HRTIM_BDMUPR_MREP_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10753 #define HRTIM_BDMUPR_MREP HRTIM_BDMUPR_MREP_Msk /*!< MREP register update enable */
AnnaBridge 171:3a7713b1edbc 10754 #define HRTIM_BDMUPR_MCMP1_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10755 #define HRTIM_BDMUPR_MCMP1_Msk (0x1U << HRTIM_BDMUPR_MCMP1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10756 #define HRTIM_BDMUPR_MCMP1 HRTIM_BDMUPR_MCMP1_Msk /*!< MCMP1 register update enable */
AnnaBridge 171:3a7713b1edbc 10757 #define HRTIM_BDMUPR_MCMP2_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10758 #define HRTIM_BDMUPR_MCMP2_Msk (0x1U << HRTIM_BDMUPR_MCMP2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10759 #define HRTIM_BDMUPR_MCMP2 HRTIM_BDMUPR_MCMP2_Msk /*!< MCMP2 register update enable */
AnnaBridge 171:3a7713b1edbc 10760 #define HRTIM_BDMUPR_MCMP3_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10761 #define HRTIM_BDMUPR_MCMP3_Msk (0x1U << HRTIM_BDMUPR_MCMP3_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10762 #define HRTIM_BDMUPR_MCMP3 HRTIM_BDMUPR_MCMP3_Msk /*!< MCMP3 register update enable */
AnnaBridge 171:3a7713b1edbc 10763 #define HRTIM_BDMUPR_MCMP4_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10764 #define HRTIM_BDMUPR_MCMP4_Msk (0x1U << HRTIM_BDMUPR_MCMP4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10765 #define HRTIM_BDMUPR_MCMP4 HRTIM_BDMUPR_MCMP4_Msk /*!< MPCMP4 register update enable */
AnnaBridge 171:3a7713b1edbc 10766
AnnaBridge 171:3a7713b1edbc 10767 /******************* Bit definition for HRTIM_BDTUPR register ***************/
AnnaBridge 171:3a7713b1edbc 10768 #define HRTIM_BDTUPR_TIMCR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10769 #define HRTIM_BDTUPR_TIMCR_Msk (0x1U << HRTIM_BDTUPR_TIMCR_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10770 #define HRTIM_BDTUPR_TIMCR HRTIM_BDTUPR_TIMCR_Msk /*!< TIMCR register update enable */
AnnaBridge 171:3a7713b1edbc 10771 #define HRTIM_BDTUPR_TIMICR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10772 #define HRTIM_BDTUPR_TIMICR_Msk (0x1U << HRTIM_BDTUPR_TIMICR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10773 #define HRTIM_BDTUPR_TIMICR HRTIM_BDTUPR_TIMICR_Msk /*!< TIMICR register update enable */
AnnaBridge 171:3a7713b1edbc 10774 #define HRTIM_BDTUPR_TIMDIER_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10775 #define HRTIM_BDTUPR_TIMDIER_Msk (0x1U << HRTIM_BDTUPR_TIMDIER_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10776 #define HRTIM_BDTUPR_TIMDIER HRTIM_BDTUPR_TIMDIER_Msk /*!< TIMDIER register update enable */
AnnaBridge 171:3a7713b1edbc 10777 #define HRTIM_BDTUPR_TIMCNT_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10778 #define HRTIM_BDTUPR_TIMCNT_Msk (0x1U << HRTIM_BDTUPR_TIMCNT_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10779 #define HRTIM_BDTUPR_TIMCNT HRTIM_BDTUPR_TIMCNT_Msk /*!< TIMCNT register update enable */
AnnaBridge 171:3a7713b1edbc 10780 #define HRTIM_BDTUPR_TIMPER_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10781 #define HRTIM_BDTUPR_TIMPER_Msk (0x1U << HRTIM_BDTUPR_TIMPER_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10782 #define HRTIM_BDTUPR_TIMPER HRTIM_BDTUPR_TIMPER_Msk /*!< TIMPER register update enable */
AnnaBridge 171:3a7713b1edbc 10783 #define HRTIM_BDTUPR_TIMREP_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10784 #define HRTIM_BDTUPR_TIMREP_Msk (0x1U << HRTIM_BDTUPR_TIMREP_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10785 #define HRTIM_BDTUPR_TIMREP HRTIM_BDTUPR_TIMREP_Msk /*!< TIMREP register update enable */
AnnaBridge 171:3a7713b1edbc 10786 #define HRTIM_BDTUPR_TIMCMP1_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10787 #define HRTIM_BDTUPR_TIMCMP1_Msk (0x1U << HRTIM_BDTUPR_TIMCMP1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10788 #define HRTIM_BDTUPR_TIMCMP1 HRTIM_BDTUPR_TIMCMP1_Msk /*!< TIMCMP1 register update enable */
AnnaBridge 171:3a7713b1edbc 10789 #define HRTIM_BDTUPR_TIMCMP2_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10790 #define HRTIM_BDTUPR_TIMCMP2_Msk (0x1U << HRTIM_BDTUPR_TIMCMP2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10791 #define HRTIM_BDTUPR_TIMCMP2 HRTIM_BDTUPR_TIMCMP2_Msk /*!< TIMCMP2 register update enable */
AnnaBridge 171:3a7713b1edbc 10792 #define HRTIM_BDTUPR_TIMCMP3_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10793 #define HRTIM_BDTUPR_TIMCMP3_Msk (0x1U << HRTIM_BDTUPR_TIMCMP3_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10794 #define HRTIM_BDTUPR_TIMCMP3 HRTIM_BDTUPR_TIMCMP3_Msk /*!< TIMCMP3 register update enable */
AnnaBridge 171:3a7713b1edbc 10795 #define HRTIM_BDTUPR_TIMCMP4_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10796 #define HRTIM_BDTUPR_TIMCMP4_Msk (0x1U << HRTIM_BDTUPR_TIMCMP4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10797 #define HRTIM_BDTUPR_TIMCMP4 HRTIM_BDTUPR_TIMCMP4_Msk /*!< TIMCMP4 register update enable */
AnnaBridge 171:3a7713b1edbc 10798 #define HRTIM_BDTUPR_TIMDTR_Pos (10U)
AnnaBridge 171:3a7713b1edbc 10799 #define HRTIM_BDTUPR_TIMDTR_Msk (0x1U << HRTIM_BDTUPR_TIMDTR_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10800 #define HRTIM_BDTUPR_TIMDTR HRTIM_BDTUPR_TIMDTR_Msk /*!< TIMDTR register update enable */
AnnaBridge 171:3a7713b1edbc 10801 #define HRTIM_BDTUPR_TIMSET1R_Pos (11U)
AnnaBridge 171:3a7713b1edbc 10802 #define HRTIM_BDTUPR_TIMSET1R_Msk (0x1U << HRTIM_BDTUPR_TIMSET1R_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10803 #define HRTIM_BDTUPR_TIMSET1R HRTIM_BDTUPR_TIMSET1R_Msk /*!< TIMSET1R register update enable */
AnnaBridge 171:3a7713b1edbc 10804 #define HRTIM_BDTUPR_TIMRST1R_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10805 #define HRTIM_BDTUPR_TIMRST1R_Msk (0x1U << HRTIM_BDTUPR_TIMRST1R_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10806 #define HRTIM_BDTUPR_TIMRST1R HRTIM_BDTUPR_TIMRST1R_Msk /*!< TIMRST1R register update enable */
AnnaBridge 171:3a7713b1edbc 10807 #define HRTIM_BDTUPR_TIMSET2R_Pos (13U)
AnnaBridge 171:3a7713b1edbc 10808 #define HRTIM_BDTUPR_TIMSET2R_Msk (0x1U << HRTIM_BDTUPR_TIMSET2R_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10809 #define HRTIM_BDTUPR_TIMSET2R HRTIM_BDTUPR_TIMSET2R_Msk /*!< TIMSET2R register update enable */
AnnaBridge 171:3a7713b1edbc 10810 #define HRTIM_BDTUPR_TIMRST2R_Pos (14U)
AnnaBridge 171:3a7713b1edbc 10811 #define HRTIM_BDTUPR_TIMRST2R_Msk (0x1U << HRTIM_BDTUPR_TIMRST2R_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10812 #define HRTIM_BDTUPR_TIMRST2R HRTIM_BDTUPR_TIMRST2R_Msk /*!< TIMRST2R register update enable */
AnnaBridge 171:3a7713b1edbc 10813 #define HRTIM_BDTUPR_TIMEEFR1_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10814 #define HRTIM_BDTUPR_TIMEEFR1_Msk (0x1U << HRTIM_BDTUPR_TIMEEFR1_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10815 #define HRTIM_BDTUPR_TIMEEFR1 HRTIM_BDTUPR_TIMEEFR1_Msk /*!< TIMEEFR1 register update enable */
AnnaBridge 171:3a7713b1edbc 10816 #define HRTIM_BDTUPR_TIMEEFR2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10817 #define HRTIM_BDTUPR_TIMEEFR2_Msk (0x1U << HRTIM_BDTUPR_TIMEEFR2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10818 #define HRTIM_BDTUPR_TIMEEFR2 HRTIM_BDTUPR_TIMEEFR2_Msk /*!< TIMEEFR2 register update enable */
AnnaBridge 171:3a7713b1edbc 10819 #define HRTIM_BDTUPR_TIMRSTR_Pos (17U)
AnnaBridge 171:3a7713b1edbc 10820 #define HRTIM_BDTUPR_TIMRSTR_Msk (0x1U << HRTIM_BDTUPR_TIMRSTR_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10821 #define HRTIM_BDTUPR_TIMRSTR HRTIM_BDTUPR_TIMRSTR_Msk /*!< TIMRSTR register update enable */
AnnaBridge 171:3a7713b1edbc 10822 #define HRTIM_BDTUPR_TIMCHPR_Pos (18U)
AnnaBridge 171:3a7713b1edbc 10823 #define HRTIM_BDTUPR_TIMCHPR_Msk (0x1U << HRTIM_BDTUPR_TIMCHPR_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10824 #define HRTIM_BDTUPR_TIMCHPR HRTIM_BDTUPR_TIMCHPR_Msk /*!< TIMCHPR register update enable */
AnnaBridge 171:3a7713b1edbc 10825 #define HRTIM_BDTUPR_TIMOUTR_Pos (19U)
AnnaBridge 171:3a7713b1edbc 10826 #define HRTIM_BDTUPR_TIMOUTR_Msk (0x1U << HRTIM_BDTUPR_TIMOUTR_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 10827 #define HRTIM_BDTUPR_TIMOUTR HRTIM_BDTUPR_TIMOUTR_Msk /*!< TIMOUTR register update enable */
AnnaBridge 171:3a7713b1edbc 10828 #define HRTIM_BDTUPR_TIMFLTR_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10829 #define HRTIM_BDTUPR_TIMFLTR_Msk (0x1U << HRTIM_BDTUPR_TIMFLTR_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10830 #define HRTIM_BDTUPR_TIMFLTR HRTIM_BDTUPR_TIMFLTR_Msk /*!< TIMFLTR register update enable */
AnnaBridge 171:3a7713b1edbc 10831
AnnaBridge 171:3a7713b1edbc 10832 /******************* Bit definition for HRTIM_BDMADR register ***************/
AnnaBridge 171:3a7713b1edbc 10833 #define HRTIM_BDMADR_BDMADR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10834 #define HRTIM_BDMADR_BDMADR_Msk (0xFFFFFFFFU << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 10835 #define HRTIM_BDMADR_BDMADR HRTIM_BDMADR_BDMADR_Msk /*!< Burst DMA Data register */
AnnaBridge 171:3a7713b1edbc 10836
AnnaBridge 171:3a7713b1edbc 10837 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 10838 /* */
AnnaBridge 171:3a7713b1edbc 10839 /* Inter-integrated Circuit Interface (I2C) */
AnnaBridge 171:3a7713b1edbc 10840 /* */
AnnaBridge 171:3a7713b1edbc 10841 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 10842 /******************* Bit definition for I2C_CR1 register *******************/
AnnaBridge 171:3a7713b1edbc 10843 #define I2C_CR1_PE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10844 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 10845 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
AnnaBridge 171:3a7713b1edbc 10846 #define I2C_CR1_TXIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10847 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 10848 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
AnnaBridge 171:3a7713b1edbc 10849 #define I2C_CR1_RXIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 10850 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 10851 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
AnnaBridge 171:3a7713b1edbc 10852 #define I2C_CR1_ADDRIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 10853 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 10854 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
AnnaBridge 171:3a7713b1edbc 10855 #define I2C_CR1_NACKIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 10856 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 10857 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
AnnaBridge 171:3a7713b1edbc 10858 #define I2C_CR1_STOPIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 10859 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 10860 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
AnnaBridge 171:3a7713b1edbc 10861 #define I2C_CR1_TCIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 10862 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 10863 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
AnnaBridge 171:3a7713b1edbc 10864 #define I2C_CR1_ERRIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 10865 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 10866 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
AnnaBridge 171:3a7713b1edbc 10867 #define I2C_CR1_DNF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10868 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 10869 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
AnnaBridge 171:3a7713b1edbc 10870 #define I2C_CR1_ANFOFF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10871 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10872 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
AnnaBridge 171:3a7713b1edbc 10873 #define I2C_CR1_SWRST_Pos (13U)
AnnaBridge 171:3a7713b1edbc 10874 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10875 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
AnnaBridge 171:3a7713b1edbc 10876 #define I2C_CR1_TXDMAEN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 10877 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10878 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
AnnaBridge 171:3a7713b1edbc 10879 #define I2C_CR1_RXDMAEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10880 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10881 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
AnnaBridge 171:3a7713b1edbc 10882 #define I2C_CR1_SBC_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10883 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 10884 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
AnnaBridge 171:3a7713b1edbc 10885 #define I2C_CR1_NOSTRETCH_Pos (17U)
AnnaBridge 171:3a7713b1edbc 10886 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 10887 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
AnnaBridge 171:3a7713b1edbc 10888 #define I2C_CR1_WUPEN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 10889 #define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 10890 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
AnnaBridge 171:3a7713b1edbc 10891 #define I2C_CR1_GCEN_Pos (19U)
AnnaBridge 171:3a7713b1edbc 10892 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 10893 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
AnnaBridge 171:3a7713b1edbc 10894 #define I2C_CR1_SMBHEN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 10895 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 10896 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
AnnaBridge 171:3a7713b1edbc 10897 #define I2C_CR1_SMBDEN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 10898 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 10899 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
AnnaBridge 171:3a7713b1edbc 10900 #define I2C_CR1_ALERTEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 10901 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 10902 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
AnnaBridge 171:3a7713b1edbc 10903 #define I2C_CR1_PECEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 10904 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 10905 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
AnnaBridge 171:3a7713b1edbc 10906
AnnaBridge 171:3a7713b1edbc 10907 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 10908 #define I2C_CR1_DFN I2C_CR1_DNF
AnnaBridge 171:3a7713b1edbc 10909
AnnaBridge 171:3a7713b1edbc 10910 /****************** Bit definition for I2C_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 10911 #define I2C_CR2_SADD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10912 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 10913 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
AnnaBridge 171:3a7713b1edbc 10914 #define I2C_CR2_RD_WRN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 10915 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10916 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
AnnaBridge 171:3a7713b1edbc 10917 #define I2C_CR2_ADD10_Pos (11U)
AnnaBridge 171:3a7713b1edbc 10918 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 10919 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
AnnaBridge 171:3a7713b1edbc 10920 #define I2C_CR2_HEAD10R_Pos (12U)
AnnaBridge 171:3a7713b1edbc 10921 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 10922 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
AnnaBridge 171:3a7713b1edbc 10923 #define I2C_CR2_START_Pos (13U)
AnnaBridge 171:3a7713b1edbc 10924 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 10925 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
AnnaBridge 171:3a7713b1edbc 10926 #define I2C_CR2_STOP_Pos (14U)
AnnaBridge 171:3a7713b1edbc 10927 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 10928 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
AnnaBridge 171:3a7713b1edbc 10929 #define I2C_CR2_NACK_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10930 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10931 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
AnnaBridge 171:3a7713b1edbc 10932 #define I2C_CR2_NBYTES_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10933 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 10934 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
AnnaBridge 171:3a7713b1edbc 10935 #define I2C_CR2_RELOAD_Pos (24U)
AnnaBridge 171:3a7713b1edbc 10936 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 10937 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
AnnaBridge 171:3a7713b1edbc 10938 #define I2C_CR2_AUTOEND_Pos (25U)
AnnaBridge 171:3a7713b1edbc 10939 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 10940 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
AnnaBridge 171:3a7713b1edbc 10941 #define I2C_CR2_PECBYTE_Pos (26U)
AnnaBridge 171:3a7713b1edbc 10942 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 10943 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
AnnaBridge 171:3a7713b1edbc 10944
AnnaBridge 171:3a7713b1edbc 10945 /******************* Bit definition for I2C_OAR1 register ******************/
AnnaBridge 171:3a7713b1edbc 10946 #define I2C_OAR1_OA1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10947 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 10948 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
AnnaBridge 171:3a7713b1edbc 10949 #define I2C_OAR1_OA1MODE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 10950 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10951 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
AnnaBridge 171:3a7713b1edbc 10952 #define I2C_OAR1_OA1EN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10953 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10954 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
AnnaBridge 171:3a7713b1edbc 10955
AnnaBridge 171:3a7713b1edbc 10956 /******************* Bit definition for I2C_OAR2 register *******************/
AnnaBridge 171:3a7713b1edbc 10957 #define I2C_OAR2_OA2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 10958 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
AnnaBridge 171:3a7713b1edbc 10959 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
AnnaBridge 171:3a7713b1edbc 10960 #define I2C_OAR2_OA2MSK_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10961 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 10962 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
AnnaBridge 171:3a7713b1edbc 10963 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
AnnaBridge 171:3a7713b1edbc 10964 #define I2C_OAR2_OA2MASK01_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10965 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 10966 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
AnnaBridge 171:3a7713b1edbc 10967 #define I2C_OAR2_OA2MASK02_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10968 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 10969 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
AnnaBridge 171:3a7713b1edbc 10970 #define I2C_OAR2_OA2MASK03_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10971 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 10972 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
AnnaBridge 171:3a7713b1edbc 10973 #define I2C_OAR2_OA2MASK04_Pos (10U)
AnnaBridge 171:3a7713b1edbc 10974 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 10975 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
AnnaBridge 171:3a7713b1edbc 10976 #define I2C_OAR2_OA2MASK05_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10977 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
AnnaBridge 171:3a7713b1edbc 10978 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
AnnaBridge 171:3a7713b1edbc 10979 #define I2C_OAR2_OA2MASK06_Pos (9U)
AnnaBridge 171:3a7713b1edbc 10980 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 10981 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
AnnaBridge 171:3a7713b1edbc 10982 #define I2C_OAR2_OA2MASK07_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10983 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 10984 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
AnnaBridge 171:3a7713b1edbc 10985 #define I2C_OAR2_OA2EN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 10986 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 10987 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
AnnaBridge 171:3a7713b1edbc 10988
AnnaBridge 171:3a7713b1edbc 10989 /******************* Bit definition for I2C_TIMINGR register *****************/
AnnaBridge 171:3a7713b1edbc 10990 #define I2C_TIMINGR_SCLL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 10991 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 10992 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
AnnaBridge 171:3a7713b1edbc 10993 #define I2C_TIMINGR_SCLH_Pos (8U)
AnnaBridge 171:3a7713b1edbc 10994 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 10995 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
AnnaBridge 171:3a7713b1edbc 10996 #define I2C_TIMINGR_SDADEL_Pos (16U)
AnnaBridge 171:3a7713b1edbc 10997 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 10998 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
AnnaBridge 171:3a7713b1edbc 10999 #define I2C_TIMINGR_SCLDEL_Pos (20U)
AnnaBridge 171:3a7713b1edbc 11000 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 11001 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
AnnaBridge 171:3a7713b1edbc 11002 #define I2C_TIMINGR_PRESC_Pos (28U)
AnnaBridge 171:3a7713b1edbc 11003 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
AnnaBridge 171:3a7713b1edbc 11004 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
AnnaBridge 171:3a7713b1edbc 11005
AnnaBridge 171:3a7713b1edbc 11006 /******************* Bit definition for I2C_TIMEOUTR register *****************/
AnnaBridge 171:3a7713b1edbc 11007 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11008 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 11009 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
AnnaBridge 171:3a7713b1edbc 11010 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11011 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11012 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
AnnaBridge 171:3a7713b1edbc 11013 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 11014 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11015 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
AnnaBridge 171:3a7713b1edbc 11016 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11017 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
AnnaBridge 171:3a7713b1edbc 11018 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
AnnaBridge 171:3a7713b1edbc 11019 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 11020 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 11021 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
AnnaBridge 171:3a7713b1edbc 11022
AnnaBridge 171:3a7713b1edbc 11023 /****************** Bit definition for I2C_ISR register *********************/
AnnaBridge 171:3a7713b1edbc 11024 #define I2C_ISR_TXE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11025 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11026 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
AnnaBridge 171:3a7713b1edbc 11027 #define I2C_ISR_TXIS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11028 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11029 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
AnnaBridge 171:3a7713b1edbc 11030 #define I2C_ISR_RXNE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11031 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11032 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
AnnaBridge 171:3a7713b1edbc 11033 #define I2C_ISR_ADDR_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11034 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11035 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
AnnaBridge 171:3a7713b1edbc 11036 #define I2C_ISR_NACKF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11037 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11038 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
AnnaBridge 171:3a7713b1edbc 11039 #define I2C_ISR_STOPF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 11040 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11041 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
AnnaBridge 171:3a7713b1edbc 11042 #define I2C_ISR_TC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 11043 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11044 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
AnnaBridge 171:3a7713b1edbc 11045 #define I2C_ISR_TCR_Pos (7U)
AnnaBridge 171:3a7713b1edbc 11046 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11047 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
AnnaBridge 171:3a7713b1edbc 11048 #define I2C_ISR_BERR_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11049 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11050 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
AnnaBridge 171:3a7713b1edbc 11051 #define I2C_ISR_ARLO_Pos (9U)
AnnaBridge 171:3a7713b1edbc 11052 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11053 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
AnnaBridge 171:3a7713b1edbc 11054 #define I2C_ISR_OVR_Pos (10U)
AnnaBridge 171:3a7713b1edbc 11055 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11056 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
AnnaBridge 171:3a7713b1edbc 11057 #define I2C_ISR_PECERR_Pos (11U)
AnnaBridge 171:3a7713b1edbc 11058 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11059 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
AnnaBridge 171:3a7713b1edbc 11060 #define I2C_ISR_TIMEOUT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11061 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11062 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
AnnaBridge 171:3a7713b1edbc 11063 #define I2C_ISR_ALERT_Pos (13U)
AnnaBridge 171:3a7713b1edbc 11064 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11065 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
AnnaBridge 171:3a7713b1edbc 11066 #define I2C_ISR_BUSY_Pos (15U)
AnnaBridge 171:3a7713b1edbc 11067 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11068 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
AnnaBridge 171:3a7713b1edbc 11069 #define I2C_ISR_DIR_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11070 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11071 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
AnnaBridge 171:3a7713b1edbc 11072 #define I2C_ISR_ADDCODE_Pos (17U)
AnnaBridge 171:3a7713b1edbc 11073 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
AnnaBridge 171:3a7713b1edbc 11074 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
AnnaBridge 171:3a7713b1edbc 11075
AnnaBridge 171:3a7713b1edbc 11076 /****************** Bit definition for I2C_ICR register *********************/
AnnaBridge 171:3a7713b1edbc 11077 #define I2C_ICR_ADDRCF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11078 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11079 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
AnnaBridge 171:3a7713b1edbc 11080 #define I2C_ICR_NACKCF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11081 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11082 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
AnnaBridge 171:3a7713b1edbc 11083 #define I2C_ICR_STOPCF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 11084 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11085 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
AnnaBridge 171:3a7713b1edbc 11086 #define I2C_ICR_BERRCF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11087 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11088 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
AnnaBridge 171:3a7713b1edbc 11089 #define I2C_ICR_ARLOCF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 11090 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11091 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
AnnaBridge 171:3a7713b1edbc 11092 #define I2C_ICR_OVRCF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 11093 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11094 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
AnnaBridge 171:3a7713b1edbc 11095 #define I2C_ICR_PECCF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 11096 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11097 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
AnnaBridge 171:3a7713b1edbc 11098 #define I2C_ICR_TIMOUTCF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11099 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11100 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
AnnaBridge 171:3a7713b1edbc 11101 #define I2C_ICR_ALERTCF_Pos (13U)
AnnaBridge 171:3a7713b1edbc 11102 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11103 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
AnnaBridge 171:3a7713b1edbc 11104
AnnaBridge 171:3a7713b1edbc 11105 /****************** Bit definition for I2C_PECR register ********************/
AnnaBridge 171:3a7713b1edbc 11106 #define I2C_PECR_PEC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11107 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 11108 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
AnnaBridge 171:3a7713b1edbc 11109
AnnaBridge 171:3a7713b1edbc 11110 /****************** Bit definition for I2C_RXDR register *********************/
AnnaBridge 171:3a7713b1edbc 11111 #define I2C_RXDR_RXDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11112 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 11113 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
AnnaBridge 171:3a7713b1edbc 11114
AnnaBridge 171:3a7713b1edbc 11115 /****************** Bit definition for I2C_TXDR register *********************/
AnnaBridge 171:3a7713b1edbc 11116 #define I2C_TXDR_TXDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11117 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 11118 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
AnnaBridge 171:3a7713b1edbc 11119
AnnaBridge 171:3a7713b1edbc 11120
AnnaBridge 171:3a7713b1edbc 11121 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 11122 /* */
AnnaBridge 171:3a7713b1edbc 11123 /* Independent WATCHDOG (IWDG) */
AnnaBridge 171:3a7713b1edbc 11124 /* */
AnnaBridge 171:3a7713b1edbc 11125 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 11126 /******************* Bit definition for IWDG_KR register ********************/
AnnaBridge 171:3a7713b1edbc 11127 #define IWDG_KR_KEY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11128 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 11129 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
AnnaBridge 171:3a7713b1edbc 11130
AnnaBridge 171:3a7713b1edbc 11131 /******************* Bit definition for IWDG_PR register ********************/
AnnaBridge 171:3a7713b1edbc 11132 #define IWDG_PR_PR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11133 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 11134 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
AnnaBridge 171:3a7713b1edbc 11135 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11136 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11137 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11138
AnnaBridge 171:3a7713b1edbc 11139 /******************* Bit definition for IWDG_RLR register *******************/
AnnaBridge 171:3a7713b1edbc 11140 #define IWDG_RLR_RL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11141 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 11142 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
AnnaBridge 171:3a7713b1edbc 11143
AnnaBridge 171:3a7713b1edbc 11144 /******************* Bit definition for IWDG_SR register ********************/
AnnaBridge 171:3a7713b1edbc 11145 #define IWDG_SR_PVU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11146 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11147 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
AnnaBridge 171:3a7713b1edbc 11148 #define IWDG_SR_RVU_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11149 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11150 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
AnnaBridge 171:3a7713b1edbc 11151 #define IWDG_SR_WVU_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11152 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11153 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
AnnaBridge 171:3a7713b1edbc 11154
AnnaBridge 171:3a7713b1edbc 11155 /******************* Bit definition for IWDG_KR register ********************/
AnnaBridge 171:3a7713b1edbc 11156 #define IWDG_WINR_WIN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11157 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 11158 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
AnnaBridge 171:3a7713b1edbc 11159
AnnaBridge 171:3a7713b1edbc 11160 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 11161 /* */
AnnaBridge 171:3a7713b1edbc 11162 /* Power Control */
AnnaBridge 171:3a7713b1edbc 11163 /* */
AnnaBridge 171:3a7713b1edbc 11164 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 11165 #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
AnnaBridge 171:3a7713b1edbc 11166 /******************** Bit definition for PWR_CR register ********************/
AnnaBridge 171:3a7713b1edbc 11167 #define PWR_CR_LPDS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11168 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11169 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-power Deepsleep */
AnnaBridge 171:3a7713b1edbc 11170 #define PWR_CR_PDDS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11171 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11172 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
AnnaBridge 171:3a7713b1edbc 11173 #define PWR_CR_CWUF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11174 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11175 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
AnnaBridge 171:3a7713b1edbc 11176 #define PWR_CR_CSBF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11177 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11178 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
AnnaBridge 171:3a7713b1edbc 11179 #define PWR_CR_PVDE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11180 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11181 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
AnnaBridge 171:3a7713b1edbc 11182
AnnaBridge 171:3a7713b1edbc 11183 #define PWR_CR_PLS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 11184 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
AnnaBridge 171:3a7713b1edbc 11185 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
AnnaBridge 171:3a7713b1edbc 11186 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11187 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11188 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11189
AnnaBridge 171:3a7713b1edbc 11190 /*!< PVD level configuration */
AnnaBridge 171:3a7713b1edbc 11191 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
AnnaBridge 171:3a7713b1edbc 11192 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
AnnaBridge 171:3a7713b1edbc 11193 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
AnnaBridge 171:3a7713b1edbc 11194 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
AnnaBridge 171:3a7713b1edbc 11195 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
AnnaBridge 171:3a7713b1edbc 11196 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
AnnaBridge 171:3a7713b1edbc 11197 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
AnnaBridge 171:3a7713b1edbc 11198 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
AnnaBridge 171:3a7713b1edbc 11199
AnnaBridge 171:3a7713b1edbc 11200 #define PWR_CR_DBP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11201 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11202 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
AnnaBridge 171:3a7713b1edbc 11203
AnnaBridge 171:3a7713b1edbc 11204 /******************* Bit definition for PWR_CSR register ********************/
AnnaBridge 171:3a7713b1edbc 11205 #define PWR_CSR_WUF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11206 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11207 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
AnnaBridge 171:3a7713b1edbc 11208 #define PWR_CSR_SBF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11209 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11210 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
AnnaBridge 171:3a7713b1edbc 11211 #define PWR_CSR_PVDO_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11212 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11213 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
AnnaBridge 171:3a7713b1edbc 11214
AnnaBridge 171:3a7713b1edbc 11215 #define PWR_CSR_EWUP1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11216 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11217 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
AnnaBridge 171:3a7713b1edbc 11218 #define PWR_CSR_EWUP2_Pos (9U)
AnnaBridge 171:3a7713b1edbc 11219 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11220 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
AnnaBridge 171:3a7713b1edbc 11221 #define PWR_CSR_EWUP3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 11222 #define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11223 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
AnnaBridge 171:3a7713b1edbc 11224
AnnaBridge 171:3a7713b1edbc 11225 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 11226 /* */
AnnaBridge 171:3a7713b1edbc 11227 /* Reset and Clock Control */
AnnaBridge 171:3a7713b1edbc 11228 /* */
AnnaBridge 171:3a7713b1edbc 11229 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 11230 /*
AnnaBridge 171:3a7713b1edbc 11231 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
AnnaBridge 171:3a7713b1edbc 11232 */
AnnaBridge 171:3a7713b1edbc 11233
AnnaBridge 171:3a7713b1edbc 11234 /******************** Bit definition for RCC_CR register ********************/
AnnaBridge 171:3a7713b1edbc 11235 #define RCC_CR_HSION_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11236 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11237 #define RCC_CR_HSION RCC_CR_HSION_Msk
AnnaBridge 171:3a7713b1edbc 11238 #define RCC_CR_HSIRDY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11239 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11240 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
AnnaBridge 171:3a7713b1edbc 11241
AnnaBridge 171:3a7713b1edbc 11242 #define RCC_CR_HSITRIM_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11243 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
AnnaBridge 171:3a7713b1edbc 11244 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
AnnaBridge 171:3a7713b1edbc 11245 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11246 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11247 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11248 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11249 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11250
AnnaBridge 171:3a7713b1edbc 11251 #define RCC_CR_HSICAL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11252 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 11253 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
AnnaBridge 171:3a7713b1edbc 11254 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11255 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11256 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11257 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11258 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11259 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11260 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11261 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11262
AnnaBridge 171:3a7713b1edbc 11263 #define RCC_CR_HSEON_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11264 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11265 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
AnnaBridge 171:3a7713b1edbc 11266 #define RCC_CR_HSERDY_Pos (17U)
AnnaBridge 171:3a7713b1edbc 11267 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11268 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
AnnaBridge 171:3a7713b1edbc 11269 #define RCC_CR_HSEBYP_Pos (18U)
AnnaBridge 171:3a7713b1edbc 11270 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11271 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
AnnaBridge 171:3a7713b1edbc 11272 #define RCC_CR_CSSON_Pos (19U)
AnnaBridge 171:3a7713b1edbc 11273 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 11274 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
AnnaBridge 171:3a7713b1edbc 11275 #define RCC_CR_PLLON_Pos (24U)
AnnaBridge 171:3a7713b1edbc 11276 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 11277 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
AnnaBridge 171:3a7713b1edbc 11278 #define RCC_CR_PLLRDY_Pos (25U)
AnnaBridge 171:3a7713b1edbc 11279 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 11280 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
AnnaBridge 171:3a7713b1edbc 11281
AnnaBridge 171:3a7713b1edbc 11282 /******************** Bit definition for RCC_CFGR register ******************/
AnnaBridge 171:3a7713b1edbc 11283 /*!< SW configuration */
AnnaBridge 171:3a7713b1edbc 11284 #define RCC_CFGR_SW_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11285 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 11286 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
AnnaBridge 171:3a7713b1edbc 11287 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11288 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11289
AnnaBridge 171:3a7713b1edbc 11290 #define RCC_CFGR_SW_HSI (0x00000000U) /*!< HSI selected as system clock */
AnnaBridge 171:3a7713b1edbc 11291 #define RCC_CFGR_SW_HSE (0x00000001U) /*!< HSE selected as system clock */
AnnaBridge 171:3a7713b1edbc 11292 #define RCC_CFGR_SW_PLL (0x00000002U) /*!< PLL selected as system clock */
AnnaBridge 171:3a7713b1edbc 11293
AnnaBridge 171:3a7713b1edbc 11294 /*!< SWS configuration */
AnnaBridge 171:3a7713b1edbc 11295 #define RCC_CFGR_SWS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11296 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 11297 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
AnnaBridge 171:3a7713b1edbc 11298 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11299 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11300
AnnaBridge 171:3a7713b1edbc 11301 #define RCC_CFGR_SWS_HSI (0x00000000U) /*!< HSI oscillator used as system clock */
AnnaBridge 171:3a7713b1edbc 11302 #define RCC_CFGR_SWS_HSE (0x00000004U) /*!< HSE oscillator used as system clock */
AnnaBridge 171:3a7713b1edbc 11303 #define RCC_CFGR_SWS_PLL (0x00000008U) /*!< PLL used as system clock */
AnnaBridge 171:3a7713b1edbc 11304
AnnaBridge 171:3a7713b1edbc 11305 /*!< HPRE configuration */
AnnaBridge 171:3a7713b1edbc 11306 #define RCC_CFGR_HPRE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11307 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 11308 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
AnnaBridge 171:3a7713b1edbc 11309 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11310 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11311 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11312 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11313
AnnaBridge 171:3a7713b1edbc 11314 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
AnnaBridge 171:3a7713b1edbc 11315 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
AnnaBridge 171:3a7713b1edbc 11316 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
AnnaBridge 171:3a7713b1edbc 11317 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
AnnaBridge 171:3a7713b1edbc 11318 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
AnnaBridge 171:3a7713b1edbc 11319 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
AnnaBridge 171:3a7713b1edbc 11320 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
AnnaBridge 171:3a7713b1edbc 11321 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
AnnaBridge 171:3a7713b1edbc 11322 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
AnnaBridge 171:3a7713b1edbc 11323
AnnaBridge 171:3a7713b1edbc 11324 /*!< PPRE1 configuration */
AnnaBridge 171:3a7713b1edbc 11325 #define RCC_CFGR_PPRE1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11326 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 11327 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
AnnaBridge 171:3a7713b1edbc 11328 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11329 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11330 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11331
AnnaBridge 171:3a7713b1edbc 11332 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
AnnaBridge 171:3a7713b1edbc 11333 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
AnnaBridge 171:3a7713b1edbc 11334 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
AnnaBridge 171:3a7713b1edbc 11335 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
AnnaBridge 171:3a7713b1edbc 11336 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
AnnaBridge 171:3a7713b1edbc 11337
AnnaBridge 171:3a7713b1edbc 11338 /*!< PPRE2 configuration */
AnnaBridge 171:3a7713b1edbc 11339 #define RCC_CFGR_PPRE2_Pos (11U)
AnnaBridge 171:3a7713b1edbc 11340 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
AnnaBridge 171:3a7713b1edbc 11341 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
AnnaBridge 171:3a7713b1edbc 11342 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11343 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11344 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11345
AnnaBridge 171:3a7713b1edbc 11346 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
AnnaBridge 171:3a7713b1edbc 11347 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
AnnaBridge 171:3a7713b1edbc 11348 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
AnnaBridge 171:3a7713b1edbc 11349 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
AnnaBridge 171:3a7713b1edbc 11350 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
AnnaBridge 171:3a7713b1edbc 11351
AnnaBridge 171:3a7713b1edbc 11352 #define RCC_CFGR_PLLSRC_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11353 #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11354 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
AnnaBridge 171:3a7713b1edbc 11355 #define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */
AnnaBridge 171:3a7713b1edbc 11356 #define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /*!< HSE/PREDIV clock selected as PLL entry clock source */
AnnaBridge 171:3a7713b1edbc 11357
AnnaBridge 171:3a7713b1edbc 11358 #define RCC_CFGR_PLLXTPRE_Pos (17U)
AnnaBridge 171:3a7713b1edbc 11359 #define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11360 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
AnnaBridge 171:3a7713b1edbc 11361 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U) /*!< HSE/PREDIV clock not divided for PLL entry */
AnnaBridge 171:3a7713b1edbc 11362 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
AnnaBridge 171:3a7713b1edbc 11363
AnnaBridge 171:3a7713b1edbc 11364 /*!< PLLMUL configuration */
AnnaBridge 171:3a7713b1edbc 11365 #define RCC_CFGR_PLLMUL_Pos (18U)
AnnaBridge 171:3a7713b1edbc 11366 #define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
AnnaBridge 171:3a7713b1edbc 11367 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
AnnaBridge 171:3a7713b1edbc 11368 #define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11369 #define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 11370 #define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 11371 #define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 11372
AnnaBridge 171:3a7713b1edbc 11373 #define RCC_CFGR_PLLMUL2 (0x00000000U) /*!< PLL input clock*2 */
AnnaBridge 171:3a7713b1edbc 11374 #define RCC_CFGR_PLLMUL3 (0x00040000U) /*!< PLL input clock*3 */
AnnaBridge 171:3a7713b1edbc 11375 #define RCC_CFGR_PLLMUL4 (0x00080000U) /*!< PLL input clock*4 */
AnnaBridge 171:3a7713b1edbc 11376 #define RCC_CFGR_PLLMUL5 (0x000C0000U) /*!< PLL input clock*5 */
AnnaBridge 171:3a7713b1edbc 11377 #define RCC_CFGR_PLLMUL6 (0x00100000U) /*!< PLL input clock*6 */
AnnaBridge 171:3a7713b1edbc 11378 #define RCC_CFGR_PLLMUL7 (0x00140000U) /*!< PLL input clock*7 */
AnnaBridge 171:3a7713b1edbc 11379 #define RCC_CFGR_PLLMUL8 (0x00180000U) /*!< PLL input clock*8 */
AnnaBridge 171:3a7713b1edbc 11380 #define RCC_CFGR_PLLMUL9 (0x001C0000U) /*!< PLL input clock*9 */
AnnaBridge 171:3a7713b1edbc 11381 #define RCC_CFGR_PLLMUL10 (0x00200000U) /*!< PLL input clock10 */
AnnaBridge 171:3a7713b1edbc 11382 #define RCC_CFGR_PLLMUL11 (0x00240000U) /*!< PLL input clock*11 */
AnnaBridge 171:3a7713b1edbc 11383 #define RCC_CFGR_PLLMUL12 (0x00280000U) /*!< PLL input clock*12 */
AnnaBridge 171:3a7713b1edbc 11384 #define RCC_CFGR_PLLMUL13 (0x002C0000U) /*!< PLL input clock*13 */
AnnaBridge 171:3a7713b1edbc 11385 #define RCC_CFGR_PLLMUL14 (0x00300000U) /*!< PLL input clock*14 */
AnnaBridge 171:3a7713b1edbc 11386 #define RCC_CFGR_PLLMUL15 (0x00340000U) /*!< PLL input clock*15 */
AnnaBridge 171:3a7713b1edbc 11387 #define RCC_CFGR_PLLMUL16 (0x00380000U) /*!< PLL input clock*16 */
AnnaBridge 171:3a7713b1edbc 11388
AnnaBridge 171:3a7713b1edbc 11389 /*!< MCO configuration */
AnnaBridge 171:3a7713b1edbc 11390 #define RCC_CFGR_MCO_Pos (24U)
AnnaBridge 171:3a7713b1edbc 11391 #define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
AnnaBridge 171:3a7713b1edbc 11392 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
AnnaBridge 171:3a7713b1edbc 11393 #define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 11394 #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 11395 #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 11396
AnnaBridge 171:3a7713b1edbc 11397 #define RCC_CFGR_MCO_NOCLOCK (0x00000000U) /*!< No clock */
AnnaBridge 171:3a7713b1edbc 11398 #define RCC_CFGR_MCO_LSI (0x02000000U) /*!< LSI clock selected as MCO source */
AnnaBridge 171:3a7713b1edbc 11399 #define RCC_CFGR_MCO_LSE (0x03000000U) /*!< LSE clock selected as MCO source */
AnnaBridge 171:3a7713b1edbc 11400 #define RCC_CFGR_MCO_SYSCLK (0x04000000U) /*!< System clock selected as MCO source */
AnnaBridge 171:3a7713b1edbc 11401 #define RCC_CFGR_MCO_HSI (0x05000000U) /*!< HSI clock selected as MCO source */
AnnaBridge 171:3a7713b1edbc 11402 #define RCC_CFGR_MCO_HSE (0x06000000U) /*!< HSE clock selected as MCO source */
AnnaBridge 171:3a7713b1edbc 11403 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divided by 2 selected as MCO source */
AnnaBridge 171:3a7713b1edbc 11404
AnnaBridge 171:3a7713b1edbc 11405 #define RCC_CFGR_MCOPRE_Pos (28U)
AnnaBridge 171:3a7713b1edbc 11406 #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
AnnaBridge 171:3a7713b1edbc 11407 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCOPRE[3:0] bits (Microcontroller Clock Output Prescaler) */
AnnaBridge 171:3a7713b1edbc 11408 #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 11409 #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 11410 #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 11411
AnnaBridge 171:3a7713b1edbc 11412 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
AnnaBridge 171:3a7713b1edbc 11413 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
AnnaBridge 171:3a7713b1edbc 11414 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
AnnaBridge 171:3a7713b1edbc 11415 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
AnnaBridge 171:3a7713b1edbc 11416 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
AnnaBridge 171:3a7713b1edbc 11417 #define RCC_CFGR_MCOPRE_DIV32 (0x50000000U) /*!< MCO is divided by 32 */
AnnaBridge 171:3a7713b1edbc 11418 #define RCC_CFGR_MCOPRE_DIV64 (0x60000000U) /*!< MCO is divided by 64 */
AnnaBridge 171:3a7713b1edbc 11419 #define RCC_CFGR_MCOPRE_DIV128 (0x70000000U) /*!< MCO is divided by 128 */
AnnaBridge 171:3a7713b1edbc 11420
AnnaBridge 171:3a7713b1edbc 11421 #define RCC_CFGR_PLLNODIV_Pos (31U)
AnnaBridge 171:3a7713b1edbc 11422 #define RCC_CFGR_PLLNODIV_Msk (0x1U << RCC_CFGR_PLLNODIV_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 11423 #define RCC_CFGR_PLLNODIV RCC_CFGR_PLLNODIV_Msk /*!< Do not divide PLL to MCO */
AnnaBridge 171:3a7713b1edbc 11424
AnnaBridge 171:3a7713b1edbc 11425 /* Reference defines */
AnnaBridge 171:3a7713b1edbc 11426 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
AnnaBridge 171:3a7713b1edbc 11427 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
AnnaBridge 171:3a7713b1edbc 11428 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
AnnaBridge 171:3a7713b1edbc 11429 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
AnnaBridge 171:3a7713b1edbc 11430 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
AnnaBridge 171:3a7713b1edbc 11431 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI
AnnaBridge 171:3a7713b1edbc 11432 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE
AnnaBridge 171:3a7713b1edbc 11433 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
AnnaBridge 171:3a7713b1edbc 11434 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
AnnaBridge 171:3a7713b1edbc 11435 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
AnnaBridge 171:3a7713b1edbc 11436 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
AnnaBridge 171:3a7713b1edbc 11437
AnnaBridge 171:3a7713b1edbc 11438 /********************* Bit definition for RCC_CIR register ********************/
AnnaBridge 171:3a7713b1edbc 11439 #define RCC_CIR_LSIRDYF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11440 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11441 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 11442 #define RCC_CIR_LSERDYF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11443 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11444 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 11445 #define RCC_CIR_HSIRDYF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11446 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11447 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 11448 #define RCC_CIR_HSERDYF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11449 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11450 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 11451 #define RCC_CIR_PLLRDYF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11452 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11453 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 11454 #define RCC_CIR_CSSF_Pos (7U)
AnnaBridge 171:3a7713b1edbc 11455 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11456 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
AnnaBridge 171:3a7713b1edbc 11457 #define RCC_CIR_LSIRDYIE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11458 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11459 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 11460 #define RCC_CIR_LSERDYIE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 11461 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11462 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 11463 #define RCC_CIR_HSIRDYIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 11464 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11465 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 11466 #define RCC_CIR_HSERDYIE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 11467 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11468 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 11469 #define RCC_CIR_PLLRDYIE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11470 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11471 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 11472 #define RCC_CIR_LSIRDYC_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11473 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11474 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 11475 #define RCC_CIR_LSERDYC_Pos (17U)
AnnaBridge 171:3a7713b1edbc 11476 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11477 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 11478 #define RCC_CIR_HSIRDYC_Pos (18U)
AnnaBridge 171:3a7713b1edbc 11479 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11480 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 11481 #define RCC_CIR_HSERDYC_Pos (19U)
AnnaBridge 171:3a7713b1edbc 11482 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 11483 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 11484 #define RCC_CIR_PLLRDYC_Pos (20U)
AnnaBridge 171:3a7713b1edbc 11485 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 11486 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 11487 #define RCC_CIR_CSSC_Pos (23U)
AnnaBridge 171:3a7713b1edbc 11488 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 11489 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 11490
AnnaBridge 171:3a7713b1edbc 11491 /****************** Bit definition for RCC_APB2RSTR register *****************/
AnnaBridge 171:3a7713b1edbc 11492 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11493 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11494 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
AnnaBridge 171:3a7713b1edbc 11495 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
AnnaBridge 171:3a7713b1edbc 11496 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11497 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */
AnnaBridge 171:3a7713b1edbc 11498 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11499 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11500 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
AnnaBridge 171:3a7713b1edbc 11501 #define RCC_APB2RSTR_USART1RST_Pos (14U)
AnnaBridge 171:3a7713b1edbc 11502 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11503 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
AnnaBridge 171:3a7713b1edbc 11504 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11505 #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11506 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */
AnnaBridge 171:3a7713b1edbc 11507 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
AnnaBridge 171:3a7713b1edbc 11508 #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11509 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */
AnnaBridge 171:3a7713b1edbc 11510 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
AnnaBridge 171:3a7713b1edbc 11511 #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11512 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */
AnnaBridge 171:3a7713b1edbc 11513 #define RCC_APB2RSTR_HRTIM1RST_Pos (29U)
AnnaBridge 171:3a7713b1edbc 11514 #define RCC_APB2RSTR_HRTIM1RST_Msk (0x1U << RCC_APB2RSTR_HRTIM1RST_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 11515 #define RCC_APB2RSTR_HRTIM1RST RCC_APB2RSTR_HRTIM1RST_Msk /*!< HRTIM1 reset */
AnnaBridge 171:3a7713b1edbc 11516
AnnaBridge 171:3a7713b1edbc 11517 /****************** Bit definition for RCC_APB1RSTR register ******************/
AnnaBridge 171:3a7713b1edbc 11518 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11519 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11520 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
AnnaBridge 171:3a7713b1edbc 11521 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11522 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11523 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
AnnaBridge 171:3a7713b1edbc 11524 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11525 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11526 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
AnnaBridge 171:3a7713b1edbc 11527 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
AnnaBridge 171:3a7713b1edbc 11528 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11529 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
AnnaBridge 171:3a7713b1edbc 11530 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
AnnaBridge 171:3a7713b1edbc 11531 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11532 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
AnnaBridge 171:3a7713b1edbc 11533 #define RCC_APB1RSTR_USART2RST_Pos (17U)
AnnaBridge 171:3a7713b1edbc 11534 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11535 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
AnnaBridge 171:3a7713b1edbc 11536 #define RCC_APB1RSTR_USART3RST_Pos (18U)
AnnaBridge 171:3a7713b1edbc 11537 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11538 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
AnnaBridge 171:3a7713b1edbc 11539 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
AnnaBridge 171:3a7713b1edbc 11540 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 11541 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
AnnaBridge 171:3a7713b1edbc 11542 #define RCC_APB1RSTR_CANRST_Pos (25U)
AnnaBridge 171:3a7713b1edbc 11543 #define RCC_APB1RSTR_CANRST_Msk (0x1U << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 11544 #define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN reset */
AnnaBridge 171:3a7713b1edbc 11545 #define RCC_APB1RSTR_DAC2RST_Pos (26U)
AnnaBridge 171:3a7713b1edbc 11546 #define RCC_APB1RSTR_DAC2RST_Msk (0x1U << RCC_APB1RSTR_DAC2RST_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 11547 #define RCC_APB1RSTR_DAC2RST RCC_APB1RSTR_DAC2RST_Msk /*!< DAC 2 reset */
AnnaBridge 171:3a7713b1edbc 11548 #define RCC_APB1RSTR_PWRRST_Pos (28U)
AnnaBridge 171:3a7713b1edbc 11549 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 11550 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
AnnaBridge 171:3a7713b1edbc 11551 #define RCC_APB1RSTR_DAC1RST_Pos (29U)
AnnaBridge 171:3a7713b1edbc 11552 #define RCC_APB1RSTR_DAC1RST_Msk (0x1U << RCC_APB1RSTR_DAC1RST_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 11553 #define RCC_APB1RSTR_DAC1RST RCC_APB1RSTR_DAC1RST_Msk /*!< DAC 1 reset */
AnnaBridge 171:3a7713b1edbc 11554
AnnaBridge 171:3a7713b1edbc 11555 /****************** Bit definition for RCC_AHBENR register ******************/
AnnaBridge 171:3a7713b1edbc 11556 #define RCC_AHBENR_DMA1EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11557 #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11558 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
AnnaBridge 171:3a7713b1edbc 11559 #define RCC_AHBENR_SRAMEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11560 #define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11561 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
AnnaBridge 171:3a7713b1edbc 11562 #define RCC_AHBENR_FLITFEN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11563 #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11564 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
AnnaBridge 171:3a7713b1edbc 11565 #define RCC_AHBENR_CRCEN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 11566 #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11567 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
AnnaBridge 171:3a7713b1edbc 11568 #define RCC_AHBENR_GPIOAEN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 11569 #define RCC_AHBENR_GPIOAEN_Msk (0x1U << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11570 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIOA clock enable */
AnnaBridge 171:3a7713b1edbc 11571 #define RCC_AHBENR_GPIOBEN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 11572 #define RCC_AHBENR_GPIOBEN_Msk (0x1U << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11573 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIOB clock enable */
AnnaBridge 171:3a7713b1edbc 11574 #define RCC_AHBENR_GPIOCEN_Pos (19U)
AnnaBridge 171:3a7713b1edbc 11575 #define RCC_AHBENR_GPIOCEN_Msk (0x1U << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 11576 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIOC clock enable */
AnnaBridge 171:3a7713b1edbc 11577 #define RCC_AHBENR_GPIODEN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 11578 #define RCC_AHBENR_GPIODEN_Msk (0x1U << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 11579 #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIOD clock enable */
AnnaBridge 171:3a7713b1edbc 11580 #define RCC_AHBENR_GPIOFEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 11581 #define RCC_AHBENR_GPIOFEN_Msk (0x1U << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 11582 #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIOF clock enable */
AnnaBridge 171:3a7713b1edbc 11583 #define RCC_AHBENR_TSCEN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 11584 #define RCC_AHBENR_TSCEN_Msk (0x1U << RCC_AHBENR_TSCEN_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 11585 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TS clock enable */
AnnaBridge 171:3a7713b1edbc 11586 #define RCC_AHBENR_ADC12EN_Pos (28U)
AnnaBridge 171:3a7713b1edbc 11587 #define RCC_AHBENR_ADC12EN_Msk (0x1U << RCC_AHBENR_ADC12EN_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 11588 #define RCC_AHBENR_ADC12EN RCC_AHBENR_ADC12EN_Msk /*!< ADC1/ ADC2 clock enable */
AnnaBridge 171:3a7713b1edbc 11589
AnnaBridge 171:3a7713b1edbc 11590 /***************** Bit definition for RCC_APB2ENR register ******************/
AnnaBridge 171:3a7713b1edbc 11591 #define RCC_APB2ENR_SYSCFGEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11592 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11593 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
AnnaBridge 171:3a7713b1edbc 11594 #define RCC_APB2ENR_TIM1EN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 11595 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11596 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */
AnnaBridge 171:3a7713b1edbc 11597 #define RCC_APB2ENR_SPI1EN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11598 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11599 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
AnnaBridge 171:3a7713b1edbc 11600 #define RCC_APB2ENR_USART1EN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 11601 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11602 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
AnnaBridge 171:3a7713b1edbc 11603 #define RCC_APB2ENR_TIM15EN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11604 #define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11605 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */
AnnaBridge 171:3a7713b1edbc 11606 #define RCC_APB2ENR_TIM16EN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 11607 #define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11608 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */
AnnaBridge 171:3a7713b1edbc 11609 #define RCC_APB2ENR_TIM17EN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 11610 #define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11611 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */
AnnaBridge 171:3a7713b1edbc 11612 #define RCC_APB2ENR_HRTIM1EN_Pos (29U)
AnnaBridge 171:3a7713b1edbc 11613 #define RCC_APB2ENR_HRTIM1EN_Msk (0x1U << RCC_APB2ENR_HRTIM1EN_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 11614 #define RCC_APB2ENR_HRTIM1EN RCC_APB2ENR_HRTIM1EN_Msk /*!< HRTIM1 reset */
AnnaBridge 171:3a7713b1edbc 11615
AnnaBridge 171:3a7713b1edbc 11616 /****************** Bit definition for RCC_APB1ENR register ******************/
AnnaBridge 171:3a7713b1edbc 11617 #define RCC_APB1ENR_TIM2EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11618 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11619 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
AnnaBridge 171:3a7713b1edbc 11620 #define RCC_APB1ENR_TIM3EN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11621 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11622 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
AnnaBridge 171:3a7713b1edbc 11623 #define RCC_APB1ENR_TIM6EN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11624 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11625 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
AnnaBridge 171:3a7713b1edbc 11626 #define RCC_APB1ENR_TIM7EN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 11627 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11628 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
AnnaBridge 171:3a7713b1edbc 11629 #define RCC_APB1ENR_WWDGEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 11630 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11631 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
AnnaBridge 171:3a7713b1edbc 11632 #define RCC_APB1ENR_USART2EN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 11633 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11634 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
AnnaBridge 171:3a7713b1edbc 11635 #define RCC_APB1ENR_USART3EN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 11636 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11637 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
AnnaBridge 171:3a7713b1edbc 11638 #define RCC_APB1ENR_I2C1EN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 11639 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 11640 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
AnnaBridge 171:3a7713b1edbc 11641 #define RCC_APB1ENR_CANEN_Pos (25U)
AnnaBridge 171:3a7713b1edbc 11642 #define RCC_APB1ENR_CANEN_Msk (0x1U << RCC_APB1ENR_CANEN_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 11643 #define RCC_APB1ENR_CANEN RCC_APB1ENR_CANEN_Msk /*!< CAN clock enable */
AnnaBridge 171:3a7713b1edbc 11644 #define RCC_APB1ENR_DAC2EN_Pos (26U)
AnnaBridge 171:3a7713b1edbc 11645 #define RCC_APB1ENR_DAC2EN_Msk (0x1U << RCC_APB1ENR_DAC2EN_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 11646 #define RCC_APB1ENR_DAC2EN RCC_APB1ENR_DAC2EN_Msk /*!< DAC 2 clock enable */
AnnaBridge 171:3a7713b1edbc 11647 #define RCC_APB1ENR_PWREN_Pos (28U)
AnnaBridge 171:3a7713b1edbc 11648 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 11649 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
AnnaBridge 171:3a7713b1edbc 11650 #define RCC_APB1ENR_DAC1EN_Pos (29U)
AnnaBridge 171:3a7713b1edbc 11651 #define RCC_APB1ENR_DAC1EN_Msk (0x1U << RCC_APB1ENR_DAC1EN_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 11652 #define RCC_APB1ENR_DAC1EN RCC_APB1ENR_DAC1EN_Msk /*!< DAC 1 clock enable */
AnnaBridge 171:3a7713b1edbc 11653
AnnaBridge 171:3a7713b1edbc 11654 /******************** Bit definition for RCC_BDCR register ******************/
AnnaBridge 171:3a7713b1edbc 11655 #define RCC_BDCR_LSE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11656 #define RCC_BDCR_LSE_Msk (0x7U << RCC_BDCR_LSE_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 11657 #define RCC_BDCR_LSE RCC_BDCR_LSE_Msk /*!< External Low Speed oscillator [2:0] bits */
AnnaBridge 171:3a7713b1edbc 11658 #define RCC_BDCR_LSEON_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11659 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11660 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
AnnaBridge 171:3a7713b1edbc 11661 #define RCC_BDCR_LSERDY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11662 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11663 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
AnnaBridge 171:3a7713b1edbc 11664 #define RCC_BDCR_LSEBYP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 11665 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11666 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
AnnaBridge 171:3a7713b1edbc 11667
AnnaBridge 171:3a7713b1edbc 11668 #define RCC_BDCR_LSEDRV_Pos (3U)
AnnaBridge 171:3a7713b1edbc 11669 #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
AnnaBridge 171:3a7713b1edbc 11670 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
AnnaBridge 171:3a7713b1edbc 11671 #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11672 #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11673
AnnaBridge 171:3a7713b1edbc 11674 #define RCC_BDCR_RTCSEL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11675 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 11676 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
AnnaBridge 171:3a7713b1edbc 11677 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11678 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11679
AnnaBridge 171:3a7713b1edbc 11680 /*!< RTC configuration */
AnnaBridge 171:3a7713b1edbc 11681 #define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
AnnaBridge 171:3a7713b1edbc 11682 #define RCC_BDCR_RTCSEL_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock */
AnnaBridge 171:3a7713b1edbc 11683 #define RCC_BDCR_RTCSEL_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock */
AnnaBridge 171:3a7713b1edbc 11684 #define RCC_BDCR_RTCSEL_HSE (0x00000300U) /*!< HSE oscillator clock divided by 32 used as RTC clock */
AnnaBridge 171:3a7713b1edbc 11685
AnnaBridge 171:3a7713b1edbc 11686 #define RCC_BDCR_RTCEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 11687 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11688 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
AnnaBridge 171:3a7713b1edbc 11689 #define RCC_BDCR_BDRST_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11690 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11691 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
AnnaBridge 171:3a7713b1edbc 11692
AnnaBridge 171:3a7713b1edbc 11693 /******************** Bit definition for RCC_CSR register *******************/
AnnaBridge 171:3a7713b1edbc 11694 #define RCC_CSR_LSION_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11695 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11696 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
AnnaBridge 171:3a7713b1edbc 11697 #define RCC_CSR_LSIRDY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 11698 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11699 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
AnnaBridge 171:3a7713b1edbc 11700 #define RCC_CSR_V18PWRRSTF_Pos (23U)
AnnaBridge 171:3a7713b1edbc 11701 #define RCC_CSR_V18PWRRSTF_Msk (0x1U << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 11702 #define RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk /*!< V1.8 power domain reset flag */
AnnaBridge 171:3a7713b1edbc 11703 #define RCC_CSR_RMVF_Pos (24U)
AnnaBridge 171:3a7713b1edbc 11704 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 11705 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
AnnaBridge 171:3a7713b1edbc 11706 #define RCC_CSR_OBLRSTF_Pos (25U)
AnnaBridge 171:3a7713b1edbc 11707 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 11708 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
AnnaBridge 171:3a7713b1edbc 11709 #define RCC_CSR_PINRSTF_Pos (26U)
AnnaBridge 171:3a7713b1edbc 11710 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 11711 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
AnnaBridge 171:3a7713b1edbc 11712 #define RCC_CSR_PORRSTF_Pos (27U)
AnnaBridge 171:3a7713b1edbc 11713 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 11714 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
AnnaBridge 171:3a7713b1edbc 11715 #define RCC_CSR_SFTRSTF_Pos (28U)
AnnaBridge 171:3a7713b1edbc 11716 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 11717 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
AnnaBridge 171:3a7713b1edbc 11718 #define RCC_CSR_IWDGRSTF_Pos (29U)
AnnaBridge 171:3a7713b1edbc 11719 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 11720 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
AnnaBridge 171:3a7713b1edbc 11721 #define RCC_CSR_WWDGRSTF_Pos (30U)
AnnaBridge 171:3a7713b1edbc 11722 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 11723 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
AnnaBridge 171:3a7713b1edbc 11724 #define RCC_CSR_LPWRRSTF_Pos (31U)
AnnaBridge 171:3a7713b1edbc 11725 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 11726 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
AnnaBridge 171:3a7713b1edbc 11727
AnnaBridge 171:3a7713b1edbc 11728 /******************* Bit definition for RCC_AHBRSTR register ****************/
AnnaBridge 171:3a7713b1edbc 11729 #define RCC_AHBRSTR_GPIOARST_Pos (17U)
AnnaBridge 171:3a7713b1edbc 11730 #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11731 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */
AnnaBridge 171:3a7713b1edbc 11732 #define RCC_AHBRSTR_GPIOBRST_Pos (18U)
AnnaBridge 171:3a7713b1edbc 11733 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11734 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */
AnnaBridge 171:3a7713b1edbc 11735 #define RCC_AHBRSTR_GPIOCRST_Pos (19U)
AnnaBridge 171:3a7713b1edbc 11736 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 11737 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */
AnnaBridge 171:3a7713b1edbc 11738 #define RCC_AHBRSTR_GPIODRST_Pos (20U)
AnnaBridge 171:3a7713b1edbc 11739 #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 11740 #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */
AnnaBridge 171:3a7713b1edbc 11741 #define RCC_AHBRSTR_GPIOFRST_Pos (22U)
AnnaBridge 171:3a7713b1edbc 11742 #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 11743 #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */
AnnaBridge 171:3a7713b1edbc 11744 #define RCC_AHBRSTR_TSCRST_Pos (24U)
AnnaBridge 171:3a7713b1edbc 11745 #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 11746 #define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TSC reset */
AnnaBridge 171:3a7713b1edbc 11747 #define RCC_AHBRSTR_ADC12RST_Pos (28U)
AnnaBridge 171:3a7713b1edbc 11748 #define RCC_AHBRSTR_ADC12RST_Msk (0x1U << RCC_AHBRSTR_ADC12RST_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 11749 #define RCC_AHBRSTR_ADC12RST RCC_AHBRSTR_ADC12RST_Msk /*!< ADC1 & ADC2 reset */
AnnaBridge 171:3a7713b1edbc 11750
AnnaBridge 171:3a7713b1edbc 11751 /******************* Bit definition for RCC_CFGR2 register ******************/
AnnaBridge 171:3a7713b1edbc 11752 /*!< PREDIV configuration */
AnnaBridge 171:3a7713b1edbc 11753 #define RCC_CFGR2_PREDIV_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11754 #define RCC_CFGR2_PREDIV_Msk (0xFU << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 11755 #define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk /*!< PREDIV[3:0] bits */
AnnaBridge 171:3a7713b1edbc 11756 #define RCC_CFGR2_PREDIV_0 (0x1U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11757 #define RCC_CFGR2_PREDIV_1 (0x2U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11758 #define RCC_CFGR2_PREDIV_2 (0x4U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11759 #define RCC_CFGR2_PREDIV_3 (0x8U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11760
AnnaBridge 171:3a7713b1edbc 11761 #define RCC_CFGR2_PREDIV_DIV1 (0x00000000U) /*!< PREDIV input clock not divided */
AnnaBridge 171:3a7713b1edbc 11762 #define RCC_CFGR2_PREDIV_DIV2 (0x00000001U) /*!< PREDIV input clock divided by 2 */
AnnaBridge 171:3a7713b1edbc 11763 #define RCC_CFGR2_PREDIV_DIV3 (0x00000002U) /*!< PREDIV input clock divided by 3 */
AnnaBridge 171:3a7713b1edbc 11764 #define RCC_CFGR2_PREDIV_DIV4 (0x00000003U) /*!< PREDIV input clock divided by 4 */
AnnaBridge 171:3a7713b1edbc 11765 #define RCC_CFGR2_PREDIV_DIV5 (0x00000004U) /*!< PREDIV input clock divided by 5 */
AnnaBridge 171:3a7713b1edbc 11766 #define RCC_CFGR2_PREDIV_DIV6 (0x00000005U) /*!< PREDIV input clock divided by 6 */
AnnaBridge 171:3a7713b1edbc 11767 #define RCC_CFGR2_PREDIV_DIV7 (0x00000006U) /*!< PREDIV input clock divided by 7 */
AnnaBridge 171:3a7713b1edbc 11768 #define RCC_CFGR2_PREDIV_DIV8 (0x00000007U) /*!< PREDIV input clock divided by 8 */
AnnaBridge 171:3a7713b1edbc 11769 #define RCC_CFGR2_PREDIV_DIV9 (0x00000008U) /*!< PREDIV input clock divided by 9 */
AnnaBridge 171:3a7713b1edbc 11770 #define RCC_CFGR2_PREDIV_DIV10 (0x00000009U) /*!< PREDIV input clock divided by 10 */
AnnaBridge 171:3a7713b1edbc 11771 #define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU) /*!< PREDIV input clock divided by 11 */
AnnaBridge 171:3a7713b1edbc 11772 #define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU) /*!< PREDIV input clock divided by 12 */
AnnaBridge 171:3a7713b1edbc 11773 #define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU) /*!< PREDIV input clock divided by 13 */
AnnaBridge 171:3a7713b1edbc 11774 #define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU) /*!< PREDIV input clock divided by 14 */
AnnaBridge 171:3a7713b1edbc 11775 #define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU) /*!< PREDIV input clock divided by 15 */
AnnaBridge 171:3a7713b1edbc 11776 #define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU) /*!< PREDIV input clock divided by 16 */
AnnaBridge 171:3a7713b1edbc 11777
AnnaBridge 171:3a7713b1edbc 11778 /*!< ADCPRE12 configuration */
AnnaBridge 171:3a7713b1edbc 11779 #define RCC_CFGR2_ADCPRE12_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11780 #define RCC_CFGR2_ADCPRE12_Msk (0x1FU << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x000001F0 */
AnnaBridge 171:3a7713b1edbc 11781 #define RCC_CFGR2_ADCPRE12 RCC_CFGR2_ADCPRE12_Msk /*!< ADCPRE12[8:4] bits */
AnnaBridge 171:3a7713b1edbc 11782 #define RCC_CFGR2_ADCPRE12_0 (0x01U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11783 #define RCC_CFGR2_ADCPRE12_1 (0x02U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11784 #define RCC_CFGR2_ADCPRE12_2 (0x04U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11785 #define RCC_CFGR2_ADCPRE12_3 (0x08U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 11786 #define RCC_CFGR2_ADCPRE12_4 (0x10U << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11787
AnnaBridge 171:3a7713b1edbc 11788 #define RCC_CFGR2_ADCPRE12_NO (0x00000000U) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
AnnaBridge 171:3a7713b1edbc 11789 #define RCC_CFGR2_ADCPRE12_DIV1 (0x00000100U) /*!< ADC12 PLL clock divided by 1 */
AnnaBridge 171:3a7713b1edbc 11790 #define RCC_CFGR2_ADCPRE12_DIV2 (0x00000110U) /*!< ADC12 PLL clock divided by 2 */
AnnaBridge 171:3a7713b1edbc 11791 #define RCC_CFGR2_ADCPRE12_DIV4 (0x00000120U) /*!< ADC12 PLL clock divided by 4 */
AnnaBridge 171:3a7713b1edbc 11792 #define RCC_CFGR2_ADCPRE12_DIV6 (0x00000130U) /*!< ADC12 PLL clock divided by 6 */
AnnaBridge 171:3a7713b1edbc 11793 #define RCC_CFGR2_ADCPRE12_DIV8 (0x00000140U) /*!< ADC12 PLL clock divided by 8 */
AnnaBridge 171:3a7713b1edbc 11794 #define RCC_CFGR2_ADCPRE12_DIV10 (0x00000150U) /*!< ADC12 PLL clock divided by 10 */
AnnaBridge 171:3a7713b1edbc 11795 #define RCC_CFGR2_ADCPRE12_DIV12 (0x00000160U) /*!< ADC12 PLL clock divided by 12 */
AnnaBridge 171:3a7713b1edbc 11796 #define RCC_CFGR2_ADCPRE12_DIV16 (0x00000170U) /*!< ADC12 PLL clock divided by 16 */
AnnaBridge 171:3a7713b1edbc 11797 #define RCC_CFGR2_ADCPRE12_DIV32 (0x00000180U) /*!< ADC12 PLL clock divided by 32 */
AnnaBridge 171:3a7713b1edbc 11798 #define RCC_CFGR2_ADCPRE12_DIV64 (0x00000190U) /*!< ADC12 PLL clock divided by 64 */
AnnaBridge 171:3a7713b1edbc 11799 #define RCC_CFGR2_ADCPRE12_DIV128 (0x000001A0U) /*!< ADC12 PLL clock divided by 128 */
AnnaBridge 171:3a7713b1edbc 11800 #define RCC_CFGR2_ADCPRE12_DIV256 (0x000001B0U) /*!< ADC12 PLL clock divided by 256 */
AnnaBridge 171:3a7713b1edbc 11801
AnnaBridge 171:3a7713b1edbc 11802 /******************* Bit definition for RCC_CFGR3 register ******************/
AnnaBridge 171:3a7713b1edbc 11803 #define RCC_CFGR3_USART1SW_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11804 #define RCC_CFGR3_USART1SW_Msk (0x3U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 11805 #define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk /*!< USART1SW[1:0] bits */
AnnaBridge 171:3a7713b1edbc 11806 #define RCC_CFGR3_USART1SW_0 (0x1U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11807 #define RCC_CFGR3_USART1SW_1 (0x2U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11808
AnnaBridge 171:3a7713b1edbc 11809 #define RCC_CFGR3_USART1SW_PCLK1 (0x00000000U) /*!< PCLK1 clock used as USART1 clock source */
AnnaBridge 171:3a7713b1edbc 11810 #define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U) /*!< System clock selected as USART1 clock source */
AnnaBridge 171:3a7713b1edbc 11811 #define RCC_CFGR3_USART1SW_LSE (0x00000002U) /*!< LSE oscillator clock used as USART1 clock source */
AnnaBridge 171:3a7713b1edbc 11812 #define RCC_CFGR3_USART1SW_HSI (0x00000003U) /*!< HSI oscillator clock used as USART1 clock source */
AnnaBridge 171:3a7713b1edbc 11813 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 11814 #define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK1
AnnaBridge 171:3a7713b1edbc 11815
AnnaBridge 171:3a7713b1edbc 11816 #define RCC_CFGR3_I2CSW_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11817 #define RCC_CFGR3_I2CSW_Msk (0x1U << RCC_CFGR3_I2CSW_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11818 #define RCC_CFGR3_I2CSW RCC_CFGR3_I2CSW_Msk /*!< I2CSW bits */
AnnaBridge 171:3a7713b1edbc 11819 #define RCC_CFGR3_I2C1SW_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11820 #define RCC_CFGR3_I2C1SW_Msk (0x1U << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11821 #define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk /*!< I2C1SW bits */
AnnaBridge 171:3a7713b1edbc 11822
AnnaBridge 171:3a7713b1edbc 11823 #define RCC_CFGR3_I2C1SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C1 clock source */
AnnaBridge 171:3a7713b1edbc 11824 #define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11825 #define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1U << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11826 #define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk /*!< System clock selected as I2C1 clock source */
AnnaBridge 171:3a7713b1edbc 11827 #define RCC_CFGR3_TIMSW_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11828 #define RCC_CFGR3_TIMSW_Msk (0x1U << RCC_CFGR3_TIMSW_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11829 #define RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk /*!< TIMSW bits */
AnnaBridge 171:3a7713b1edbc 11830 #define RCC_CFGR3_TIM1SW_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11831 #define RCC_CFGR3_TIM1SW_Msk (0x1U << RCC_CFGR3_TIM1SW_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11832 #define RCC_CFGR3_TIM1SW RCC_CFGR3_TIM1SW_Msk /*!< TIM1SW bits */
AnnaBridge 171:3a7713b1edbc 11833 #define RCC_CFGR3_TIM1SW_PCLK2 (0x00000000U) /*!< PCLK2 used as TIM1 clock source */
AnnaBridge 171:3a7713b1edbc 11834 #define RCC_CFGR3_TIM1SW_PLL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11835 #define RCC_CFGR3_TIM1SW_PLL_Msk (0x1U << RCC_CFGR3_TIM1SW_PLL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11836 #define RCC_CFGR3_TIM1SW_PLL RCC_CFGR3_TIM1SW_PLL_Msk /*!< PLL clock used as TIM1 clock source */
AnnaBridge 171:3a7713b1edbc 11837
AnnaBridge 171:3a7713b1edbc 11838 #define RCC_CFGR3_HRTIMSW_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11839 #define RCC_CFGR3_HRTIMSW_Msk (0x1U << RCC_CFGR3_HRTIMSW_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11840 #define RCC_CFGR3_HRTIMSW RCC_CFGR3_HRTIMSW_Msk /*!< HRTIM1SW bits */
AnnaBridge 171:3a7713b1edbc 11841 #define RCC_CFGR3_HRTIM1SW_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11842 #define RCC_CFGR3_HRTIM1SW_Msk (0x1U << RCC_CFGR3_HRTIM1SW_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11843 #define RCC_CFGR3_HRTIM1SW RCC_CFGR3_HRTIM1SW_Msk /*!< HRTIM1SW bits */
AnnaBridge 171:3a7713b1edbc 11844
AnnaBridge 171:3a7713b1edbc 11845 #define RCC_CFGR3_HRTIM1SW_PCLK2 (0x00000000U) /*!< PCLK2 used as HRTIM1 clock source */
AnnaBridge 171:3a7713b1edbc 11846 #define RCC_CFGR3_HRTIM1SW_PLL_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11847 #define RCC_CFGR3_HRTIM1SW_PLL_Msk (0x1U << RCC_CFGR3_HRTIM1SW_PLL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11848 #define RCC_CFGR3_HRTIM1SW_PLL RCC_CFGR3_HRTIM1SW_PLL_Msk /*!< PLL clock used as HRTIM1 clock source */
AnnaBridge 171:3a7713b1edbc 11849
AnnaBridge 171:3a7713b1edbc 11850 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 11851 #define RCC_CFGR3_TIM1SW_HCLK RCC_CFGR3_TIM1SW_PCLK2
AnnaBridge 171:3a7713b1edbc 11852 #define RCC_CFGR3_HRTIM1SW_HCLK RCC_CFGR3_HRTIM1SW_PCLK2
AnnaBridge 171:3a7713b1edbc 11853
AnnaBridge 171:3a7713b1edbc 11854 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 11855 /* */
AnnaBridge 171:3a7713b1edbc 11856 /* Real-Time Clock (RTC) */
AnnaBridge 171:3a7713b1edbc 11857 /* */
AnnaBridge 171:3a7713b1edbc 11858 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 11859 /*
AnnaBridge 171:3a7713b1edbc 11860 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
AnnaBridge 171:3a7713b1edbc 11861 */
AnnaBridge 171:3a7713b1edbc 11862 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
AnnaBridge 171:3a7713b1edbc 11863 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
AnnaBridge 171:3a7713b1edbc 11864 #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */
AnnaBridge 171:3a7713b1edbc 11865 #define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */
AnnaBridge 171:3a7713b1edbc 11866
AnnaBridge 171:3a7713b1edbc 11867 /******************** Bits definition for RTC_TR register *******************/
AnnaBridge 171:3a7713b1edbc 11868 #define RTC_TR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 11869 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 11870 #define RTC_TR_PM RTC_TR_PM_Msk
AnnaBridge 171:3a7713b1edbc 11871 #define RTC_TR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 11872 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 11873 #define RTC_TR_HT RTC_TR_HT_Msk
AnnaBridge 171:3a7713b1edbc 11874 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 11875 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 11876 #define RTC_TR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11877 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 11878 #define RTC_TR_HU RTC_TR_HU_Msk
AnnaBridge 171:3a7713b1edbc 11879 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11880 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11881 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11882 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 11883 #define RTC_TR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11884 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 11885 #define RTC_TR_MNT RTC_TR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 11886 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11887 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11888 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11889 #define RTC_TR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11890 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 11891 #define RTC_TR_MNU RTC_TR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 11892 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11893 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11894 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11895 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11896 #define RTC_TR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11897 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 11898 #define RTC_TR_ST RTC_TR_ST_Msk
AnnaBridge 171:3a7713b1edbc 11899 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11900 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11901 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 11902 #define RTC_TR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11903 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 11904 #define RTC_TR_SU RTC_TR_SU_Msk
AnnaBridge 171:3a7713b1edbc 11905 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11906 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11907 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11908 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11909
AnnaBridge 171:3a7713b1edbc 11910 /******************** Bits definition for RTC_DR register *******************/
AnnaBridge 171:3a7713b1edbc 11911 #define RTC_DR_YT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 11912 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 11913 #define RTC_DR_YT RTC_DR_YT_Msk
AnnaBridge 171:3a7713b1edbc 11914 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 11915 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 11916 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 11917 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 11918 #define RTC_DR_YU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11919 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 11920 #define RTC_DR_YU RTC_DR_YU_Msk
AnnaBridge 171:3a7713b1edbc 11921 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11922 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11923 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11924 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 11925 #define RTC_DR_WDU_Pos (13U)
AnnaBridge 171:3a7713b1edbc 11926 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 11927 #define RTC_DR_WDU RTC_DR_WDU_Msk
AnnaBridge 171:3a7713b1edbc 11928 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11929 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11930 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11931 #define RTC_DR_MT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11932 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11933 #define RTC_DR_MT RTC_DR_MT_Msk
AnnaBridge 171:3a7713b1edbc 11934 #define RTC_DR_MU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 11935 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 11936 #define RTC_DR_MU RTC_DR_MU_Msk
AnnaBridge 171:3a7713b1edbc 11937 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 11938 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11939 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11940 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11941 #define RTC_DR_DT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 11942 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 11943 #define RTC_DR_DT RTC_DR_DT_Msk
AnnaBridge 171:3a7713b1edbc 11944 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 11945 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 11946 #define RTC_DR_DU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 11947 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 11948 #define RTC_DR_DU RTC_DR_DU_Msk
AnnaBridge 171:3a7713b1edbc 11949 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 11950 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 11951 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 11952 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 11953
AnnaBridge 171:3a7713b1edbc 11954 /******************** Bits definition for RTC_CR register *******************/
AnnaBridge 171:3a7713b1edbc 11955 #define RTC_CR_COE_Pos (23U)
AnnaBridge 171:3a7713b1edbc 11956 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 11957 #define RTC_CR_COE RTC_CR_COE_Msk
AnnaBridge 171:3a7713b1edbc 11958 #define RTC_CR_OSEL_Pos (21U)
AnnaBridge 171:3a7713b1edbc 11959 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
AnnaBridge 171:3a7713b1edbc 11960 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
AnnaBridge 171:3a7713b1edbc 11961 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 11962 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 11963 #define RTC_CR_POL_Pos (20U)
AnnaBridge 171:3a7713b1edbc 11964 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 11965 #define RTC_CR_POL RTC_CR_POL_Msk
AnnaBridge 171:3a7713b1edbc 11966 #define RTC_CR_COSEL_Pos (19U)
AnnaBridge 171:3a7713b1edbc 11967 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 11968 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
AnnaBridge 171:3a7713b1edbc 11969 #define RTC_CR_BKP_Pos (18U)
AnnaBridge 171:3a7713b1edbc 11970 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 11971 #define RTC_CR_BKP RTC_CR_BKP_Msk
AnnaBridge 171:3a7713b1edbc 11972 #define RTC_CR_SUB1H_Pos (17U)
AnnaBridge 171:3a7713b1edbc 11973 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 11974 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
AnnaBridge 171:3a7713b1edbc 11975 #define RTC_CR_ADD1H_Pos (16U)
AnnaBridge 171:3a7713b1edbc 11976 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 11977 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
AnnaBridge 171:3a7713b1edbc 11978 #define RTC_CR_TSIE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 11979 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 11980 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
AnnaBridge 171:3a7713b1edbc 11981 #define RTC_CR_WUTIE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 11982 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 11983 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
AnnaBridge 171:3a7713b1edbc 11984 #define RTC_CR_ALRBIE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 11985 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 11986 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
AnnaBridge 171:3a7713b1edbc 11987 #define RTC_CR_ALRAIE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 11988 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 11989 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
AnnaBridge 171:3a7713b1edbc 11990 #define RTC_CR_TSE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 11991 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 11992 #define RTC_CR_TSE RTC_CR_TSE_Msk
AnnaBridge 171:3a7713b1edbc 11993 #define RTC_CR_WUTE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 11994 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 11995 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
AnnaBridge 171:3a7713b1edbc 11996 #define RTC_CR_ALRBE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 11997 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 11998 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
AnnaBridge 171:3a7713b1edbc 11999 #define RTC_CR_ALRAE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12000 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12001 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
AnnaBridge 171:3a7713b1edbc 12002 #define RTC_CR_FMT_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12003 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12004 #define RTC_CR_FMT RTC_CR_FMT_Msk
AnnaBridge 171:3a7713b1edbc 12005 #define RTC_CR_BYPSHAD_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12006 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12007 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
AnnaBridge 171:3a7713b1edbc 12008 #define RTC_CR_REFCKON_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12009 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12010 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
AnnaBridge 171:3a7713b1edbc 12011 #define RTC_CR_TSEDGE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12012 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12013 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
AnnaBridge 171:3a7713b1edbc 12014 #define RTC_CR_WUCKSEL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12015 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 12016 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
AnnaBridge 171:3a7713b1edbc 12017 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12018 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12019 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12020
AnnaBridge 171:3a7713b1edbc 12021 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 12022 #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
AnnaBridge 171:3a7713b1edbc 12023 #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
AnnaBridge 171:3a7713b1edbc 12024 #define RTC_CR_BCK RTC_CR_BKP
AnnaBridge 171:3a7713b1edbc 12025
AnnaBridge 171:3a7713b1edbc 12026 /******************** Bits definition for RTC_ISR register ******************/
AnnaBridge 171:3a7713b1edbc 12027 #define RTC_ISR_RECALPF_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12028 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 12029 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
AnnaBridge 171:3a7713b1edbc 12030 #define RTC_ISR_TAMP2F_Pos (14U)
AnnaBridge 171:3a7713b1edbc 12031 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12032 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
AnnaBridge 171:3a7713b1edbc 12033 #define RTC_ISR_TAMP1F_Pos (13U)
AnnaBridge 171:3a7713b1edbc 12034 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12035 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
AnnaBridge 171:3a7713b1edbc 12036 #define RTC_ISR_TSOVF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12037 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12038 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
AnnaBridge 171:3a7713b1edbc 12039 #define RTC_ISR_TSF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12040 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12041 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
AnnaBridge 171:3a7713b1edbc 12042 #define RTC_ISR_WUTF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12043 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12044 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
AnnaBridge 171:3a7713b1edbc 12045 #define RTC_ISR_ALRBF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 12046 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12047 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
AnnaBridge 171:3a7713b1edbc 12048 #define RTC_ISR_ALRAF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12049 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12050 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
AnnaBridge 171:3a7713b1edbc 12051 #define RTC_ISR_INIT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12052 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12053 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
AnnaBridge 171:3a7713b1edbc 12054 #define RTC_ISR_INITF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12055 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12056 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
AnnaBridge 171:3a7713b1edbc 12057 #define RTC_ISR_RSF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12058 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12059 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
AnnaBridge 171:3a7713b1edbc 12060 #define RTC_ISR_INITS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12061 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12062 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
AnnaBridge 171:3a7713b1edbc 12063 #define RTC_ISR_SHPF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12064 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12065 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
AnnaBridge 171:3a7713b1edbc 12066 #define RTC_ISR_WUTWF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12067 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12068 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
AnnaBridge 171:3a7713b1edbc 12069 #define RTC_ISR_ALRBWF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12070 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12071 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
AnnaBridge 171:3a7713b1edbc 12072 #define RTC_ISR_ALRAWF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12073 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12074 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
AnnaBridge 171:3a7713b1edbc 12075
AnnaBridge 171:3a7713b1edbc 12076 /******************** Bits definition for RTC_PRER register *****************/
AnnaBridge 171:3a7713b1edbc 12077 #define RTC_PRER_PREDIV_A_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12078 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
AnnaBridge 171:3a7713b1edbc 12079 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
AnnaBridge 171:3a7713b1edbc 12080 #define RTC_PRER_PREDIV_S_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12081 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 12082 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
AnnaBridge 171:3a7713b1edbc 12083
AnnaBridge 171:3a7713b1edbc 12084 /******************** Bits definition for RTC_WUTR register *****************/
AnnaBridge 171:3a7713b1edbc 12085 #define RTC_WUTR_WUT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12086 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12087 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
AnnaBridge 171:3a7713b1edbc 12088
AnnaBridge 171:3a7713b1edbc 12089 /******************** Bits definition for RTC_ALRMAR register ***************/
AnnaBridge 171:3a7713b1edbc 12090 #define RTC_ALRMAR_MSK4_Pos (31U)
AnnaBridge 171:3a7713b1edbc 12091 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 12092 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
AnnaBridge 171:3a7713b1edbc 12093 #define RTC_ALRMAR_WDSEL_Pos (30U)
AnnaBridge 171:3a7713b1edbc 12094 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 12095 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
AnnaBridge 171:3a7713b1edbc 12096 #define RTC_ALRMAR_DT_Pos (28U)
AnnaBridge 171:3a7713b1edbc 12097 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 12098 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
AnnaBridge 171:3a7713b1edbc 12099 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 12100 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 12101 #define RTC_ALRMAR_DU_Pos (24U)
AnnaBridge 171:3a7713b1edbc 12102 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 12103 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
AnnaBridge 171:3a7713b1edbc 12104 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 12105 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 12106 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 12107 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 12108 #define RTC_ALRMAR_MSK3_Pos (23U)
AnnaBridge 171:3a7713b1edbc 12109 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 12110 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
AnnaBridge 171:3a7713b1edbc 12111 #define RTC_ALRMAR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 12112 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 12113 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
AnnaBridge 171:3a7713b1edbc 12114 #define RTC_ALRMAR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 12115 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 12116 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
AnnaBridge 171:3a7713b1edbc 12117 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 12118 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 12119 #define RTC_ALRMAR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12120 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 12121 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
AnnaBridge 171:3a7713b1edbc 12122 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 12123 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 12124 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 12125 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 12126 #define RTC_ALRMAR_MSK2_Pos (15U)
AnnaBridge 171:3a7713b1edbc 12127 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12128 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
AnnaBridge 171:3a7713b1edbc 12129 #define RTC_ALRMAR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12130 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 12131 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 12132 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12133 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12134 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12135 #define RTC_ALRMAR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12136 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 12137 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 12138 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12139 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12140 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12141 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12142 #define RTC_ALRMAR_MSK1_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12143 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12144 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
AnnaBridge 171:3a7713b1edbc 12145 #define RTC_ALRMAR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12146 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 12147 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
AnnaBridge 171:3a7713b1edbc 12148 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12149 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12150 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12151 #define RTC_ALRMAR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12152 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 12153 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
AnnaBridge 171:3a7713b1edbc 12154 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12155 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12156 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12157 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12158
AnnaBridge 171:3a7713b1edbc 12159 /******************** Bits definition for RTC_ALRMBR register ***************/
AnnaBridge 171:3a7713b1edbc 12160 #define RTC_ALRMBR_MSK4_Pos (31U)
AnnaBridge 171:3a7713b1edbc 12161 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 12162 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
AnnaBridge 171:3a7713b1edbc 12163 #define RTC_ALRMBR_WDSEL_Pos (30U)
AnnaBridge 171:3a7713b1edbc 12164 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 12165 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
AnnaBridge 171:3a7713b1edbc 12166 #define RTC_ALRMBR_DT_Pos (28U)
AnnaBridge 171:3a7713b1edbc 12167 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 12168 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
AnnaBridge 171:3a7713b1edbc 12169 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 12170 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 12171 #define RTC_ALRMBR_DU_Pos (24U)
AnnaBridge 171:3a7713b1edbc 12172 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 12173 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
AnnaBridge 171:3a7713b1edbc 12174 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 12175 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 12176 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 12177 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 12178 #define RTC_ALRMBR_MSK3_Pos (23U)
AnnaBridge 171:3a7713b1edbc 12179 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 12180 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
AnnaBridge 171:3a7713b1edbc 12181 #define RTC_ALRMBR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 12182 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 12183 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
AnnaBridge 171:3a7713b1edbc 12184 #define RTC_ALRMBR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 12185 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 12186 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
AnnaBridge 171:3a7713b1edbc 12187 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 12188 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 12189 #define RTC_ALRMBR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12190 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 12191 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
AnnaBridge 171:3a7713b1edbc 12192 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 12193 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 12194 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 12195 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 12196 #define RTC_ALRMBR_MSK2_Pos (15U)
AnnaBridge 171:3a7713b1edbc 12197 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12198 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
AnnaBridge 171:3a7713b1edbc 12199 #define RTC_ALRMBR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12200 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 12201 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 12202 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12203 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12204 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12205 #define RTC_ALRMBR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12206 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 12207 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 12208 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12209 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12210 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12211 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12212 #define RTC_ALRMBR_MSK1_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12213 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12214 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
AnnaBridge 171:3a7713b1edbc 12215 #define RTC_ALRMBR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12216 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 12217 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
AnnaBridge 171:3a7713b1edbc 12218 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12219 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12220 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12221 #define RTC_ALRMBR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12222 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 12223 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
AnnaBridge 171:3a7713b1edbc 12224 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12225 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12226 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12227 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12228
AnnaBridge 171:3a7713b1edbc 12229 /******************** Bits definition for RTC_WPR register ******************/
AnnaBridge 171:3a7713b1edbc 12230 #define RTC_WPR_KEY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12231 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 12232 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
AnnaBridge 171:3a7713b1edbc 12233
AnnaBridge 171:3a7713b1edbc 12234 /******************** Bits definition for RTC_SSR register ******************/
AnnaBridge 171:3a7713b1edbc 12235 #define RTC_SSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12236 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12237 #define RTC_SSR_SS RTC_SSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 12238
AnnaBridge 171:3a7713b1edbc 12239 /******************** Bits definition for RTC_SHIFTR register ***************/
AnnaBridge 171:3a7713b1edbc 12240 #define RTC_SHIFTR_SUBFS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12241 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 12242 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
AnnaBridge 171:3a7713b1edbc 12243 #define RTC_SHIFTR_ADD1S_Pos (31U)
AnnaBridge 171:3a7713b1edbc 12244 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 12245 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
AnnaBridge 171:3a7713b1edbc 12246
AnnaBridge 171:3a7713b1edbc 12247 /******************** Bits definition for RTC_TSTR register *****************/
AnnaBridge 171:3a7713b1edbc 12248 #define RTC_TSTR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 12249 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 12250 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
AnnaBridge 171:3a7713b1edbc 12251 #define RTC_TSTR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 12252 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 12253 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
AnnaBridge 171:3a7713b1edbc 12254 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 12255 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 12256 #define RTC_TSTR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12257 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 12258 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
AnnaBridge 171:3a7713b1edbc 12259 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 12260 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 12261 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 12262 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 12263 #define RTC_TSTR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12264 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 12265 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 12266 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12267 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12268 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12269 #define RTC_TSTR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12270 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 12271 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 12272 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12273 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12274 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12275 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12276 #define RTC_TSTR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12277 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 12278 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
AnnaBridge 171:3a7713b1edbc 12279 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12280 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12281 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12282 #define RTC_TSTR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12283 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 12284 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
AnnaBridge 171:3a7713b1edbc 12285 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12286 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12287 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12288 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12289
AnnaBridge 171:3a7713b1edbc 12290 /******************** Bits definition for RTC_TSDR register *****************/
AnnaBridge 171:3a7713b1edbc 12291 #define RTC_TSDR_WDU_Pos (13U)
AnnaBridge 171:3a7713b1edbc 12292 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 12293 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
AnnaBridge 171:3a7713b1edbc 12294 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12295 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12296 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12297 #define RTC_TSDR_MT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12298 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12299 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
AnnaBridge 171:3a7713b1edbc 12300 #define RTC_TSDR_MU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12301 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 12302 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
AnnaBridge 171:3a7713b1edbc 12303 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12304 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12305 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12306 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12307 #define RTC_TSDR_DT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12308 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 12309 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
AnnaBridge 171:3a7713b1edbc 12310 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12311 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12312 #define RTC_TSDR_DU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12313 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 12314 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
AnnaBridge 171:3a7713b1edbc 12315 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12316 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12317 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12318 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12319
AnnaBridge 171:3a7713b1edbc 12320 /******************** Bits definition for RTC_TSSSR register ****************/
AnnaBridge 171:3a7713b1edbc 12321 #define RTC_TSSSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12322 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12323 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 12324
AnnaBridge 171:3a7713b1edbc 12325 /******************** Bits definition for RTC_CAL register *****************/
AnnaBridge 171:3a7713b1edbc 12326 #define RTC_CALR_CALP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 12327 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12328 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
AnnaBridge 171:3a7713b1edbc 12329 #define RTC_CALR_CALW8_Pos (14U)
AnnaBridge 171:3a7713b1edbc 12330 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12331 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
AnnaBridge 171:3a7713b1edbc 12332 #define RTC_CALR_CALW16_Pos (13U)
AnnaBridge 171:3a7713b1edbc 12333 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12334 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
AnnaBridge 171:3a7713b1edbc 12335 #define RTC_CALR_CALM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12336 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
AnnaBridge 171:3a7713b1edbc 12337 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
AnnaBridge 171:3a7713b1edbc 12338 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12339 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12340 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12341 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12342 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12343 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12344 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12345 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12346 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12347
AnnaBridge 171:3a7713b1edbc 12348 /******************** Bits definition for RTC_TAFCR register ****************/
AnnaBridge 171:3a7713b1edbc 12349 #define RTC_TAFCR_PC15MODE_Pos (23U)
AnnaBridge 171:3a7713b1edbc 12350 #define RTC_TAFCR_PC15MODE_Msk (0x1U << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 12351 #define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk
AnnaBridge 171:3a7713b1edbc 12352 #define RTC_TAFCR_PC15VALUE_Pos (22U)
AnnaBridge 171:3a7713b1edbc 12353 #define RTC_TAFCR_PC15VALUE_Msk (0x1U << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 12354 #define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk
AnnaBridge 171:3a7713b1edbc 12355 #define RTC_TAFCR_PC14MODE_Pos (21U)
AnnaBridge 171:3a7713b1edbc 12356 #define RTC_TAFCR_PC14MODE_Msk (0x1U << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 12357 #define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk
AnnaBridge 171:3a7713b1edbc 12358 #define RTC_TAFCR_PC14VALUE_Pos (20U)
AnnaBridge 171:3a7713b1edbc 12359 #define RTC_TAFCR_PC14VALUE_Msk (0x1U << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 12360 #define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk
AnnaBridge 171:3a7713b1edbc 12361 #define RTC_TAFCR_PC13MODE_Pos (19U)
AnnaBridge 171:3a7713b1edbc 12362 #define RTC_TAFCR_PC13MODE_Msk (0x1U << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 12363 #define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk
AnnaBridge 171:3a7713b1edbc 12364 #define RTC_TAFCR_PC13VALUE_Pos (18U)
AnnaBridge 171:3a7713b1edbc 12365 #define RTC_TAFCR_PC13VALUE_Msk (0x1U << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 12366 #define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk
AnnaBridge 171:3a7713b1edbc 12367 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
AnnaBridge 171:3a7713b1edbc 12368 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12369 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
AnnaBridge 171:3a7713b1edbc 12370 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
AnnaBridge 171:3a7713b1edbc 12371 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
AnnaBridge 171:3a7713b1edbc 12372 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
AnnaBridge 171:3a7713b1edbc 12373 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12374 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12375 #define RTC_TAFCR_TAMPFLT_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12376 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
AnnaBridge 171:3a7713b1edbc 12377 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
AnnaBridge 171:3a7713b1edbc 12378 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12379 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12380 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12381 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 12382 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
AnnaBridge 171:3a7713b1edbc 12383 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12384 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12385 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12386 #define RTC_TAFCR_TAMPTS_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12387 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12388 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
AnnaBridge 171:3a7713b1edbc 12389 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12390 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12391 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
AnnaBridge 171:3a7713b1edbc 12392 #define RTC_TAFCR_TAMP2E_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12393 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12394 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
AnnaBridge 171:3a7713b1edbc 12395 #define RTC_TAFCR_TAMPIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12396 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12397 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
AnnaBridge 171:3a7713b1edbc 12398 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12399 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12400 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
AnnaBridge 171:3a7713b1edbc 12401 #define RTC_TAFCR_TAMP1E_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12402 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12403 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
AnnaBridge 171:3a7713b1edbc 12404
AnnaBridge 171:3a7713b1edbc 12405 /* Reference defines */
AnnaBridge 171:3a7713b1edbc 12406 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE
AnnaBridge 171:3a7713b1edbc 12407
AnnaBridge 171:3a7713b1edbc 12408 /******************** Bits definition for RTC_ALRMASSR register *************/
AnnaBridge 171:3a7713b1edbc 12409 #define RTC_ALRMASSR_MASKSS_Pos (24U)
AnnaBridge 171:3a7713b1edbc 12410 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 12411 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
AnnaBridge 171:3a7713b1edbc 12412 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 12413 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 12414 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 12415 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 12416 #define RTC_ALRMASSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12417 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 12418 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 12419
AnnaBridge 171:3a7713b1edbc 12420 /******************** Bits definition for RTC_ALRMBSSR register *************/
AnnaBridge 171:3a7713b1edbc 12421 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
AnnaBridge 171:3a7713b1edbc 12422 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 12423 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
AnnaBridge 171:3a7713b1edbc 12424 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 12425 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 12426 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 12427 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 12428 #define RTC_ALRMBSSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12429 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 12430 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 12431
AnnaBridge 171:3a7713b1edbc 12432 /******************** Bits definition for RTC_BKP0R register ****************/
AnnaBridge 171:3a7713b1edbc 12433 #define RTC_BKP0R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12434 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 12435 #define RTC_BKP0R RTC_BKP0R_Msk
AnnaBridge 171:3a7713b1edbc 12436
AnnaBridge 171:3a7713b1edbc 12437 /******************** Bits definition for RTC_BKP1R register ****************/
AnnaBridge 171:3a7713b1edbc 12438 #define RTC_BKP1R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12439 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 12440 #define RTC_BKP1R RTC_BKP1R_Msk
AnnaBridge 171:3a7713b1edbc 12441
AnnaBridge 171:3a7713b1edbc 12442 /******************** Bits definition for RTC_BKP2R register ****************/
AnnaBridge 171:3a7713b1edbc 12443 #define RTC_BKP2R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12444 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 12445 #define RTC_BKP2R RTC_BKP2R_Msk
AnnaBridge 171:3a7713b1edbc 12446
AnnaBridge 171:3a7713b1edbc 12447 /******************** Bits definition for RTC_BKP3R register ****************/
AnnaBridge 171:3a7713b1edbc 12448 #define RTC_BKP3R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12449 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 12450 #define RTC_BKP3R RTC_BKP3R_Msk
AnnaBridge 171:3a7713b1edbc 12451
AnnaBridge 171:3a7713b1edbc 12452 /******************** Bits definition for RTC_BKP4R register ****************/
AnnaBridge 171:3a7713b1edbc 12453 #define RTC_BKP4R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12454 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 12455 #define RTC_BKP4R RTC_BKP4R_Msk
AnnaBridge 171:3a7713b1edbc 12456
AnnaBridge 171:3a7713b1edbc 12457 /******************** Number of backup registers ******************************/
AnnaBridge 171:3a7713b1edbc 12458 #define RTC_BKP_NUMBER 5
AnnaBridge 171:3a7713b1edbc 12459
AnnaBridge 171:3a7713b1edbc 12460 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12461 /* */
AnnaBridge 171:3a7713b1edbc 12462 /* Serial Peripheral Interface (SPI) */
AnnaBridge 171:3a7713b1edbc 12463 /* */
AnnaBridge 171:3a7713b1edbc 12464 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12465
AnnaBridge 171:3a7713b1edbc 12466 /*
AnnaBridge 171:3a7713b1edbc 12467 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
AnnaBridge 171:3a7713b1edbc 12468 */
AnnaBridge 171:3a7713b1edbc 12469 /* Note: No specific macro feature on this device */
AnnaBridge 171:3a7713b1edbc 12470
AnnaBridge 171:3a7713b1edbc 12471 /******************* Bit definition for SPI_CR1 register ********************/
AnnaBridge 171:3a7713b1edbc 12472 #define SPI_CR1_CPHA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12473 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12474 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
AnnaBridge 171:3a7713b1edbc 12475 #define SPI_CR1_CPOL_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12476 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12477 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
AnnaBridge 171:3a7713b1edbc 12478 #define SPI_CR1_MSTR_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12479 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12480 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
AnnaBridge 171:3a7713b1edbc 12481 #define SPI_CR1_BR_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12482 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 12483 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
AnnaBridge 171:3a7713b1edbc 12484 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12485 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12486 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12487 #define SPI_CR1_SPE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12488 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12489 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
AnnaBridge 171:3a7713b1edbc 12490 #define SPI_CR1_LSBFIRST_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12491 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12492 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
AnnaBridge 171:3a7713b1edbc 12493 #define SPI_CR1_SSI_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12494 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12495 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
AnnaBridge 171:3a7713b1edbc 12496 #define SPI_CR1_SSM_Pos (9U)
AnnaBridge 171:3a7713b1edbc 12497 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12498 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
AnnaBridge 171:3a7713b1edbc 12499 #define SPI_CR1_RXONLY_Pos (10U)
AnnaBridge 171:3a7713b1edbc 12500 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12501 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
AnnaBridge 171:3a7713b1edbc 12502 #define SPI_CR1_CRCL_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12503 #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12504 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
AnnaBridge 171:3a7713b1edbc 12505 #define SPI_CR1_CRCNEXT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12506 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12507 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
AnnaBridge 171:3a7713b1edbc 12508 #define SPI_CR1_CRCEN_Pos (13U)
AnnaBridge 171:3a7713b1edbc 12509 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12510 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
AnnaBridge 171:3a7713b1edbc 12511 #define SPI_CR1_BIDIOE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 12512 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12513 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
AnnaBridge 171:3a7713b1edbc 12514 #define SPI_CR1_BIDIMODE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 12515 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12516 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
AnnaBridge 171:3a7713b1edbc 12517
AnnaBridge 171:3a7713b1edbc 12518 /******************* Bit definition for SPI_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 12519 #define SPI_CR2_RXDMAEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12520 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12521 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
AnnaBridge 171:3a7713b1edbc 12522 #define SPI_CR2_TXDMAEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12523 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12524 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
AnnaBridge 171:3a7713b1edbc 12525 #define SPI_CR2_SSOE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12526 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12527 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
AnnaBridge 171:3a7713b1edbc 12528 #define SPI_CR2_NSSP_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12529 #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12530 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
AnnaBridge 171:3a7713b1edbc 12531 #define SPI_CR2_FRF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12532 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12533 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
AnnaBridge 171:3a7713b1edbc 12534 #define SPI_CR2_ERRIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12535 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12536 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12537 #define SPI_CR2_RXNEIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12538 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12539 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12540 #define SPI_CR2_TXEIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12541 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12542 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12543 #define SPI_CR2_DS_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12544 #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 12545 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
AnnaBridge 171:3a7713b1edbc 12546 #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12547 #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12548 #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12549 #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12550 #define SPI_CR2_FRXTH_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12551 #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12552 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
AnnaBridge 171:3a7713b1edbc 12553 #define SPI_CR2_LDMARX_Pos (13U)
AnnaBridge 171:3a7713b1edbc 12554 #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12555 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
AnnaBridge 171:3a7713b1edbc 12556 #define SPI_CR2_LDMATX_Pos (14U)
AnnaBridge 171:3a7713b1edbc 12557 #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12558 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
AnnaBridge 171:3a7713b1edbc 12559
AnnaBridge 171:3a7713b1edbc 12560 /******************** Bit definition for SPI_SR register ********************/
AnnaBridge 171:3a7713b1edbc 12561 #define SPI_SR_RXNE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12562 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12563 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
AnnaBridge 171:3a7713b1edbc 12564 #define SPI_SR_TXE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12565 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12566 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
AnnaBridge 171:3a7713b1edbc 12567 #define SPI_SR_CRCERR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12568 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12569 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
AnnaBridge 171:3a7713b1edbc 12570 #define SPI_SR_MODF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12571 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12572 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
AnnaBridge 171:3a7713b1edbc 12573 #define SPI_SR_OVR_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12574 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12575 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
AnnaBridge 171:3a7713b1edbc 12576 #define SPI_SR_BSY_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12577 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12578 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
AnnaBridge 171:3a7713b1edbc 12579 #define SPI_SR_FRE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12580 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12581 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
AnnaBridge 171:3a7713b1edbc 12582 #define SPI_SR_FRLVL_Pos (9U)
AnnaBridge 171:3a7713b1edbc 12583 #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 12584 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
AnnaBridge 171:3a7713b1edbc 12585 #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12586 #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 12587 #define SPI_SR_FTLVL_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12588 #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
AnnaBridge 171:3a7713b1edbc 12589 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
AnnaBridge 171:3a7713b1edbc 12590 #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12591 #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12592
AnnaBridge 171:3a7713b1edbc 12593 /******************** Bit definition for SPI_DR register ********************/
AnnaBridge 171:3a7713b1edbc 12594 #define SPI_DR_DR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12595 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12596 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
AnnaBridge 171:3a7713b1edbc 12597
AnnaBridge 171:3a7713b1edbc 12598 /******************* Bit definition for SPI_CRCPR register ******************/
AnnaBridge 171:3a7713b1edbc 12599 #define SPI_CRCPR_CRCPOLY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12600 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12601 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
AnnaBridge 171:3a7713b1edbc 12602
AnnaBridge 171:3a7713b1edbc 12603 /****************** Bit definition for SPI_RXCRCR register ******************/
AnnaBridge 171:3a7713b1edbc 12604 #define SPI_RXCRCR_RXCRC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12605 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12606 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
AnnaBridge 171:3a7713b1edbc 12607
AnnaBridge 171:3a7713b1edbc 12608 /****************** Bit definition for SPI_TXCRCR register ******************/
AnnaBridge 171:3a7713b1edbc 12609 #define SPI_TXCRCR_TXCRC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12610 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 12611 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
AnnaBridge 171:3a7713b1edbc 12612
AnnaBridge 171:3a7713b1edbc 12613 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12614 /* */
AnnaBridge 171:3a7713b1edbc 12615 /* System Configuration(SYSCFG) */
AnnaBridge 171:3a7713b1edbc 12616 /* */
AnnaBridge 171:3a7713b1edbc 12617 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12618 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
AnnaBridge 171:3a7713b1edbc 12619 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12620 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 12621 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
AnnaBridge 171:3a7713b1edbc 12622 #define SYSCFG_CFGR1_MEM_MODE_0 (0x00000001U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 12623 #define SYSCFG_CFGR1_MEM_MODE_1 (0x00000002U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 12624 #define SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12625 #define SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12626 #define SYSCFG_CFGR1_TIM1_ITR3_RMP SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk /*!< Timer 1 ITR3 selection */
AnnaBridge 171:3a7713b1edbc 12627 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12628 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk (0x1U << SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12629 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk /*!< DAC1 Trigger1 remap */
AnnaBridge 171:3a7713b1edbc 12630 #define SYSCFG_CFGR1_DMA_RMP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12631 #define SYSCFG_CFGR1_DMA_RMP_Msk (0x1FU << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x0000F800 */
AnnaBridge 171:3a7713b1edbc 12632 #define SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk /*!< DMA remap mask */
AnnaBridge 171:3a7713b1edbc 12633 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 12634 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 12635 #define SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk /*!< Timer 16 DMA remap */
AnnaBridge 171:3a7713b1edbc 12636 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12637 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 12638 #define SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk /*!< Timer 17 DMA remap */
AnnaBridge 171:3a7713b1edbc 12639 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos (13U)
AnnaBridge 171:3a7713b1edbc 12640 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 12641 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk /*!< Timer 6 / DAC1 Ch1 DMA remap */
AnnaBridge 171:3a7713b1edbc 12642 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos (14U)
AnnaBridge 171:3a7713b1edbc 12643 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 12644 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk /*!< Timer 7 / DAC1 Ch2 DMA remap */
AnnaBridge 171:3a7713b1edbc 12645 #define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 12646 #define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_DAC2Ch1_DMA_RMP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 12647 #define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP SYSCFG_CFGR1_DAC2Ch1_DMA_RMP_Msk /*!< DAC2 CH1 DMA remap */
AnnaBridge 171:3a7713b1edbc 12648 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12649 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 12650 #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
AnnaBridge 171:3a7713b1edbc 12651 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
AnnaBridge 171:3a7713b1edbc 12652 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 12653 #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
AnnaBridge 171:3a7713b1edbc 12654 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
AnnaBridge 171:3a7713b1edbc 12655 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 12656 #define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
AnnaBridge 171:3a7713b1edbc 12657 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
AnnaBridge 171:3a7713b1edbc 12658 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 12659 #define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
AnnaBridge 171:3a7713b1edbc 12660 #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
AnnaBridge 171:3a7713b1edbc 12661 #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 12662 #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
AnnaBridge 171:3a7713b1edbc 12663 #define SYSCFG_CFGR1_ENCODER_MODE_Pos (22U)
AnnaBridge 171:3a7713b1edbc 12664 #define SYSCFG_CFGR1_ENCODER_MODE_Msk (0x3U << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 12665 #define SYSCFG_CFGR1_ENCODER_MODE SYSCFG_CFGR1_ENCODER_MODE_Msk /*!< Encoder Mode */
AnnaBridge 171:3a7713b1edbc 12666 #define SYSCFG_CFGR1_ENCODER_MODE_0 (0x1U << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 12667 #define SYSCFG_CFGR1_ENCODER_MODE_1 (0x2U << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 12668 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos (22U)
AnnaBridge 171:3a7713b1edbc 12669 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk (0x1U << SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 12670 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2 SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
AnnaBridge 171:3a7713b1edbc 12671 #define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos (23U)
AnnaBridge 171:3a7713b1edbc 12672 #define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk (0x1U << SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 12673 #define SYSCFG_CFGR1_ENCODER_MODE_TIM3 SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
AnnaBridge 171:3a7713b1edbc 12674 #define SYSCFG_CFGR1_FPU_IE_Pos (26U)
AnnaBridge 171:3a7713b1edbc 12675 #define SYSCFG_CFGR1_FPU_IE_Msk (0x3FU << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0xFC000000 */
AnnaBridge 171:3a7713b1edbc 12676 #define SYSCFG_CFGR1_FPU_IE SYSCFG_CFGR1_FPU_IE_Msk /*!< Floating Point Unit Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 12677 #define SYSCFG_CFGR1_FPU_IE_0 (0x01U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 12678 #define SYSCFG_CFGR1_FPU_IE_1 (0x02U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 12679 #define SYSCFG_CFGR1_FPU_IE_2 (0x04U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 12680 #define SYSCFG_CFGR1_FPU_IE_3 (0x08U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 12681 #define SYSCFG_CFGR1_FPU_IE_4 (0x10U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 12682 #define SYSCFG_CFGR1_FPU_IE_5 (0x20U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 12683
AnnaBridge 171:3a7713b1edbc 12684 /***************** Bit definition for SYSCFG_RCR register *******************/
AnnaBridge 171:3a7713b1edbc 12685 #define SYSCFG_RCR_PAGE0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12686 #define SYSCFG_RCR_PAGE0_Msk (0x1U << SYSCFG_RCR_PAGE0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12687 #define SYSCFG_RCR_PAGE0 SYSCFG_RCR_PAGE0_Msk /*!< ICODE SRAM Write protection page 0 */
AnnaBridge 171:3a7713b1edbc 12688 #define SYSCFG_RCR_PAGE1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12689 #define SYSCFG_RCR_PAGE1_Msk (0x1U << SYSCFG_RCR_PAGE1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12690 #define SYSCFG_RCR_PAGE1 SYSCFG_RCR_PAGE1_Msk /*!< ICODE SRAM Write protection page 1 */
AnnaBridge 171:3a7713b1edbc 12691 #define SYSCFG_RCR_PAGE2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12692 #define SYSCFG_RCR_PAGE2_Msk (0x1U << SYSCFG_RCR_PAGE2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12693 #define SYSCFG_RCR_PAGE2 SYSCFG_RCR_PAGE2_Msk /*!< ICODE SRAM Write protection page 2 */
AnnaBridge 171:3a7713b1edbc 12694 #define SYSCFG_RCR_PAGE3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12695 #define SYSCFG_RCR_PAGE3_Msk (0x1U << SYSCFG_RCR_PAGE3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12696 #define SYSCFG_RCR_PAGE3 SYSCFG_RCR_PAGE3_Msk /*!< ICODE SRAM Write protection page 3 */
AnnaBridge 171:3a7713b1edbc 12697
AnnaBridge 171:3a7713b1edbc 12698 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
AnnaBridge 171:3a7713b1edbc 12699 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12700 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 12701 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
AnnaBridge 171:3a7713b1edbc 12702 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12703 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 12704 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
AnnaBridge 171:3a7713b1edbc 12705 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12706 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 12707 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
AnnaBridge 171:3a7713b1edbc 12708 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12709 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 12710 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
AnnaBridge 171:3a7713b1edbc 12711
AnnaBridge 171:3a7713b1edbc 12712 /*!<*
AnnaBridge 171:3a7713b1edbc 12713 * @brief EXTI0 configuration
AnnaBridge 171:3a7713b1edbc 12714 */
AnnaBridge 171:3a7713b1edbc 12715 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
AnnaBridge 171:3a7713b1edbc 12716 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
AnnaBridge 171:3a7713b1edbc 12717 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
AnnaBridge 171:3a7713b1edbc 12718 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
AnnaBridge 171:3a7713b1edbc 12719 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */
AnnaBridge 171:3a7713b1edbc 12720 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!< PF[0] pin */
AnnaBridge 171:3a7713b1edbc 12721
AnnaBridge 171:3a7713b1edbc 12722 /*!<*
AnnaBridge 171:3a7713b1edbc 12723 * @brief EXTI1 configuration
AnnaBridge 171:3a7713b1edbc 12724 */
AnnaBridge 171:3a7713b1edbc 12725 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
AnnaBridge 171:3a7713b1edbc 12726 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
AnnaBridge 171:3a7713b1edbc 12727 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
AnnaBridge 171:3a7713b1edbc 12728 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
AnnaBridge 171:3a7713b1edbc 12729 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */
AnnaBridge 171:3a7713b1edbc 12730 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!< PF[1] pin */
AnnaBridge 171:3a7713b1edbc 12731
AnnaBridge 171:3a7713b1edbc 12732 /*!<*
AnnaBridge 171:3a7713b1edbc 12733 * @brief EXTI2 configuration
AnnaBridge 171:3a7713b1edbc 12734 */
AnnaBridge 171:3a7713b1edbc 12735 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
AnnaBridge 171:3a7713b1edbc 12736 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
AnnaBridge 171:3a7713b1edbc 12737 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
AnnaBridge 171:3a7713b1edbc 12738 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
AnnaBridge 171:3a7713b1edbc 12739 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */
AnnaBridge 171:3a7713b1edbc 12740 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!< PF[2] pin */
AnnaBridge 171:3a7713b1edbc 12741
AnnaBridge 171:3a7713b1edbc 12742 /*!<*
AnnaBridge 171:3a7713b1edbc 12743 * @brief EXTI3 configuration
AnnaBridge 171:3a7713b1edbc 12744 */
AnnaBridge 171:3a7713b1edbc 12745 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
AnnaBridge 171:3a7713b1edbc 12746 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
AnnaBridge 171:3a7713b1edbc 12747 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
AnnaBridge 171:3a7713b1edbc 12748 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
AnnaBridge 171:3a7713b1edbc 12749 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
AnnaBridge 171:3a7713b1edbc 12750
AnnaBridge 171:3a7713b1edbc 12751 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
AnnaBridge 171:3a7713b1edbc 12752 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12753 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 12754 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
AnnaBridge 171:3a7713b1edbc 12755 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12756 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 12757 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
AnnaBridge 171:3a7713b1edbc 12758 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12759 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 12760 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
AnnaBridge 171:3a7713b1edbc 12761 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12762 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 12763 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
AnnaBridge 171:3a7713b1edbc 12764
AnnaBridge 171:3a7713b1edbc 12765 /*!<*
AnnaBridge 171:3a7713b1edbc 12766 * @brief EXTI4 configuration
AnnaBridge 171:3a7713b1edbc 12767 */
AnnaBridge 171:3a7713b1edbc 12768 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
AnnaBridge 171:3a7713b1edbc 12769 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
AnnaBridge 171:3a7713b1edbc 12770 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
AnnaBridge 171:3a7713b1edbc 12771 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
AnnaBridge 171:3a7713b1edbc 12772 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */
AnnaBridge 171:3a7713b1edbc 12773 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!< PF[4] pin */
AnnaBridge 171:3a7713b1edbc 12774
AnnaBridge 171:3a7713b1edbc 12775 /*!<*
AnnaBridge 171:3a7713b1edbc 12776 * @brief EXTI5 configuration
AnnaBridge 171:3a7713b1edbc 12777 */
AnnaBridge 171:3a7713b1edbc 12778 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
AnnaBridge 171:3a7713b1edbc 12779 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
AnnaBridge 171:3a7713b1edbc 12780 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
AnnaBridge 171:3a7713b1edbc 12781 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
AnnaBridge 171:3a7713b1edbc 12782 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */
AnnaBridge 171:3a7713b1edbc 12783 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!< PF[5] pin */
AnnaBridge 171:3a7713b1edbc 12784
AnnaBridge 171:3a7713b1edbc 12785 /*!<*
AnnaBridge 171:3a7713b1edbc 12786 * @brief EXTI6 configuration
AnnaBridge 171:3a7713b1edbc 12787 */
AnnaBridge 171:3a7713b1edbc 12788 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
AnnaBridge 171:3a7713b1edbc 12789 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
AnnaBridge 171:3a7713b1edbc 12790 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
AnnaBridge 171:3a7713b1edbc 12791 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
AnnaBridge 171:3a7713b1edbc 12792 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */
AnnaBridge 171:3a7713b1edbc 12793 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!< PF[6] pin */
AnnaBridge 171:3a7713b1edbc 12794
AnnaBridge 171:3a7713b1edbc 12795 /*!<*
AnnaBridge 171:3a7713b1edbc 12796 * @brief EXTI7 configuration
AnnaBridge 171:3a7713b1edbc 12797 */
AnnaBridge 171:3a7713b1edbc 12798 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
AnnaBridge 171:3a7713b1edbc 12799 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
AnnaBridge 171:3a7713b1edbc 12800 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
AnnaBridge 171:3a7713b1edbc 12801 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
AnnaBridge 171:3a7713b1edbc 12802 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */
AnnaBridge 171:3a7713b1edbc 12803
AnnaBridge 171:3a7713b1edbc 12804 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
AnnaBridge 171:3a7713b1edbc 12805 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12806 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 12807 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
AnnaBridge 171:3a7713b1edbc 12808 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12809 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 12810 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
AnnaBridge 171:3a7713b1edbc 12811 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12812 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 12813 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
AnnaBridge 171:3a7713b1edbc 12814 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12815 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 12816 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
AnnaBridge 171:3a7713b1edbc 12817
AnnaBridge 171:3a7713b1edbc 12818 /*!<*
AnnaBridge 171:3a7713b1edbc 12819 * @brief EXTI8 configuration
AnnaBridge 171:3a7713b1edbc 12820 */
AnnaBridge 171:3a7713b1edbc 12821 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
AnnaBridge 171:3a7713b1edbc 12822 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
AnnaBridge 171:3a7713b1edbc 12823 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
AnnaBridge 171:3a7713b1edbc 12824 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
AnnaBridge 171:3a7713b1edbc 12825 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */
AnnaBridge 171:3a7713b1edbc 12826
AnnaBridge 171:3a7713b1edbc 12827 /*!<*
AnnaBridge 171:3a7713b1edbc 12828 * @brief EXTI9 configuration
AnnaBridge 171:3a7713b1edbc 12829 */
AnnaBridge 171:3a7713b1edbc 12830 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
AnnaBridge 171:3a7713b1edbc 12831 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
AnnaBridge 171:3a7713b1edbc 12832 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
AnnaBridge 171:3a7713b1edbc 12833 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
AnnaBridge 171:3a7713b1edbc 12834 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */
AnnaBridge 171:3a7713b1edbc 12835 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!< PF[9] pin */
AnnaBridge 171:3a7713b1edbc 12836
AnnaBridge 171:3a7713b1edbc 12837 /*!<*
AnnaBridge 171:3a7713b1edbc 12838 * @brief EXTI10 configuration
AnnaBridge 171:3a7713b1edbc 12839 */
AnnaBridge 171:3a7713b1edbc 12840 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
AnnaBridge 171:3a7713b1edbc 12841 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
AnnaBridge 171:3a7713b1edbc 12842 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
AnnaBridge 171:3a7713b1edbc 12843 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
AnnaBridge 171:3a7713b1edbc 12844 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */
AnnaBridge 171:3a7713b1edbc 12845 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!< PF[10] pin */
AnnaBridge 171:3a7713b1edbc 12846
AnnaBridge 171:3a7713b1edbc 12847 /*!<*
AnnaBridge 171:3a7713b1edbc 12848 * @brief EXTI11 configuration
AnnaBridge 171:3a7713b1edbc 12849 */
AnnaBridge 171:3a7713b1edbc 12850 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
AnnaBridge 171:3a7713b1edbc 12851 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
AnnaBridge 171:3a7713b1edbc 12852 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
AnnaBridge 171:3a7713b1edbc 12853 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
AnnaBridge 171:3a7713b1edbc 12854 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */
AnnaBridge 171:3a7713b1edbc 12855
AnnaBridge 171:3a7713b1edbc 12856 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
AnnaBridge 171:3a7713b1edbc 12857 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12858 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 12859 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
AnnaBridge 171:3a7713b1edbc 12860 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12861 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 12862 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
AnnaBridge 171:3a7713b1edbc 12863 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12864 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 12865 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
AnnaBridge 171:3a7713b1edbc 12866 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
AnnaBridge 171:3a7713b1edbc 12867 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 12868 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
AnnaBridge 171:3a7713b1edbc 12869
AnnaBridge 171:3a7713b1edbc 12870 /*!<*
AnnaBridge 171:3a7713b1edbc 12871 * @brief EXTI12 configuration
AnnaBridge 171:3a7713b1edbc 12872 */
AnnaBridge 171:3a7713b1edbc 12873 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
AnnaBridge 171:3a7713b1edbc 12874 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
AnnaBridge 171:3a7713b1edbc 12875 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
AnnaBridge 171:3a7713b1edbc 12876 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
AnnaBridge 171:3a7713b1edbc 12877 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */
AnnaBridge 171:3a7713b1edbc 12878
AnnaBridge 171:3a7713b1edbc 12879 /*!<*
AnnaBridge 171:3a7713b1edbc 12880 * @brief EXTI13 configuration
AnnaBridge 171:3a7713b1edbc 12881 */
AnnaBridge 171:3a7713b1edbc 12882 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
AnnaBridge 171:3a7713b1edbc 12883 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
AnnaBridge 171:3a7713b1edbc 12884 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
AnnaBridge 171:3a7713b1edbc 12885 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
AnnaBridge 171:3a7713b1edbc 12886 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */
AnnaBridge 171:3a7713b1edbc 12887
AnnaBridge 171:3a7713b1edbc 12888 /*!<*
AnnaBridge 171:3a7713b1edbc 12889 * @brief EXTI14 configuration
AnnaBridge 171:3a7713b1edbc 12890 */
AnnaBridge 171:3a7713b1edbc 12891 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
AnnaBridge 171:3a7713b1edbc 12892 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
AnnaBridge 171:3a7713b1edbc 12893 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
AnnaBridge 171:3a7713b1edbc 12894 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
AnnaBridge 171:3a7713b1edbc 12895 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */
AnnaBridge 171:3a7713b1edbc 12896
AnnaBridge 171:3a7713b1edbc 12897 /*!<*
AnnaBridge 171:3a7713b1edbc 12898 * @brief EXTI15 configuration
AnnaBridge 171:3a7713b1edbc 12899 */
AnnaBridge 171:3a7713b1edbc 12900 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
AnnaBridge 171:3a7713b1edbc 12901 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
AnnaBridge 171:3a7713b1edbc 12902 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
AnnaBridge 171:3a7713b1edbc 12903 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
AnnaBridge 171:3a7713b1edbc 12904 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
AnnaBridge 171:3a7713b1edbc 12905
AnnaBridge 171:3a7713b1edbc 12906 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
AnnaBridge 171:3a7713b1edbc 12907 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12908 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12909 #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
AnnaBridge 171:3a7713b1edbc 12910 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12911 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1U << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12912 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
AnnaBridge 171:3a7713b1edbc 12913 #define SYSCFG_CFGR2_PVD_LOCK_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12914 #define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1U << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12915 #define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
AnnaBridge 171:3a7713b1edbc 12916 #define SYSCFG_CFGR2_BYP_ADDR_PAR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12917 #define SYSCFG_CFGR2_BYP_ADDR_PAR_Msk (0x1U << SYSCFG_CFGR2_BYP_ADDR_PAR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12918 #define SYSCFG_CFGR2_BYP_ADDR_PAR SYSCFG_CFGR2_BYP_ADDR_PAR_Msk /*!< Disables the adddress parity check on RAM */
AnnaBridge 171:3a7713b1edbc 12919 #define SYSCFG_CFGR2_SRAM_PE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12920 #define SYSCFG_CFGR2_SRAM_PE_Msk (0x1U << SYSCFG_CFGR2_SRAM_PE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12921 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PE_Msk /*!< SRAM Parity error flag */
AnnaBridge 171:3a7713b1edbc 12922
AnnaBridge 171:3a7713b1edbc 12923 /***************** Bit definition for SYSCFG_CFGR3 register *****************/
AnnaBridge 171:3a7713b1edbc 12924 #define SYSCFG_CFGR3_DMA_RMP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12925 #define SYSCFG_CFGR3_DMA_RMP_Msk (0x3FFU << SYSCFG_CFGR3_DMA_RMP_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 12926 #define SYSCFG_CFGR3_DMA_RMP SYSCFG_CFGR3_DMA_RMP_Msk /*!< DMA remap mask */
AnnaBridge 171:3a7713b1edbc 12927 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12928 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Msk (0x3U << SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 12929 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Msk /*!< SPI1 RX DMA remap */
AnnaBridge 171:3a7713b1edbc 12930 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0 (0x1U << SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12931 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1 (0x2U << SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12932 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12933 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Msk (0x3U << SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 12934 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Msk /*!< SPI1 TX DMA remap */
AnnaBridge 171:3a7713b1edbc 12935 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0 (0x1U << SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12936 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1 (0x2U << SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12937 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12938 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Msk (0x3U << SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 12939 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Msk /*!< I2C1 RX DMA remap */
AnnaBridge 171:3a7713b1edbc 12940 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0 (0x1U << SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12941 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1 (0x2U << SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12942 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Pos (6U)
AnnaBridge 171:3a7713b1edbc 12943 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Msk (0x3U << SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 12944 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Msk /*!< I2C1 RX DMA remap */
AnnaBridge 171:3a7713b1edbc 12945 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0 (0x1U << SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12946 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1 (0x2U << SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12947 #define SYSCFG_CFGR3_ADC2_DMA_RMP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12948 #define SYSCFG_CFGR3_ADC2_DMA_RMP_Msk (0x3U << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 12949 #define SYSCFG_CFGR3_ADC2_DMA_RMP SYSCFG_CFGR3_ADC2_DMA_RMP_Msk /*!< ADC2 DMA remap */
AnnaBridge 171:3a7713b1edbc 12950 #define SYSCFG_CFGR3_ADC2_DMA_RMP_0 (0x1U << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12951 #define SYSCFG_CFGR3_ADC2_DMA_RMP_1 (0x2U << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12952 #define SYSCFG_CFGR3_TRIGGER_RMP_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12953 #define SYSCFG_CFGR3_TRIGGER_RMP_Msk (0x3U << SYSCFG_CFGR3_TRIGGER_RMP_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 12954 #define SYSCFG_CFGR3_TRIGGER_RMP SYSCFG_CFGR3_TRIGGER_RMP_Msk /*!< Trigger remap mask */
AnnaBridge 171:3a7713b1edbc 12955 #define SYSCFG_CFGR3_DAC1_TRG3_RMP_Pos (16U)
AnnaBridge 171:3a7713b1edbc 12956 #define SYSCFG_CFGR3_DAC1_TRG3_RMP_Msk (0x1U << SYSCFG_CFGR3_DAC1_TRG3_RMP_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 12957 #define SYSCFG_CFGR3_DAC1_TRG3_RMP SYSCFG_CFGR3_DAC1_TRG3_RMP_Msk /*!< DAC1 TRG3 remap */
AnnaBridge 171:3a7713b1edbc 12958 #define SYSCFG_CFGR3_DAC1_TRG5_RMP_Pos (17U)
AnnaBridge 171:3a7713b1edbc 12959 #define SYSCFG_CFGR3_DAC1_TRG5_RMP_Msk (0x1U << SYSCFG_CFGR3_DAC1_TRG5_RMP_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 12960 #define SYSCFG_CFGR3_DAC1_TRG5_RMP SYSCFG_CFGR3_DAC1_TRG5_RMP_Msk /*!< DAC1 TRG5 remap */
AnnaBridge 171:3a7713b1edbc 12961
AnnaBridge 171:3a7713b1edbc 12962 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12963 /* */
AnnaBridge 171:3a7713b1edbc 12964 /* TIM */
AnnaBridge 171:3a7713b1edbc 12965 /* */
AnnaBridge 171:3a7713b1edbc 12966 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 12967 /******************* Bit definition for TIM_CR1 register ********************/
AnnaBridge 171:3a7713b1edbc 12968 #define TIM_CR1_CEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 12969 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 12970 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
AnnaBridge 171:3a7713b1edbc 12971 #define TIM_CR1_UDIS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 12972 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 12973 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
AnnaBridge 171:3a7713b1edbc 12974 #define TIM_CR1_URS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 12975 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 12976 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
AnnaBridge 171:3a7713b1edbc 12977 #define TIM_CR1_OPM_Pos (3U)
AnnaBridge 171:3a7713b1edbc 12978 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 12979 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
AnnaBridge 171:3a7713b1edbc 12980 #define TIM_CR1_DIR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 12981 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 12982 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
AnnaBridge 171:3a7713b1edbc 12983
AnnaBridge 171:3a7713b1edbc 12984 #define TIM_CR1_CMS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 12985 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
AnnaBridge 171:3a7713b1edbc 12986 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
AnnaBridge 171:3a7713b1edbc 12987 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 12988 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 12989
AnnaBridge 171:3a7713b1edbc 12990 #define TIM_CR1_ARPE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 12991 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 12992 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
AnnaBridge 171:3a7713b1edbc 12993
AnnaBridge 171:3a7713b1edbc 12994 #define TIM_CR1_CKD_Pos (8U)
AnnaBridge 171:3a7713b1edbc 12995 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 12996 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
AnnaBridge 171:3a7713b1edbc 12997 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 12998 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 12999
AnnaBridge 171:3a7713b1edbc 13000 #define TIM_CR1_UIFREMAP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13001 #define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13002 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
AnnaBridge 171:3a7713b1edbc 13003
AnnaBridge 171:3a7713b1edbc 13004 /******************* Bit definition for TIM_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 13005 #define TIM_CR2_CCPC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13006 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13007 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
AnnaBridge 171:3a7713b1edbc 13008 #define TIM_CR2_CCUS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13009 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13010 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
AnnaBridge 171:3a7713b1edbc 13011 #define TIM_CR2_CCDS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13012 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13013 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
AnnaBridge 171:3a7713b1edbc 13014
AnnaBridge 171:3a7713b1edbc 13015 #define TIM_CR2_MMS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13016 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 13017 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
AnnaBridge 171:3a7713b1edbc 13018 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13019 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13020 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13021
AnnaBridge 171:3a7713b1edbc 13022 #define TIM_CR2_TI1S_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13023 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13024 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
AnnaBridge 171:3a7713b1edbc 13025 #define TIM_CR2_OIS1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13026 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13027 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
AnnaBridge 171:3a7713b1edbc 13028 #define TIM_CR2_OIS1N_Pos (9U)
AnnaBridge 171:3a7713b1edbc 13029 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13030 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
AnnaBridge 171:3a7713b1edbc 13031 #define TIM_CR2_OIS2_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13032 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13033 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
AnnaBridge 171:3a7713b1edbc 13034 #define TIM_CR2_OIS2N_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13035 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13036 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
AnnaBridge 171:3a7713b1edbc 13037 #define TIM_CR2_OIS3_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13038 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13039 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
AnnaBridge 171:3a7713b1edbc 13040 #define TIM_CR2_OIS3N_Pos (13U)
AnnaBridge 171:3a7713b1edbc 13041 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13042 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
AnnaBridge 171:3a7713b1edbc 13043 #define TIM_CR2_OIS4_Pos (14U)
AnnaBridge 171:3a7713b1edbc 13044 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13045 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
AnnaBridge 171:3a7713b1edbc 13046
AnnaBridge 171:3a7713b1edbc 13047 #define TIM_CR2_OIS5_Pos (16U)
AnnaBridge 171:3a7713b1edbc 13048 #define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 13049 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
AnnaBridge 171:3a7713b1edbc 13050 #define TIM_CR2_OIS6_Pos (18U)
AnnaBridge 171:3a7713b1edbc 13051 #define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 13052 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
AnnaBridge 171:3a7713b1edbc 13053
AnnaBridge 171:3a7713b1edbc 13054 #define TIM_CR2_MMS2_Pos (20U)
AnnaBridge 171:3a7713b1edbc 13055 #define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 13056 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
AnnaBridge 171:3a7713b1edbc 13057 #define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 13058 #define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 13059 #define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 13060 #define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 13061
AnnaBridge 171:3a7713b1edbc 13062 /******************* Bit definition for TIM_SMCR register *******************/
AnnaBridge 171:3a7713b1edbc 13063 #define TIM_SMCR_SMS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13064 #define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
AnnaBridge 171:3a7713b1edbc 13065 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
AnnaBridge 171:3a7713b1edbc 13066 #define TIM_SMCR_SMS_0 (0x00000001U) /*!<Bit 0 */
AnnaBridge 171:3a7713b1edbc 13067 #define TIM_SMCR_SMS_1 (0x00000002U) /*!<Bit 1 */
AnnaBridge 171:3a7713b1edbc 13068 #define TIM_SMCR_SMS_2 (0x00000004U) /*!<Bit 2 */
AnnaBridge 171:3a7713b1edbc 13069 #define TIM_SMCR_SMS_3 (0x00010000U) /*!<Bit 3 */
AnnaBridge 171:3a7713b1edbc 13070
AnnaBridge 171:3a7713b1edbc 13071 #define TIM_SMCR_OCCS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13072 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13073 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
AnnaBridge 171:3a7713b1edbc 13074
AnnaBridge 171:3a7713b1edbc 13075 #define TIM_SMCR_TS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13076 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 13077 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
AnnaBridge 171:3a7713b1edbc 13078 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13079 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13080 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13081
AnnaBridge 171:3a7713b1edbc 13082 #define TIM_SMCR_MSM_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13083 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13084 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
AnnaBridge 171:3a7713b1edbc 13085
AnnaBridge 171:3a7713b1edbc 13086 #define TIM_SMCR_ETF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13087 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 13088 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
AnnaBridge 171:3a7713b1edbc 13089 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13090 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13091 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13092 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13093
AnnaBridge 171:3a7713b1edbc 13094 #define TIM_SMCR_ETPS_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13095 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 13096 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
AnnaBridge 171:3a7713b1edbc 13097 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13098 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13099
AnnaBridge 171:3a7713b1edbc 13100 #define TIM_SMCR_ECE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 13101 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13102 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
AnnaBridge 171:3a7713b1edbc 13103 #define TIM_SMCR_ETP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 13104 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13105 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
AnnaBridge 171:3a7713b1edbc 13106
AnnaBridge 171:3a7713b1edbc 13107 /******************* Bit definition for TIM_DIER register *******************/
AnnaBridge 171:3a7713b1edbc 13108 #define TIM_DIER_UIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13109 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13110 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
AnnaBridge 171:3a7713b1edbc 13111 #define TIM_DIER_CC1IE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13112 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13113 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
AnnaBridge 171:3a7713b1edbc 13114 #define TIM_DIER_CC2IE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13115 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13116 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
AnnaBridge 171:3a7713b1edbc 13117 #define TIM_DIER_CC3IE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13118 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13119 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
AnnaBridge 171:3a7713b1edbc 13120 #define TIM_DIER_CC4IE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13121 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13122 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
AnnaBridge 171:3a7713b1edbc 13123 #define TIM_DIER_COMIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13124 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13125 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
AnnaBridge 171:3a7713b1edbc 13126 #define TIM_DIER_TIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13127 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13128 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
AnnaBridge 171:3a7713b1edbc 13129 #define TIM_DIER_BIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13130 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13131 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
AnnaBridge 171:3a7713b1edbc 13132 #define TIM_DIER_UDE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13133 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13134 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
AnnaBridge 171:3a7713b1edbc 13135 #define TIM_DIER_CC1DE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 13136 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13137 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
AnnaBridge 171:3a7713b1edbc 13138 #define TIM_DIER_CC2DE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13139 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13140 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
AnnaBridge 171:3a7713b1edbc 13141 #define TIM_DIER_CC3DE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13142 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13143 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
AnnaBridge 171:3a7713b1edbc 13144 #define TIM_DIER_CC4DE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13145 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13146 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
AnnaBridge 171:3a7713b1edbc 13147 #define TIM_DIER_COMDE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 13148 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13149 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
AnnaBridge 171:3a7713b1edbc 13150 #define TIM_DIER_TDE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 13151 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13152 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
AnnaBridge 171:3a7713b1edbc 13153
AnnaBridge 171:3a7713b1edbc 13154 /******************** Bit definition for TIM_SR register ********************/
AnnaBridge 171:3a7713b1edbc 13155 #define TIM_SR_UIF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13156 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13157 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13158 #define TIM_SR_CC1IF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13159 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13160 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13161 #define TIM_SR_CC2IF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13162 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13163 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13164 #define TIM_SR_CC3IF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13165 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13166 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13167 #define TIM_SR_CC4IF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13168 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13169 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13170 #define TIM_SR_COMIF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13171 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13172 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13173 #define TIM_SR_TIF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13174 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13175 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13176 #define TIM_SR_BIF_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13177 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13178 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13179 #define TIM_SR_B2IF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13180 #define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13181 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13182 #define TIM_SR_CC1OF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 13183 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13184 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 13185 #define TIM_SR_CC2OF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13186 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13187 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 13188 #define TIM_SR_CC3OF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13189 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13190 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 13191 #define TIM_SR_CC4OF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13192 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13193 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 13194 #define TIM_SR_CC5IF_Pos (16U)
AnnaBridge 171:3a7713b1edbc 13195 #define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 13196 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13197 #define TIM_SR_CC6IF_Pos (17U)
AnnaBridge 171:3a7713b1edbc 13198 #define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 13199 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 13200
AnnaBridge 171:3a7713b1edbc 13201 /******************* Bit definition for TIM_EGR register ********************/
AnnaBridge 171:3a7713b1edbc 13202 #define TIM_EGR_UG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13203 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13204 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
AnnaBridge 171:3a7713b1edbc 13205 #define TIM_EGR_CC1G_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13206 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13207 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
AnnaBridge 171:3a7713b1edbc 13208 #define TIM_EGR_CC2G_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13209 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13210 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
AnnaBridge 171:3a7713b1edbc 13211 #define TIM_EGR_CC3G_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13212 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13213 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
AnnaBridge 171:3a7713b1edbc 13214 #define TIM_EGR_CC4G_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13215 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13216 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
AnnaBridge 171:3a7713b1edbc 13217 #define TIM_EGR_COMG_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13218 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13219 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
AnnaBridge 171:3a7713b1edbc 13220 #define TIM_EGR_TG_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13221 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13222 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
AnnaBridge 171:3a7713b1edbc 13223 #define TIM_EGR_BG_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13224 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13225 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
AnnaBridge 171:3a7713b1edbc 13226 #define TIM_EGR_B2G_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13227 #define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13228 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break Generation */
AnnaBridge 171:3a7713b1edbc 13229
AnnaBridge 171:3a7713b1edbc 13230 /****************** Bit definition for TIM_CCMR1 register *******************/
AnnaBridge 171:3a7713b1edbc 13231 #define TIM_CCMR1_CC1S_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13232 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 13233 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
AnnaBridge 171:3a7713b1edbc 13234 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13235 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13236
AnnaBridge 171:3a7713b1edbc 13237 #define TIM_CCMR1_OC1FE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13238 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13239 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
AnnaBridge 171:3a7713b1edbc 13240 #define TIM_CCMR1_OC1PE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13241 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13242 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
AnnaBridge 171:3a7713b1edbc 13243
AnnaBridge 171:3a7713b1edbc 13244 #define TIM_CCMR1_OC1M_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13245 #define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
AnnaBridge 171:3a7713b1edbc 13246 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
AnnaBridge 171:3a7713b1edbc 13247 #define TIM_CCMR1_OC1M_0 (0x00000010U) /*!<Bit 0 */
AnnaBridge 171:3a7713b1edbc 13248 #define TIM_CCMR1_OC1M_1 (0x00000020U) /*!<Bit 1 */
AnnaBridge 171:3a7713b1edbc 13249 #define TIM_CCMR1_OC1M_2 (0x00000040U) /*!<Bit 2 */
AnnaBridge 171:3a7713b1edbc 13250 #define TIM_CCMR1_OC1M_3 (0x00010000U) /*!<Bit 3 */
AnnaBridge 171:3a7713b1edbc 13251
AnnaBridge 171:3a7713b1edbc 13252 #define TIM_CCMR1_OC1CE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13253 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13254 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
AnnaBridge 171:3a7713b1edbc 13255
AnnaBridge 171:3a7713b1edbc 13256 #define TIM_CCMR1_CC2S_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13257 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 13258 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
AnnaBridge 171:3a7713b1edbc 13259 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13260 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13261
AnnaBridge 171:3a7713b1edbc 13262 #define TIM_CCMR1_OC2FE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13263 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13264 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
AnnaBridge 171:3a7713b1edbc 13265 #define TIM_CCMR1_OC2PE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13266 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13267 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
AnnaBridge 171:3a7713b1edbc 13268
AnnaBridge 171:3a7713b1edbc 13269 #define TIM_CCMR1_OC2M_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13270 #define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
AnnaBridge 171:3a7713b1edbc 13271 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
AnnaBridge 171:3a7713b1edbc 13272 #define TIM_CCMR1_OC2M_0 (0x00001000U) /*!<Bit 0 */
AnnaBridge 171:3a7713b1edbc 13273 #define TIM_CCMR1_OC2M_1 (0x00002000U) /*!<Bit 1 */
AnnaBridge 171:3a7713b1edbc 13274 #define TIM_CCMR1_OC2M_2 (0x00004000U) /*!<Bit 2 */
AnnaBridge 171:3a7713b1edbc 13275 #define TIM_CCMR1_OC2M_3 (0x01000000U) /*!<Bit 3 */
AnnaBridge 171:3a7713b1edbc 13276
AnnaBridge 171:3a7713b1edbc 13277 #define TIM_CCMR1_OC2CE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 13278 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13279 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
AnnaBridge 171:3a7713b1edbc 13280
AnnaBridge 171:3a7713b1edbc 13281 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 13282
AnnaBridge 171:3a7713b1edbc 13283 #define TIM_CCMR1_IC1PSC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13284 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 13285 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
AnnaBridge 171:3a7713b1edbc 13286 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13287 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13288
AnnaBridge 171:3a7713b1edbc 13289 #define TIM_CCMR1_IC1F_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13290 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 13291 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
AnnaBridge 171:3a7713b1edbc 13292 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13293 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13294 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13295 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13296
AnnaBridge 171:3a7713b1edbc 13297 #define TIM_CCMR1_IC2PSC_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13298 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 13299 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
AnnaBridge 171:3a7713b1edbc 13300 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13301 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13302
AnnaBridge 171:3a7713b1edbc 13303 #define TIM_CCMR1_IC2F_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13304 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 13305 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
AnnaBridge 171:3a7713b1edbc 13306 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13307 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13308 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13309 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13310
AnnaBridge 171:3a7713b1edbc 13311 /****************** Bit definition for TIM_CCMR2 register *******************/
AnnaBridge 171:3a7713b1edbc 13312 #define TIM_CCMR2_CC3S_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13313 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 13314 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
AnnaBridge 171:3a7713b1edbc 13315 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13316 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13317
AnnaBridge 171:3a7713b1edbc 13318 #define TIM_CCMR2_OC3FE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13319 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13320 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
AnnaBridge 171:3a7713b1edbc 13321 #define TIM_CCMR2_OC3PE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13322 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13323 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
AnnaBridge 171:3a7713b1edbc 13324
AnnaBridge 171:3a7713b1edbc 13325 #define TIM_CCMR2_OC3M_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13326 #define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
AnnaBridge 171:3a7713b1edbc 13327 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
AnnaBridge 171:3a7713b1edbc 13328 #define TIM_CCMR2_OC3M_0 (0x00000010U) /*!<Bit 0 */
AnnaBridge 171:3a7713b1edbc 13329 #define TIM_CCMR2_OC3M_1 (0x00000020U) /*!<Bit 1 */
AnnaBridge 171:3a7713b1edbc 13330 #define TIM_CCMR2_OC3M_2 (0x00000040U) /*!<Bit 2 */
AnnaBridge 171:3a7713b1edbc 13331 #define TIM_CCMR2_OC3M_3 (0x00010000U) /*!<Bit 3 */
AnnaBridge 171:3a7713b1edbc 13332
AnnaBridge 171:3a7713b1edbc 13333 #define TIM_CCMR2_OC3CE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13334 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13335 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
AnnaBridge 171:3a7713b1edbc 13336
AnnaBridge 171:3a7713b1edbc 13337 #define TIM_CCMR2_CC4S_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13338 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 13339 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
AnnaBridge 171:3a7713b1edbc 13340 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13341 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13342
AnnaBridge 171:3a7713b1edbc 13343 #define TIM_CCMR2_OC4FE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13344 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13345 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
AnnaBridge 171:3a7713b1edbc 13346 #define TIM_CCMR2_OC4PE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13347 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13348 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
AnnaBridge 171:3a7713b1edbc 13349
AnnaBridge 171:3a7713b1edbc 13350 #define TIM_CCMR2_OC4M_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13351 #define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
AnnaBridge 171:3a7713b1edbc 13352 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
AnnaBridge 171:3a7713b1edbc 13353 #define TIM_CCMR2_OC4M_0 (0x00001000U) /*!<Bit 0 */
AnnaBridge 171:3a7713b1edbc 13354 #define TIM_CCMR2_OC4M_1 (0x00002000U) /*!<Bit 1 */
AnnaBridge 171:3a7713b1edbc 13355 #define TIM_CCMR2_OC4M_2 (0x00004000U) /*!<Bit 2 */
AnnaBridge 171:3a7713b1edbc 13356 #define TIM_CCMR2_OC4M_3 (0x01000000U) /*!<Bit 3 */
AnnaBridge 171:3a7713b1edbc 13357
AnnaBridge 171:3a7713b1edbc 13358 #define TIM_CCMR2_OC4CE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 13359 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13360 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
AnnaBridge 171:3a7713b1edbc 13361
AnnaBridge 171:3a7713b1edbc 13362 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 13363
AnnaBridge 171:3a7713b1edbc 13364 #define TIM_CCMR2_IC3PSC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13365 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 13366 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
AnnaBridge 171:3a7713b1edbc 13367 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13368 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13369
AnnaBridge 171:3a7713b1edbc 13370 #define TIM_CCMR2_IC3F_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13371 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 13372 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
AnnaBridge 171:3a7713b1edbc 13373 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13374 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13375 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13376 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13377
AnnaBridge 171:3a7713b1edbc 13378 #define TIM_CCMR2_IC4PSC_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13379 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 13380 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
AnnaBridge 171:3a7713b1edbc 13381 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13382 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13383
AnnaBridge 171:3a7713b1edbc 13384 #define TIM_CCMR2_IC4F_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13385 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 13386 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
AnnaBridge 171:3a7713b1edbc 13387 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13388 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13389 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13390 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13391
AnnaBridge 171:3a7713b1edbc 13392 /******************* Bit definition for TIM_CCER register *******************/
AnnaBridge 171:3a7713b1edbc 13393 #define TIM_CCER_CC1E_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13394 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13395 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
AnnaBridge 171:3a7713b1edbc 13396 #define TIM_CCER_CC1P_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13397 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13398 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
AnnaBridge 171:3a7713b1edbc 13399 #define TIM_CCER_CC1NE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13400 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13401 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
AnnaBridge 171:3a7713b1edbc 13402 #define TIM_CCER_CC1NP_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13403 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13404 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 13405 #define TIM_CCER_CC2E_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13406 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13407 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
AnnaBridge 171:3a7713b1edbc 13408 #define TIM_CCER_CC2P_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13409 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13410 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
AnnaBridge 171:3a7713b1edbc 13411 #define TIM_CCER_CC2NE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13412 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13413 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
AnnaBridge 171:3a7713b1edbc 13414 #define TIM_CCER_CC2NP_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13415 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13416 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 13417 #define TIM_CCER_CC3E_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13418 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13419 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
AnnaBridge 171:3a7713b1edbc 13420 #define TIM_CCER_CC3P_Pos (9U)
AnnaBridge 171:3a7713b1edbc 13421 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13422 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
AnnaBridge 171:3a7713b1edbc 13423 #define TIM_CCER_CC3NE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13424 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13425 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
AnnaBridge 171:3a7713b1edbc 13426 #define TIM_CCER_CC3NP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13427 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13428 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 13429 #define TIM_CCER_CC4E_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13430 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13431 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
AnnaBridge 171:3a7713b1edbc 13432 #define TIM_CCER_CC4P_Pos (13U)
AnnaBridge 171:3a7713b1edbc 13433 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13434 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
AnnaBridge 171:3a7713b1edbc 13435 #define TIM_CCER_CC4NP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 13436 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13437 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 13438 #define TIM_CCER_CC5E_Pos (16U)
AnnaBridge 171:3a7713b1edbc 13439 #define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 13440 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
AnnaBridge 171:3a7713b1edbc 13441 #define TIM_CCER_CC5P_Pos (17U)
AnnaBridge 171:3a7713b1edbc 13442 #define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 13443 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
AnnaBridge 171:3a7713b1edbc 13444 #define TIM_CCER_CC6E_Pos (20U)
AnnaBridge 171:3a7713b1edbc 13445 #define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 13446 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
AnnaBridge 171:3a7713b1edbc 13447 #define TIM_CCER_CC6P_Pos (21U)
AnnaBridge 171:3a7713b1edbc 13448 #define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 13449 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
AnnaBridge 171:3a7713b1edbc 13450
AnnaBridge 171:3a7713b1edbc 13451 /******************* Bit definition for TIM_CNT register ********************/
AnnaBridge 171:3a7713b1edbc 13452 #define TIM_CNT_CNT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13453 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 13454 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
AnnaBridge 171:3a7713b1edbc 13455 #define TIM_CNT_UIFCPY_Pos (31U)
AnnaBridge 171:3a7713b1edbc 13456 #define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 13457 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy */
AnnaBridge 171:3a7713b1edbc 13458
AnnaBridge 171:3a7713b1edbc 13459 /******************* Bit definition for TIM_PSC register ********************/
AnnaBridge 171:3a7713b1edbc 13460 #define TIM_PSC_PSC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13461 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 13462 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
AnnaBridge 171:3a7713b1edbc 13463
AnnaBridge 171:3a7713b1edbc 13464 /******************* Bit definition for TIM_ARR register ********************/
AnnaBridge 171:3a7713b1edbc 13465 #define TIM_ARR_ARR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13466 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 13467 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
AnnaBridge 171:3a7713b1edbc 13468
AnnaBridge 171:3a7713b1edbc 13469 /******************* Bit definition for TIM_RCR register ********************/
AnnaBridge 171:3a7713b1edbc 13470 #define TIM_RCR_REP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13471 #define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 13472 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
AnnaBridge 171:3a7713b1edbc 13473
AnnaBridge 171:3a7713b1edbc 13474 /******************* Bit definition for TIM_CCR1 register *******************/
AnnaBridge 171:3a7713b1edbc 13475 #define TIM_CCR1_CCR1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13476 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 13477 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
AnnaBridge 171:3a7713b1edbc 13478
AnnaBridge 171:3a7713b1edbc 13479 /******************* Bit definition for TIM_CCR2 register *******************/
AnnaBridge 171:3a7713b1edbc 13480 #define TIM_CCR2_CCR2_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13481 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 13482 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
AnnaBridge 171:3a7713b1edbc 13483
AnnaBridge 171:3a7713b1edbc 13484 /******************* Bit definition for TIM_CCR3 register *******************/
AnnaBridge 171:3a7713b1edbc 13485 #define TIM_CCR3_CCR3_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13486 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 13487 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
AnnaBridge 171:3a7713b1edbc 13488
AnnaBridge 171:3a7713b1edbc 13489 /******************* Bit definition for TIM_CCR4 register *******************/
AnnaBridge 171:3a7713b1edbc 13490 #define TIM_CCR4_CCR4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13491 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 13492 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
AnnaBridge 171:3a7713b1edbc 13493
AnnaBridge 171:3a7713b1edbc 13494 /******************* Bit definition for TIM_CCR5 register *******************/
AnnaBridge 171:3a7713b1edbc 13495 #define TIM_CCR5_CCR5_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13496 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 13497 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
AnnaBridge 171:3a7713b1edbc 13498 #define TIM_CCR5_GC5C1_Pos (29U)
AnnaBridge 171:3a7713b1edbc 13499 #define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 13500 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
AnnaBridge 171:3a7713b1edbc 13501 #define TIM_CCR5_GC5C2_Pos (30U)
AnnaBridge 171:3a7713b1edbc 13502 #define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 13503 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
AnnaBridge 171:3a7713b1edbc 13504 #define TIM_CCR5_GC5C3_Pos (31U)
AnnaBridge 171:3a7713b1edbc 13505 #define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 13506 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
AnnaBridge 171:3a7713b1edbc 13507
AnnaBridge 171:3a7713b1edbc 13508 /******************* Bit definition for TIM_CCR6 register *******************/
AnnaBridge 171:3a7713b1edbc 13509 #define TIM_CCR6_CCR6_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13510 #define TIM_CCR6_CCR6_Msk (0xFFFFU << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 13511 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
AnnaBridge 171:3a7713b1edbc 13512
AnnaBridge 171:3a7713b1edbc 13513 /******************* Bit definition for TIM_BDTR register *******************/
AnnaBridge 171:3a7713b1edbc 13514 #define TIM_BDTR_DTG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13515 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 13516 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
AnnaBridge 171:3a7713b1edbc 13517 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13518 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13519 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13520 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13521 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13522 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13523 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13524 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13525
AnnaBridge 171:3a7713b1edbc 13526 #define TIM_BDTR_LOCK_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13527 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 13528 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
AnnaBridge 171:3a7713b1edbc 13529 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13530 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13531
AnnaBridge 171:3a7713b1edbc 13532 #define TIM_BDTR_OSSI_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13533 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13534 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
AnnaBridge 171:3a7713b1edbc 13535 #define TIM_BDTR_OSSR_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13536 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13537 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
AnnaBridge 171:3a7713b1edbc 13538 #define TIM_BDTR_BKE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13539 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13540 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break1 */
AnnaBridge 171:3a7713b1edbc 13541 #define TIM_BDTR_BKP_Pos (13U)
AnnaBridge 171:3a7713b1edbc 13542 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13543 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break1 */
AnnaBridge 171:3a7713b1edbc 13544 #define TIM_BDTR_AOE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 13545 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13546 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
AnnaBridge 171:3a7713b1edbc 13547 #define TIM_BDTR_MOE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 13548 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13549 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
AnnaBridge 171:3a7713b1edbc 13550
AnnaBridge 171:3a7713b1edbc 13551 #define TIM_BDTR_BKF_Pos (16U)
AnnaBridge 171:3a7713b1edbc 13552 #define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 13553 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */
AnnaBridge 171:3a7713b1edbc 13554 #define TIM_BDTR_BK2F_Pos (20U)
AnnaBridge 171:3a7713b1edbc 13555 #define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 13556 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */
AnnaBridge 171:3a7713b1edbc 13557
AnnaBridge 171:3a7713b1edbc 13558 #define TIM_BDTR_BK2E_Pos (24U)
AnnaBridge 171:3a7713b1edbc 13559 #define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 13560 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */
AnnaBridge 171:3a7713b1edbc 13561 #define TIM_BDTR_BK2P_Pos (25U)
AnnaBridge 171:3a7713b1edbc 13562 #define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 13563 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
AnnaBridge 171:3a7713b1edbc 13564
AnnaBridge 171:3a7713b1edbc 13565 /******************* Bit definition for TIM_DCR register ********************/
AnnaBridge 171:3a7713b1edbc 13566 #define TIM_DCR_DBA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13567 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 13568 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
AnnaBridge 171:3a7713b1edbc 13569 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13570 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13571 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13572 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13573 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13574
AnnaBridge 171:3a7713b1edbc 13575 #define TIM_DCR_DBL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13576 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
AnnaBridge 171:3a7713b1edbc 13577 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
AnnaBridge 171:3a7713b1edbc 13578 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13579 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13580 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13581 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13582 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13583
AnnaBridge 171:3a7713b1edbc 13584 /******************* Bit definition for TIM_DMAR register *******************/
AnnaBridge 171:3a7713b1edbc 13585 #define TIM_DMAR_DMAB_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13586 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 13587 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
AnnaBridge 171:3a7713b1edbc 13588
AnnaBridge 171:3a7713b1edbc 13589 /******************* Bit definition for TIM16_OR register *********************/
AnnaBridge 171:3a7713b1edbc 13590 #define TIM16_OR_TI1_RMP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13591 #define TIM16_OR_TI1_RMP_Msk (0x3U << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 13592 #define TIM16_OR_TI1_RMP TIM16_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
AnnaBridge 171:3a7713b1edbc 13593 #define TIM16_OR_TI1_RMP_0 (0x1U << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13594 #define TIM16_OR_TI1_RMP_1 (0x2U << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13595
AnnaBridge 171:3a7713b1edbc 13596 /******************* Bit definition for TIM1_OR register *********************/
AnnaBridge 171:3a7713b1edbc 13597 #define TIM1_OR_ETR_RMP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13598 #define TIM1_OR_ETR_RMP_Msk (0xFU << TIM1_OR_ETR_RMP_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 13599 #define TIM1_OR_ETR_RMP TIM1_OR_ETR_RMP_Msk /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
AnnaBridge 171:3a7713b1edbc 13600 #define TIM1_OR_ETR_RMP_0 (0x1U << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13601 #define TIM1_OR_ETR_RMP_1 (0x2U << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13602 #define TIM1_OR_ETR_RMP_2 (0x4U << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13603 #define TIM1_OR_ETR_RMP_3 (0x8U << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13604
AnnaBridge 171:3a7713b1edbc 13605 /****************** Bit definition for TIM_CCMR3 register *******************/
AnnaBridge 171:3a7713b1edbc 13606 #define TIM_CCMR3_OC5FE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13607 #define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13608 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
AnnaBridge 171:3a7713b1edbc 13609 #define TIM_CCMR3_OC5PE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13610 #define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13611 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
AnnaBridge 171:3a7713b1edbc 13612
AnnaBridge 171:3a7713b1edbc 13613 #define TIM_CCMR3_OC5M_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13614 #define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
AnnaBridge 171:3a7713b1edbc 13615 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
AnnaBridge 171:3a7713b1edbc 13616 #define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13617 #define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13618 #define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13619 #define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 13620
AnnaBridge 171:3a7713b1edbc 13621 #define TIM_CCMR3_OC5CE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13622 #define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13623 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
AnnaBridge 171:3a7713b1edbc 13624
AnnaBridge 171:3a7713b1edbc 13625 #define TIM_CCMR3_OC6FE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13626 #define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13627 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
AnnaBridge 171:3a7713b1edbc 13628 #define TIM_CCMR3_OC6PE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13629 #define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13630 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
AnnaBridge 171:3a7713b1edbc 13631
AnnaBridge 171:3a7713b1edbc 13632 #define TIM_CCMR3_OC6M_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13633 #define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
AnnaBridge 171:3a7713b1edbc 13634 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[2:0] bits (Output Compare 6 Mode) */
AnnaBridge 171:3a7713b1edbc 13635 #define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13636 #define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13637 #define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13638 #define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 13639
AnnaBridge 171:3a7713b1edbc 13640 #define TIM_CCMR3_OC6CE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 13641 #define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13642 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
AnnaBridge 171:3a7713b1edbc 13643
AnnaBridge 171:3a7713b1edbc 13644 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 13645 /* */
AnnaBridge 171:3a7713b1edbc 13646 /* Touch Sensing Controller (TSC) */
AnnaBridge 171:3a7713b1edbc 13647 /* */
AnnaBridge 171:3a7713b1edbc 13648 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 13649 /******************* Bit definition for TSC_CR register *********************/
AnnaBridge 171:3a7713b1edbc 13650 #define TSC_CR_TSCE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13651 #define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13652 #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
AnnaBridge 171:3a7713b1edbc 13653 #define TSC_CR_START_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13654 #define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13655 #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
AnnaBridge 171:3a7713b1edbc 13656 #define TSC_CR_AM_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13657 #define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13658 #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
AnnaBridge 171:3a7713b1edbc 13659 #define TSC_CR_SYNCPOL_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13660 #define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13661 #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
AnnaBridge 171:3a7713b1edbc 13662 #define TSC_CR_IODEF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13663 #define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13664 #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
AnnaBridge 171:3a7713b1edbc 13665
AnnaBridge 171:3a7713b1edbc 13666 #define TSC_CR_MCV_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13667 #define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
AnnaBridge 171:3a7713b1edbc 13668 #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
AnnaBridge 171:3a7713b1edbc 13669 #define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13670 #define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13671 #define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13672
AnnaBridge 171:3a7713b1edbc 13673 #define TSC_CR_PGPSC_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13674 #define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 13675 #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
AnnaBridge 171:3a7713b1edbc 13676 #define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13677 #define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13678 #define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13679
AnnaBridge 171:3a7713b1edbc 13680 #define TSC_CR_SSPSC_Pos (15U)
AnnaBridge 171:3a7713b1edbc 13681 #define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13682 #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
AnnaBridge 171:3a7713b1edbc 13683 #define TSC_CR_SSE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 13684 #define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 13685 #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
AnnaBridge 171:3a7713b1edbc 13686
AnnaBridge 171:3a7713b1edbc 13687 #define TSC_CR_SSD_Pos (17U)
AnnaBridge 171:3a7713b1edbc 13688 #define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
AnnaBridge 171:3a7713b1edbc 13689 #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
AnnaBridge 171:3a7713b1edbc 13690 #define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 13691 #define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 13692 #define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 13693 #define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 13694 #define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 13695 #define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 13696 #define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 13697
AnnaBridge 171:3a7713b1edbc 13698 #define TSC_CR_CTPL_Pos (24U)
AnnaBridge 171:3a7713b1edbc 13699 #define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 13700 #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
AnnaBridge 171:3a7713b1edbc 13701 #define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 13702 #define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 13703 #define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 13704 #define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 13705
AnnaBridge 171:3a7713b1edbc 13706 #define TSC_CR_CTPH_Pos (28U)
AnnaBridge 171:3a7713b1edbc 13707 #define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
AnnaBridge 171:3a7713b1edbc 13708 #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
AnnaBridge 171:3a7713b1edbc 13709 #define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 13710 #define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 13711 #define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 13712 #define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 13713
AnnaBridge 171:3a7713b1edbc 13714 /******************* Bit definition for TSC_IER register ********************/
AnnaBridge 171:3a7713b1edbc 13715 #define TSC_IER_EOAIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13716 #define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13717 #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
AnnaBridge 171:3a7713b1edbc 13718 #define TSC_IER_MCEIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13719 #define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13720 #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
AnnaBridge 171:3a7713b1edbc 13721
AnnaBridge 171:3a7713b1edbc 13722 /******************* Bit definition for TSC_ICR register ********************/
AnnaBridge 171:3a7713b1edbc 13723 #define TSC_ICR_EOAIC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13724 #define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13725 #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
AnnaBridge 171:3a7713b1edbc 13726 #define TSC_ICR_MCEIC_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13727 #define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13728 #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
AnnaBridge 171:3a7713b1edbc 13729
AnnaBridge 171:3a7713b1edbc 13730 /******************* Bit definition for TSC_ISR register ********************/
AnnaBridge 171:3a7713b1edbc 13731 #define TSC_ISR_EOAF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13732 #define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13733 #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
AnnaBridge 171:3a7713b1edbc 13734 #define TSC_ISR_MCEF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13735 #define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13736 #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
AnnaBridge 171:3a7713b1edbc 13737
AnnaBridge 171:3a7713b1edbc 13738 /******************* Bit definition for TSC_IOHCR register ******************/
AnnaBridge 171:3a7713b1edbc 13739 #define TSC_IOHCR_G1_IO1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13740 #define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13741 #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13742 #define TSC_IOHCR_G1_IO2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13743 #define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13744 #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13745 #define TSC_IOHCR_G1_IO3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13746 #define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13747 #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13748 #define TSC_IOHCR_G1_IO4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13749 #define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13750 #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13751 #define TSC_IOHCR_G2_IO1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13752 #define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13753 #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13754 #define TSC_IOHCR_G2_IO2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13755 #define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13756 #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13757 #define TSC_IOHCR_G2_IO3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13758 #define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13759 #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13760 #define TSC_IOHCR_G2_IO4_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13761 #define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13762 #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13763 #define TSC_IOHCR_G3_IO1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13764 #define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13765 #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13766 #define TSC_IOHCR_G3_IO2_Pos (9U)
AnnaBridge 171:3a7713b1edbc 13767 #define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13768 #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13769 #define TSC_IOHCR_G3_IO3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13770 #define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13771 #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13772 #define TSC_IOHCR_G3_IO4_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13773 #define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13774 #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13775 #define TSC_IOHCR_G4_IO1_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13776 #define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13777 #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13778 #define TSC_IOHCR_G4_IO2_Pos (13U)
AnnaBridge 171:3a7713b1edbc 13779 #define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13780 #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13781 #define TSC_IOHCR_G4_IO3_Pos (14U)
AnnaBridge 171:3a7713b1edbc 13782 #define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13783 #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13784 #define TSC_IOHCR_G4_IO4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 13785 #define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13786 #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13787 #define TSC_IOHCR_G5_IO1_Pos (16U)
AnnaBridge 171:3a7713b1edbc 13788 #define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 13789 #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13790 #define TSC_IOHCR_G5_IO2_Pos (17U)
AnnaBridge 171:3a7713b1edbc 13791 #define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 13792 #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13793 #define TSC_IOHCR_G5_IO3_Pos (18U)
AnnaBridge 171:3a7713b1edbc 13794 #define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 13795 #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13796 #define TSC_IOHCR_G5_IO4_Pos (19U)
AnnaBridge 171:3a7713b1edbc 13797 #define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 13798 #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13799 #define TSC_IOHCR_G6_IO1_Pos (20U)
AnnaBridge 171:3a7713b1edbc 13800 #define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 13801 #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13802 #define TSC_IOHCR_G6_IO2_Pos (21U)
AnnaBridge 171:3a7713b1edbc 13803 #define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 13804 #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13805 #define TSC_IOHCR_G6_IO3_Pos (22U)
AnnaBridge 171:3a7713b1edbc 13806 #define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 13807 #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13808 #define TSC_IOHCR_G6_IO4_Pos (23U)
AnnaBridge 171:3a7713b1edbc 13809 #define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 13810 #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13811 #define TSC_IOHCR_G7_IO1_Pos (24U)
AnnaBridge 171:3a7713b1edbc 13812 #define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 13813 #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13814 #define TSC_IOHCR_G7_IO2_Pos (25U)
AnnaBridge 171:3a7713b1edbc 13815 #define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 13816 #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13817 #define TSC_IOHCR_G7_IO3_Pos (26U)
AnnaBridge 171:3a7713b1edbc 13818 #define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 13819 #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13820 #define TSC_IOHCR_G7_IO4_Pos (27U)
AnnaBridge 171:3a7713b1edbc 13821 #define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 13822 #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13823 #define TSC_IOHCR_G8_IO1_Pos (28U)
AnnaBridge 171:3a7713b1edbc 13824 #define TSC_IOHCR_G8_IO1_Msk (0x1U << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 13825 #define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13826 #define TSC_IOHCR_G8_IO2_Pos (29U)
AnnaBridge 171:3a7713b1edbc 13827 #define TSC_IOHCR_G8_IO2_Msk (0x1U << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 13828 #define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13829 #define TSC_IOHCR_G8_IO3_Pos (30U)
AnnaBridge 171:3a7713b1edbc 13830 #define TSC_IOHCR_G8_IO3_Msk (0x1U << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 13831 #define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13832 #define TSC_IOHCR_G8_IO4_Pos (31U)
AnnaBridge 171:3a7713b1edbc 13833 #define TSC_IOHCR_G8_IO4_Msk (0x1U << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 13834 #define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
AnnaBridge 171:3a7713b1edbc 13835
AnnaBridge 171:3a7713b1edbc 13836 /******************* Bit definition for TSC_IOASCR register *****************/
AnnaBridge 171:3a7713b1edbc 13837 #define TSC_IOASCR_G1_IO1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13838 #define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13839 #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13840 #define TSC_IOASCR_G1_IO2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13841 #define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13842 #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13843 #define TSC_IOASCR_G1_IO3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13844 #define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13845 #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13846 #define TSC_IOASCR_G1_IO4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13847 #define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13848 #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13849 #define TSC_IOASCR_G2_IO1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13850 #define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13851 #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13852 #define TSC_IOASCR_G2_IO2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13853 #define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13854 #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13855 #define TSC_IOASCR_G2_IO3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13856 #define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13857 #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13858 #define TSC_IOASCR_G2_IO4_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13859 #define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13860 #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13861 #define TSC_IOASCR_G3_IO1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13862 #define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13863 #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13864 #define TSC_IOASCR_G3_IO2_Pos (9U)
AnnaBridge 171:3a7713b1edbc 13865 #define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13866 #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13867 #define TSC_IOASCR_G3_IO3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13868 #define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13869 #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13870 #define TSC_IOASCR_G3_IO4_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13871 #define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13872 #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13873 #define TSC_IOASCR_G4_IO1_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13874 #define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13875 #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13876 #define TSC_IOASCR_G4_IO2_Pos (13U)
AnnaBridge 171:3a7713b1edbc 13877 #define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13878 #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13879 #define TSC_IOASCR_G4_IO3_Pos (14U)
AnnaBridge 171:3a7713b1edbc 13880 #define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13881 #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13882 #define TSC_IOASCR_G4_IO4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 13883 #define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13884 #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13885 #define TSC_IOASCR_G5_IO1_Pos (16U)
AnnaBridge 171:3a7713b1edbc 13886 #define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 13887 #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13888 #define TSC_IOASCR_G5_IO2_Pos (17U)
AnnaBridge 171:3a7713b1edbc 13889 #define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 13890 #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13891 #define TSC_IOASCR_G5_IO3_Pos (18U)
AnnaBridge 171:3a7713b1edbc 13892 #define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 13893 #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13894 #define TSC_IOASCR_G5_IO4_Pos (19U)
AnnaBridge 171:3a7713b1edbc 13895 #define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 13896 #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13897 #define TSC_IOASCR_G6_IO1_Pos (20U)
AnnaBridge 171:3a7713b1edbc 13898 #define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 13899 #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13900 #define TSC_IOASCR_G6_IO2_Pos (21U)
AnnaBridge 171:3a7713b1edbc 13901 #define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 13902 #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13903 #define TSC_IOASCR_G6_IO3_Pos (22U)
AnnaBridge 171:3a7713b1edbc 13904 #define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 13905 #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13906 #define TSC_IOASCR_G6_IO4_Pos (23U)
AnnaBridge 171:3a7713b1edbc 13907 #define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 13908 #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13909 #define TSC_IOASCR_G7_IO1_Pos (24U)
AnnaBridge 171:3a7713b1edbc 13910 #define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 13911 #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13912 #define TSC_IOASCR_G7_IO2_Pos (25U)
AnnaBridge 171:3a7713b1edbc 13913 #define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 13914 #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13915 #define TSC_IOASCR_G7_IO3_Pos (26U)
AnnaBridge 171:3a7713b1edbc 13916 #define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 13917 #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13918 #define TSC_IOASCR_G7_IO4_Pos (27U)
AnnaBridge 171:3a7713b1edbc 13919 #define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 13920 #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13921 #define TSC_IOASCR_G8_IO1_Pos (28U)
AnnaBridge 171:3a7713b1edbc 13922 #define TSC_IOASCR_G8_IO1_Msk (0x1U << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 13923 #define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13924 #define TSC_IOASCR_G8_IO2_Pos (29U)
AnnaBridge 171:3a7713b1edbc 13925 #define TSC_IOASCR_G8_IO2_Msk (0x1U << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 13926 #define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13927 #define TSC_IOASCR_G8_IO3_Pos (30U)
AnnaBridge 171:3a7713b1edbc 13928 #define TSC_IOASCR_G8_IO3_Msk (0x1U << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 13929 #define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13930 #define TSC_IOASCR_G8_IO4_Pos (31U)
AnnaBridge 171:3a7713b1edbc 13931 #define TSC_IOASCR_G8_IO4_Msk (0x1U << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 13932 #define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
AnnaBridge 171:3a7713b1edbc 13933
AnnaBridge 171:3a7713b1edbc 13934 /******************* Bit definition for TSC_IOSCR register ******************/
AnnaBridge 171:3a7713b1edbc 13935 #define TSC_IOSCR_G1_IO1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 13936 #define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 13937 #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
AnnaBridge 171:3a7713b1edbc 13938 #define TSC_IOSCR_G1_IO2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 13939 #define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 13940 #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
AnnaBridge 171:3a7713b1edbc 13941 #define TSC_IOSCR_G1_IO3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 13942 #define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 13943 #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
AnnaBridge 171:3a7713b1edbc 13944 #define TSC_IOSCR_G1_IO4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 13945 #define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 13946 #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
AnnaBridge 171:3a7713b1edbc 13947 #define TSC_IOSCR_G2_IO1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 13948 #define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 13949 #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
AnnaBridge 171:3a7713b1edbc 13950 #define TSC_IOSCR_G2_IO2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 13951 #define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 13952 #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
AnnaBridge 171:3a7713b1edbc 13953 #define TSC_IOSCR_G2_IO3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 13954 #define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 13955 #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
AnnaBridge 171:3a7713b1edbc 13956 #define TSC_IOSCR_G2_IO4_Pos (7U)
AnnaBridge 171:3a7713b1edbc 13957 #define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 13958 #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
AnnaBridge 171:3a7713b1edbc 13959 #define TSC_IOSCR_G3_IO1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 13960 #define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 13961 #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
AnnaBridge 171:3a7713b1edbc 13962 #define TSC_IOSCR_G3_IO2_Pos (9U)
AnnaBridge 171:3a7713b1edbc 13963 #define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 13964 #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
AnnaBridge 171:3a7713b1edbc 13965 #define TSC_IOSCR_G3_IO3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 13966 #define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 13967 #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
AnnaBridge 171:3a7713b1edbc 13968 #define TSC_IOSCR_G3_IO4_Pos (11U)
AnnaBridge 171:3a7713b1edbc 13969 #define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 13970 #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
AnnaBridge 171:3a7713b1edbc 13971 #define TSC_IOSCR_G4_IO1_Pos (12U)
AnnaBridge 171:3a7713b1edbc 13972 #define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 13973 #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
AnnaBridge 171:3a7713b1edbc 13974 #define TSC_IOSCR_G4_IO2_Pos (13U)
AnnaBridge 171:3a7713b1edbc 13975 #define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 13976 #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
AnnaBridge 171:3a7713b1edbc 13977 #define TSC_IOSCR_G4_IO3_Pos (14U)
AnnaBridge 171:3a7713b1edbc 13978 #define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 13979 #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
AnnaBridge 171:3a7713b1edbc 13980 #define TSC_IOSCR_G4_IO4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 13981 #define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 13982 #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
AnnaBridge 171:3a7713b1edbc 13983 #define TSC_IOSCR_G5_IO1_Pos (16U)
AnnaBridge 171:3a7713b1edbc 13984 #define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 13985 #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
AnnaBridge 171:3a7713b1edbc 13986 #define TSC_IOSCR_G5_IO2_Pos (17U)
AnnaBridge 171:3a7713b1edbc 13987 #define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 13988 #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
AnnaBridge 171:3a7713b1edbc 13989 #define TSC_IOSCR_G5_IO3_Pos (18U)
AnnaBridge 171:3a7713b1edbc 13990 #define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 13991 #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
AnnaBridge 171:3a7713b1edbc 13992 #define TSC_IOSCR_G5_IO4_Pos (19U)
AnnaBridge 171:3a7713b1edbc 13993 #define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 13994 #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
AnnaBridge 171:3a7713b1edbc 13995 #define TSC_IOSCR_G6_IO1_Pos (20U)
AnnaBridge 171:3a7713b1edbc 13996 #define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 13997 #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
AnnaBridge 171:3a7713b1edbc 13998 #define TSC_IOSCR_G6_IO2_Pos (21U)
AnnaBridge 171:3a7713b1edbc 13999 #define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 14000 #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
AnnaBridge 171:3a7713b1edbc 14001 #define TSC_IOSCR_G6_IO3_Pos (22U)
AnnaBridge 171:3a7713b1edbc 14002 #define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 14003 #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
AnnaBridge 171:3a7713b1edbc 14004 #define TSC_IOSCR_G6_IO4_Pos (23U)
AnnaBridge 171:3a7713b1edbc 14005 #define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 14006 #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
AnnaBridge 171:3a7713b1edbc 14007 #define TSC_IOSCR_G7_IO1_Pos (24U)
AnnaBridge 171:3a7713b1edbc 14008 #define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 14009 #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
AnnaBridge 171:3a7713b1edbc 14010 #define TSC_IOSCR_G7_IO2_Pos (25U)
AnnaBridge 171:3a7713b1edbc 14011 #define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 14012 #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
AnnaBridge 171:3a7713b1edbc 14013 #define TSC_IOSCR_G7_IO3_Pos (26U)
AnnaBridge 171:3a7713b1edbc 14014 #define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 14015 #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
AnnaBridge 171:3a7713b1edbc 14016 #define TSC_IOSCR_G7_IO4_Pos (27U)
AnnaBridge 171:3a7713b1edbc 14017 #define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 14018 #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
AnnaBridge 171:3a7713b1edbc 14019 #define TSC_IOSCR_G8_IO1_Pos (28U)
AnnaBridge 171:3a7713b1edbc 14020 #define TSC_IOSCR_G8_IO1_Msk (0x1U << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 14021 #define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
AnnaBridge 171:3a7713b1edbc 14022 #define TSC_IOSCR_G8_IO2_Pos (29U)
AnnaBridge 171:3a7713b1edbc 14023 #define TSC_IOSCR_G8_IO2_Msk (0x1U << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 14024 #define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
AnnaBridge 171:3a7713b1edbc 14025 #define TSC_IOSCR_G8_IO3_Pos (30U)
AnnaBridge 171:3a7713b1edbc 14026 #define TSC_IOSCR_G8_IO3_Msk (0x1U << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 14027 #define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
AnnaBridge 171:3a7713b1edbc 14028 #define TSC_IOSCR_G8_IO4_Pos (31U)
AnnaBridge 171:3a7713b1edbc 14029 #define TSC_IOSCR_G8_IO4_Msk (0x1U << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 14030 #define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
AnnaBridge 171:3a7713b1edbc 14031
AnnaBridge 171:3a7713b1edbc 14032 /******************* Bit definition for TSC_IOCCR register ******************/
AnnaBridge 171:3a7713b1edbc 14033 #define TSC_IOCCR_G1_IO1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14034 #define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14035 #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
AnnaBridge 171:3a7713b1edbc 14036 #define TSC_IOCCR_G1_IO2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14037 #define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14038 #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
AnnaBridge 171:3a7713b1edbc 14039 #define TSC_IOCCR_G1_IO3_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14040 #define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14041 #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
AnnaBridge 171:3a7713b1edbc 14042 #define TSC_IOCCR_G1_IO4_Pos (3U)
AnnaBridge 171:3a7713b1edbc 14043 #define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14044 #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
AnnaBridge 171:3a7713b1edbc 14045 #define TSC_IOCCR_G2_IO1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14046 #define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14047 #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
AnnaBridge 171:3a7713b1edbc 14048 #define TSC_IOCCR_G2_IO2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 14049 #define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 14050 #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
AnnaBridge 171:3a7713b1edbc 14051 #define TSC_IOCCR_G2_IO3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14052 #define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14053 #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
AnnaBridge 171:3a7713b1edbc 14054 #define TSC_IOCCR_G2_IO4_Pos (7U)
AnnaBridge 171:3a7713b1edbc 14055 #define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 14056 #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
AnnaBridge 171:3a7713b1edbc 14057 #define TSC_IOCCR_G3_IO1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 14058 #define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 14059 #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
AnnaBridge 171:3a7713b1edbc 14060 #define TSC_IOCCR_G3_IO2_Pos (9U)
AnnaBridge 171:3a7713b1edbc 14061 #define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 14062 #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
AnnaBridge 171:3a7713b1edbc 14063 #define TSC_IOCCR_G3_IO3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 14064 #define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 14065 #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
AnnaBridge 171:3a7713b1edbc 14066 #define TSC_IOCCR_G3_IO4_Pos (11U)
AnnaBridge 171:3a7713b1edbc 14067 #define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14068 #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
AnnaBridge 171:3a7713b1edbc 14069 #define TSC_IOCCR_G4_IO1_Pos (12U)
AnnaBridge 171:3a7713b1edbc 14070 #define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 14071 #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
AnnaBridge 171:3a7713b1edbc 14072 #define TSC_IOCCR_G4_IO2_Pos (13U)
AnnaBridge 171:3a7713b1edbc 14073 #define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 14074 #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
AnnaBridge 171:3a7713b1edbc 14075 #define TSC_IOCCR_G4_IO3_Pos (14U)
AnnaBridge 171:3a7713b1edbc 14076 #define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 14077 #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
AnnaBridge 171:3a7713b1edbc 14078 #define TSC_IOCCR_G4_IO4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 14079 #define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 14080 #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
AnnaBridge 171:3a7713b1edbc 14081 #define TSC_IOCCR_G5_IO1_Pos (16U)
AnnaBridge 171:3a7713b1edbc 14082 #define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 14083 #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
AnnaBridge 171:3a7713b1edbc 14084 #define TSC_IOCCR_G5_IO2_Pos (17U)
AnnaBridge 171:3a7713b1edbc 14085 #define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 14086 #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
AnnaBridge 171:3a7713b1edbc 14087 #define TSC_IOCCR_G5_IO3_Pos (18U)
AnnaBridge 171:3a7713b1edbc 14088 #define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 14089 #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
AnnaBridge 171:3a7713b1edbc 14090 #define TSC_IOCCR_G5_IO4_Pos (19U)
AnnaBridge 171:3a7713b1edbc 14091 #define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 14092 #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
AnnaBridge 171:3a7713b1edbc 14093 #define TSC_IOCCR_G6_IO1_Pos (20U)
AnnaBridge 171:3a7713b1edbc 14094 #define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 14095 #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
AnnaBridge 171:3a7713b1edbc 14096 #define TSC_IOCCR_G6_IO2_Pos (21U)
AnnaBridge 171:3a7713b1edbc 14097 #define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 14098 #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
AnnaBridge 171:3a7713b1edbc 14099 #define TSC_IOCCR_G6_IO3_Pos (22U)
AnnaBridge 171:3a7713b1edbc 14100 #define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 14101 #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
AnnaBridge 171:3a7713b1edbc 14102 #define TSC_IOCCR_G6_IO4_Pos (23U)
AnnaBridge 171:3a7713b1edbc 14103 #define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 14104 #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
AnnaBridge 171:3a7713b1edbc 14105 #define TSC_IOCCR_G7_IO1_Pos (24U)
AnnaBridge 171:3a7713b1edbc 14106 #define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 14107 #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
AnnaBridge 171:3a7713b1edbc 14108 #define TSC_IOCCR_G7_IO2_Pos (25U)
AnnaBridge 171:3a7713b1edbc 14109 #define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 14110 #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
AnnaBridge 171:3a7713b1edbc 14111 #define TSC_IOCCR_G7_IO3_Pos (26U)
AnnaBridge 171:3a7713b1edbc 14112 #define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 14113 #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
AnnaBridge 171:3a7713b1edbc 14114 #define TSC_IOCCR_G7_IO4_Pos (27U)
AnnaBridge 171:3a7713b1edbc 14115 #define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 14116 #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
AnnaBridge 171:3a7713b1edbc 14117 #define TSC_IOCCR_G8_IO1_Pos (28U)
AnnaBridge 171:3a7713b1edbc 14118 #define TSC_IOCCR_G8_IO1_Msk (0x1U << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 14119 #define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
AnnaBridge 171:3a7713b1edbc 14120 #define TSC_IOCCR_G8_IO2_Pos (29U)
AnnaBridge 171:3a7713b1edbc 14121 #define TSC_IOCCR_G8_IO2_Msk (0x1U << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 14122 #define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
AnnaBridge 171:3a7713b1edbc 14123 #define TSC_IOCCR_G8_IO3_Pos (30U)
AnnaBridge 171:3a7713b1edbc 14124 #define TSC_IOCCR_G8_IO3_Msk (0x1U << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 14125 #define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
AnnaBridge 171:3a7713b1edbc 14126 #define TSC_IOCCR_G8_IO4_Pos (31U)
AnnaBridge 171:3a7713b1edbc 14127 #define TSC_IOCCR_G8_IO4_Msk (0x1U << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 14128 #define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
AnnaBridge 171:3a7713b1edbc 14129
AnnaBridge 171:3a7713b1edbc 14130 /******************* Bit definition for TSC_IOGCSR register *****************/
AnnaBridge 171:3a7713b1edbc 14131 #define TSC_IOGCSR_G1E_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14132 #define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14133 #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
AnnaBridge 171:3a7713b1edbc 14134 #define TSC_IOGCSR_G2E_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14135 #define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14136 #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
AnnaBridge 171:3a7713b1edbc 14137 #define TSC_IOGCSR_G3E_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14138 #define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14139 #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
AnnaBridge 171:3a7713b1edbc 14140 #define TSC_IOGCSR_G4E_Pos (3U)
AnnaBridge 171:3a7713b1edbc 14141 #define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14142 #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
AnnaBridge 171:3a7713b1edbc 14143 #define TSC_IOGCSR_G5E_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14144 #define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14145 #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
AnnaBridge 171:3a7713b1edbc 14146 #define TSC_IOGCSR_G6E_Pos (5U)
AnnaBridge 171:3a7713b1edbc 14147 #define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 14148 #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
AnnaBridge 171:3a7713b1edbc 14149 #define TSC_IOGCSR_G7E_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14150 #define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14151 #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
AnnaBridge 171:3a7713b1edbc 14152 #define TSC_IOGCSR_G8E_Pos (7U)
AnnaBridge 171:3a7713b1edbc 14153 #define TSC_IOGCSR_G8E_Msk (0x1U << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 14154 #define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
AnnaBridge 171:3a7713b1edbc 14155 #define TSC_IOGCSR_G1S_Pos (16U)
AnnaBridge 171:3a7713b1edbc 14156 #define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 14157 #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
AnnaBridge 171:3a7713b1edbc 14158 #define TSC_IOGCSR_G2S_Pos (17U)
AnnaBridge 171:3a7713b1edbc 14159 #define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 14160 #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
AnnaBridge 171:3a7713b1edbc 14161 #define TSC_IOGCSR_G3S_Pos (18U)
AnnaBridge 171:3a7713b1edbc 14162 #define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 14163 #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
AnnaBridge 171:3a7713b1edbc 14164 #define TSC_IOGCSR_G4S_Pos (19U)
AnnaBridge 171:3a7713b1edbc 14165 #define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 14166 #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
AnnaBridge 171:3a7713b1edbc 14167 #define TSC_IOGCSR_G5S_Pos (20U)
AnnaBridge 171:3a7713b1edbc 14168 #define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 14169 #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
AnnaBridge 171:3a7713b1edbc 14170 #define TSC_IOGCSR_G6S_Pos (21U)
AnnaBridge 171:3a7713b1edbc 14171 #define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 14172 #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
AnnaBridge 171:3a7713b1edbc 14173 #define TSC_IOGCSR_G7S_Pos (22U)
AnnaBridge 171:3a7713b1edbc 14174 #define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 14175 #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
AnnaBridge 171:3a7713b1edbc 14176 #define TSC_IOGCSR_G8S_Pos (23U)
AnnaBridge 171:3a7713b1edbc 14177 #define TSC_IOGCSR_G8S_Msk (0x1U << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 14178 #define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
AnnaBridge 171:3a7713b1edbc 14179
AnnaBridge 171:3a7713b1edbc 14180 /******************* Bit definition for TSC_IOGXCR register *****************/
AnnaBridge 171:3a7713b1edbc 14181 #define TSC_IOGXCR_CNT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14182 #define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
AnnaBridge 171:3a7713b1edbc 14183 #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
AnnaBridge 171:3a7713b1edbc 14184
AnnaBridge 171:3a7713b1edbc 14185 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 14186 /* */
AnnaBridge 171:3a7713b1edbc 14187 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
AnnaBridge 171:3a7713b1edbc 14188 /* */
AnnaBridge 171:3a7713b1edbc 14189 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 14190
AnnaBridge 171:3a7713b1edbc 14191 /*
AnnaBridge 171:3a7713b1edbc 14192 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
AnnaBridge 171:3a7713b1edbc 14193 */
AnnaBridge 171:3a7713b1edbc 14194
AnnaBridge 171:3a7713b1edbc 14195 /* Support of 7 bits data length feature */
AnnaBridge 171:3a7713b1edbc 14196 #define USART_7BITS_SUPPORT
AnnaBridge 171:3a7713b1edbc 14197
AnnaBridge 171:3a7713b1edbc 14198 /****************** Bit definition for USART_CR1 register *******************/
AnnaBridge 171:3a7713b1edbc 14199 #define USART_CR1_UE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14200 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14201 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
AnnaBridge 171:3a7713b1edbc 14202 #define USART_CR1_UESM_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14203 #define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14204 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
AnnaBridge 171:3a7713b1edbc 14205 #define USART_CR1_RE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14206 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14207 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
AnnaBridge 171:3a7713b1edbc 14208 #define USART_CR1_TE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 14209 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14210 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
AnnaBridge 171:3a7713b1edbc 14211 #define USART_CR1_IDLEIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14212 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14213 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14214 #define USART_CR1_RXNEIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 14215 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 14216 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14217 #define USART_CR1_TCIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14218 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14219 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14220 #define USART_CR1_TXEIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 14221 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 14222 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14223 #define USART_CR1_PEIE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 14224 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 14225 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14226 #define USART_CR1_PS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 14227 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 14228 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
AnnaBridge 171:3a7713b1edbc 14229 #define USART_CR1_PCE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 14230 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 14231 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
AnnaBridge 171:3a7713b1edbc 14232 #define USART_CR1_WAKE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 14233 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14234 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
AnnaBridge 171:3a7713b1edbc 14235 #define USART_CR1_M0_Pos (12U)
AnnaBridge 171:3a7713b1edbc 14236 #define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 14237 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length bit 0 */
AnnaBridge 171:3a7713b1edbc 14238 #define USART_CR1_MME_Pos (13U)
AnnaBridge 171:3a7713b1edbc 14239 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 14240 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
AnnaBridge 171:3a7713b1edbc 14241 #define USART_CR1_CMIE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 14242 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 14243 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
AnnaBridge 171:3a7713b1edbc 14244 #define USART_CR1_OVER8_Pos (15U)
AnnaBridge 171:3a7713b1edbc 14245 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 14246 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
AnnaBridge 171:3a7713b1edbc 14247 #define USART_CR1_DEDT_Pos (16U)
AnnaBridge 171:3a7713b1edbc 14248 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
AnnaBridge 171:3a7713b1edbc 14249 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
AnnaBridge 171:3a7713b1edbc 14250 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 14251 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 14252 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 14253 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 14254 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 14255 #define USART_CR1_DEAT_Pos (21U)
AnnaBridge 171:3a7713b1edbc 14256 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
AnnaBridge 171:3a7713b1edbc 14257 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
AnnaBridge 171:3a7713b1edbc 14258 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 14259 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 14260 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 14261 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 14262 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 14263 #define USART_CR1_RTOIE_Pos (26U)
AnnaBridge 171:3a7713b1edbc 14264 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 14265 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
AnnaBridge 171:3a7713b1edbc 14266 #define USART_CR1_EOBIE_Pos (27U)
AnnaBridge 171:3a7713b1edbc 14267 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 14268 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
AnnaBridge 171:3a7713b1edbc 14269 #define USART_CR1_M1_Pos (28U)
AnnaBridge 171:3a7713b1edbc 14270 #define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 14271 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length bit 1 */
AnnaBridge 171:3a7713b1edbc 14272 #define USART_CR1_M_Pos (12U)
AnnaBridge 171:3a7713b1edbc 14273 #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
AnnaBridge 171:3a7713b1edbc 14274 #define USART_CR1_M USART_CR1_M_Msk /*!< [M1:M0] Word length */
AnnaBridge 171:3a7713b1edbc 14275
AnnaBridge 171:3a7713b1edbc 14276 /****************** Bit definition for USART_CR2 register *******************/
AnnaBridge 171:3a7713b1edbc 14277 #define USART_CR2_ADDM7_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14278 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14279 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
AnnaBridge 171:3a7713b1edbc 14280 #define USART_CR2_LBDL_Pos (5U)
AnnaBridge 171:3a7713b1edbc 14281 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 14282 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
AnnaBridge 171:3a7713b1edbc 14283 #define USART_CR2_LBDIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14284 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14285 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14286 #define USART_CR2_LBCL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 14287 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 14288 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
AnnaBridge 171:3a7713b1edbc 14289 #define USART_CR2_CPHA_Pos (9U)
AnnaBridge 171:3a7713b1edbc 14290 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 14291 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
AnnaBridge 171:3a7713b1edbc 14292 #define USART_CR2_CPOL_Pos (10U)
AnnaBridge 171:3a7713b1edbc 14293 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 14294 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
AnnaBridge 171:3a7713b1edbc 14295 #define USART_CR2_CLKEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 14296 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14297 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
AnnaBridge 171:3a7713b1edbc 14298 #define USART_CR2_STOP_Pos (12U)
AnnaBridge 171:3a7713b1edbc 14299 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 14300 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
AnnaBridge 171:3a7713b1edbc 14301 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 14302 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 14303 #define USART_CR2_LINEN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 14304 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 14305 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
AnnaBridge 171:3a7713b1edbc 14306 #define USART_CR2_SWAP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 14307 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 14308 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
AnnaBridge 171:3a7713b1edbc 14309 #define USART_CR2_RXINV_Pos (16U)
AnnaBridge 171:3a7713b1edbc 14310 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 14311 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
AnnaBridge 171:3a7713b1edbc 14312 #define USART_CR2_TXINV_Pos (17U)
AnnaBridge 171:3a7713b1edbc 14313 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 14314 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
AnnaBridge 171:3a7713b1edbc 14315 #define USART_CR2_DATAINV_Pos (18U)
AnnaBridge 171:3a7713b1edbc 14316 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 14317 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
AnnaBridge 171:3a7713b1edbc 14318 #define USART_CR2_MSBFIRST_Pos (19U)
AnnaBridge 171:3a7713b1edbc 14319 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 14320 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
AnnaBridge 171:3a7713b1edbc 14321 #define USART_CR2_ABREN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 14322 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 14323 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
AnnaBridge 171:3a7713b1edbc 14324 #define USART_CR2_ABRMODE_Pos (21U)
AnnaBridge 171:3a7713b1edbc 14325 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
AnnaBridge 171:3a7713b1edbc 14326 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
AnnaBridge 171:3a7713b1edbc 14327 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 14328 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 14329 #define USART_CR2_RTOEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 14330 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 14331 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
AnnaBridge 171:3a7713b1edbc 14332 #define USART_CR2_ADD_Pos (24U)
AnnaBridge 171:3a7713b1edbc 14333 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 14334 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
AnnaBridge 171:3a7713b1edbc 14335
AnnaBridge 171:3a7713b1edbc 14336 /****************** Bit definition for USART_CR3 register *******************/
AnnaBridge 171:3a7713b1edbc 14337 #define USART_CR3_EIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14338 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14339 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14340 #define USART_CR3_IREN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14341 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14342 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
AnnaBridge 171:3a7713b1edbc 14343 #define USART_CR3_IRLP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14344 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14345 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
AnnaBridge 171:3a7713b1edbc 14346 #define USART_CR3_HDSEL_Pos (3U)
AnnaBridge 171:3a7713b1edbc 14347 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14348 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
AnnaBridge 171:3a7713b1edbc 14349 #define USART_CR3_NACK_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14350 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14351 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
AnnaBridge 171:3a7713b1edbc 14352 #define USART_CR3_SCEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 14353 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 14354 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
AnnaBridge 171:3a7713b1edbc 14355 #define USART_CR3_DMAR_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14356 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14357 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
AnnaBridge 171:3a7713b1edbc 14358 #define USART_CR3_DMAT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 14359 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 14360 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
AnnaBridge 171:3a7713b1edbc 14361 #define USART_CR3_RTSE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 14362 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 14363 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
AnnaBridge 171:3a7713b1edbc 14364 #define USART_CR3_CTSE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 14365 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 14366 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
AnnaBridge 171:3a7713b1edbc 14367 #define USART_CR3_CTSIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 14368 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 14369 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14370 #define USART_CR3_ONEBIT_Pos (11U)
AnnaBridge 171:3a7713b1edbc 14371 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14372 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
AnnaBridge 171:3a7713b1edbc 14373 #define USART_CR3_OVRDIS_Pos (12U)
AnnaBridge 171:3a7713b1edbc 14374 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 14375 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
AnnaBridge 171:3a7713b1edbc 14376 #define USART_CR3_DDRE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 14377 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 14378 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
AnnaBridge 171:3a7713b1edbc 14379 #define USART_CR3_DEM_Pos (14U)
AnnaBridge 171:3a7713b1edbc 14380 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 14381 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
AnnaBridge 171:3a7713b1edbc 14382 #define USART_CR3_DEP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 14383 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 14384 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
AnnaBridge 171:3a7713b1edbc 14385 #define USART_CR3_SCARCNT_Pos (17U)
AnnaBridge 171:3a7713b1edbc 14386 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
AnnaBridge 171:3a7713b1edbc 14387 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
AnnaBridge 171:3a7713b1edbc 14388 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 14389 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 14390 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 14391 #define USART_CR3_WUS_Pos (20U)
AnnaBridge 171:3a7713b1edbc 14392 #define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 14393 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
AnnaBridge 171:3a7713b1edbc 14394 #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 14395 #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 14396 #define USART_CR3_WUFIE_Pos (22U)
AnnaBridge 171:3a7713b1edbc 14397 #define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 14398 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 14399
AnnaBridge 171:3a7713b1edbc 14400 /****************** Bit definition for USART_BRR register *******************/
AnnaBridge 171:3a7713b1edbc 14401 #define USART_BRR_DIV_FRACTION_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14402 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 14403 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
AnnaBridge 171:3a7713b1edbc 14404 #define USART_BRR_DIV_MANTISSA_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14405 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
AnnaBridge 171:3a7713b1edbc 14406 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
AnnaBridge 171:3a7713b1edbc 14407
AnnaBridge 171:3a7713b1edbc 14408 /****************** Bit definition for USART_GTPR register ******************/
AnnaBridge 171:3a7713b1edbc 14409 #define USART_GTPR_PSC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14410 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 14411 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
AnnaBridge 171:3a7713b1edbc 14412 #define USART_GTPR_GT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 14413 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 14414 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
AnnaBridge 171:3a7713b1edbc 14415
AnnaBridge 171:3a7713b1edbc 14416
AnnaBridge 171:3a7713b1edbc 14417 /******************* Bit definition for USART_RTOR register *****************/
AnnaBridge 171:3a7713b1edbc 14418 #define USART_RTOR_RTO_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14419 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
AnnaBridge 171:3a7713b1edbc 14420 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
AnnaBridge 171:3a7713b1edbc 14421 #define USART_RTOR_BLEN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 14422 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 14423 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
AnnaBridge 171:3a7713b1edbc 14424
AnnaBridge 171:3a7713b1edbc 14425 /******************* Bit definition for USART_RQR register ******************/
AnnaBridge 171:3a7713b1edbc 14426 #define USART_RQR_ABRRQ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14427 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14428 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
AnnaBridge 171:3a7713b1edbc 14429 #define USART_RQR_SBKRQ_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14430 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14431 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
AnnaBridge 171:3a7713b1edbc 14432 #define USART_RQR_MMRQ_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14433 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14434 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
AnnaBridge 171:3a7713b1edbc 14435 #define USART_RQR_RXFRQ_Pos (3U)
AnnaBridge 171:3a7713b1edbc 14436 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14437 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
AnnaBridge 171:3a7713b1edbc 14438 #define USART_RQR_TXFRQ_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14439 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14440 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
AnnaBridge 171:3a7713b1edbc 14441
AnnaBridge 171:3a7713b1edbc 14442 /******************* Bit definition for USART_ISR register ******************/
AnnaBridge 171:3a7713b1edbc 14443 #define USART_ISR_PE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14444 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14445 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
AnnaBridge 171:3a7713b1edbc 14446 #define USART_ISR_FE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14447 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14448 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
AnnaBridge 171:3a7713b1edbc 14449 #define USART_ISR_NE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14450 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14451 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
AnnaBridge 171:3a7713b1edbc 14452 #define USART_ISR_ORE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 14453 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14454 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
AnnaBridge 171:3a7713b1edbc 14455 #define USART_ISR_IDLE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14456 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14457 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
AnnaBridge 171:3a7713b1edbc 14458 #define USART_ISR_RXNE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 14459 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 14460 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
AnnaBridge 171:3a7713b1edbc 14461 #define USART_ISR_TC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14462 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14463 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
AnnaBridge 171:3a7713b1edbc 14464 #define USART_ISR_TXE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 14465 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 14466 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
AnnaBridge 171:3a7713b1edbc 14467 #define USART_ISR_LBDF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 14468 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 14469 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
AnnaBridge 171:3a7713b1edbc 14470 #define USART_ISR_CTSIF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 14471 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 14472 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
AnnaBridge 171:3a7713b1edbc 14473 #define USART_ISR_CTS_Pos (10U)
AnnaBridge 171:3a7713b1edbc 14474 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 14475 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
AnnaBridge 171:3a7713b1edbc 14476 #define USART_ISR_RTOF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 14477 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14478 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
AnnaBridge 171:3a7713b1edbc 14479 #define USART_ISR_EOBF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 14480 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 14481 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
AnnaBridge 171:3a7713b1edbc 14482 #define USART_ISR_ABRE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 14483 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 14484 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
AnnaBridge 171:3a7713b1edbc 14485 #define USART_ISR_ABRF_Pos (15U)
AnnaBridge 171:3a7713b1edbc 14486 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 14487 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
AnnaBridge 171:3a7713b1edbc 14488 #define USART_ISR_BUSY_Pos (16U)
AnnaBridge 171:3a7713b1edbc 14489 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 14490 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
AnnaBridge 171:3a7713b1edbc 14491 #define USART_ISR_CMF_Pos (17U)
AnnaBridge 171:3a7713b1edbc 14492 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 14493 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
AnnaBridge 171:3a7713b1edbc 14494 #define USART_ISR_SBKF_Pos (18U)
AnnaBridge 171:3a7713b1edbc 14495 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 14496 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
AnnaBridge 171:3a7713b1edbc 14497 #define USART_ISR_RWU_Pos (19U)
AnnaBridge 171:3a7713b1edbc 14498 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 14499 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
AnnaBridge 171:3a7713b1edbc 14500 #define USART_ISR_WUF_Pos (20U)
AnnaBridge 171:3a7713b1edbc 14501 #define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 14502 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
AnnaBridge 171:3a7713b1edbc 14503 #define USART_ISR_TEACK_Pos (21U)
AnnaBridge 171:3a7713b1edbc 14504 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 14505 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
AnnaBridge 171:3a7713b1edbc 14506 #define USART_ISR_REACK_Pos (22U)
AnnaBridge 171:3a7713b1edbc 14507 #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 14508 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
AnnaBridge 171:3a7713b1edbc 14509
AnnaBridge 171:3a7713b1edbc 14510 /******************* Bit definition for USART_ICR register ******************/
AnnaBridge 171:3a7713b1edbc 14511 #define USART_ICR_PECF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14512 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14513 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
AnnaBridge 171:3a7713b1edbc 14514 #define USART_ICR_FECF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 14515 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14516 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
AnnaBridge 171:3a7713b1edbc 14517 #define USART_ICR_NCF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 14518 #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14519 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
AnnaBridge 171:3a7713b1edbc 14520 #define USART_ICR_ORECF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 14521 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14522 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
AnnaBridge 171:3a7713b1edbc 14523 #define USART_ICR_IDLECF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 14524 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14525 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
AnnaBridge 171:3a7713b1edbc 14526 #define USART_ICR_TCCF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 14527 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14528 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
AnnaBridge 171:3a7713b1edbc 14529 #define USART_ICR_LBDCF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 14530 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 14531 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
AnnaBridge 171:3a7713b1edbc 14532 #define USART_ICR_CTSCF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 14533 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 14534 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
AnnaBridge 171:3a7713b1edbc 14535 #define USART_ICR_RTOCF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 14536 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 14537 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
AnnaBridge 171:3a7713b1edbc 14538 #define USART_ICR_EOBCF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 14539 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 14540 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
AnnaBridge 171:3a7713b1edbc 14541 #define USART_ICR_CMCF_Pos (17U)
AnnaBridge 171:3a7713b1edbc 14542 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 14543 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
AnnaBridge 171:3a7713b1edbc 14544 #define USART_ICR_WUCF_Pos (20U)
AnnaBridge 171:3a7713b1edbc 14545 #define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 14546 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
AnnaBridge 171:3a7713b1edbc 14547
AnnaBridge 171:3a7713b1edbc 14548 /******************* Bit definition for USART_RDR register ******************/
AnnaBridge 171:3a7713b1edbc 14549 #define USART_RDR_RDR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14550 #define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
AnnaBridge 171:3a7713b1edbc 14551 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
AnnaBridge 171:3a7713b1edbc 14552
AnnaBridge 171:3a7713b1edbc 14553 /******************* Bit definition for USART_TDR register ******************/
AnnaBridge 171:3a7713b1edbc 14554 #define USART_TDR_TDR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14555 #define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
AnnaBridge 171:3a7713b1edbc 14556 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
AnnaBridge 171:3a7713b1edbc 14557
AnnaBridge 171:3a7713b1edbc 14558 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 14559 /* */
AnnaBridge 171:3a7713b1edbc 14560 /* Window WATCHDOG */
AnnaBridge 171:3a7713b1edbc 14561 /* */
AnnaBridge 171:3a7713b1edbc 14562 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 14563 /******************* Bit definition for WWDG_CR register ********************/
AnnaBridge 171:3a7713b1edbc 14564 #define WWDG_CR_T_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14565 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
AnnaBridge 171:3a7713b1edbc 14566 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
AnnaBridge 171:3a7713b1edbc 14567 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14568 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14569 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14570 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14571 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14572 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 14573 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14574
AnnaBridge 171:3a7713b1edbc 14575 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 14576 #define WWDG_CR_T0 WWDG_CR_T_0
AnnaBridge 171:3a7713b1edbc 14577 #define WWDG_CR_T1 WWDG_CR_T_1
AnnaBridge 171:3a7713b1edbc 14578 #define WWDG_CR_T2 WWDG_CR_T_2
AnnaBridge 171:3a7713b1edbc 14579 #define WWDG_CR_T3 WWDG_CR_T_3
AnnaBridge 171:3a7713b1edbc 14580 #define WWDG_CR_T4 WWDG_CR_T_4
AnnaBridge 171:3a7713b1edbc 14581 #define WWDG_CR_T5 WWDG_CR_T_5
AnnaBridge 171:3a7713b1edbc 14582 #define WWDG_CR_T6 WWDG_CR_T_6
AnnaBridge 171:3a7713b1edbc 14583
AnnaBridge 171:3a7713b1edbc 14584 #define WWDG_CR_WDGA_Pos (7U)
AnnaBridge 171:3a7713b1edbc 14585 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 14586 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
AnnaBridge 171:3a7713b1edbc 14587
AnnaBridge 171:3a7713b1edbc 14588 /******************* Bit definition for WWDG_CFR register *******************/
AnnaBridge 171:3a7713b1edbc 14589 #define WWDG_CFR_W_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14590 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
AnnaBridge 171:3a7713b1edbc 14591 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
AnnaBridge 171:3a7713b1edbc 14592 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14593 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 14594 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 14595 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 14596 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 14597 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 14598 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 14599
AnnaBridge 171:3a7713b1edbc 14600 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 14601 #define WWDG_CFR_W0 WWDG_CFR_W_0
AnnaBridge 171:3a7713b1edbc 14602 #define WWDG_CFR_W1 WWDG_CFR_W_1
AnnaBridge 171:3a7713b1edbc 14603 #define WWDG_CFR_W2 WWDG_CFR_W_2
AnnaBridge 171:3a7713b1edbc 14604 #define WWDG_CFR_W3 WWDG_CFR_W_3
AnnaBridge 171:3a7713b1edbc 14605 #define WWDG_CFR_W4 WWDG_CFR_W_4
AnnaBridge 171:3a7713b1edbc 14606 #define WWDG_CFR_W5 WWDG_CFR_W_5
AnnaBridge 171:3a7713b1edbc 14607 #define WWDG_CFR_W6 WWDG_CFR_W_6
AnnaBridge 171:3a7713b1edbc 14608
AnnaBridge 171:3a7713b1edbc 14609 #define WWDG_CFR_WDGTB_Pos (7U)
AnnaBridge 171:3a7713b1edbc 14610 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
AnnaBridge 171:3a7713b1edbc 14611 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
AnnaBridge 171:3a7713b1edbc 14612 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 14613 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 14614
AnnaBridge 171:3a7713b1edbc 14615 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 14616 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
AnnaBridge 171:3a7713b1edbc 14617 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
AnnaBridge 171:3a7713b1edbc 14618
AnnaBridge 171:3a7713b1edbc 14619 #define WWDG_CFR_EWI_Pos (9U)
AnnaBridge 171:3a7713b1edbc 14620 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 14621 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
AnnaBridge 171:3a7713b1edbc 14622
AnnaBridge 171:3a7713b1edbc 14623 /******************* Bit definition for WWDG_SR register ********************/
AnnaBridge 171:3a7713b1edbc 14624 #define WWDG_SR_EWIF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 14625 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 14626 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 14627
AnnaBridge 171:3a7713b1edbc 14628 /**
AnnaBridge 171:3a7713b1edbc 14629 * @}
AnnaBridge 171:3a7713b1edbc 14630 */
AnnaBridge 171:3a7713b1edbc 14631
AnnaBridge 171:3a7713b1edbc 14632 /**
AnnaBridge 171:3a7713b1edbc 14633 * @}
AnnaBridge 171:3a7713b1edbc 14634 */
AnnaBridge 171:3a7713b1edbc 14635
AnnaBridge 171:3a7713b1edbc 14636 /** @addtogroup Exported_macros
AnnaBridge 171:3a7713b1edbc 14637 * @{
AnnaBridge 171:3a7713b1edbc 14638 */
AnnaBridge 171:3a7713b1edbc 14639
AnnaBridge 171:3a7713b1edbc 14640 /****************************** ADC Instances *********************************/
AnnaBridge 171:3a7713b1edbc 14641 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
AnnaBridge 171:3a7713b1edbc 14642 ((INSTANCE) == ADC2))
AnnaBridge 171:3a7713b1edbc 14643
AnnaBridge 171:3a7713b1edbc 14644 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
AnnaBridge 171:3a7713b1edbc 14645
AnnaBridge 171:3a7713b1edbc 14646 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
AnnaBridge 171:3a7713b1edbc 14647 /****************************** CAN Instances *********************************/
AnnaBridge 171:3a7713b1edbc 14648 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
AnnaBridge 171:3a7713b1edbc 14649
AnnaBridge 171:3a7713b1edbc 14650 /****************************** COMP Instances ********************************/
AnnaBridge 171:3a7713b1edbc 14651 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \
AnnaBridge 171:3a7713b1edbc 14652 ((INSTANCE) == COMP4) || \
AnnaBridge 171:3a7713b1edbc 14653 ((INSTANCE) == COMP6))
AnnaBridge 171:3a7713b1edbc 14654
AnnaBridge 171:3a7713b1edbc 14655 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) (0U)
AnnaBridge 171:3a7713b1edbc 14656
AnnaBridge 171:3a7713b1edbc 14657 /******************** COMP Instances with switch on DAC1 Channel1 output ******/
AnnaBridge 171:3a7713b1edbc 14658 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) (0U)
AnnaBridge 171:3a7713b1edbc 14659
AnnaBridge 171:3a7713b1edbc 14660 /******************** COMP Instances with window mode capability **************/
AnnaBridge 171:3a7713b1edbc 14661 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (0U)
AnnaBridge 171:3a7713b1edbc 14662
AnnaBridge 171:3a7713b1edbc 14663 /****************************** CRC Instances *********************************/
AnnaBridge 171:3a7713b1edbc 14664 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
AnnaBridge 171:3a7713b1edbc 14665
AnnaBridge 171:3a7713b1edbc 14666 /****************************** DAC Instances *********************************/
AnnaBridge 171:3a7713b1edbc 14667 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
AnnaBridge 171:3a7713b1edbc 14668 ((INSTANCE) == DAC2))
AnnaBridge 171:3a7713b1edbc 14669
AnnaBridge 171:3a7713b1edbc 14670 #define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
AnnaBridge 171:3a7713b1edbc 14671 ((((INSTANCE) == DAC1) && \
AnnaBridge 171:3a7713b1edbc 14672 (((CHANNEL) == DAC_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 14673 ((CHANNEL) == DAC_CHANNEL_2))) \
AnnaBridge 171:3a7713b1edbc 14674 || \
AnnaBridge 171:3a7713b1edbc 14675 (((INSTANCE) == DAC2) && \
AnnaBridge 171:3a7713b1edbc 14676 (((CHANNEL) == DAC_CHANNEL_1))))
AnnaBridge 171:3a7713b1edbc 14677
AnnaBridge 171:3a7713b1edbc 14678 /****************************** DMA Instances *********************************/
AnnaBridge 171:3a7713b1edbc 14679 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
AnnaBridge 171:3a7713b1edbc 14680 ((INSTANCE) == DMA1_Channel2) || \
AnnaBridge 171:3a7713b1edbc 14681 ((INSTANCE) == DMA1_Channel3) || \
AnnaBridge 171:3a7713b1edbc 14682 ((INSTANCE) == DMA1_Channel4) || \
AnnaBridge 171:3a7713b1edbc 14683 ((INSTANCE) == DMA1_Channel5) || \
AnnaBridge 171:3a7713b1edbc 14684 ((INSTANCE) == DMA1_Channel6) || \
AnnaBridge 171:3a7713b1edbc 14685 ((INSTANCE) == DMA1_Channel7))
AnnaBridge 171:3a7713b1edbc 14686
AnnaBridge 171:3a7713b1edbc 14687 /****************************** GPIO Instances ********************************/
AnnaBridge 171:3a7713b1edbc 14688 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
AnnaBridge 171:3a7713b1edbc 14689 ((INSTANCE) == GPIOB) || \
AnnaBridge 171:3a7713b1edbc 14690 ((INSTANCE) == GPIOC) || \
AnnaBridge 171:3a7713b1edbc 14691 ((INSTANCE) == GPIOD) || \
AnnaBridge 171:3a7713b1edbc 14692 ((INSTANCE) == GPIOF))
AnnaBridge 171:3a7713b1edbc 14693
AnnaBridge 171:3a7713b1edbc 14694 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
AnnaBridge 171:3a7713b1edbc 14695 ((INSTANCE) == GPIOB) || \
AnnaBridge 171:3a7713b1edbc 14696 ((INSTANCE) == GPIOC) || \
AnnaBridge 171:3a7713b1edbc 14697 ((INSTANCE) == GPIOD) || \
AnnaBridge 171:3a7713b1edbc 14698 ((INSTANCE) == GPIOF))
AnnaBridge 171:3a7713b1edbc 14699
AnnaBridge 171:3a7713b1edbc 14700 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
AnnaBridge 171:3a7713b1edbc 14701 ((INSTANCE) == GPIOB) || \
AnnaBridge 171:3a7713b1edbc 14702 ((INSTANCE) == GPIOC) || \
AnnaBridge 171:3a7713b1edbc 14703 ((INSTANCE) == GPIOD) || \
AnnaBridge 171:3a7713b1edbc 14704 ((INSTANCE) == GPIOF))
AnnaBridge 171:3a7713b1edbc 14705
AnnaBridge 171:3a7713b1edbc 14706 /****************************** HRTIM Instances *********************************/
AnnaBridge 171:3a7713b1edbc 14707 #define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
AnnaBridge 171:3a7713b1edbc 14708
AnnaBridge 171:3a7713b1edbc 14709 /****************************** I2C Instances *********************************/
AnnaBridge 171:3a7713b1edbc 14710 #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
AnnaBridge 171:3a7713b1edbc 14711
AnnaBridge 171:3a7713b1edbc 14712 /****************** I2C Instances : wakeup capability from stop modes *********/
AnnaBridge 171:3a7713b1edbc 14713 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
AnnaBridge 171:3a7713b1edbc 14714
AnnaBridge 171:3a7713b1edbc 14715
AnnaBridge 171:3a7713b1edbc 14716 /****************************** OPAMP Instances *******************************/
AnnaBridge 171:3a7713b1edbc 14717 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2)
AnnaBridge 171:3a7713b1edbc 14718
AnnaBridge 171:3a7713b1edbc 14719 /****************************** IWDG Instances ********************************/
AnnaBridge 171:3a7713b1edbc 14720 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
AnnaBridge 171:3a7713b1edbc 14721
AnnaBridge 171:3a7713b1edbc 14722 /****************************** RTC Instances *********************************/
AnnaBridge 171:3a7713b1edbc 14723 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
AnnaBridge 171:3a7713b1edbc 14724
AnnaBridge 171:3a7713b1edbc 14725 /****************************** SMBUS Instances *******************************/
AnnaBridge 171:3a7713b1edbc 14726 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
AnnaBridge 171:3a7713b1edbc 14727
AnnaBridge 171:3a7713b1edbc 14728 /****************************** SPI Instances *********************************/
AnnaBridge 171:3a7713b1edbc 14729 #define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
AnnaBridge 171:3a7713b1edbc 14730
AnnaBridge 171:3a7713b1edbc 14731 /******************* TIM Instances : All supported instances ******************/
AnnaBridge 171:3a7713b1edbc 14732 #define IS_TIM_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14733 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14734 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14735 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 14736 ((INSTANCE) == TIM6) || \
AnnaBridge 171:3a7713b1edbc 14737 ((INSTANCE) == TIM7) || \
AnnaBridge 171:3a7713b1edbc 14738 ((INSTANCE) == TIM15) || \
AnnaBridge 171:3a7713b1edbc 14739 ((INSTANCE) == TIM16) || \
AnnaBridge 171:3a7713b1edbc 14740 ((INSTANCE) == TIM17))
AnnaBridge 171:3a7713b1edbc 14741
AnnaBridge 171:3a7713b1edbc 14742 /******************* TIM Instances : at least 1 capture/compare channel *******/
AnnaBridge 171:3a7713b1edbc 14743 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14744 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14745 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14746 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 14747 ((INSTANCE) == TIM15) || \
AnnaBridge 171:3a7713b1edbc 14748 ((INSTANCE) == TIM16) || \
AnnaBridge 171:3a7713b1edbc 14749 ((INSTANCE) == TIM17))
AnnaBridge 171:3a7713b1edbc 14750
AnnaBridge 171:3a7713b1edbc 14751 /****************** TIM Instances : at least 2 capture/compare channels *******/
AnnaBridge 171:3a7713b1edbc 14752 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14753 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14754 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14755 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 14756 ((INSTANCE) == TIM15))
AnnaBridge 171:3a7713b1edbc 14757
AnnaBridge 171:3a7713b1edbc 14758 /****************** TIM Instances : at least 3 capture/compare channels *******/
AnnaBridge 171:3a7713b1edbc 14759 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14760 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14761 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14762 ((INSTANCE) == TIM3))
AnnaBridge 171:3a7713b1edbc 14763
AnnaBridge 171:3a7713b1edbc 14764 /****************** TIM Instances : at least 4 capture/compare channels *******/
AnnaBridge 171:3a7713b1edbc 14765 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14766 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14767 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14768 ((INSTANCE) == TIM3))
AnnaBridge 171:3a7713b1edbc 14769
AnnaBridge 171:3a7713b1edbc 14770 /****************** TIM Instances : at least 5 capture/compare channels *******/
AnnaBridge 171:3a7713b1edbc 14771 #define IS_TIM_CC5_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14772 (((INSTANCE) == TIM1))
AnnaBridge 171:3a7713b1edbc 14773
AnnaBridge 171:3a7713b1edbc 14774 /****************** TIM Instances : at least 6 capture/compare channels *******/
AnnaBridge 171:3a7713b1edbc 14775 #define IS_TIM_CC6_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14776 (((INSTANCE) == TIM1))
AnnaBridge 171:3a7713b1edbc 14777
AnnaBridge 171:3a7713b1edbc 14778 /************************** TIM Instances : Advanced-control timers ***********/
AnnaBridge 171:3a7713b1edbc 14779
AnnaBridge 171:3a7713b1edbc 14780 /****************** TIM Instances : Advanced timer instances *******************/
AnnaBridge 171:3a7713b1edbc 14781 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14782 ((INSTANCE) == TIM1)
AnnaBridge 171:3a7713b1edbc 14783
AnnaBridge 171:3a7713b1edbc 14784 /****************** TIM Instances : supporting clock selection ****************/
AnnaBridge 171:3a7713b1edbc 14785 #define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14786 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14787 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14788 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 14789 ((INSTANCE) == TIM15))
AnnaBridge 171:3a7713b1edbc 14790
AnnaBridge 171:3a7713b1edbc 14791 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
AnnaBridge 171:3a7713b1edbc 14792 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14793 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14794 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14795 ((INSTANCE) == TIM3))
AnnaBridge 171:3a7713b1edbc 14796
AnnaBridge 171:3a7713b1edbc 14797 /****************** TIM Instances : supporting external clock mode 2 **********/
AnnaBridge 171:3a7713b1edbc 14798 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14799 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14800 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14801 ((INSTANCE) == TIM3))
AnnaBridge 171:3a7713b1edbc 14802
AnnaBridge 171:3a7713b1edbc 14803 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
AnnaBridge 171:3a7713b1edbc 14804 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14805 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14806 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14807 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 14808 ((INSTANCE) == TIM15))
AnnaBridge 171:3a7713b1edbc 14809
AnnaBridge 171:3a7713b1edbc 14810 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
AnnaBridge 171:3a7713b1edbc 14811 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14812 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14813 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14814 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 14815 ((INSTANCE) == TIM15))
AnnaBridge 171:3a7713b1edbc 14816
AnnaBridge 171:3a7713b1edbc 14817 /****************** TIM Instances : supporting OCxREF clear *******************/
AnnaBridge 171:3a7713b1edbc 14818 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14819 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14820 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14821 ((INSTANCE) == TIM3))
AnnaBridge 171:3a7713b1edbc 14822
AnnaBridge 171:3a7713b1edbc 14823 /****************** TIM Instances : supporting encoder interface **************/
AnnaBridge 171:3a7713b1edbc 14824 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14825 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14826 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14827 ((INSTANCE) == TIM3))
AnnaBridge 171:3a7713b1edbc 14828
AnnaBridge 171:3a7713b1edbc 14829 /****************** TIM Instances : supporting Hall interface *****************/
AnnaBridge 171:3a7713b1edbc 14830 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14831 (((INSTANCE) == TIM1))
AnnaBridge 171:3a7713b1edbc 14832
AnnaBridge 171:3a7713b1edbc 14833 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14834 (((INSTANCE) == TIM1))
AnnaBridge 171:3a7713b1edbc 14835
AnnaBridge 171:3a7713b1edbc 14836 /**************** TIM Instances : external trigger input available ************/
AnnaBridge 171:3a7713b1edbc 14837 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14838 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14839 ((INSTANCE) == TIM3))
AnnaBridge 171:3a7713b1edbc 14840
AnnaBridge 171:3a7713b1edbc 14841 /****************** TIM Instances : supporting input XOR function *************/
AnnaBridge 171:3a7713b1edbc 14842 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14843 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14844 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14845 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 14846 ((INSTANCE) == TIM15))
AnnaBridge 171:3a7713b1edbc 14847
AnnaBridge 171:3a7713b1edbc 14848 /****************** TIM Instances : supporting master mode ********************/
AnnaBridge 171:3a7713b1edbc 14849 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14850 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14851 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14852 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 14853 ((INSTANCE) == TIM6) || \
AnnaBridge 171:3a7713b1edbc 14854 ((INSTANCE) == TIM7) || \
AnnaBridge 171:3a7713b1edbc 14855 ((INSTANCE) == TIM15))
AnnaBridge 171:3a7713b1edbc 14856
AnnaBridge 171:3a7713b1edbc 14857 /****************** TIM Instances : supporting slave mode *********************/
AnnaBridge 171:3a7713b1edbc 14858 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14859 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14860 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14861 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 14862 ((INSTANCE) == TIM15))
AnnaBridge 171:3a7713b1edbc 14863
AnnaBridge 171:3a7713b1edbc 14864 /****************** TIM Instances : supporting synchronization ****************/
AnnaBridge 171:3a7713b1edbc 14865 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14866 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14867 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14868 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 14869 ((INSTANCE) == TIM6) || \
AnnaBridge 171:3a7713b1edbc 14870 ((INSTANCE) == TIM7) || \
AnnaBridge 171:3a7713b1edbc 14871 ((INSTANCE) == TIM15))
AnnaBridge 171:3a7713b1edbc 14872
AnnaBridge 171:3a7713b1edbc 14873 /****************** TIM Instances : supporting 32 bits counter ****************/
AnnaBridge 171:3a7713b1edbc 14874 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14875 ((INSTANCE) == TIM2)
AnnaBridge 171:3a7713b1edbc 14876
AnnaBridge 171:3a7713b1edbc 14877 /****************** TIM Instances : supporting DMA burst **********************/
AnnaBridge 171:3a7713b1edbc 14878 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14879 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14880 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14881 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 14882 ((INSTANCE) == TIM15) || \
AnnaBridge 171:3a7713b1edbc 14883 ((INSTANCE) == TIM16) || \
AnnaBridge 171:3a7713b1edbc 14884 ((INSTANCE) == TIM17))
AnnaBridge 171:3a7713b1edbc 14885
AnnaBridge 171:3a7713b1edbc 14886 /****************** TIM Instances : supporting the break function *************/
AnnaBridge 171:3a7713b1edbc 14887 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14888 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14889 ((INSTANCE) == TIM15) || \
AnnaBridge 171:3a7713b1edbc 14890 ((INSTANCE) == TIM16) || \
AnnaBridge 171:3a7713b1edbc 14891 ((INSTANCE) == TIM17))
AnnaBridge 171:3a7713b1edbc 14892
AnnaBridge 171:3a7713b1edbc 14893 /****************** TIM Instances : supporting input/output channel(s) ********/
AnnaBridge 171:3a7713b1edbc 14894 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
AnnaBridge 171:3a7713b1edbc 14895 ((((INSTANCE) == TIM1) && \
AnnaBridge 171:3a7713b1edbc 14896 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 14897 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 14898 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 14899 ((CHANNEL) == TIM_CHANNEL_4) || \
AnnaBridge 171:3a7713b1edbc 14900 ((CHANNEL) == TIM_CHANNEL_5) || \
AnnaBridge 171:3a7713b1edbc 14901 ((CHANNEL) == TIM_CHANNEL_6))) \
AnnaBridge 171:3a7713b1edbc 14902 || \
AnnaBridge 171:3a7713b1edbc 14903 (((INSTANCE) == TIM2) && \
AnnaBridge 171:3a7713b1edbc 14904 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 14905 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 14906 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 14907 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 171:3a7713b1edbc 14908 || \
AnnaBridge 171:3a7713b1edbc 14909 (((INSTANCE) == TIM3) && \
AnnaBridge 171:3a7713b1edbc 14910 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 14911 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 14912 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 14913 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 171:3a7713b1edbc 14914 || \
AnnaBridge 171:3a7713b1edbc 14915 (((INSTANCE) == TIM15) && \
AnnaBridge 171:3a7713b1edbc 14916 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 14917 ((CHANNEL) == TIM_CHANNEL_2))) \
AnnaBridge 171:3a7713b1edbc 14918 || \
AnnaBridge 171:3a7713b1edbc 14919 (((INSTANCE) == TIM16) && \
AnnaBridge 171:3a7713b1edbc 14920 (((CHANNEL) == TIM_CHANNEL_1))) \
AnnaBridge 171:3a7713b1edbc 14921 || \
AnnaBridge 171:3a7713b1edbc 14922 (((INSTANCE) == TIM17) && \
AnnaBridge 171:3a7713b1edbc 14923 (((CHANNEL) == TIM_CHANNEL_1))))
AnnaBridge 171:3a7713b1edbc 14924
AnnaBridge 171:3a7713b1edbc 14925 /****************** TIM Instances : supporting complementary output(s) ********/
AnnaBridge 171:3a7713b1edbc 14926 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
AnnaBridge 171:3a7713b1edbc 14927 ((((INSTANCE) == TIM1) && \
AnnaBridge 171:3a7713b1edbc 14928 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 14929 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 14930 ((CHANNEL) == TIM_CHANNEL_3))) \
AnnaBridge 171:3a7713b1edbc 14931 || \
AnnaBridge 171:3a7713b1edbc 14932 (((INSTANCE) == TIM15) && \
AnnaBridge 171:3a7713b1edbc 14933 ((CHANNEL) == TIM_CHANNEL_1)) \
AnnaBridge 171:3a7713b1edbc 14934 || \
AnnaBridge 171:3a7713b1edbc 14935 (((INSTANCE) == TIM16) && \
AnnaBridge 171:3a7713b1edbc 14936 ((CHANNEL) == TIM_CHANNEL_1)) \
AnnaBridge 171:3a7713b1edbc 14937 || \
AnnaBridge 171:3a7713b1edbc 14938 (((INSTANCE) == TIM17) && \
AnnaBridge 171:3a7713b1edbc 14939 ((CHANNEL) == TIM_CHANNEL_1)))
AnnaBridge 171:3a7713b1edbc 14940
AnnaBridge 171:3a7713b1edbc 14941 /****************** TIM Instances : supporting counting mode selection ********/
AnnaBridge 171:3a7713b1edbc 14942 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14943 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14944 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14945 ((INSTANCE) == TIM3))
AnnaBridge 171:3a7713b1edbc 14946
AnnaBridge 171:3a7713b1edbc 14947 /****************** TIM Instances : supporting repetition counter *************/
AnnaBridge 171:3a7713b1edbc 14948 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14949 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14950 ((INSTANCE) == TIM15) || \
AnnaBridge 171:3a7713b1edbc 14951 ((INSTANCE) == TIM16) || \
AnnaBridge 171:3a7713b1edbc 14952 ((INSTANCE) == TIM17))
AnnaBridge 171:3a7713b1edbc 14953
AnnaBridge 171:3a7713b1edbc 14954 /****************** TIM Instances : supporting clock division *****************/
AnnaBridge 171:3a7713b1edbc 14955 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14956 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14957 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14958 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 14959 ((INSTANCE) == TIM15) || \
AnnaBridge 171:3a7713b1edbc 14960 ((INSTANCE) == TIM16) || \
AnnaBridge 171:3a7713b1edbc 14961 ((INSTANCE) == TIM17))
AnnaBridge 171:3a7713b1edbc 14962
AnnaBridge 171:3a7713b1edbc 14963 /****************** TIM Instances : supporting 2 break inputs *****************/
AnnaBridge 171:3a7713b1edbc 14964 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14965 (((INSTANCE) == TIM1))
AnnaBridge 171:3a7713b1edbc 14966
AnnaBridge 171:3a7713b1edbc 14967 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
AnnaBridge 171:3a7713b1edbc 14968 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14969 (((INSTANCE) == TIM1))
AnnaBridge 171:3a7713b1edbc 14970
AnnaBridge 171:3a7713b1edbc 14971 /****************** TIM Instances : supporting DMA generation on Update events*/
AnnaBridge 171:3a7713b1edbc 14972 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14973 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14974 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14975 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 14976 ((INSTANCE) == TIM6) || \
AnnaBridge 171:3a7713b1edbc 14977 ((INSTANCE) == TIM7) || \
AnnaBridge 171:3a7713b1edbc 14978 ((INSTANCE) == TIM15) || \
AnnaBridge 171:3a7713b1edbc 14979 ((INSTANCE) == TIM16) || \
AnnaBridge 171:3a7713b1edbc 14980 ((INSTANCE) == TIM17))
AnnaBridge 171:3a7713b1edbc 14981
AnnaBridge 171:3a7713b1edbc 14982 /****************** TIM Instances : supporting DMA generation on Capture/Compare events */
AnnaBridge 171:3a7713b1edbc 14983 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14984 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14985 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 14986 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 14987 ((INSTANCE) == TIM15) || \
AnnaBridge 171:3a7713b1edbc 14988 ((INSTANCE) == TIM16) || \
AnnaBridge 171:3a7713b1edbc 14989 ((INSTANCE) == TIM17))
AnnaBridge 171:3a7713b1edbc 14990
AnnaBridge 171:3a7713b1edbc 14991 /****************** TIM Instances : supporting commutation event generation ***/
AnnaBridge 171:3a7713b1edbc 14992 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 14993 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 14994 ((INSTANCE) == TIM15) || \
AnnaBridge 171:3a7713b1edbc 14995 ((INSTANCE) == TIM16) || \
AnnaBridge 171:3a7713b1edbc 14996 ((INSTANCE) == TIM17))
AnnaBridge 171:3a7713b1edbc 14997
AnnaBridge 171:3a7713b1edbc 14998 /****************** TIM Instances : supporting remapping capability ***********/
AnnaBridge 171:3a7713b1edbc 14999 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 15000 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 15001 ((INSTANCE) == TIM16))
AnnaBridge 171:3a7713b1edbc 15002
AnnaBridge 171:3a7713b1edbc 15003 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
AnnaBridge 171:3a7713b1edbc 15004 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \
AnnaBridge 171:3a7713b1edbc 15005 (((INSTANCE) == TIM1))
AnnaBridge 171:3a7713b1edbc 15006
AnnaBridge 171:3a7713b1edbc 15007 /****************************** TSC Instances *********************************/
AnnaBridge 171:3a7713b1edbc 15008 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
AnnaBridge 171:3a7713b1edbc 15009
AnnaBridge 171:3a7713b1edbc 15010 /******************** USART Instances : Synchronous mode **********************/
AnnaBridge 171:3a7713b1edbc 15011 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 15012 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 15013 ((INSTANCE) == USART3))
AnnaBridge 171:3a7713b1edbc 15014
AnnaBridge 171:3a7713b1edbc 15015 /****************** USART Instances : Auto Baud Rate detection ****************/
AnnaBridge 171:3a7713b1edbc 15016 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
AnnaBridge 171:3a7713b1edbc 15017
AnnaBridge 171:3a7713b1edbc 15018 /******************** UART Instances : Asynchronous mode **********************/
AnnaBridge 171:3a7713b1edbc 15019 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 15020 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 15021 ((INSTANCE) == USART3))
AnnaBridge 171:3a7713b1edbc 15022
AnnaBridge 171:3a7713b1edbc 15023 /******************** UART Instances : Half-Duplex mode **********************/
AnnaBridge 171:3a7713b1edbc 15024 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 15025 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 15026 ((INSTANCE) == USART3))
AnnaBridge 171:3a7713b1edbc 15027
AnnaBridge 171:3a7713b1edbc 15028 /******************** UART Instances : LIN mode **********************/
AnnaBridge 171:3a7713b1edbc 15029 #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
AnnaBridge 171:3a7713b1edbc 15030
AnnaBridge 171:3a7713b1edbc 15031 /******************** UART Instances : Wake-up from Stop mode **********************/
AnnaBridge 171:3a7713b1edbc 15032 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
AnnaBridge 171:3a7713b1edbc 15033
AnnaBridge 171:3a7713b1edbc 15034 /****************** UART Instances : Hardware Flow control ********************/
AnnaBridge 171:3a7713b1edbc 15035 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 15036 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 15037 ((INSTANCE) == USART3))
AnnaBridge 171:3a7713b1edbc 15038
AnnaBridge 171:3a7713b1edbc 15039 /****************** UART Instances : Auto Baud Rate detection *****************/
AnnaBridge 171:3a7713b1edbc 15040 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
AnnaBridge 171:3a7713b1edbc 15041
AnnaBridge 171:3a7713b1edbc 15042 /****************** UART Instances : Driver Enable ****************************/
AnnaBridge 171:3a7713b1edbc 15043 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 15044 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 15045 ((INSTANCE) == USART3))
AnnaBridge 171:3a7713b1edbc 15046
AnnaBridge 171:3a7713b1edbc 15047 /********************* UART Instances : Smard card mode ***********************/
AnnaBridge 171:3a7713b1edbc 15048 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
AnnaBridge 171:3a7713b1edbc 15049
AnnaBridge 171:3a7713b1edbc 15050 /*********************** UART Instances : IRDA mode ***************************/
AnnaBridge 171:3a7713b1edbc 15051 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
AnnaBridge 171:3a7713b1edbc 15052
AnnaBridge 171:3a7713b1edbc 15053 /******************** UART Instances : Support of continuous communication using DMA ****/
AnnaBridge 171:3a7713b1edbc 15054 #define IS_UART_DMA_INSTANCE(INSTANCE) (1)
AnnaBridge 171:3a7713b1edbc 15055 /****************************** WWDG Instances ********************************/
AnnaBridge 171:3a7713b1edbc 15056 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
AnnaBridge 171:3a7713b1edbc 15057
AnnaBridge 171:3a7713b1edbc 15058 /**
AnnaBridge 171:3a7713b1edbc 15059 * @}
AnnaBridge 171:3a7713b1edbc 15060 */
AnnaBridge 171:3a7713b1edbc 15061
AnnaBridge 171:3a7713b1edbc 15062
AnnaBridge 171:3a7713b1edbc 15063 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 15064 /* For a painless codes migration between the STM32F3xx device product */
AnnaBridge 171:3a7713b1edbc 15065 /* lines, the aliases defined below are put in place to overcome the */
AnnaBridge 171:3a7713b1edbc 15066 /* differences in the interrupt handlers and IRQn definitions. */
AnnaBridge 171:3a7713b1edbc 15067 /* No need to update developed interrupt code when moving across */
AnnaBridge 171:3a7713b1edbc 15068 /* product lines within the same STM32F3 Family */
AnnaBridge 171:3a7713b1edbc 15069 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 15070
AnnaBridge 171:3a7713b1edbc 15071 /* Aliases for __IRQn */
AnnaBridge 171:3a7713b1edbc 15072 #define ADC1_IRQn ADC1_2_IRQn
AnnaBridge 171:3a7713b1edbc 15073 #define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
AnnaBridge 171:3a7713b1edbc 15074 #define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
AnnaBridge 171:3a7713b1edbc 15075 #define COMP1_2_IRQn COMP2_IRQn
AnnaBridge 171:3a7713b1edbc 15076 #define COMP1_2_3_IRQn COMP2_IRQn
AnnaBridge 171:3a7713b1edbc 15077 #define COMP_IRQn COMP2_IRQn
AnnaBridge 171:3a7713b1edbc 15078 #define COMP4_5_6_IRQn COMP4_6_IRQn
AnnaBridge 171:3a7713b1edbc 15079 #define I2C3_ER_IRQn HRTIM1_FLT_IRQn
AnnaBridge 171:3a7713b1edbc 15080 #define I2C3_EV_IRQn HRTIM1_TIME_IRQn
AnnaBridge 171:3a7713b1edbc 15081 #define TIM15_IRQn TIM1_BRK_TIM15_IRQn
AnnaBridge 171:3a7713b1edbc 15082 #define TIM18_DAC2_IRQn TIM1_CC_IRQn
AnnaBridge 171:3a7713b1edbc 15083 #define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
AnnaBridge 171:3a7713b1edbc 15084 #define TIM16_IRQn TIM1_UP_TIM16_IRQn
AnnaBridge 171:3a7713b1edbc 15085 #define TIM6_DAC_IRQn TIM6_DAC1_IRQn
AnnaBridge 171:3a7713b1edbc 15086 #define TIM7_IRQn TIM7_DAC2_IRQn
AnnaBridge 171:3a7713b1edbc 15087
AnnaBridge 171:3a7713b1edbc 15088
AnnaBridge 171:3a7713b1edbc 15089 /* Aliases for __IRQHandler */
AnnaBridge 171:3a7713b1edbc 15090 #define ADC1_IRQHandler ADC1_2_IRQHandler
AnnaBridge 171:3a7713b1edbc 15091 #define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
AnnaBridge 171:3a7713b1edbc 15092 #define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
AnnaBridge 171:3a7713b1edbc 15093 #define COMP1_2_IRQHandler COMP2_IRQHandler
AnnaBridge 171:3a7713b1edbc 15094 #define COMP1_2_3_IRQHandler COMP2_IRQHandler
AnnaBridge 171:3a7713b1edbc 15095 #define COMP_IRQHandler COMP2_IRQHandler
AnnaBridge 171:3a7713b1edbc 15096 #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
AnnaBridge 171:3a7713b1edbc 15097 #define I2C3_ER_IRQHandler HRTIM1_FLT_IRQHandler
AnnaBridge 171:3a7713b1edbc 15098 #define I2C3_EV_IRQHandler HRTIM1_TIME_IRQHandler
AnnaBridge 171:3a7713b1edbc 15099 #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
AnnaBridge 171:3a7713b1edbc 15100 #define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
AnnaBridge 171:3a7713b1edbc 15101 #define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
AnnaBridge 171:3a7713b1edbc 15102 #define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
AnnaBridge 171:3a7713b1edbc 15103 #define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
AnnaBridge 171:3a7713b1edbc 15104 #define TIM7_IRQHandler TIM7_DAC2_IRQHandler
AnnaBridge 171:3a7713b1edbc 15105
AnnaBridge 171:3a7713b1edbc 15106
AnnaBridge 171:3a7713b1edbc 15107 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 15108 }
AnnaBridge 171:3a7713b1edbc 15109 #endif /* __cplusplus */
AnnaBridge 171:3a7713b1edbc 15110
AnnaBridge 171:3a7713b1edbc 15111 #endif /* __STM32F334x8_H */
AnnaBridge 171:3a7713b1edbc 15112
AnnaBridge 171:3a7713b1edbc 15113 /**
AnnaBridge 171:3a7713b1edbc 15114 * @}
AnnaBridge 171:3a7713b1edbc 15115 */
AnnaBridge 171:3a7713b1edbc 15116
AnnaBridge 171:3a7713b1edbc 15117 /**
AnnaBridge 171:3a7713b1edbc 15118 * @}
AnnaBridge 171:3a7713b1edbc 15119 */
AnnaBridge 171:3a7713b1edbc 15120
AnnaBridge 171:3a7713b1edbc 15121 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/