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TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_MICRO/stm32f3xx_ll_cortex.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_DISCO_F303VC/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_cortex.h@168:b9e159c1930a
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 163:e59c8e839560 | 1 | /** |
| AnnaBridge | 163:e59c8e839560 | 2 | ****************************************************************************** |
| AnnaBridge | 163:e59c8e839560 | 3 | * @file stm32f3xx_ll_cortex.h |
| AnnaBridge | 163:e59c8e839560 | 4 | * @author MCD Application Team |
| AnnaBridge | 163:e59c8e839560 | 5 | * @brief Header file of CORTEX LL module. |
| AnnaBridge | 163:e59c8e839560 | 6 | @verbatim |
| AnnaBridge | 163:e59c8e839560 | 7 | ============================================================================== |
| AnnaBridge | 163:e59c8e839560 | 8 | ##### How to use this driver ##### |
| AnnaBridge | 163:e59c8e839560 | 9 | ============================================================================== |
| AnnaBridge | 163:e59c8e839560 | 10 | [..] |
| AnnaBridge | 163:e59c8e839560 | 11 | The LL CORTEX driver contains a set of generic APIs that can be |
| AnnaBridge | 163:e59c8e839560 | 12 | used by user: |
| AnnaBridge | 163:e59c8e839560 | 13 | (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick |
| AnnaBridge | 163:e59c8e839560 | 14 | functions |
| AnnaBridge | 163:e59c8e839560 | 15 | (+) Low power mode configuration (SCB register of Cortex-MCU) |
| AnnaBridge | 163:e59c8e839560 | 16 | (+) MPU API to configure and enable regions |
| AnnaBridge | 163:e59c8e839560 | 17 | (MPU services provided only on some devices) |
| AnnaBridge | 163:e59c8e839560 | 18 | (+) API to access to MCU info (CPUID register) |
| AnnaBridge | 163:e59c8e839560 | 19 | (+) API to enable fault handler (SHCSR accesses) |
| AnnaBridge | 163:e59c8e839560 | 20 | |
| AnnaBridge | 163:e59c8e839560 | 21 | @endverbatim |
| AnnaBridge | 163:e59c8e839560 | 22 | ****************************************************************************** |
| AnnaBridge | 163:e59c8e839560 | 23 | * @attention |
| AnnaBridge | 163:e59c8e839560 | 24 | * |
| AnnaBridge | 163:e59c8e839560 | 25 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 163:e59c8e839560 | 26 | * |
| AnnaBridge | 163:e59c8e839560 | 27 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 163:e59c8e839560 | 28 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 163:e59c8e839560 | 29 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 163:e59c8e839560 | 30 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 163:e59c8e839560 | 31 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 163:e59c8e839560 | 32 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 163:e59c8e839560 | 33 | * and/or other materials provided with the distribution. |
| AnnaBridge | 163:e59c8e839560 | 34 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 163:e59c8e839560 | 35 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 163:e59c8e839560 | 36 | * without specific prior written permission. |
| AnnaBridge | 163:e59c8e839560 | 37 | * |
| AnnaBridge | 163:e59c8e839560 | 38 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 163:e59c8e839560 | 39 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 163:e59c8e839560 | 40 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 163:e59c8e839560 | 41 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 163:e59c8e839560 | 42 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 163:e59c8e839560 | 43 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 163:e59c8e839560 | 44 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 163:e59c8e839560 | 45 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 163:e59c8e839560 | 46 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 163:e59c8e839560 | 47 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 163:e59c8e839560 | 48 | * |
| AnnaBridge | 163:e59c8e839560 | 49 | ****************************************************************************** |
| AnnaBridge | 163:e59c8e839560 | 50 | */ |
| AnnaBridge | 163:e59c8e839560 | 51 | |
| AnnaBridge | 163:e59c8e839560 | 52 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 53 | #ifndef __STM32F3xx_LL_CORTEX_H |
| AnnaBridge | 163:e59c8e839560 | 54 | #define __STM32F3xx_LL_CORTEX_H |
| AnnaBridge | 163:e59c8e839560 | 55 | |
| AnnaBridge | 163:e59c8e839560 | 56 | #ifdef __cplusplus |
| AnnaBridge | 163:e59c8e839560 | 57 | extern "C" { |
| AnnaBridge | 163:e59c8e839560 | 58 | #endif |
| AnnaBridge | 163:e59c8e839560 | 59 | |
| AnnaBridge | 163:e59c8e839560 | 60 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 61 | #include "stm32f3xx.h" |
| AnnaBridge | 163:e59c8e839560 | 62 | |
| AnnaBridge | 163:e59c8e839560 | 63 | /** @addtogroup STM32F3xx_LL_Driver |
| AnnaBridge | 163:e59c8e839560 | 64 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 65 | */ |
| AnnaBridge | 163:e59c8e839560 | 66 | |
| AnnaBridge | 163:e59c8e839560 | 67 | /** @defgroup CORTEX_LL CORTEX |
| AnnaBridge | 163:e59c8e839560 | 68 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 69 | */ |
| AnnaBridge | 163:e59c8e839560 | 70 | |
| AnnaBridge | 163:e59c8e839560 | 71 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 72 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 73 | |
| AnnaBridge | 163:e59c8e839560 | 74 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 75 | |
| AnnaBridge | 163:e59c8e839560 | 76 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 77 | |
| AnnaBridge | 163:e59c8e839560 | 78 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 79 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 80 | /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants |
| AnnaBridge | 163:e59c8e839560 | 81 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 82 | */ |
| AnnaBridge | 163:e59c8e839560 | 83 | |
| AnnaBridge | 163:e59c8e839560 | 84 | /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source |
| AnnaBridge | 163:e59c8e839560 | 85 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 86 | */ |
| AnnaBridge | 168:b9e159c1930a | 87 | #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ |
| AnnaBridge | 168:b9e159c1930a | 88 | #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ |
| AnnaBridge | 163:e59c8e839560 | 89 | /** |
| AnnaBridge | 163:e59c8e839560 | 90 | * @} |
| AnnaBridge | 163:e59c8e839560 | 91 | */ |
| AnnaBridge | 163:e59c8e839560 | 92 | |
| AnnaBridge | 163:e59c8e839560 | 93 | /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type |
| AnnaBridge | 163:e59c8e839560 | 94 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 95 | */ |
| AnnaBridge | 163:e59c8e839560 | 96 | #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ |
| AnnaBridge | 163:e59c8e839560 | 97 | #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ |
| AnnaBridge | 163:e59c8e839560 | 98 | #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ |
| AnnaBridge | 163:e59c8e839560 | 99 | /** |
| AnnaBridge | 163:e59c8e839560 | 100 | * @} |
| AnnaBridge | 163:e59c8e839560 | 101 | */ |
| AnnaBridge | 163:e59c8e839560 | 102 | |
| AnnaBridge | 163:e59c8e839560 | 103 | #if __MPU_PRESENT |
| AnnaBridge | 163:e59c8e839560 | 104 | |
| AnnaBridge | 163:e59c8e839560 | 105 | /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control |
| AnnaBridge | 163:e59c8e839560 | 106 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 107 | */ |
| AnnaBridge | 168:b9e159c1930a | 108 | #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ |
| AnnaBridge | 163:e59c8e839560 | 109 | #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ |
| AnnaBridge | 163:e59c8e839560 | 110 | #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ |
| AnnaBridge | 163:e59c8e839560 | 111 | #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ |
| AnnaBridge | 163:e59c8e839560 | 112 | /** |
| AnnaBridge | 163:e59c8e839560 | 113 | * @} |
| AnnaBridge | 163:e59c8e839560 | 114 | */ |
| AnnaBridge | 163:e59c8e839560 | 115 | |
| AnnaBridge | 163:e59c8e839560 | 116 | /** @defgroup CORTEX_LL_EC_REGION MPU Region Number |
| AnnaBridge | 163:e59c8e839560 | 117 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 118 | */ |
| AnnaBridge | 168:b9e159c1930a | 119 | #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ |
| AnnaBridge | 168:b9e159c1930a | 120 | #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ |
| AnnaBridge | 168:b9e159c1930a | 121 | #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ |
| AnnaBridge | 168:b9e159c1930a | 122 | #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ |
| AnnaBridge | 168:b9e159c1930a | 123 | #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ |
| AnnaBridge | 168:b9e159c1930a | 124 | #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ |
| AnnaBridge | 168:b9e159c1930a | 125 | #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ |
| AnnaBridge | 168:b9e159c1930a | 126 | #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ |
| AnnaBridge | 163:e59c8e839560 | 127 | /** |
| AnnaBridge | 163:e59c8e839560 | 128 | * @} |
| AnnaBridge | 163:e59c8e839560 | 129 | */ |
| AnnaBridge | 163:e59c8e839560 | 130 | |
| AnnaBridge | 163:e59c8e839560 | 131 | /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size |
| AnnaBridge | 163:e59c8e839560 | 132 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 133 | */ |
| AnnaBridge | 168:b9e159c1930a | 134 | #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 135 | #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 136 | #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 137 | #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 138 | #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 139 | #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 140 | #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 141 | #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 142 | #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 143 | #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 144 | #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 145 | #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 146 | #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 147 | #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 148 | #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 149 | #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 150 | #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 151 | #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 152 | #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 153 | #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 154 | #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 155 | #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 156 | #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 157 | #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 158 | #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 159 | #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 160 | #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ |
| AnnaBridge | 168:b9e159c1930a | 161 | #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ |
| AnnaBridge | 163:e59c8e839560 | 162 | /** |
| AnnaBridge | 163:e59c8e839560 | 163 | * @} |
| AnnaBridge | 163:e59c8e839560 | 164 | */ |
| AnnaBridge | 163:e59c8e839560 | 165 | |
| AnnaBridge | 163:e59c8e839560 | 166 | /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges |
| AnnaBridge | 163:e59c8e839560 | 167 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 168 | */ |
| AnnaBridge | 168:b9e159c1930a | 169 | #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ |
| AnnaBridge | 168:b9e159c1930a | 170 | #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ |
| AnnaBridge | 168:b9e159c1930a | 171 | #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ |
| AnnaBridge | 168:b9e159c1930a | 172 | #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ |
| AnnaBridge | 168:b9e159c1930a | 173 | #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ |
| AnnaBridge | 168:b9e159c1930a | 174 | #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ |
| AnnaBridge | 163:e59c8e839560 | 175 | /** |
| AnnaBridge | 163:e59c8e839560 | 176 | * @} |
| AnnaBridge | 163:e59c8e839560 | 177 | */ |
| AnnaBridge | 163:e59c8e839560 | 178 | |
| AnnaBridge | 163:e59c8e839560 | 179 | /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level |
| AnnaBridge | 163:e59c8e839560 | 180 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 181 | */ |
| AnnaBridge | 168:b9e159c1930a | 182 | #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ |
| AnnaBridge | 168:b9e159c1930a | 183 | #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ |
| AnnaBridge | 168:b9e159c1930a | 184 | #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ |
| AnnaBridge | 168:b9e159c1930a | 185 | #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ |
| AnnaBridge | 163:e59c8e839560 | 186 | /** |
| AnnaBridge | 163:e59c8e839560 | 187 | * @} |
| AnnaBridge | 163:e59c8e839560 | 188 | */ |
| AnnaBridge | 163:e59c8e839560 | 189 | |
| AnnaBridge | 163:e59c8e839560 | 190 | /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access |
| AnnaBridge | 163:e59c8e839560 | 191 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 192 | */ |
| AnnaBridge | 168:b9e159c1930a | 193 | #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ |
| AnnaBridge | 163:e59c8e839560 | 194 | #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ |
| AnnaBridge | 163:e59c8e839560 | 195 | /** |
| AnnaBridge | 163:e59c8e839560 | 196 | * @} |
| AnnaBridge | 163:e59c8e839560 | 197 | */ |
| AnnaBridge | 163:e59c8e839560 | 198 | |
| AnnaBridge | 163:e59c8e839560 | 199 | /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access |
| AnnaBridge | 163:e59c8e839560 | 200 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 201 | */ |
| AnnaBridge | 163:e59c8e839560 | 202 | #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ |
| AnnaBridge | 168:b9e159c1930a | 203 | #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ |
| AnnaBridge | 163:e59c8e839560 | 204 | /** |
| AnnaBridge | 163:e59c8e839560 | 205 | * @} |
| AnnaBridge | 163:e59c8e839560 | 206 | */ |
| AnnaBridge | 163:e59c8e839560 | 207 | |
| AnnaBridge | 163:e59c8e839560 | 208 | /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access |
| AnnaBridge | 163:e59c8e839560 | 209 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 210 | */ |
| AnnaBridge | 163:e59c8e839560 | 211 | #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ |
| AnnaBridge | 168:b9e159c1930a | 212 | #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ |
| AnnaBridge | 163:e59c8e839560 | 213 | /** |
| AnnaBridge | 163:e59c8e839560 | 214 | * @} |
| AnnaBridge | 163:e59c8e839560 | 215 | */ |
| AnnaBridge | 163:e59c8e839560 | 216 | |
| AnnaBridge | 163:e59c8e839560 | 217 | /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access |
| AnnaBridge | 163:e59c8e839560 | 218 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 219 | */ |
| AnnaBridge | 163:e59c8e839560 | 220 | #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ |
| AnnaBridge | 168:b9e159c1930a | 221 | #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ |
| AnnaBridge | 163:e59c8e839560 | 222 | /** |
| AnnaBridge | 163:e59c8e839560 | 223 | * @} |
| AnnaBridge | 163:e59c8e839560 | 224 | */ |
| AnnaBridge | 163:e59c8e839560 | 225 | #endif /* __MPU_PRESENT */ |
| AnnaBridge | 163:e59c8e839560 | 226 | /** |
| AnnaBridge | 163:e59c8e839560 | 227 | * @} |
| AnnaBridge | 163:e59c8e839560 | 228 | */ |
| AnnaBridge | 163:e59c8e839560 | 229 | |
| AnnaBridge | 163:e59c8e839560 | 230 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 231 | |
| AnnaBridge | 163:e59c8e839560 | 232 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 233 | /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions |
| AnnaBridge | 163:e59c8e839560 | 234 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 235 | */ |
| AnnaBridge | 163:e59c8e839560 | 236 | |
| AnnaBridge | 163:e59c8e839560 | 237 | /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK |
| AnnaBridge | 163:e59c8e839560 | 238 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 239 | */ |
| AnnaBridge | 163:e59c8e839560 | 240 | |
| AnnaBridge | 163:e59c8e839560 | 241 | /** |
| AnnaBridge | 163:e59c8e839560 | 242 | * @brief This function checks if the Systick counter flag is active or not. |
| AnnaBridge | 163:e59c8e839560 | 243 | * @note It can be used in timeout function on application side. |
| AnnaBridge | 163:e59c8e839560 | 244 | * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag |
| AnnaBridge | 163:e59c8e839560 | 245 | * @retval State of bit (1 or 0). |
| AnnaBridge | 163:e59c8e839560 | 246 | */ |
| AnnaBridge | 163:e59c8e839560 | 247 | __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) |
| AnnaBridge | 163:e59c8e839560 | 248 | { |
| AnnaBridge | 163:e59c8e839560 | 249 | return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); |
| AnnaBridge | 163:e59c8e839560 | 250 | } |
| AnnaBridge | 163:e59c8e839560 | 251 | |
| AnnaBridge | 163:e59c8e839560 | 252 | /** |
| AnnaBridge | 163:e59c8e839560 | 253 | * @brief Configures the SysTick clock source |
| AnnaBridge | 163:e59c8e839560 | 254 | * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource |
| AnnaBridge | 163:e59c8e839560 | 255 | * @param Source This parameter can be one of the following values: |
| AnnaBridge | 163:e59c8e839560 | 256 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 |
| AnnaBridge | 163:e59c8e839560 | 257 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK |
| AnnaBridge | 163:e59c8e839560 | 258 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 259 | */ |
| AnnaBridge | 163:e59c8e839560 | 260 | __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) |
| AnnaBridge | 163:e59c8e839560 | 261 | { |
| AnnaBridge | 163:e59c8e839560 | 262 | if (Source == LL_SYSTICK_CLKSOURCE_HCLK) |
| AnnaBridge | 163:e59c8e839560 | 263 | { |
| AnnaBridge | 163:e59c8e839560 | 264 | SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); |
| AnnaBridge | 163:e59c8e839560 | 265 | } |
| AnnaBridge | 163:e59c8e839560 | 266 | else |
| AnnaBridge | 163:e59c8e839560 | 267 | { |
| AnnaBridge | 163:e59c8e839560 | 268 | CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); |
| AnnaBridge | 163:e59c8e839560 | 269 | } |
| AnnaBridge | 163:e59c8e839560 | 270 | } |
| AnnaBridge | 163:e59c8e839560 | 271 | |
| AnnaBridge | 163:e59c8e839560 | 272 | /** |
| AnnaBridge | 163:e59c8e839560 | 273 | * @brief Get the SysTick clock source |
| AnnaBridge | 163:e59c8e839560 | 274 | * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource |
| AnnaBridge | 163:e59c8e839560 | 275 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 163:e59c8e839560 | 276 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 |
| AnnaBridge | 163:e59c8e839560 | 277 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK |
| AnnaBridge | 163:e59c8e839560 | 278 | */ |
| AnnaBridge | 163:e59c8e839560 | 279 | __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) |
| AnnaBridge | 163:e59c8e839560 | 280 | { |
| AnnaBridge | 163:e59c8e839560 | 281 | return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); |
| AnnaBridge | 163:e59c8e839560 | 282 | } |
| AnnaBridge | 163:e59c8e839560 | 283 | |
| AnnaBridge | 163:e59c8e839560 | 284 | /** |
| AnnaBridge | 163:e59c8e839560 | 285 | * @brief Enable SysTick exception request |
| AnnaBridge | 163:e59c8e839560 | 286 | * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT |
| AnnaBridge | 163:e59c8e839560 | 287 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 288 | */ |
| AnnaBridge | 163:e59c8e839560 | 289 | __STATIC_INLINE void LL_SYSTICK_EnableIT(void) |
| AnnaBridge | 163:e59c8e839560 | 290 | { |
| AnnaBridge | 163:e59c8e839560 | 291 | SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); |
| AnnaBridge | 163:e59c8e839560 | 292 | } |
| AnnaBridge | 163:e59c8e839560 | 293 | |
| AnnaBridge | 163:e59c8e839560 | 294 | /** |
| AnnaBridge | 163:e59c8e839560 | 295 | * @brief Disable SysTick exception request |
| AnnaBridge | 163:e59c8e839560 | 296 | * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT |
| AnnaBridge | 163:e59c8e839560 | 297 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 298 | */ |
| AnnaBridge | 163:e59c8e839560 | 299 | __STATIC_INLINE void LL_SYSTICK_DisableIT(void) |
| AnnaBridge | 163:e59c8e839560 | 300 | { |
| AnnaBridge | 163:e59c8e839560 | 301 | CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); |
| AnnaBridge | 163:e59c8e839560 | 302 | } |
| AnnaBridge | 163:e59c8e839560 | 303 | |
| AnnaBridge | 163:e59c8e839560 | 304 | /** |
| AnnaBridge | 163:e59c8e839560 | 305 | * @brief Checks if the SYSTICK interrupt is enabled or disabled. |
| AnnaBridge | 163:e59c8e839560 | 306 | * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT |
| AnnaBridge | 163:e59c8e839560 | 307 | * @retval State of bit (1 or 0). |
| AnnaBridge | 163:e59c8e839560 | 308 | */ |
| AnnaBridge | 163:e59c8e839560 | 309 | __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) |
| AnnaBridge | 163:e59c8e839560 | 310 | { |
| AnnaBridge | 163:e59c8e839560 | 311 | return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); |
| AnnaBridge | 163:e59c8e839560 | 312 | } |
| AnnaBridge | 163:e59c8e839560 | 313 | |
| AnnaBridge | 163:e59c8e839560 | 314 | /** |
| AnnaBridge | 163:e59c8e839560 | 315 | * @} |
| AnnaBridge | 163:e59c8e839560 | 316 | */ |
| AnnaBridge | 163:e59c8e839560 | 317 | |
| AnnaBridge | 163:e59c8e839560 | 318 | /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE |
| AnnaBridge | 163:e59c8e839560 | 319 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 320 | */ |
| AnnaBridge | 163:e59c8e839560 | 321 | |
| AnnaBridge | 163:e59c8e839560 | 322 | /** |
| AnnaBridge | 163:e59c8e839560 | 323 | * @brief Processor uses sleep as its low power mode |
| AnnaBridge | 163:e59c8e839560 | 324 | * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep |
| AnnaBridge | 163:e59c8e839560 | 325 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 326 | */ |
| AnnaBridge | 163:e59c8e839560 | 327 | __STATIC_INLINE void LL_LPM_EnableSleep(void) |
| AnnaBridge | 163:e59c8e839560 | 328 | { |
| AnnaBridge | 163:e59c8e839560 | 329 | /* Clear SLEEPDEEP bit of Cortex System Control Register */ |
| AnnaBridge | 163:e59c8e839560 | 330 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
| AnnaBridge | 163:e59c8e839560 | 331 | } |
| AnnaBridge | 163:e59c8e839560 | 332 | |
| AnnaBridge | 163:e59c8e839560 | 333 | /** |
| AnnaBridge | 163:e59c8e839560 | 334 | * @brief Processor uses deep sleep as its low power mode |
| AnnaBridge | 163:e59c8e839560 | 335 | * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep |
| AnnaBridge | 163:e59c8e839560 | 336 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 337 | */ |
| AnnaBridge | 163:e59c8e839560 | 338 | __STATIC_INLINE void LL_LPM_EnableDeepSleep(void) |
| AnnaBridge | 163:e59c8e839560 | 339 | { |
| AnnaBridge | 163:e59c8e839560 | 340 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
| AnnaBridge | 163:e59c8e839560 | 341 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
| AnnaBridge | 163:e59c8e839560 | 342 | } |
| AnnaBridge | 163:e59c8e839560 | 343 | |
| AnnaBridge | 163:e59c8e839560 | 344 | /** |
| AnnaBridge | 163:e59c8e839560 | 345 | * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. |
| AnnaBridge | 163:e59c8e839560 | 346 | * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an |
| AnnaBridge | 163:e59c8e839560 | 347 | * empty main application. |
| AnnaBridge | 163:e59c8e839560 | 348 | * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit |
| AnnaBridge | 163:e59c8e839560 | 349 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 350 | */ |
| AnnaBridge | 163:e59c8e839560 | 351 | __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) |
| AnnaBridge | 163:e59c8e839560 | 352 | { |
| AnnaBridge | 163:e59c8e839560 | 353 | /* Set SLEEPONEXIT bit of Cortex System Control Register */ |
| AnnaBridge | 163:e59c8e839560 | 354 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
| AnnaBridge | 163:e59c8e839560 | 355 | } |
| AnnaBridge | 163:e59c8e839560 | 356 | |
| AnnaBridge | 163:e59c8e839560 | 357 | /** |
| AnnaBridge | 163:e59c8e839560 | 358 | * @brief Do not sleep when returning to Thread mode. |
| AnnaBridge | 163:e59c8e839560 | 359 | * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit |
| AnnaBridge | 163:e59c8e839560 | 360 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 361 | */ |
| AnnaBridge | 163:e59c8e839560 | 362 | __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) |
| AnnaBridge | 163:e59c8e839560 | 363 | { |
| AnnaBridge | 163:e59c8e839560 | 364 | /* Clear SLEEPONEXIT bit of Cortex System Control Register */ |
| AnnaBridge | 163:e59c8e839560 | 365 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
| AnnaBridge | 163:e59c8e839560 | 366 | } |
| AnnaBridge | 163:e59c8e839560 | 367 | |
| AnnaBridge | 163:e59c8e839560 | 368 | /** |
| AnnaBridge | 163:e59c8e839560 | 369 | * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the |
| AnnaBridge | 163:e59c8e839560 | 370 | * processor. |
| AnnaBridge | 163:e59c8e839560 | 371 | * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend |
| AnnaBridge | 163:e59c8e839560 | 372 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 373 | */ |
| AnnaBridge | 163:e59c8e839560 | 374 | __STATIC_INLINE void LL_LPM_EnableEventOnPend(void) |
| AnnaBridge | 163:e59c8e839560 | 375 | { |
| AnnaBridge | 163:e59c8e839560 | 376 | /* Set SEVEONPEND bit of Cortex System Control Register */ |
| AnnaBridge | 163:e59c8e839560 | 377 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
| AnnaBridge | 163:e59c8e839560 | 378 | } |
| AnnaBridge | 163:e59c8e839560 | 379 | |
| AnnaBridge | 163:e59c8e839560 | 380 | /** |
| AnnaBridge | 163:e59c8e839560 | 381 | * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are |
| AnnaBridge | 163:e59c8e839560 | 382 | * excluded |
| AnnaBridge | 163:e59c8e839560 | 383 | * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend |
| AnnaBridge | 163:e59c8e839560 | 384 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 385 | */ |
| AnnaBridge | 163:e59c8e839560 | 386 | __STATIC_INLINE void LL_LPM_DisableEventOnPend(void) |
| AnnaBridge | 163:e59c8e839560 | 387 | { |
| AnnaBridge | 163:e59c8e839560 | 388 | /* Clear SEVEONPEND bit of Cortex System Control Register */ |
| AnnaBridge | 163:e59c8e839560 | 389 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
| AnnaBridge | 163:e59c8e839560 | 390 | } |
| AnnaBridge | 163:e59c8e839560 | 391 | |
| AnnaBridge | 163:e59c8e839560 | 392 | /** |
| AnnaBridge | 163:e59c8e839560 | 393 | * @} |
| AnnaBridge | 163:e59c8e839560 | 394 | */ |
| AnnaBridge | 163:e59c8e839560 | 395 | |
| AnnaBridge | 163:e59c8e839560 | 396 | /** @defgroup CORTEX_LL_EF_HANDLER HANDLER |
| AnnaBridge | 163:e59c8e839560 | 397 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 398 | */ |
| AnnaBridge | 163:e59c8e839560 | 399 | |
| AnnaBridge | 163:e59c8e839560 | 400 | /** |
| AnnaBridge | 163:e59c8e839560 | 401 | * @brief Enable a fault in System handler control register (SHCSR) |
| AnnaBridge | 163:e59c8e839560 | 402 | * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault |
| AnnaBridge | 163:e59c8e839560 | 403 | * @param Fault This parameter can be a combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 404 | * @arg @ref LL_HANDLER_FAULT_USG |
| AnnaBridge | 163:e59c8e839560 | 405 | * @arg @ref LL_HANDLER_FAULT_BUS |
| AnnaBridge | 163:e59c8e839560 | 406 | * @arg @ref LL_HANDLER_FAULT_MEM |
| AnnaBridge | 163:e59c8e839560 | 407 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 408 | */ |
| AnnaBridge | 163:e59c8e839560 | 409 | __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) |
| AnnaBridge | 163:e59c8e839560 | 410 | { |
| AnnaBridge | 163:e59c8e839560 | 411 | /* Enable the system handler fault */ |
| AnnaBridge | 163:e59c8e839560 | 412 | SET_BIT(SCB->SHCSR, Fault); |
| AnnaBridge | 163:e59c8e839560 | 413 | } |
| AnnaBridge | 163:e59c8e839560 | 414 | |
| AnnaBridge | 163:e59c8e839560 | 415 | /** |
| AnnaBridge | 163:e59c8e839560 | 416 | * @brief Disable a fault in System handler control register (SHCSR) |
| AnnaBridge | 163:e59c8e839560 | 417 | * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault |
| AnnaBridge | 163:e59c8e839560 | 418 | * @param Fault This parameter can be a combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 419 | * @arg @ref LL_HANDLER_FAULT_USG |
| AnnaBridge | 163:e59c8e839560 | 420 | * @arg @ref LL_HANDLER_FAULT_BUS |
| AnnaBridge | 163:e59c8e839560 | 421 | * @arg @ref LL_HANDLER_FAULT_MEM |
| AnnaBridge | 163:e59c8e839560 | 422 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 423 | */ |
| AnnaBridge | 163:e59c8e839560 | 424 | __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) |
| AnnaBridge | 163:e59c8e839560 | 425 | { |
| AnnaBridge | 163:e59c8e839560 | 426 | /* Disable the system handler fault */ |
| AnnaBridge | 163:e59c8e839560 | 427 | CLEAR_BIT(SCB->SHCSR, Fault); |
| AnnaBridge | 163:e59c8e839560 | 428 | } |
| AnnaBridge | 163:e59c8e839560 | 429 | |
| AnnaBridge | 163:e59c8e839560 | 430 | /** |
| AnnaBridge | 163:e59c8e839560 | 431 | * @} |
| AnnaBridge | 163:e59c8e839560 | 432 | */ |
| AnnaBridge | 163:e59c8e839560 | 433 | |
| AnnaBridge | 163:e59c8e839560 | 434 | /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO |
| AnnaBridge | 163:e59c8e839560 | 435 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 436 | */ |
| AnnaBridge | 163:e59c8e839560 | 437 | |
| AnnaBridge | 163:e59c8e839560 | 438 | /** |
| AnnaBridge | 163:e59c8e839560 | 439 | * @brief Get Implementer code |
| AnnaBridge | 163:e59c8e839560 | 440 | * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer |
| AnnaBridge | 163:e59c8e839560 | 441 | * @retval Value should be equal to 0x41 for ARM |
| AnnaBridge | 163:e59c8e839560 | 442 | */ |
| AnnaBridge | 163:e59c8e839560 | 443 | __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) |
| AnnaBridge | 163:e59c8e839560 | 444 | { |
| AnnaBridge | 163:e59c8e839560 | 445 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); |
| AnnaBridge | 163:e59c8e839560 | 446 | } |
| AnnaBridge | 163:e59c8e839560 | 447 | |
| AnnaBridge | 163:e59c8e839560 | 448 | /** |
| AnnaBridge | 163:e59c8e839560 | 449 | * @brief Get Variant number (The r value in the rnpn product revision identifier) |
| AnnaBridge | 163:e59c8e839560 | 450 | * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant |
| AnnaBridge | 163:e59c8e839560 | 451 | * @retval Value between 0 and 255 (0x0: revision 0) |
| AnnaBridge | 163:e59c8e839560 | 452 | */ |
| AnnaBridge | 163:e59c8e839560 | 453 | __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) |
| AnnaBridge | 163:e59c8e839560 | 454 | { |
| AnnaBridge | 163:e59c8e839560 | 455 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); |
| AnnaBridge | 163:e59c8e839560 | 456 | } |
| AnnaBridge | 163:e59c8e839560 | 457 | |
| AnnaBridge | 163:e59c8e839560 | 458 | /** |
| AnnaBridge | 163:e59c8e839560 | 459 | * @brief Get Constant number |
| AnnaBridge | 163:e59c8e839560 | 460 | * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant |
| AnnaBridge | 163:e59c8e839560 | 461 | * @retval Value should be equal to 0xF for Cortex-M4 devices |
| AnnaBridge | 163:e59c8e839560 | 462 | */ |
| AnnaBridge | 163:e59c8e839560 | 463 | __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) |
| AnnaBridge | 163:e59c8e839560 | 464 | { |
| AnnaBridge | 163:e59c8e839560 | 465 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); |
| AnnaBridge | 163:e59c8e839560 | 466 | } |
| AnnaBridge | 163:e59c8e839560 | 467 | |
| AnnaBridge | 163:e59c8e839560 | 468 | /** |
| AnnaBridge | 163:e59c8e839560 | 469 | * @brief Get Part number |
| AnnaBridge | 163:e59c8e839560 | 470 | * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo |
| AnnaBridge | 163:e59c8e839560 | 471 | * @retval Value should be equal to 0xC24 for Cortex-M4 |
| AnnaBridge | 163:e59c8e839560 | 472 | */ |
| AnnaBridge | 163:e59c8e839560 | 473 | __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) |
| AnnaBridge | 163:e59c8e839560 | 474 | { |
| AnnaBridge | 163:e59c8e839560 | 475 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); |
| AnnaBridge | 163:e59c8e839560 | 476 | } |
| AnnaBridge | 163:e59c8e839560 | 477 | |
| AnnaBridge | 163:e59c8e839560 | 478 | /** |
| AnnaBridge | 163:e59c8e839560 | 479 | * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) |
| AnnaBridge | 163:e59c8e839560 | 480 | * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision |
| AnnaBridge | 163:e59c8e839560 | 481 | * @retval Value between 0 and 255 (0x1: patch 1) |
| AnnaBridge | 163:e59c8e839560 | 482 | */ |
| AnnaBridge | 163:e59c8e839560 | 483 | __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) |
| AnnaBridge | 163:e59c8e839560 | 484 | { |
| AnnaBridge | 163:e59c8e839560 | 485 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); |
| AnnaBridge | 163:e59c8e839560 | 486 | } |
| AnnaBridge | 163:e59c8e839560 | 487 | |
| AnnaBridge | 163:e59c8e839560 | 488 | /** |
| AnnaBridge | 163:e59c8e839560 | 489 | * @} |
| AnnaBridge | 163:e59c8e839560 | 490 | */ |
| AnnaBridge | 163:e59c8e839560 | 491 | |
| AnnaBridge | 163:e59c8e839560 | 492 | #if __MPU_PRESENT |
| AnnaBridge | 163:e59c8e839560 | 493 | /** @defgroup CORTEX_LL_EF_MPU MPU |
| AnnaBridge | 163:e59c8e839560 | 494 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 495 | */ |
| AnnaBridge | 163:e59c8e839560 | 496 | |
| AnnaBridge | 163:e59c8e839560 | 497 | /** |
| AnnaBridge | 163:e59c8e839560 | 498 | * @brief Enable MPU with input options |
| AnnaBridge | 163:e59c8e839560 | 499 | * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable |
| AnnaBridge | 163:e59c8e839560 | 500 | * @param Options This parameter can be one of the following values: |
| AnnaBridge | 163:e59c8e839560 | 501 | * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE |
| AnnaBridge | 163:e59c8e839560 | 502 | * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI |
| AnnaBridge | 163:e59c8e839560 | 503 | * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT |
| AnnaBridge | 163:e59c8e839560 | 504 | * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF |
| AnnaBridge | 163:e59c8e839560 | 505 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 506 | */ |
| AnnaBridge | 163:e59c8e839560 | 507 | __STATIC_INLINE void LL_MPU_Enable(uint32_t Options) |
| AnnaBridge | 163:e59c8e839560 | 508 | { |
| AnnaBridge | 163:e59c8e839560 | 509 | /* Enable the MPU*/ |
| AnnaBridge | 163:e59c8e839560 | 510 | WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); |
| AnnaBridge | 163:e59c8e839560 | 511 | /* Ensure MPU settings take effects */ |
| AnnaBridge | 163:e59c8e839560 | 512 | __DSB(); |
| AnnaBridge | 163:e59c8e839560 | 513 | /* Sequence instruction fetches using update settings */ |
| AnnaBridge | 163:e59c8e839560 | 514 | __ISB(); |
| AnnaBridge | 163:e59c8e839560 | 515 | } |
| AnnaBridge | 163:e59c8e839560 | 516 | |
| AnnaBridge | 163:e59c8e839560 | 517 | /** |
| AnnaBridge | 163:e59c8e839560 | 518 | * @brief Disable MPU |
| AnnaBridge | 163:e59c8e839560 | 519 | * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable |
| AnnaBridge | 163:e59c8e839560 | 520 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 521 | */ |
| AnnaBridge | 163:e59c8e839560 | 522 | __STATIC_INLINE void LL_MPU_Disable(void) |
| AnnaBridge | 163:e59c8e839560 | 523 | { |
| AnnaBridge | 163:e59c8e839560 | 524 | /* Make sure outstanding transfers are done */ |
| AnnaBridge | 163:e59c8e839560 | 525 | __DMB(); |
| AnnaBridge | 163:e59c8e839560 | 526 | /* Disable MPU*/ |
| AnnaBridge | 163:e59c8e839560 | 527 | WRITE_REG(MPU->CTRL, 0U); |
| AnnaBridge | 163:e59c8e839560 | 528 | } |
| AnnaBridge | 163:e59c8e839560 | 529 | |
| AnnaBridge | 163:e59c8e839560 | 530 | /** |
| AnnaBridge | 163:e59c8e839560 | 531 | * @brief Check if MPU is enabled or not |
| AnnaBridge | 163:e59c8e839560 | 532 | * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled |
| AnnaBridge | 163:e59c8e839560 | 533 | * @retval State of bit (1 or 0). |
| AnnaBridge | 163:e59c8e839560 | 534 | */ |
| AnnaBridge | 163:e59c8e839560 | 535 | __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) |
| AnnaBridge | 163:e59c8e839560 | 536 | { |
| AnnaBridge | 163:e59c8e839560 | 537 | return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); |
| AnnaBridge | 163:e59c8e839560 | 538 | } |
| AnnaBridge | 163:e59c8e839560 | 539 | |
| AnnaBridge | 163:e59c8e839560 | 540 | /** |
| AnnaBridge | 163:e59c8e839560 | 541 | * @brief Enable a MPU region |
| AnnaBridge | 163:e59c8e839560 | 542 | * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion |
| AnnaBridge | 163:e59c8e839560 | 543 | * @param Region This parameter can be one of the following values: |
| AnnaBridge | 163:e59c8e839560 | 544 | * @arg @ref LL_MPU_REGION_NUMBER0 |
| AnnaBridge | 163:e59c8e839560 | 545 | * @arg @ref LL_MPU_REGION_NUMBER1 |
| AnnaBridge | 163:e59c8e839560 | 546 | * @arg @ref LL_MPU_REGION_NUMBER2 |
| AnnaBridge | 163:e59c8e839560 | 547 | * @arg @ref LL_MPU_REGION_NUMBER3 |
| AnnaBridge | 163:e59c8e839560 | 548 | * @arg @ref LL_MPU_REGION_NUMBER4 |
| AnnaBridge | 163:e59c8e839560 | 549 | * @arg @ref LL_MPU_REGION_NUMBER5 |
| AnnaBridge | 163:e59c8e839560 | 550 | * @arg @ref LL_MPU_REGION_NUMBER6 |
| AnnaBridge | 163:e59c8e839560 | 551 | * @arg @ref LL_MPU_REGION_NUMBER7 |
| AnnaBridge | 163:e59c8e839560 | 552 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 553 | */ |
| AnnaBridge | 163:e59c8e839560 | 554 | __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) |
| AnnaBridge | 163:e59c8e839560 | 555 | { |
| AnnaBridge | 163:e59c8e839560 | 556 | /* Set Region number */ |
| AnnaBridge | 163:e59c8e839560 | 557 | WRITE_REG(MPU->RNR, Region); |
| AnnaBridge | 163:e59c8e839560 | 558 | /* Enable the MPU region */ |
| AnnaBridge | 163:e59c8e839560 | 559 | SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); |
| AnnaBridge | 163:e59c8e839560 | 560 | } |
| AnnaBridge | 163:e59c8e839560 | 561 | |
| AnnaBridge | 163:e59c8e839560 | 562 | /** |
| AnnaBridge | 163:e59c8e839560 | 563 | * @brief Configure and enable a region |
| AnnaBridge | 163:e59c8e839560 | 564 | * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n |
| AnnaBridge | 163:e59c8e839560 | 565 | * MPU_RBAR REGION LL_MPU_ConfigRegion\n |
| AnnaBridge | 163:e59c8e839560 | 566 | * MPU_RBAR ADDR LL_MPU_ConfigRegion\n |
| AnnaBridge | 163:e59c8e839560 | 567 | * MPU_RASR XN LL_MPU_ConfigRegion\n |
| AnnaBridge | 163:e59c8e839560 | 568 | * MPU_RASR AP LL_MPU_ConfigRegion\n |
| AnnaBridge | 163:e59c8e839560 | 569 | * MPU_RASR S LL_MPU_ConfigRegion\n |
| AnnaBridge | 163:e59c8e839560 | 570 | * MPU_RASR C LL_MPU_ConfigRegion\n |
| AnnaBridge | 163:e59c8e839560 | 571 | * MPU_RASR B LL_MPU_ConfigRegion\n |
| AnnaBridge | 163:e59c8e839560 | 572 | * MPU_RASR SIZE LL_MPU_ConfigRegion |
| AnnaBridge | 163:e59c8e839560 | 573 | * @param Region This parameter can be one of the following values: |
| AnnaBridge | 163:e59c8e839560 | 574 | * @arg @ref LL_MPU_REGION_NUMBER0 |
| AnnaBridge | 163:e59c8e839560 | 575 | * @arg @ref LL_MPU_REGION_NUMBER1 |
| AnnaBridge | 163:e59c8e839560 | 576 | * @arg @ref LL_MPU_REGION_NUMBER2 |
| AnnaBridge | 163:e59c8e839560 | 577 | * @arg @ref LL_MPU_REGION_NUMBER3 |
| AnnaBridge | 163:e59c8e839560 | 578 | * @arg @ref LL_MPU_REGION_NUMBER4 |
| AnnaBridge | 163:e59c8e839560 | 579 | * @arg @ref LL_MPU_REGION_NUMBER5 |
| AnnaBridge | 163:e59c8e839560 | 580 | * @arg @ref LL_MPU_REGION_NUMBER6 |
| AnnaBridge | 163:e59c8e839560 | 581 | * @arg @ref LL_MPU_REGION_NUMBER7 |
| AnnaBridge | 163:e59c8e839560 | 582 | * @param Address Value of region base address |
| AnnaBridge | 163:e59c8e839560 | 583 | * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF |
| AnnaBridge | 163:e59c8e839560 | 584 | * @param Attributes This parameter can be a combination of the following values: |
| AnnaBridge | 163:e59c8e839560 | 585 | * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B |
| AnnaBridge | 163:e59c8e839560 | 586 | * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB |
| AnnaBridge | 163:e59c8e839560 | 587 | * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB |
| AnnaBridge | 163:e59c8e839560 | 588 | * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB |
| AnnaBridge | 163:e59c8e839560 | 589 | * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB |
| AnnaBridge | 163:e59c8e839560 | 590 | * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB |
| AnnaBridge | 163:e59c8e839560 | 591 | * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS |
| AnnaBridge | 163:e59c8e839560 | 592 | * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO |
| AnnaBridge | 163:e59c8e839560 | 593 | * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 |
| AnnaBridge | 163:e59c8e839560 | 594 | * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE |
| AnnaBridge | 163:e59c8e839560 | 595 | * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE |
| AnnaBridge | 163:e59c8e839560 | 596 | * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE |
| AnnaBridge | 163:e59c8e839560 | 597 | * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE |
| AnnaBridge | 163:e59c8e839560 | 598 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 599 | */ |
| AnnaBridge | 163:e59c8e839560 | 600 | __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) |
| AnnaBridge | 163:e59c8e839560 | 601 | { |
| AnnaBridge | 163:e59c8e839560 | 602 | /* Set Region number */ |
| AnnaBridge | 163:e59c8e839560 | 603 | WRITE_REG(MPU->RNR, Region); |
| AnnaBridge | 163:e59c8e839560 | 604 | /* Set base address */ |
| AnnaBridge | 163:e59c8e839560 | 605 | WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); |
| AnnaBridge | 163:e59c8e839560 | 606 | /* Configure MPU */ |
| AnnaBridge | 163:e59c8e839560 | 607 | WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); |
| AnnaBridge | 163:e59c8e839560 | 608 | } |
| AnnaBridge | 163:e59c8e839560 | 609 | |
| AnnaBridge | 163:e59c8e839560 | 610 | /** |
| AnnaBridge | 163:e59c8e839560 | 611 | * @brief Disable a region |
| AnnaBridge | 163:e59c8e839560 | 612 | * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n |
| AnnaBridge | 163:e59c8e839560 | 613 | * MPU_RASR ENABLE LL_MPU_DisableRegion |
| AnnaBridge | 163:e59c8e839560 | 614 | * @param Region This parameter can be one of the following values: |
| AnnaBridge | 163:e59c8e839560 | 615 | * @arg @ref LL_MPU_REGION_NUMBER0 |
| AnnaBridge | 163:e59c8e839560 | 616 | * @arg @ref LL_MPU_REGION_NUMBER1 |
| AnnaBridge | 163:e59c8e839560 | 617 | * @arg @ref LL_MPU_REGION_NUMBER2 |
| AnnaBridge | 163:e59c8e839560 | 618 | * @arg @ref LL_MPU_REGION_NUMBER3 |
| AnnaBridge | 163:e59c8e839560 | 619 | * @arg @ref LL_MPU_REGION_NUMBER4 |
| AnnaBridge | 163:e59c8e839560 | 620 | * @arg @ref LL_MPU_REGION_NUMBER5 |
| AnnaBridge | 163:e59c8e839560 | 621 | * @arg @ref LL_MPU_REGION_NUMBER6 |
| AnnaBridge | 163:e59c8e839560 | 622 | * @arg @ref LL_MPU_REGION_NUMBER7 |
| AnnaBridge | 163:e59c8e839560 | 623 | * @retval None |
| AnnaBridge | 163:e59c8e839560 | 624 | */ |
| AnnaBridge | 163:e59c8e839560 | 625 | __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) |
| AnnaBridge | 163:e59c8e839560 | 626 | { |
| AnnaBridge | 163:e59c8e839560 | 627 | /* Set Region number */ |
| AnnaBridge | 163:e59c8e839560 | 628 | WRITE_REG(MPU->RNR, Region); |
| AnnaBridge | 163:e59c8e839560 | 629 | /* Disable the MPU region */ |
| AnnaBridge | 163:e59c8e839560 | 630 | CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); |
| AnnaBridge | 163:e59c8e839560 | 631 | } |
| AnnaBridge | 163:e59c8e839560 | 632 | |
| AnnaBridge | 163:e59c8e839560 | 633 | /** |
| AnnaBridge | 163:e59c8e839560 | 634 | * @} |
| AnnaBridge | 163:e59c8e839560 | 635 | */ |
| AnnaBridge | 163:e59c8e839560 | 636 | |
| AnnaBridge | 163:e59c8e839560 | 637 | #endif /* __MPU_PRESENT */ |
| AnnaBridge | 163:e59c8e839560 | 638 | /** |
| AnnaBridge | 163:e59c8e839560 | 639 | * @} |
| AnnaBridge | 163:e59c8e839560 | 640 | */ |
| AnnaBridge | 163:e59c8e839560 | 641 | |
| AnnaBridge | 163:e59c8e839560 | 642 | /** |
| AnnaBridge | 163:e59c8e839560 | 643 | * @} |
| AnnaBridge | 163:e59c8e839560 | 644 | */ |
| AnnaBridge | 163:e59c8e839560 | 645 | |
| AnnaBridge | 163:e59c8e839560 | 646 | /** |
| AnnaBridge | 163:e59c8e839560 | 647 | * @} |
| AnnaBridge | 163:e59c8e839560 | 648 | */ |
| AnnaBridge | 163:e59c8e839560 | 649 | |
| AnnaBridge | 163:e59c8e839560 | 650 | #ifdef __cplusplus |
| AnnaBridge | 163:e59c8e839560 | 651 | } |
| AnnaBridge | 163:e59c8e839560 | 652 | #endif |
| AnnaBridge | 163:e59c8e839560 | 653 | |
| AnnaBridge | 163:e59c8e839560 | 654 | #endif /* __STM32F3xx_LL_CORTEX_H */ |
| AnnaBridge | 163:e59c8e839560 | 655 | |
| AnnaBridge | 163:e59c8e839560 | 656 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
