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TARGET_NUCLEO_F207ZG/TOOLCHAIN_IAR/stm32f2xx_hal_eth.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32f2xx_hal_eth.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @version V1.2.1
AnnaBridge	171:3a7713b1edbc	6	* @date 14-April-2017
AnnaBridge	171:3a7713b1edbc	7	* @brief Header file of ETH HAL module.
AnnaBridge	171:3a7713b1edbc	8	******************************************************************************
AnnaBridge	171:3a7713b1edbc	9	* @attention
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	12	*
AnnaBridge	171:3a7713b1edbc	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	14	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	16	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	19	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	21	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	22	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	23	*
AnnaBridge	171:3a7713b1edbc	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	34	*
AnnaBridge	171:3a7713b1edbc	35	******************************************************************************
AnnaBridge	171:3a7713b1edbc	36	*/
AnnaBridge	171:3a7713b1edbc	37
AnnaBridge	171:3a7713b1edbc	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	39	#ifndef __STM32F2xx_HAL_ETH_H
AnnaBridge	171:3a7713b1edbc	40	#define __STM32F2xx_HAL_ETH_H
AnnaBridge	171:3a7713b1edbc	41
AnnaBridge	171:3a7713b1edbc	42	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	43	extern "C" {
AnnaBridge	171:3a7713b1edbc	44	#endif
AnnaBridge	171:3a7713b1edbc	45
AnnaBridge	171:3a7713b1edbc	46	#if defined(STM32F207xx) \|\| defined(STM32F217xx)
AnnaBridge	171:3a7713b1edbc	47	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	48	#include "stm32f2xx_hal_def.h"
AnnaBridge	171:3a7713b1edbc	49
AnnaBridge	171:3a7713b1edbc	50	/** @addtogroup STM32F2xx_HAL_Driver
AnnaBridge	171:3a7713b1edbc	51	* @{
AnnaBridge	171:3a7713b1edbc	52	*/
AnnaBridge	171:3a7713b1edbc	53
AnnaBridge	171:3a7713b1edbc	54	/** @addtogroup ETH
AnnaBridge	171:3a7713b1edbc	55	* @{
AnnaBridge	171:3a7713b1edbc	56	*/
AnnaBridge	171:3a7713b1edbc	57
AnnaBridge	171:3a7713b1edbc	58	/** @defgroup ETH_Private_Macros ETH Private Macros
AnnaBridge	171:3a7713b1edbc	59	* @{
AnnaBridge	171:3a7713b1edbc	60	*/
AnnaBridge	171:3a7713b1edbc	61	#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
AnnaBridge	171:3a7713b1edbc	62	#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	63	((CMD) == ETH_AUTONEGOTIATION_DISABLE))
AnnaBridge	171:3a7713b1edbc	64	#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) \|\| \
AnnaBridge	171:3a7713b1edbc	65	((SPEED) == ETH_SPEED_100M))
AnnaBridge	171:3a7713b1edbc	66	#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) \|\| \
AnnaBridge	171:3a7713b1edbc	67	((MODE) == ETH_MODE_HALFDUPLEX))
AnnaBridge	171:3a7713b1edbc	68	#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) \|\| \
AnnaBridge	171:3a7713b1edbc	69	((MODE) == ETH_RXINTERRUPT_MODE))
AnnaBridge	171:3a7713b1edbc	70	#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) \|\| \
AnnaBridge	171:3a7713b1edbc	71	((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
AnnaBridge	171:3a7713b1edbc	72	#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) \|\| \
AnnaBridge	171:3a7713b1edbc	73	((MODE) == ETH_MEDIA_INTERFACE_RMII))
AnnaBridge	171:3a7713b1edbc	74	#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	75	((CMD) == ETH_WATCHDOG_DISABLE))
AnnaBridge	171:3a7713b1edbc	76	#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	77	((CMD) == ETH_JABBER_DISABLE))
AnnaBridge	171:3a7713b1edbc	78	#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) \|\| \
AnnaBridge	171:3a7713b1edbc	79	((GAP) == ETH_INTERFRAMEGAP_88BIT) \|\| \
AnnaBridge	171:3a7713b1edbc	80	((GAP) == ETH_INTERFRAMEGAP_80BIT) \|\| \
AnnaBridge	171:3a7713b1edbc	81	((GAP) == ETH_INTERFRAMEGAP_72BIT) \|\| \
AnnaBridge	171:3a7713b1edbc	82	((GAP) == ETH_INTERFRAMEGAP_64BIT) \|\| \
AnnaBridge	171:3a7713b1edbc	83	((GAP) == ETH_INTERFRAMEGAP_56BIT) \|\| \
AnnaBridge	171:3a7713b1edbc	84	((GAP) == ETH_INTERFRAMEGAP_48BIT) \|\| \
AnnaBridge	171:3a7713b1edbc	85	((GAP) == ETH_INTERFRAMEGAP_40BIT))
AnnaBridge	171:3a7713b1edbc	86	#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	87	((CMD) == ETH_CARRIERSENCE_DISABLE))
AnnaBridge	171:3a7713b1edbc	88	#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	89	((CMD) == ETH_RECEIVEOWN_DISABLE))
AnnaBridge	171:3a7713b1edbc	90	#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	91	((CMD) == ETH_LOOPBACKMODE_DISABLE))
AnnaBridge	171:3a7713b1edbc	92	#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	93	((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
AnnaBridge	171:3a7713b1edbc	94	#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	95	((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
AnnaBridge	171:3a7713b1edbc	96	#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	97	((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
AnnaBridge	171:3a7713b1edbc	98	#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) \|\| \
AnnaBridge	171:3a7713b1edbc	99	((LIMIT) == ETH_BACKOFFLIMIT_8) \|\| \
AnnaBridge	171:3a7713b1edbc	100	((LIMIT) == ETH_BACKOFFLIMIT_4) \|\| \
AnnaBridge	171:3a7713b1edbc	101	((LIMIT) == ETH_BACKOFFLIMIT_1))
AnnaBridge	171:3a7713b1edbc	102	#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	103	((CMD) == ETH_DEFFERRALCHECK_DISABLE))
AnnaBridge	171:3a7713b1edbc	104	#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	105	((CMD) == ETH_RECEIVEAll_DISABLE))
AnnaBridge	171:3a7713b1edbc	106	#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	107	((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	108	((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
AnnaBridge	171:3a7713b1edbc	109	#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) \|\| \
AnnaBridge	171:3a7713b1edbc	110	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) \|\| \
AnnaBridge	171:3a7713b1edbc	111	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
AnnaBridge	171:3a7713b1edbc	112	#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	113	((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
AnnaBridge	171:3a7713b1edbc	114	#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) \|\| \
AnnaBridge	171:3a7713b1edbc	115	((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
AnnaBridge	171:3a7713b1edbc	116	#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	117	((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
AnnaBridge	171:3a7713b1edbc	118	#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	119	((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	120	((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) \|\| \
AnnaBridge	171:3a7713b1edbc	121	((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
AnnaBridge	171:3a7713b1edbc	122	#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	123	((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	124	((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
AnnaBridge	171:3a7713b1edbc	125	#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
AnnaBridge	171:3a7713b1edbc	126	#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	127	((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
AnnaBridge	171:3a7713b1edbc	128	#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) \|\| \
AnnaBridge	171:3a7713b1edbc	129	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) \|\| \
AnnaBridge	171:3a7713b1edbc	130	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) \|\| \
AnnaBridge	171:3a7713b1edbc	131	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
AnnaBridge	171:3a7713b1edbc	132	#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	133	((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
AnnaBridge	171:3a7713b1edbc	134	#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	135	((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
AnnaBridge	171:3a7713b1edbc	136	#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	137	((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
AnnaBridge	171:3a7713b1edbc	138	#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) \|\| \
AnnaBridge	171:3a7713b1edbc	139	((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
AnnaBridge	171:3a7713b1edbc	140	#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
AnnaBridge	171:3a7713b1edbc	141	#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) \|\| \
AnnaBridge	171:3a7713b1edbc	142	((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
AnnaBridge	171:3a7713b1edbc	143	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
AnnaBridge	171:3a7713b1edbc	144	((ADDRESS) == ETH_MAC_ADDRESS3))
AnnaBridge	171:3a7713b1edbc	145	#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
AnnaBridge	171:3a7713b1edbc	146	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
AnnaBridge	171:3a7713b1edbc	147	((ADDRESS) == ETH_MAC_ADDRESS3))
AnnaBridge	171:3a7713b1edbc	148	#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) \|\| \
AnnaBridge	171:3a7713b1edbc	149	((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
AnnaBridge	171:3a7713b1edbc	150	#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) \|\| \
AnnaBridge	171:3a7713b1edbc	151	((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) \|\| \
AnnaBridge	171:3a7713b1edbc	152	((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) \|\| \
AnnaBridge	171:3a7713b1edbc	153	((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) \|\| \
AnnaBridge	171:3a7713b1edbc	154	((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) \|\| \
AnnaBridge	171:3a7713b1edbc	155	((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
AnnaBridge	171:3a7713b1edbc	156	#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	157	((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
AnnaBridge	171:3a7713b1edbc	158	#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	159	((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
AnnaBridge	171:3a7713b1edbc	160	#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	161	((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
AnnaBridge	171:3a7713b1edbc	162	#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	163	((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
AnnaBridge	171:3a7713b1edbc	164	#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) \|\| \
AnnaBridge	171:3a7713b1edbc	165	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) \|\| \
AnnaBridge	171:3a7713b1edbc	166	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) \|\| \
AnnaBridge	171:3a7713b1edbc	167	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) \|\| \
AnnaBridge	171:3a7713b1edbc	168	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) \|\| \
AnnaBridge	171:3a7713b1edbc	169	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) \|\| \
AnnaBridge	171:3a7713b1edbc	170	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) \|\| \
AnnaBridge	171:3a7713b1edbc	171	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
AnnaBridge	171:3a7713b1edbc	172	#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	173	((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
AnnaBridge	171:3a7713b1edbc	174	#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	175	((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
AnnaBridge	171:3a7713b1edbc	176	#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) \|\| \
AnnaBridge	171:3a7713b1edbc	177	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) \|\| \
AnnaBridge	171:3a7713b1edbc	178	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) \|\| \
AnnaBridge	171:3a7713b1edbc	179	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
AnnaBridge	171:3a7713b1edbc	180	#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	181	((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
AnnaBridge	171:3a7713b1edbc	182	#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	183	((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
AnnaBridge	171:3a7713b1edbc	184	#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	185	((CMD) == ETH_FIXEDBURST_DISABLE))
AnnaBridge	171:3a7713b1edbc	186	#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	187	((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	188	((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	189	((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	190	((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	191	((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	192	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	193	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	194	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	195	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	196	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	197	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
AnnaBridge	171:3a7713b1edbc	198	#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	199	((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	200	((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	201	((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	202	((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	203	((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	204	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	205	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	206	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	207	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	208	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
AnnaBridge	171:3a7713b1edbc	209	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
AnnaBridge	171:3a7713b1edbc	210	#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
AnnaBridge	171:3a7713b1edbc	211	#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) \|\| \
AnnaBridge	171:3a7713b1edbc	212	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) \|\| \
AnnaBridge	171:3a7713b1edbc	213	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) \|\| \
AnnaBridge	171:3a7713b1edbc	214	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) \|\| \
AnnaBridge	171:3a7713b1edbc	215	((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
AnnaBridge	171:3a7713b1edbc	216	#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) \|\| \
AnnaBridge	171:3a7713b1edbc	217	((FLAG) == ETH_DMATXDESC_IC) \|\| \
AnnaBridge	171:3a7713b1edbc	218	((FLAG) == ETH_DMATXDESC_LS) \|\| \
AnnaBridge	171:3a7713b1edbc	219	((FLAG) == ETH_DMATXDESC_FS) \|\| \
AnnaBridge	171:3a7713b1edbc	220	((FLAG) == ETH_DMATXDESC_DC) \|\| \
AnnaBridge	171:3a7713b1edbc	221	((FLAG) == ETH_DMATXDESC_DP) \|\| \
AnnaBridge	171:3a7713b1edbc	222	((FLAG) == ETH_DMATXDESC_TTSE) \|\| \
AnnaBridge	171:3a7713b1edbc	223	((FLAG) == ETH_DMATXDESC_TER) \|\| \
AnnaBridge	171:3a7713b1edbc	224	((FLAG) == ETH_DMATXDESC_TCH) \|\| \
AnnaBridge	171:3a7713b1edbc	225	((FLAG) == ETH_DMATXDESC_TTSS) \|\| \
AnnaBridge	171:3a7713b1edbc	226	((FLAG) == ETH_DMATXDESC_IHE) \|\| \
AnnaBridge	171:3a7713b1edbc	227	((FLAG) == ETH_DMATXDESC_ES) \|\| \
AnnaBridge	171:3a7713b1edbc	228	((FLAG) == ETH_DMATXDESC_JT) \|\| \
AnnaBridge	171:3a7713b1edbc	229	((FLAG) == ETH_DMATXDESC_FF) \|\| \
AnnaBridge	171:3a7713b1edbc	230	((FLAG) == ETH_DMATXDESC_PCE) \|\| \
AnnaBridge	171:3a7713b1edbc	231	((FLAG) == ETH_DMATXDESC_LCA) \|\| \
AnnaBridge	171:3a7713b1edbc	232	((FLAG) == ETH_DMATXDESC_NC) \|\| \
AnnaBridge	171:3a7713b1edbc	233	((FLAG) == ETH_DMATXDESC_LCO) \|\| \
AnnaBridge	171:3a7713b1edbc	234	((FLAG) == ETH_DMATXDESC_EC) \|\| \
AnnaBridge	171:3a7713b1edbc	235	((FLAG) == ETH_DMATXDESC_VF) \|\| \
AnnaBridge	171:3a7713b1edbc	236	((FLAG) == ETH_DMATXDESC_CC) \|\| \
AnnaBridge	171:3a7713b1edbc	237	((FLAG) == ETH_DMATXDESC_ED) \|\| \
AnnaBridge	171:3a7713b1edbc	238	((FLAG) == ETH_DMATXDESC_UF) \|\| \
AnnaBridge	171:3a7713b1edbc	239	((FLAG) == ETH_DMATXDESC_DB))
AnnaBridge	171:3a7713b1edbc	240	#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) \|\| \
AnnaBridge	171:3a7713b1edbc	241	((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
AnnaBridge	171:3a7713b1edbc	242	#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) \|\| \
AnnaBridge	171:3a7713b1edbc	243	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) \|\| \
AnnaBridge	171:3a7713b1edbc	244	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) \|\| \
AnnaBridge	171:3a7713b1edbc	245	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
AnnaBridge	171:3a7713b1edbc	246	#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
AnnaBridge	171:3a7713b1edbc	247	#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) \|\| \
AnnaBridge	171:3a7713b1edbc	248	((FLAG) == ETH_DMARXDESC_AFM) \|\| \
AnnaBridge	171:3a7713b1edbc	249	((FLAG) == ETH_DMARXDESC_ES) \|\| \
AnnaBridge	171:3a7713b1edbc	250	((FLAG) == ETH_DMARXDESC_DE) \|\| \
AnnaBridge	171:3a7713b1edbc	251	((FLAG) == ETH_DMARXDESC_SAF) \|\| \
AnnaBridge	171:3a7713b1edbc	252	((FLAG) == ETH_DMARXDESC_LE) \|\| \
AnnaBridge	171:3a7713b1edbc	253	((FLAG) == ETH_DMARXDESC_OE) \|\| \
AnnaBridge	171:3a7713b1edbc	254	((FLAG) == ETH_DMARXDESC_VLAN) \|\| \
AnnaBridge	171:3a7713b1edbc	255	((FLAG) == ETH_DMARXDESC_FS) \|\| \
AnnaBridge	171:3a7713b1edbc	256	((FLAG) == ETH_DMARXDESC_LS) \|\| \
AnnaBridge	171:3a7713b1edbc	257	((FLAG) == ETH_DMARXDESC_IPV4HCE) \|\| \
AnnaBridge	171:3a7713b1edbc	258	((FLAG) == ETH_DMARXDESC_LC) \|\| \
AnnaBridge	171:3a7713b1edbc	259	((FLAG) == ETH_DMARXDESC_FT) \|\| \
AnnaBridge	171:3a7713b1edbc	260	((FLAG) == ETH_DMARXDESC_RWT) \|\| \
AnnaBridge	171:3a7713b1edbc	261	((FLAG) == ETH_DMARXDESC_RE) \|\| \
AnnaBridge	171:3a7713b1edbc	262	((FLAG) == ETH_DMARXDESC_DBE) \|\| \
AnnaBridge	171:3a7713b1edbc	263	((FLAG) == ETH_DMARXDESC_CE) \|\| \
AnnaBridge	171:3a7713b1edbc	264	((FLAG) == ETH_DMARXDESC_MAMPCE))
AnnaBridge	171:3a7713b1edbc	265	#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) \|\| \
AnnaBridge	171:3a7713b1edbc	266	((BUFFER) == ETH_DMARXDESC_BUFFER2))
AnnaBridge	171:3a7713b1edbc	267	#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) \|\| \
AnnaBridge	171:3a7713b1edbc	268	((FLAG) == ETH_PMT_FLAG_MPR))
AnnaBridge	171:3a7713b1edbc	269	#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
AnnaBridge	171:3a7713b1edbc	270	#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) \|\| ((FLAG) == ETH_DMA_FLAG_PMT) \|\| \
AnnaBridge	171:3a7713b1edbc	271	((FLAG) == ETH_DMA_FLAG_MMC) \|\| ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) \|\| \
AnnaBridge	171:3a7713b1edbc	272	((FLAG) == ETH_DMA_FLAG_READWRITEERROR) \|\| ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) \|\| \
AnnaBridge	171:3a7713b1edbc	273	((FLAG) == ETH_DMA_FLAG_NIS) \|\| ((FLAG) == ETH_DMA_FLAG_AIS) \|\| \
AnnaBridge	171:3a7713b1edbc	274	((FLAG) == ETH_DMA_FLAG_ER) \|\| ((FLAG) == ETH_DMA_FLAG_FBE) \|\| \
AnnaBridge	171:3a7713b1edbc	275	((FLAG) == ETH_DMA_FLAG_ET) \|\| ((FLAG) == ETH_DMA_FLAG_RWT) \|\| \
AnnaBridge	171:3a7713b1edbc	276	((FLAG) == ETH_DMA_FLAG_RPS) \|\| ((FLAG) == ETH_DMA_FLAG_RBU) \|\| \
AnnaBridge	171:3a7713b1edbc	277	((FLAG) == ETH_DMA_FLAG_R) \|\| ((FLAG) == ETH_DMA_FLAG_TU) \|\| \
AnnaBridge	171:3a7713b1edbc	278	((FLAG) == ETH_DMA_FLAG_RO) \|\| ((FLAG) == ETH_DMA_FLAG_TJT) \|\| \
AnnaBridge	171:3a7713b1edbc	279	((FLAG) == ETH_DMA_FLAG_TBU) \|\| ((FLAG) == ETH_DMA_FLAG_TPS) \|\| \
AnnaBridge	171:3a7713b1edbc	280	((FLAG) == ETH_DMA_FLAG_T))
AnnaBridge	171:3a7713b1edbc	281	#define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFD87U) == 0x00U) && ((IT) != 0x00U))
AnnaBridge	171:3a7713b1edbc	282	#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) \|\| ((IT) == ETH_MAC_IT_MMCT) \|\| \
AnnaBridge	171:3a7713b1edbc	283	((IT) == ETH_MAC_IT_MMCR) \|\| ((IT) == ETH_MAC_IT_MMC) \|\| \
AnnaBridge	171:3a7713b1edbc	284	((IT) == ETH_MAC_IT_PMT))
AnnaBridge	171:3a7713b1edbc	285	#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) \|\| ((FLAG) == ETH_MAC_FLAG_MMCT) \|\| \
AnnaBridge	171:3a7713b1edbc	286	((FLAG) == ETH_MAC_FLAG_MMCR) \|\| ((FLAG) == ETH_MAC_FLAG_MMC) \|\| \
AnnaBridge	171:3a7713b1edbc	287	((FLAG) == ETH_MAC_FLAG_PMT))
AnnaBridge	171:3a7713b1edbc	288	#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
AnnaBridge	171:3a7713b1edbc	289	#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) \|\| ((IT) == ETH_DMA_IT_PMT) \|\| \
AnnaBridge	171:3a7713b1edbc	290	((IT) == ETH_DMA_IT_MMC) \|\| ((IT) == ETH_DMA_IT_NIS) \|\| \
AnnaBridge	171:3a7713b1edbc	291	((IT) == ETH_DMA_IT_AIS) \|\| ((IT) == ETH_DMA_IT_ER) \|\| \
AnnaBridge	171:3a7713b1edbc	292	((IT) == ETH_DMA_IT_FBE) \|\| ((IT) == ETH_DMA_IT_ET) \|\| \
AnnaBridge	171:3a7713b1edbc	293	((IT) == ETH_DMA_IT_RWT) \|\| ((IT) == ETH_DMA_IT_RPS) \|\| \
AnnaBridge	171:3a7713b1edbc	294	((IT) == ETH_DMA_IT_RBU) \|\| ((IT) == ETH_DMA_IT_R) \|\| \
AnnaBridge	171:3a7713b1edbc	295	((IT) == ETH_DMA_IT_TU) \|\| ((IT) == ETH_DMA_IT_RO) \|\| \
AnnaBridge	171:3a7713b1edbc	296	((IT) == ETH_DMA_IT_TJT) \|\| ((IT) == ETH_DMA_IT_TBU) \|\| \
AnnaBridge	171:3a7713b1edbc	297	((IT) == ETH_DMA_IT_TPS) \|\| ((IT) == ETH_DMA_IT_T))
AnnaBridge	171:3a7713b1edbc	298	#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) \|\| \
AnnaBridge	171:3a7713b1edbc	299	((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
AnnaBridge	171:3a7713b1edbc	300	#define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFF) == 0x00U) \|\| (((IT) & 0xEFFDFF9FU) == 0x00U)) && \
AnnaBridge	171:3a7713b1edbc	301	((IT) != 0x00U))
AnnaBridge	171:3a7713b1edbc	302	#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) \|\| ((IT) == ETH_MMC_IT_TGFMSC) \|\| \
AnnaBridge	171:3a7713b1edbc	303	((IT) == ETH_MMC_IT_TGFSC) \|\| ((IT) == ETH_MMC_IT_RGUF) \|\| \
AnnaBridge	171:3a7713b1edbc	304	((IT) == ETH_MMC_IT_RFAE) \|\| ((IT) == ETH_MMC_IT_RFCE))
AnnaBridge	171:3a7713b1edbc	305	#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	306	((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
AnnaBridge	171:3a7713b1edbc	307
AnnaBridge	171:3a7713b1edbc	308
AnnaBridge	171:3a7713b1edbc	309	/**
AnnaBridge	171:3a7713b1edbc	310	* @}
AnnaBridge	171:3a7713b1edbc	311	*/
AnnaBridge	171:3a7713b1edbc	312
AnnaBridge	171:3a7713b1edbc	313	/** @defgroup ETH_Private_Defines ETH Private Defines
AnnaBridge	171:3a7713b1edbc	314	* @{
AnnaBridge	171:3a7713b1edbc	315	*/
AnnaBridge	171:3a7713b1edbc	316	/* Delay to wait when writing to some Ethernet registers */
AnnaBridge	171:3a7713b1edbc	317	#define ETH_REG_WRITE_DELAY 0x00000001U
AnnaBridge	171:3a7713b1edbc	318
AnnaBridge	171:3a7713b1edbc	319	/* ETHERNET Errors */
AnnaBridge	171:3a7713b1edbc	320	#define ETH_SUCCESS 0U
AnnaBridge	171:3a7713b1edbc	321	#define ETH_ERROR 1U
AnnaBridge	171:3a7713b1edbc	322
AnnaBridge	171:3a7713b1edbc	323	/* ETHERNET DMA Tx descriptors Collision Count Shift */
AnnaBridge	171:3a7713b1edbc	324	#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U
AnnaBridge	171:3a7713b1edbc	325
AnnaBridge	171:3a7713b1edbc	326	/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
AnnaBridge	171:3a7713b1edbc	327	#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U
AnnaBridge	171:3a7713b1edbc	328
AnnaBridge	171:3a7713b1edbc	329	/* ETHERNET DMA Rx descriptors Frame Length Shift */
AnnaBridge	171:3a7713b1edbc	330	#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U
AnnaBridge	171:3a7713b1edbc	331
AnnaBridge	171:3a7713b1edbc	332	/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
AnnaBridge	171:3a7713b1edbc	333	#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U
AnnaBridge	171:3a7713b1edbc	334
AnnaBridge	171:3a7713b1edbc	335	/* ETHERNET DMA Rx descriptors Frame length Shift */
AnnaBridge	171:3a7713b1edbc	336	#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U
AnnaBridge	171:3a7713b1edbc	337
AnnaBridge	171:3a7713b1edbc	338	/* ETHERNET MAC address offsets */
AnnaBridge	171:3a7713b1edbc	339	#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */
AnnaBridge	171:3a7713b1edbc	340	#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */
AnnaBridge	171:3a7713b1edbc	341
AnnaBridge	171:3a7713b1edbc	342	/* ETHERNET MACMIIAR register Mask */
AnnaBridge	171:3a7713b1edbc	343	#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U
AnnaBridge	171:3a7713b1edbc	344
AnnaBridge	171:3a7713b1edbc	345	/* ETHERNET MACCR register Mask */
AnnaBridge	171:3a7713b1edbc	346	#define ETH_MACCR_CLEAR_MASK 0xFF20810FU
AnnaBridge	171:3a7713b1edbc	347
AnnaBridge	171:3a7713b1edbc	348	/* ETHERNET MACFCR register Mask */
AnnaBridge	171:3a7713b1edbc	349	#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U
AnnaBridge	171:3a7713b1edbc	350
AnnaBridge	171:3a7713b1edbc	351	/* ETHERNET DMAOMR register Mask */
AnnaBridge	171:3a7713b1edbc	352	#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U
AnnaBridge	171:3a7713b1edbc	353
AnnaBridge	171:3a7713b1edbc	354	/* ETHERNET Remote Wake-up frame register length */
AnnaBridge	171:3a7713b1edbc	355	#define ETH_WAKEUP_REGISTER_LENGTH 8U
AnnaBridge	171:3a7713b1edbc	356
AnnaBridge	171:3a7713b1edbc	357	/* ETHERNET Missed frames counter Shift */
AnnaBridge	171:3a7713b1edbc	358	#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
AnnaBridge	171:3a7713b1edbc	359	/**
AnnaBridge	171:3a7713b1edbc	360	* @}
AnnaBridge	171:3a7713b1edbc	361	*/
AnnaBridge	171:3a7713b1edbc	362
AnnaBridge	171:3a7713b1edbc	363	/* Exported types ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	364	/** @defgroup ETH_Exported_Types ETH Exported Types
AnnaBridge	171:3a7713b1edbc	365	* @{
AnnaBridge	171:3a7713b1edbc	366	*/
AnnaBridge	171:3a7713b1edbc	367
AnnaBridge	171:3a7713b1edbc	368	/**
AnnaBridge	171:3a7713b1edbc	369	* @brief HAL State structures definition
AnnaBridge	171:3a7713b1edbc	370	*/
AnnaBridge	171:3a7713b1edbc	371	typedef enum
AnnaBridge	171:3a7713b1edbc	372	{
AnnaBridge	171:3a7713b1edbc	373	HAL_ETH_STATE_RESET = 0x00U, /!< Peripheral not yet Initialized or disabled /
AnnaBridge	171:3a7713b1edbc	374	HAL_ETH_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
AnnaBridge	171:3a7713b1edbc	375	HAL_ETH_STATE_BUSY = 0x02U, /!< an internal process is ongoing /
AnnaBridge	171:3a7713b1edbc	376	HAL_ETH_STATE_BUSY_TX = 0x12U, /!< Data Transmission process is ongoing /
AnnaBridge	171:3a7713b1edbc	377	HAL_ETH_STATE_BUSY_RX = 0x22U, /!< Data Reception process is ongoing /
AnnaBridge	171:3a7713b1edbc	378	HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /!< Data Transmission and Reception process is ongoing /
AnnaBridge	171:3a7713b1edbc	379	HAL_ETH_STATE_BUSY_WR = 0x42U, /!< Write process is ongoing /
AnnaBridge	171:3a7713b1edbc	380	HAL_ETH_STATE_BUSY_RD = 0x82U, /!< Read process is ongoing /
AnnaBridge	171:3a7713b1edbc	381	HAL_ETH_STATE_TIMEOUT = 0x03U, /!< Timeout state /
AnnaBridge	171:3a7713b1edbc	382	HAL_ETH_STATE_ERROR = 0x04U /!< Reception process is ongoing /
AnnaBridge	171:3a7713b1edbc	383	}HAL_ETH_StateTypeDef;
AnnaBridge	171:3a7713b1edbc	384
AnnaBridge	171:3a7713b1edbc	385	/**
AnnaBridge	171:3a7713b1edbc	386	* @brief ETH Init Structure definition
AnnaBridge	171:3a7713b1edbc	387	*/
AnnaBridge	171:3a7713b1edbc	388
AnnaBridge	171:3a7713b1edbc	389	typedef struct
AnnaBridge	171:3a7713b1edbc	390	{
AnnaBridge	171:3a7713b1edbc	391	uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
AnnaBridge	171:3a7713b1edbc	392	The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
AnnaBridge	171:3a7713b1edbc	393	and the mode (half/full-duplex).
AnnaBridge	171:3a7713b1edbc	394	This parameter can be a value of @ref ETH_AutoNegotiation */
AnnaBridge	171:3a7713b1edbc	395
AnnaBridge	171:3a7713b1edbc	396	uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
AnnaBridge	171:3a7713b1edbc	397	This parameter can be a value of @ref ETH_Speed */
AnnaBridge	171:3a7713b1edbc	398
AnnaBridge	171:3a7713b1edbc	399	uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
AnnaBridge	171:3a7713b1edbc	400	This parameter can be a value of @ref ETH_Duplex_Mode */
AnnaBridge	171:3a7713b1edbc	401
AnnaBridge	171:3a7713b1edbc	402	uint16_t PhyAddress; /*!< Ethernet PHY address.
AnnaBridge	171:3a7713b1edbc	403	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
AnnaBridge	171:3a7713b1edbc	404
AnnaBridge	171:3a7713b1edbc	405	uint8_t MACAddr; /!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
AnnaBridge	171:3a7713b1edbc	406
AnnaBridge	171:3a7713b1edbc	407	uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
AnnaBridge	171:3a7713b1edbc	408	This parameter can be a value of @ref ETH_Rx_Mode */
AnnaBridge	171:3a7713b1edbc	409
AnnaBridge	171:3a7713b1edbc	410	uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
AnnaBridge	171:3a7713b1edbc	411	This parameter can be a value of @ref ETH_Checksum_Mode */
AnnaBridge	171:3a7713b1edbc	412
AnnaBridge	171:3a7713b1edbc	413	uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
AnnaBridge	171:3a7713b1edbc	414	This parameter can be a value of @ref ETH_Media_Interface */
AnnaBridge	171:3a7713b1edbc	415
AnnaBridge	171:3a7713b1edbc	416	} ETH_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	417
AnnaBridge	171:3a7713b1edbc	418
AnnaBridge	171:3a7713b1edbc	419	/**
AnnaBridge	171:3a7713b1edbc	420	* @brief ETH MAC Configuration Structure definition
AnnaBridge	171:3a7713b1edbc	421	*/
AnnaBridge	171:3a7713b1edbc	422
AnnaBridge	171:3a7713b1edbc	423	typedef struct
AnnaBridge	171:3a7713b1edbc	424	{
AnnaBridge	171:3a7713b1edbc	425	uint32_t Watchdog; /*!< Selects or not the Watchdog timer
AnnaBridge	171:3a7713b1edbc	426	When enabled, the MAC allows no more then 2048 bytes to be received.
AnnaBridge	171:3a7713b1edbc	427	When disabled, the MAC can receive up to 16384 bytes.
AnnaBridge	171:3a7713b1edbc	428	This parameter can be a value of @ref ETH_Watchdog */
AnnaBridge	171:3a7713b1edbc	429
AnnaBridge	171:3a7713b1edbc	430	uint32_t Jabber; /*!< Selects or not Jabber timer
AnnaBridge	171:3a7713b1edbc	431	When enabled, the MAC allows no more then 2048 bytes to be sent.
AnnaBridge	171:3a7713b1edbc	432	When disabled, the MAC can send up to 16384 bytes.
AnnaBridge	171:3a7713b1edbc	433	This parameter can be a value of @ref ETH_Jabber */
AnnaBridge	171:3a7713b1edbc	434
AnnaBridge	171:3a7713b1edbc	435	uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
AnnaBridge	171:3a7713b1edbc	436	This parameter can be a value of @ref ETH_Inter_Frame_Gap */
AnnaBridge	171:3a7713b1edbc	437
AnnaBridge	171:3a7713b1edbc	438	uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
AnnaBridge	171:3a7713b1edbc	439	This parameter can be a value of @ref ETH_Carrier_Sense */
AnnaBridge	171:3a7713b1edbc	440
AnnaBridge	171:3a7713b1edbc	441	uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
AnnaBridge	171:3a7713b1edbc	442	ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
AnnaBridge	171:3a7713b1edbc	443	in Half-Duplex mode.
AnnaBridge	171:3a7713b1edbc	444	This parameter can be a value of @ref ETH_Receive_Own */
AnnaBridge	171:3a7713b1edbc	445
AnnaBridge	171:3a7713b1edbc	446	uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
AnnaBridge	171:3a7713b1edbc	447	This parameter can be a value of @ref ETH_Loop_Back_Mode */
AnnaBridge	171:3a7713b1edbc	448
AnnaBridge	171:3a7713b1edbc	449	uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
AnnaBridge	171:3a7713b1edbc	450	This parameter can be a value of @ref ETH_Checksum_Offload */
AnnaBridge	171:3a7713b1edbc	451
AnnaBridge	171:3a7713b1edbc	452	uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
AnnaBridge	171:3a7713b1edbc	453	when a collision occurs (Half-Duplex mode).
AnnaBridge	171:3a7713b1edbc	454	This parameter can be a value of @ref ETH_Retry_Transmission */
AnnaBridge	171:3a7713b1edbc	455
AnnaBridge	171:3a7713b1edbc	456	uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
AnnaBridge	171:3a7713b1edbc	457	This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
AnnaBridge	171:3a7713b1edbc	458
AnnaBridge	171:3a7713b1edbc	459	uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
AnnaBridge	171:3a7713b1edbc	460	This parameter can be a value of @ref ETH_Back_Off_Limit */
AnnaBridge	171:3a7713b1edbc	461
AnnaBridge	171:3a7713b1edbc	462	uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
AnnaBridge	171:3a7713b1edbc	463	This parameter can be a value of @ref ETH_Deferral_Check */
AnnaBridge	171:3a7713b1edbc	464
AnnaBridge	171:3a7713b1edbc	465	uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
AnnaBridge	171:3a7713b1edbc	466	This parameter can be a value of @ref ETH_Receive_All */
AnnaBridge	171:3a7713b1edbc	467
AnnaBridge	171:3a7713b1edbc	468	uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
AnnaBridge	171:3a7713b1edbc	469	This parameter can be a value of @ref ETH_Source_Addr_Filter */
AnnaBridge	171:3a7713b1edbc	470
AnnaBridge	171:3a7713b1edbc	471	uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
AnnaBridge	171:3a7713b1edbc	472	This parameter can be a value of @ref ETH_Pass_Control_Frames */
AnnaBridge	171:3a7713b1edbc	473
AnnaBridge	171:3a7713b1edbc	474	uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
AnnaBridge	171:3a7713b1edbc	475	This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
AnnaBridge	171:3a7713b1edbc	476
AnnaBridge	171:3a7713b1edbc	477	uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
AnnaBridge	171:3a7713b1edbc	478	This parameter can be a value of @ref ETH_Destination_Addr_Filter */
AnnaBridge	171:3a7713b1edbc	479
AnnaBridge	171:3a7713b1edbc	480	uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
AnnaBridge	171:3a7713b1edbc	481	This parameter can be a value of @ref ETH_Promiscuous_Mode */
AnnaBridge	171:3a7713b1edbc	482
AnnaBridge	171:3a7713b1edbc	483	uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
AnnaBridge	171:3a7713b1edbc	484	This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
AnnaBridge	171:3a7713b1edbc	485
AnnaBridge	171:3a7713b1edbc	486	uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
AnnaBridge	171:3a7713b1edbc	487	This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
AnnaBridge	171:3a7713b1edbc	488
AnnaBridge	171:3a7713b1edbc	489	uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
AnnaBridge	171:3a7713b1edbc	490	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
AnnaBridge	171:3a7713b1edbc	491
AnnaBridge	171:3a7713b1edbc	492	uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
AnnaBridge	171:3a7713b1edbc	493	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
AnnaBridge	171:3a7713b1edbc	494
AnnaBridge	171:3a7713b1edbc	495	uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
AnnaBridge	171:3a7713b1edbc	496	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
AnnaBridge	171:3a7713b1edbc	497
AnnaBridge	171:3a7713b1edbc	498	uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
AnnaBridge	171:3a7713b1edbc	499	This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
AnnaBridge	171:3a7713b1edbc	500
AnnaBridge	171:3a7713b1edbc	501	uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
AnnaBridge	171:3a7713b1edbc	502	automatic retransmission of PAUSE Frame.
AnnaBridge	171:3a7713b1edbc	503	This parameter can be a value of @ref ETH_Pause_Low_Threshold */
AnnaBridge	171:3a7713b1edbc	504
AnnaBridge	171:3a7713b1edbc	505	uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
AnnaBridge	171:3a7713b1edbc	506	unicast address and unique multicast address).
AnnaBridge	171:3a7713b1edbc	507	This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
AnnaBridge	171:3a7713b1edbc	508
AnnaBridge	171:3a7713b1edbc	509	uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
AnnaBridge	171:3a7713b1edbc	510	disable its transmitter for a specified time (Pause Time)
AnnaBridge	171:3a7713b1edbc	511	This parameter can be a value of @ref ETH_Receive_Flow_Control */
AnnaBridge	171:3a7713b1edbc	512
AnnaBridge	171:3a7713b1edbc	513	uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
AnnaBridge	171:3a7713b1edbc	514	or the MAC back-pressure operation (Half-Duplex mode)
AnnaBridge	171:3a7713b1edbc	515	This parameter can be a value of @ref ETH_Transmit_Flow_Control */
AnnaBridge	171:3a7713b1edbc	516
AnnaBridge	171:3a7713b1edbc	517	uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
AnnaBridge	171:3a7713b1edbc	518	comparison and filtering.
AnnaBridge	171:3a7713b1edbc	519	This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
AnnaBridge	171:3a7713b1edbc	520
AnnaBridge	171:3a7713b1edbc	521	uint32_t VLANTagIdentifier; /!< Holds the VLAN tag identifier for receive frames /
AnnaBridge	171:3a7713b1edbc	522
AnnaBridge	171:3a7713b1edbc	523	} ETH_MACInitTypeDef;
AnnaBridge	171:3a7713b1edbc	524
AnnaBridge	171:3a7713b1edbc	525
AnnaBridge	171:3a7713b1edbc	526	/**
AnnaBridge	171:3a7713b1edbc	527	* @brief ETH DMA Configuration Structure definition
AnnaBridge	171:3a7713b1edbc	528	*/
AnnaBridge	171:3a7713b1edbc	529
AnnaBridge	171:3a7713b1edbc	530	typedef struct
AnnaBridge	171:3a7713b1edbc	531	{
AnnaBridge	171:3a7713b1edbc	532	uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
AnnaBridge	171:3a7713b1edbc	533	This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
AnnaBridge	171:3a7713b1edbc	534
AnnaBridge	171:3a7713b1edbc	535	uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
AnnaBridge	171:3a7713b1edbc	536	This parameter can be a value of @ref ETH_Receive_Store_Forward */
AnnaBridge	171:3a7713b1edbc	537
AnnaBridge	171:3a7713b1edbc	538	uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
AnnaBridge	171:3a7713b1edbc	539	This parameter can be a value of @ref ETH_Flush_Received_Frame */
AnnaBridge	171:3a7713b1edbc	540
AnnaBridge	171:3a7713b1edbc	541	uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
AnnaBridge	171:3a7713b1edbc	542	This parameter can be a value of @ref ETH_Transmit_Store_Forward */
AnnaBridge	171:3a7713b1edbc	543
AnnaBridge	171:3a7713b1edbc	544	uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
AnnaBridge	171:3a7713b1edbc	545	This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
AnnaBridge	171:3a7713b1edbc	546
AnnaBridge	171:3a7713b1edbc	547	uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
AnnaBridge	171:3a7713b1edbc	548	This parameter can be a value of @ref ETH_Forward_Error_Frames */
AnnaBridge	171:3a7713b1edbc	549
AnnaBridge	171:3a7713b1edbc	550	uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
AnnaBridge	171:3a7713b1edbc	551	and length less than 64 bytes) including pad-bytes and CRC)
AnnaBridge	171:3a7713b1edbc	552	This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
AnnaBridge	171:3a7713b1edbc	553
AnnaBridge	171:3a7713b1edbc	554	uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
AnnaBridge	171:3a7713b1edbc	555	This parameter can be a value of @ref ETH_Receive_Threshold_Control */
AnnaBridge	171:3a7713b1edbc	556
AnnaBridge	171:3a7713b1edbc	557	uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
AnnaBridge	171:3a7713b1edbc	558	frame of Transmit data even before obtaining the status for the first frame.
AnnaBridge	171:3a7713b1edbc	559	This parameter can be a value of @ref ETH_Second_Frame_Operate */
AnnaBridge	171:3a7713b1edbc	560
AnnaBridge	171:3a7713b1edbc	561	uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
AnnaBridge	171:3a7713b1edbc	562	This parameter can be a value of @ref ETH_Address_Aligned_Beats */
AnnaBridge	171:3a7713b1edbc	563
AnnaBridge	171:3a7713b1edbc	564	uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
AnnaBridge	171:3a7713b1edbc	565	This parameter can be a value of @ref ETH_Fixed_Burst */
AnnaBridge	171:3a7713b1edbc	566
AnnaBridge	171:3a7713b1edbc	567	uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
AnnaBridge	171:3a7713b1edbc	568	This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
AnnaBridge	171:3a7713b1edbc	569
AnnaBridge	171:3a7713b1edbc	570	uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
AnnaBridge	171:3a7713b1edbc	571	This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
AnnaBridge	171:3a7713b1edbc	572
AnnaBridge	171:3a7713b1edbc	573	uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
AnnaBridge	171:3a7713b1edbc	574	This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
AnnaBridge	171:3a7713b1edbc	575
AnnaBridge	171:3a7713b1edbc	576	uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
AnnaBridge	171:3a7713b1edbc	577	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
AnnaBridge	171:3a7713b1edbc	578
AnnaBridge	171:3a7713b1edbc	579	uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
AnnaBridge	171:3a7713b1edbc	580	This parameter can be a value of @ref ETH_DMA_Arbitration */
AnnaBridge	171:3a7713b1edbc	581	} ETH_DMAInitTypeDef;
AnnaBridge	171:3a7713b1edbc	582
AnnaBridge	171:3a7713b1edbc	583
AnnaBridge	171:3a7713b1edbc	584	/**
AnnaBridge	171:3a7713b1edbc	585	* @brief ETH DMA Descriptors data structure definition
AnnaBridge	171:3a7713b1edbc	586	*/
AnnaBridge	171:3a7713b1edbc	587
AnnaBridge	171:3a7713b1edbc	588	typedef struct
AnnaBridge	171:3a7713b1edbc	589	{
AnnaBridge	171:3a7713b1edbc	590	__IO uint32_t Status; /!< Status /
AnnaBridge	171:3a7713b1edbc	591
AnnaBridge	171:3a7713b1edbc	592	uint32_t ControlBufferSize; /!< Control and Buffer1, Buffer2 lengths /
AnnaBridge	171:3a7713b1edbc	593
AnnaBridge	171:3a7713b1edbc	594	uint32_t Buffer1Addr; /!< Buffer1 address pointer /
AnnaBridge	171:3a7713b1edbc	595
AnnaBridge	171:3a7713b1edbc	596	uint32_t Buffer2NextDescAddr; /!< Buffer2 or next descriptor address pointer /
AnnaBridge	171:3a7713b1edbc	597
AnnaBridge	171:3a7713b1edbc	598	/!< Enhanced ETHERNET DMA PTP Descriptors /
AnnaBridge	171:3a7713b1edbc	599	uint32_t ExtendedStatus; /!< Extended status for PTP receive descriptor /
AnnaBridge	171:3a7713b1edbc	600
AnnaBridge	171:3a7713b1edbc	601	uint32_t Reserved1; /!< Reserved /
AnnaBridge	171:3a7713b1edbc	602
AnnaBridge	171:3a7713b1edbc	603	uint32_t TimeStampLow; /!< Time Stamp Low value for transmit and receive /
AnnaBridge	171:3a7713b1edbc	604
AnnaBridge	171:3a7713b1edbc	605	uint32_t TimeStampHigh; /!< Time Stamp High value for transmit and receive /
AnnaBridge	171:3a7713b1edbc	606
AnnaBridge	171:3a7713b1edbc	607	} ETH_DMADescTypeDef;
AnnaBridge	171:3a7713b1edbc	608
AnnaBridge	171:3a7713b1edbc	609
AnnaBridge	171:3a7713b1edbc	610	/**
AnnaBridge	171:3a7713b1edbc	611	* @brief Received Frame Informations structure definition
AnnaBridge	171:3a7713b1edbc	612	*/
AnnaBridge	171:3a7713b1edbc	613	typedef struct
AnnaBridge	171:3a7713b1edbc	614	{
AnnaBridge	171:3a7713b1edbc	615	ETH_DMADescTypeDef FSRxDesc; /!< First Segment Rx Desc */
AnnaBridge	171:3a7713b1edbc	616
AnnaBridge	171:3a7713b1edbc	617	ETH_DMADescTypeDef LSRxDesc; /!< Last Segment Rx Desc */
AnnaBridge	171:3a7713b1edbc	618
AnnaBridge	171:3a7713b1edbc	619	uint32_t SegCount; /!< Segment count /
AnnaBridge	171:3a7713b1edbc	620
AnnaBridge	171:3a7713b1edbc	621	uint32_t length; /!< Frame length /
AnnaBridge	171:3a7713b1edbc	622
AnnaBridge	171:3a7713b1edbc	623	uint32_t buffer; /!< Frame buffer /
AnnaBridge	171:3a7713b1edbc	624
AnnaBridge	171:3a7713b1edbc	625	} ETH_DMARxFrameInfos;
AnnaBridge	171:3a7713b1edbc	626
AnnaBridge	171:3a7713b1edbc	627
AnnaBridge	171:3a7713b1edbc	628	/**
AnnaBridge	171:3a7713b1edbc	629	* @brief ETH Handle Structure definition
AnnaBridge	171:3a7713b1edbc	630	*/
AnnaBridge	171:3a7713b1edbc	631
AnnaBridge	171:3a7713b1edbc	632	typedef struct
AnnaBridge	171:3a7713b1edbc	633	{
AnnaBridge	171:3a7713b1edbc	634	ETH_TypeDef Instance; /!< Register base address */
AnnaBridge	171:3a7713b1edbc	635
AnnaBridge	171:3a7713b1edbc	636	ETH_InitTypeDef Init; /!< Ethernet Init Configuration /
AnnaBridge	171:3a7713b1edbc	637
AnnaBridge	171:3a7713b1edbc	638	uint32_t LinkStatus; /!< Ethernet link status /
AnnaBridge	171:3a7713b1edbc	639
AnnaBridge	171:3a7713b1edbc	640	ETH_DMADescTypeDef RxDesc; /!< Rx descriptor to Get */
AnnaBridge	171:3a7713b1edbc	641
AnnaBridge	171:3a7713b1edbc	642	ETH_DMADescTypeDef TxDesc; /!< Tx descriptor to Set */
AnnaBridge	171:3a7713b1edbc	643
AnnaBridge	171:3a7713b1edbc	644	ETH_DMARxFrameInfos RxFrameInfos; /!< last Rx frame infos /
AnnaBridge	171:3a7713b1edbc	645
AnnaBridge	171:3a7713b1edbc	646	__IO HAL_ETH_StateTypeDef State; /!< ETH communication state /
AnnaBridge	171:3a7713b1edbc	647
AnnaBridge	171:3a7713b1edbc	648	HAL_LockTypeDef Lock; /!< ETH Lock /
AnnaBridge	171:3a7713b1edbc	649
AnnaBridge	171:3a7713b1edbc	650	} ETH_HandleTypeDef;
AnnaBridge	171:3a7713b1edbc	651
AnnaBridge	171:3a7713b1edbc	652	/**
AnnaBridge	171:3a7713b1edbc	653	* @}
AnnaBridge	171:3a7713b1edbc	654	*/
AnnaBridge	171:3a7713b1edbc	655
AnnaBridge	171:3a7713b1edbc	656	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	657	/** @defgroup ETH_Exported_Constants ETH Exported Constants
AnnaBridge	171:3a7713b1edbc	658	* @{
AnnaBridge	171:3a7713b1edbc	659	*/
AnnaBridge	171:3a7713b1edbc	660
AnnaBridge	171:3a7713b1edbc	661	/** @defgroup ETH_Buffers_setting ETH Buffers setting
AnnaBridge	171:3a7713b1edbc	662	* @{
AnnaBridge	171:3a7713b1edbc	663	*/
AnnaBridge	171:3a7713b1edbc	664	#define ETH_MAX_PACKET_SIZE 1524U /!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC /
AnnaBridge	171:3a7713b1edbc	665	#define ETH_HEADER 14U /!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type /
AnnaBridge	171:3a7713b1edbc	666	#define ETH_CRC 4U /!< Ethernet CRC /
AnnaBridge	171:3a7713b1edbc	667	#define ETH_EXTRA 2U /!< Extra bytes in some cases /
AnnaBridge	171:3a7713b1edbc	668	#define ETH_VLAN_TAG 4U /!< optional 802.1q VLAN Tag /
AnnaBridge	171:3a7713b1edbc	669	#define ETH_MIN_ETH_PAYLOAD 46U /!< Minimum Ethernet payload size /
AnnaBridge	171:3a7713b1edbc	670	#define ETH_MAX_ETH_PAYLOAD 1500U /!< Maximum Ethernet payload size /
AnnaBridge	171:3a7713b1edbc	671	#define ETH_JUMBO_FRAME_PAYLOAD 9000U /!< Jumbo frame payload size /
AnnaBridge	171:3a7713b1edbc	672
AnnaBridge	171:3a7713b1edbc	673	/* Ethernet driver receive buffers are organized in a chained linked-list, when
AnnaBridge	171:3a7713b1edbc	674	an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
AnnaBridge	171:3a7713b1edbc	675	to the driver receive buffers memory.
AnnaBridge	171:3a7713b1edbc	676
AnnaBridge	171:3a7713b1edbc	677	Depending on the size of the received ethernet packet and the size of
AnnaBridge	171:3a7713b1edbc	678	each ethernet driver receive buffer, the received packet can take one or more
AnnaBridge	171:3a7713b1edbc	679	ethernet driver receive buffer.
AnnaBridge	171:3a7713b1edbc	680
AnnaBridge	171:3a7713b1edbc	681	In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
AnnaBridge	171:3a7713b1edbc	682	and the total count of the driver receive buffers ETH_RXBUFNB.
AnnaBridge	171:3a7713b1edbc	683
AnnaBridge	171:3a7713b1edbc	684	The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
AnnaBridge	171:3a7713b1edbc	685	example, they can be reconfigured in the application layer to fit the application
AnnaBridge	171:3a7713b1edbc	686	needs */
AnnaBridge	171:3a7713b1edbc	687
AnnaBridge	171:3a7713b1edbc	688	/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
AnnaBridge	171:3a7713b1edbc	689	packet */
AnnaBridge	171:3a7713b1edbc	690	#ifndef ETH_RX_BUF_SIZE
AnnaBridge	171:3a7713b1edbc	691	#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
AnnaBridge	171:3a7713b1edbc	692	#endif
AnnaBridge	171:3a7713b1edbc	693
AnnaBridge	171:3a7713b1edbc	694	/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
AnnaBridge	171:3a7713b1edbc	695	#ifndef ETH_RXBUFNB
AnnaBridge	171:3a7713b1edbc	696	#define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
AnnaBridge	171:3a7713b1edbc	697	#endif
AnnaBridge	171:3a7713b1edbc	698
AnnaBridge	171:3a7713b1edbc	699
AnnaBridge	171:3a7713b1edbc	700	/* Ethernet driver transmit buffers are organized in a chained linked-list, when
AnnaBridge	171:3a7713b1edbc	701	an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
AnnaBridge	171:3a7713b1edbc	702	driver transmit buffers memory to the TxFIFO.
AnnaBridge	171:3a7713b1edbc	703
AnnaBridge	171:3a7713b1edbc	704	Depending on the size of the Ethernet packet to be transmitted and the size of
AnnaBridge	171:3a7713b1edbc	705	each ethernet driver transmit buffer, the packet to be transmitted can take
AnnaBridge	171:3a7713b1edbc	706	one or more ethernet driver transmit buffer.
AnnaBridge	171:3a7713b1edbc	707
AnnaBridge	171:3a7713b1edbc	708	In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
AnnaBridge	171:3a7713b1edbc	709	and the total count of the driver transmit buffers ETH_TXBUFNB.
AnnaBridge	171:3a7713b1edbc	710
AnnaBridge	171:3a7713b1edbc	711	The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
AnnaBridge	171:3a7713b1edbc	712	example, they can be reconfigured in the application layer to fit the application
AnnaBridge	171:3a7713b1edbc	713	needs */
AnnaBridge	171:3a7713b1edbc	714
AnnaBridge	171:3a7713b1edbc	715	/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
AnnaBridge	171:3a7713b1edbc	716	packet */
AnnaBridge	171:3a7713b1edbc	717	#ifndef ETH_TX_BUF_SIZE
AnnaBridge	171:3a7713b1edbc	718	#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
AnnaBridge	171:3a7713b1edbc	719	#endif
AnnaBridge	171:3a7713b1edbc	720
AnnaBridge	171:3a7713b1edbc	721	/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
AnnaBridge	171:3a7713b1edbc	722	#ifndef ETH_TXBUFNB
AnnaBridge	171:3a7713b1edbc	723	#define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
AnnaBridge	171:3a7713b1edbc	724	#endif
AnnaBridge	171:3a7713b1edbc	725
AnnaBridge	171:3a7713b1edbc	726	/**
AnnaBridge	171:3a7713b1edbc	727	* @}
AnnaBridge	171:3a7713b1edbc	728	*/
AnnaBridge	171:3a7713b1edbc	729
AnnaBridge	171:3a7713b1edbc	730	/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
AnnaBridge	171:3a7713b1edbc	731	* @{
AnnaBridge	171:3a7713b1edbc	732	*/
AnnaBridge	171:3a7713b1edbc	733
AnnaBridge	171:3a7713b1edbc	734	/*
AnnaBridge	171:3a7713b1edbc	735	DMA Tx Descriptor
AnnaBridge	171:3a7713b1edbc	736	-----------------------------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	737	TDES0 \| OWN(31) \| CTRL[30:26] \| Reserved[25:24] \| CTRL[23:20] \| Reserved[19:17] \| Status[16:0] \|
AnnaBridge	171:3a7713b1edbc	738	-----------------------------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	739	TDES1 \| Reserved[31:29] \| Buffer2 ByteCount[28:16] \| Reserved[15:13] \| Buffer1 ByteCount[12:0] \|
AnnaBridge	171:3a7713b1edbc	740	-----------------------------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	741	TDES2 \| Buffer1 Address [31:0] \|
AnnaBridge	171:3a7713b1edbc	742	-----------------------------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	743	TDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
AnnaBridge	171:3a7713b1edbc	744	-----------------------------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	745	*/
AnnaBridge	171:3a7713b1edbc	746
AnnaBridge	171:3a7713b1edbc	747	/**
AnnaBridge	171:3a7713b1edbc	748	* @brief Bit definition of TDES0 register: DMA Tx descriptor status register
AnnaBridge	171:3a7713b1edbc	749	*/
AnnaBridge	171:3a7713b1edbc	750	#define ETH_DMATXDESC_OWN 0x80000000U /!< OWN bit: descriptor is owned by DMA engine /
AnnaBridge	171:3a7713b1edbc	751	#define ETH_DMATXDESC_IC 0x40000000U /!< Interrupt on Completion /
AnnaBridge	171:3a7713b1edbc	752	#define ETH_DMATXDESC_LS 0x20000000U /!< Last Segment /
AnnaBridge	171:3a7713b1edbc	753	#define ETH_DMATXDESC_FS 0x10000000U /!< First Segment /
AnnaBridge	171:3a7713b1edbc	754	#define ETH_DMATXDESC_DC 0x08000000U /!< Disable CRC /
AnnaBridge	171:3a7713b1edbc	755	#define ETH_DMATXDESC_DP 0x04000000U /!< Disable Padding /
AnnaBridge	171:3a7713b1edbc	756	#define ETH_DMATXDESC_TTSE 0x02000000U /!< Transmit Time Stamp Enable /
AnnaBridge	171:3a7713b1edbc	757	#define ETH_DMATXDESC_CIC 0x00C00000U /!< Checksum Insertion Control: 4 cases /
AnnaBridge	171:3a7713b1edbc	758	#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /!< Do Nothing: Checksum Engine is bypassed /
AnnaBridge	171:3a7713b1edbc	759	#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /!< IPV4 header Checksum Insertion /
AnnaBridge	171:3a7713b1edbc	760	#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /!< TCP/UDP/ICMP Checksum Insertion calculated over segment only /
AnnaBridge	171:3a7713b1edbc	761	#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /!< TCP/UDP/ICMP Checksum Insertion fully calculated /
AnnaBridge	171:3a7713b1edbc	762	#define ETH_DMATXDESC_TER 0x00200000U /!< Transmit End of Ring /
AnnaBridge	171:3a7713b1edbc	763	#define ETH_DMATXDESC_TCH 0x00100000U /!< Second Address Chained /
AnnaBridge	171:3a7713b1edbc	764	#define ETH_DMATXDESC_TTSS 0x00020000U /!< Tx Time Stamp Status /
AnnaBridge	171:3a7713b1edbc	765	#define ETH_DMATXDESC_IHE 0x00010000U /!< IP Header Error /
AnnaBridge	171:3a7713b1edbc	766	#define ETH_DMATXDESC_ES 0x00008000U /!< Error summary: OR of the following bits: UE \|\| ED \|\| EC \|\| LCO \|\| NC \|\| LCA \|\| FF \|\| JT /
AnnaBridge	171:3a7713b1edbc	767	#define ETH_DMATXDESC_JT 0x00004000U /!< Jabber Timeout /
AnnaBridge	171:3a7713b1edbc	768	#define ETH_DMATXDESC_FF 0x00002000U /!< Frame Flushed: DMA/MTL flushed the frame due to SW flush /
AnnaBridge	171:3a7713b1edbc	769	#define ETH_DMATXDESC_PCE 0x00001000U /!< Payload Checksum Error /
AnnaBridge	171:3a7713b1edbc	770	#define ETH_DMATXDESC_LCA 0x00000800U /!< Loss of Carrier: carrier lost during transmission /
AnnaBridge	171:3a7713b1edbc	771	#define ETH_DMATXDESC_NC 0x00000400U /!< No Carrier: no carrier signal from the transceiver /
AnnaBridge	171:3a7713b1edbc	772	#define ETH_DMATXDESC_LCO 0x00000200U /!< Late Collision: transmission aborted due to collision /
AnnaBridge	171:3a7713b1edbc	773	#define ETH_DMATXDESC_EC 0x00000100U /!< Excessive Collision: transmission aborted after 16 collisions /
AnnaBridge	171:3a7713b1edbc	774	#define ETH_DMATXDESC_VF 0x00000080U /!< VLAN Frame /
AnnaBridge	171:3a7713b1edbc	775	#define ETH_DMATXDESC_CC 0x00000078U /!< Collision Count /
AnnaBridge	171:3a7713b1edbc	776	#define ETH_DMATXDESC_ED 0x00000004U /!< Excessive Deferral /
AnnaBridge	171:3a7713b1edbc	777	#define ETH_DMATXDESC_UF 0x00000002U /!< Underflow Error: late data arrival from the memory /
AnnaBridge	171:3a7713b1edbc	778	#define ETH_DMATXDESC_DB 0x00000001U /!< Deferred Bit /
AnnaBridge	171:3a7713b1edbc	779
AnnaBridge	171:3a7713b1edbc	780	/**
AnnaBridge	171:3a7713b1edbc	781	* @brief Bit definition of TDES1 register
AnnaBridge	171:3a7713b1edbc	782	*/
AnnaBridge	171:3a7713b1edbc	783	#define ETH_DMATXDESC_TBS2 0x1FFF0000U /!< Transmit Buffer2 Size /
AnnaBridge	171:3a7713b1edbc	784	#define ETH_DMATXDESC_TBS1 0x00001FFFU /!< Transmit Buffer1 Size /
AnnaBridge	171:3a7713b1edbc	785
AnnaBridge	171:3a7713b1edbc	786	/**
AnnaBridge	171:3a7713b1edbc	787	* @brief Bit definition of TDES2 register
AnnaBridge	171:3a7713b1edbc	788	*/
AnnaBridge	171:3a7713b1edbc	789	#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /!< Buffer1 Address Pointer /
AnnaBridge	171:3a7713b1edbc	790
AnnaBridge	171:3a7713b1edbc	791	/**
AnnaBridge	171:3a7713b1edbc	792	* @brief Bit definition of TDES3 register
AnnaBridge	171:3a7713b1edbc	793	*/
AnnaBridge	171:3a7713b1edbc	794	#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /!< Buffer2 Address Pointer /
AnnaBridge	171:3a7713b1edbc	795
AnnaBridge	171:3a7713b1edbc	796	/*---------------------------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	797	TDES6 \| Transmit Time Stamp Low [31:0] \|
AnnaBridge	171:3a7713b1edbc	798	-----------------------------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	799	TDES7 \| Transmit Time Stamp High [31:0] \|
AnnaBridge	171:3a7713b1edbc	800	----------------------------------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	801
AnnaBridge	171:3a7713b1edbc	802	/* Bit definition of TDES6 register */
AnnaBridge	171:3a7713b1edbc	803	#define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */
AnnaBridge	171:3a7713b1edbc	804
AnnaBridge	171:3a7713b1edbc	805	/* Bit definition of TDES7 register */
AnnaBridge	171:3a7713b1edbc	806	#define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */
AnnaBridge	171:3a7713b1edbc	807
AnnaBridge	171:3a7713b1edbc	808	/**
AnnaBridge	171:3a7713b1edbc	809	* @}
AnnaBridge	171:3a7713b1edbc	810	*/
AnnaBridge	171:3a7713b1edbc	811	/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
AnnaBridge	171:3a7713b1edbc	812	* @{
AnnaBridge	171:3a7713b1edbc	813	*/
AnnaBridge	171:3a7713b1edbc	814
AnnaBridge	171:3a7713b1edbc	815	/*
AnnaBridge	171:3a7713b1edbc	816	DMA Rx Descriptor
AnnaBridge	171:3a7713b1edbc	817	--------------------------------------------------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	818	RDES0 \| OWN(31) \| Status [30:0] \|
AnnaBridge	171:3a7713b1edbc	819	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	820	RDES1 \| CTRL(31) \| Reserved[30:29] \| Buffer2 ByteCount[28:16] \| CTRL[15:14] \| Reserved(13) \| Buffer1 ByteCount[12:0] \|
AnnaBridge	171:3a7713b1edbc	821	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	822	RDES2 \| Buffer1 Address [31:0] \|
AnnaBridge	171:3a7713b1edbc	823	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	824	RDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
AnnaBridge	171:3a7713b1edbc	825	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	826	*/
AnnaBridge	171:3a7713b1edbc	827
AnnaBridge	171:3a7713b1edbc	828	/**
AnnaBridge	171:3a7713b1edbc	829	* @brief Bit definition of RDES0 register: DMA Rx descriptor status register
AnnaBridge	171:3a7713b1edbc	830	*/
AnnaBridge	171:3a7713b1edbc	831	#define ETH_DMARXDESC_OWN 0x80000000U /!< OWN bit: descriptor is owned by DMA engine /
AnnaBridge	171:3a7713b1edbc	832	#define ETH_DMARXDESC_AFM 0x40000000U /!< DA Filter Fail for the rx frame /
AnnaBridge	171:3a7713b1edbc	833	#define ETH_DMARXDESC_FL 0x3FFF0000U /!< Receive descriptor frame length /
AnnaBridge	171:3a7713b1edbc	834	#define ETH_DMARXDESC_ES 0x00008000U /!< Error summary: OR of the following bits: DE \|\| OE \|\| IPC \|\| LC \|\| RWT \|\| RE \|\| CE /
AnnaBridge	171:3a7713b1edbc	835	#define ETH_DMARXDESC_DE 0x00004000U /!< Descriptor error: no more descriptors for receive frame /
AnnaBridge	171:3a7713b1edbc	836	#define ETH_DMARXDESC_SAF 0x00002000U /!< SA Filter Fail for the received frame /
AnnaBridge	171:3a7713b1edbc	837	#define ETH_DMARXDESC_LE 0x00001000U /!< Frame size not matching with length field /
AnnaBridge	171:3a7713b1edbc	838	#define ETH_DMARXDESC_OE 0x00000800U /!< Overflow Error: Frame was damaged due to buffer overflow /
AnnaBridge	171:3a7713b1edbc	839	#define ETH_DMARXDESC_VLAN 0x00000400U /!< VLAN Tag: received frame is a VLAN frame /
AnnaBridge	171:3a7713b1edbc	840	#define ETH_DMARXDESC_FS 0x00000200U /!< First descriptor of the frame /
AnnaBridge	171:3a7713b1edbc	841	#define ETH_DMARXDESC_LS 0x00000100U /!< Last descriptor of the frame /
AnnaBridge	171:3a7713b1edbc	842	#define ETH_DMARXDESC_IPV4HCE 0x00000080U /!< IPC Checksum Error: Rx Ipv4 header checksum error /
AnnaBridge	171:3a7713b1edbc	843	#define ETH_DMARXDESC_LC 0x00000040U /!< Late collision occurred during reception /
AnnaBridge	171:3a7713b1edbc	844	#define ETH_DMARXDESC_FT 0x00000020U /!< Frame type - Ethernet, otherwise 802.3 /
AnnaBridge	171:3a7713b1edbc	845	#define ETH_DMARXDESC_RWT 0x00000010U /!< Receive Watchdog Timeout: watchdog timer expired during reception /
AnnaBridge	171:3a7713b1edbc	846	#define ETH_DMARXDESC_RE 0x00000008U /!< Receive error: error reported by MII interface /
AnnaBridge	171:3a7713b1edbc	847	#define ETH_DMARXDESC_DBE 0x00000004U /!< Dribble bit error: frame contains non int multiple of 8 bits /
AnnaBridge	171:3a7713b1edbc	848	#define ETH_DMARXDESC_CE 0x00000002U /!< CRC error /
AnnaBridge	171:3a7713b1edbc	849	#define ETH_DMARXDESC_MAMPCE 0x00000001U /!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error /
AnnaBridge	171:3a7713b1edbc	850
AnnaBridge	171:3a7713b1edbc	851	/**
AnnaBridge	171:3a7713b1edbc	852	* @brief Bit definition of RDES1 register
AnnaBridge	171:3a7713b1edbc	853	*/
AnnaBridge	171:3a7713b1edbc	854	#define ETH_DMARXDESC_DIC 0x80000000U /!< Disable Interrupt on Completion /
AnnaBridge	171:3a7713b1edbc	855	#define ETH_DMARXDESC_RBS2 0x1FFF0000U /!< Receive Buffer2 Size /
AnnaBridge	171:3a7713b1edbc	856	#define ETH_DMARXDESC_RER 0x00008000U /!< Receive End of Ring /
AnnaBridge	171:3a7713b1edbc	857	#define ETH_DMARXDESC_RCH 0x00004000U /!< Second Address Chained /
AnnaBridge	171:3a7713b1edbc	858	#define ETH_DMARXDESC_RBS1 0x00001FFFU /!< Receive Buffer1 Size /
AnnaBridge	171:3a7713b1edbc	859
AnnaBridge	171:3a7713b1edbc	860	/**
AnnaBridge	171:3a7713b1edbc	861	* @brief Bit definition of RDES2 register
AnnaBridge	171:3a7713b1edbc	862	*/
AnnaBridge	171:3a7713b1edbc	863	#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /!< Buffer1 Address Pointer /
AnnaBridge	171:3a7713b1edbc	864
AnnaBridge	171:3a7713b1edbc	865	/**
AnnaBridge	171:3a7713b1edbc	866	* @brief Bit definition of RDES3 register
AnnaBridge	171:3a7713b1edbc	867	*/
AnnaBridge	171:3a7713b1edbc	868	#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /!< Buffer2 Address Pointer /
AnnaBridge	171:3a7713b1edbc	869
AnnaBridge	171:3a7713b1edbc	870	/*---------------------------------------------------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	871	RDES4 \| Reserved[31:15] \| Extended Status [14:0] \|
AnnaBridge	171:3a7713b1edbc	872	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	873	RDES5 \| Reserved[31:0] \|
AnnaBridge	171:3a7713b1edbc	874	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	875	RDES6 \| Receive Time Stamp Low [31:0] \|
AnnaBridge	171:3a7713b1edbc	876	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	877	RDES7 \| Receive Time Stamp High [31:0] \|
AnnaBridge	171:3a7713b1edbc	878	--------------------------------------------------------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	879
AnnaBridge	171:3a7713b1edbc	880	/* Bit definition of RDES4 register */
AnnaBridge	171:3a7713b1edbc	881	#define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */
AnnaBridge	171:3a7713b1edbc	882	#define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */
AnnaBridge	171:3a7713b1edbc	883	#define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */
AnnaBridge	171:3a7713b1edbc	884	#define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */
AnnaBridge	171:3a7713b1edbc	885	#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */
AnnaBridge	171:3a7713b1edbc	886	#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */
AnnaBridge	171:3a7713b1edbc	887	#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */
AnnaBridge	171:3a7713b1edbc	888	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
AnnaBridge	171:3a7713b1edbc	889	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
AnnaBridge	171:3a7713b1edbc	890	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
AnnaBridge	171:3a7713b1edbc	891	#define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */
AnnaBridge	171:3a7713b1edbc	892	#define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */
AnnaBridge	171:3a7713b1edbc	893	#define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */
AnnaBridge	171:3a7713b1edbc	894	#define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */
AnnaBridge	171:3a7713b1edbc	895	#define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */
AnnaBridge	171:3a7713b1edbc	896	#define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */
AnnaBridge	171:3a7713b1edbc	897	#define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */
AnnaBridge	171:3a7713b1edbc	898	#define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */
AnnaBridge	171:3a7713b1edbc	899	#define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */
AnnaBridge	171:3a7713b1edbc	900
AnnaBridge	171:3a7713b1edbc	901	/* Bit definition of RDES6 register */
AnnaBridge	171:3a7713b1edbc	902	#define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */
AnnaBridge	171:3a7713b1edbc	903
AnnaBridge	171:3a7713b1edbc	904	/* Bit definition of RDES7 register */
AnnaBridge	171:3a7713b1edbc	905	#define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */
AnnaBridge	171:3a7713b1edbc	906	/**
AnnaBridge	171:3a7713b1edbc	907	* @}
AnnaBridge	171:3a7713b1edbc	908	*/
AnnaBridge	171:3a7713b1edbc	909	/** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
AnnaBridge	171:3a7713b1edbc	910	* @{
AnnaBridge	171:3a7713b1edbc	911	*/
AnnaBridge	171:3a7713b1edbc	912	#define ETH_AUTONEGOTIATION_ENABLE 0x00000001U
AnnaBridge	171:3a7713b1edbc	913	#define ETH_AUTONEGOTIATION_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	914
AnnaBridge	171:3a7713b1edbc	915	/**
AnnaBridge	171:3a7713b1edbc	916	* @}
AnnaBridge	171:3a7713b1edbc	917	*/
AnnaBridge	171:3a7713b1edbc	918	/** @defgroup ETH_Speed ETH Speed
AnnaBridge	171:3a7713b1edbc	919	* @{
AnnaBridge	171:3a7713b1edbc	920	*/
AnnaBridge	171:3a7713b1edbc	921	#define ETH_SPEED_10M 0x00000000U
AnnaBridge	171:3a7713b1edbc	922	#define ETH_SPEED_100M 0x00004000U
AnnaBridge	171:3a7713b1edbc	923
AnnaBridge	171:3a7713b1edbc	924	/**
AnnaBridge	171:3a7713b1edbc	925	* @}
AnnaBridge	171:3a7713b1edbc	926	*/
AnnaBridge	171:3a7713b1edbc	927	/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
AnnaBridge	171:3a7713b1edbc	928	* @{
AnnaBridge	171:3a7713b1edbc	929	*/
AnnaBridge	171:3a7713b1edbc	930	#define ETH_MODE_FULLDUPLEX 0x00000800U
AnnaBridge	171:3a7713b1edbc	931	#define ETH_MODE_HALFDUPLEX 0x00000000U
AnnaBridge	171:3a7713b1edbc	932	/**
AnnaBridge	171:3a7713b1edbc	933	* @}
AnnaBridge	171:3a7713b1edbc	934	*/
AnnaBridge	171:3a7713b1edbc	935	/** @defgroup ETH_Rx_Mode ETH Rx Mode
AnnaBridge	171:3a7713b1edbc	936	* @{
AnnaBridge	171:3a7713b1edbc	937	*/
AnnaBridge	171:3a7713b1edbc	938	#define ETH_RXPOLLING_MODE 0x00000000U
AnnaBridge	171:3a7713b1edbc	939	#define ETH_RXINTERRUPT_MODE 0x00000001U
AnnaBridge	171:3a7713b1edbc	940	/**
AnnaBridge	171:3a7713b1edbc	941	* @}
AnnaBridge	171:3a7713b1edbc	942	*/
AnnaBridge	171:3a7713b1edbc	943
AnnaBridge	171:3a7713b1edbc	944	/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
AnnaBridge	171:3a7713b1edbc	945	* @{
AnnaBridge	171:3a7713b1edbc	946	*/
AnnaBridge	171:3a7713b1edbc	947	#define ETH_CHECKSUM_BY_HARDWARE 0x00000000U
AnnaBridge	171:3a7713b1edbc	948	#define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U
AnnaBridge	171:3a7713b1edbc	949	/**
AnnaBridge	171:3a7713b1edbc	950	* @}
AnnaBridge	171:3a7713b1edbc	951	*/
AnnaBridge	171:3a7713b1edbc	952
AnnaBridge	171:3a7713b1edbc	953	/** @defgroup ETH_Media_Interface ETH Media Interface
AnnaBridge	171:3a7713b1edbc	954	* @{
AnnaBridge	171:3a7713b1edbc	955	*/
AnnaBridge	171:3a7713b1edbc	956	#define ETH_MEDIA_INTERFACE_MII 0x00000000U
AnnaBridge	171:3a7713b1edbc	957	#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
AnnaBridge	171:3a7713b1edbc	958	/**
AnnaBridge	171:3a7713b1edbc	959	* @}
AnnaBridge	171:3a7713b1edbc	960	*/
AnnaBridge	171:3a7713b1edbc	961
AnnaBridge	171:3a7713b1edbc	962	/** @defgroup ETH_Watchdog ETH Watchdog
AnnaBridge	171:3a7713b1edbc	963	* @{
AnnaBridge	171:3a7713b1edbc	964	*/
AnnaBridge	171:3a7713b1edbc	965	#define ETH_WATCHDOG_ENABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	966	#define ETH_WATCHDOG_DISABLE 0x00800000U
AnnaBridge	171:3a7713b1edbc	967	/**
AnnaBridge	171:3a7713b1edbc	968	* @}
AnnaBridge	171:3a7713b1edbc	969	*/
AnnaBridge	171:3a7713b1edbc	970
AnnaBridge	171:3a7713b1edbc	971	/** @defgroup ETH_Jabber ETH Jabber
AnnaBridge	171:3a7713b1edbc	972	* @{
AnnaBridge	171:3a7713b1edbc	973	*/
AnnaBridge	171:3a7713b1edbc	974	#define ETH_JABBER_ENABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	975	#define ETH_JABBER_DISABLE 0x00400000U
AnnaBridge	171:3a7713b1edbc	976	/**
AnnaBridge	171:3a7713b1edbc	977	* @}
AnnaBridge	171:3a7713b1edbc	978	*/
AnnaBridge	171:3a7713b1edbc	979
AnnaBridge	171:3a7713b1edbc	980	/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
AnnaBridge	171:3a7713b1edbc	981	* @{
AnnaBridge	171:3a7713b1edbc	982	*/
AnnaBridge	171:3a7713b1edbc	983	#define ETH_INTERFRAMEGAP_96BIT 0x00000000U /!< minimum IFG between frames during transmission is 96Bit /
AnnaBridge	171:3a7713b1edbc	984	#define ETH_INTERFRAMEGAP_88BIT 0x00020000U /!< minimum IFG between frames during transmission is 88Bit /
AnnaBridge	171:3a7713b1edbc	985	#define ETH_INTERFRAMEGAP_80BIT 0x00040000U /!< minimum IFG between frames during transmission is 80Bit /
AnnaBridge	171:3a7713b1edbc	986	#define ETH_INTERFRAMEGAP_72BIT 0x00060000U /!< minimum IFG between frames during transmission is 72Bit /
AnnaBridge	171:3a7713b1edbc	987	#define ETH_INTERFRAMEGAP_64BIT 0x00080000U /!< minimum IFG between frames during transmission is 64Bit /
AnnaBridge	171:3a7713b1edbc	988	#define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /!< minimum IFG between frames during transmission is 56Bit /
AnnaBridge	171:3a7713b1edbc	989	#define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /!< minimum IFG between frames during transmission is 48Bit /
AnnaBridge	171:3a7713b1edbc	990	#define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /!< minimum IFG between frames during transmission is 40Bit /
AnnaBridge	171:3a7713b1edbc	991	/**
AnnaBridge	171:3a7713b1edbc	992	* @}
AnnaBridge	171:3a7713b1edbc	993	*/
AnnaBridge	171:3a7713b1edbc	994
AnnaBridge	171:3a7713b1edbc	995	/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
AnnaBridge	171:3a7713b1edbc	996	* @{
AnnaBridge	171:3a7713b1edbc	997	*/
AnnaBridge	171:3a7713b1edbc	998	#define ETH_CARRIERSENCE_ENABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	999	#define ETH_CARRIERSENCE_DISABLE 0x00010000U
AnnaBridge	171:3a7713b1edbc	1000	/**
AnnaBridge	171:3a7713b1edbc	1001	* @}
AnnaBridge	171:3a7713b1edbc	1002	*/
AnnaBridge	171:3a7713b1edbc	1003
AnnaBridge	171:3a7713b1edbc	1004	/** @defgroup ETH_Receive_Own ETH Receive Own
AnnaBridge	171:3a7713b1edbc	1005	* @{
AnnaBridge	171:3a7713b1edbc	1006	*/
AnnaBridge	171:3a7713b1edbc	1007	#define ETH_RECEIVEOWN_ENABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1008	#define ETH_RECEIVEOWN_DISABLE 0x00002000U
AnnaBridge	171:3a7713b1edbc	1009	/**
AnnaBridge	171:3a7713b1edbc	1010	* @}
AnnaBridge	171:3a7713b1edbc	1011	*/
AnnaBridge	171:3a7713b1edbc	1012
AnnaBridge	171:3a7713b1edbc	1013	/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
AnnaBridge	171:3a7713b1edbc	1014	* @{
AnnaBridge	171:3a7713b1edbc	1015	*/
AnnaBridge	171:3a7713b1edbc	1016	#define ETH_LOOPBACKMODE_ENABLE 0x00001000U
AnnaBridge	171:3a7713b1edbc	1017	#define ETH_LOOPBACKMODE_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1018	/**
AnnaBridge	171:3a7713b1edbc	1019	* @}
AnnaBridge	171:3a7713b1edbc	1020	*/
AnnaBridge	171:3a7713b1edbc	1021
AnnaBridge	171:3a7713b1edbc	1022	/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
AnnaBridge	171:3a7713b1edbc	1023	* @{
AnnaBridge	171:3a7713b1edbc	1024	*/
AnnaBridge	171:3a7713b1edbc	1025	#define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U
AnnaBridge	171:3a7713b1edbc	1026	#define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1027	/**
AnnaBridge	171:3a7713b1edbc	1028	* @}
AnnaBridge	171:3a7713b1edbc	1029	*/
AnnaBridge	171:3a7713b1edbc	1030
AnnaBridge	171:3a7713b1edbc	1031	/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
AnnaBridge	171:3a7713b1edbc	1032	* @{
AnnaBridge	171:3a7713b1edbc	1033	*/
AnnaBridge	171:3a7713b1edbc	1034	#define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1035	#define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U
AnnaBridge	171:3a7713b1edbc	1036	/**
AnnaBridge	171:3a7713b1edbc	1037	* @}
AnnaBridge	171:3a7713b1edbc	1038	*/
AnnaBridge	171:3a7713b1edbc	1039
AnnaBridge	171:3a7713b1edbc	1040	/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
AnnaBridge	171:3a7713b1edbc	1041	* @{
AnnaBridge	171:3a7713b1edbc	1042	*/
AnnaBridge	171:3a7713b1edbc	1043	#define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U
AnnaBridge	171:3a7713b1edbc	1044	#define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1045	/**
AnnaBridge	171:3a7713b1edbc	1046	* @}
AnnaBridge	171:3a7713b1edbc	1047	*/
AnnaBridge	171:3a7713b1edbc	1048
AnnaBridge	171:3a7713b1edbc	1049	/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
AnnaBridge	171:3a7713b1edbc	1050	* @{
AnnaBridge	171:3a7713b1edbc	1051	*/
AnnaBridge	171:3a7713b1edbc	1052	#define ETH_BACKOFFLIMIT_10 0x00000000U
AnnaBridge	171:3a7713b1edbc	1053	#define ETH_BACKOFFLIMIT_8 0x00000020U
AnnaBridge	171:3a7713b1edbc	1054	#define ETH_BACKOFFLIMIT_4 0x00000040U
AnnaBridge	171:3a7713b1edbc	1055	#define ETH_BACKOFFLIMIT_1 0x00000060U
AnnaBridge	171:3a7713b1edbc	1056	/**
AnnaBridge	171:3a7713b1edbc	1057	* @}
AnnaBridge	171:3a7713b1edbc	1058	*/
AnnaBridge	171:3a7713b1edbc	1059
AnnaBridge	171:3a7713b1edbc	1060	/** @defgroup ETH_Deferral_Check ETH Deferral Check
AnnaBridge	171:3a7713b1edbc	1061	* @{
AnnaBridge	171:3a7713b1edbc	1062	*/
AnnaBridge	171:3a7713b1edbc	1063	#define ETH_DEFFERRALCHECK_ENABLE 0x00000010U
AnnaBridge	171:3a7713b1edbc	1064	#define ETH_DEFFERRALCHECK_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1065	/**
AnnaBridge	171:3a7713b1edbc	1066	* @}
AnnaBridge	171:3a7713b1edbc	1067	*/
AnnaBridge	171:3a7713b1edbc	1068
AnnaBridge	171:3a7713b1edbc	1069	/** @defgroup ETH_Receive_All ETH Receive All
AnnaBridge	171:3a7713b1edbc	1070	* @{
AnnaBridge	171:3a7713b1edbc	1071	*/
AnnaBridge	171:3a7713b1edbc	1072	#define ETH_RECEIVEALL_ENABLE 0x80000000U
AnnaBridge	171:3a7713b1edbc	1073	#define ETH_RECEIVEAll_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1074	/**
AnnaBridge	171:3a7713b1edbc	1075	* @}
AnnaBridge	171:3a7713b1edbc	1076	*/
AnnaBridge	171:3a7713b1edbc	1077
AnnaBridge	171:3a7713b1edbc	1078	/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
AnnaBridge	171:3a7713b1edbc	1079	* @{
AnnaBridge	171:3a7713b1edbc	1080	*/
AnnaBridge	171:3a7713b1edbc	1081	#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U
AnnaBridge	171:3a7713b1edbc	1082	#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U
AnnaBridge	171:3a7713b1edbc	1083	#define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1084	/**
AnnaBridge	171:3a7713b1edbc	1085	* @}
AnnaBridge	171:3a7713b1edbc	1086	*/
AnnaBridge	171:3a7713b1edbc	1087
AnnaBridge	171:3a7713b1edbc	1088	/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
AnnaBridge	171:3a7713b1edbc	1089	* @{
AnnaBridge	171:3a7713b1edbc	1090	*/
AnnaBridge	171:3a7713b1edbc	1091	#define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /!< MAC filters all control frames from reaching the application /
AnnaBridge	171:3a7713b1edbc	1092	#define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /!< MAC forwards all control frames to application even if they fail the Address Filter /
AnnaBridge	171:3a7713b1edbc	1093	#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /!< MAC forwards control frames that pass the Address Filter. /
AnnaBridge	171:3a7713b1edbc	1094	/**
AnnaBridge	171:3a7713b1edbc	1095	* @}
AnnaBridge	171:3a7713b1edbc	1096	*/
AnnaBridge	171:3a7713b1edbc	1097
AnnaBridge	171:3a7713b1edbc	1098	/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
AnnaBridge	171:3a7713b1edbc	1099	* @{
AnnaBridge	171:3a7713b1edbc	1100	*/
AnnaBridge	171:3a7713b1edbc	1101	#define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1102	#define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U
AnnaBridge	171:3a7713b1edbc	1103	/**
AnnaBridge	171:3a7713b1edbc	1104	* @}
AnnaBridge	171:3a7713b1edbc	1105	*/
AnnaBridge	171:3a7713b1edbc	1106
AnnaBridge	171:3a7713b1edbc	1107	/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
AnnaBridge	171:3a7713b1edbc	1108	* @{
AnnaBridge	171:3a7713b1edbc	1109	*/
AnnaBridge	171:3a7713b1edbc	1110	#define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U
AnnaBridge	171:3a7713b1edbc	1111	#define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U
AnnaBridge	171:3a7713b1edbc	1112	/**
AnnaBridge	171:3a7713b1edbc	1113	* @}
AnnaBridge	171:3a7713b1edbc	1114	*/
AnnaBridge	171:3a7713b1edbc	1115
AnnaBridge	171:3a7713b1edbc	1116	/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
AnnaBridge	171:3a7713b1edbc	1117	* @{
AnnaBridge	171:3a7713b1edbc	1118	*/
AnnaBridge	171:3a7713b1edbc	1119	#define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U
AnnaBridge	171:3a7713b1edbc	1120	#define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1121	/**
AnnaBridge	171:3a7713b1edbc	1122	* @}
AnnaBridge	171:3a7713b1edbc	1123	*/
AnnaBridge	171:3a7713b1edbc	1124
AnnaBridge	171:3a7713b1edbc	1125	/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
AnnaBridge	171:3a7713b1edbc	1126	* @{
AnnaBridge	171:3a7713b1edbc	1127	*/
AnnaBridge	171:3a7713b1edbc	1128	#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U
AnnaBridge	171:3a7713b1edbc	1129	#define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U
AnnaBridge	171:3a7713b1edbc	1130	#define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U
AnnaBridge	171:3a7713b1edbc	1131	#define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U
AnnaBridge	171:3a7713b1edbc	1132	/**
AnnaBridge	171:3a7713b1edbc	1133	* @}
AnnaBridge	171:3a7713b1edbc	1134	*/
AnnaBridge	171:3a7713b1edbc	1135
AnnaBridge	171:3a7713b1edbc	1136	/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
AnnaBridge	171:3a7713b1edbc	1137	* @{
AnnaBridge	171:3a7713b1edbc	1138	*/
AnnaBridge	171:3a7713b1edbc	1139	#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
AnnaBridge	171:3a7713b1edbc	1140	#define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U
AnnaBridge	171:3a7713b1edbc	1141	#define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U
AnnaBridge	171:3a7713b1edbc	1142	/**
AnnaBridge	171:3a7713b1edbc	1143	* @}
AnnaBridge	171:3a7713b1edbc	1144	*/
AnnaBridge	171:3a7713b1edbc	1145
AnnaBridge	171:3a7713b1edbc	1146	/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
AnnaBridge	171:3a7713b1edbc	1147	* @{
AnnaBridge	171:3a7713b1edbc	1148	*/
AnnaBridge	171:3a7713b1edbc	1149	#define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1150	#define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U
AnnaBridge	171:3a7713b1edbc	1151	/**
AnnaBridge	171:3a7713b1edbc	1152	* @}
AnnaBridge	171:3a7713b1edbc	1153	*/
AnnaBridge	171:3a7713b1edbc	1154
AnnaBridge	171:3a7713b1edbc	1155	/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
AnnaBridge	171:3a7713b1edbc	1156	* @{
AnnaBridge	171:3a7713b1edbc	1157	*/
AnnaBridge	171:3a7713b1edbc	1158	#define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /!< Pause time minus 4 slot times /
AnnaBridge	171:3a7713b1edbc	1159	#define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /!< Pause time minus 28 slot times /
AnnaBridge	171:3a7713b1edbc	1160	#define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /!< Pause time minus 144 slot times /
AnnaBridge	171:3a7713b1edbc	1161	#define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /!< Pause time minus 256 slot times /
AnnaBridge	171:3a7713b1edbc	1162	/**
AnnaBridge	171:3a7713b1edbc	1163	* @}
AnnaBridge	171:3a7713b1edbc	1164	*/
AnnaBridge	171:3a7713b1edbc	1165
AnnaBridge	171:3a7713b1edbc	1166	/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
AnnaBridge	171:3a7713b1edbc	1167	* @{
AnnaBridge	171:3a7713b1edbc	1168	*/
AnnaBridge	171:3a7713b1edbc	1169	#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U
AnnaBridge	171:3a7713b1edbc	1170	#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1171	/**
AnnaBridge	171:3a7713b1edbc	1172	* @}
AnnaBridge	171:3a7713b1edbc	1173	*/
AnnaBridge	171:3a7713b1edbc	1174
AnnaBridge	171:3a7713b1edbc	1175	/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
AnnaBridge	171:3a7713b1edbc	1176	* @{
AnnaBridge	171:3a7713b1edbc	1177	*/
AnnaBridge	171:3a7713b1edbc	1178	#define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U
AnnaBridge	171:3a7713b1edbc	1179	#define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1180	/**
AnnaBridge	171:3a7713b1edbc	1181	* @}
AnnaBridge	171:3a7713b1edbc	1182	*/
AnnaBridge	171:3a7713b1edbc	1183
AnnaBridge	171:3a7713b1edbc	1184	/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
AnnaBridge	171:3a7713b1edbc	1185	* @{
AnnaBridge	171:3a7713b1edbc	1186	*/
AnnaBridge	171:3a7713b1edbc	1187	#define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U
AnnaBridge	171:3a7713b1edbc	1188	#define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1189	/**
AnnaBridge	171:3a7713b1edbc	1190	* @}
AnnaBridge	171:3a7713b1edbc	1191	*/
AnnaBridge	171:3a7713b1edbc	1192
AnnaBridge	171:3a7713b1edbc	1193	/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
AnnaBridge	171:3a7713b1edbc	1194	* @{
AnnaBridge	171:3a7713b1edbc	1195	*/
AnnaBridge	171:3a7713b1edbc	1196	#define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U
AnnaBridge	171:3a7713b1edbc	1197	#define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U
AnnaBridge	171:3a7713b1edbc	1198	/**
AnnaBridge	171:3a7713b1edbc	1199	* @}
AnnaBridge	171:3a7713b1edbc	1200	*/
AnnaBridge	171:3a7713b1edbc	1201
AnnaBridge	171:3a7713b1edbc	1202	/** @defgroup ETH_MAC_addresses ETH MAC addresses
AnnaBridge	171:3a7713b1edbc	1203	* @{
AnnaBridge	171:3a7713b1edbc	1204	*/
AnnaBridge	171:3a7713b1edbc	1205	#define ETH_MAC_ADDRESS0 0x00000000U
AnnaBridge	171:3a7713b1edbc	1206	#define ETH_MAC_ADDRESS1 0x00000008U
AnnaBridge	171:3a7713b1edbc	1207	#define ETH_MAC_ADDRESS2 0x00000010U
AnnaBridge	171:3a7713b1edbc	1208	#define ETH_MAC_ADDRESS3 0x00000018U
AnnaBridge	171:3a7713b1edbc	1209	/**
AnnaBridge	171:3a7713b1edbc	1210	* @}
AnnaBridge	171:3a7713b1edbc	1211	*/
AnnaBridge	171:3a7713b1edbc	1212
AnnaBridge	171:3a7713b1edbc	1213	/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
AnnaBridge	171:3a7713b1edbc	1214	* @{
AnnaBridge	171:3a7713b1edbc	1215	*/
AnnaBridge	171:3a7713b1edbc	1216	#define ETH_MAC_ADDRESSFILTER_SA 0x00000000U
AnnaBridge	171:3a7713b1edbc	1217	#define ETH_MAC_ADDRESSFILTER_DA 0x00000008U
AnnaBridge	171:3a7713b1edbc	1218	/**
AnnaBridge	171:3a7713b1edbc	1219	* @}
AnnaBridge	171:3a7713b1edbc	1220	*/
AnnaBridge	171:3a7713b1edbc	1221
AnnaBridge	171:3a7713b1edbc	1222	/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
AnnaBridge	171:3a7713b1edbc	1223	* @{
AnnaBridge	171:3a7713b1edbc	1224	*/
AnnaBridge	171:3a7713b1edbc	1225	#define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /!< Mask MAC Address high reg bits [15:8] /
AnnaBridge	171:3a7713b1edbc	1226	#define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /!< Mask MAC Address high reg bits [7:0] /
AnnaBridge	171:3a7713b1edbc	1227	#define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /!< Mask MAC Address low reg bits [31:24] /
AnnaBridge	171:3a7713b1edbc	1228	#define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /!< Mask MAC Address low reg bits [23:16] /
AnnaBridge	171:3a7713b1edbc	1229	#define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /!< Mask MAC Address low reg bits [15:8] /
AnnaBridge	171:3a7713b1edbc	1230	#define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /!< Mask MAC Address low reg bits [70] /
AnnaBridge	171:3a7713b1edbc	1231	/**
AnnaBridge	171:3a7713b1edbc	1232	* @}
AnnaBridge	171:3a7713b1edbc	1233	*/
AnnaBridge	171:3a7713b1edbc	1234
AnnaBridge	171:3a7713b1edbc	1235	/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
AnnaBridge	171:3a7713b1edbc	1236	* @{
AnnaBridge	171:3a7713b1edbc	1237	*/
AnnaBridge	171:3a7713b1edbc	1238	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1239	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U
AnnaBridge	171:3a7713b1edbc	1240	/**
AnnaBridge	171:3a7713b1edbc	1241	* @}
AnnaBridge	171:3a7713b1edbc	1242	*/
AnnaBridge	171:3a7713b1edbc	1243
AnnaBridge	171:3a7713b1edbc	1244	/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
AnnaBridge	171:3a7713b1edbc	1245	* @{
AnnaBridge	171:3a7713b1edbc	1246	*/
AnnaBridge	171:3a7713b1edbc	1247	#define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U
AnnaBridge	171:3a7713b1edbc	1248	#define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1249	/**
AnnaBridge	171:3a7713b1edbc	1250	* @}
AnnaBridge	171:3a7713b1edbc	1251	*/
AnnaBridge	171:3a7713b1edbc	1252
AnnaBridge	171:3a7713b1edbc	1253	/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
AnnaBridge	171:3a7713b1edbc	1254	* @{
AnnaBridge	171:3a7713b1edbc	1255	*/
AnnaBridge	171:3a7713b1edbc	1256	#define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1257	#define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U
AnnaBridge	171:3a7713b1edbc	1258	/**
AnnaBridge	171:3a7713b1edbc	1259	* @}
AnnaBridge	171:3a7713b1edbc	1260	*/
AnnaBridge	171:3a7713b1edbc	1261
AnnaBridge	171:3a7713b1edbc	1262	/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
AnnaBridge	171:3a7713b1edbc	1263	* @{
AnnaBridge	171:3a7713b1edbc	1264	*/
AnnaBridge	171:3a7713b1edbc	1265	#define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U
AnnaBridge	171:3a7713b1edbc	1266	#define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1267	/**
AnnaBridge	171:3a7713b1edbc	1268	* @}
AnnaBridge	171:3a7713b1edbc	1269	*/
AnnaBridge	171:3a7713b1edbc	1270
AnnaBridge	171:3a7713b1edbc	1271	/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
AnnaBridge	171:3a7713b1edbc	1272	* @{
AnnaBridge	171:3a7713b1edbc	1273	*/
AnnaBridge	171:3a7713b1edbc	1274	#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /!< threshold level of the MTL Transmit FIFO is 64 Bytes /
AnnaBridge	171:3a7713b1edbc	1275	#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /!< threshold level of the MTL Transmit FIFO is 128 Bytes /
AnnaBridge	171:3a7713b1edbc	1276	#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /!< threshold level of the MTL Transmit FIFO is 192 Bytes /
AnnaBridge	171:3a7713b1edbc	1277	#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /!< threshold level of the MTL Transmit FIFO is 256 Bytes /
AnnaBridge	171:3a7713b1edbc	1278	#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /!< threshold level of the MTL Transmit FIFO is 40 Bytes /
AnnaBridge	171:3a7713b1edbc	1279	#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /!< threshold level of the MTL Transmit FIFO is 32 Bytes /
AnnaBridge	171:3a7713b1edbc	1280	#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /!< threshold level of the MTL Transmit FIFO is 24 Bytes /
AnnaBridge	171:3a7713b1edbc	1281	#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /!< threshold level of the MTL Transmit FIFO is 16 Bytes /
AnnaBridge	171:3a7713b1edbc	1282	/**
AnnaBridge	171:3a7713b1edbc	1283	* @}
AnnaBridge	171:3a7713b1edbc	1284	*/
AnnaBridge	171:3a7713b1edbc	1285
AnnaBridge	171:3a7713b1edbc	1286	/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
AnnaBridge	171:3a7713b1edbc	1287	* @{
AnnaBridge	171:3a7713b1edbc	1288	*/
AnnaBridge	171:3a7713b1edbc	1289	#define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U
AnnaBridge	171:3a7713b1edbc	1290	#define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1291	/**
AnnaBridge	171:3a7713b1edbc	1292	* @}
AnnaBridge	171:3a7713b1edbc	1293	*/
AnnaBridge	171:3a7713b1edbc	1294
AnnaBridge	171:3a7713b1edbc	1295	/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
AnnaBridge	171:3a7713b1edbc	1296	* @{
AnnaBridge	171:3a7713b1edbc	1297	*/
AnnaBridge	171:3a7713b1edbc	1298	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U
AnnaBridge	171:3a7713b1edbc	1299	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1300	/**
AnnaBridge	171:3a7713b1edbc	1301	* @}
AnnaBridge	171:3a7713b1edbc	1302	*/
AnnaBridge	171:3a7713b1edbc	1303
AnnaBridge	171:3a7713b1edbc	1304	/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
AnnaBridge	171:3a7713b1edbc	1305	* @{
AnnaBridge	171:3a7713b1edbc	1306	*/
AnnaBridge	171:3a7713b1edbc	1307	#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /!< threshold level of the MTL Receive FIFO is 64 Bytes /
AnnaBridge	171:3a7713b1edbc	1308	#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /!< threshold level of the MTL Receive FIFO is 32 Bytes /
AnnaBridge	171:3a7713b1edbc	1309	#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /!< threshold level of the MTL Receive FIFO is 96 Bytes /
AnnaBridge	171:3a7713b1edbc	1310	#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /!< threshold level of the MTL Receive FIFO is 128 Bytes /
AnnaBridge	171:3a7713b1edbc	1311	/**
AnnaBridge	171:3a7713b1edbc	1312	* @}
AnnaBridge	171:3a7713b1edbc	1313	*/
AnnaBridge	171:3a7713b1edbc	1314
AnnaBridge	171:3a7713b1edbc	1315	/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
AnnaBridge	171:3a7713b1edbc	1316	* @{
AnnaBridge	171:3a7713b1edbc	1317	*/
AnnaBridge	171:3a7713b1edbc	1318	#define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U
AnnaBridge	171:3a7713b1edbc	1319	#define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1320	/**
AnnaBridge	171:3a7713b1edbc	1321	* @}
AnnaBridge	171:3a7713b1edbc	1322	*/
AnnaBridge	171:3a7713b1edbc	1323
AnnaBridge	171:3a7713b1edbc	1324	/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
AnnaBridge	171:3a7713b1edbc	1325	* @{
AnnaBridge	171:3a7713b1edbc	1326	*/
AnnaBridge	171:3a7713b1edbc	1327	#define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U
AnnaBridge	171:3a7713b1edbc	1328	#define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1329	/**
AnnaBridge	171:3a7713b1edbc	1330	* @}
AnnaBridge	171:3a7713b1edbc	1331	*/
AnnaBridge	171:3a7713b1edbc	1332
AnnaBridge	171:3a7713b1edbc	1333	/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
AnnaBridge	171:3a7713b1edbc	1334	* @{
AnnaBridge	171:3a7713b1edbc	1335	*/
AnnaBridge	171:3a7713b1edbc	1336	#define ETH_FIXEDBURST_ENABLE 0x00010000U
AnnaBridge	171:3a7713b1edbc	1337	#define ETH_FIXEDBURST_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1338	/**
AnnaBridge	171:3a7713b1edbc	1339	* @}
AnnaBridge	171:3a7713b1edbc	1340	*/
AnnaBridge	171:3a7713b1edbc	1341
AnnaBridge	171:3a7713b1edbc	1342	/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
AnnaBridge	171:3a7713b1edbc	1343	* @{
AnnaBridge	171:3a7713b1edbc	1344	*/
AnnaBridge	171:3a7713b1edbc	1345	#define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /!< maximum number of beats to be transferred in one RxDMA transaction is 1 /
AnnaBridge	171:3a7713b1edbc	1346	#define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /!< maximum number of beats to be transferred in one RxDMA transaction is 2 /
AnnaBridge	171:3a7713b1edbc	1347	#define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
AnnaBridge	171:3a7713b1edbc	1348	#define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
AnnaBridge	171:3a7713b1edbc	1349	#define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
AnnaBridge	171:3a7713b1edbc	1350	#define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
AnnaBridge	171:3a7713b1edbc	1351	#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
AnnaBridge	171:3a7713b1edbc	1352	#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
AnnaBridge	171:3a7713b1edbc	1353	#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
AnnaBridge	171:3a7713b1edbc	1354	#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
AnnaBridge	171:3a7713b1edbc	1355	#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /!< maximum number of beats to be transferred in one RxDMA transaction is 64 /
AnnaBridge	171:3a7713b1edbc	1356	#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /!< maximum number of beats to be transferred in one RxDMA transaction is 128 /
AnnaBridge	171:3a7713b1edbc	1357	/**
AnnaBridge	171:3a7713b1edbc	1358	* @}
AnnaBridge	171:3a7713b1edbc	1359	*/
AnnaBridge	171:3a7713b1edbc	1360
AnnaBridge	171:3a7713b1edbc	1361	/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
AnnaBridge	171:3a7713b1edbc	1362	* @{
AnnaBridge	171:3a7713b1edbc	1363	*/
AnnaBridge	171:3a7713b1edbc	1364	#define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 /
AnnaBridge	171:3a7713b1edbc	1365	#define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 /
AnnaBridge	171:3a7713b1edbc	1366	#define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
AnnaBridge	171:3a7713b1edbc	1367	#define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
AnnaBridge	171:3a7713b1edbc	1368	#define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
AnnaBridge	171:3a7713b1edbc	1369	#define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
AnnaBridge	171:3a7713b1edbc	1370	#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
AnnaBridge	171:3a7713b1edbc	1371	#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
AnnaBridge	171:3a7713b1edbc	1372	#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
AnnaBridge	171:3a7713b1edbc	1373	#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
AnnaBridge	171:3a7713b1edbc	1374	#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 /
AnnaBridge	171:3a7713b1edbc	1375	#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 /
AnnaBridge	171:3a7713b1edbc	1376	/**
AnnaBridge	171:3a7713b1edbc	1377	* @}
AnnaBridge	171:3a7713b1edbc	1378	*/
AnnaBridge	171:3a7713b1edbc	1379
AnnaBridge	171:3a7713b1edbc	1380	/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
AnnaBridge	171:3a7713b1edbc	1381	* @{
AnnaBridge	171:3a7713b1edbc	1382	*/
AnnaBridge	171:3a7713b1edbc	1383	#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE 0x00000080U
AnnaBridge	171:3a7713b1edbc	1384	#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	1385	/**
AnnaBridge	171:3a7713b1edbc	1386	* @}
AnnaBridge	171:3a7713b1edbc	1387	*/
AnnaBridge	171:3a7713b1edbc	1388
AnnaBridge	171:3a7713b1edbc	1389	/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
AnnaBridge	171:3a7713b1edbc	1390	* @{
AnnaBridge	171:3a7713b1edbc	1391	*/
AnnaBridge	171:3a7713b1edbc	1392	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U
AnnaBridge	171:3a7713b1edbc	1393	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U
AnnaBridge	171:3a7713b1edbc	1394	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U
AnnaBridge	171:3a7713b1edbc	1395	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U
AnnaBridge	171:3a7713b1edbc	1396	#define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U
AnnaBridge	171:3a7713b1edbc	1397	/**
AnnaBridge	171:3a7713b1edbc	1398	* @}
AnnaBridge	171:3a7713b1edbc	1399	*/
AnnaBridge	171:3a7713b1edbc	1400
AnnaBridge	171:3a7713b1edbc	1401	/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
AnnaBridge	171:3a7713b1edbc	1402	* @{
AnnaBridge	171:3a7713b1edbc	1403	*/
AnnaBridge	171:3a7713b1edbc	1404	#define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /!< Last Segment /
AnnaBridge	171:3a7713b1edbc	1405	#define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /!< First Segment /
AnnaBridge	171:3a7713b1edbc	1406	/**
AnnaBridge	171:3a7713b1edbc	1407	* @}
AnnaBridge	171:3a7713b1edbc	1408	*/
AnnaBridge	171:3a7713b1edbc	1409
AnnaBridge	171:3a7713b1edbc	1410	/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
AnnaBridge	171:3a7713b1edbc	1411	* @{
AnnaBridge	171:3a7713b1edbc	1412	*/
AnnaBridge	171:3a7713b1edbc	1413	#define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /!< Checksum engine bypass /
AnnaBridge	171:3a7713b1edbc	1414	#define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /!< IPv4 header checksum insertion /
AnnaBridge	171:3a7713b1edbc	1415	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present /
AnnaBridge	171:3a7713b1edbc	1416	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /!< TCP/UDP/ICMP checksum fully in hardware including pseudo header /
AnnaBridge	171:3a7713b1edbc	1417	/**
AnnaBridge	171:3a7713b1edbc	1418	* @}
AnnaBridge	171:3a7713b1edbc	1419	*/
AnnaBridge	171:3a7713b1edbc	1420
AnnaBridge	171:3a7713b1edbc	1421	/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
AnnaBridge	171:3a7713b1edbc	1422	* @{
AnnaBridge	171:3a7713b1edbc	1423	*/
AnnaBridge	171:3a7713b1edbc	1424	#define ETH_DMARXDESC_BUFFER1 0x00000000U /!< DMA Rx Desc Buffer1 /
AnnaBridge	171:3a7713b1edbc	1425	#define ETH_DMARXDESC_BUFFER2 0x00000001U /!< DMA Rx Desc Buffer2 /
AnnaBridge	171:3a7713b1edbc	1426	/**
AnnaBridge	171:3a7713b1edbc	1427	* @}
AnnaBridge	171:3a7713b1edbc	1428	*/
AnnaBridge	171:3a7713b1edbc	1429
AnnaBridge	171:3a7713b1edbc	1430	/** @defgroup ETH_PMT_Flags ETH PMT Flags
AnnaBridge	171:3a7713b1edbc	1431	* @{
AnnaBridge	171:3a7713b1edbc	1432	*/
AnnaBridge	171:3a7713b1edbc	1433	#define ETH_PMT_FLAG_WUFFRPR 0x80000000U /!< Wake-Up Frame Filter Register Pointer Reset /
AnnaBridge	171:3a7713b1edbc	1434	#define ETH_PMT_FLAG_WUFR 0x00000040U /!< Wake-Up Frame Received /
AnnaBridge	171:3a7713b1edbc	1435	#define ETH_PMT_FLAG_MPR 0x00000020U /!< Magic Packet Received /
AnnaBridge	171:3a7713b1edbc	1436	/**
AnnaBridge	171:3a7713b1edbc	1437	* @}
AnnaBridge	171:3a7713b1edbc	1438	*/
AnnaBridge	171:3a7713b1edbc	1439
AnnaBridge	171:3a7713b1edbc	1440	/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
AnnaBridge	171:3a7713b1edbc	1441	* @{
AnnaBridge	171:3a7713b1edbc	1442	*/
AnnaBridge	171:3a7713b1edbc	1443	#define ETH_MMC_IT_TGF 0x00200000U /!< When Tx good frame counter reaches half the maximum value /
AnnaBridge	171:3a7713b1edbc	1444	#define ETH_MMC_IT_TGFMSC 0x00008000U /!< When Tx good multi col counter reaches half the maximum value /
AnnaBridge	171:3a7713b1edbc	1445	#define ETH_MMC_IT_TGFSC 0x00004000U /!< When Tx good single col counter reaches half the maximum value /
AnnaBridge	171:3a7713b1edbc	1446	/**
AnnaBridge	171:3a7713b1edbc	1447	* @}
AnnaBridge	171:3a7713b1edbc	1448	*/
AnnaBridge	171:3a7713b1edbc	1449
AnnaBridge	171:3a7713b1edbc	1450	/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
AnnaBridge	171:3a7713b1edbc	1451	* @{
AnnaBridge	171:3a7713b1edbc	1452	*/
AnnaBridge	171:3a7713b1edbc	1453	#define ETH_MMC_IT_RGUF 0x10020000U /!< When Rx good unicast frames counter reaches half the maximum value /
AnnaBridge	171:3a7713b1edbc	1454	#define ETH_MMC_IT_RFAE 0x10000040U /!< When Rx alignment error counter reaches half the maximum value /
AnnaBridge	171:3a7713b1edbc	1455	#define ETH_MMC_IT_RFCE 0x10000020U /!< When Rx crc error counter reaches half the maximum value /
AnnaBridge	171:3a7713b1edbc	1456	/**
AnnaBridge	171:3a7713b1edbc	1457	* @}
AnnaBridge	171:3a7713b1edbc	1458	*/
AnnaBridge	171:3a7713b1edbc	1459
AnnaBridge	171:3a7713b1edbc	1460	/** @defgroup ETH_MAC_Flags ETH MAC Flags
AnnaBridge	171:3a7713b1edbc	1461	* @{
AnnaBridge	171:3a7713b1edbc	1462	*/
AnnaBridge	171:3a7713b1edbc	1463	#define ETH_MAC_FLAG_TST 0x00000200U /!< Time stamp trigger flag (on MAC) /
AnnaBridge	171:3a7713b1edbc	1464	#define ETH_MAC_FLAG_MMCT 0x00000040U /!< MMC transmit flag /
AnnaBridge	171:3a7713b1edbc	1465	#define ETH_MAC_FLAG_MMCR 0x00000020U /!< MMC receive flag /
AnnaBridge	171:3a7713b1edbc	1466	#define ETH_MAC_FLAG_MMC 0x00000010U /!< MMC flag (on MAC) /
AnnaBridge	171:3a7713b1edbc	1467	#define ETH_MAC_FLAG_PMT 0x00000008U /!< PMT flag (on MAC) /
AnnaBridge	171:3a7713b1edbc	1468	/**
AnnaBridge	171:3a7713b1edbc	1469	* @}
AnnaBridge	171:3a7713b1edbc	1470	*/
AnnaBridge	171:3a7713b1edbc	1471
AnnaBridge	171:3a7713b1edbc	1472	/** @defgroup ETH_DMA_Flags ETH DMA Flags
AnnaBridge	171:3a7713b1edbc	1473	* @{
AnnaBridge	171:3a7713b1edbc	1474	*/
AnnaBridge	171:3a7713b1edbc	1475	#define ETH_DMA_FLAG_TST 0x20000000U /!< Time-stamp trigger interrupt (on DMA) /
AnnaBridge	171:3a7713b1edbc	1476	#define ETH_DMA_FLAG_PMT 0x10000000U /!< PMT interrupt (on DMA) /
AnnaBridge	171:3a7713b1edbc	1477	#define ETH_DMA_FLAG_MMC 0x08000000U /!< MMC interrupt (on DMA) /
AnnaBridge	171:3a7713b1edbc	1478	#define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /!< Error bits 0-Rx DMA, 1-Tx DMA /
AnnaBridge	171:3a7713b1edbc	1479	#define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /!< Error bits 0-write transfer, 1-read transfer /
AnnaBridge	171:3a7713b1edbc	1480	#define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /!< Error bits 0-data buffer, 1-desc. access /
AnnaBridge	171:3a7713b1edbc	1481	#define ETH_DMA_FLAG_NIS 0x00010000U /!< Normal interrupt summary flag /
AnnaBridge	171:3a7713b1edbc	1482	#define ETH_DMA_FLAG_AIS 0x00008000U /!< Abnormal interrupt summary flag /
AnnaBridge	171:3a7713b1edbc	1483	#define ETH_DMA_FLAG_ER 0x00004000U /!< Early receive flag /
AnnaBridge	171:3a7713b1edbc	1484	#define ETH_DMA_FLAG_FBE 0x00002000U /!< Fatal bus error flag /
AnnaBridge	171:3a7713b1edbc	1485	#define ETH_DMA_FLAG_ET 0x00000400U /!< Early transmit flag /
AnnaBridge	171:3a7713b1edbc	1486	#define ETH_DMA_FLAG_RWT 0x00000200U /!< Receive watchdog timeout flag /
AnnaBridge	171:3a7713b1edbc	1487	#define ETH_DMA_FLAG_RPS 0x00000100U /!< Receive process stopped flag /
AnnaBridge	171:3a7713b1edbc	1488	#define ETH_DMA_FLAG_RBU 0x00000080U /!< Receive buffer unavailable flag /
AnnaBridge	171:3a7713b1edbc	1489	#define ETH_DMA_FLAG_R 0x00000040U /!< Receive flag /
AnnaBridge	171:3a7713b1edbc	1490	#define ETH_DMA_FLAG_TU 0x00000020U /!< Underflow flag /
AnnaBridge	171:3a7713b1edbc	1491	#define ETH_DMA_FLAG_RO 0x00000010U /!< Overflow flag /
AnnaBridge	171:3a7713b1edbc	1492	#define ETH_DMA_FLAG_TJT 0x00000008U /!< Transmit jabber timeout flag /
AnnaBridge	171:3a7713b1edbc	1493	#define ETH_DMA_FLAG_TBU 0x00000004U /!< Transmit buffer unavailable flag /
AnnaBridge	171:3a7713b1edbc	1494	#define ETH_DMA_FLAG_TPS 0x00000002U /!< Transmit process stopped flag /
AnnaBridge	171:3a7713b1edbc	1495	#define ETH_DMA_FLAG_T 0x00000001U /!< Transmit flag /
AnnaBridge	171:3a7713b1edbc	1496	/**
AnnaBridge	171:3a7713b1edbc	1497	* @}
AnnaBridge	171:3a7713b1edbc	1498	*/
AnnaBridge	171:3a7713b1edbc	1499
AnnaBridge	171:3a7713b1edbc	1500	/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
AnnaBridge	171:3a7713b1edbc	1501	* @{
AnnaBridge	171:3a7713b1edbc	1502	*/
AnnaBridge	171:3a7713b1edbc	1503	#define ETH_MAC_IT_TST 0x00000200U /!< Time stamp trigger interrupt (on MAC) /
AnnaBridge	171:3a7713b1edbc	1504	#define ETH_MAC_IT_MMCT 0x00000040U /!< MMC transmit interrupt /
AnnaBridge	171:3a7713b1edbc	1505	#define ETH_MAC_IT_MMCR 0x00000020U /!< MMC receive interrupt /
AnnaBridge	171:3a7713b1edbc	1506	#define ETH_MAC_IT_MMC 0x00000010U /!< MMC interrupt (on MAC) /
AnnaBridge	171:3a7713b1edbc	1507	#define ETH_MAC_IT_PMT 0x00000008U /!< PMT interrupt (on MAC) /
AnnaBridge	171:3a7713b1edbc	1508	/**
AnnaBridge	171:3a7713b1edbc	1509	* @}
AnnaBridge	171:3a7713b1edbc	1510	*/
AnnaBridge	171:3a7713b1edbc	1511
AnnaBridge	171:3a7713b1edbc	1512	/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
AnnaBridge	171:3a7713b1edbc	1513	* @{
AnnaBridge	171:3a7713b1edbc	1514	*/
AnnaBridge	171:3a7713b1edbc	1515	#define ETH_DMA_IT_TST 0x20000000U /!< Time-stamp trigger interrupt (on DMA) /
AnnaBridge	171:3a7713b1edbc	1516	#define ETH_DMA_IT_PMT 0x10000000U /!< PMT interrupt (on DMA) /
AnnaBridge	171:3a7713b1edbc	1517	#define ETH_DMA_IT_MMC 0x08000000U /!< MMC interrupt (on DMA) /
AnnaBridge	171:3a7713b1edbc	1518	#define ETH_DMA_IT_NIS 0x00010000U /!< Normal interrupt summary /
AnnaBridge	171:3a7713b1edbc	1519	#define ETH_DMA_IT_AIS 0x00008000U /!< Abnormal interrupt summary /
AnnaBridge	171:3a7713b1edbc	1520	#define ETH_DMA_IT_ER 0x00004000U /!< Early receive interrupt /
AnnaBridge	171:3a7713b1edbc	1521	#define ETH_DMA_IT_FBE 0x00002000U /!< Fatal bus error interrupt /
AnnaBridge	171:3a7713b1edbc	1522	#define ETH_DMA_IT_ET 0x00000400U /!< Early transmit interrupt /
AnnaBridge	171:3a7713b1edbc	1523	#define ETH_DMA_IT_RWT 0x00000200U /!< Receive watchdog timeout interrupt /
AnnaBridge	171:3a7713b1edbc	1524	#define ETH_DMA_IT_RPS 0x00000100U /!< Receive process stopped interrupt /
AnnaBridge	171:3a7713b1edbc	1525	#define ETH_DMA_IT_RBU 0x00000080U /!< Receive buffer unavailable interrupt /
AnnaBridge	171:3a7713b1edbc	1526	#define ETH_DMA_IT_R 0x00000040U /!< Receive interrupt /
AnnaBridge	171:3a7713b1edbc	1527	#define ETH_DMA_IT_TU 0x00000020U /!< Underflow interrupt /
AnnaBridge	171:3a7713b1edbc	1528	#define ETH_DMA_IT_RO 0x00000010U /!< Overflow interrupt /
AnnaBridge	171:3a7713b1edbc	1529	#define ETH_DMA_IT_TJT 0x00000008U /!< Transmit jabber timeout interrupt /
AnnaBridge	171:3a7713b1edbc	1530	#define ETH_DMA_IT_TBU 0x00000004U /!< Transmit buffer unavailable interrupt /
AnnaBridge	171:3a7713b1edbc	1531	#define ETH_DMA_IT_TPS 0x00000002U /!< Transmit process stopped interrupt /
AnnaBridge	171:3a7713b1edbc	1532	#define ETH_DMA_IT_T 0x00000001U /!< Transmit interrupt /
AnnaBridge	171:3a7713b1edbc	1533	/**
AnnaBridge	171:3a7713b1edbc	1534	* @}
AnnaBridge	171:3a7713b1edbc	1535	*/
AnnaBridge	171:3a7713b1edbc	1536
AnnaBridge	171:3a7713b1edbc	1537	/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
AnnaBridge	171:3a7713b1edbc	1538	* @{
AnnaBridge	171:3a7713b1edbc	1539	*/
AnnaBridge	171:3a7713b1edbc	1540	#define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /!< Stopped - Reset or Stop Tx Command issued /
AnnaBridge	171:3a7713b1edbc	1541	#define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /!< Running - fetching the Tx descriptor /
AnnaBridge	171:3a7713b1edbc	1542	#define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /!< Running - waiting for status /
AnnaBridge	171:3a7713b1edbc	1543	#define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /!< Running - reading the data from host memory /
AnnaBridge	171:3a7713b1edbc	1544	#define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /!< Suspended - Tx Descriptor unavailable /
AnnaBridge	171:3a7713b1edbc	1545	#define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /!< Running - closing Rx descriptor /
AnnaBridge	171:3a7713b1edbc	1546
AnnaBridge	171:3a7713b1edbc	1547	/**
AnnaBridge	171:3a7713b1edbc	1548	* @}
AnnaBridge	171:3a7713b1edbc	1549	*/
AnnaBridge	171:3a7713b1edbc	1550
AnnaBridge	171:3a7713b1edbc	1551
AnnaBridge	171:3a7713b1edbc	1552	/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
AnnaBridge	171:3a7713b1edbc	1553	* @{
AnnaBridge	171:3a7713b1edbc	1554	*/
AnnaBridge	171:3a7713b1edbc	1555	#define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /!< Stopped - Reset or Stop Rx Command issued /
AnnaBridge	171:3a7713b1edbc	1556	#define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /!< Running - fetching the Rx descriptor /
AnnaBridge	171:3a7713b1edbc	1557	#define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /!< Running - waiting for packet /
AnnaBridge	171:3a7713b1edbc	1558	#define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /!< Suspended - Rx Descriptor unavailable /
AnnaBridge	171:3a7713b1edbc	1559	#define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /!< Running - closing descriptor /
AnnaBridge	171:3a7713b1edbc	1560	#define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /!< Running - queuing the receive frame into host memory /
AnnaBridge	171:3a7713b1edbc	1561
AnnaBridge	171:3a7713b1edbc	1562	/**
AnnaBridge	171:3a7713b1edbc	1563	* @}
AnnaBridge	171:3a7713b1edbc	1564	*/
AnnaBridge	171:3a7713b1edbc	1565
AnnaBridge	171:3a7713b1edbc	1566	/** @defgroup ETH_DMA_overflow ETH DMA overflow
AnnaBridge	171:3a7713b1edbc	1567	* @{
AnnaBridge	171:3a7713b1edbc	1568	*/
AnnaBridge	171:3a7713b1edbc	1569	#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /!< Overflow bit for FIFO overflow counter /
AnnaBridge	171:3a7713b1edbc	1570	#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /!< Overflow bit for missed frame counter /
AnnaBridge	171:3a7713b1edbc	1571	/**
AnnaBridge	171:3a7713b1edbc	1572	* @}
AnnaBridge	171:3a7713b1edbc	1573	*/
AnnaBridge	171:3a7713b1edbc	1574
AnnaBridge	171:3a7713b1edbc	1575	/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
AnnaBridge	171:3a7713b1edbc	1576	* @{
AnnaBridge	171:3a7713b1edbc	1577	*/
AnnaBridge	171:3a7713b1edbc	1578	#define ETH_EXTI_LINE_WAKEUP 0x00080000U /!< External interrupt line 19 Connected to the ETH EXTI Line /
AnnaBridge	171:3a7713b1edbc	1579
AnnaBridge	171:3a7713b1edbc	1580	/**
AnnaBridge	171:3a7713b1edbc	1581	* @}
AnnaBridge	171:3a7713b1edbc	1582	*/
AnnaBridge	171:3a7713b1edbc	1583
AnnaBridge	171:3a7713b1edbc	1584	/**
AnnaBridge	171:3a7713b1edbc	1585	* @}
AnnaBridge	171:3a7713b1edbc	1586	*/
AnnaBridge	171:3a7713b1edbc	1587
AnnaBridge	171:3a7713b1edbc	1588	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1589	/** @defgroup ETH_Exported_Macros ETH Exported Macros
AnnaBridge	171:3a7713b1edbc	1590	* @brief macros to handle interrupts and specific clock configurations
AnnaBridge	171:3a7713b1edbc	1591	* @{
AnnaBridge	171:3a7713b1edbc	1592	*/
AnnaBridge	171:3a7713b1edbc	1593
AnnaBridge	171:3a7713b1edbc	1594	/** @brief Reset ETH handle state
AnnaBridge	171:3a7713b1edbc	1595	* @param __HANDLE__: specifies the ETH handle.
AnnaBridge	171:3a7713b1edbc	1596	* @retval None
AnnaBridge	171:3a7713b1edbc	1597	*/
AnnaBridge	171:3a7713b1edbc	1598	#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
AnnaBridge	171:3a7713b1edbc	1599
AnnaBridge	171:3a7713b1edbc	1600	/**
AnnaBridge	171:3a7713b1edbc	1601	* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
AnnaBridge	171:3a7713b1edbc	1602	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1603	* @param __FLAG__: specifies the flag of TDES0 to check.
AnnaBridge	171:3a7713b1edbc	1604	* @retval the ETH_DMATxDescFlag (SET or RESET).
AnnaBridge	171:3a7713b1edbc	1605	*/
AnnaBridge	171:3a7713b1edbc	1606	#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
AnnaBridge	171:3a7713b1edbc	1607
AnnaBridge	171:3a7713b1edbc	1608	/**
AnnaBridge	171:3a7713b1edbc	1609	* @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
AnnaBridge	171:3a7713b1edbc	1610	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1611	* @param __FLAG__: specifies the flag of RDES0 to check.
AnnaBridge	171:3a7713b1edbc	1612	* @retval the ETH_DMATxDescFlag (SET or RESET).
AnnaBridge	171:3a7713b1edbc	1613	*/
AnnaBridge	171:3a7713b1edbc	1614	#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
AnnaBridge	171:3a7713b1edbc	1615
AnnaBridge	171:3a7713b1edbc	1616	/**
AnnaBridge	171:3a7713b1edbc	1617	* @brief Enables the specified DMA Rx Desc receive interrupt.
AnnaBridge	171:3a7713b1edbc	1618	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1619	* @retval None
AnnaBridge	171:3a7713b1edbc	1620	*/
AnnaBridge	171:3a7713b1edbc	1621	#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
AnnaBridge	171:3a7713b1edbc	1622
AnnaBridge	171:3a7713b1edbc	1623	/**
AnnaBridge	171:3a7713b1edbc	1624	* @brief Disables the specified DMA Rx Desc receive interrupt.
AnnaBridge	171:3a7713b1edbc	1625	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1626	* @retval None
AnnaBridge	171:3a7713b1edbc	1627	*/
AnnaBridge	171:3a7713b1edbc	1628	#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize \|= ETH_DMARXDESC_DIC)
AnnaBridge	171:3a7713b1edbc	1629
AnnaBridge	171:3a7713b1edbc	1630	/**
AnnaBridge	171:3a7713b1edbc	1631	* @brief Set the specified DMA Rx Desc Own bit.
AnnaBridge	171:3a7713b1edbc	1632	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1633	* @retval None
AnnaBridge	171:3a7713b1edbc	1634	*/
AnnaBridge	171:3a7713b1edbc	1635	#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status \|= ETH_DMARXDESC_OWN)
AnnaBridge	171:3a7713b1edbc	1636
AnnaBridge	171:3a7713b1edbc	1637	/**
AnnaBridge	171:3a7713b1edbc	1638	* @brief Returns the specified ETHERNET DMA Tx Desc collision count.
AnnaBridge	171:3a7713b1edbc	1639	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1640	* @retval The Transmit descriptor collision counter value.
AnnaBridge	171:3a7713b1edbc	1641	*/
AnnaBridge	171:3a7713b1edbc	1642	#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
AnnaBridge	171:3a7713b1edbc	1643
AnnaBridge	171:3a7713b1edbc	1644	/**
AnnaBridge	171:3a7713b1edbc	1645	* @brief Set the specified DMA Tx Desc Own bit.
AnnaBridge	171:3a7713b1edbc	1646	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1647	* @retval None
AnnaBridge	171:3a7713b1edbc	1648	*/
AnnaBridge	171:3a7713b1edbc	1649	#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_OWN)
AnnaBridge	171:3a7713b1edbc	1650
AnnaBridge	171:3a7713b1edbc	1651	/**
AnnaBridge	171:3a7713b1edbc	1652	* @brief Enables the specified DMA Tx Desc Transmit interrupt.
AnnaBridge	171:3a7713b1edbc	1653	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1654	* @retval None
AnnaBridge	171:3a7713b1edbc	1655	*/
AnnaBridge	171:3a7713b1edbc	1656	#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_IC)
AnnaBridge	171:3a7713b1edbc	1657
AnnaBridge	171:3a7713b1edbc	1658	/**
AnnaBridge	171:3a7713b1edbc	1659	* @brief Disables the specified DMA Tx Desc Transmit interrupt.
AnnaBridge	171:3a7713b1edbc	1660	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1661	* @retval None
AnnaBridge	171:3a7713b1edbc	1662	*/
AnnaBridge	171:3a7713b1edbc	1663	#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
AnnaBridge	171:3a7713b1edbc	1664
AnnaBridge	171:3a7713b1edbc	1665	/**
AnnaBridge	171:3a7713b1edbc	1666	* @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
AnnaBridge	171:3a7713b1edbc	1667	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1668	* @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
AnnaBridge	171:3a7713b1edbc	1669	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1670	* @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
AnnaBridge	171:3a7713b1edbc	1671	* @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
AnnaBridge	171:3a7713b1edbc	1672	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
AnnaBridge	171:3a7713b1edbc	1673	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
AnnaBridge	171:3a7713b1edbc	1674	* @retval None
AnnaBridge	171:3a7713b1edbc	1675	*/
AnnaBridge	171:3a7713b1edbc	1676	#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status \|= (__CHECKSUM__))
AnnaBridge	171:3a7713b1edbc	1677
AnnaBridge	171:3a7713b1edbc	1678	/**
AnnaBridge	171:3a7713b1edbc	1679	* @brief Enables the DMA Tx Desc CRC.
AnnaBridge	171:3a7713b1edbc	1680	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1681	* @retval None
AnnaBridge	171:3a7713b1edbc	1682	*/
AnnaBridge	171:3a7713b1edbc	1683	#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
AnnaBridge	171:3a7713b1edbc	1684
AnnaBridge	171:3a7713b1edbc	1685	/**
AnnaBridge	171:3a7713b1edbc	1686	* @brief Disables the DMA Tx Desc CRC.
AnnaBridge	171:3a7713b1edbc	1687	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1688	* @retval None
AnnaBridge	171:3a7713b1edbc	1689	*/
AnnaBridge	171:3a7713b1edbc	1690	#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DC)
AnnaBridge	171:3a7713b1edbc	1691
AnnaBridge	171:3a7713b1edbc	1692	/**
AnnaBridge	171:3a7713b1edbc	1693	* @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
AnnaBridge	171:3a7713b1edbc	1694	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1695	* @retval None
AnnaBridge	171:3a7713b1edbc	1696	*/
AnnaBridge	171:3a7713b1edbc	1697	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
AnnaBridge	171:3a7713b1edbc	1698
AnnaBridge	171:3a7713b1edbc	1699	/**
AnnaBridge	171:3a7713b1edbc	1700	* @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
AnnaBridge	171:3a7713b1edbc	1701	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1702	* @retval None
AnnaBridge	171:3a7713b1edbc	1703	*/
AnnaBridge	171:3a7713b1edbc	1704	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DP)
AnnaBridge	171:3a7713b1edbc	1705
AnnaBridge	171:3a7713b1edbc	1706	/**
AnnaBridge	171:3a7713b1edbc	1707	* @brief Enables the specified ETHERNET MAC interrupts.
AnnaBridge	171:3a7713b1edbc	1708	* @param __HANDLE__ : ETH Handle
AnnaBridge	171:3a7713b1edbc	1709	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
AnnaBridge	171:3a7713b1edbc	1710	* enabled or disabled.
AnnaBridge	171:3a7713b1edbc	1711	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	1712	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
AnnaBridge	171:3a7713b1edbc	1713	* @arg ETH_MAC_IT_PMT : PMT interrupt
AnnaBridge	171:3a7713b1edbc	1714	* @retval None
AnnaBridge	171:3a7713b1edbc	1715	*/
AnnaBridge	171:3a7713b1edbc	1716	#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR \|= (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1717
AnnaBridge	171:3a7713b1edbc	1718	/**
AnnaBridge	171:3a7713b1edbc	1719	* @brief Disables the specified ETHERNET MAC interrupts.
AnnaBridge	171:3a7713b1edbc	1720	* @param __HANDLE__ : ETH Handle
AnnaBridge	171:3a7713b1edbc	1721	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
AnnaBridge	171:3a7713b1edbc	1722	* enabled or disabled.
AnnaBridge	171:3a7713b1edbc	1723	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	1724	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
AnnaBridge	171:3a7713b1edbc	1725	* @arg ETH_MAC_IT_PMT : PMT interrupt
AnnaBridge	171:3a7713b1edbc	1726	* @retval None
AnnaBridge	171:3a7713b1edbc	1727	*/
AnnaBridge	171:3a7713b1edbc	1728	#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1729
AnnaBridge	171:3a7713b1edbc	1730	/**
AnnaBridge	171:3a7713b1edbc	1731	* @brief Initiate a Pause Control Frame (Full-duplex only).
AnnaBridge	171:3a7713b1edbc	1732	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1733	* @retval None
AnnaBridge	171:3a7713b1edbc	1734	*/
AnnaBridge	171:3a7713b1edbc	1735	#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
AnnaBridge	171:3a7713b1edbc	1736
AnnaBridge	171:3a7713b1edbc	1737	/**
AnnaBridge	171:3a7713b1edbc	1738	* @brief Checks whether the ETHERNET flow control busy bit is set or not.
AnnaBridge	171:3a7713b1edbc	1739	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1740	* @retval The new state of flow control busy status bit (SET or RESET).
AnnaBridge	171:3a7713b1edbc	1741	*/
AnnaBridge	171:3a7713b1edbc	1742	#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
AnnaBridge	171:3a7713b1edbc	1743
AnnaBridge	171:3a7713b1edbc	1744	/**
AnnaBridge	171:3a7713b1edbc	1745	* @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
AnnaBridge	171:3a7713b1edbc	1746	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1747	* @retval None
AnnaBridge	171:3a7713b1edbc	1748	*/
AnnaBridge	171:3a7713b1edbc	1749	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
AnnaBridge	171:3a7713b1edbc	1750
AnnaBridge	171:3a7713b1edbc	1751	/**
AnnaBridge	171:3a7713b1edbc	1752	* @brief Disables the MAC BackPressure operation activation (Half-duplex only).
AnnaBridge	171:3a7713b1edbc	1753	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1754	* @retval None
AnnaBridge	171:3a7713b1edbc	1755	*/
AnnaBridge	171:3a7713b1edbc	1756	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
AnnaBridge	171:3a7713b1edbc	1757
AnnaBridge	171:3a7713b1edbc	1758	/**
AnnaBridge	171:3a7713b1edbc	1759	* @brief Checks whether the specified ETHERNET MAC flag is set or not.
AnnaBridge	171:3a7713b1edbc	1760	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1761	* @param __FLAG__: specifies the flag to check.
AnnaBridge	171:3a7713b1edbc	1762	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1763	* @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
AnnaBridge	171:3a7713b1edbc	1764	* @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
AnnaBridge	171:3a7713b1edbc	1765	* @arg ETH_MAC_FLAG_MMCR : MMC receive flag
AnnaBridge	171:3a7713b1edbc	1766	* @arg ETH_MAC_FLAG_MMC : MMC flag
AnnaBridge	171:3a7713b1edbc	1767	* @arg ETH_MAC_FLAG_PMT : PMT flag
AnnaBridge	171:3a7713b1edbc	1768	* @retval The state of ETHERNET MAC flag.
AnnaBridge	171:3a7713b1edbc	1769	*/
AnnaBridge	171:3a7713b1edbc	1770	#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
AnnaBridge	171:3a7713b1edbc	1771
AnnaBridge	171:3a7713b1edbc	1772	/**
AnnaBridge	171:3a7713b1edbc	1773	* @brief Enables the specified ETHERNET DMA interrupts.
AnnaBridge	171:3a7713b1edbc	1774	* @param __HANDLE__ : ETH Handle
AnnaBridge	171:3a7713b1edbc	1775	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
AnnaBridge	171:3a7713b1edbc	1776	* enabled @ref ETH_DMA_Interrupts
AnnaBridge	171:3a7713b1edbc	1777	* @retval None
AnnaBridge	171:3a7713b1edbc	1778	*/
AnnaBridge	171:3a7713b1edbc	1779	#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \|= (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1780
AnnaBridge	171:3a7713b1edbc	1781	/**
AnnaBridge	171:3a7713b1edbc	1782	* @brief Disables the specified ETHERNET DMA interrupts.
AnnaBridge	171:3a7713b1edbc	1783	* @param __HANDLE__ : ETH Handle
AnnaBridge	171:3a7713b1edbc	1784	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
AnnaBridge	171:3a7713b1edbc	1785	* disabled. @ref ETH_DMA_Interrupts
AnnaBridge	171:3a7713b1edbc	1786	* @retval None
AnnaBridge	171:3a7713b1edbc	1787	*/
AnnaBridge	171:3a7713b1edbc	1788	#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1789
AnnaBridge	171:3a7713b1edbc	1790	/**
AnnaBridge	171:3a7713b1edbc	1791	* @brief Clears the ETHERNET DMA IT pending bit.
AnnaBridge	171:3a7713b1edbc	1792	* @param __HANDLE__ : ETH Handle
AnnaBridge	171:3a7713b1edbc	1793	* @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
AnnaBridge	171:3a7713b1edbc	1794	* @retval None
AnnaBridge	171:3a7713b1edbc	1795	*/
AnnaBridge	171:3a7713b1edbc	1796	#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1797
AnnaBridge	171:3a7713b1edbc	1798	/**
AnnaBridge	171:3a7713b1edbc	1799	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
AnnaBridge	171:3a7713b1edbc	1800	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1801	* @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
AnnaBridge	171:3a7713b1edbc	1802	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
AnnaBridge	171:3a7713b1edbc	1803	*/
AnnaBridge	171:3a7713b1edbc	1804	#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
AnnaBridge	171:3a7713b1edbc	1805
AnnaBridge	171:3a7713b1edbc	1806	/**
AnnaBridge	171:3a7713b1edbc	1807	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
AnnaBridge	171:3a7713b1edbc	1808	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1809	* @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
AnnaBridge	171:3a7713b1edbc	1810	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
AnnaBridge	171:3a7713b1edbc	1811	*/
AnnaBridge	171:3a7713b1edbc	1812	#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
AnnaBridge	171:3a7713b1edbc	1813
AnnaBridge	171:3a7713b1edbc	1814	/**
AnnaBridge	171:3a7713b1edbc	1815	* @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
AnnaBridge	171:3a7713b1edbc	1816	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1817	* @param __OVERFLOW__: specifies the DMA overflow flag to check.
AnnaBridge	171:3a7713b1edbc	1818	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1819	* @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
AnnaBridge	171:3a7713b1edbc	1820	* @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
AnnaBridge	171:3a7713b1edbc	1821	* @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
AnnaBridge	171:3a7713b1edbc	1822	*/
AnnaBridge	171:3a7713b1edbc	1823	#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
AnnaBridge	171:3a7713b1edbc	1824
AnnaBridge	171:3a7713b1edbc	1825	/**
AnnaBridge	171:3a7713b1edbc	1826	* @brief Set the DMA Receive status watchdog timer register value
AnnaBridge	171:3a7713b1edbc	1827	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1828	* @param __VALUE__: DMA Receive status watchdog timer register value
AnnaBridge	171:3a7713b1edbc	1829	* @retval None
AnnaBridge	171:3a7713b1edbc	1830	*/
AnnaBridge	171:3a7713b1edbc	1831	#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
AnnaBridge	171:3a7713b1edbc	1832
AnnaBridge	171:3a7713b1edbc	1833	/**
AnnaBridge	171:3a7713b1edbc	1834	* @brief Enables any unicast packet filtered by the MAC address
AnnaBridge	171:3a7713b1edbc	1835	* recognition to be a wake-up frame.
AnnaBridge	171:3a7713b1edbc	1836	* @param __HANDLE__: ETH Handle.
AnnaBridge	171:3a7713b1edbc	1837	* @retval None
AnnaBridge	171:3a7713b1edbc	1838	*/
AnnaBridge	171:3a7713b1edbc	1839	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_GU)
AnnaBridge	171:3a7713b1edbc	1840
AnnaBridge	171:3a7713b1edbc	1841	/**
AnnaBridge	171:3a7713b1edbc	1842	* @brief Disables any unicast packet filtered by the MAC address
AnnaBridge	171:3a7713b1edbc	1843	* recognition to be a wake-up frame.
AnnaBridge	171:3a7713b1edbc	1844	* @param __HANDLE__: ETH Handle.
AnnaBridge	171:3a7713b1edbc	1845	* @retval None
AnnaBridge	171:3a7713b1edbc	1846	*/
AnnaBridge	171:3a7713b1edbc	1847	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
AnnaBridge	171:3a7713b1edbc	1848
AnnaBridge	171:3a7713b1edbc	1849	/**
AnnaBridge	171:3a7713b1edbc	1850	* @brief Enables the MAC Wake-Up Frame Detection.
AnnaBridge	171:3a7713b1edbc	1851	* @param __HANDLE__: ETH Handle.
AnnaBridge	171:3a7713b1edbc	1852	* @retval None
AnnaBridge	171:3a7713b1edbc	1853	*/
AnnaBridge	171:3a7713b1edbc	1854	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_WFE)
AnnaBridge	171:3a7713b1edbc	1855
AnnaBridge	171:3a7713b1edbc	1856	/**
AnnaBridge	171:3a7713b1edbc	1857	* @brief Disables the MAC Wake-Up Frame Detection.
AnnaBridge	171:3a7713b1edbc	1858	* @param __HANDLE__: ETH Handle.
AnnaBridge	171:3a7713b1edbc	1859	* @retval None
AnnaBridge	171:3a7713b1edbc	1860	*/
AnnaBridge	171:3a7713b1edbc	1861	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
AnnaBridge	171:3a7713b1edbc	1862
AnnaBridge	171:3a7713b1edbc	1863	/**
AnnaBridge	171:3a7713b1edbc	1864	* @brief Enables the MAC Magic Packet Detection.
AnnaBridge	171:3a7713b1edbc	1865	* @param __HANDLE__: ETH Handle.
AnnaBridge	171:3a7713b1edbc	1866	* @retval None
AnnaBridge	171:3a7713b1edbc	1867	*/
AnnaBridge	171:3a7713b1edbc	1868	#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_MPE)
AnnaBridge	171:3a7713b1edbc	1869
AnnaBridge	171:3a7713b1edbc	1870	/**
AnnaBridge	171:3a7713b1edbc	1871	* @brief Disables the MAC Magic Packet Detection.
AnnaBridge	171:3a7713b1edbc	1872	* @param __HANDLE__: ETH Handle.
AnnaBridge	171:3a7713b1edbc	1873	* @retval None
AnnaBridge	171:3a7713b1edbc	1874	*/
AnnaBridge	171:3a7713b1edbc	1875	#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
AnnaBridge	171:3a7713b1edbc	1876
AnnaBridge	171:3a7713b1edbc	1877	/**
AnnaBridge	171:3a7713b1edbc	1878	* @brief Enables the MAC Power Down.
AnnaBridge	171:3a7713b1edbc	1879	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1880	* @retval None
AnnaBridge	171:3a7713b1edbc	1881	*/
AnnaBridge	171:3a7713b1edbc	1882	#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_PD)
AnnaBridge	171:3a7713b1edbc	1883
AnnaBridge	171:3a7713b1edbc	1884	/**
AnnaBridge	171:3a7713b1edbc	1885	* @brief Disables the MAC Power Down.
AnnaBridge	171:3a7713b1edbc	1886	* @param __HANDLE__: ETH Handle
AnnaBridge	171:3a7713b1edbc	1887	* @retval None
AnnaBridge	171:3a7713b1edbc	1888	*/
AnnaBridge	171:3a7713b1edbc	1889	#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
AnnaBridge	171:3a7713b1edbc	1890
AnnaBridge	171:3a7713b1edbc	1891	/**
AnnaBridge	171:3a7713b1edbc	1892	* @brief Checks whether the specified ETHERNET PMT flag is set or not.
AnnaBridge	171:3a7713b1edbc	1893	* @param __HANDLE__: ETH Handle.
AnnaBridge	171:3a7713b1edbc	1894	* @param __FLAG__: specifies the flag to check.
AnnaBridge	171:3a7713b1edbc	1895	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1896	* @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
AnnaBridge	171:3a7713b1edbc	1897	* @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
AnnaBridge	171:3a7713b1edbc	1898	* @arg ETH_PMT_FLAG_MPR : Magic Packet Received
AnnaBridge	171:3a7713b1edbc	1899	* @retval The new state of ETHERNET PMT Flag (SET or RESET).
AnnaBridge	171:3a7713b1edbc	1900	*/
AnnaBridge	171:3a7713b1edbc	1901	#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
AnnaBridge	171:3a7713b1edbc	1902
AnnaBridge	171:3a7713b1edbc	1903	/**
AnnaBridge	171:3a7713b1edbc	1904	* @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
AnnaBridge	171:3a7713b1edbc	1905	* @param __HANDLE__: ETH Handle.
AnnaBridge	171:3a7713b1edbc	1906	* @retval None
AnnaBridge	171:3a7713b1edbc	1907	*/
AnnaBridge	171:3a7713b1edbc	1908	#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= (ETH_MMCCR_MCFHP \| ETH_MMCCR_MCP))
AnnaBridge	171:3a7713b1edbc	1909
AnnaBridge	171:3a7713b1edbc	1910	/**
AnnaBridge	171:3a7713b1edbc	1911	* @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
AnnaBridge	171:3a7713b1edbc	1912	* @param __HANDLE__: ETH Handle.
AnnaBridge	171:3a7713b1edbc	1913	* @retval None
AnnaBridge	171:3a7713b1edbc	1914	*/
AnnaBridge	171:3a7713b1edbc	1915	#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
AnnaBridge	171:3a7713b1edbc	1916	(__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCP;} while (0)
AnnaBridge	171:3a7713b1edbc	1917
AnnaBridge	171:3a7713b1edbc	1918	/**
AnnaBridge	171:3a7713b1edbc	1919	* @brief Enables the MMC Counter Freeze.
AnnaBridge	171:3a7713b1edbc	1920	* @param __HANDLE__: ETH Handle.
AnnaBridge	171:3a7713b1edbc	1921	* @retval None
AnnaBridge	171:3a7713b1edbc	1922	*/
AnnaBridge	171:3a7713b1edbc	1923	#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCF)
AnnaBridge	171:3a7713b1edbc	1924
AnnaBridge	171:3a7713b1edbc	1925	/**
AnnaBridge	171:3a7713b1edbc	1926	* @brief Disables the MMC Counter Freeze.
AnnaBridge	171:3a7713b1edbc	1927	* @param __HANDLE__: ETH Handle.
AnnaBridge	171:3a7713b1edbc	1928	* @retval None
AnnaBridge	171:3a7713b1edbc	1929	*/
AnnaBridge	171:3a7713b1edbc	1930	#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
AnnaBridge	171:3a7713b1edbc	1931
AnnaBridge	171:3a7713b1edbc	1932	/**
AnnaBridge	171:3a7713b1edbc	1933	* @brief Enables the MMC Reset On Read.
AnnaBridge	171:3a7713b1edbc	1934	* @param __HANDLE__: ETH Handle.
AnnaBridge	171:3a7713b1edbc	1935	* @retval None
AnnaBridge	171:3a7713b1edbc	1936	*/
AnnaBridge	171:3a7713b1edbc	1937	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_ROR)
AnnaBridge	171:3a7713b1edbc	1938
AnnaBridge	171:3a7713b1edbc	1939	/**
AnnaBridge	171:3a7713b1edbc	1940	* @brief Disables the MMC Reset On Read.
AnnaBridge	171:3a7713b1edbc	1941	* @param __HANDLE__: ETH Handle.
AnnaBridge	171:3a7713b1edbc	1942	* @retval None
AnnaBridge	171:3a7713b1edbc	1943	*/
AnnaBridge	171:3a7713b1edbc	1944	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
AnnaBridge	171:3a7713b1edbc	1945
AnnaBridge	171:3a7713b1edbc	1946	/**
AnnaBridge	171:3a7713b1edbc	1947	* @brief Enables the MMC Counter Stop Rollover.
AnnaBridge	171:3a7713b1edbc	1948	* @param __HANDLE__: ETH Handle.
AnnaBridge	171:3a7713b1edbc	1949	* @retval None
AnnaBridge	171:3a7713b1edbc	1950	*/
AnnaBridge	171:3a7713b1edbc	1951	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
AnnaBridge	171:3a7713b1edbc	1952
AnnaBridge	171:3a7713b1edbc	1953	/**
AnnaBridge	171:3a7713b1edbc	1954	* @brief Disables the MMC Counter Stop Rollover.
AnnaBridge	171:3a7713b1edbc	1955	* @param __HANDLE__: ETH Handle.
AnnaBridge	171:3a7713b1edbc	1956	* @retval None
AnnaBridge	171:3a7713b1edbc	1957	*/
AnnaBridge	171:3a7713b1edbc	1958	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CSR)
AnnaBridge	171:3a7713b1edbc	1959
AnnaBridge	171:3a7713b1edbc	1960	/**
AnnaBridge	171:3a7713b1edbc	1961	* @brief Resets the MMC Counters.
AnnaBridge	171:3a7713b1edbc	1962	* @param __HANDLE__: ETH Handle.
AnnaBridge	171:3a7713b1edbc	1963	* @retval None
AnnaBridge	171:3a7713b1edbc	1964	*/
AnnaBridge	171:3a7713b1edbc	1965	#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CR)
AnnaBridge	171:3a7713b1edbc	1966
AnnaBridge	171:3a7713b1edbc	1967	/**
AnnaBridge	171:3a7713b1edbc	1968	* @brief Enables the specified ETHERNET MMC Rx interrupts.
AnnaBridge	171:3a7713b1edbc	1969	* @param __HANDLE__: ETH Handle.
AnnaBridge	171:3a7713b1edbc	1970	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
AnnaBridge	171:3a7713b1edbc	1971	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1972	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
AnnaBridge	171:3a7713b1edbc	1973	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
AnnaBridge	171:3a7713b1edbc	1974	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
AnnaBridge	171:3a7713b1edbc	1975	* @retval None
AnnaBridge	171:3a7713b1edbc	1976	*/
AnnaBridge	171:3a7713b1edbc	1977	#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
AnnaBridge	171:3a7713b1edbc	1978	/**
AnnaBridge	171:3a7713b1edbc	1979	* @brief Disables the specified ETHERNET MMC Rx interrupts.
AnnaBridge	171:3a7713b1edbc	1980	* @param __HANDLE__: ETH Handle.
AnnaBridge	171:3a7713b1edbc	1981	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
AnnaBridge	171:3a7713b1edbc	1982	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1983	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
AnnaBridge	171:3a7713b1edbc	1984	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
AnnaBridge	171:3a7713b1edbc	1985	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
AnnaBridge	171:3a7713b1edbc	1986	* @retval None
AnnaBridge	171:3a7713b1edbc	1987	*/
AnnaBridge	171:3a7713b1edbc	1988	#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR \|= ((__INTERRUPT__) & 0xEFFFFFFF)
AnnaBridge	171:3a7713b1edbc	1989	/**
AnnaBridge	171:3a7713b1edbc	1990	* @brief Enables the specified ETHERNET MMC Tx interrupts.
AnnaBridge	171:3a7713b1edbc	1991	* @param __HANDLE__: ETH Handle.
AnnaBridge	171:3a7713b1edbc	1992	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
AnnaBridge	171:3a7713b1edbc	1993	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1994	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
AnnaBridge	171:3a7713b1edbc	1995	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
AnnaBridge	171:3a7713b1edbc	1996	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
AnnaBridge	171:3a7713b1edbc	1997	* @retval None
AnnaBridge	171:3a7713b1edbc	1998	*/
AnnaBridge	171:3a7713b1edbc	1999	#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	2000
AnnaBridge	171:3a7713b1edbc	2001	/**
AnnaBridge	171:3a7713b1edbc	2002	* @brief Disables the specified ETHERNET MMC Tx interrupts.
AnnaBridge	171:3a7713b1edbc	2003	* @param __HANDLE__: ETH Handle.
AnnaBridge	171:3a7713b1edbc	2004	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
AnnaBridge	171:3a7713b1edbc	2005	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2006	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
AnnaBridge	171:3a7713b1edbc	2007	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
AnnaBridge	171:3a7713b1edbc	2008	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
AnnaBridge	171:3a7713b1edbc	2009	* @retval None
AnnaBridge	171:3a7713b1edbc	2010	*/
AnnaBridge	171:3a7713b1edbc	2011	#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR \|= (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	2012
AnnaBridge	171:3a7713b1edbc	2013	/**
AnnaBridge	171:3a7713b1edbc	2014	* @brief Enables the ETH External interrupt line.
AnnaBridge	171:3a7713b1edbc	2015	* @retval None
AnnaBridge	171:3a7713b1edbc	2016	*/
AnnaBridge	171:3a7713b1edbc	2017	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR \|= (ETH_EXTI_LINE_WAKEUP)
AnnaBridge	171:3a7713b1edbc	2018
AnnaBridge	171:3a7713b1edbc	2019	/**
AnnaBridge	171:3a7713b1edbc	2020	* @brief Disables the ETH External interrupt line.
AnnaBridge	171:3a7713b1edbc	2021	* @retval None
AnnaBridge	171:3a7713b1edbc	2022	*/
AnnaBridge	171:3a7713b1edbc	2023	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
AnnaBridge	171:3a7713b1edbc	2024
AnnaBridge	171:3a7713b1edbc	2025	/**
AnnaBridge	171:3a7713b1edbc	2026	* @brief Enable event on ETH External event line.
AnnaBridge	171:3a7713b1edbc	2027	* @retval None.
AnnaBridge	171:3a7713b1edbc	2028	*/
AnnaBridge	171:3a7713b1edbc	2029	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR \|= (ETH_EXTI_LINE_WAKEUP)
AnnaBridge	171:3a7713b1edbc	2030
AnnaBridge	171:3a7713b1edbc	2031	/**
AnnaBridge	171:3a7713b1edbc	2032	* @brief Disable event on ETH External event line
AnnaBridge	171:3a7713b1edbc	2033	* @retval None.
AnnaBridge	171:3a7713b1edbc	2034	*/
AnnaBridge	171:3a7713b1edbc	2035	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
AnnaBridge	171:3a7713b1edbc	2036
AnnaBridge	171:3a7713b1edbc	2037	/**
AnnaBridge	171:3a7713b1edbc	2038	* @brief Get flag of the ETH External interrupt line.
AnnaBridge	171:3a7713b1edbc	2039	* @retval None
AnnaBridge	171:3a7713b1edbc	2040	*/
AnnaBridge	171:3a7713b1edbc	2041	#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
AnnaBridge	171:3a7713b1edbc	2042
AnnaBridge	171:3a7713b1edbc	2043	/**
AnnaBridge	171:3a7713b1edbc	2044	* @brief Clear flag of the ETH External interrupt line.
AnnaBridge	171:3a7713b1edbc	2045	* @retval None
AnnaBridge	171:3a7713b1edbc	2046	*/
AnnaBridge	171:3a7713b1edbc	2047	#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
AnnaBridge	171:3a7713b1edbc	2048
AnnaBridge	171:3a7713b1edbc	2049	/**
AnnaBridge	171:3a7713b1edbc	2050	* @brief Enables rising edge trigger to the ETH External interrupt line.
AnnaBridge	171:3a7713b1edbc	2051	* @retval None
AnnaBridge	171:3a7713b1edbc	2052	*/
AnnaBridge	171:3a7713b1edbc	2053	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP
AnnaBridge	171:3a7713b1edbc	2054
AnnaBridge	171:3a7713b1edbc	2055	/**
AnnaBridge	171:3a7713b1edbc	2056	* @brief Disables the rising edge trigger to the ETH External interrupt line.
AnnaBridge	171:3a7713b1edbc	2057	* @retval None
AnnaBridge	171:3a7713b1edbc	2058	*/
AnnaBridge	171:3a7713b1edbc	2059	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
AnnaBridge	171:3a7713b1edbc	2060
AnnaBridge	171:3a7713b1edbc	2061	/**
AnnaBridge	171:3a7713b1edbc	2062	* @brief Enables falling edge trigger to the ETH External interrupt line.
AnnaBridge	171:3a7713b1edbc	2063	* @retval None
AnnaBridge	171:3a7713b1edbc	2064	*/
AnnaBridge	171:3a7713b1edbc	2065	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR \|= (ETH_EXTI_LINE_WAKEUP)
AnnaBridge	171:3a7713b1edbc	2066
AnnaBridge	171:3a7713b1edbc	2067	/**
AnnaBridge	171:3a7713b1edbc	2068	* @brief Disables falling edge trigger to the ETH External interrupt line.
AnnaBridge	171:3a7713b1edbc	2069	* @retval None
AnnaBridge	171:3a7713b1edbc	2070	*/
AnnaBridge	171:3a7713b1edbc	2071	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
AnnaBridge	171:3a7713b1edbc	2072
AnnaBridge	171:3a7713b1edbc	2073	/**
AnnaBridge	171:3a7713b1edbc	2074	* @brief Enables rising/falling edge trigger to the ETH External interrupt line.
AnnaBridge	171:3a7713b1edbc	2075	* @retval None
AnnaBridge	171:3a7713b1edbc	2076	*/
AnnaBridge	171:3a7713b1edbc	2077	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP;\
AnnaBridge	171:3a7713b1edbc	2078	EXTI->FTSR \|= ETH_EXTI_LINE_WAKEUP;\
AnnaBridge	171:3a7713b1edbc	2079	}while(0)
AnnaBridge	171:3a7713b1edbc	2080
AnnaBridge	171:3a7713b1edbc	2081	/**
AnnaBridge	171:3a7713b1edbc	2082	* @brief Disables rising/falling edge trigger to the ETH External interrupt line.
AnnaBridge	171:3a7713b1edbc	2083	* @retval None
AnnaBridge	171:3a7713b1edbc	2084	*/
AnnaBridge	171:3a7713b1edbc	2085	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
AnnaBridge	171:3a7713b1edbc	2086	EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
AnnaBridge	171:3a7713b1edbc	2087	}while(0)
AnnaBridge	171:3a7713b1edbc	2088
AnnaBridge	171:3a7713b1edbc	2089	/**
AnnaBridge	171:3a7713b1edbc	2090	* @brief Generate a Software interrupt on selected EXTI line.
AnnaBridge	171:3a7713b1edbc	2091	* @retval None.
AnnaBridge	171:3a7713b1edbc	2092	*/
AnnaBridge	171:3a7713b1edbc	2093	#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER\|= ETH_EXTI_LINE_WAKEUP
AnnaBridge	171:3a7713b1edbc	2094
AnnaBridge	171:3a7713b1edbc	2095	/**
AnnaBridge	171:3a7713b1edbc	2096	* @}
AnnaBridge	171:3a7713b1edbc	2097	*/
AnnaBridge	171:3a7713b1edbc	2098	/* Exported functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	2099
AnnaBridge	171:3a7713b1edbc	2100	/** @addtogroup ETH_Exported_Functions
AnnaBridge	171:3a7713b1edbc	2101	* @{
AnnaBridge	171:3a7713b1edbc	2102	*/
AnnaBridge	171:3a7713b1edbc	2103
AnnaBridge	171:3a7713b1edbc	2104	/* Initialization and de-initialization functions ****************************/
AnnaBridge	171:3a7713b1edbc	2105
AnnaBridge	171:3a7713b1edbc	2106	/** @addtogroup ETH_Exported_Functions_Group1
AnnaBridge	171:3a7713b1edbc	2107	* @{
AnnaBridge	171:3a7713b1edbc	2108	*/
AnnaBridge	171:3a7713b1edbc	2109	HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
AnnaBridge	171:3a7713b1edbc	2110	HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
AnnaBridge	171:3a7713b1edbc	2111	void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
AnnaBridge	171:3a7713b1edbc	2112	void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
AnnaBridge	171:3a7713b1edbc	2113	HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
AnnaBridge	171:3a7713b1edbc	2114	HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
AnnaBridge	171:3a7713b1edbc	2115
AnnaBridge	171:3a7713b1edbc	2116	/**
AnnaBridge	171:3a7713b1edbc	2117	* @}
AnnaBridge	171:3a7713b1edbc	2118	*/
AnnaBridge	171:3a7713b1edbc	2119	/* IO operation functions ****************************************************/
AnnaBridge	171:3a7713b1edbc	2120
AnnaBridge	171:3a7713b1edbc	2121	/** @addtogroup ETH_Exported_Functions_Group2
AnnaBridge	171:3a7713b1edbc	2122	* @{
AnnaBridge	171:3a7713b1edbc	2123	*/
AnnaBridge	171:3a7713b1edbc	2124	HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
AnnaBridge	171:3a7713b1edbc	2125	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
AnnaBridge	171:3a7713b1edbc	2126	/* Communication with PHY functions*/
AnnaBridge	171:3a7713b1edbc	2127	HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef heth, uint16_t PHYReg, uint32_t RegValue);
AnnaBridge	171:3a7713b1edbc	2128	HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
AnnaBridge	171:3a7713b1edbc	2129	/* Non-Blocking mode: Interrupt */
AnnaBridge	171:3a7713b1edbc	2130	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
AnnaBridge	171:3a7713b1edbc	2131	void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
AnnaBridge	171:3a7713b1edbc	2132	/* Callback in non blocking modes (Interrupt) */
AnnaBridge	171:3a7713b1edbc	2133	void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
AnnaBridge	171:3a7713b1edbc	2134	void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
AnnaBridge	171:3a7713b1edbc	2135	void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
AnnaBridge	171:3a7713b1edbc	2136	/**
AnnaBridge	171:3a7713b1edbc	2137	* @}
AnnaBridge	171:3a7713b1edbc	2138	*/
AnnaBridge	171:3a7713b1edbc	2139
AnnaBridge	171:3a7713b1edbc	2140	/* Peripheral Control functions **********************************************/
AnnaBridge	171:3a7713b1edbc	2141
AnnaBridge	171:3a7713b1edbc	2142	/** @addtogroup ETH_Exported_Functions_Group3
AnnaBridge	171:3a7713b1edbc	2143	* @{
AnnaBridge	171:3a7713b1edbc	2144	*/
AnnaBridge	171:3a7713b1edbc	2145
AnnaBridge	171:3a7713b1edbc	2146	HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
AnnaBridge	171:3a7713b1edbc	2147	HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
AnnaBridge	171:3a7713b1edbc	2148	HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef heth, ETH_MACInitTypeDef macconf);
AnnaBridge	171:3a7713b1edbc	2149	HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef heth, ETH_DMAInitTypeDef dmaconf);
AnnaBridge	171:3a7713b1edbc	2150	/**
AnnaBridge	171:3a7713b1edbc	2151	* @}
AnnaBridge	171:3a7713b1edbc	2152	*/
AnnaBridge	171:3a7713b1edbc	2153
AnnaBridge	171:3a7713b1edbc	2154	/* Peripheral State functions ************************************************/
AnnaBridge	171:3a7713b1edbc	2155
AnnaBridge	171:3a7713b1edbc	2156	/** @addtogroup ETH_Exported_Functions_Group4
AnnaBridge	171:3a7713b1edbc	2157	* @{
AnnaBridge	171:3a7713b1edbc	2158	*/
AnnaBridge	171:3a7713b1edbc	2159	HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
AnnaBridge	171:3a7713b1edbc	2160	/**
AnnaBridge	171:3a7713b1edbc	2161	* @}
AnnaBridge	171:3a7713b1edbc	2162	*/
AnnaBridge	171:3a7713b1edbc	2163
AnnaBridge	171:3a7713b1edbc	2164	#endif /* STM32F207xx \|\| STM32F217xx */
AnnaBridge	171:3a7713b1edbc	2165	/**
AnnaBridge	171:3a7713b1edbc	2166	* @}
AnnaBridge	171:3a7713b1edbc	2167	*/
AnnaBridge	171:3a7713b1edbc	2168
AnnaBridge	171:3a7713b1edbc	2169	/**
AnnaBridge	171:3a7713b1edbc	2170	* @}
AnnaBridge	171:3a7713b1edbc	2171	*/
AnnaBridge	171:3a7713b1edbc	2172
AnnaBridge	171:3a7713b1edbc	2173	/**
AnnaBridge	171:3a7713b1edbc	2174	* @}
AnnaBridge	171:3a7713b1edbc	2175	*/
AnnaBridge	171:3a7713b1edbc	2176
AnnaBridge	171:3a7713b1edbc	2177
AnnaBridge	171:3a7713b1edbc	2178	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	2179	}
AnnaBridge	171:3a7713b1edbc	2180	#endif
AnnaBridge	171:3a7713b1edbc	2181
AnnaBridge	171:3a7713b1edbc	2182	#endif /* __STM32F2xx_HAL_ETH_H */
AnnaBridge	171:3a7713b1edbc	2183
AnnaBridge	171:3a7713b1edbc	2184
AnnaBridge	171:3a7713b1edbc	2185
AnnaBridge	171:3a7713b1edbc	2186	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/