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TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/stm32l1xx_hal_dma.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32l1xx_hal_dma.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief Header file of DMA HAL module.
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @attention
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 12 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 14 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 17 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 19 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 20 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 32 *
AnnaBridge 171:3a7713b1edbc 33 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 34 */
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 37 #ifndef __STM32L1xx_HAL_DMA_H
AnnaBridge 171:3a7713b1edbc 38 #define __STM32L1xx_HAL_DMA_H
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 41 extern "C" {
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 45 #include "stm32l1xx_hal_def.h"
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /** @addtogroup STM32L1xx_HAL_Driver
AnnaBridge 171:3a7713b1edbc 48 * @{
AnnaBridge 171:3a7713b1edbc 49 */
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 /** @addtogroup DMA
AnnaBridge 171:3a7713b1edbc 52 * @{
AnnaBridge 171:3a7713b1edbc 53 */
AnnaBridge 171:3a7713b1edbc 54
AnnaBridge 171:3a7713b1edbc 55 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 56
AnnaBridge 171:3a7713b1edbc 57 /** @defgroup DMA_Exported_Types DMA Exported Types
AnnaBridge 171:3a7713b1edbc 58 * @{
AnnaBridge 171:3a7713b1edbc 59 */
AnnaBridge 171:3a7713b1edbc 60
AnnaBridge 171:3a7713b1edbc 61 /**
AnnaBridge 171:3a7713b1edbc 62 * @brief DMA Configuration Structure definition
AnnaBridge 171:3a7713b1edbc 63 */
AnnaBridge 171:3a7713b1edbc 64 typedef struct
AnnaBridge 171:3a7713b1edbc 65 {
AnnaBridge 171:3a7713b1edbc 66 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge 171:3a7713b1edbc 67 from memory to memory or from peripheral to memory.
AnnaBridge 171:3a7713b1edbc 68 This parameter can be a value of @ref DMA_Data_transfer_direction */
AnnaBridge 171:3a7713b1edbc 69
AnnaBridge 171:3a7713b1edbc 70 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
AnnaBridge 171:3a7713b1edbc 71 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
AnnaBridge 171:3a7713b1edbc 74 This parameter can be a value of @ref DMA_Memory_incremented_mode */
AnnaBridge 171:3a7713b1edbc 75
AnnaBridge 171:3a7713b1edbc 76 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
AnnaBridge 171:3a7713b1edbc 77 This parameter can be a value of @ref DMA_Peripheral_data_size */
AnnaBridge 171:3a7713b1edbc 78
AnnaBridge 171:3a7713b1edbc 79 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
AnnaBridge 171:3a7713b1edbc 80 This parameter can be a value of @ref DMA_Memory_data_size */
AnnaBridge 171:3a7713b1edbc 81
AnnaBridge 171:3a7713b1edbc 82 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
AnnaBridge 171:3a7713b1edbc 83 This parameter can be a value of @ref DMA_mode
AnnaBridge 171:3a7713b1edbc 84 @note The circular buffer mode cannot be used if the memory-to-memory
AnnaBridge 171:3a7713b1edbc 85 data transfer is configured on the selected Channel */
AnnaBridge 171:3a7713b1edbc 86
AnnaBridge 171:3a7713b1edbc 87 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
AnnaBridge 171:3a7713b1edbc 88 This parameter can be a value of @ref DMA_Priority_level */
AnnaBridge 171:3a7713b1edbc 89 } DMA_InitTypeDef;
AnnaBridge 171:3a7713b1edbc 90
AnnaBridge 171:3a7713b1edbc 91 /**
AnnaBridge 171:3a7713b1edbc 92 * @brief HAL DMA State structures definition
AnnaBridge 171:3a7713b1edbc 93 */
AnnaBridge 171:3a7713b1edbc 94 typedef enum
AnnaBridge 171:3a7713b1edbc 95 {
AnnaBridge 171:3a7713b1edbc 96 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
AnnaBridge 171:3a7713b1edbc 97 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
AnnaBridge 171:3a7713b1edbc 98 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
AnnaBridge 171:3a7713b1edbc 99 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
AnnaBridge 171:3a7713b1edbc 100 }HAL_DMA_StateTypeDef;
AnnaBridge 171:3a7713b1edbc 101
AnnaBridge 171:3a7713b1edbc 102 /**
AnnaBridge 171:3a7713b1edbc 103 * @brief HAL DMA Error Code structure definition
AnnaBridge 171:3a7713b1edbc 104 */
AnnaBridge 171:3a7713b1edbc 105 typedef enum
AnnaBridge 171:3a7713b1edbc 106 {
AnnaBridge 171:3a7713b1edbc 107 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
AnnaBridge 171:3a7713b1edbc 108 HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */
AnnaBridge 171:3a7713b1edbc 109 }HAL_DMA_LevelCompleteTypeDef;
AnnaBridge 171:3a7713b1edbc 110
AnnaBridge 171:3a7713b1edbc 111
AnnaBridge 171:3a7713b1edbc 112 /**
AnnaBridge 171:3a7713b1edbc 113 * @brief HAL DMA Callback ID structure definition
AnnaBridge 171:3a7713b1edbc 114 */
AnnaBridge 171:3a7713b1edbc 115 typedef enum
AnnaBridge 171:3a7713b1edbc 116 {
AnnaBridge 171:3a7713b1edbc 117 HAL_DMA_XFER_CPLT_CB_ID = 0x00, /*!< Full transfer */
AnnaBridge 171:3a7713b1edbc 118 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01, /*!< Half transfer */
AnnaBridge 171:3a7713b1edbc 119 HAL_DMA_XFER_ERROR_CB_ID = 0x02, /*!< Error */
AnnaBridge 171:3a7713b1edbc 120 HAL_DMA_XFER_ABORT_CB_ID = 0x03, /*!< Abort */
AnnaBridge 171:3a7713b1edbc 121 HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */
AnnaBridge 171:3a7713b1edbc 122
AnnaBridge 171:3a7713b1edbc 123 }HAL_DMA_CallbackIDTypeDef;
AnnaBridge 171:3a7713b1edbc 124
AnnaBridge 171:3a7713b1edbc 125 /**
AnnaBridge 171:3a7713b1edbc 126 * @brief DMA handle Structure definition
AnnaBridge 171:3a7713b1edbc 127 */
AnnaBridge 171:3a7713b1edbc 128 typedef struct __DMA_HandleTypeDef
AnnaBridge 171:3a7713b1edbc 129 {
AnnaBridge 171:3a7713b1edbc 130 DMA_Channel_TypeDef *Instance; /*!< Register base address */
AnnaBridge 171:3a7713b1edbc 131
AnnaBridge 171:3a7713b1edbc 132 DMA_InitTypeDef Init; /*!< DMA communication parameters */
AnnaBridge 171:3a7713b1edbc 133
AnnaBridge 171:3a7713b1edbc 134 HAL_LockTypeDef Lock; /*!< DMA locking object */
AnnaBridge 171:3a7713b1edbc 135
AnnaBridge 171:3a7713b1edbc 136 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
AnnaBridge 171:3a7713b1edbc 137
AnnaBridge 171:3a7713b1edbc 138 void *Parent; /*!< Parent object state */
AnnaBridge 171:3a7713b1edbc 139
AnnaBridge 171:3a7713b1edbc 140 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
AnnaBridge 171:3a7713b1edbc 141
AnnaBridge 171:3a7713b1edbc 142 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
AnnaBridge 171:3a7713b1edbc 143
AnnaBridge 171:3a7713b1edbc 144 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
AnnaBridge 171:3a7713b1edbc 145
AnnaBridge 171:3a7713b1edbc 146 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
AnnaBridge 171:3a7713b1edbc 147
AnnaBridge 171:3a7713b1edbc 148 __IO uint32_t ErrorCode; /*!< DMA Error code */
AnnaBridge 171:3a7713b1edbc 149
AnnaBridge 171:3a7713b1edbc 150 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
AnnaBridge 171:3a7713b1edbc 151
AnnaBridge 171:3a7713b1edbc 152 uint32_t ChannelIndex; /*!< DMA Channel Index */
AnnaBridge 171:3a7713b1edbc 153
AnnaBridge 171:3a7713b1edbc 154 } DMA_HandleTypeDef;
AnnaBridge 171:3a7713b1edbc 155 /**
AnnaBridge 171:3a7713b1edbc 156 * @}
AnnaBridge 171:3a7713b1edbc 157 */
AnnaBridge 171:3a7713b1edbc 158
AnnaBridge 171:3a7713b1edbc 159 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 160
AnnaBridge 171:3a7713b1edbc 161 /** @defgroup DMA_Exported_Constants DMA Exported Constants
AnnaBridge 171:3a7713b1edbc 162 * @{
AnnaBridge 171:3a7713b1edbc 163 */
AnnaBridge 171:3a7713b1edbc 164
AnnaBridge 171:3a7713b1edbc 165 /** @defgroup DMA_Error_Code DMA Error Code
AnnaBridge 171:3a7713b1edbc 166 * @{
AnnaBridge 171:3a7713b1edbc 167 */
AnnaBridge 171:3a7713b1edbc 168 #define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */
AnnaBridge 171:3a7713b1edbc 169 #define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */
AnnaBridge 171:3a7713b1edbc 170 #define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoing transfer */
AnnaBridge 171:3a7713b1edbc 171 #define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
AnnaBridge 171:3a7713b1edbc 172 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */
AnnaBridge 171:3a7713b1edbc 173 /**
AnnaBridge 171:3a7713b1edbc 174 * @}
AnnaBridge 171:3a7713b1edbc 175 */
AnnaBridge 171:3a7713b1edbc 176
AnnaBridge 171:3a7713b1edbc 177 /** @defgroup DMA_request DMA request
AnnaBridge 171:3a7713b1edbc 178 * @{
AnnaBridge 171:3a7713b1edbc 179 */
AnnaBridge 171:3a7713b1edbc 180 #define DMA_REQUEST_0 (0x00000000U)
AnnaBridge 171:3a7713b1edbc 181 #define DMA_REQUEST_1 (0x00000001U)
AnnaBridge 171:3a7713b1edbc 182 #define DMA_REQUEST_2 (0x00000002U)
AnnaBridge 171:3a7713b1edbc 183 #define DMA_REQUEST_3 (0x00000003U)
AnnaBridge 171:3a7713b1edbc 184 #define DMA_REQUEST_4 (0x00000004U)
AnnaBridge 171:3a7713b1edbc 185 #define DMA_REQUEST_5 (0x00000005U)
AnnaBridge 171:3a7713b1edbc 186 #define DMA_REQUEST_6 (0x00000006U)
AnnaBridge 171:3a7713b1edbc 187 #define DMA_REQUEST_7 (0x00000007U)
AnnaBridge 171:3a7713b1edbc 188
AnnaBridge 171:3a7713b1edbc 189 /**
AnnaBridge 171:3a7713b1edbc 190 * @}
AnnaBridge 171:3a7713b1edbc 191 */
AnnaBridge 171:3a7713b1edbc 192
AnnaBridge 171:3a7713b1edbc 193 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
AnnaBridge 171:3a7713b1edbc 194 * @{
AnnaBridge 171:3a7713b1edbc 195 */
AnnaBridge 171:3a7713b1edbc 196 #define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */
AnnaBridge 171:3a7713b1edbc 197 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
AnnaBridge 171:3a7713b1edbc 198 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
AnnaBridge 171:3a7713b1edbc 199
AnnaBridge 171:3a7713b1edbc 200 /**
AnnaBridge 171:3a7713b1edbc 201 * @}
AnnaBridge 171:3a7713b1edbc 202 */
AnnaBridge 171:3a7713b1edbc 203
AnnaBridge 171:3a7713b1edbc 204 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
AnnaBridge 171:3a7713b1edbc 205 * @{
AnnaBridge 171:3a7713b1edbc 206 */
AnnaBridge 171:3a7713b1edbc 207 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
AnnaBridge 171:3a7713b1edbc 208 #define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */
AnnaBridge 171:3a7713b1edbc 209 /**
AnnaBridge 171:3a7713b1edbc 210 * @}
AnnaBridge 171:3a7713b1edbc 211 */
AnnaBridge 171:3a7713b1edbc 212
AnnaBridge 171:3a7713b1edbc 213 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
AnnaBridge 171:3a7713b1edbc 214 * @{
AnnaBridge 171:3a7713b1edbc 215 */
AnnaBridge 171:3a7713b1edbc 216 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
AnnaBridge 171:3a7713b1edbc 217 #define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */
AnnaBridge 171:3a7713b1edbc 218 /**
AnnaBridge 171:3a7713b1edbc 219 * @}
AnnaBridge 171:3a7713b1edbc 220 */
AnnaBridge 171:3a7713b1edbc 221
AnnaBridge 171:3a7713b1edbc 222 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
AnnaBridge 171:3a7713b1edbc 223 * @{
AnnaBridge 171:3a7713b1edbc 224 */
AnnaBridge 171:3a7713b1edbc 225 #define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment: Byte */
AnnaBridge 171:3a7713b1edbc 226 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
AnnaBridge 171:3a7713b1edbc 227 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */
AnnaBridge 171:3a7713b1edbc 228 /**
AnnaBridge 171:3a7713b1edbc 229 * @}
AnnaBridge 171:3a7713b1edbc 230 */
AnnaBridge 171:3a7713b1edbc 231
AnnaBridge 171:3a7713b1edbc 232 /** @defgroup DMA_Memory_data_size DMA Memory data size
AnnaBridge 171:3a7713b1edbc 233 * @{
AnnaBridge 171:3a7713b1edbc 234 */
AnnaBridge 171:3a7713b1edbc 235 #define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment: Byte */
AnnaBridge 171:3a7713b1edbc 236 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
AnnaBridge 171:3a7713b1edbc 237 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */
AnnaBridge 171:3a7713b1edbc 238 /**
AnnaBridge 171:3a7713b1edbc 239 * @}
AnnaBridge 171:3a7713b1edbc 240 */
AnnaBridge 171:3a7713b1edbc 241
AnnaBridge 171:3a7713b1edbc 242 /** @defgroup DMA_mode DMA mode
AnnaBridge 171:3a7713b1edbc 243 * @{
AnnaBridge 171:3a7713b1edbc 244 */
AnnaBridge 171:3a7713b1edbc 245 #define DMA_NORMAL (0x00000000U) /*!< Normal mode */
AnnaBridge 171:3a7713b1edbc 246 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
AnnaBridge 171:3a7713b1edbc 247 /**
AnnaBridge 171:3a7713b1edbc 248 * @}
AnnaBridge 171:3a7713b1edbc 249 */
AnnaBridge 171:3a7713b1edbc 250
AnnaBridge 171:3a7713b1edbc 251 /** @defgroup DMA_Priority_level DMA Priority level
AnnaBridge 171:3a7713b1edbc 252 * @{
AnnaBridge 171:3a7713b1edbc 253 */
AnnaBridge 171:3a7713b1edbc 254 #define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */
AnnaBridge 171:3a7713b1edbc 255 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
AnnaBridge 171:3a7713b1edbc 256 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
AnnaBridge 171:3a7713b1edbc 257 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
AnnaBridge 171:3a7713b1edbc 258 /**
AnnaBridge 171:3a7713b1edbc 259 * @}
AnnaBridge 171:3a7713b1edbc 260 */
AnnaBridge 171:3a7713b1edbc 261
AnnaBridge 171:3a7713b1edbc 262
AnnaBridge 171:3a7713b1edbc 263 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
AnnaBridge 171:3a7713b1edbc 264 * @{
AnnaBridge 171:3a7713b1edbc 265 */
AnnaBridge 171:3a7713b1edbc 266 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
AnnaBridge 171:3a7713b1edbc 267 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
AnnaBridge 171:3a7713b1edbc 268 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
AnnaBridge 171:3a7713b1edbc 269 /**
AnnaBridge 171:3a7713b1edbc 270 * @}
AnnaBridge 171:3a7713b1edbc 271 */
AnnaBridge 171:3a7713b1edbc 272
AnnaBridge 171:3a7713b1edbc 273 /** @defgroup DMA_flag_definitions DMA flag definitions
AnnaBridge 171:3a7713b1edbc 274 * @{
AnnaBridge 171:3a7713b1edbc 275 */
AnnaBridge 171:3a7713b1edbc 276 #define DMA_FLAG_GL1 (0x00000001U)
AnnaBridge 171:3a7713b1edbc 277 #define DMA_FLAG_TC1 (0x00000002U)
AnnaBridge 171:3a7713b1edbc 278 #define DMA_FLAG_HT1 (0x00000004U)
AnnaBridge 171:3a7713b1edbc 279 #define DMA_FLAG_TE1 (0x00000008U)
AnnaBridge 171:3a7713b1edbc 280 #define DMA_FLAG_GL2 (0x00000010U)
AnnaBridge 171:3a7713b1edbc 281 #define DMA_FLAG_TC2 (0x00000020U)
AnnaBridge 171:3a7713b1edbc 282 #define DMA_FLAG_HT2 (0x00000040U)
AnnaBridge 171:3a7713b1edbc 283 #define DMA_FLAG_TE2 (0x00000080U)
AnnaBridge 171:3a7713b1edbc 284 #define DMA_FLAG_GL3 (0x00000100U)
AnnaBridge 171:3a7713b1edbc 285 #define DMA_FLAG_TC3 (0x00000200U)
AnnaBridge 171:3a7713b1edbc 286 #define DMA_FLAG_HT3 (0x00000400U)
AnnaBridge 171:3a7713b1edbc 287 #define DMA_FLAG_TE3 (0x00000800U)
AnnaBridge 171:3a7713b1edbc 288 #define DMA_FLAG_GL4 (0x00001000U)
AnnaBridge 171:3a7713b1edbc 289 #define DMA_FLAG_TC4 (0x00002000U)
AnnaBridge 171:3a7713b1edbc 290 #define DMA_FLAG_HT4 (0x00004000U)
AnnaBridge 171:3a7713b1edbc 291 #define DMA_FLAG_TE4 (0x00008000U)
AnnaBridge 171:3a7713b1edbc 292 #define DMA_FLAG_GL5 (0x00010000U)
AnnaBridge 171:3a7713b1edbc 293 #define DMA_FLAG_TC5 (0x00020000U)
AnnaBridge 171:3a7713b1edbc 294 #define DMA_FLAG_HT5 (0x00040000U)
AnnaBridge 171:3a7713b1edbc 295 #define DMA_FLAG_TE5 (0x00080000U)
AnnaBridge 171:3a7713b1edbc 296 #define DMA_FLAG_GL6 (0x00100000U)
AnnaBridge 171:3a7713b1edbc 297 #define DMA_FLAG_TC6 (0x00200000U)
AnnaBridge 171:3a7713b1edbc 298 #define DMA_FLAG_HT6 (0x00400000U)
AnnaBridge 171:3a7713b1edbc 299 #define DMA_FLAG_TE6 (0x00800000U)
AnnaBridge 171:3a7713b1edbc 300 #define DMA_FLAG_GL7 (0x01000000U)
AnnaBridge 171:3a7713b1edbc 301 #define DMA_FLAG_TC7 (0x02000000U)
AnnaBridge 171:3a7713b1edbc 302 #define DMA_FLAG_HT7 (0x04000000U)
AnnaBridge 171:3a7713b1edbc 303 #define DMA_FLAG_TE7 (0x08000000U)
AnnaBridge 171:3a7713b1edbc 304 /**
AnnaBridge 171:3a7713b1edbc 305 * @}
AnnaBridge 171:3a7713b1edbc 306 */
AnnaBridge 171:3a7713b1edbc 307
AnnaBridge 171:3a7713b1edbc 308 /**
AnnaBridge 171:3a7713b1edbc 309 * @}
AnnaBridge 171:3a7713b1edbc 310 */
AnnaBridge 171:3a7713b1edbc 311
AnnaBridge 171:3a7713b1edbc 312 /* Exported macros -----------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 313 /** @defgroup DMA_Exported_Macros DMA Exported Macros
AnnaBridge 171:3a7713b1edbc 314 * @{
AnnaBridge 171:3a7713b1edbc 315 */
AnnaBridge 171:3a7713b1edbc 316
AnnaBridge 171:3a7713b1edbc 317 /** @brief Reset DMA handle state
AnnaBridge 171:3a7713b1edbc 318 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 319 * @retval None
AnnaBridge 171:3a7713b1edbc 320 */
AnnaBridge 171:3a7713b1edbc 321 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
AnnaBridge 171:3a7713b1edbc 322
AnnaBridge 171:3a7713b1edbc 323 /**
AnnaBridge 171:3a7713b1edbc 324 * @brief Enable the specified DMA Channel.
AnnaBridge 171:3a7713b1edbc 325 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 326 * @retval None
AnnaBridge 171:3a7713b1edbc 327 */
AnnaBridge 171:3a7713b1edbc 328 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
AnnaBridge 171:3a7713b1edbc 329
AnnaBridge 171:3a7713b1edbc 330 /**
AnnaBridge 171:3a7713b1edbc 331 * @brief Disable the specified DMA Channel.
AnnaBridge 171:3a7713b1edbc 332 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 333 * @retval None
AnnaBridge 171:3a7713b1edbc 334 */
AnnaBridge 171:3a7713b1edbc 335 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
AnnaBridge 171:3a7713b1edbc 336
AnnaBridge 171:3a7713b1edbc 337
AnnaBridge 171:3a7713b1edbc 338 /* Interrupt & Flag management */
AnnaBridge 171:3a7713b1edbc 339 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
AnnaBridge 171:3a7713b1edbc 340 defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
AnnaBridge 171:3a7713b1edbc 341 defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
AnnaBridge 171:3a7713b1edbc 342
AnnaBridge 171:3a7713b1edbc 343 /**
AnnaBridge 171:3a7713b1edbc 344 * @brief Return the current DMA Channel transfer complete flag.
AnnaBridge 171:3a7713b1edbc 345 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 346 * @retval The specified transfer complete flag index.
AnnaBridge 171:3a7713b1edbc 347 */
AnnaBridge 171:3a7713b1edbc 348
AnnaBridge 171:3a7713b1edbc 349 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 350 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
AnnaBridge 171:3a7713b1edbc 351 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
AnnaBridge 171:3a7713b1edbc 352 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
AnnaBridge 171:3a7713b1edbc 353 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
AnnaBridge 171:3a7713b1edbc 354 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
AnnaBridge 171:3a7713b1edbc 355 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
AnnaBridge 171:3a7713b1edbc 356 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
AnnaBridge 171:3a7713b1edbc 357 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
AnnaBridge 171:3a7713b1edbc 358 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
AnnaBridge 171:3a7713b1edbc 359 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
AnnaBridge 171:3a7713b1edbc 360 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
AnnaBridge 171:3a7713b1edbc 361 DMA_FLAG_TC7)
AnnaBridge 171:3a7713b1edbc 362
AnnaBridge 171:3a7713b1edbc 363 /**
AnnaBridge 171:3a7713b1edbc 364 * @brief Return the current DMA Channel half transfer complete flag.
AnnaBridge 171:3a7713b1edbc 365 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 366 * @retval The specified half transfer complete flag index.
AnnaBridge 171:3a7713b1edbc 367 */
AnnaBridge 171:3a7713b1edbc 368 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
AnnaBridge 171:3a7713b1edbc 369 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
AnnaBridge 171:3a7713b1edbc 370 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
AnnaBridge 171:3a7713b1edbc 371 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
AnnaBridge 171:3a7713b1edbc 372 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
AnnaBridge 171:3a7713b1edbc 373 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
AnnaBridge 171:3a7713b1edbc 374 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
AnnaBridge 171:3a7713b1edbc 375 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
AnnaBridge 171:3a7713b1edbc 376 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
AnnaBridge 171:3a7713b1edbc 377 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
AnnaBridge 171:3a7713b1edbc 378 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
AnnaBridge 171:3a7713b1edbc 379 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
AnnaBridge 171:3a7713b1edbc 380 DMA_FLAG_HT7)
AnnaBridge 171:3a7713b1edbc 381
AnnaBridge 171:3a7713b1edbc 382 /**
AnnaBridge 171:3a7713b1edbc 383 * @brief Return the current DMA Channel transfer error flag.
AnnaBridge 171:3a7713b1edbc 384 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 385 * @retval The specified transfer error flag index.
AnnaBridge 171:3a7713b1edbc 386 */
AnnaBridge 171:3a7713b1edbc 387 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
AnnaBridge 171:3a7713b1edbc 388 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
AnnaBridge 171:3a7713b1edbc 389 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
AnnaBridge 171:3a7713b1edbc 390 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
AnnaBridge 171:3a7713b1edbc 391 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
AnnaBridge 171:3a7713b1edbc 392 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
AnnaBridge 171:3a7713b1edbc 393 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
AnnaBridge 171:3a7713b1edbc 394 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
AnnaBridge 171:3a7713b1edbc 395 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
AnnaBridge 171:3a7713b1edbc 396 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
AnnaBridge 171:3a7713b1edbc 397 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
AnnaBridge 171:3a7713b1edbc 398 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
AnnaBridge 171:3a7713b1edbc 399 DMA_FLAG_TE7)
AnnaBridge 171:3a7713b1edbc 400
AnnaBridge 171:3a7713b1edbc 401 /**
AnnaBridge 171:3a7713b1edbc 402 * @brief Return the current DMA Channel Global interrupt flag.
AnnaBridge 171:3a7713b1edbc 403 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 404 * @retval The specified transfer error flag index.
AnnaBridge 171:3a7713b1edbc 405 */
AnnaBridge 171:3a7713b1edbc 406 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
AnnaBridge 171:3a7713b1edbc 407 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
AnnaBridge 171:3a7713b1edbc 408 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
AnnaBridge 171:3a7713b1edbc 409 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
AnnaBridge 171:3a7713b1edbc 410 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
AnnaBridge 171:3a7713b1edbc 411 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
AnnaBridge 171:3a7713b1edbc 412 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
AnnaBridge 171:3a7713b1edbc 413 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
AnnaBridge 171:3a7713b1edbc 414 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
AnnaBridge 171:3a7713b1edbc 415 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
AnnaBridge 171:3a7713b1edbc 416 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
AnnaBridge 171:3a7713b1edbc 417 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
AnnaBridge 171:3a7713b1edbc 418 DMA_ISR_GIF7)
AnnaBridge 171:3a7713b1edbc 419
AnnaBridge 171:3a7713b1edbc 420 /**
AnnaBridge 171:3a7713b1edbc 421 * @brief Get the DMA Channel pending flags.
AnnaBridge 171:3a7713b1edbc 422 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 423 * @param __FLAG__: Get the specified flag.
AnnaBridge 171:3a7713b1edbc 424 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 425 * @arg DMA_FLAG_TCx: Transfer complete flag
AnnaBridge 171:3a7713b1edbc 426 * @arg DMA_FLAG_HTx: Half transfer complete flag
AnnaBridge 171:3a7713b1edbc 427 * @arg DMA_FLAG_TEx: Transfer error flag
AnnaBridge 171:3a7713b1edbc 428 * @arg DMA_FLAG_GLx: Global interrupt flag
AnnaBridge 171:3a7713b1edbc 429 * Where x can be from 1 to 7 to select the DMA Channel x flag.
AnnaBridge 171:3a7713b1edbc 430 * @retval The state of FLAG (SET or RESET).
AnnaBridge 171:3a7713b1edbc 431 */
AnnaBridge 171:3a7713b1edbc 432 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
AnnaBridge 171:3a7713b1edbc 433 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
AnnaBridge 171:3a7713b1edbc 434
AnnaBridge 171:3a7713b1edbc 435 /**
AnnaBridge 171:3a7713b1edbc 436 * @brief Clear the DMA Channel pending flags.
AnnaBridge 171:3a7713b1edbc 437 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 438 * @param __FLAG__: specifies the flag to clear.
AnnaBridge 171:3a7713b1edbc 439 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 440 * @arg DMA_FLAG_TCx: Transfer complete flag
AnnaBridge 171:3a7713b1edbc 441 * @arg DMA_FLAG_HTx: Half transfer complete flag
AnnaBridge 171:3a7713b1edbc 442 * @arg DMA_FLAG_TEx: Transfer error flag
AnnaBridge 171:3a7713b1edbc 443 * @arg DMA_FLAG_GLx: Global interrupt flag
AnnaBridge 171:3a7713b1edbc 444 * Where x can be from 1 to 7 to select the DMA Channel x flag.
AnnaBridge 171:3a7713b1edbc 445 * @retval None
AnnaBridge 171:3a7713b1edbc 446 */
AnnaBridge 171:3a7713b1edbc 447 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
AnnaBridge 171:3a7713b1edbc 448 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
AnnaBridge 171:3a7713b1edbc 449
AnnaBridge 171:3a7713b1edbc 450 #else
AnnaBridge 171:3a7713b1edbc 451 /**
AnnaBridge 171:3a7713b1edbc 452 * @brief Return the current DMA Channel transfer complete flag.
AnnaBridge 171:3a7713b1edbc 453 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 454 * @retval The specified transfer complete flag index.
AnnaBridge 171:3a7713b1edbc 455 */
AnnaBridge 171:3a7713b1edbc 456
AnnaBridge 171:3a7713b1edbc 457 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 458 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
AnnaBridge 171:3a7713b1edbc 459 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
AnnaBridge 171:3a7713b1edbc 460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
AnnaBridge 171:3a7713b1edbc 461 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
AnnaBridge 171:3a7713b1edbc 462 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
AnnaBridge 171:3a7713b1edbc 463 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
AnnaBridge 171:3a7713b1edbc 464 DMA_FLAG_TC7)
AnnaBridge 171:3a7713b1edbc 465
AnnaBridge 171:3a7713b1edbc 466 /**
AnnaBridge 171:3a7713b1edbc 467 * @brief Return the current DMA Channel half transfer complete flag.
AnnaBridge 171:3a7713b1edbc 468 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 469 * @retval The specified half transfer complete flag index.
AnnaBridge 171:3a7713b1edbc 470 */
AnnaBridge 171:3a7713b1edbc 471 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
AnnaBridge 171:3a7713b1edbc 472 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
AnnaBridge 171:3a7713b1edbc 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
AnnaBridge 171:3a7713b1edbc 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
AnnaBridge 171:3a7713b1edbc 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
AnnaBridge 171:3a7713b1edbc 476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
AnnaBridge 171:3a7713b1edbc 477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
AnnaBridge 171:3a7713b1edbc 478 DMA_FLAG_HT7)
AnnaBridge 171:3a7713b1edbc 479
AnnaBridge 171:3a7713b1edbc 480 /**
AnnaBridge 171:3a7713b1edbc 481 * @brief Return the current DMA Channel transfer error flag.
AnnaBridge 171:3a7713b1edbc 482 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 483 * @retval The specified transfer error flag index.
AnnaBridge 171:3a7713b1edbc 484 */
AnnaBridge 171:3a7713b1edbc 485 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
AnnaBridge 171:3a7713b1edbc 486 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
AnnaBridge 171:3a7713b1edbc 487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
AnnaBridge 171:3a7713b1edbc 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
AnnaBridge 171:3a7713b1edbc 489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
AnnaBridge 171:3a7713b1edbc 490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
AnnaBridge 171:3a7713b1edbc 491 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
AnnaBridge 171:3a7713b1edbc 492 DMA_FLAG_TE7)
AnnaBridge 171:3a7713b1edbc 493
AnnaBridge 171:3a7713b1edbc 494 /**
AnnaBridge 171:3a7713b1edbc 495 * @brief Return the current DMA Channel Global interrupt flag.
AnnaBridge 171:3a7713b1edbc 496 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 497 * @retval The specified transfer error flag index.
AnnaBridge 171:3a7713b1edbc 498 */
AnnaBridge 171:3a7713b1edbc 499 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
AnnaBridge 171:3a7713b1edbc 500 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
AnnaBridge 171:3a7713b1edbc 501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
AnnaBridge 171:3a7713b1edbc 502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
AnnaBridge 171:3a7713b1edbc 503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
AnnaBridge 171:3a7713b1edbc 504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
AnnaBridge 171:3a7713b1edbc 505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
AnnaBridge 171:3a7713b1edbc 506 DMA_ISR_GIF7)
AnnaBridge 171:3a7713b1edbc 507
AnnaBridge 171:3a7713b1edbc 508 /**
AnnaBridge 171:3a7713b1edbc 509 * @brief Get the DMA Channel pending flags.
AnnaBridge 171:3a7713b1edbc 510 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 511 * @param __FLAG__: Get the specified flag.
AnnaBridge 171:3a7713b1edbc 512 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 513 * @arg DMA_FLAG_TCx: Transfer complete flag
AnnaBridge 171:3a7713b1edbc 514 * @arg DMA_FLAG_HTx: Half transfer complete flag
AnnaBridge 171:3a7713b1edbc 515 * @arg DMA_FLAG_TEx: Transfer error flag
AnnaBridge 171:3a7713b1edbc 516 * @arg DMA_FLAG_GLx: Global interrupt flag
AnnaBridge 171:3a7713b1edbc 517 * Where x can be from 1 to 7 to select the DMA Channel x flag.
AnnaBridge 171:3a7713b1edbc 518 * @retval The state of FLAG (SET or RESET).
AnnaBridge 171:3a7713b1edbc 519 */
AnnaBridge 171:3a7713b1edbc 520 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
AnnaBridge 171:3a7713b1edbc 521
AnnaBridge 171:3a7713b1edbc 522 /**
AnnaBridge 171:3a7713b1edbc 523 * @brief Clear the DMA Channel pending flags.
AnnaBridge 171:3a7713b1edbc 524 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 525 * @param __FLAG__: specifies the flag to clear.
AnnaBridge 171:3a7713b1edbc 526 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 527 * @arg DMA_FLAG_TCx: Transfer complete flag
AnnaBridge 171:3a7713b1edbc 528 * @arg DMA_FLAG_HTx: Half transfer complete flag
AnnaBridge 171:3a7713b1edbc 529 * @arg DMA_FLAG_TEx: Transfer error flag
AnnaBridge 171:3a7713b1edbc 530 * @arg DMA_FLAG_GLx: Global interrupt flag
AnnaBridge 171:3a7713b1edbc 531 * Where x can be from 1 to 7 to select the DMA Channel x flag.
AnnaBridge 171:3a7713b1edbc 532 * @retval None
AnnaBridge 171:3a7713b1edbc 533 */
AnnaBridge 171:3a7713b1edbc 534 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
AnnaBridge 171:3a7713b1edbc 535
AnnaBridge 171:3a7713b1edbc 536 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
AnnaBridge 171:3a7713b1edbc 537
AnnaBridge 171:3a7713b1edbc 538 /**
AnnaBridge 171:3a7713b1edbc 539 * @brief Enable the specified DMA Channel interrupts.
AnnaBridge 171:3a7713b1edbc 540 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 541 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
AnnaBridge 171:3a7713b1edbc 542 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 543 * @arg DMA_IT_TC: Transfer complete interrupt mask
AnnaBridge 171:3a7713b1edbc 544 * @arg DMA_IT_HT: Half transfer complete interrupt mask
AnnaBridge 171:3a7713b1edbc 545 * @arg DMA_IT_TE: Transfer error interrupt mask
AnnaBridge 171:3a7713b1edbc 546 * @retval None
AnnaBridge 171:3a7713b1edbc 547 */
AnnaBridge 171:3a7713b1edbc 548 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
AnnaBridge 171:3a7713b1edbc 549
AnnaBridge 171:3a7713b1edbc 550 /**
AnnaBridge 171:3a7713b1edbc 551 * @brief Disable the specified DMA Channel interrupts.
AnnaBridge 171:3a7713b1edbc 552 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 553 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
AnnaBridge 171:3a7713b1edbc 554 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 555 * @arg DMA_IT_TC: Transfer complete interrupt mask
AnnaBridge 171:3a7713b1edbc 556 * @arg DMA_IT_HT: Half transfer complete interrupt mask
AnnaBridge 171:3a7713b1edbc 557 * @arg DMA_IT_TE: Transfer error interrupt mask
AnnaBridge 171:3a7713b1edbc 558 * @retval None
AnnaBridge 171:3a7713b1edbc 559 */
AnnaBridge 171:3a7713b1edbc 560 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
AnnaBridge 171:3a7713b1edbc 561
AnnaBridge 171:3a7713b1edbc 562 /**
AnnaBridge 171:3a7713b1edbc 563 * @brief Check whether the specified DMA Channel interrupt is enabled or not.
AnnaBridge 171:3a7713b1edbc 564 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 565 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
AnnaBridge 171:3a7713b1edbc 566 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 567 * @arg DMA_IT_TC: Transfer complete interrupt mask
AnnaBridge 171:3a7713b1edbc 568 * @arg DMA_IT_HT: Half transfer complete interrupt mask
AnnaBridge 171:3a7713b1edbc 569 * @arg DMA_IT_TE: Transfer error interrupt mask
AnnaBridge 171:3a7713b1edbc 570 * @retval The state of DMA_IT (SET or RESET).
AnnaBridge 171:3a7713b1edbc 571 */
AnnaBridge 171:3a7713b1edbc 572 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
AnnaBridge 171:3a7713b1edbc 573
AnnaBridge 171:3a7713b1edbc 574 /**
AnnaBridge 171:3a7713b1edbc 575 * @brief Return the number of remaining data units in the current DMA Channel transfer.
AnnaBridge 171:3a7713b1edbc 576 * @param __HANDLE__: DMA handle
AnnaBridge 171:3a7713b1edbc 577 * @retval The number of remaining data units in the current DMA Channel transfer.
AnnaBridge 171:3a7713b1edbc 578 */
AnnaBridge 171:3a7713b1edbc 579 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
AnnaBridge 171:3a7713b1edbc 580
AnnaBridge 171:3a7713b1edbc 581 /**
AnnaBridge 171:3a7713b1edbc 582 * @}
AnnaBridge 171:3a7713b1edbc 583 */
AnnaBridge 171:3a7713b1edbc 584
AnnaBridge 171:3a7713b1edbc 585 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 586
AnnaBridge 171:3a7713b1edbc 587 /** @addtogroup DMA_Exported_Functions
AnnaBridge 171:3a7713b1edbc 588 * @{
AnnaBridge 171:3a7713b1edbc 589 */
AnnaBridge 171:3a7713b1edbc 590
AnnaBridge 171:3a7713b1edbc 591 /** @addtogroup DMA_Exported_Functions_Group1
AnnaBridge 171:3a7713b1edbc 592 * @{
AnnaBridge 171:3a7713b1edbc 593 */
AnnaBridge 171:3a7713b1edbc 594 /* Initialization and de-initialization functions *****************************/
AnnaBridge 171:3a7713b1edbc 595 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 596 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 597 /**
AnnaBridge 171:3a7713b1edbc 598 * @}
AnnaBridge 171:3a7713b1edbc 599 */
AnnaBridge 171:3a7713b1edbc 600
AnnaBridge 171:3a7713b1edbc 601 /** @addtogroup DMA_Exported_Functions_Group2
AnnaBridge 171:3a7713b1edbc 602 * @{
AnnaBridge 171:3a7713b1edbc 603 */
AnnaBridge 171:3a7713b1edbc 604 /* IO operation functions *****************************************************/
AnnaBridge 171:3a7713b1edbc 605 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
AnnaBridge 171:3a7713b1edbc 606 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
AnnaBridge 171:3a7713b1edbc 607 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 608 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 609 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
AnnaBridge 171:3a7713b1edbc 610 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 611 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
AnnaBridge 171:3a7713b1edbc 612 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
AnnaBridge 171:3a7713b1edbc 613
AnnaBridge 171:3a7713b1edbc 614 /**
AnnaBridge 171:3a7713b1edbc 615 * @}
AnnaBridge 171:3a7713b1edbc 616 */
AnnaBridge 171:3a7713b1edbc 617
AnnaBridge 171:3a7713b1edbc 618 /** @addtogroup DMA_Exported_Functions_Group3
AnnaBridge 171:3a7713b1edbc 619 * @{
AnnaBridge 171:3a7713b1edbc 620 */
AnnaBridge 171:3a7713b1edbc 621 /* Peripheral State and Error functions ***************************************/
AnnaBridge 171:3a7713b1edbc 622 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 623 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 624 /**
AnnaBridge 171:3a7713b1edbc 625 * @}
AnnaBridge 171:3a7713b1edbc 626 */
AnnaBridge 171:3a7713b1edbc 627
AnnaBridge 171:3a7713b1edbc 628 /**
AnnaBridge 171:3a7713b1edbc 629 * @}
AnnaBridge 171:3a7713b1edbc 630 */
AnnaBridge 171:3a7713b1edbc 631
AnnaBridge 171:3a7713b1edbc 632 /* Private macros ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 633 /** @defgroup DMA_Private_Macros DMA Private Macros
AnnaBridge 171:3a7713b1edbc 634 * @{
AnnaBridge 171:3a7713b1edbc 635 */
AnnaBridge 171:3a7713b1edbc 636
AnnaBridge 171:3a7713b1edbc 637 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
AnnaBridge 171:3a7713b1edbc 638 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
AnnaBridge 171:3a7713b1edbc 639 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
AnnaBridge 171:3a7713b1edbc 640
AnnaBridge 171:3a7713b1edbc 641 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
AnnaBridge 171:3a7713b1edbc 642
AnnaBridge 171:3a7713b1edbc 643 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
AnnaBridge 171:3a7713b1edbc 644 ((STATE) == DMA_PINC_DISABLE))
AnnaBridge 171:3a7713b1edbc 645
AnnaBridge 171:3a7713b1edbc 646 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
AnnaBridge 171:3a7713b1edbc 647 ((STATE) == DMA_MINC_DISABLE))
AnnaBridge 171:3a7713b1edbc 648
AnnaBridge 171:3a7713b1edbc 649 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
AnnaBridge 171:3a7713b1edbc 650 ((REQUEST) == DMA_REQUEST_1) || \
AnnaBridge 171:3a7713b1edbc 651 ((REQUEST) == DMA_REQUEST_2) || \
AnnaBridge 171:3a7713b1edbc 652 ((REQUEST) == DMA_REQUEST_3) || \
AnnaBridge 171:3a7713b1edbc 653 ((REQUEST) == DMA_REQUEST_4) || \
AnnaBridge 171:3a7713b1edbc 654 ((REQUEST) == DMA_REQUEST_5) || \
AnnaBridge 171:3a7713b1edbc 655 ((REQUEST) == DMA_REQUEST_6) || \
AnnaBridge 171:3a7713b1edbc 656 ((REQUEST) == DMA_REQUEST_7))
AnnaBridge 171:3a7713b1edbc 657 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
AnnaBridge 171:3a7713b1edbc 658 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
AnnaBridge 171:3a7713b1edbc 659 ((SIZE) == DMA_PDATAALIGN_WORD))
AnnaBridge 171:3a7713b1edbc 660
AnnaBridge 171:3a7713b1edbc 661 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
AnnaBridge 171:3a7713b1edbc 662 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
AnnaBridge 171:3a7713b1edbc 663 ((SIZE) == DMA_MDATAALIGN_WORD ))
AnnaBridge 171:3a7713b1edbc 664
AnnaBridge 171:3a7713b1edbc 665 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
AnnaBridge 171:3a7713b1edbc 666 ((MODE) == DMA_CIRCULAR))
AnnaBridge 171:3a7713b1edbc 667
AnnaBridge 171:3a7713b1edbc 668 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
AnnaBridge 171:3a7713b1edbc 669 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
AnnaBridge 171:3a7713b1edbc 670 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
AnnaBridge 171:3a7713b1edbc 671 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
AnnaBridge 171:3a7713b1edbc 672
AnnaBridge 171:3a7713b1edbc 673 /**
AnnaBridge 171:3a7713b1edbc 674 * @}
AnnaBridge 171:3a7713b1edbc 675 */
AnnaBridge 171:3a7713b1edbc 676
AnnaBridge 171:3a7713b1edbc 677 /* Private functions ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 678
AnnaBridge 171:3a7713b1edbc 679 /**
AnnaBridge 171:3a7713b1edbc 680 * @}
AnnaBridge 171:3a7713b1edbc 681 */
AnnaBridge 171:3a7713b1edbc 682
AnnaBridge 171:3a7713b1edbc 683 /**
AnnaBridge 171:3a7713b1edbc 684 * @}
AnnaBridge 171:3a7713b1edbc 685 */
AnnaBridge 171:3a7713b1edbc 686
AnnaBridge 171:3a7713b1edbc 687 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 688 }
AnnaBridge 171:3a7713b1edbc 689 #endif
AnnaBridge 171:3a7713b1edbc 690
AnnaBridge 171:3a7713b1edbc 691 #endif /* __STM32L1xx_HAL_DMA_H */
AnnaBridge 171:3a7713b1edbc 692
AnnaBridge 171:3a7713b1edbc 693 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/