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TARGET_MAX32600MBED/TOOLCHAIN_IAR/afe_regs.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 12 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 24 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 25 *
AnnaBridge 171:3a7713b1edbc 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 30 * ownership rights.
AnnaBridge 171:3a7713b1edbc 31 *******************************************************************************
AnnaBridge 171:3a7713b1edbc 32 */
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #ifndef _MXC_AFE_REGS_H
AnnaBridge 171:3a7713b1edbc 35 #define _MXC_AFE_REGS_H
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 38 extern "C" {
AnnaBridge 171:3a7713b1edbc 39 #endif
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 42
AnnaBridge 171:3a7713b1edbc 43 /**
AnnaBridge 171:3a7713b1edbc 44 * @file afe_regs.h
AnnaBridge 171:3a7713b1edbc 45 * @addtogroup afe AFE
AnnaBridge 171:3a7713b1edbc 46 * @{
AnnaBridge 171:3a7713b1edbc 47 */
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /**
AnnaBridge 171:3a7713b1edbc 50 * @brief Defines Configure Options for the LED Ports.
AnnaBridge 171:3a7713b1edbc 51 */
AnnaBridge 171:3a7713b1edbc 52 typedef enum {
AnnaBridge 171:3a7713b1edbc 53 /** LED Sink Port 0 with OpAmp A, LED Sink Port 1 with OpAmp C */
AnnaBridge 171:3a7713b1edbc 54 MXC_E_AFE_LED_CFG_PORT_OPAMP_A_C = 0,
AnnaBridge 171:3a7713b1edbc 55 /** LED Sink Port 0 with OpAmp B, LED Sink Port 1 with OpAmp D */
AnnaBridge 171:3a7713b1edbc 56 MXC_E_AFE_LED_CFG_PORT_OPAMP_B_D,
AnnaBridge 171:3a7713b1edbc 57 /** Disable LED Sink Port 0,Disable LED Sink Port 1 */
AnnaBridge 171:3a7713b1edbc 58 MXC_E_AFE_LED_CFG_PORT_DISABLED,
AnnaBridge 171:3a7713b1edbc 59 } mxc_afe_led_cfg_port_t;
AnnaBridge 171:3a7713b1edbc 60
AnnaBridge 171:3a7713b1edbc 61 /**
AnnaBridge 171:3a7713b1edbc 62 * @brief Setup of Wake Up Detector for LPCs.
AnnaBridge 171:3a7713b1edbc 63 */
AnnaBridge 171:3a7713b1edbc 64 typedef enum {
AnnaBridge 171:3a7713b1edbc 65 /** IDLE */
AnnaBridge 171:3a7713b1edbc 66 MXC_E_AFE_EN_WUD_COMP_IDLE = 0,
AnnaBridge 171:3a7713b1edbc 67 /** Activate WUD for falling edges */
AnnaBridge 171:3a7713b1edbc 68 MXC_E_AFE_EN_WUD_COMP_FALLING_EDGE = 2,
AnnaBridge 171:3a7713b1edbc 69 /** Activate WUD for rising edges */
AnnaBridge 171:3a7713b1edbc 70 MXC_E_AFE_EN_WUD_COMP_RISING_EDGE = 3
AnnaBridge 171:3a7713b1edbc 71 } mxc_afe_en_wud_comp_t;
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 /**
AnnaBridge 171:3a7713b1edbc 74 * @brief LPC InMode.
AnnaBridge 171:3a7713b1edbc 75 */
AnnaBridge 171:3a7713b1edbc 76 typedef enum {
AnnaBridge 171:3a7713b1edbc 77 /** InMode: both Nch and Pch */
AnnaBridge 171:3a7713b1edbc 78 MXC_E_AFE_IN_MODE_COMP_NCH_PCH = 0,
AnnaBridge 171:3a7713b1edbc 79 /** InMode: only Nch */
AnnaBridge 171:3a7713b1edbc 80 MXC_E_AFE_IN_MODE_COMP_NCH,
AnnaBridge 171:3a7713b1edbc 81 /** InMode: only Pch */
AnnaBridge 171:3a7713b1edbc 82 MXC_E_AFE_IN_MODE_COMP_PCH,
AnnaBridge 171:3a7713b1edbc 83 } mxc_afe_in_mode_comp_t;
AnnaBridge 171:3a7713b1edbc 84
AnnaBridge 171:3a7713b1edbc 85 /**
AnnaBridge 171:3a7713b1edbc 86 * @brief LPC Bias.
AnnaBridge 171:3a7713b1edbc 87 */
AnnaBridge 171:3a7713b1edbc 88 typedef enum {
AnnaBridge 171:3a7713b1edbc 89 /** BIAS 0.52uA Delay 4.0us */
AnnaBridge 171:3a7713b1edbc 90 MXC_E_AFE_BIAS_MODE_COMP_0 = 0,
AnnaBridge 171:3a7713b1edbc 91 /** BIAS 1.4uA Delay 1.7us */
AnnaBridge 171:3a7713b1edbc 92 MXC_E_AFE_BIAS_MODE_COMP_1,
AnnaBridge 171:3a7713b1edbc 93 /** BIAS 2.8uA Delay 1.1us */
AnnaBridge 171:3a7713b1edbc 94 MXC_E_AFE_BIAS_MODE_COMP_2,
AnnaBridge 171:3a7713b1edbc 95 /** BIAS 5.1uA Delay 0.7us */
AnnaBridge 171:3a7713b1edbc 96 MXC_E_AFE_BIAS_MODE_COMP_3
AnnaBridge 171:3a7713b1edbc 97 } mxc_afe_bias_mode_comp_t;
AnnaBridge 171:3a7713b1edbc 98
AnnaBridge 171:3a7713b1edbc 99 /**
AnnaBridge 171:3a7713b1edbc 100 * @brief TMON Current Value.
AnnaBridge 171:3a7713b1edbc 101 */
AnnaBridge 171:3a7713b1edbc 102 typedef enum {
AnnaBridge 171:3a7713b1edbc 103 /** TMON Current 4uA */
AnnaBridge 171:3a7713b1edbc 104 MXC_E_AFE_TMON_CURRENT_VAL_0 = 0,
AnnaBridge 171:3a7713b1edbc 105 /** TMON Current 60uA */
AnnaBridge 171:3a7713b1edbc 106 MXC_E_AFE_TMON_CURRENT_VAL_1,
AnnaBridge 171:3a7713b1edbc 107 /** TMON Current 64uA */
AnnaBridge 171:3a7713b1edbc 108 MXC_E_AFE_TMON_CURRENT_VAL_2,
AnnaBridge 171:3a7713b1edbc 109 /** TMON Current 120uA */
AnnaBridge 171:3a7713b1edbc 110 MXC_E_AFE_TMON_CURRENT_VAL_3
AnnaBridge 171:3a7713b1edbc 111 } mxc_afe_tmon_current_t;
AnnaBridge 171:3a7713b1edbc 112
AnnaBridge 171:3a7713b1edbc 113 /**
AnnaBridge 171:3a7713b1edbc 114 * @brief REFADC and REFDAC Voltage Select.
AnnaBridge 171:3a7713b1edbc 115 */
AnnaBridge 171:3a7713b1edbc 116 typedef enum {
AnnaBridge 171:3a7713b1edbc 117 /** Voltage Reference = 1.024 V */
AnnaBridge 171:3a7713b1edbc 118 MXC_E_AFE_REF_VOLT_SEL_1024 = 0,
AnnaBridge 171:3a7713b1edbc 119 /** Voltage Reference = 1.5 V */
AnnaBridge 171:3a7713b1edbc 120 MXC_E_AFE_REF_VOLT_SEL_1500,
AnnaBridge 171:3a7713b1edbc 121 /** Voltage Reference = 2.048 V */
AnnaBridge 171:3a7713b1edbc 122 MXC_E_AFE_REF_VOLT_SEL_2048,
AnnaBridge 171:3a7713b1edbc 123 /** Voltage Reference = 2.5 V */
AnnaBridge 171:3a7713b1edbc 124 MXC_E_AFE_REF_VOLT_SEL_2500
AnnaBridge 171:3a7713b1edbc 125 } mxc_afe_ref_volt_sel_t;
AnnaBridge 171:3a7713b1edbc 126
AnnaBridge 171:3a7713b1edbc 127 /**
AnnaBridge 171:3a7713b1edbc 128 * @brief Selection for DAC VOltage Reference, REFADC or REFDAC.
AnnaBridge 171:3a7713b1edbc 129 */
AnnaBridge 171:3a7713b1edbc 130 typedef enum {
AnnaBridge 171:3a7713b1edbc 131 /** DAC Voltage Reference = REFADC */
AnnaBridge 171:3a7713b1edbc 132 MXC_E_AFE_DAC_REF_REFADC = 0,
AnnaBridge 171:3a7713b1edbc 133 /** DAC Voltage Reference = REFDAC */
AnnaBridge 171:3a7713b1edbc 134 MXC_E_AFE_DAC_REF_REFDAC
AnnaBridge 171:3a7713b1edbc 135 } mxc_afe_dac_ref_t;
AnnaBridge 171:3a7713b1edbc 136
AnnaBridge 171:3a7713b1edbc 137 /**
AnnaBridge 171:3a7713b1edbc 138 * @brief Selection for LPC Hysteresis.
AnnaBridge 171:3a7713b1edbc 139 */
AnnaBridge 171:3a7713b1edbc 140 typedef enum {
AnnaBridge 171:3a7713b1edbc 141 /** LPC Hysteresis = 0 mV */
AnnaBridge 171:3a7713b1edbc 142 MXC_E_AFE_HYST_COMP_0 = 0,
AnnaBridge 171:3a7713b1edbc 143 /** LPC Hysteresis = 7.5 mV */
AnnaBridge 171:3a7713b1edbc 144 MXC_E_AFE_HYST_COMP_1,
AnnaBridge 171:3a7713b1edbc 145 /** LPC Hysteresis = 15 mV */
AnnaBridge 171:3a7713b1edbc 146 MXC_E_AFE_HYST_COMP_2,
AnnaBridge 171:3a7713b1edbc 147 /** LPC Hysteresis = 30 mV */
AnnaBridge 171:3a7713b1edbc 148 MXC_E_AFE_HYST_COMP_3
AnnaBridge 171:3a7713b1edbc 149 } mxc_afe_hyst_comp_t;
AnnaBridge 171:3a7713b1edbc 150
AnnaBridge 171:3a7713b1edbc 151 /**
AnnaBridge 171:3a7713b1edbc 152 * @brief Selection for MUX for SCM_or_sel.
AnnaBridge 171:3a7713b1edbc 153 */
AnnaBridge 171:3a7713b1edbc 154 typedef enum {
AnnaBridge 171:3a7713b1edbc 155 /** SCM_or = HIZ */
AnnaBridge 171:3a7713b1edbc 156 MXC_E_AFE_SCM_OR_SEL_HIZ = 0,
AnnaBridge 171:3a7713b1edbc 157 /** SCM_or = SCM0 */
AnnaBridge 171:3a7713b1edbc 158 MXC_E_AFE_SCM_OR_SEL_SCM0,
AnnaBridge 171:3a7713b1edbc 159 /** SCM_or = SCM1 */
AnnaBridge 171:3a7713b1edbc 160 MXC_E_AFE_SCM_OR_SEL_SCM1,
AnnaBridge 171:3a7713b1edbc 161 /** SCM_or = SCM2 */
AnnaBridge 171:3a7713b1edbc 162 MXC_E_AFE_SCM_OR_SEL_SCM2,
AnnaBridge 171:3a7713b1edbc 163 /** SCM_or = SCM3 */
AnnaBridge 171:3a7713b1edbc 164 MXC_E_AFE_SCM_OR_SEL_SCM3
AnnaBridge 171:3a7713b1edbc 165 } mxc_afe_scm_or_sel_t;
AnnaBridge 171:3a7713b1edbc 166
AnnaBridge 171:3a7713b1edbc 167 /**
AnnaBridge 171:3a7713b1edbc 168 * @brief Selection for MUX for SNO_or_sel.
AnnaBridge 171:3a7713b1edbc 169 */
AnnaBridge 171:3a7713b1edbc 170 typedef enum {
AnnaBridge 171:3a7713b1edbc 171 /** SNO_or = HIZ */
AnnaBridge 171:3a7713b1edbc 172 MXC_E_AFE_SNO_OR_SEL_HIZ = 0,
AnnaBridge 171:3a7713b1edbc 173 /** SNO_or = SNO0 */
AnnaBridge 171:3a7713b1edbc 174 MXC_E_AFE_SNO_OR_SEL_SNO0,
AnnaBridge 171:3a7713b1edbc 175 /** SNO_or = SNO1 */
AnnaBridge 171:3a7713b1edbc 176 MXC_E_AFE_SNO_OR_SEL_SNO1,
AnnaBridge 171:3a7713b1edbc 177 /** SNO_or = SNO2 */
AnnaBridge 171:3a7713b1edbc 178 MXC_E_AFE_SNO_OR_SEL_SNO2,
AnnaBridge 171:3a7713b1edbc 179 /** SNO_or = SNO3 */
AnnaBridge 171:3a7713b1edbc 180 MXC_E_AFE_SNO_OR_SEL_SNO3
AnnaBridge 171:3a7713b1edbc 181 } mxc_afe_sno_or_sel_t;
AnnaBridge 171:3a7713b1edbc 182
AnnaBridge 171:3a7713b1edbc 183 /**
AnnaBridge 171:3a7713b1edbc 184 * @brief Selection for MUX DACx_sel.
AnnaBridge 171:3a7713b1edbc 185 */
AnnaBridge 171:3a7713b1edbc 186 typedef enum {
AnnaBridge 171:3a7713b1edbc 187 /** dacx = DACOP */
AnnaBridge 171:3a7713b1edbc 188 MXC_E_AFE_DACX_SEL_P = 0,
AnnaBridge 171:3a7713b1edbc 189 /** dacx = DACON */
AnnaBridge 171:3a7713b1edbc 190 MXC_E_AFE_DACX_SEL_N
AnnaBridge 171:3a7713b1edbc 191 } mxc_afe_dacx_sel_t;
AnnaBridge 171:3a7713b1edbc 192
AnnaBridge 171:3a7713b1edbc 193 /**
AnnaBridge 171:3a7713b1edbc 194 * @brief Selection for state of Switch.
AnnaBridge 171:3a7713b1edbc 195 */
AnnaBridge 171:3a7713b1edbc 196 typedef enum {
AnnaBridge 171:3a7713b1edbc 197 /** Switch is OPEN */
AnnaBridge 171:3a7713b1edbc 198 MXC_E_AFE_CLOSE_SPST_SWITCH_OPEN = 0,
AnnaBridge 171:3a7713b1edbc 199 /** Switch is CLOSED */
AnnaBridge 171:3a7713b1edbc 200 MXC_E_AFE_CLOSE_SPST_SWITCH_CLOSE
AnnaBridge 171:3a7713b1edbc 201 } mxc_afe_close_spst_t;
AnnaBridge 171:3a7713b1edbc 202
AnnaBridge 171:3a7713b1edbc 203 /**
AnnaBridge 171:3a7713b1edbc 204 * @brief Switch to Connect Positive Pad to GND.
AnnaBridge 171:3a7713b1edbc 205 */
AnnaBridge 171:3a7713b1edbc 206 typedef enum {
AnnaBridge 171:3a7713b1edbc 207 /** Positive Pad GND Switch OPEN */
AnnaBridge 171:3a7713b1edbc 208 MXC_E_AFE_GND_SEL_OPAMP_SWITCH_OPEN = 0,
AnnaBridge 171:3a7713b1edbc 209 /** Positive Pad GND Switch CLOSED */
AnnaBridge 171:3a7713b1edbc 210 MXC_E_AFE_GND_SEL_OPAMP_SWITCH_CLOSED
AnnaBridge 171:3a7713b1edbc 211 } mxc_afe_gnd_sel_opamp_t;
AnnaBridge 171:3a7713b1edbc 212
AnnaBridge 171:3a7713b1edbc 213 /**
AnnaBridge 171:3a7713b1edbc 214 * @brief MUX Selection for OpPsel.
AnnaBridge 171:3a7713b1edbc 215 */
AnnaBridge 171:3a7713b1edbc 216 typedef enum {
AnnaBridge 171:3a7713b1edbc 217 /** OpPsel = INx+ */
AnnaBridge 171:3a7713b1edbc 218 MXC_E_AFE_P_IN_SEL_OPAMP_INPLUS = 0,
AnnaBridge 171:3a7713b1edbc 219 /** OpPsel = DAC_or */
AnnaBridge 171:3a7713b1edbc 220 MXC_E_AFE_P_IN_SEL_OPAMP_DAC_OR,
AnnaBridge 171:3a7713b1edbc 221 /** OpPsel = SNO_or */
AnnaBridge 171:3a7713b1edbc 222 MXC_E_AFE_P_IN_SEL_OPAMP_SNO_OR,
AnnaBridge 171:3a7713b1edbc 223 /** OpPsel = DAC_or also output on INx+ */
AnnaBridge 171:3a7713b1edbc 224 MXC_E_AFE_P_IN_SEL_OPAMP_DAC_OR_AND_INPLUS
AnnaBridge 171:3a7713b1edbc 225 } mxc_afe_p_in_sel_opamp_t;
AnnaBridge 171:3a7713b1edbc 226
AnnaBridge 171:3a7713b1edbc 227 /**
AnnaBridge 171:3a7713b1edbc 228 * @brief MUX Selection for OpNsel.
AnnaBridge 171:3a7713b1edbc 229 */
AnnaBridge 171:3a7713b1edbc 230 typedef enum {
AnnaBridge 171:3a7713b1edbc 231 /** OpNsel = INx- */
AnnaBridge 171:3a7713b1edbc 232 MXC_E_AFE_N_IN_SEL_OPAMP_INMINUS = 0,
AnnaBridge 171:3a7713b1edbc 233 /** OpNsel = OUTx */
AnnaBridge 171:3a7713b1edbc 234 MXC_E_AFE_N_IN_SEL_OPAMP_OUT,
AnnaBridge 171:3a7713b1edbc 235 /** OpNsel = SCM_or */
AnnaBridge 171:3a7713b1edbc 236 MXC_E_AFE_N_IN_SEL_OPAMP_SCM_OR,
AnnaBridge 171:3a7713b1edbc 237 /**OpNsel = SCM_or also output on INx- */
AnnaBridge 171:3a7713b1edbc 238 MXC_E_AFE_N_IN_SEL_OPAMP_SCM_OR_AND_INMINUS,
AnnaBridge 171:3a7713b1edbc 239 } mxc_afe_n_in_sel_opamp_t;
AnnaBridge 171:3a7713b1edbc 240
AnnaBridge 171:3a7713b1edbc 241 /**
AnnaBridge 171:3a7713b1edbc 242 * @brief MUX Selection for DAC_sel.
AnnaBridge 171:3a7713b1edbc 243 */
AnnaBridge 171:3a7713b1edbc 244 typedef enum {
AnnaBridge 171:3a7713b1edbc 245 /** DAC_or = DAC0 */
AnnaBridge 171:3a7713b1edbc 246 MXC_E_AFE_DAC_SEL_DAC0 = 0,
AnnaBridge 171:3a7713b1edbc 247 /** DAC_or = DAC1 */
AnnaBridge 171:3a7713b1edbc 248 MXC_E_AFE_DAC_SEL_DAC1,
AnnaBridge 171:3a7713b1edbc 249 /** DAC_or = DAC2P */
AnnaBridge 171:3a7713b1edbc 250 MXC_E_AFE_DAC_SEL_DAC2P,
AnnaBridge 171:3a7713b1edbc 251 /** DAC_or = DAC3P */
AnnaBridge 171:3a7713b1edbc 252 MXC_E_AFE_DAC_SEL_DAC3P
AnnaBridge 171:3a7713b1edbc 253 } mxc_afe_dac_sel_t;
AnnaBridge 171:3a7713b1edbc 254
AnnaBridge 171:3a7713b1edbc 255 /**
AnnaBridge 171:3a7713b1edbc 256 * @brief MUX Selection for NPAD_sel.
AnnaBridge 171:3a7713b1edbc 257 */
AnnaBridge 171:3a7713b1edbc 258 typedef enum {
AnnaBridge 171:3a7713b1edbc 259 /** NPAD_Sel = HIZ */
AnnaBridge 171:3a7713b1edbc 260 MXC_E_AFE_NPAD_SEL_HIZ = 0,
AnnaBridge 171:3a7713b1edbc 261 /** NPAD_Sel = LED Observe Port */
AnnaBridge 171:3a7713b1edbc 262 MXC_E_AFE_NPAD_SEL_LED_OBS_PORT,
AnnaBridge 171:3a7713b1edbc 263 /** NPAD_Sel = DAC_or */
AnnaBridge 171:3a7713b1edbc 264 MXC_E_AFE_NPAD_SEL_DAC_OR,
AnnaBridge 171:3a7713b1edbc 265 /** NPAD_Sel = DAC_or and LED Observe Port */
AnnaBridge 171:3a7713b1edbc 266 MXC_E_AFE_NPAD_SEL_DAC_OR_AND_LED_OBS_PORT
AnnaBridge 171:3a7713b1edbc 267 } mxc_afe_npad_sel_t;
AnnaBridge 171:3a7713b1edbc 268
AnnaBridge 171:3a7713b1edbc 269 /**
AnnaBridge 171:3a7713b1edbc 270 * @brief MUX Selection for CmpPSel.
AnnaBridge 171:3a7713b1edbc 271 */
AnnaBridge 171:3a7713b1edbc 272 typedef enum {
AnnaBridge 171:3a7713b1edbc 273 /** CmpPSel = INx+ */
AnnaBridge 171:3a7713b1edbc 274 MXC_E_AFE_POS_IN_SEL_COMP_INPLUS = 0,
AnnaBridge 171:3a7713b1edbc 275 /** CmpPSel = SCM */
AnnaBridge 171:3a7713b1edbc 276 MXC_E_AFE_POS_IN_SEL_COMP_SCM,
AnnaBridge 171:3a7713b1edbc 277 /** CmpPSel = dac1 */
AnnaBridge 171:3a7713b1edbc 278 MXC_E_AFE_POS_IN_SEL_COMP_DAC1,
AnnaBridge 171:3a7713b1edbc 279 /** CmpPSel = DAC3P */
AnnaBridge 171:3a7713b1edbc 280 MXC_E_AFE_POS_IN_SEL_COMP_DAC3P,
AnnaBridge 171:3a7713b1edbc 281 /** CmpPSel = LED Observe Port */
AnnaBridge 171:3a7713b1edbc 282 MXC_E_AFE_POS_IN_SEL_COMP_LED_OBS_PORT,
AnnaBridge 171:3a7713b1edbc 283 /** CmpPSel = dac1 also output on INx+ */
AnnaBridge 171:3a7713b1edbc 284 MXC_E_AFE_POS_IN_SEL_COMP_DAC1_AND_INPLUS,
AnnaBridge 171:3a7713b1edbc 285 /** CmpPSel = DAC3P also output on INx+ */
AnnaBridge 171:3a7713b1edbc 286 MXC_E_AFE_POS_IN_SEL_COMP_DAC3P_AND_INPLUS,
AnnaBridge 171:3a7713b1edbc 287 /** CmpPSel = dac1 also output on SCM */
AnnaBridge 171:3a7713b1edbc 288 MXC_E_AFE_POS_IN_SEL_COMP_DAC1_AND_SCM
AnnaBridge 171:3a7713b1edbc 289 } mxc_afe_pos_in_sel_comp_t;
AnnaBridge 171:3a7713b1edbc 290
AnnaBridge 171:3a7713b1edbc 291 /**
AnnaBridge 171:3a7713b1edbc 292 * @brief MUX Selection for CmpNSel.
AnnaBridge 171:3a7713b1edbc 293 */
AnnaBridge 171:3a7713b1edbc 294 typedef enum {
AnnaBridge 171:3a7713b1edbc 295 /** CmpNSel = INx- */
AnnaBridge 171:3a7713b1edbc 296 MXC_E_AFE_NEG_IN_SEL_COMP_INMINUS = 0,
AnnaBridge 171:3a7713b1edbc 297 /** CmpNSel = SNO */
AnnaBridge 171:3a7713b1edbc 298 MXC_E_AFE_NEG_IN_SEL_COMP_SNO,
AnnaBridge 171:3a7713b1edbc 299 /** CmpNSel = dac0 */
AnnaBridge 171:3a7713b1edbc 300 MXC_E_AFE_NEG_IN_SEL_COMP_DAC0,
AnnaBridge 171:3a7713b1edbc 301 /** CmpNSel = DAC2P */
AnnaBridge 171:3a7713b1edbc 302 MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P,
AnnaBridge 171:3a7713b1edbc 303 /** CmpNSel = LED Observation Port */
AnnaBridge 171:3a7713b1edbc 304 MXC_E_AFE_NEG_IN_SEL_COMP_LED_OBS_PORT,
AnnaBridge 171:3a7713b1edbc 305 /** CmpNSel = dac0 also output on INx- */
AnnaBridge 171:3a7713b1edbc 306 MXC_E_AFE_NEG_IN_SEL_COMP_DAC0_AND_INMINUS,
AnnaBridge 171:3a7713b1edbc 307 /** CmpNSel = DAC2 also output on INx- */
AnnaBridge 171:3a7713b1edbc 308 MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P_AND_INMINUS,
AnnaBridge 171:3a7713b1edbc 309 /** CmpNSel = DAC2 also output on SNO */
AnnaBridge 171:3a7713b1edbc 310 MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P_AND_SNO
AnnaBridge 171:3a7713b1edbc 311 } mxc_afe_neg_in_sel_comp_t;
AnnaBridge 171:3a7713b1edbc 312
AnnaBridge 171:3a7713b1edbc 313 /* Offset Register Description
AnnaBridge 171:3a7713b1edbc 314 ====== ==================================================== */
AnnaBridge 171:3a7713b1edbc 315 typedef struct {
AnnaBridge 171:3a7713b1edbc 316 __IO uint32_t intr; /* 0x0000 Analog Front End Interrupt Flags and Enable/Disable */
AnnaBridge 171:3a7713b1edbc 317 __IO uint32_t ctrl0; /* 0x0004 Analog Front End Control 0 */
AnnaBridge 171:3a7713b1edbc 318 __IO uint32_t ctrl1; /* 0x0008 Analog Front End Control 1 */
AnnaBridge 171:3a7713b1edbc 319 __IO uint32_t ctrl2; /* 0x000C Analog Front End Control 2 */
AnnaBridge 171:3a7713b1edbc 320 __IO uint32_t ctrl3; /* 0x0010 Analog Front End Control 3 */
AnnaBridge 171:3a7713b1edbc 321 __IO uint32_t ctrl4; /* 0x0014 Analog Front End Control 4 */
AnnaBridge 171:3a7713b1edbc 322 __IO uint32_t ctrl5; /* 0x0018 Analog Front End Control 5 */
AnnaBridge 171:3a7713b1edbc 323 } mxc_afe_regs_t;
AnnaBridge 171:3a7713b1edbc 324
AnnaBridge 171:3a7713b1edbc 325 /*
AnnaBridge 171:3a7713b1edbc 326 Register offsets for module AFE.
AnnaBridge 171:3a7713b1edbc 327 */
AnnaBridge 171:3a7713b1edbc 328 #define MXC_R_AFE_OFFS_INTR ((uint32_t)0x00000000UL)
AnnaBridge 171:3a7713b1edbc 329 #define MXC_R_AFE_OFFS_CTRL0 ((uint32_t)0x00000004UL)
AnnaBridge 171:3a7713b1edbc 330 #define MXC_R_AFE_OFFS_CTRL1 ((uint32_t)0x00000008UL)
AnnaBridge 171:3a7713b1edbc 331 #define MXC_R_AFE_OFFS_CTRL2 ((uint32_t)0x0000000CUL)
AnnaBridge 171:3a7713b1edbc 332 #define MXC_R_AFE_OFFS_CTRL3 ((uint32_t)0x00000010UL)
AnnaBridge 171:3a7713b1edbc 333 #define MXC_R_AFE_OFFS_CTRL4 ((uint32_t)0x00000014UL)
AnnaBridge 171:3a7713b1edbc 334 #define MXC_R_AFE_OFFS_CTRL5 ((uint32_t)0x00000018UL)
AnnaBridge 171:3a7713b1edbc 335
AnnaBridge 171:3a7713b1edbc 336 /*
AnnaBridge 171:3a7713b1edbc 337 Field positions and masks for module AFE.
AnnaBridge 171:3a7713b1edbc 338 */
AnnaBridge 171:3a7713b1edbc 339 #define MXC_F_AFE_INTR_OP_COMP0_IF_POS 0
AnnaBridge 171:3a7713b1edbc 340 #define MXC_F_AFE_INTR_OP_COMP0_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_IF_POS))
AnnaBridge 171:3a7713b1edbc 341 #define MXC_F_AFE_INTR_OP_COMP1_IF_POS 1
AnnaBridge 171:3a7713b1edbc 342 #define MXC_F_AFE_INTR_OP_COMP1_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_IF_POS))
AnnaBridge 171:3a7713b1edbc 343 #define MXC_F_AFE_INTR_OP_COMP2_IF_POS 2
AnnaBridge 171:3a7713b1edbc 344 #define MXC_F_AFE_INTR_OP_COMP2_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_IF_POS))
AnnaBridge 171:3a7713b1edbc 345 #define MXC_F_AFE_INTR_OP_COMP3_IF_POS 3
AnnaBridge 171:3a7713b1edbc 346 #define MXC_F_AFE_INTR_OP_COMP3_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_IF_POS))
AnnaBridge 171:3a7713b1edbc 347 #define MXC_F_AFE_INTR_LP_COMP0_IF_POS 4
AnnaBridge 171:3a7713b1edbc 348 #define MXC_F_AFE_INTR_LP_COMP0_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_IF_POS))
AnnaBridge 171:3a7713b1edbc 349 #define MXC_F_AFE_INTR_LP_COMP1_IF_POS 5
AnnaBridge 171:3a7713b1edbc 350 #define MXC_F_AFE_INTR_LP_COMP1_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_IF_POS))
AnnaBridge 171:3a7713b1edbc 351 #define MXC_F_AFE_INTR_LP_COMP2_IF_POS 6
AnnaBridge 171:3a7713b1edbc 352 #define MXC_F_AFE_INTR_LP_COMP2_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_IF_POS))
AnnaBridge 171:3a7713b1edbc 353 #define MXC_F_AFE_INTR_LP_COMP3_IF_POS 7
AnnaBridge 171:3a7713b1edbc 354 #define MXC_F_AFE_INTR_LP_COMP3_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_IF_POS))
AnnaBridge 171:3a7713b1edbc 355 #define MXC_F_AFE_INTR_OP_COMP0_NMI_PMU_POS 8
AnnaBridge 171:3a7713b1edbc 356 #define MXC_F_AFE_INTR_OP_COMP0_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_NMI_PMU_POS))
AnnaBridge 171:3a7713b1edbc 357 #define MXC_F_AFE_INTR_OP_COMP1_NMI_PMU_POS 9
AnnaBridge 171:3a7713b1edbc 358 #define MXC_F_AFE_INTR_OP_COMP1_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_NMI_PMU_POS))
AnnaBridge 171:3a7713b1edbc 359 #define MXC_F_AFE_INTR_OP_COMP2_NMI_PMU_POS 10
AnnaBridge 171:3a7713b1edbc 360 #define MXC_F_AFE_INTR_OP_COMP2_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_NMI_PMU_POS))
AnnaBridge 171:3a7713b1edbc 361 #define MXC_F_AFE_INTR_OP_COMP3_NMI_PMU_POS 11
AnnaBridge 171:3a7713b1edbc 362 #define MXC_F_AFE_INTR_OP_COMP3_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_NMI_PMU_POS))
AnnaBridge 171:3a7713b1edbc 363 #define MXC_F_AFE_INTR_LP_COMP0_NMI_PMU_POS 12
AnnaBridge 171:3a7713b1edbc 364 #define MXC_F_AFE_INTR_LP_COMP0_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_NMI_PMU_POS))
AnnaBridge 171:3a7713b1edbc 365 #define MXC_F_AFE_INTR_LP_COMP1_NMI_PMU_POS 13
AnnaBridge 171:3a7713b1edbc 366 #define MXC_F_AFE_INTR_LP_COMP1_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_NMI_PMU_POS))
AnnaBridge 171:3a7713b1edbc 367 #define MXC_F_AFE_INTR_LP_COMP2_NMI_PMU_POS 14
AnnaBridge 171:3a7713b1edbc 368 #define MXC_F_AFE_INTR_LP_COMP2_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_NMI_PMU_POS))
AnnaBridge 171:3a7713b1edbc 369 #define MXC_F_AFE_INTR_LP_COMP3_NMI_PMU_POS 15
AnnaBridge 171:3a7713b1edbc 370 #define MXC_F_AFE_INTR_LP_COMP3_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_NMI_PMU_POS))
AnnaBridge 171:3a7713b1edbc 371 #define MXC_F_AFE_INTR_OP_COMP0_POL_POS 16
AnnaBridge 171:3a7713b1edbc 372 #define MXC_F_AFE_INTR_OP_COMP0_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_POL_POS))
AnnaBridge 171:3a7713b1edbc 373 #define MXC_F_AFE_INTR_OP_COMP1_POL_POS 17
AnnaBridge 171:3a7713b1edbc 374 #define MXC_F_AFE_INTR_OP_COMP1_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_POL_POS))
AnnaBridge 171:3a7713b1edbc 375 #define MXC_F_AFE_INTR_OP_COMP2_POL_POS 18
AnnaBridge 171:3a7713b1edbc 376 #define MXC_F_AFE_INTR_OP_COMP2_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_POL_POS))
AnnaBridge 171:3a7713b1edbc 377 #define MXC_F_AFE_INTR_OP_COMP3_POL_POS 19
AnnaBridge 171:3a7713b1edbc 378 #define MXC_F_AFE_INTR_OP_COMP3_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_POL_POS))
AnnaBridge 171:3a7713b1edbc 379 #define MXC_F_AFE_INTR_LP_COMP0_POL_POS 20
AnnaBridge 171:3a7713b1edbc 380 #define MXC_F_AFE_INTR_LP_COMP0_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_POL_POS))
AnnaBridge 171:3a7713b1edbc 381 #define MXC_F_AFE_INTR_LP_COMP1_POL_POS 21
AnnaBridge 171:3a7713b1edbc 382 #define MXC_F_AFE_INTR_LP_COMP1_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_POL_POS))
AnnaBridge 171:3a7713b1edbc 383 #define MXC_F_AFE_INTR_LP_COMP2_POL_POS 22
AnnaBridge 171:3a7713b1edbc 384 #define MXC_F_AFE_INTR_LP_COMP2_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_POL_POS))
AnnaBridge 171:3a7713b1edbc 385 #define MXC_F_AFE_INTR_LP_COMP3_POL_POS 23
AnnaBridge 171:3a7713b1edbc 386 #define MXC_F_AFE_INTR_LP_COMP3_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_POL_POS))
AnnaBridge 171:3a7713b1edbc 387 #define MXC_F_AFE_INTR_OP_COMP0_IE_POS 24
AnnaBridge 171:3a7713b1edbc 388 #define MXC_F_AFE_INTR_OP_COMP0_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_IE_POS))
AnnaBridge 171:3a7713b1edbc 389 #define MXC_F_AFE_INTR_OP_COMP1_IE_POS 25
AnnaBridge 171:3a7713b1edbc 390 #define MXC_F_AFE_INTR_OP_COMP1_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_IE_POS))
AnnaBridge 171:3a7713b1edbc 391 #define MXC_F_AFE_INTR_OP_COMP2_IE_POS 26
AnnaBridge 171:3a7713b1edbc 392 #define MXC_F_AFE_INTR_OP_COMP2_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_IE_POS))
AnnaBridge 171:3a7713b1edbc 393 #define MXC_F_AFE_INTR_OP_COMP3_IE_POS 27
AnnaBridge 171:3a7713b1edbc 394 #define MXC_F_AFE_INTR_OP_COMP3_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_IE_POS))
AnnaBridge 171:3a7713b1edbc 395 #define MXC_F_AFE_INTR_LP_COMP0_IE_POS 28
AnnaBridge 171:3a7713b1edbc 396 #define MXC_F_AFE_INTR_LP_COMP0_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_IE_POS))
AnnaBridge 171:3a7713b1edbc 397 #define MXC_F_AFE_INTR_LP_COMP1_IE_POS 29
AnnaBridge 171:3a7713b1edbc 398 #define MXC_F_AFE_INTR_LP_COMP1_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_IE_POS))
AnnaBridge 171:3a7713b1edbc 399 #define MXC_F_AFE_INTR_LP_COMP2_IE_POS 30
AnnaBridge 171:3a7713b1edbc 400 #define MXC_F_AFE_INTR_LP_COMP2_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_IE_POS))
AnnaBridge 171:3a7713b1edbc 401 #define MXC_F_AFE_INTR_LP_COMP3_IE_POS 31
AnnaBridge 171:3a7713b1edbc 402 #define MXC_F_AFE_INTR_LP_COMP3_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_IE_POS))
AnnaBridge 171:3a7713b1edbc 403
AnnaBridge 171:3a7713b1edbc 404 #define MXC_F_AFE_CTRL0_LED_CFG_POS 0
AnnaBridge 171:3a7713b1edbc 405 #define MXC_F_AFE_CTRL0_LED_CFG ((uint32_t)(0x0000000FUL << MXC_F_AFE_CTRL0_LED_CFG_POS))
AnnaBridge 171:3a7713b1edbc 406 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0_POS 4
AnnaBridge 171:3a7713b1edbc 407 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0_POS))
AnnaBridge 171:3a7713b1edbc 408 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1_POS 5
AnnaBridge 171:3a7713b1edbc 409 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1_POS))
AnnaBridge 171:3a7713b1edbc 410 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2_POS 6
AnnaBridge 171:3a7713b1edbc 411 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2_POS))
AnnaBridge 171:3a7713b1edbc 412 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3_POS 7
AnnaBridge 171:3a7713b1edbc 413 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3_POS))
AnnaBridge 171:3a7713b1edbc 414 #define MXC_F_AFE_CTRL0_EN_WUD_COMP0_POS 8
AnnaBridge 171:3a7713b1edbc 415 #define MXC_F_AFE_CTRL0_EN_WUD_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP0_POS))
AnnaBridge 171:3a7713b1edbc 416 #define MXC_F_AFE_CTRL0_EN_WUD_COMP1_POS 10
AnnaBridge 171:3a7713b1edbc 417 #define MXC_F_AFE_CTRL0_EN_WUD_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP1_POS))
AnnaBridge 171:3a7713b1edbc 418 #define MXC_F_AFE_CTRL0_EN_WUD_COMP2_POS 12
AnnaBridge 171:3a7713b1edbc 419 #define MXC_F_AFE_CTRL0_EN_WUD_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP2_POS))
AnnaBridge 171:3a7713b1edbc 420 #define MXC_F_AFE_CTRL0_EN_WUD_COMP3_POS 14
AnnaBridge 171:3a7713b1edbc 421 #define MXC_F_AFE_CTRL0_EN_WUD_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP3_POS))
AnnaBridge 171:3a7713b1edbc 422 #define MXC_F_AFE_CTRL0_IN_MODE_COMP0_POS 16
AnnaBridge 171:3a7713b1edbc 423 #define MXC_F_AFE_CTRL0_IN_MODE_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP0_POS))
AnnaBridge 171:3a7713b1edbc 424 #define MXC_F_AFE_CTRL0_IN_MODE_COMP1_POS 18
AnnaBridge 171:3a7713b1edbc 425 #define MXC_F_AFE_CTRL0_IN_MODE_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP1_POS))
AnnaBridge 171:3a7713b1edbc 426 #define MXC_F_AFE_CTRL0_IN_MODE_COMP2_POS 20
AnnaBridge 171:3a7713b1edbc 427 #define MXC_F_AFE_CTRL0_IN_MODE_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP2_POS))
AnnaBridge 171:3a7713b1edbc 428 #define MXC_F_AFE_CTRL0_IN_MODE_COMP3_POS 22
AnnaBridge 171:3a7713b1edbc 429 #define MXC_F_AFE_CTRL0_IN_MODE_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP3_POS))
AnnaBridge 171:3a7713b1edbc 430 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP0_POS 24
AnnaBridge 171:3a7713b1edbc 431 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP0_POS))
AnnaBridge 171:3a7713b1edbc 432 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP1_POS 26
AnnaBridge 171:3a7713b1edbc 433 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP1_POS))
AnnaBridge 171:3a7713b1edbc 434 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP2_POS 28
AnnaBridge 171:3a7713b1edbc 435 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP2_POS))
AnnaBridge 171:3a7713b1edbc 436 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP3_POS 30
AnnaBridge 171:3a7713b1edbc 437 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP3_POS))
AnnaBridge 171:3a7713b1edbc 438
AnnaBridge 171:3a7713b1edbc 439 #define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN_POS 0
AnnaBridge 171:3a7713b1edbc 440 #define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN_POS))
AnnaBridge 171:3a7713b1edbc 441 #define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL_POS 1
AnnaBridge 171:3a7713b1edbc 442 #define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL_POS))
AnnaBridge 171:3a7713b1edbc 443 #define MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN_POS 3
AnnaBridge 171:3a7713b1edbc 444 #define MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN_POS))
AnnaBridge 171:3a7713b1edbc 445 #define MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN_POS 4
AnnaBridge 171:3a7713b1edbc 446 #define MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN_POS))
AnnaBridge 171:3a7713b1edbc 447 #define MXC_F_AFE_CTRL1_REF_BANDGAP_SEL_POS 5
AnnaBridge 171:3a7713b1edbc 448 #define MXC_F_AFE_CTRL1_REF_BANDGAP_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_BANDGAP_SEL_POS))
AnnaBridge 171:3a7713b1edbc 449 #define MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS 6
AnnaBridge 171:3a7713b1edbc 450 #define MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS))
AnnaBridge 171:3a7713b1edbc 451 #define MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL_POS 8
AnnaBridge 171:3a7713b1edbc 452 #define MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL_POS))
AnnaBridge 171:3a7713b1edbc 453 #define MXC_F_AFE_CTRL1_REF_SEL_POS 10
AnnaBridge 171:3a7713b1edbc 454 #define MXC_F_AFE_CTRL1_REF_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_SEL_POS))
AnnaBridge 171:3a7713b1edbc 455 #define MXC_F_AFE_CTRL1_REF_ADC_POWERUP_POS 11
AnnaBridge 171:3a7713b1edbc 456 #define MXC_F_AFE_CTRL1_REF_ADC_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_POWERUP_POS))
AnnaBridge 171:3a7713b1edbc 457 #define MXC_F_AFE_CTRL1_REF_DAC_POWERUP_POS 12
AnnaBridge 171:3a7713b1edbc 458 #define MXC_F_AFE_CTRL1_REF_DAC_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_POWERUP_POS))
AnnaBridge 171:3a7713b1edbc 459 #define MXC_F_AFE_CTRL1_REF_BLK_POWERUP_POS 13
AnnaBridge 171:3a7713b1edbc 460 #define MXC_F_AFE_CTRL1_REF_BLK_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_BLK_POWERUP_POS))
AnnaBridge 171:3a7713b1edbc 461 #define MXC_F_AFE_CTRL1_REF_ADC_COMP_POS 14
AnnaBridge 171:3a7713b1edbc 462 #define MXC_F_AFE_CTRL1_REF_ADC_COMP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_COMP_POS))
AnnaBridge 171:3a7713b1edbc 463 #define MXC_F_AFE_CTRL1_REF_DAC_COMP_POS 15
AnnaBridge 171:3a7713b1edbc 464 #define MXC_F_AFE_CTRL1_REF_DAC_COMP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_COMP_POS))
AnnaBridge 171:3a7713b1edbc 465 #define MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN_POS 16
AnnaBridge 171:3a7713b1edbc 466 #define MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN_POS))
AnnaBridge 171:3a7713b1edbc 467 #define MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN_POS 18
AnnaBridge 171:3a7713b1edbc 468 #define MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN_POS))
AnnaBridge 171:3a7713b1edbc 469 #define MXC_F_AFE_CTRL1_ABUS_PAGE_2_0_POS 20
AnnaBridge 171:3a7713b1edbc 470 #define MXC_F_AFE_CTRL1_ABUS_PAGE_2_0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL1_ABUS_PAGE_2_0_POS))
AnnaBridge 171:3a7713b1edbc 471 #define MXC_F_AFE_CTRL1_PLL_TST_EN_POS 23
AnnaBridge 171:3a7713b1edbc 472 #define MXC_F_AFE_CTRL1_PLL_TST_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_PLL_TST_EN_POS))
AnnaBridge 171:3a7713b1edbc 473 #define MXC_F_AFE_CTRL1_V1EXTADJ_POS 25
AnnaBridge 171:3a7713b1edbc 474 #define MXC_F_AFE_CTRL1_V1EXTADJ ((uint32_t)(0x0000001FUL << MXC_F_AFE_CTRL1_V1EXTADJ_POS))
AnnaBridge 171:3a7713b1edbc 475 #define MXC_F_AFE_CTRL1_TMON_CUR_SEL_POS 30
AnnaBridge 171:3a7713b1edbc 476 #define MXC_F_AFE_CTRL1_TMON_CUR_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_TMON_CUR_SEL_POS))
AnnaBridge 171:3a7713b1edbc 477
AnnaBridge 171:3a7713b1edbc 478 #define MXC_F_AFE_CTRL2_HYST_COMP0_POS 0
AnnaBridge 171:3a7713b1edbc 479 #define MXC_F_AFE_CTRL2_HYST_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP0_POS))
AnnaBridge 171:3a7713b1edbc 480 #define MXC_F_AFE_CTRL2_HYST_COMP1_POS 2
AnnaBridge 171:3a7713b1edbc 481 #define MXC_F_AFE_CTRL2_HYST_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP1_POS))
AnnaBridge 171:3a7713b1edbc 482 #define MXC_F_AFE_CTRL2_HYST_COMP2_POS 4
AnnaBridge 171:3a7713b1edbc 483 #define MXC_F_AFE_CTRL2_HYST_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP2_POS))
AnnaBridge 171:3a7713b1edbc 484 #define MXC_F_AFE_CTRL2_HYST_COMP3_POS 6
AnnaBridge 171:3a7713b1edbc 485 #define MXC_F_AFE_CTRL2_HYST_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP3_POS))
AnnaBridge 171:3a7713b1edbc 486 #define MXC_F_AFE_CTRL2_HY_POL_COMP0_POS 8
AnnaBridge 171:3a7713b1edbc 487 #define MXC_F_AFE_CTRL2_HY_POL_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP0_POS))
AnnaBridge 171:3a7713b1edbc 488 #define MXC_F_AFE_CTRL2_HY_POL_COMP1_POS 9
AnnaBridge 171:3a7713b1edbc 489 #define MXC_F_AFE_CTRL2_HY_POL_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP1_POS))
AnnaBridge 171:3a7713b1edbc 490 #define MXC_F_AFE_CTRL2_HY_POL_COMP2_POS 10
AnnaBridge 171:3a7713b1edbc 491 #define MXC_F_AFE_CTRL2_HY_POL_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP2_POS))
AnnaBridge 171:3a7713b1edbc 492 #define MXC_F_AFE_CTRL2_HY_POL_COMP3_POS 11
AnnaBridge 171:3a7713b1edbc 493 #define MXC_F_AFE_CTRL2_HY_POL_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP3_POS))
AnnaBridge 171:3a7713b1edbc 494 #define MXC_F_AFE_CTRL2_POWERUP_COMP0_POS 12
AnnaBridge 171:3a7713b1edbc 495 #define MXC_F_AFE_CTRL2_POWERUP_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP0_POS))
AnnaBridge 171:3a7713b1edbc 496 #define MXC_F_AFE_CTRL2_POWERUP_COMP1_POS 13
AnnaBridge 171:3a7713b1edbc 497 #define MXC_F_AFE_CTRL2_POWERUP_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP1_POS))
AnnaBridge 171:3a7713b1edbc 498 #define MXC_F_AFE_CTRL2_POWERUP_COMP2_POS 14
AnnaBridge 171:3a7713b1edbc 499 #define MXC_F_AFE_CTRL2_POWERUP_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP2_POS))
AnnaBridge 171:3a7713b1edbc 500 #define MXC_F_AFE_CTRL2_POWERUP_COMP3_POS 15
AnnaBridge 171:3a7713b1edbc 501 #define MXC_F_AFE_CTRL2_POWERUP_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP3_POS))
AnnaBridge 171:3a7713b1edbc 502 #define MXC_F_AFE_CTRL2_DACOUT_EN0_POS 16
AnnaBridge 171:3a7713b1edbc 503 #define MXC_F_AFE_CTRL2_DACOUT_EN0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN0_POS))
AnnaBridge 171:3a7713b1edbc 504 #define MXC_F_AFE_CTRL2_DACOUT_EN1_POS 17
AnnaBridge 171:3a7713b1edbc 505 #define MXC_F_AFE_CTRL2_DACOUT_EN1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN1_POS))
AnnaBridge 171:3a7713b1edbc 506 #define MXC_F_AFE_CTRL2_DACOUT_EN2_POS 18
AnnaBridge 171:3a7713b1edbc 507 #define MXC_F_AFE_CTRL2_DACOUT_EN2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN2_POS))
AnnaBridge 171:3a7713b1edbc 508 #define MXC_F_AFE_CTRL2_DACOUT_EN3_POS 19
AnnaBridge 171:3a7713b1edbc 509 #define MXC_F_AFE_CTRL2_DACOUT_EN3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN3_POS))
AnnaBridge 171:3a7713b1edbc 510 #define MXC_F_AFE_CTRL2_SCM_OR_SEL_POS 20
AnnaBridge 171:3a7713b1edbc 511 #define MXC_F_AFE_CTRL2_SCM_OR_SEL ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL2_SCM_OR_SEL_POS))
AnnaBridge 171:3a7713b1edbc 512 #define MXC_F_AFE_CTRL2_SNO_OR_SEL_POS 23
AnnaBridge 171:3a7713b1edbc 513 #define MXC_F_AFE_CTRL2_SNO_OR_SEL ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL2_SNO_OR_SEL_POS))
AnnaBridge 171:3a7713b1edbc 514 #define MXC_F_AFE_CTRL2_DAC0_SEL_POS 26
AnnaBridge 171:3a7713b1edbc 515 #define MXC_F_AFE_CTRL2_DAC0_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DAC0_SEL_POS))
AnnaBridge 171:3a7713b1edbc 516 #define MXC_F_AFE_CTRL2_DAC1_SEL_POS 27
AnnaBridge 171:3a7713b1edbc 517 #define MXC_F_AFE_CTRL2_DAC1_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DAC1_SEL_POS))
AnnaBridge 171:3a7713b1edbc 518
AnnaBridge 171:3a7713b1edbc 519 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP0_POS 12
AnnaBridge 171:3a7713b1edbc 520 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP0_POS))
AnnaBridge 171:3a7713b1edbc 521 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP1_POS 13
AnnaBridge 171:3a7713b1edbc 522 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP1_POS))
AnnaBridge 171:3a7713b1edbc 523 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP2_POS 14
AnnaBridge 171:3a7713b1edbc 524 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP2_POS))
AnnaBridge 171:3a7713b1edbc 525 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP3_POS 15
AnnaBridge 171:3a7713b1edbc 526 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP3_POS))
AnnaBridge 171:3a7713b1edbc 527 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP0_POS 16
AnnaBridge 171:3a7713b1edbc 528 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP0_POS))
AnnaBridge 171:3a7713b1edbc 529 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP1_POS 17
AnnaBridge 171:3a7713b1edbc 530 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP1_POS))
AnnaBridge 171:3a7713b1edbc 531 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP2_POS 18
AnnaBridge 171:3a7713b1edbc 532 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP2_POS))
AnnaBridge 171:3a7713b1edbc 533 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP3_POS 19
AnnaBridge 171:3a7713b1edbc 534 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP3_POS))
AnnaBridge 171:3a7713b1edbc 535 #define MXC_F_AFE_CTRL3_CLOSE_SPST0_POS 20
AnnaBridge 171:3a7713b1edbc 536 #define MXC_F_AFE_CTRL3_CLOSE_SPST0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST0_POS))
AnnaBridge 171:3a7713b1edbc 537 #define MXC_F_AFE_CTRL3_CLOSE_SPST1_POS 21
AnnaBridge 171:3a7713b1edbc 538 #define MXC_F_AFE_CTRL3_CLOSE_SPST1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST1_POS))
AnnaBridge 171:3a7713b1edbc 539 #define MXC_F_AFE_CTRL3_CLOSE_SPST2_POS 22
AnnaBridge 171:3a7713b1edbc 540 #define MXC_F_AFE_CTRL3_CLOSE_SPST2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST2_POS))
AnnaBridge 171:3a7713b1edbc 541 #define MXC_F_AFE_CTRL3_CLOSE_SPST3_POS 23
AnnaBridge 171:3a7713b1edbc 542 #define MXC_F_AFE_CTRL3_CLOSE_SPST3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST3_POS))
AnnaBridge 171:3a7713b1edbc 543 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP0_POS 24
AnnaBridge 171:3a7713b1edbc 544 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP0_POS))
AnnaBridge 171:3a7713b1edbc 545 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP1_POS 25
AnnaBridge 171:3a7713b1edbc 546 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP1_POS))
AnnaBridge 171:3a7713b1edbc 547 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP2_POS 26
AnnaBridge 171:3a7713b1edbc 548 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP2_POS))
AnnaBridge 171:3a7713b1edbc 549 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP3_POS 27
AnnaBridge 171:3a7713b1edbc 550 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP3_POS))
AnnaBridge 171:3a7713b1edbc 551 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP0_POS 28
AnnaBridge 171:3a7713b1edbc 552 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP0_POS))
AnnaBridge 171:3a7713b1edbc 553 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP1_POS 29
AnnaBridge 171:3a7713b1edbc 554 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP1_POS))
AnnaBridge 171:3a7713b1edbc 555 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP2_POS 30
AnnaBridge 171:3a7713b1edbc 556 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP2_POS))
AnnaBridge 171:3a7713b1edbc 557 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP3_POS 31
AnnaBridge 171:3a7713b1edbc 558 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP3_POS))
AnnaBridge 171:3a7713b1edbc 559
AnnaBridge 171:3a7713b1edbc 560 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS 0
AnnaBridge 171:3a7713b1edbc 561 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS))
AnnaBridge 171:3a7713b1edbc 562 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS 2
AnnaBridge 171:3a7713b1edbc 563 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS))
AnnaBridge 171:3a7713b1edbc 564 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS 4
AnnaBridge 171:3a7713b1edbc 565 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS))
AnnaBridge 171:3a7713b1edbc 566 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS 6
AnnaBridge 171:3a7713b1edbc 567 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS))
AnnaBridge 171:3a7713b1edbc 568 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS 8
AnnaBridge 171:3a7713b1edbc 569 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS))
AnnaBridge 171:3a7713b1edbc 570 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS 10
AnnaBridge 171:3a7713b1edbc 571 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS))
AnnaBridge 171:3a7713b1edbc 572 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS 12
AnnaBridge 171:3a7713b1edbc 573 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS))
AnnaBridge 171:3a7713b1edbc 574 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS 14
AnnaBridge 171:3a7713b1edbc 575 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS))
AnnaBridge 171:3a7713b1edbc 576 #define MXC_F_AFE_CTRL4_DAC_SEL_A_POS 16
AnnaBridge 171:3a7713b1edbc 577 #define MXC_F_AFE_CTRL4_DAC_SEL_A ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_A_POS))
AnnaBridge 171:3a7713b1edbc 578 #define MXC_F_AFE_CTRL4_DAC_SEL_B_POS 18
AnnaBridge 171:3a7713b1edbc 579 #define MXC_F_AFE_CTRL4_DAC_SEL_B ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_B_POS))
AnnaBridge 171:3a7713b1edbc 580 #define MXC_F_AFE_CTRL4_DAC_SEL_C_POS 20
AnnaBridge 171:3a7713b1edbc 581 #define MXC_F_AFE_CTRL4_DAC_SEL_C ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_C_POS))
AnnaBridge 171:3a7713b1edbc 582 #define MXC_F_AFE_CTRL4_DAC_SEL_D_POS 22
AnnaBridge 171:3a7713b1edbc 583 #define MXC_F_AFE_CTRL4_DAC_SEL_D ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_D_POS))
AnnaBridge 171:3a7713b1edbc 584 #define MXC_F_AFE_CTRL4_NPAD_SEL_A_POS 24
AnnaBridge 171:3a7713b1edbc 585 #define MXC_F_AFE_CTRL4_NPAD_SEL_A ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_A_POS))
AnnaBridge 171:3a7713b1edbc 586 #define MXC_F_AFE_CTRL4_NPAD_SEL_B_POS 26
AnnaBridge 171:3a7713b1edbc 587 #define MXC_F_AFE_CTRL4_NPAD_SEL_B ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_B_POS))
AnnaBridge 171:3a7713b1edbc 588 #define MXC_F_AFE_CTRL4_NPAD_SEL_C_POS 28
AnnaBridge 171:3a7713b1edbc 589 #define MXC_F_AFE_CTRL4_NPAD_SEL_C ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_C_POS))
AnnaBridge 171:3a7713b1edbc 590 #define MXC_F_AFE_CTRL4_NPAD_SEL_D_POS 30
AnnaBridge 171:3a7713b1edbc 591 #define MXC_F_AFE_CTRL4_NPAD_SEL_D ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_D_POS))
AnnaBridge 171:3a7713b1edbc 592
AnnaBridge 171:3a7713b1edbc 593 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0_POS 0
AnnaBridge 171:3a7713b1edbc 594 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0_POS))
AnnaBridge 171:3a7713b1edbc 595 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1_POS 3
AnnaBridge 171:3a7713b1edbc 596 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1_POS))
AnnaBridge 171:3a7713b1edbc 597 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2_POS 6
AnnaBridge 171:3a7713b1edbc 598 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2_POS))
AnnaBridge 171:3a7713b1edbc 599 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3_POS 9
AnnaBridge 171:3a7713b1edbc 600 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3_POS))
AnnaBridge 171:3a7713b1edbc 601 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0_POS 12
AnnaBridge 171:3a7713b1edbc 602 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0_POS))
AnnaBridge 171:3a7713b1edbc 603 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1_POS 15
AnnaBridge 171:3a7713b1edbc 604 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1_POS))
AnnaBridge 171:3a7713b1edbc 605 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2_POS 18
AnnaBridge 171:3a7713b1edbc 606 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2_POS))
AnnaBridge 171:3a7713b1edbc 607 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3_POS 21
AnnaBridge 171:3a7713b1edbc 608 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3_POS))
AnnaBridge 171:3a7713b1edbc 609 #define MXC_F_AFE_CTRL5_OP_CMP0_POS 24
AnnaBridge 171:3a7713b1edbc 610 #define MXC_F_AFE_CTRL5_OP_CMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP0_POS))
AnnaBridge 171:3a7713b1edbc 611 #define MXC_F_AFE_CTRL5_OP_CMP1_POS 25
AnnaBridge 171:3a7713b1edbc 612 #define MXC_F_AFE_CTRL5_OP_CMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP1_POS))
AnnaBridge 171:3a7713b1edbc 613 #define MXC_F_AFE_CTRL5_OP_CMP2_POS 26
AnnaBridge 171:3a7713b1edbc 614 #define MXC_F_AFE_CTRL5_OP_CMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP2_POS))
AnnaBridge 171:3a7713b1edbc 615 #define MXC_F_AFE_CTRL5_OP_CMP3_POS 27
AnnaBridge 171:3a7713b1edbc 616 #define MXC_F_AFE_CTRL5_OP_CMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP3_POS))
AnnaBridge 171:3a7713b1edbc 617
AnnaBridge 171:3a7713b1edbc 618 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 619 }
AnnaBridge 171:3a7713b1edbc 620 #endif
AnnaBridge 171:3a7713b1edbc 621
AnnaBridge 171:3a7713b1edbc 622 /**
AnnaBridge 171:3a7713b1edbc 623 * @}
AnnaBridge 171:3a7713b1edbc 624 */
AnnaBridge 171:3a7713b1edbc 625
AnnaBridge 171:3a7713b1edbc 626 #endif /* _MXC_AFE_REGS_H_ */