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TARGET_MAX32600MBED/TOOLCHAIN_ARM_STD/ioman_regs.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /******************************************************************************* |
| AnnaBridge | 171:3a7713b1edbc | 2 | * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. |
| AnnaBridge | 171:3a7713b1edbc | 3 | * |
| AnnaBridge | 171:3a7713b1edbc | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| AnnaBridge | 171:3a7713b1edbc | 5 | * copy of this software and associated documentation files (the "Software"), |
| AnnaBridge | 171:3a7713b1edbc | 6 | * to deal in the Software without restriction, including without limitation |
| AnnaBridge | 171:3a7713b1edbc | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| AnnaBridge | 171:3a7713b1edbc | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| AnnaBridge | 171:3a7713b1edbc | 9 | * Software is furnished to do so, subject to the following conditions: |
| AnnaBridge | 171:3a7713b1edbc | 10 | * |
| AnnaBridge | 171:3a7713b1edbc | 11 | * The above copyright notice and this permission notice shall be included |
| AnnaBridge | 171:3a7713b1edbc | 12 | * in all copies or substantial portions of the Software. |
| AnnaBridge | 171:3a7713b1edbc | 13 | * |
| AnnaBridge | 171:3a7713b1edbc | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| AnnaBridge | 171:3a7713b1edbc | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| AnnaBridge | 171:3a7713b1edbc | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| AnnaBridge | 171:3a7713b1edbc | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| AnnaBridge | 171:3a7713b1edbc | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| AnnaBridge | 171:3a7713b1edbc | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| AnnaBridge | 171:3a7713b1edbc | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * |
| AnnaBridge | 171:3a7713b1edbc | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| AnnaBridge | 171:3a7713b1edbc | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| AnnaBridge | 171:3a7713b1edbc | 24 | * Products, Inc. Branding Policy. |
| AnnaBridge | 171:3a7713b1edbc | 25 | * |
| AnnaBridge | 171:3a7713b1edbc | 26 | * The mere transfer of this software does not imply any licenses |
| AnnaBridge | 171:3a7713b1edbc | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| AnnaBridge | 171:3a7713b1edbc | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| AnnaBridge | 171:3a7713b1edbc | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| AnnaBridge | 171:3a7713b1edbc | 30 | * ownership rights. |
| AnnaBridge | 171:3a7713b1edbc | 31 | ******************************************************************************* |
| AnnaBridge | 171:3a7713b1edbc | 32 | */ |
| AnnaBridge | 171:3a7713b1edbc | 33 | |
| AnnaBridge | 171:3a7713b1edbc | 34 | #ifndef _MXC_IOMAN_REGS_H_ |
| AnnaBridge | 171:3a7713b1edbc | 35 | #define _MXC_IOMAN_REGS_H_ |
| AnnaBridge | 171:3a7713b1edbc | 36 | |
| AnnaBridge | 171:3a7713b1edbc | 37 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 38 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 39 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 40 | |
| AnnaBridge | 171:3a7713b1edbc | 41 | #include <stdint.h> |
| AnnaBridge | 171:3a7713b1edbc | 42 | |
| AnnaBridge | 171:3a7713b1edbc | 43 | /** |
| AnnaBridge | 171:3a7713b1edbc | 44 | * @file ioman_regs.h |
| AnnaBridge | 171:3a7713b1edbc | 45 | * @addtogroup ioman IO MUX Manager |
| AnnaBridge | 171:3a7713b1edbc | 46 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 47 | */ |
| AnnaBridge | 171:3a7713b1edbc | 48 | |
| AnnaBridge | 171:3a7713b1edbc | 49 | typedef enum { |
| AnnaBridge | 171:3a7713b1edbc | 50 | /** Pin Mapping 'A' */ |
| AnnaBridge | 171:3a7713b1edbc | 51 | MXC_E_IOMAN_MAPPING_A = 0, |
| AnnaBridge | 171:3a7713b1edbc | 52 | /** Pin Mapping 'B' */ |
| AnnaBridge | 171:3a7713b1edbc | 53 | MXC_E_IOMAN_MAPPING_B, |
| AnnaBridge | 171:3a7713b1edbc | 54 | /** Pin Mapping 'C' */ |
| AnnaBridge | 171:3a7713b1edbc | 55 | MXC_E_IOMAN_MAPPING_C, |
| AnnaBridge | 171:3a7713b1edbc | 56 | /** Pin Mapping 'D' */ |
| AnnaBridge | 171:3a7713b1edbc | 57 | MXC_E_IOMAN_MAPPING_D, |
| AnnaBridge | 171:3a7713b1edbc | 58 | /** Pin Mapping 'E' */ |
| AnnaBridge | 171:3a7713b1edbc | 59 | MXC_E_IOMAN_MAPPING_E, |
| AnnaBridge | 171:3a7713b1edbc | 60 | /** Pin Mapping 'F' */ |
| AnnaBridge | 171:3a7713b1edbc | 61 | MXC_E_IOMAN_MAPPING_F, |
| AnnaBridge | 171:3a7713b1edbc | 62 | /** Pin Mapping 'G' */ |
| AnnaBridge | 171:3a7713b1edbc | 63 | MXC_E_IOMAN_MAPPING_G, |
| AnnaBridge | 171:3a7713b1edbc | 64 | /** Pin Mapping 'H' */ |
| AnnaBridge | 171:3a7713b1edbc | 65 | MXC_E_IOMAN_MAPPING_H, |
| AnnaBridge | 171:3a7713b1edbc | 66 | } ioman_mapping_t; |
| AnnaBridge | 171:3a7713b1edbc | 67 | |
| AnnaBridge | 171:3a7713b1edbc | 68 | /* Offset Register Description |
| AnnaBridge | 171:3a7713b1edbc | 69 | ====== ========================================== */ |
| AnnaBridge | 171:3a7713b1edbc | 70 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 71 | __IO uint32_t wud_req0; /* 0x0000 Wakeup Detect Mode Request Register 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 72 | __IO uint32_t wud_req1; /* 0x0004 Wakeup Detect Mode Request Register 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 73 | __IO uint32_t wud_ack0; /* 0x0008 Wakeup Detect Mode Acknowledge Register 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 74 | __IO uint32_t wud_ack1; /* 0x000C Wakeup Detect Mode Acknowledge Register 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 75 | __IO uint32_t ali_req0; /* 0x0010 Analog Input Request Register 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 76 | __IO uint32_t ali_req1; /* 0x0014 Analog Input Request Register 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 77 | __IO uint32_t ali_ack0; /* 0x0018 Analog Input Acknowledge Register 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 78 | __IO uint32_t ali_ack1; /* 0x001C Analog Input Acknowledge Register 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 79 | __IO uint32_t spi0_req; /* 0x0020 SPI0 I/O Mode Request */ |
| AnnaBridge | 171:3a7713b1edbc | 80 | __IO uint32_t spi0_ack; /* 0x0024 SPI0 I/O Mode Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 81 | __IO uint32_t spi1_req; /* 0x0028 SPI1 I/O Mode Request */ |
| AnnaBridge | 171:3a7713b1edbc | 82 | __IO uint32_t spi1_ack; /* 0x002C SPI1 I/O Mode Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 83 | __IO uint32_t spi2_req; /* 0x0030 SPI2 I/O Mode Request */ |
| AnnaBridge | 171:3a7713b1edbc | 84 | __IO uint32_t spi2_ack; /* 0x0034 SPI2 I/O Mode Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 85 | __IO uint32_t uart0_req; /* 0x0038 UART0 I/O Mode Request */ |
| AnnaBridge | 171:3a7713b1edbc | 86 | __IO uint32_t uart0_ack; /* 0x003C UART0 I/O Mode Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 87 | __IO uint32_t uart1_req; /* 0x0040 UART1 I/O Mode Request */ |
| AnnaBridge | 171:3a7713b1edbc | 88 | __IO uint32_t uart1_ack; /* 0x0044 UART1 I/O Mode Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 89 | __IO uint32_t i2cm0_req; /* 0x0048 I2C Master 0 I/O Request */ |
| AnnaBridge | 171:3a7713b1edbc | 90 | __IO uint32_t i2cm0_ack; /* 0x004C I2C Master 0 I/O Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 91 | __IO uint32_t i2cs0_req; /* 0x0050 I2C Slave 0 I/O Request */ |
| AnnaBridge | 171:3a7713b1edbc | 92 | __IO uint32_t i2s0_ack; /* 0x0054 I2C Slave 0 I/O Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 93 | __IO uint32_t lcd_com_req; /* 0x0058 LCD COM Driver I/O Request */ |
| AnnaBridge | 171:3a7713b1edbc | 94 | __IO uint32_t lcd_com_ack; /* 0x005C LCD COM Driver I/O Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 95 | __IO uint32_t lcd_seg_req0; /* 0x0060 LCD SEG Driver I/O Request Register 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 96 | __IO uint32_t lcd_seg_req1; /* 0x0064 LCD SEG Driver I/O Request Register 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 97 | __IO uint32_t lcd_seg_ack0; /* 0x0068 LCD SEG Driver I/O Acknowledge Register 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 98 | __IO uint32_t lcd_seg_ack1; /* 0x006C LCD SEG Driver I/O Acknowledge Register 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 99 | __IO uint32_t crnt_req; /* 0x0070 Current Drive I/O Request Register */ |
| AnnaBridge | 171:3a7713b1edbc | 100 | __IO uint32_t io_crnt_ack; /* 0x0074 Current Drive I/O Acknowledge Register */ |
| AnnaBridge | 171:3a7713b1edbc | 101 | __IO uint32_t crnt_mode; /* 0x0078 Current Drive I/O Mode Control */ |
| AnnaBridge | 171:3a7713b1edbc | 102 | __IO uint32_t ali_connect0; /* 0x007C Analog I/O Connection Control Register 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 103 | __IO uint32_t ali_connect1; /* 0x0080 Analog I/O Connection Control Register 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 104 | __IO uint32_t i2cm1_req; /* 0x0084 I2C Master 1 I/O Request */ |
| AnnaBridge | 171:3a7713b1edbc | 105 | __IO uint32_t i2cm1_ack; /* 0x0088 I2C Master 1 I/O Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 106 | __IO uint32_t padx_control; /* 0x008C PADX Control */ |
| AnnaBridge | 171:3a7713b1edbc | 107 | } mxc_ioman_regs_t; |
| AnnaBridge | 171:3a7713b1edbc | 108 | |
| AnnaBridge | 171:3a7713b1edbc | 109 | |
| AnnaBridge | 171:3a7713b1edbc | 110 | /* |
| AnnaBridge | 171:3a7713b1edbc | 111 | Register offsets for module IOMAN. |
| AnnaBridge | 171:3a7713b1edbc | 112 | */ |
| AnnaBridge | 171:3a7713b1edbc | 113 | #define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL) |
| AnnaBridge | 171:3a7713b1edbc | 114 | #define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL) |
| AnnaBridge | 171:3a7713b1edbc | 115 | #define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL) |
| AnnaBridge | 171:3a7713b1edbc | 116 | #define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL) |
| AnnaBridge | 171:3a7713b1edbc | 117 | #define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL) |
| AnnaBridge | 171:3a7713b1edbc | 118 | #define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL) |
| AnnaBridge | 171:3a7713b1edbc | 119 | #define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL) |
| AnnaBridge | 171:3a7713b1edbc | 120 | #define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL) |
| AnnaBridge | 171:3a7713b1edbc | 121 | #define MXC_R_IOMAN_OFFS_SPI0_REQ ((uint32_t)0x00000020UL) |
| AnnaBridge | 171:3a7713b1edbc | 122 | #define MXC_R_IOMAN_OFFS_SPI0_ACK ((uint32_t)0x00000024UL) |
| AnnaBridge | 171:3a7713b1edbc | 123 | #define MXC_R_IOMAN_OFFS_SPI1_REQ ((uint32_t)0x00000028UL) |
| AnnaBridge | 171:3a7713b1edbc | 124 | #define MXC_R_IOMAN_OFFS_SPI1_ACK ((uint32_t)0x0000002CUL) |
| AnnaBridge | 171:3a7713b1edbc | 125 | #define MXC_R_IOMAN_OFFS_SPI2_REQ ((uint32_t)0x00000030UL) |
| AnnaBridge | 171:3a7713b1edbc | 126 | #define MXC_R_IOMAN_OFFS_SPI2_ACK ((uint32_t)0x00000034UL) |
| AnnaBridge | 171:3a7713b1edbc | 127 | #define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000038UL) |
| AnnaBridge | 171:3a7713b1edbc | 128 | #define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x0000003CUL) |
| AnnaBridge | 171:3a7713b1edbc | 129 | #define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000040UL) |
| AnnaBridge | 171:3a7713b1edbc | 130 | #define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x00000044UL) |
| AnnaBridge | 171:3a7713b1edbc | 131 | #define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000048UL) |
| AnnaBridge | 171:3a7713b1edbc | 132 | #define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x0000004CUL) |
| AnnaBridge | 171:3a7713b1edbc | 133 | #define MXC_R_IOMAN_OFFS_I2CS0_REQ ((uint32_t)0x00000050UL) |
| AnnaBridge | 171:3a7713b1edbc | 134 | #define MXC_R_IOMAN_OFFS_I2SC0_ACK ((uint32_t)0x00000054UL) |
| AnnaBridge | 171:3a7713b1edbc | 135 | #define MXC_R_IOMAN_OFFS_LCD_COM_REQ ((uint32_t)0x00000058UL) |
| AnnaBridge | 171:3a7713b1edbc | 136 | #define MXC_R_IOMAN_OFFS_LCD_COM_ACK ((uint32_t)0x0000005CUL) |
| AnnaBridge | 171:3a7713b1edbc | 137 | #define MXC_R_IOMAN_OFFS_LCD_SEG_REQ0 ((uint32_t)0x00000060UL) |
| AnnaBridge | 171:3a7713b1edbc | 138 | #define MXC_R_IOMAN_OFFS_LCD_SEG_REQ1 ((uint32_t)0x00000064UL) |
| AnnaBridge | 171:3a7713b1edbc | 139 | #define MXC_R_IOMAN_OFFS_LCD_SEG_ACK0 ((uint32_t)0x00000068UL) |
| AnnaBridge | 171:3a7713b1edbc | 140 | #define MXC_R_IOMAN_OFFS_LCD_SEG_ACK1 ((uint32_t)0x0000006CUL) |
| AnnaBridge | 171:3a7713b1edbc | 141 | #define MXC_R_IOMAN_OFFS_IO_CRNT_REQ ((uint32_t)0x00000070UL) |
| AnnaBridge | 171:3a7713b1edbc | 142 | #define MXC_R_IOMAN_OFFS_IO_CRNT_ACK ((uint32_t)0x00000074UL) |
| AnnaBridge | 171:3a7713b1edbc | 143 | #define MXC_R_IOMAN_OFFS_IO_CRNT_MODE ((uint32_t)0x00000078UL) |
| AnnaBridge | 171:3a7713b1edbc | 144 | #define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x0000007CUL) |
| AnnaBridge | 171:3a7713b1edbc | 145 | #define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000080UL) |
| AnnaBridge | 171:3a7713b1edbc | 146 | #define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000084UL) |
| AnnaBridge | 171:3a7713b1edbc | 147 | #define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x00000088UL) |
| AnnaBridge | 171:3a7713b1edbc | 148 | #define MXC_R_IOMAN_OFFS_PADX_CONTROL ((uint32_t)0x0000008CUL) |
| AnnaBridge | 171:3a7713b1edbc | 149 | |
| AnnaBridge | 171:3a7713b1edbc | 150 | |
| AnnaBridge | 171:3a7713b1edbc | 151 | /* |
| AnnaBridge | 171:3a7713b1edbc | 152 | Field positions and masks for module IOMAN. |
| AnnaBridge | 171:3a7713b1edbc | 153 | */ |
| AnnaBridge | 171:3a7713b1edbc | 154 | #define MXC_F_IOMAN_WUD_REQ0_PORT0_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 155 | #define MXC_F_IOMAN_WUD_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT0_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 156 | #define MXC_F_IOMAN_WUD_REQ0_PORT1_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 157 | #define MXC_F_IOMAN_WUD_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT1_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 158 | #define MXC_F_IOMAN_WUD_REQ0_PORT2_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 159 | #define MXC_F_IOMAN_WUD_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT2_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 160 | #define MXC_F_IOMAN_WUD_REQ0_PORT3_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 161 | #define MXC_F_IOMAN_WUD_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT3_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 162 | |
| AnnaBridge | 171:3a7713b1edbc | 163 | #define MXC_F_IOMAN_WUD_REQ1_PORT4_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 164 | #define MXC_F_IOMAN_WUD_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT4_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 165 | #define MXC_F_IOMAN_WUD_REQ1_PORT5_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 166 | #define MXC_F_IOMAN_WUD_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT5_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 167 | #define MXC_F_IOMAN_WUD_REQ1_PORT6_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 168 | #define MXC_F_IOMAN_WUD_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT6_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 169 | #define MXC_F_IOMAN_WUD_REQ1_PORT7_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 170 | #define MXC_F_IOMAN_WUD_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT7_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 171 | |
| AnnaBridge | 171:3a7713b1edbc | 172 | #define MXC_F_IOMAN_WUD_ACK0_PORT0_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 173 | #define MXC_F_IOMAN_WUD_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT0_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 174 | #define MXC_F_IOMAN_WUD_ACK0_PORT1_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 175 | #define MXC_F_IOMAN_WUD_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT1_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 176 | #define MXC_F_IOMAN_WUD_ACK0_PORT2_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 177 | #define MXC_F_IOMAN_WUD_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT2_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 178 | #define MXC_F_IOMAN_WUD_ACK0_PORT3_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 179 | #define MXC_F_IOMAN_WUD_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT3_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 180 | |
| AnnaBridge | 171:3a7713b1edbc | 181 | #define MXC_F_IOMAN_WUD_ACK1_PORT4_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 182 | #define MXC_F_IOMAN_WUD_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT4_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 183 | #define MXC_F_IOMAN_WUD_ACK1_PORT5_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 184 | #define MXC_F_IOMAN_WUD_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT5_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 185 | #define MXC_F_IOMAN_WUD_ACK1_PORT6_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 186 | #define MXC_F_IOMAN_WUD_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT6_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 187 | #define MXC_F_IOMAN_WUD_ACK1_PORT7_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 188 | #define MXC_F_IOMAN_WUD_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT7_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 189 | |
| AnnaBridge | 171:3a7713b1edbc | 190 | #define MXC_F_IOMAN_ALI_REQ0_PORT0_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 191 | #define MXC_F_IOMAN_ALI_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT0_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 192 | #define MXC_F_IOMAN_ALI_REQ0_PORT1_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 193 | #define MXC_F_IOMAN_ALI_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT1_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 194 | #define MXC_F_IOMAN_ALI_REQ0_PORT2_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 195 | #define MXC_F_IOMAN_ALI_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT2_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 196 | #define MXC_F_IOMAN_ALI_REQ0_PORT3_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 197 | #define MXC_F_IOMAN_ALI_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT3_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 198 | |
| AnnaBridge | 171:3a7713b1edbc | 199 | #define MXC_F_IOMAN_ALI_REQ1_PORT4_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 200 | #define MXC_F_IOMAN_ALI_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT4_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 201 | #define MXC_F_IOMAN_ALI_REQ1_PORT5_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 202 | #define MXC_F_IOMAN_ALI_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT5_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 203 | #define MXC_F_IOMAN_ALI_REQ1_PORT6_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 204 | #define MXC_F_IOMAN_ALI_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT6_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 205 | #define MXC_F_IOMAN_ALI_REQ1_PORT7_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 206 | #define MXC_F_IOMAN_ALI_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT7_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 207 | |
| AnnaBridge | 171:3a7713b1edbc | 208 | #define MXC_F_IOMAN_ALI_ACK0_PORT0_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 209 | #define MXC_F_IOMAN_ALI_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT0_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 210 | #define MXC_F_IOMAN_ALI_ACK0_PORT1_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 211 | #define MXC_F_IOMAN_ALI_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT1_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 212 | #define MXC_F_IOMAN_ALI_ACK0_PORT2_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 213 | #define MXC_F_IOMAN_ALI_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT2_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 214 | #define MXC_F_IOMAN_ALI_ACK0_PORT3_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 215 | #define MXC_F_IOMAN_ALI_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT3_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 216 | |
| AnnaBridge | 171:3a7713b1edbc | 217 | #define MXC_F_IOMAN_ALI_ACK1_PORT4_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 218 | #define MXC_F_IOMAN_ALI_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT4_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 219 | #define MXC_F_IOMAN_ALI_ACK1_PORT5_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 220 | #define MXC_F_IOMAN_ALI_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT5_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 221 | #define MXC_F_IOMAN_ALI_ACK1_PORT6_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 222 | #define MXC_F_IOMAN_ALI_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT6_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 223 | #define MXC_F_IOMAN_ALI_ACK1_PORT7_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 224 | #define MXC_F_IOMAN_ALI_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT7_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 225 | |
| AnnaBridge | 171:3a7713b1edbc | 226 | #define MXC_F_IOMAN_SPI_MAPPING_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 227 | #define MXC_F_IOMAN_SPI_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPI_MAPPING_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 228 | #define MXC_F_IOMAN_SPI_CORE_IO_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 229 | #define MXC_F_IOMAN_SPI_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_CORE_IO_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 230 | #define MXC_F_IOMAN_SPI_SS0_IO_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 231 | #define MXC_F_IOMAN_SPI_SS0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS0_IO_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 232 | #define MXC_F_IOMAN_SPI_SS1_IO_POS 9 |
| AnnaBridge | 171:3a7713b1edbc | 233 | #define MXC_F_IOMAN_SPI_SS1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS1_IO_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 234 | #define MXC_F_IOMAN_SPI_SS2_IO_POS 10 |
| AnnaBridge | 171:3a7713b1edbc | 235 | #define MXC_F_IOMAN_SPI_SS2_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS2_IO_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 236 | #define MXC_F_IOMAN_SPI_SS3_IO_POS 11 |
| AnnaBridge | 171:3a7713b1edbc | 237 | #define MXC_F_IOMAN_SPI_SS3_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS3_IO_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 238 | #define MXC_F_IOMAN_SPI_SS4_IO_POS 12 |
| AnnaBridge | 171:3a7713b1edbc | 239 | #define MXC_F_IOMAN_SPI_SS4_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS4_IO_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 240 | #define MXC_F_IOMAN_SPI_SR0_IO_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 241 | #define MXC_F_IOMAN_SPI_SR0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR0_IO_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 242 | #define MXC_F_IOMAN_SPI_SR1_IO_POS 17 |
| AnnaBridge | 171:3a7713b1edbc | 243 | #define MXC_F_IOMAN_SPI_SR1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR1_IO_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 244 | #define MXC_F_IOMAN_SPI_QUAD_IO_POS 20 |
| AnnaBridge | 171:3a7713b1edbc | 245 | #define MXC_F_IOMAN_SPI_QUAD_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_QUAD_IO_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 246 | #define MXC_F_IOMAN_SPI_FAST_MODE_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 247 | #define MXC_F_IOMAN_SPI_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_FAST_MODE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 248 | |
| AnnaBridge | 171:3a7713b1edbc | 249 | #define MXC_F_IOMAN_UART_MAPPING_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 250 | #define MXC_F_IOMAN_UART_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_UART_MAPPING_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 251 | #define MXC_F_IOMAN_UART_CORE_IO_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 252 | #define MXC_F_IOMAN_UART_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CORE_IO_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 253 | #define MXC_F_IOMAN_UART_CTS_IO_POS 5 |
| AnnaBridge | 171:3a7713b1edbc | 254 | #define MXC_F_IOMAN_UART_CTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CTS_IO_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 255 | #define MXC_F_IOMAN_UART_RTS_IO_POS 6 |
| AnnaBridge | 171:3a7713b1edbc | 256 | #define MXC_F_IOMAN_UART_RTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_RTS_IO_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 257 | |
| AnnaBridge | 171:3a7713b1edbc | 258 | #define MXC_F_IOMAN_I2CM_MAPPING_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 259 | #define MXC_F_IOMAN_I2CM_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM_MAPPING_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 260 | #define MXC_F_IOMAN_I2CM_CORE_IO_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 261 | #define MXC_F_IOMAN_I2CM_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM_CORE_IO_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 262 | |
| AnnaBridge | 171:3a7713b1edbc | 263 | #define MXC_F_IOMAN_I2CS_MAPPING_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 264 | #define MXC_F_IOMAN_I2CS_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_MAPPING_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 265 | #define MXC_F_IOMAN_I2CS_CORE_IO_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 266 | #define MXC_F_IOMAN_I2CS_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_CORE_IO_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 267 | |
| AnnaBridge | 171:3a7713b1edbc | 268 | #define MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 269 | #define MXC_F_IOMAN_LCD_COM_REQ_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 270 | |
| AnnaBridge | 171:3a7713b1edbc | 271 | #define MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define MXC_F_IOMAN_LCD_COM_ACK_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 273 | |
| AnnaBridge | 171:3a7713b1edbc | 274 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 275 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 276 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 277 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 278 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS 2 |
| AnnaBridge | 171:3a7713b1edbc | 279 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 280 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS 3 |
| AnnaBridge | 171:3a7713b1edbc | 281 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 282 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 283 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 284 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS 5 |
| AnnaBridge | 171:3a7713b1edbc | 285 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 286 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS 6 |
| AnnaBridge | 171:3a7713b1edbc | 287 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 288 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS 7 |
| AnnaBridge | 171:3a7713b1edbc | 289 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 290 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 291 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 292 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS 9 |
| AnnaBridge | 171:3a7713b1edbc | 293 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 294 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS 10 |
| AnnaBridge | 171:3a7713b1edbc | 295 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 296 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS 11 |
| AnnaBridge | 171:3a7713b1edbc | 297 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 298 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS 12 |
| AnnaBridge | 171:3a7713b1edbc | 299 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 300 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS 13 |
| AnnaBridge | 171:3a7713b1edbc | 301 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 302 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS 14 |
| AnnaBridge | 171:3a7713b1edbc | 303 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 304 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS 15 |
| AnnaBridge | 171:3a7713b1edbc | 305 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 306 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 307 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 308 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS 17 |
| AnnaBridge | 171:3a7713b1edbc | 309 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 310 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS 18 |
| AnnaBridge | 171:3a7713b1edbc | 311 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 312 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS 19 |
| AnnaBridge | 171:3a7713b1edbc | 313 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 314 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS 20 |
| AnnaBridge | 171:3a7713b1edbc | 315 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 316 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS 21 |
| AnnaBridge | 171:3a7713b1edbc | 317 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 318 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS 22 |
| AnnaBridge | 171:3a7713b1edbc | 319 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 320 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS 23 |
| AnnaBridge | 171:3a7713b1edbc | 321 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 322 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 323 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 324 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS 25 |
| AnnaBridge | 171:3a7713b1edbc | 325 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 326 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS 26 |
| AnnaBridge | 171:3a7713b1edbc | 327 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 328 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS 27 |
| AnnaBridge | 171:3a7713b1edbc | 329 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 330 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS 28 |
| AnnaBridge | 171:3a7713b1edbc | 331 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 332 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS 29 |
| AnnaBridge | 171:3a7713b1edbc | 333 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 334 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS 30 |
| AnnaBridge | 171:3a7713b1edbc | 335 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 336 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS 31 |
| AnnaBridge | 171:3a7713b1edbc | 337 | #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 338 | |
| AnnaBridge | 171:3a7713b1edbc | 339 | #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 340 | #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 341 | #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 342 | #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 343 | #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS 2 |
| AnnaBridge | 171:3a7713b1edbc | 344 | #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 345 | #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS 3 |
| AnnaBridge | 171:3a7713b1edbc | 346 | #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 347 | #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 348 | #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 349 | #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS 5 |
| AnnaBridge | 171:3a7713b1edbc | 350 | #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 351 | #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS 6 |
| AnnaBridge | 171:3a7713b1edbc | 352 | #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 353 | #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS 7 |
| AnnaBridge | 171:3a7713b1edbc | 354 | #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 355 | |
| AnnaBridge | 171:3a7713b1edbc | 356 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 357 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 358 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 359 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 360 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS 2 |
| AnnaBridge | 171:3a7713b1edbc | 361 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 362 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS 3 |
| AnnaBridge | 171:3a7713b1edbc | 363 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 364 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 365 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 366 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS 5 |
| AnnaBridge | 171:3a7713b1edbc | 367 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 368 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS 6 |
| AnnaBridge | 171:3a7713b1edbc | 369 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 370 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS 7 |
| AnnaBridge | 171:3a7713b1edbc | 371 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 372 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 373 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 374 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS 9 |
| AnnaBridge | 171:3a7713b1edbc | 375 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 376 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS 10 |
| AnnaBridge | 171:3a7713b1edbc | 377 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 378 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS 11 |
| AnnaBridge | 171:3a7713b1edbc | 379 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 380 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS 12 |
| AnnaBridge | 171:3a7713b1edbc | 381 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 382 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS 13 |
| AnnaBridge | 171:3a7713b1edbc | 383 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 384 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS 14 |
| AnnaBridge | 171:3a7713b1edbc | 385 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 386 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS 15 |
| AnnaBridge | 171:3a7713b1edbc | 387 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 388 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 389 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 390 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS 17 |
| AnnaBridge | 171:3a7713b1edbc | 391 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 392 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS 18 |
| AnnaBridge | 171:3a7713b1edbc | 393 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 394 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS 19 |
| AnnaBridge | 171:3a7713b1edbc | 395 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 396 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS 20 |
| AnnaBridge | 171:3a7713b1edbc | 397 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 398 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS 21 |
| AnnaBridge | 171:3a7713b1edbc | 399 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 400 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS 22 |
| AnnaBridge | 171:3a7713b1edbc | 401 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 402 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS 23 |
| AnnaBridge | 171:3a7713b1edbc | 403 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 404 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 405 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 406 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS 25 |
| AnnaBridge | 171:3a7713b1edbc | 407 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 408 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS 26 |
| AnnaBridge | 171:3a7713b1edbc | 409 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 410 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS 27 |
| AnnaBridge | 171:3a7713b1edbc | 411 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 412 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS 28 |
| AnnaBridge | 171:3a7713b1edbc | 413 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 414 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS 29 |
| AnnaBridge | 171:3a7713b1edbc | 415 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 416 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS 30 |
| AnnaBridge | 171:3a7713b1edbc | 417 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 418 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS 31 |
| AnnaBridge | 171:3a7713b1edbc | 419 | #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 420 | |
| AnnaBridge | 171:3a7713b1edbc | 421 | #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 422 | #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 423 | #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 424 | #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 425 | #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS 2 |
| AnnaBridge | 171:3a7713b1edbc | 426 | #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 427 | #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS 3 |
| AnnaBridge | 171:3a7713b1edbc | 428 | #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 429 | #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 430 | #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 431 | #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS 5 |
| AnnaBridge | 171:3a7713b1edbc | 432 | #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 433 | #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS 6 |
| AnnaBridge | 171:3a7713b1edbc | 434 | #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 435 | #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS 7 |
| AnnaBridge | 171:3a7713b1edbc | 436 | #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 437 | |
| AnnaBridge | 171:3a7713b1edbc | 438 | #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 439 | #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 440 | #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 441 | #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 442 | #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS 2 |
| AnnaBridge | 171:3a7713b1edbc | 443 | #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 444 | #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS 3 |
| AnnaBridge | 171:3a7713b1edbc | 445 | #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 446 | #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 447 | #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 448 | #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS 5 |
| AnnaBridge | 171:3a7713b1edbc | 449 | #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 450 | #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS 6 |
| AnnaBridge | 171:3a7713b1edbc | 451 | #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 452 | #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS 7 |
| AnnaBridge | 171:3a7713b1edbc | 453 | #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 454 | |
| AnnaBridge | 171:3a7713b1edbc | 455 | #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 456 | #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 457 | #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 458 | #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 459 | #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS 2 |
| AnnaBridge | 171:3a7713b1edbc | 460 | #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 461 | #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS 3 |
| AnnaBridge | 171:3a7713b1edbc | 462 | #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 463 | #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 464 | #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 465 | #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS 5 |
| AnnaBridge | 171:3a7713b1edbc | 466 | #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 467 | #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS 6 |
| AnnaBridge | 171:3a7713b1edbc | 468 | #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 469 | #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS 7 |
| AnnaBridge | 171:3a7713b1edbc | 470 | #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 471 | |
| AnnaBridge | 171:3a7713b1edbc | 472 | #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 473 | #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 474 | #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 475 | #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 476 | #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 477 | #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 478 | #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS 12 |
| AnnaBridge | 171:3a7713b1edbc | 479 | #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 480 | #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 481 | #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 482 | #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS 20 |
| AnnaBridge | 171:3a7713b1edbc | 483 | #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 484 | #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 485 | #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 486 | #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS 28 |
| AnnaBridge | 171:3a7713b1edbc | 487 | #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 488 | |
| AnnaBridge | 171:3a7713b1edbc | 489 | #define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 490 | #define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 491 | #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 492 | #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 493 | #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS 6 |
| AnnaBridge | 171:3a7713b1edbc | 494 | #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 495 | #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 496 | #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 497 | #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS 10 |
| AnnaBridge | 171:3a7713b1edbc | 498 | #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 499 | |
| AnnaBridge | 171:3a7713b1edbc | 500 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 501 | } |
| AnnaBridge | 171:3a7713b1edbc | 502 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 503 | |
| AnnaBridge | 171:3a7713b1edbc | 504 | /** |
| AnnaBridge | 171:3a7713b1edbc | 505 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 506 | */ |
| AnnaBridge | 171:3a7713b1edbc | 507 | |
| AnnaBridge | 171:3a7713b1edbc | 508 | #endif /* _MXC_IOMAN_REGS_H_ */ |
