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TARGET_LPC1768/TOOLCHAIN_IAR/cmsis_gcc.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/************************************************************************//
AnnaBridge	171:3a7713b1edbc	2	* @file cmsis_gcc.h
AnnaBridge	171:3a7713b1edbc	3	* @brief CMSIS compiler GCC header file
AnnaBridge	171:3a7713b1edbc	4	* @version V5.0.4
AnnaBridge	171:3a7713b1edbc	5	* @date 09. April 2018
AnnaBridge	171:3a7713b1edbc	6	******************************************************************************/
AnnaBridge	171:3a7713b1edbc	7	/*
AnnaBridge	171:3a7713b1edbc	8	* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
AnnaBridge	171:3a7713b1edbc	9	*
AnnaBridge	171:3a7713b1edbc	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	171:3a7713b1edbc	11	*
AnnaBridge	171:3a7713b1edbc	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	171:3a7713b1edbc	13	* not use this file except in compliance with the License.
AnnaBridge	171:3a7713b1edbc	14	* You may obtain a copy of the License at
AnnaBridge	171:3a7713b1edbc	15	*
AnnaBridge	171:3a7713b1edbc	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	171:3a7713b1edbc	17	*
AnnaBridge	171:3a7713b1edbc	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	171:3a7713b1edbc	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	171:3a7713b1edbc	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	171:3a7713b1edbc	21	* See the License for the specific language governing permissions and
AnnaBridge	171:3a7713b1edbc	22	* limitations under the License.
AnnaBridge	171:3a7713b1edbc	23	*/
AnnaBridge	171:3a7713b1edbc	24
AnnaBridge	171:3a7713b1edbc	25	#ifndef __CMSIS_GCC_H
AnnaBridge	171:3a7713b1edbc	26	#define __CMSIS_GCC_H
AnnaBridge	171:3a7713b1edbc	27
AnnaBridge	171:3a7713b1edbc	28	/* ignore some GCC warnings */
AnnaBridge	171:3a7713b1edbc	29	#pragma GCC diagnostic push
AnnaBridge	171:3a7713b1edbc	30	#pragma GCC diagnostic ignored "-Wsign-conversion"
AnnaBridge	171:3a7713b1edbc	31	#pragma GCC diagnostic ignored "-Wconversion"
AnnaBridge	171:3a7713b1edbc	32	#pragma GCC diagnostic ignored "-Wunused-parameter"
AnnaBridge	171:3a7713b1edbc	33
AnnaBridge	171:3a7713b1edbc	34	/* Fallback for __has_builtin */
AnnaBridge	171:3a7713b1edbc	35	#ifndef __has_builtin
AnnaBridge	171:3a7713b1edbc	36	#define __has_builtin(x) (0)
AnnaBridge	171:3a7713b1edbc	37	#endif
AnnaBridge	171:3a7713b1edbc	38
AnnaBridge	171:3a7713b1edbc	39	/* CMSIS compiler specific defines */
AnnaBridge	171:3a7713b1edbc	40	#ifndef __ASM
AnnaBridge	171:3a7713b1edbc	41	#define __ASM __asm
AnnaBridge	171:3a7713b1edbc	42	#endif
AnnaBridge	171:3a7713b1edbc	43	#ifndef __INLINE
AnnaBridge	171:3a7713b1edbc	44	#define __INLINE inline
AnnaBridge	171:3a7713b1edbc	45	#endif
AnnaBridge	171:3a7713b1edbc	46	#ifndef __STATIC_INLINE
AnnaBridge	171:3a7713b1edbc	47	#define __STATIC_INLINE static inline
AnnaBridge	171:3a7713b1edbc	48	#endif
AnnaBridge	171:3a7713b1edbc	49	#ifndef __STATIC_FORCEINLINE
AnnaBridge	171:3a7713b1edbc	50	#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
AnnaBridge	171:3a7713b1edbc	51	#endif
AnnaBridge	171:3a7713b1edbc	52	#ifndef __NO_RETURN
AnnaBridge	171:3a7713b1edbc	53	#define __NO_RETURN __attribute__((__noreturn__))
AnnaBridge	171:3a7713b1edbc	54	#endif
AnnaBridge	171:3a7713b1edbc	55	#ifndef __USED
AnnaBridge	171:3a7713b1edbc	56	#define __USED __attribute__((used))
AnnaBridge	171:3a7713b1edbc	57	#endif
AnnaBridge	171:3a7713b1edbc	58	#ifndef __WEAK
AnnaBridge	171:3a7713b1edbc	59	#define __WEAK __attribute__((weak))
AnnaBridge	171:3a7713b1edbc	60	#endif
AnnaBridge	171:3a7713b1edbc	61	#ifndef __PACKED
AnnaBridge	171:3a7713b1edbc	62	#define __PACKED __attribute__((packed, aligned(1)))
AnnaBridge	171:3a7713b1edbc	63	#endif
AnnaBridge	171:3a7713b1edbc	64	#ifndef __PACKED_STRUCT
AnnaBridge	171:3a7713b1edbc	65	#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
AnnaBridge	171:3a7713b1edbc	66	#endif
AnnaBridge	171:3a7713b1edbc	67	#ifndef __PACKED_UNION
AnnaBridge	171:3a7713b1edbc	68	#define __PACKED_UNION union __attribute__((packed, aligned(1)))
AnnaBridge	171:3a7713b1edbc	69	#endif
AnnaBridge	171:3a7713b1edbc	70	#ifndef __UNALIGNED_UINT32 /* deprecated */
AnnaBridge	171:3a7713b1edbc	71	#pragma GCC diagnostic push
AnnaBridge	171:3a7713b1edbc	72	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	171:3a7713b1edbc	73	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	171:3a7713b1edbc	74	struct __attribute__((packed)) T_UINT32 { uint32_t v; };
AnnaBridge	171:3a7713b1edbc	75	#pragma GCC diagnostic pop
AnnaBridge	171:3a7713b1edbc	76	#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
AnnaBridge	171:3a7713b1edbc	77	#endif
AnnaBridge	171:3a7713b1edbc	78	#ifndef __UNALIGNED_UINT16_WRITE
AnnaBridge	171:3a7713b1edbc	79	#pragma GCC diagnostic push
AnnaBridge	171:3a7713b1edbc	80	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	171:3a7713b1edbc	81	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	171:3a7713b1edbc	82	__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
AnnaBridge	171:3a7713b1edbc	83	#pragma GCC diagnostic pop
AnnaBridge	171:3a7713b1edbc	84	#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE )(void )(addr))->v) = (val))
AnnaBridge	171:3a7713b1edbc	85	#endif
AnnaBridge	171:3a7713b1edbc	86	#ifndef __UNALIGNED_UINT16_READ
AnnaBridge	171:3a7713b1edbc	87	#pragma GCC diagnostic push
AnnaBridge	171:3a7713b1edbc	88	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	171:3a7713b1edbc	89	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	171:3a7713b1edbc	90	__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
AnnaBridge	171:3a7713b1edbc	91	#pragma GCC diagnostic pop
AnnaBridge	171:3a7713b1edbc	92	#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ )(const void )(addr))->v)
AnnaBridge	171:3a7713b1edbc	93	#endif
AnnaBridge	171:3a7713b1edbc	94	#ifndef __UNALIGNED_UINT32_WRITE
AnnaBridge	171:3a7713b1edbc	95	#pragma GCC diagnostic push
AnnaBridge	171:3a7713b1edbc	96	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	171:3a7713b1edbc	97	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	171:3a7713b1edbc	98	__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
AnnaBridge	171:3a7713b1edbc	99	#pragma GCC diagnostic pop
AnnaBridge	171:3a7713b1edbc	100	#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE )(void )(addr))->v) = (val))
AnnaBridge	171:3a7713b1edbc	101	#endif
AnnaBridge	171:3a7713b1edbc	102	#ifndef __UNALIGNED_UINT32_READ
AnnaBridge	171:3a7713b1edbc	103	#pragma GCC diagnostic push
AnnaBridge	171:3a7713b1edbc	104	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	171:3a7713b1edbc	105	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	171:3a7713b1edbc	106	__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
AnnaBridge	171:3a7713b1edbc	107	#pragma GCC diagnostic pop
AnnaBridge	171:3a7713b1edbc	108	#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ )(const void )(addr))->v)
AnnaBridge	171:3a7713b1edbc	109	#endif
AnnaBridge	171:3a7713b1edbc	110	#ifndef __ALIGNED
AnnaBridge	171:3a7713b1edbc	111	#define __ALIGNED(x) __attribute__((aligned(x)))
AnnaBridge	171:3a7713b1edbc	112	#endif
AnnaBridge	171:3a7713b1edbc	113	#ifndef __RESTRICT
AnnaBridge	171:3a7713b1edbc	114	#define __RESTRICT __restrict
AnnaBridge	171:3a7713b1edbc	115	#endif
AnnaBridge	171:3a7713b1edbc	116
AnnaBridge	171:3a7713b1edbc	117
AnnaBridge	171:3a7713b1edbc	118	/* ########################### Core Function Access ########################### */
AnnaBridge	171:3a7713b1edbc	119	/** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge	171:3a7713b1edbc	120	\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
AnnaBridge	171:3a7713b1edbc	121	@{
AnnaBridge	171:3a7713b1edbc	122	*/
AnnaBridge	171:3a7713b1edbc	123
AnnaBridge	171:3a7713b1edbc	124	/**
AnnaBridge	171:3a7713b1edbc	125	\brief Enable IRQ Interrupts
AnnaBridge	171:3a7713b1edbc	126	\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
AnnaBridge	171:3a7713b1edbc	127	Can only be executed in Privileged modes.
AnnaBridge	171:3a7713b1edbc	128	*/
AnnaBridge	171:3a7713b1edbc	129	__STATIC_FORCEINLINE void __enable_irq(void)
AnnaBridge	171:3a7713b1edbc	130	{
AnnaBridge	171:3a7713b1edbc	131	__ASM volatile ("cpsie i" : : : "memory");
AnnaBridge	171:3a7713b1edbc	132	}
AnnaBridge	171:3a7713b1edbc	133
AnnaBridge	171:3a7713b1edbc	134
AnnaBridge	171:3a7713b1edbc	135	/**
AnnaBridge	171:3a7713b1edbc	136	\brief Disable IRQ Interrupts
AnnaBridge	171:3a7713b1edbc	137	\details Disables IRQ interrupts by setting the I-bit in the CPSR.
AnnaBridge	171:3a7713b1edbc	138	Can only be executed in Privileged modes.
AnnaBridge	171:3a7713b1edbc	139	*/
AnnaBridge	171:3a7713b1edbc	140	__STATIC_FORCEINLINE void __disable_irq(void)
AnnaBridge	171:3a7713b1edbc	141	{
AnnaBridge	171:3a7713b1edbc	142	__ASM volatile ("cpsid i" : : : "memory");
AnnaBridge	171:3a7713b1edbc	143	}
AnnaBridge	171:3a7713b1edbc	144
AnnaBridge	171:3a7713b1edbc	145
AnnaBridge	171:3a7713b1edbc	146	/**
AnnaBridge	171:3a7713b1edbc	147	\brief Get Control Register
AnnaBridge	171:3a7713b1edbc	148	\details Returns the content of the Control Register.
AnnaBridge	171:3a7713b1edbc	149	\return Control Register value
AnnaBridge	171:3a7713b1edbc	150	*/
AnnaBridge	171:3a7713b1edbc	151	__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
AnnaBridge	171:3a7713b1edbc	152	{
AnnaBridge	171:3a7713b1edbc	153	uint32_t result;
AnnaBridge	171:3a7713b1edbc	154
AnnaBridge	171:3a7713b1edbc	155	__ASM volatile ("MRS %0, control" : "=r" (result) );
AnnaBridge	171:3a7713b1edbc	156	return(result);
AnnaBridge	171:3a7713b1edbc	157	}
AnnaBridge	171:3a7713b1edbc	158
AnnaBridge	171:3a7713b1edbc	159
AnnaBridge	171:3a7713b1edbc	160	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	171:3a7713b1edbc	161	/**
AnnaBridge	171:3a7713b1edbc	162	\brief Get Control Register (non-secure)
AnnaBridge	171:3a7713b1edbc	163	\details Returns the content of the non-secure Control Register when in secure mode.
AnnaBridge	171:3a7713b1edbc	164	\return non-secure Control Register value
AnnaBridge	171:3a7713b1edbc	165	*/
AnnaBridge	171:3a7713b1edbc	166	__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
AnnaBridge	171:3a7713b1edbc	167	{
AnnaBridge	171:3a7713b1edbc	168	uint32_t result;
AnnaBridge	171:3a7713b1edbc	169
AnnaBridge	171:3a7713b1edbc	170	__ASM volatile ("MRS %0, control_ns" : "=r" (result) );
AnnaBridge	171:3a7713b1edbc	171	return(result);
AnnaBridge	171:3a7713b1edbc	172	}
AnnaBridge	171:3a7713b1edbc	173	#endif
AnnaBridge	171:3a7713b1edbc	174
AnnaBridge	171:3a7713b1edbc	175
AnnaBridge	171:3a7713b1edbc	176	/**
AnnaBridge	171:3a7713b1edbc	177	\brief Set Control Register
AnnaBridge	171:3a7713b1edbc	178	\details Writes the given value to the Control Register.
AnnaBridge	171:3a7713b1edbc	179	\param [in] control Control Register value to set
AnnaBridge	171:3a7713b1edbc	180	*/
AnnaBridge	171:3a7713b1edbc	181	__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
AnnaBridge	171:3a7713b1edbc	182	{
AnnaBridge	171:3a7713b1edbc	183	__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
AnnaBridge	171:3a7713b1edbc	184	}
AnnaBridge	171:3a7713b1edbc	185
AnnaBridge	171:3a7713b1edbc	186
AnnaBridge	171:3a7713b1edbc	187	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	171:3a7713b1edbc	188	/**
AnnaBridge	171:3a7713b1edbc	189	\brief Set Control Register (non-secure)
AnnaBridge	171:3a7713b1edbc	190	\details Writes the given value to the non-secure Control Register when in secure state.
AnnaBridge	171:3a7713b1edbc	191	\param [in] control Control Register value to set
AnnaBridge	171:3a7713b1edbc	192	*/
AnnaBridge	171:3a7713b1edbc	193	__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
AnnaBridge	171:3a7713b1edbc	194	{
AnnaBridge	171:3a7713b1edbc	195	__ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
AnnaBridge	171:3a7713b1edbc	196	}
AnnaBridge	171:3a7713b1edbc	197	#endif
AnnaBridge	171:3a7713b1edbc	198
AnnaBridge	171:3a7713b1edbc	199
AnnaBridge	171:3a7713b1edbc	200	/**
AnnaBridge	171:3a7713b1edbc	201	\brief Get IPSR Register
AnnaBridge	171:3a7713b1edbc	202	\details Returns the content of the IPSR Register.
AnnaBridge	171:3a7713b1edbc	203	\return IPSR Register value
AnnaBridge	171:3a7713b1edbc	204	*/
AnnaBridge	171:3a7713b1edbc	205	__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
AnnaBridge	171:3a7713b1edbc	206	{
AnnaBridge	171:3a7713b1edbc	207	uint32_t result;
AnnaBridge	171:3a7713b1edbc	208
AnnaBridge	171:3a7713b1edbc	209	__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
AnnaBridge	171:3a7713b1edbc	210	return(result);
AnnaBridge	171:3a7713b1edbc	211	}
AnnaBridge	171:3a7713b1edbc	212
AnnaBridge	171:3a7713b1edbc	213
AnnaBridge	171:3a7713b1edbc	214	/**
AnnaBridge	171:3a7713b1edbc	215	\brief Get APSR Register
AnnaBridge	171:3a7713b1edbc	216	\details Returns the content of the APSR Register.
AnnaBridge	171:3a7713b1edbc	217	\return APSR Register value
AnnaBridge	171:3a7713b1edbc	218	*/
AnnaBridge	171:3a7713b1edbc	219	__STATIC_FORCEINLINE uint32_t __get_APSR(void)
AnnaBridge	171:3a7713b1edbc	220	{
AnnaBridge	171:3a7713b1edbc	221	uint32_t result;
AnnaBridge	171:3a7713b1edbc	222
AnnaBridge	171:3a7713b1edbc	223	__ASM volatile ("MRS %0, apsr" : "=r" (result) );
AnnaBridge	171:3a7713b1edbc	224	return(result);
AnnaBridge	171:3a7713b1edbc	225	}
AnnaBridge	171:3a7713b1edbc	226
AnnaBridge	171:3a7713b1edbc	227
AnnaBridge	171:3a7713b1edbc	228	/**
AnnaBridge	171:3a7713b1edbc	229	\brief Get xPSR Register
AnnaBridge	171:3a7713b1edbc	230	\details Returns the content of the xPSR Register.
AnnaBridge	171:3a7713b1edbc	231	\return xPSR Register value
AnnaBridge	171:3a7713b1edbc	232	*/
AnnaBridge	171:3a7713b1edbc	233	__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
AnnaBridge	171:3a7713b1edbc	234	{
AnnaBridge	171:3a7713b1edbc	235	uint32_t result;
AnnaBridge	171:3a7713b1edbc	236
AnnaBridge	171:3a7713b1edbc	237	__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
AnnaBridge	171:3a7713b1edbc	238	return(result);
AnnaBridge	171:3a7713b1edbc	239	}
AnnaBridge	171:3a7713b1edbc	240
AnnaBridge	171:3a7713b1edbc	241
AnnaBridge	171:3a7713b1edbc	242	/**
AnnaBridge	171:3a7713b1edbc	243	\brief Get Process Stack Pointer
AnnaBridge	171:3a7713b1edbc	244	\details Returns the current value of the Process Stack Pointer (PSP).
AnnaBridge	171:3a7713b1edbc	245	\return PSP Register value
AnnaBridge	171:3a7713b1edbc	246	*/
AnnaBridge	171:3a7713b1edbc	247	__STATIC_FORCEINLINE uint32_t __get_PSP(void)
AnnaBridge	171:3a7713b1edbc	248	{
AnnaBridge	171:3a7713b1edbc	249	uint32_t result;
AnnaBridge	171:3a7713b1edbc	250
AnnaBridge	171:3a7713b1edbc	251	__ASM volatile ("MRS %0, psp" : "=r" (result) );
AnnaBridge	171:3a7713b1edbc	252	return(result);
AnnaBridge	171:3a7713b1edbc	253	}
AnnaBridge	171:3a7713b1edbc	254
AnnaBridge	171:3a7713b1edbc	255
AnnaBridge	171:3a7713b1edbc	256	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	171:3a7713b1edbc	257	/**
AnnaBridge	171:3a7713b1edbc	258	\brief Get Process Stack Pointer (non-secure)
AnnaBridge	171:3a7713b1edbc	259	\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge	171:3a7713b1edbc	260	\return PSP Register value
AnnaBridge	171:3a7713b1edbc	261	*/
AnnaBridge	171:3a7713b1edbc	262	__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
AnnaBridge	171:3a7713b1edbc	263	{
AnnaBridge	171:3a7713b1edbc	264	uint32_t result;
AnnaBridge	171:3a7713b1edbc	265
AnnaBridge	171:3a7713b1edbc	266	__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
AnnaBridge	171:3a7713b1edbc	267	return(result);
AnnaBridge	171:3a7713b1edbc	268	}
AnnaBridge	171:3a7713b1edbc	269	#endif
AnnaBridge	171:3a7713b1edbc	270
AnnaBridge	171:3a7713b1edbc	271
AnnaBridge	171:3a7713b1edbc	272	/**
AnnaBridge	171:3a7713b1edbc	273	\brief Set Process Stack Pointer
AnnaBridge	171:3a7713b1edbc	274	\details Assigns the given value to the Process Stack Pointer (PSP).
AnnaBridge	171:3a7713b1edbc	275	\param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge	171:3a7713b1edbc	276	*/
AnnaBridge	171:3a7713b1edbc	277	__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
AnnaBridge	171:3a7713b1edbc	278	{
AnnaBridge	171:3a7713b1edbc	279	__ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
AnnaBridge	171:3a7713b1edbc	280	}
AnnaBridge	171:3a7713b1edbc	281
AnnaBridge	171:3a7713b1edbc	282
AnnaBridge	171:3a7713b1edbc	283	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	171:3a7713b1edbc	284	/**
AnnaBridge	171:3a7713b1edbc	285	\brief Set Process Stack Pointer (non-secure)
AnnaBridge	171:3a7713b1edbc	286	\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge	171:3a7713b1edbc	287	\param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge	171:3a7713b1edbc	288	*/
AnnaBridge	171:3a7713b1edbc	289	__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
AnnaBridge	171:3a7713b1edbc	290	{
AnnaBridge	171:3a7713b1edbc	291	__ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
AnnaBridge	171:3a7713b1edbc	292	}
AnnaBridge	171:3a7713b1edbc	293	#endif
AnnaBridge	171:3a7713b1edbc	294
AnnaBridge	171:3a7713b1edbc	295
AnnaBridge	171:3a7713b1edbc	296	/**
AnnaBridge	171:3a7713b1edbc	297	\brief Get Main Stack Pointer
AnnaBridge	171:3a7713b1edbc	298	\details Returns the current value of the Main Stack Pointer (MSP).
AnnaBridge	171:3a7713b1edbc	299	\return MSP Register value
AnnaBridge	171:3a7713b1edbc	300	*/
AnnaBridge	171:3a7713b1edbc	301	__STATIC_FORCEINLINE uint32_t __get_MSP(void)
AnnaBridge	171:3a7713b1edbc	302	{
AnnaBridge	171:3a7713b1edbc	303	uint32_t result;
AnnaBridge	171:3a7713b1edbc	304
AnnaBridge	171:3a7713b1edbc	305	__ASM volatile ("MRS %0, msp" : "=r" (result) );
AnnaBridge	171:3a7713b1edbc	306	return(result);
AnnaBridge	171:3a7713b1edbc	307	}
AnnaBridge	171:3a7713b1edbc	308
AnnaBridge	171:3a7713b1edbc	309
AnnaBridge	171:3a7713b1edbc	310	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	171:3a7713b1edbc	311	/**
AnnaBridge	171:3a7713b1edbc	312	\brief Get Main Stack Pointer (non-secure)
AnnaBridge	171:3a7713b1edbc	313	\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge	171:3a7713b1edbc	314	\return MSP Register value
AnnaBridge	171:3a7713b1edbc	315	*/
AnnaBridge	171:3a7713b1edbc	316	__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
AnnaBridge	171:3a7713b1edbc	317	{
AnnaBridge	171:3a7713b1edbc	318	uint32_t result;
AnnaBridge	171:3a7713b1edbc	319
AnnaBridge	171:3a7713b1edbc	320	__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
AnnaBridge	171:3a7713b1edbc	321	return(result);
AnnaBridge	171:3a7713b1edbc	322	}
AnnaBridge	171:3a7713b1edbc	323	#endif
AnnaBridge	171:3a7713b1edbc	324
AnnaBridge	171:3a7713b1edbc	325
AnnaBridge	171:3a7713b1edbc	326	/**
AnnaBridge	171:3a7713b1edbc	327	\brief Set Main Stack Pointer
AnnaBridge	171:3a7713b1edbc	328	\details Assigns the given value to the Main Stack Pointer (MSP).
AnnaBridge	171:3a7713b1edbc	329	\param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge	171:3a7713b1edbc	330	*/
AnnaBridge	171:3a7713b1edbc	331	__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
AnnaBridge	171:3a7713b1edbc	332	{
AnnaBridge	171:3a7713b1edbc	333	__ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
AnnaBridge	171:3a7713b1edbc	334	}
AnnaBridge	171:3a7713b1edbc	335
AnnaBridge	171:3a7713b1edbc	336
AnnaBridge	171:3a7713b1edbc	337	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	171:3a7713b1edbc	338	/**
AnnaBridge	171:3a7713b1edbc	339	\brief Set Main Stack Pointer (non-secure)
AnnaBridge	171:3a7713b1edbc	340	\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge	171:3a7713b1edbc	341	\param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge	171:3a7713b1edbc	342	*/
AnnaBridge	171:3a7713b1edbc	343	__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
AnnaBridge	171:3a7713b1edbc	344	{
AnnaBridge	171:3a7713b1edbc	345	__ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
AnnaBridge	171:3a7713b1edbc	346	}
AnnaBridge	171:3a7713b1edbc	347	#endif
AnnaBridge	171:3a7713b1edbc	348
AnnaBridge	171:3a7713b1edbc	349
AnnaBridge	171:3a7713b1edbc	350	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	171:3a7713b1edbc	351	/**
AnnaBridge	171:3a7713b1edbc	352	\brief Get Stack Pointer (non-secure)
AnnaBridge	171:3a7713b1edbc	353	\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge	171:3a7713b1edbc	354	\return SP Register value
AnnaBridge	171:3a7713b1edbc	355	*/
AnnaBridge	171:3a7713b1edbc	356	__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
AnnaBridge	171:3a7713b1edbc	357	{
AnnaBridge	171:3a7713b1edbc	358	uint32_t result;
AnnaBridge	171:3a7713b1edbc	359
AnnaBridge	171:3a7713b1edbc	360	__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
AnnaBridge	171:3a7713b1edbc	361	return(result);
AnnaBridge	171:3a7713b1edbc	362	}
AnnaBridge	171:3a7713b1edbc	363
AnnaBridge	171:3a7713b1edbc	364
AnnaBridge	171:3a7713b1edbc	365	/**
AnnaBridge	171:3a7713b1edbc	366	\brief Set Stack Pointer (non-secure)
AnnaBridge	171:3a7713b1edbc	367	\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge	171:3a7713b1edbc	368	\param [in] topOfStack Stack Pointer value to set
AnnaBridge	171:3a7713b1edbc	369	*/
AnnaBridge	171:3a7713b1edbc	370	__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
AnnaBridge	171:3a7713b1edbc	371	{
AnnaBridge	171:3a7713b1edbc	372	__ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
AnnaBridge	171:3a7713b1edbc	373	}
AnnaBridge	171:3a7713b1edbc	374	#endif
AnnaBridge	171:3a7713b1edbc	375
AnnaBridge	171:3a7713b1edbc	376
AnnaBridge	171:3a7713b1edbc	377	/**
AnnaBridge	171:3a7713b1edbc	378	\brief Get Priority Mask
AnnaBridge	171:3a7713b1edbc	379	\details Returns the current state of the priority mask bit from the Priority Mask Register.
AnnaBridge	171:3a7713b1edbc	380	\return Priority Mask value
AnnaBridge	171:3a7713b1edbc	381	*/
AnnaBridge	171:3a7713b1edbc	382	__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
AnnaBridge	171:3a7713b1edbc	383	{
AnnaBridge	171:3a7713b1edbc	384	uint32_t result;
AnnaBridge	171:3a7713b1edbc	385
AnnaBridge	171:3a7713b1edbc	386	__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
AnnaBridge	171:3a7713b1edbc	387	return(result);
AnnaBridge	171:3a7713b1edbc	388	}
AnnaBridge	171:3a7713b1edbc	389
AnnaBridge	171:3a7713b1edbc	390
AnnaBridge	171:3a7713b1edbc	391	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	171:3a7713b1edbc	392	/**
AnnaBridge	171:3a7713b1edbc	393	\brief Get Priority Mask (non-secure)
AnnaBridge	171:3a7713b1edbc	394	\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
AnnaBridge	171:3a7713b1edbc	395	\return Priority Mask value
AnnaBridge	171:3a7713b1edbc	396	*/
AnnaBridge	171:3a7713b1edbc	397	__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
AnnaBridge	171:3a7713b1edbc	398	{
AnnaBridge	171:3a7713b1edbc	399	uint32_t result;
AnnaBridge	171:3a7713b1edbc	400
AnnaBridge	171:3a7713b1edbc	401	__ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
AnnaBridge	171:3a7713b1edbc	402	return(result);
AnnaBridge	171:3a7713b1edbc	403	}
AnnaBridge	171:3a7713b1edbc	404	#endif
AnnaBridge	171:3a7713b1edbc	405
AnnaBridge	171:3a7713b1edbc	406
AnnaBridge	171:3a7713b1edbc	407	/**
AnnaBridge	171:3a7713b1edbc	408	\brief Set Priority Mask
AnnaBridge	171:3a7713b1edbc	409	\details Assigns the given value to the Priority Mask Register.
AnnaBridge	171:3a7713b1edbc	410	\param [in] priMask Priority Mask
AnnaBridge	171:3a7713b1edbc	411	*/
AnnaBridge	171:3a7713b1edbc	412	__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
AnnaBridge	171:3a7713b1edbc	413	{
AnnaBridge	171:3a7713b1edbc	414	__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
AnnaBridge	171:3a7713b1edbc	415	}
AnnaBridge	171:3a7713b1edbc	416
AnnaBridge	171:3a7713b1edbc	417
AnnaBridge	171:3a7713b1edbc	418	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	171:3a7713b1edbc	419	/**
AnnaBridge	171:3a7713b1edbc	420	\brief Set Priority Mask (non-secure)
AnnaBridge	171:3a7713b1edbc	421	\details Assigns the given value to the non-secure Priority Mask Register when in secure state.
AnnaBridge	171:3a7713b1edbc	422	\param [in] priMask Priority Mask
AnnaBridge	171:3a7713b1edbc	423	*/
AnnaBridge	171:3a7713b1edbc	424	__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
AnnaBridge	171:3a7713b1edbc	425	{
AnnaBridge	171:3a7713b1edbc	426	__ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
AnnaBridge	171:3a7713b1edbc	427	}
AnnaBridge	171:3a7713b1edbc	428	#endif
AnnaBridge	171:3a7713b1edbc	429
AnnaBridge	171:3a7713b1edbc	430
AnnaBridge	171:3a7713b1edbc	431	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	432	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	433	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	171:3a7713b1edbc	434	/**
AnnaBridge	171:3a7713b1edbc	435	\brief Enable FIQ
AnnaBridge	171:3a7713b1edbc	436	\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
AnnaBridge	171:3a7713b1edbc	437	Can only be executed in Privileged modes.
AnnaBridge	171:3a7713b1edbc	438	*/
AnnaBridge	171:3a7713b1edbc	439	__STATIC_FORCEINLINE void __enable_fault_irq(void)
AnnaBridge	171:3a7713b1edbc	440	{
AnnaBridge	171:3a7713b1edbc	441	__ASM volatile ("cpsie f" : : : "memory");
AnnaBridge	171:3a7713b1edbc	442	}
AnnaBridge	171:3a7713b1edbc	443
AnnaBridge	171:3a7713b1edbc	444
AnnaBridge	171:3a7713b1edbc	445	/**
AnnaBridge	171:3a7713b1edbc	446	\brief Disable FIQ
AnnaBridge	171:3a7713b1edbc	447	\details Disables FIQ interrupts by setting the F-bit in the CPSR.
AnnaBridge	171:3a7713b1edbc	448	Can only be executed in Privileged modes.
AnnaBridge	171:3a7713b1edbc	449	*/
AnnaBridge	171:3a7713b1edbc	450	__STATIC_FORCEINLINE void __disable_fault_irq(void)
AnnaBridge	171:3a7713b1edbc	451	{
AnnaBridge	171:3a7713b1edbc	452	__ASM volatile ("cpsid f" : : : "memory");
AnnaBridge	171:3a7713b1edbc	453	}
AnnaBridge	171:3a7713b1edbc	454
AnnaBridge	171:3a7713b1edbc	455
AnnaBridge	171:3a7713b1edbc	456	/**
AnnaBridge	171:3a7713b1edbc	457	\brief Get Base Priority
AnnaBridge	171:3a7713b1edbc	458	\details Returns the current value of the Base Priority register.
AnnaBridge	171:3a7713b1edbc	459	\return Base Priority register value
AnnaBridge	171:3a7713b1edbc	460	*/
AnnaBridge	171:3a7713b1edbc	461	__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
AnnaBridge	171:3a7713b1edbc	462	{
AnnaBridge	171:3a7713b1edbc	463	uint32_t result;
AnnaBridge	171:3a7713b1edbc	464
AnnaBridge	171:3a7713b1edbc	465	__ASM volatile ("MRS %0, basepri" : "=r" (result) );
AnnaBridge	171:3a7713b1edbc	466	return(result);
AnnaBridge	171:3a7713b1edbc	467	}
AnnaBridge	171:3a7713b1edbc	468
AnnaBridge	171:3a7713b1edbc	469
AnnaBridge	171:3a7713b1edbc	470	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	171:3a7713b1edbc	471	/**
AnnaBridge	171:3a7713b1edbc	472	\brief Get Base Priority (non-secure)
AnnaBridge	171:3a7713b1edbc	473	\details Returns the current value of the non-secure Base Priority register when in secure state.
AnnaBridge	171:3a7713b1edbc	474	\return Base Priority register value
AnnaBridge	171:3a7713b1edbc	475	*/
AnnaBridge	171:3a7713b1edbc	476	__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
AnnaBridge	171:3a7713b1edbc	477	{
AnnaBridge	171:3a7713b1edbc	478	uint32_t result;
AnnaBridge	171:3a7713b1edbc	479
AnnaBridge	171:3a7713b1edbc	480	__ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
AnnaBridge	171:3a7713b1edbc	481	return(result);
AnnaBridge	171:3a7713b1edbc	482	}
AnnaBridge	171:3a7713b1edbc	483	#endif
AnnaBridge	171:3a7713b1edbc	484
AnnaBridge	171:3a7713b1edbc	485
AnnaBridge	171:3a7713b1edbc	486	/**
AnnaBridge	171:3a7713b1edbc	487	\brief Set Base Priority
AnnaBridge	171:3a7713b1edbc	488	\details Assigns the given value to the Base Priority register.
AnnaBridge	171:3a7713b1edbc	489	\param [in] basePri Base Priority value to set
AnnaBridge	171:3a7713b1edbc	490	*/
AnnaBridge	171:3a7713b1edbc	491	__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
AnnaBridge	171:3a7713b1edbc	492	{
AnnaBridge	171:3a7713b1edbc	493	__ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
AnnaBridge	171:3a7713b1edbc	494	}
AnnaBridge	171:3a7713b1edbc	495
AnnaBridge	171:3a7713b1edbc	496
AnnaBridge	171:3a7713b1edbc	497	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	171:3a7713b1edbc	498	/**
AnnaBridge	171:3a7713b1edbc	499	\brief Set Base Priority (non-secure)
AnnaBridge	171:3a7713b1edbc	500	\details Assigns the given value to the non-secure Base Priority register when in secure state.
AnnaBridge	171:3a7713b1edbc	501	\param [in] basePri Base Priority value to set
AnnaBridge	171:3a7713b1edbc	502	*/
AnnaBridge	171:3a7713b1edbc	503	__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
AnnaBridge	171:3a7713b1edbc	504	{
AnnaBridge	171:3a7713b1edbc	505	__ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
AnnaBridge	171:3a7713b1edbc	506	}
AnnaBridge	171:3a7713b1edbc	507	#endif
AnnaBridge	171:3a7713b1edbc	508
AnnaBridge	171:3a7713b1edbc	509
AnnaBridge	171:3a7713b1edbc	510	/**
AnnaBridge	171:3a7713b1edbc	511	\brief Set Base Priority with condition
AnnaBridge	171:3a7713b1edbc	512	\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
AnnaBridge	171:3a7713b1edbc	513	or the new value increases the BASEPRI priority level.
AnnaBridge	171:3a7713b1edbc	514	\param [in] basePri Base Priority value to set
AnnaBridge	171:3a7713b1edbc	515	*/
AnnaBridge	171:3a7713b1edbc	516	__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
AnnaBridge	171:3a7713b1edbc	517	{
AnnaBridge	171:3a7713b1edbc	518	__ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
AnnaBridge	171:3a7713b1edbc	519	}
AnnaBridge	171:3a7713b1edbc	520
AnnaBridge	171:3a7713b1edbc	521
AnnaBridge	171:3a7713b1edbc	522	/**
AnnaBridge	171:3a7713b1edbc	523	\brief Get Fault Mask
AnnaBridge	171:3a7713b1edbc	524	\details Returns the current value of the Fault Mask register.
AnnaBridge	171:3a7713b1edbc	525	\return Fault Mask register value
AnnaBridge	171:3a7713b1edbc	526	*/
AnnaBridge	171:3a7713b1edbc	527	__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
AnnaBridge	171:3a7713b1edbc	528	{
AnnaBridge	171:3a7713b1edbc	529	uint32_t result;
AnnaBridge	171:3a7713b1edbc	530
AnnaBridge	171:3a7713b1edbc	531	__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
AnnaBridge	171:3a7713b1edbc	532	return(result);
AnnaBridge	171:3a7713b1edbc	533	}
AnnaBridge	171:3a7713b1edbc	534
AnnaBridge	171:3a7713b1edbc	535
AnnaBridge	171:3a7713b1edbc	536	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	171:3a7713b1edbc	537	/**
AnnaBridge	171:3a7713b1edbc	538	\brief Get Fault Mask (non-secure)
AnnaBridge	171:3a7713b1edbc	539	\details Returns the current value of the non-secure Fault Mask register when in secure state.
AnnaBridge	171:3a7713b1edbc	540	\return Fault Mask register value
AnnaBridge	171:3a7713b1edbc	541	*/
AnnaBridge	171:3a7713b1edbc	542	__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
AnnaBridge	171:3a7713b1edbc	543	{
AnnaBridge	171:3a7713b1edbc	544	uint32_t result;
AnnaBridge	171:3a7713b1edbc	545
AnnaBridge	171:3a7713b1edbc	546	__ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
AnnaBridge	171:3a7713b1edbc	547	return(result);
AnnaBridge	171:3a7713b1edbc	548	}
AnnaBridge	171:3a7713b1edbc	549	#endif
AnnaBridge	171:3a7713b1edbc	550
AnnaBridge	171:3a7713b1edbc	551
AnnaBridge	171:3a7713b1edbc	552	/**
AnnaBridge	171:3a7713b1edbc	553	\brief Set Fault Mask
AnnaBridge	171:3a7713b1edbc	554	\details Assigns the given value to the Fault Mask register.
AnnaBridge	171:3a7713b1edbc	555	\param [in] faultMask Fault Mask value to set
AnnaBridge	171:3a7713b1edbc	556	*/
AnnaBridge	171:3a7713b1edbc	557	__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
AnnaBridge	171:3a7713b1edbc	558	{
AnnaBridge	171:3a7713b1edbc	559	__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
AnnaBridge	171:3a7713b1edbc	560	}
AnnaBridge	171:3a7713b1edbc	561
AnnaBridge	171:3a7713b1edbc	562
AnnaBridge	171:3a7713b1edbc	563	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	171:3a7713b1edbc	564	/**
AnnaBridge	171:3a7713b1edbc	565	\brief Set Fault Mask (non-secure)
AnnaBridge	171:3a7713b1edbc	566	\details Assigns the given value to the non-secure Fault Mask register when in secure state.
AnnaBridge	171:3a7713b1edbc	567	\param [in] faultMask Fault Mask value to set
AnnaBridge	171:3a7713b1edbc	568	*/
AnnaBridge	171:3a7713b1edbc	569	__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
AnnaBridge	171:3a7713b1edbc	570	{
AnnaBridge	171:3a7713b1edbc	571	__ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
AnnaBridge	171:3a7713b1edbc	572	}
AnnaBridge	171:3a7713b1edbc	573	#endif
AnnaBridge	171:3a7713b1edbc	574
AnnaBridge	171:3a7713b1edbc	575	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	576	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	577	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge	171:3a7713b1edbc	578
AnnaBridge	171:3a7713b1edbc	579
AnnaBridge	171:3a7713b1edbc	580	#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	581	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge	171:3a7713b1edbc	582
AnnaBridge	171:3a7713b1edbc	583	/**
AnnaBridge	171:3a7713b1edbc	584	\brief Get Process Stack Pointer Limit
AnnaBridge	171:3a7713b1edbc	585	Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
AnnaBridge	171:3a7713b1edbc	586	Stack Pointer Limit register hence zero is returned always in non-secure
AnnaBridge	171:3a7713b1edbc	587	mode.
AnnaBridge	171:3a7713b1edbc	588
AnnaBridge	171:3a7713b1edbc	589	\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
AnnaBridge	171:3a7713b1edbc	590	\return PSPLIM Register value
AnnaBridge	171:3a7713b1edbc	591	*/
AnnaBridge	171:3a7713b1edbc	592	__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
AnnaBridge	171:3a7713b1edbc	593	{
AnnaBridge	171:3a7713b1edbc	594	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
AnnaBridge	171:3a7713b1edbc	595	(!defined (__ARM_FEATURE_CMSE) \|\| (__ARM_FEATURE_CMSE < 3)))
AnnaBridge	171:3a7713b1edbc	596	// without main extensions, the non-secure PSPLIM is RAZ/WI
AnnaBridge	171:3a7713b1edbc	597	return 0U;
AnnaBridge	171:3a7713b1edbc	598	#else
AnnaBridge	171:3a7713b1edbc	599	uint32_t result;
AnnaBridge	171:3a7713b1edbc	600	__ASM volatile ("MRS %0, psplim" : "=r" (result) );
AnnaBridge	171:3a7713b1edbc	601	return result;
AnnaBridge	171:3a7713b1edbc	602	#endif
AnnaBridge	171:3a7713b1edbc	603	}
AnnaBridge	171:3a7713b1edbc	604
AnnaBridge	171:3a7713b1edbc	605	#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	171:3a7713b1edbc	606	/**
AnnaBridge	171:3a7713b1edbc	607	\brief Get Process Stack Pointer Limit (non-secure)
AnnaBridge	171:3a7713b1edbc	608	Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
AnnaBridge	171:3a7713b1edbc	609	Stack Pointer Limit register hence zero is returned always.
AnnaBridge	171:3a7713b1edbc	610
AnnaBridge	171:3a7713b1edbc	611	\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge	171:3a7713b1edbc	612	\return PSPLIM Register value
AnnaBridge	171:3a7713b1edbc	613	*/
AnnaBridge	171:3a7713b1edbc	614	__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
AnnaBridge	171:3a7713b1edbc	615	{
AnnaBridge	171:3a7713b1edbc	616	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
AnnaBridge	171:3a7713b1edbc	617	// without main extensions, the non-secure PSPLIM is RAZ/WI
AnnaBridge	171:3a7713b1edbc	618	return 0U;
AnnaBridge	171:3a7713b1edbc	619	#else
AnnaBridge	171:3a7713b1edbc	620	uint32_t result;
AnnaBridge	171:3a7713b1edbc	621	__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
AnnaBridge	171:3a7713b1edbc	622	return result;
AnnaBridge	171:3a7713b1edbc	623	#endif
AnnaBridge	171:3a7713b1edbc	624	}
AnnaBridge	171:3a7713b1edbc	625	#endif
AnnaBridge	171:3a7713b1edbc	626
AnnaBridge	171:3a7713b1edbc	627
AnnaBridge	171:3a7713b1edbc	628	/**
AnnaBridge	171:3a7713b1edbc	629	\brief Set Process Stack Pointer Limit
AnnaBridge	171:3a7713b1edbc	630	Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
AnnaBridge	171:3a7713b1edbc	631	Stack Pointer Limit register hence the write is silently ignored in non-secure
AnnaBridge	171:3a7713b1edbc	632	mode.
AnnaBridge	171:3a7713b1edbc	633
AnnaBridge	171:3a7713b1edbc	634	\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
AnnaBridge	171:3a7713b1edbc	635	\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge	171:3a7713b1edbc	636	*/
AnnaBridge	171:3a7713b1edbc	637	__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
AnnaBridge	171:3a7713b1edbc	638	{
AnnaBridge	171:3a7713b1edbc	639	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
AnnaBridge	171:3a7713b1edbc	640	(!defined (__ARM_FEATURE_CMSE) \|\| (__ARM_FEATURE_CMSE < 3)))
AnnaBridge	171:3a7713b1edbc	641	// without main extensions, the non-secure PSPLIM is RAZ/WI
AnnaBridge	171:3a7713b1edbc	642	(void)ProcStackPtrLimit;
AnnaBridge	171:3a7713b1edbc	643	#else
AnnaBridge	171:3a7713b1edbc	644	__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
AnnaBridge	171:3a7713b1edbc	645	#endif
AnnaBridge	171:3a7713b1edbc	646	}
AnnaBridge	171:3a7713b1edbc	647
AnnaBridge	171:3a7713b1edbc	648
AnnaBridge	171:3a7713b1edbc	649	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	171:3a7713b1edbc	650	/**
AnnaBridge	171:3a7713b1edbc	651	\brief Set Process Stack Pointer (non-secure)
AnnaBridge	171:3a7713b1edbc	652	Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
AnnaBridge	171:3a7713b1edbc	653	Stack Pointer Limit register hence the write is silently ignored.
AnnaBridge	171:3a7713b1edbc	654
AnnaBridge	171:3a7713b1edbc	655	\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge	171:3a7713b1edbc	656	\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge	171:3a7713b1edbc	657	*/
AnnaBridge	171:3a7713b1edbc	658	__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
AnnaBridge	171:3a7713b1edbc	659	{
AnnaBridge	171:3a7713b1edbc	660	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
AnnaBridge	171:3a7713b1edbc	661	// without main extensions, the non-secure PSPLIM is RAZ/WI
AnnaBridge	171:3a7713b1edbc	662	(void)ProcStackPtrLimit;
AnnaBridge	171:3a7713b1edbc	663	#else
AnnaBridge	171:3a7713b1edbc	664	__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
AnnaBridge	171:3a7713b1edbc	665	#endif
AnnaBridge	171:3a7713b1edbc	666	}
AnnaBridge	171:3a7713b1edbc	667	#endif
AnnaBridge	171:3a7713b1edbc	668
AnnaBridge	171:3a7713b1edbc	669
AnnaBridge	171:3a7713b1edbc	670	/**
AnnaBridge	171:3a7713b1edbc	671	\brief Get Main Stack Pointer Limit
AnnaBridge	171:3a7713b1edbc	672	Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
AnnaBridge	171:3a7713b1edbc	673	Stack Pointer Limit register hence zero is returned always in non-secure
AnnaBridge	171:3a7713b1edbc	674	mode.
AnnaBridge	171:3a7713b1edbc	675
AnnaBridge	171:3a7713b1edbc	676	\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
AnnaBridge	171:3a7713b1edbc	677	\return MSPLIM Register value
AnnaBridge	171:3a7713b1edbc	678	*/
AnnaBridge	171:3a7713b1edbc	679	__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
AnnaBridge	171:3a7713b1edbc	680	{
AnnaBridge	171:3a7713b1edbc	681	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
AnnaBridge	171:3a7713b1edbc	682	(!defined (__ARM_FEATURE_CMSE) \|\| (__ARM_FEATURE_CMSE < 3)))
AnnaBridge	171:3a7713b1edbc	683	// without main extensions, the non-secure MSPLIM is RAZ/WI
AnnaBridge	171:3a7713b1edbc	684	return 0U;
AnnaBridge	171:3a7713b1edbc	685	#else
AnnaBridge	171:3a7713b1edbc	686	uint32_t result;
AnnaBridge	171:3a7713b1edbc	687	__ASM volatile ("MRS %0, msplim" : "=r" (result) );
AnnaBridge	171:3a7713b1edbc	688	return result;
AnnaBridge	171:3a7713b1edbc	689	#endif
AnnaBridge	171:3a7713b1edbc	690	}
AnnaBridge	171:3a7713b1edbc	691
AnnaBridge	171:3a7713b1edbc	692
AnnaBridge	171:3a7713b1edbc	693	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	171:3a7713b1edbc	694	/**
AnnaBridge	171:3a7713b1edbc	695	\brief Get Main Stack Pointer Limit (non-secure)
AnnaBridge	171:3a7713b1edbc	696	Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
AnnaBridge	171:3a7713b1edbc	697	Stack Pointer Limit register hence zero is returned always.
AnnaBridge	171:3a7713b1edbc	698
AnnaBridge	171:3a7713b1edbc	699	\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
AnnaBridge	171:3a7713b1edbc	700	\return MSPLIM Register value
AnnaBridge	171:3a7713b1edbc	701	*/
AnnaBridge	171:3a7713b1edbc	702	__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
AnnaBridge	171:3a7713b1edbc	703	{
AnnaBridge	171:3a7713b1edbc	704	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
AnnaBridge	171:3a7713b1edbc	705	// without main extensions, the non-secure MSPLIM is RAZ/WI
AnnaBridge	171:3a7713b1edbc	706	return 0U;
AnnaBridge	171:3a7713b1edbc	707	#else
AnnaBridge	171:3a7713b1edbc	708	uint32_t result;
AnnaBridge	171:3a7713b1edbc	709	__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
AnnaBridge	171:3a7713b1edbc	710	return result;
AnnaBridge	171:3a7713b1edbc	711	#endif
AnnaBridge	171:3a7713b1edbc	712	}
AnnaBridge	171:3a7713b1edbc	713	#endif
AnnaBridge	171:3a7713b1edbc	714
AnnaBridge	171:3a7713b1edbc	715
AnnaBridge	171:3a7713b1edbc	716	/**
AnnaBridge	171:3a7713b1edbc	717	\brief Set Main Stack Pointer Limit
AnnaBridge	171:3a7713b1edbc	718	Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
AnnaBridge	171:3a7713b1edbc	719	Stack Pointer Limit register hence the write is silently ignored in non-secure
AnnaBridge	171:3a7713b1edbc	720	mode.
AnnaBridge	171:3a7713b1edbc	721
AnnaBridge	171:3a7713b1edbc	722	\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
AnnaBridge	171:3a7713b1edbc	723	\param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
AnnaBridge	171:3a7713b1edbc	724	*/
AnnaBridge	171:3a7713b1edbc	725	__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
AnnaBridge	171:3a7713b1edbc	726	{
AnnaBridge	171:3a7713b1edbc	727	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
AnnaBridge	171:3a7713b1edbc	728	(!defined (__ARM_FEATURE_CMSE) \|\| (__ARM_FEATURE_CMSE < 3)))
AnnaBridge	171:3a7713b1edbc	729	// without main extensions, the non-secure MSPLIM is RAZ/WI
AnnaBridge	171:3a7713b1edbc	730	(void)MainStackPtrLimit;
AnnaBridge	171:3a7713b1edbc	731	#else
AnnaBridge	171:3a7713b1edbc	732	__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
AnnaBridge	171:3a7713b1edbc	733	#endif
AnnaBridge	171:3a7713b1edbc	734	}
AnnaBridge	171:3a7713b1edbc	735
AnnaBridge	171:3a7713b1edbc	736
AnnaBridge	171:3a7713b1edbc	737	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	171:3a7713b1edbc	738	/**
AnnaBridge	171:3a7713b1edbc	739	\brief Set Main Stack Pointer Limit (non-secure)
AnnaBridge	171:3a7713b1edbc	740	Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
AnnaBridge	171:3a7713b1edbc	741	Stack Pointer Limit register hence the write is silently ignored.
AnnaBridge	171:3a7713b1edbc	742
AnnaBridge	171:3a7713b1edbc	743	\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
AnnaBridge	171:3a7713b1edbc	744	\param [in] MainStackPtrLimit Main Stack Pointer value to set
AnnaBridge	171:3a7713b1edbc	745	*/
AnnaBridge	171:3a7713b1edbc	746	__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
AnnaBridge	171:3a7713b1edbc	747	{
AnnaBridge	171:3a7713b1edbc	748	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
AnnaBridge	171:3a7713b1edbc	749	// without main extensions, the non-secure MSPLIM is RAZ/WI
AnnaBridge	171:3a7713b1edbc	750	(void)MainStackPtrLimit;
AnnaBridge	171:3a7713b1edbc	751	#else
AnnaBridge	171:3a7713b1edbc	752	__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
AnnaBridge	171:3a7713b1edbc	753	#endif
AnnaBridge	171:3a7713b1edbc	754	}
AnnaBridge	171:3a7713b1edbc	755	#endif
AnnaBridge	171:3a7713b1edbc	756
AnnaBridge	171:3a7713b1edbc	757	#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	758	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge	171:3a7713b1edbc	759
AnnaBridge	171:3a7713b1edbc	760
AnnaBridge	171:3a7713b1edbc	761	/**
AnnaBridge	171:3a7713b1edbc	762	\brief Get FPSCR
AnnaBridge	171:3a7713b1edbc	763	\details Returns the current value of the Floating Point Status/Control register.
AnnaBridge	171:3a7713b1edbc	764	\return Floating Point Status/Control register value
AnnaBridge	171:3a7713b1edbc	765	*/
AnnaBridge	171:3a7713b1edbc	766	__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
AnnaBridge	171:3a7713b1edbc	767	{
AnnaBridge	171:3a7713b1edbc	768	#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge	171:3a7713b1edbc	769	(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge	171:3a7713b1edbc	770	#if __has_builtin(__builtin_arm_get_fpscr)
AnnaBridge	171:3a7713b1edbc	771	// Re-enable using built-in when GCC has been fixed
AnnaBridge	171:3a7713b1edbc	772	// \|\| (__GNUC__ > 7) \|\| (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
AnnaBridge	171:3a7713b1edbc	773	/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
AnnaBridge	171:3a7713b1edbc	774	return __builtin_arm_get_fpscr();
AnnaBridge	171:3a7713b1edbc	775	#else
AnnaBridge	171:3a7713b1edbc	776	uint32_t result;
AnnaBridge	171:3a7713b1edbc	777
AnnaBridge	171:3a7713b1edbc	778	__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
AnnaBridge	171:3a7713b1edbc	779	return(result);
AnnaBridge	171:3a7713b1edbc	780	#endif
AnnaBridge	171:3a7713b1edbc	781	#else
AnnaBridge	171:3a7713b1edbc	782	return(0U);
AnnaBridge	171:3a7713b1edbc	783	#endif
AnnaBridge	171:3a7713b1edbc	784	}
AnnaBridge	171:3a7713b1edbc	785
AnnaBridge	171:3a7713b1edbc	786
AnnaBridge	171:3a7713b1edbc	787	/**
AnnaBridge	171:3a7713b1edbc	788	\brief Set FPSCR
AnnaBridge	171:3a7713b1edbc	789	\details Assigns the given value to the Floating Point Status/Control register.
AnnaBridge	171:3a7713b1edbc	790	\param [in] fpscr Floating Point Status/Control value to set
AnnaBridge	171:3a7713b1edbc	791	*/
AnnaBridge	171:3a7713b1edbc	792	__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
AnnaBridge	171:3a7713b1edbc	793	{
AnnaBridge	171:3a7713b1edbc	794	#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge	171:3a7713b1edbc	795	(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge	171:3a7713b1edbc	796	#if __has_builtin(__builtin_arm_set_fpscr)
AnnaBridge	171:3a7713b1edbc	797	// Re-enable using built-in when GCC has been fixed
AnnaBridge	171:3a7713b1edbc	798	// \|\| (__GNUC__ > 7) \|\| (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
AnnaBridge	171:3a7713b1edbc	799	/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
AnnaBridge	171:3a7713b1edbc	800	__builtin_arm_set_fpscr(fpscr);
AnnaBridge	171:3a7713b1edbc	801	#else
AnnaBridge	171:3a7713b1edbc	802	__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
AnnaBridge	171:3a7713b1edbc	803	#endif
AnnaBridge	171:3a7713b1edbc	804	#else
AnnaBridge	171:3a7713b1edbc	805	(void)fpscr;
AnnaBridge	171:3a7713b1edbc	806	#endif
AnnaBridge	171:3a7713b1edbc	807	}
AnnaBridge	171:3a7713b1edbc	808
AnnaBridge	171:3a7713b1edbc	809
AnnaBridge	171:3a7713b1edbc	810	/@} end of CMSIS_Core_RegAccFunctions /
AnnaBridge	171:3a7713b1edbc	811
AnnaBridge	171:3a7713b1edbc	812
AnnaBridge	171:3a7713b1edbc	813	/* ########################## Core Instruction Access ######################### */
AnnaBridge	171:3a7713b1edbc	814	/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
AnnaBridge	171:3a7713b1edbc	815	Access to dedicated instructions
AnnaBridge	171:3a7713b1edbc	816	@{
AnnaBridge	171:3a7713b1edbc	817	*/
AnnaBridge	171:3a7713b1edbc	818
AnnaBridge	171:3a7713b1edbc	819	/* Define macros for porting to both thumb1 and thumb2.
AnnaBridge	171:3a7713b1edbc	820	* For thumb1, use low register (r0-r7), specified by constraint "l"
AnnaBridge	171:3a7713b1edbc	821	* Otherwise, use general registers, specified by constraint "r" */
AnnaBridge	171:3a7713b1edbc	822	#if defined (__thumb__) && !defined (__thumb2__)
AnnaBridge	171:3a7713b1edbc	823	#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
AnnaBridge	171:3a7713b1edbc	824	#define __CMSIS_GCC_RW_REG(r) "+l" (r)
AnnaBridge	171:3a7713b1edbc	825	#define __CMSIS_GCC_USE_REG(r) "l" (r)
AnnaBridge	171:3a7713b1edbc	826	#else
AnnaBridge	171:3a7713b1edbc	827	#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
AnnaBridge	171:3a7713b1edbc	828	#define __CMSIS_GCC_RW_REG(r) "+r" (r)
AnnaBridge	171:3a7713b1edbc	829	#define __CMSIS_GCC_USE_REG(r) "r" (r)
AnnaBridge	171:3a7713b1edbc	830	#endif
AnnaBridge	171:3a7713b1edbc	831
AnnaBridge	171:3a7713b1edbc	832	/**
AnnaBridge	171:3a7713b1edbc	833	\brief No Operation
AnnaBridge	171:3a7713b1edbc	834	\details No Operation does nothing. This instruction can be used for code alignment purposes.
AnnaBridge	171:3a7713b1edbc	835	*/
AnnaBridge	171:3a7713b1edbc	836	#define __NOP() __ASM volatile ("nop")
AnnaBridge	171:3a7713b1edbc	837
AnnaBridge	171:3a7713b1edbc	838	/**
AnnaBridge	171:3a7713b1edbc	839	\brief Wait For Interrupt
AnnaBridge	171:3a7713b1edbc	840	\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
AnnaBridge	171:3a7713b1edbc	841	*/
AnnaBridge	171:3a7713b1edbc	842	#define __WFI() __ASM volatile ("wfi")
AnnaBridge	171:3a7713b1edbc	843
AnnaBridge	171:3a7713b1edbc	844
AnnaBridge	171:3a7713b1edbc	845	/**
AnnaBridge	171:3a7713b1edbc	846	\brief Wait For Event
AnnaBridge	171:3a7713b1edbc	847	\details Wait For Event is a hint instruction that permits the processor to enter
AnnaBridge	171:3a7713b1edbc	848	a low-power state until one of a number of events occurs.
AnnaBridge	171:3a7713b1edbc	849	*/
AnnaBridge	171:3a7713b1edbc	850	#define __WFE() __ASM volatile ("wfe")
AnnaBridge	171:3a7713b1edbc	851
AnnaBridge	171:3a7713b1edbc	852
AnnaBridge	171:3a7713b1edbc	853	/**
AnnaBridge	171:3a7713b1edbc	854	\brief Send Event
AnnaBridge	171:3a7713b1edbc	855	\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
AnnaBridge	171:3a7713b1edbc	856	*/
AnnaBridge	171:3a7713b1edbc	857	#define __SEV() __ASM volatile ("sev")
AnnaBridge	171:3a7713b1edbc	858
AnnaBridge	171:3a7713b1edbc	859
AnnaBridge	171:3a7713b1edbc	860	/**
AnnaBridge	171:3a7713b1edbc	861	\brief Instruction Synchronization Barrier
AnnaBridge	171:3a7713b1edbc	862	\details Instruction Synchronization Barrier flushes the pipeline in the processor,
AnnaBridge	171:3a7713b1edbc	863	so that all instructions following the ISB are fetched from cache or memory,
AnnaBridge	171:3a7713b1edbc	864	after the instruction has been completed.
AnnaBridge	171:3a7713b1edbc	865	*/
AnnaBridge	171:3a7713b1edbc	866	__STATIC_FORCEINLINE void __ISB(void)
AnnaBridge	171:3a7713b1edbc	867	{
AnnaBridge	171:3a7713b1edbc	868	__ASM volatile ("isb 0xF":::"memory");
AnnaBridge	171:3a7713b1edbc	869	}
AnnaBridge	171:3a7713b1edbc	870
AnnaBridge	171:3a7713b1edbc	871
AnnaBridge	171:3a7713b1edbc	872	/**
AnnaBridge	171:3a7713b1edbc	873	\brief Data Synchronization Barrier
AnnaBridge	171:3a7713b1edbc	874	\details Acts as a special kind of Data Memory Barrier.
AnnaBridge	171:3a7713b1edbc	875	It completes when all explicit memory accesses before this instruction complete.
AnnaBridge	171:3a7713b1edbc	876	*/
AnnaBridge	171:3a7713b1edbc	877	__STATIC_FORCEINLINE void __DSB(void)
AnnaBridge	171:3a7713b1edbc	878	{
AnnaBridge	171:3a7713b1edbc	879	__ASM volatile ("dsb 0xF":::"memory");
AnnaBridge	171:3a7713b1edbc	880	}
AnnaBridge	171:3a7713b1edbc	881
AnnaBridge	171:3a7713b1edbc	882
AnnaBridge	171:3a7713b1edbc	883	/**
AnnaBridge	171:3a7713b1edbc	884	\brief Data Memory Barrier
AnnaBridge	171:3a7713b1edbc	885	\details Ensures the apparent order of the explicit memory operations before
AnnaBridge	171:3a7713b1edbc	886	and after the instruction, without ensuring their completion.
AnnaBridge	171:3a7713b1edbc	887	*/
AnnaBridge	171:3a7713b1edbc	888	__STATIC_FORCEINLINE void __DMB(void)
AnnaBridge	171:3a7713b1edbc	889	{
AnnaBridge	171:3a7713b1edbc	890	__ASM volatile ("dmb 0xF":::"memory");
AnnaBridge	171:3a7713b1edbc	891	}
AnnaBridge	171:3a7713b1edbc	892
AnnaBridge	171:3a7713b1edbc	893
AnnaBridge	171:3a7713b1edbc	894	/**
AnnaBridge	171:3a7713b1edbc	895	\brief Reverse byte order (32 bit)
AnnaBridge	171:3a7713b1edbc	896	\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
AnnaBridge	171:3a7713b1edbc	897	\param [in] value Value to reverse
AnnaBridge	171:3a7713b1edbc	898	\return Reversed value
AnnaBridge	171:3a7713b1edbc	899	*/
AnnaBridge	171:3a7713b1edbc	900	__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
AnnaBridge	171:3a7713b1edbc	901	{
AnnaBridge	171:3a7713b1edbc	902	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
AnnaBridge	171:3a7713b1edbc	903	return __builtin_bswap32(value);
AnnaBridge	171:3a7713b1edbc	904	#else
AnnaBridge	171:3a7713b1edbc	905	uint32_t result;
AnnaBridge	171:3a7713b1edbc	906
AnnaBridge	171:3a7713b1edbc	907	__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge	171:3a7713b1edbc	908	return result;
AnnaBridge	171:3a7713b1edbc	909	#endif
AnnaBridge	171:3a7713b1edbc	910	}
AnnaBridge	171:3a7713b1edbc	911
AnnaBridge	171:3a7713b1edbc	912
AnnaBridge	171:3a7713b1edbc	913	/**
AnnaBridge	171:3a7713b1edbc	914	\brief Reverse byte order (16 bit)
AnnaBridge	171:3a7713b1edbc	915	\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
AnnaBridge	171:3a7713b1edbc	916	\param [in] value Value to reverse
AnnaBridge	171:3a7713b1edbc	917	\return Reversed value
AnnaBridge	171:3a7713b1edbc	918	*/
AnnaBridge	171:3a7713b1edbc	919	__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
AnnaBridge	171:3a7713b1edbc	920	{
AnnaBridge	171:3a7713b1edbc	921	uint32_t result;
AnnaBridge	171:3a7713b1edbc	922
AnnaBridge	171:3a7713b1edbc	923	__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge	171:3a7713b1edbc	924	return result;
AnnaBridge	171:3a7713b1edbc	925	}
AnnaBridge	171:3a7713b1edbc	926
AnnaBridge	171:3a7713b1edbc	927
AnnaBridge	171:3a7713b1edbc	928	/**
AnnaBridge	171:3a7713b1edbc	929	\brief Reverse byte order (16 bit)
AnnaBridge	171:3a7713b1edbc	930	\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
AnnaBridge	171:3a7713b1edbc	931	\param [in] value Value to reverse
AnnaBridge	171:3a7713b1edbc	932	\return Reversed value
AnnaBridge	171:3a7713b1edbc	933	*/
AnnaBridge	171:3a7713b1edbc	934	__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
AnnaBridge	171:3a7713b1edbc	935	{
AnnaBridge	171:3a7713b1edbc	936	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	171:3a7713b1edbc	937	return (int16_t)__builtin_bswap16(value);
AnnaBridge	171:3a7713b1edbc	938	#else
AnnaBridge	171:3a7713b1edbc	939	int16_t result;
AnnaBridge	171:3a7713b1edbc	940
AnnaBridge	171:3a7713b1edbc	941	__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge	171:3a7713b1edbc	942	return result;
AnnaBridge	171:3a7713b1edbc	943	#endif
AnnaBridge	171:3a7713b1edbc	944	}
AnnaBridge	171:3a7713b1edbc	945
AnnaBridge	171:3a7713b1edbc	946
AnnaBridge	171:3a7713b1edbc	947	/**
AnnaBridge	171:3a7713b1edbc	948	\brief Rotate Right in unsigned value (32 bit)
AnnaBridge	171:3a7713b1edbc	949	\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
AnnaBridge	171:3a7713b1edbc	950	\param [in] op1 Value to rotate
AnnaBridge	171:3a7713b1edbc	951	\param [in] op2 Number of Bits to rotate
AnnaBridge	171:3a7713b1edbc	952	\return Rotated value
AnnaBridge	171:3a7713b1edbc	953	*/
AnnaBridge	171:3a7713b1edbc	954	__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	955	{
AnnaBridge	171:3a7713b1edbc	956	op2 %= 32U;
AnnaBridge	171:3a7713b1edbc	957	if (op2 == 0U)
AnnaBridge	171:3a7713b1edbc	958	{
AnnaBridge	171:3a7713b1edbc	959	return op1;
AnnaBridge	171:3a7713b1edbc	960	}
AnnaBridge	171:3a7713b1edbc	961	return (op1 >> op2) \| (op1 << (32U - op2));
AnnaBridge	171:3a7713b1edbc	962	}
AnnaBridge	171:3a7713b1edbc	963
AnnaBridge	171:3a7713b1edbc	964
AnnaBridge	171:3a7713b1edbc	965	/**
AnnaBridge	171:3a7713b1edbc	966	\brief Breakpoint
AnnaBridge	171:3a7713b1edbc	967	\details Causes the processor to enter Debug state.
AnnaBridge	171:3a7713b1edbc	968	Debug tools can use this to investigate system state when the instruction at a particular address is reached.
AnnaBridge	171:3a7713b1edbc	969	\param [in] value is ignored by the processor.
AnnaBridge	171:3a7713b1edbc	970	If required, a debugger can use it to store additional information about the breakpoint.
AnnaBridge	171:3a7713b1edbc	971	*/
AnnaBridge	171:3a7713b1edbc	972	#define __BKPT(value) __ASM volatile ("bkpt "#value)
AnnaBridge	171:3a7713b1edbc	973
AnnaBridge	171:3a7713b1edbc	974
AnnaBridge	171:3a7713b1edbc	975	/**
AnnaBridge	171:3a7713b1edbc	976	\brief Reverse bit order of value
AnnaBridge	171:3a7713b1edbc	977	\details Reverses the bit order of the given value.
AnnaBridge	171:3a7713b1edbc	978	\param [in] value Value to reverse
AnnaBridge	171:3a7713b1edbc	979	\return Reversed value
AnnaBridge	171:3a7713b1edbc	980	*/
AnnaBridge	171:3a7713b1edbc	981	__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
AnnaBridge	171:3a7713b1edbc	982	{
AnnaBridge	171:3a7713b1edbc	983	uint32_t result;
AnnaBridge	171:3a7713b1edbc	984
AnnaBridge	171:3a7713b1edbc	985	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	986	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	987	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	171:3a7713b1edbc	988	__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
AnnaBridge	171:3a7713b1edbc	989	#else
AnnaBridge	171:3a7713b1edbc	990	uint32_t s = (4U /sizeof(v)/ * 8U) - 1U; /* extra shift needed at end */
AnnaBridge	171:3a7713b1edbc	991
AnnaBridge	171:3a7713b1edbc	992	result = value; /* r will be reversed bits of v; first get LSB of v */
AnnaBridge	171:3a7713b1edbc	993	for (value >>= 1U; value != 0U; value >>= 1U)
AnnaBridge	171:3a7713b1edbc	994	{
AnnaBridge	171:3a7713b1edbc	995	result <<= 1U;
AnnaBridge	171:3a7713b1edbc	996	result \|= value & 1U;
AnnaBridge	171:3a7713b1edbc	997	s--;
AnnaBridge	171:3a7713b1edbc	998	}
AnnaBridge	171:3a7713b1edbc	999	result <<= s; /* shift when v's highest bits are zero */
AnnaBridge	171:3a7713b1edbc	1000	#endif
AnnaBridge	171:3a7713b1edbc	1001	return result;
AnnaBridge	171:3a7713b1edbc	1002	}
AnnaBridge	171:3a7713b1edbc	1003
AnnaBridge	171:3a7713b1edbc	1004
AnnaBridge	171:3a7713b1edbc	1005	/**
AnnaBridge	171:3a7713b1edbc	1006	\brief Count leading zeros
AnnaBridge	171:3a7713b1edbc	1007	\details Counts the number of leading zeros of a data value.
AnnaBridge	171:3a7713b1edbc	1008	\param [in] value Value to count the leading zeros
AnnaBridge	171:3a7713b1edbc	1009	\return number of leading zeros in value
AnnaBridge	171:3a7713b1edbc	1010	*/
AnnaBridge	171:3a7713b1edbc	1011	#define __CLZ (uint8_t)__builtin_clz
AnnaBridge	171:3a7713b1edbc	1012
AnnaBridge	171:3a7713b1edbc	1013
AnnaBridge	171:3a7713b1edbc	1014	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	1015	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	1016	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	1017	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge	171:3a7713b1edbc	1018	/**
AnnaBridge	171:3a7713b1edbc	1019	\brief LDR Exclusive (8 bit)
AnnaBridge	171:3a7713b1edbc	1020	\details Executes a exclusive LDR instruction for 8 bit value.
AnnaBridge	171:3a7713b1edbc	1021	\param [in] ptr Pointer to data
AnnaBridge	171:3a7713b1edbc	1022	\return value of type uint8_t at (*ptr)
AnnaBridge	171:3a7713b1edbc	1023	*/
AnnaBridge	171:3a7713b1edbc	1024	__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
AnnaBridge	171:3a7713b1edbc	1025	{
AnnaBridge	171:3a7713b1edbc	1026	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1027
AnnaBridge	171:3a7713b1edbc	1028	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	171:3a7713b1edbc	1029	__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge	171:3a7713b1edbc	1030	#else
AnnaBridge	171:3a7713b1edbc	1031	/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge	171:3a7713b1edbc	1032	accepted by assembler. So has to use following less efficient pattern.
AnnaBridge	171:3a7713b1edbc	1033	*/
AnnaBridge	171:3a7713b1edbc	1034	__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
AnnaBridge	171:3a7713b1edbc	1035	#endif
AnnaBridge	171:3a7713b1edbc	1036	return ((uint8_t) result); /* Add explicit type cast here */
AnnaBridge	171:3a7713b1edbc	1037	}
AnnaBridge	171:3a7713b1edbc	1038
AnnaBridge	171:3a7713b1edbc	1039
AnnaBridge	171:3a7713b1edbc	1040	/**
AnnaBridge	171:3a7713b1edbc	1041	\brief LDR Exclusive (16 bit)
AnnaBridge	171:3a7713b1edbc	1042	\details Executes a exclusive LDR instruction for 16 bit values.
AnnaBridge	171:3a7713b1edbc	1043	\param [in] ptr Pointer to data
AnnaBridge	171:3a7713b1edbc	1044	\return value of type uint16_t at (*ptr)
AnnaBridge	171:3a7713b1edbc	1045	*/
AnnaBridge	171:3a7713b1edbc	1046	__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
AnnaBridge	171:3a7713b1edbc	1047	{
AnnaBridge	171:3a7713b1edbc	1048	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1049
AnnaBridge	171:3a7713b1edbc	1050	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	171:3a7713b1edbc	1051	__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge	171:3a7713b1edbc	1052	#else
AnnaBridge	171:3a7713b1edbc	1053	/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge	171:3a7713b1edbc	1054	accepted by assembler. So has to use following less efficient pattern.
AnnaBridge	171:3a7713b1edbc	1055	*/
AnnaBridge	171:3a7713b1edbc	1056	__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
AnnaBridge	171:3a7713b1edbc	1057	#endif
AnnaBridge	171:3a7713b1edbc	1058	return ((uint16_t) result); /* Add explicit type cast here */
AnnaBridge	171:3a7713b1edbc	1059	}
AnnaBridge	171:3a7713b1edbc	1060
AnnaBridge	171:3a7713b1edbc	1061
AnnaBridge	171:3a7713b1edbc	1062	/**
AnnaBridge	171:3a7713b1edbc	1063	\brief LDR Exclusive (32 bit)
AnnaBridge	171:3a7713b1edbc	1064	\details Executes a exclusive LDR instruction for 32 bit values.
AnnaBridge	171:3a7713b1edbc	1065	\param [in] ptr Pointer to data
AnnaBridge	171:3a7713b1edbc	1066	\return value of type uint32_t at (*ptr)
AnnaBridge	171:3a7713b1edbc	1067	*/
AnnaBridge	171:3a7713b1edbc	1068	__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
AnnaBridge	171:3a7713b1edbc	1069	{
AnnaBridge	171:3a7713b1edbc	1070	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1071
AnnaBridge	171:3a7713b1edbc	1072	__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge	171:3a7713b1edbc	1073	return(result);
AnnaBridge	171:3a7713b1edbc	1074	}
AnnaBridge	171:3a7713b1edbc	1075
AnnaBridge	171:3a7713b1edbc	1076
AnnaBridge	171:3a7713b1edbc	1077	/**
AnnaBridge	171:3a7713b1edbc	1078	\brief STR Exclusive (8 bit)
AnnaBridge	171:3a7713b1edbc	1079	\details Executes a exclusive STR instruction for 8 bit values.
AnnaBridge	171:3a7713b1edbc	1080	\param [in] value Value to store
AnnaBridge	171:3a7713b1edbc	1081	\param [in] ptr Pointer to location
AnnaBridge	171:3a7713b1edbc	1082	\return 0 Function succeeded
AnnaBridge	171:3a7713b1edbc	1083	\return 1 Function failed
AnnaBridge	171:3a7713b1edbc	1084	*/
AnnaBridge	171:3a7713b1edbc	1085	__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
AnnaBridge	171:3a7713b1edbc	1086	{
AnnaBridge	171:3a7713b1edbc	1087	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1088
AnnaBridge	171:3a7713b1edbc	1089	__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
AnnaBridge	171:3a7713b1edbc	1090	return(result);
AnnaBridge	171:3a7713b1edbc	1091	}
AnnaBridge	171:3a7713b1edbc	1092
AnnaBridge	171:3a7713b1edbc	1093
AnnaBridge	171:3a7713b1edbc	1094	/**
AnnaBridge	171:3a7713b1edbc	1095	\brief STR Exclusive (16 bit)
AnnaBridge	171:3a7713b1edbc	1096	\details Executes a exclusive STR instruction for 16 bit values.
AnnaBridge	171:3a7713b1edbc	1097	\param [in] value Value to store
AnnaBridge	171:3a7713b1edbc	1098	\param [in] ptr Pointer to location
AnnaBridge	171:3a7713b1edbc	1099	\return 0 Function succeeded
AnnaBridge	171:3a7713b1edbc	1100	\return 1 Function failed
AnnaBridge	171:3a7713b1edbc	1101	*/
AnnaBridge	171:3a7713b1edbc	1102	__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
AnnaBridge	171:3a7713b1edbc	1103	{
AnnaBridge	171:3a7713b1edbc	1104	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1105
AnnaBridge	171:3a7713b1edbc	1106	__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
AnnaBridge	171:3a7713b1edbc	1107	return(result);
AnnaBridge	171:3a7713b1edbc	1108	}
AnnaBridge	171:3a7713b1edbc	1109
AnnaBridge	171:3a7713b1edbc	1110
AnnaBridge	171:3a7713b1edbc	1111	/**
AnnaBridge	171:3a7713b1edbc	1112	\brief STR Exclusive (32 bit)
AnnaBridge	171:3a7713b1edbc	1113	\details Executes a exclusive STR instruction for 32 bit values.
AnnaBridge	171:3a7713b1edbc	1114	\param [in] value Value to store
AnnaBridge	171:3a7713b1edbc	1115	\param [in] ptr Pointer to location
AnnaBridge	171:3a7713b1edbc	1116	\return 0 Function succeeded
AnnaBridge	171:3a7713b1edbc	1117	\return 1 Function failed
AnnaBridge	171:3a7713b1edbc	1118	*/
AnnaBridge	171:3a7713b1edbc	1119	__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
AnnaBridge	171:3a7713b1edbc	1120	{
AnnaBridge	171:3a7713b1edbc	1121	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1122
AnnaBridge	171:3a7713b1edbc	1123	__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
AnnaBridge	171:3a7713b1edbc	1124	return(result);
AnnaBridge	171:3a7713b1edbc	1125	}
AnnaBridge	171:3a7713b1edbc	1126
AnnaBridge	171:3a7713b1edbc	1127
AnnaBridge	171:3a7713b1edbc	1128	/**
AnnaBridge	171:3a7713b1edbc	1129	\brief Remove the exclusive lock
AnnaBridge	171:3a7713b1edbc	1130	\details Removes the exclusive lock which is created by LDREX.
AnnaBridge	171:3a7713b1edbc	1131	*/
AnnaBridge	171:3a7713b1edbc	1132	__STATIC_FORCEINLINE void __CLREX(void)
AnnaBridge	171:3a7713b1edbc	1133	{
AnnaBridge	171:3a7713b1edbc	1134	__ASM volatile ("clrex" ::: "memory");
AnnaBridge	171:3a7713b1edbc	1135	}
AnnaBridge	171:3a7713b1edbc	1136
AnnaBridge	171:3a7713b1edbc	1137	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	1138	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	1139	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	1140	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge	171:3a7713b1edbc	1141
AnnaBridge	171:3a7713b1edbc	1142
AnnaBridge	171:3a7713b1edbc	1143	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	1144	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	1145	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	171:3a7713b1edbc	1146	/**
AnnaBridge	171:3a7713b1edbc	1147	\brief Signed Saturate
AnnaBridge	171:3a7713b1edbc	1148	\details Saturates a signed value.
AnnaBridge	171:3a7713b1edbc	1149	\param [in] ARG1 Value to be saturated
AnnaBridge	171:3a7713b1edbc	1150	\param [in] ARG2 Bit position to saturate to (1..32)
AnnaBridge	171:3a7713b1edbc	1151	\return Saturated value
AnnaBridge	171:3a7713b1edbc	1152	*/
AnnaBridge	171:3a7713b1edbc	1153	#define __SSAT(ARG1,ARG2) \
AnnaBridge	171:3a7713b1edbc	1154	__extension__ \
AnnaBridge	171:3a7713b1edbc	1155	({ \
AnnaBridge	171:3a7713b1edbc	1156	int32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	171:3a7713b1edbc	1157	__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	171:3a7713b1edbc	1158	__RES; \
AnnaBridge	171:3a7713b1edbc	1159	})
AnnaBridge	171:3a7713b1edbc	1160
AnnaBridge	171:3a7713b1edbc	1161
AnnaBridge	171:3a7713b1edbc	1162	/**
AnnaBridge	171:3a7713b1edbc	1163	\brief Unsigned Saturate
AnnaBridge	171:3a7713b1edbc	1164	\details Saturates an unsigned value.
AnnaBridge	171:3a7713b1edbc	1165	\param [in] ARG1 Value to be saturated
AnnaBridge	171:3a7713b1edbc	1166	\param [in] ARG2 Bit position to saturate to (0..31)
AnnaBridge	171:3a7713b1edbc	1167	\return Saturated value
AnnaBridge	171:3a7713b1edbc	1168	*/
AnnaBridge	171:3a7713b1edbc	1169	#define __USAT(ARG1,ARG2) \
AnnaBridge	171:3a7713b1edbc	1170	__extension__ \
AnnaBridge	171:3a7713b1edbc	1171	({ \
AnnaBridge	171:3a7713b1edbc	1172	uint32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	171:3a7713b1edbc	1173	__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	171:3a7713b1edbc	1174	__RES; \
AnnaBridge	171:3a7713b1edbc	1175	})
AnnaBridge	171:3a7713b1edbc	1176
AnnaBridge	171:3a7713b1edbc	1177
AnnaBridge	171:3a7713b1edbc	1178	/**
AnnaBridge	171:3a7713b1edbc	1179	\brief Rotate Right with Extend (32 bit)
AnnaBridge	171:3a7713b1edbc	1180	\details Moves each bit of a bitstring right by one bit.
AnnaBridge	171:3a7713b1edbc	1181	The carry input is shifted in at the left end of the bitstring.
AnnaBridge	171:3a7713b1edbc	1182	\param [in] value Value to rotate
AnnaBridge	171:3a7713b1edbc	1183	\return Rotated value
AnnaBridge	171:3a7713b1edbc	1184	*/
AnnaBridge	171:3a7713b1edbc	1185	__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
AnnaBridge	171:3a7713b1edbc	1186	{
AnnaBridge	171:3a7713b1edbc	1187	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1188
AnnaBridge	171:3a7713b1edbc	1189	__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge	171:3a7713b1edbc	1190	return(result);
AnnaBridge	171:3a7713b1edbc	1191	}
AnnaBridge	171:3a7713b1edbc	1192
AnnaBridge	171:3a7713b1edbc	1193
AnnaBridge	171:3a7713b1edbc	1194	/**
AnnaBridge	171:3a7713b1edbc	1195	\brief LDRT Unprivileged (8 bit)
AnnaBridge	171:3a7713b1edbc	1196	\details Executes a Unprivileged LDRT instruction for 8 bit value.
AnnaBridge	171:3a7713b1edbc	1197	\param [in] ptr Pointer to data
AnnaBridge	171:3a7713b1edbc	1198	\return value of type uint8_t at (*ptr)
AnnaBridge	171:3a7713b1edbc	1199	*/
AnnaBridge	171:3a7713b1edbc	1200	__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
AnnaBridge	171:3a7713b1edbc	1201	{
AnnaBridge	171:3a7713b1edbc	1202	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1203
AnnaBridge	171:3a7713b1edbc	1204	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	171:3a7713b1edbc	1205	__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	171:3a7713b1edbc	1206	#else
AnnaBridge	171:3a7713b1edbc	1207	/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge	171:3a7713b1edbc	1208	accepted by assembler. So has to use following less efficient pattern.
AnnaBridge	171:3a7713b1edbc	1209	*/
AnnaBridge	171:3a7713b1edbc	1210	__ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
AnnaBridge	171:3a7713b1edbc	1211	#endif
AnnaBridge	171:3a7713b1edbc	1212	return ((uint8_t) result); /* Add explicit type cast here */
AnnaBridge	171:3a7713b1edbc	1213	}
AnnaBridge	171:3a7713b1edbc	1214
AnnaBridge	171:3a7713b1edbc	1215
AnnaBridge	171:3a7713b1edbc	1216	/**
AnnaBridge	171:3a7713b1edbc	1217	\brief LDRT Unprivileged (16 bit)
AnnaBridge	171:3a7713b1edbc	1218	\details Executes a Unprivileged LDRT instruction for 16 bit values.
AnnaBridge	171:3a7713b1edbc	1219	\param [in] ptr Pointer to data
AnnaBridge	171:3a7713b1edbc	1220	\return value of type uint16_t at (*ptr)
AnnaBridge	171:3a7713b1edbc	1221	*/
AnnaBridge	171:3a7713b1edbc	1222	__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
AnnaBridge	171:3a7713b1edbc	1223	{
AnnaBridge	171:3a7713b1edbc	1224	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1225
AnnaBridge	171:3a7713b1edbc	1226	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	171:3a7713b1edbc	1227	__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	171:3a7713b1edbc	1228	#else
AnnaBridge	171:3a7713b1edbc	1229	/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge	171:3a7713b1edbc	1230	accepted by assembler. So has to use following less efficient pattern.
AnnaBridge	171:3a7713b1edbc	1231	*/
AnnaBridge	171:3a7713b1edbc	1232	__ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
AnnaBridge	171:3a7713b1edbc	1233	#endif
AnnaBridge	171:3a7713b1edbc	1234	return ((uint16_t) result); /* Add explicit type cast here */
AnnaBridge	171:3a7713b1edbc	1235	}
AnnaBridge	171:3a7713b1edbc	1236
AnnaBridge	171:3a7713b1edbc	1237
AnnaBridge	171:3a7713b1edbc	1238	/**
AnnaBridge	171:3a7713b1edbc	1239	\brief LDRT Unprivileged (32 bit)
AnnaBridge	171:3a7713b1edbc	1240	\details Executes a Unprivileged LDRT instruction for 32 bit values.
AnnaBridge	171:3a7713b1edbc	1241	\param [in] ptr Pointer to data
AnnaBridge	171:3a7713b1edbc	1242	\return value of type uint32_t at (*ptr)
AnnaBridge	171:3a7713b1edbc	1243	*/
AnnaBridge	171:3a7713b1edbc	1244	__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
AnnaBridge	171:3a7713b1edbc	1245	{
AnnaBridge	171:3a7713b1edbc	1246	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1247
AnnaBridge	171:3a7713b1edbc	1248	__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	171:3a7713b1edbc	1249	return(result);
AnnaBridge	171:3a7713b1edbc	1250	}
AnnaBridge	171:3a7713b1edbc	1251
AnnaBridge	171:3a7713b1edbc	1252
AnnaBridge	171:3a7713b1edbc	1253	/**
AnnaBridge	171:3a7713b1edbc	1254	\brief STRT Unprivileged (8 bit)
AnnaBridge	171:3a7713b1edbc	1255	\details Executes a Unprivileged STRT instruction for 8 bit values.
AnnaBridge	171:3a7713b1edbc	1256	\param [in] value Value to store
AnnaBridge	171:3a7713b1edbc	1257	\param [in] ptr Pointer to location
AnnaBridge	171:3a7713b1edbc	1258	*/
AnnaBridge	171:3a7713b1edbc	1259	__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
AnnaBridge	171:3a7713b1edbc	1260	{
AnnaBridge	171:3a7713b1edbc	1261	__ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	171:3a7713b1edbc	1262	}
AnnaBridge	171:3a7713b1edbc	1263
AnnaBridge	171:3a7713b1edbc	1264
AnnaBridge	171:3a7713b1edbc	1265	/**
AnnaBridge	171:3a7713b1edbc	1266	\brief STRT Unprivileged (16 bit)
AnnaBridge	171:3a7713b1edbc	1267	\details Executes a Unprivileged STRT instruction for 16 bit values.
AnnaBridge	171:3a7713b1edbc	1268	\param [in] value Value to store
AnnaBridge	171:3a7713b1edbc	1269	\param [in] ptr Pointer to location
AnnaBridge	171:3a7713b1edbc	1270	*/
AnnaBridge	171:3a7713b1edbc	1271	__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
AnnaBridge	171:3a7713b1edbc	1272	{
AnnaBridge	171:3a7713b1edbc	1273	__ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	171:3a7713b1edbc	1274	}
AnnaBridge	171:3a7713b1edbc	1275
AnnaBridge	171:3a7713b1edbc	1276
AnnaBridge	171:3a7713b1edbc	1277	/**
AnnaBridge	171:3a7713b1edbc	1278	\brief STRT Unprivileged (32 bit)
AnnaBridge	171:3a7713b1edbc	1279	\details Executes a Unprivileged STRT instruction for 32 bit values.
AnnaBridge	171:3a7713b1edbc	1280	\param [in] value Value to store
AnnaBridge	171:3a7713b1edbc	1281	\param [in] ptr Pointer to location
AnnaBridge	171:3a7713b1edbc	1282	*/
AnnaBridge	171:3a7713b1edbc	1283	__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
AnnaBridge	171:3a7713b1edbc	1284	{
AnnaBridge	171:3a7713b1edbc	1285	__ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
AnnaBridge	171:3a7713b1edbc	1286	}
AnnaBridge	171:3a7713b1edbc	1287
AnnaBridge	171:3a7713b1edbc	1288	#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	1289	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	1290	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge	171:3a7713b1edbc	1291
AnnaBridge	171:3a7713b1edbc	1292	/**
AnnaBridge	171:3a7713b1edbc	1293	\brief Signed Saturate
AnnaBridge	171:3a7713b1edbc	1294	\details Saturates a signed value.
AnnaBridge	171:3a7713b1edbc	1295	\param [in] value Value to be saturated
AnnaBridge	171:3a7713b1edbc	1296	\param [in] sat Bit position to saturate to (1..32)
AnnaBridge	171:3a7713b1edbc	1297	\return Saturated value
AnnaBridge	171:3a7713b1edbc	1298	*/
AnnaBridge	171:3a7713b1edbc	1299	__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
AnnaBridge	171:3a7713b1edbc	1300	{
AnnaBridge	171:3a7713b1edbc	1301	if ((sat >= 1U) && (sat <= 32U))
AnnaBridge	171:3a7713b1edbc	1302	{
AnnaBridge	171:3a7713b1edbc	1303	const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
AnnaBridge	171:3a7713b1edbc	1304	const int32_t min = -1 - max ;
AnnaBridge	171:3a7713b1edbc	1305	if (val > max)
AnnaBridge	171:3a7713b1edbc	1306	{
AnnaBridge	171:3a7713b1edbc	1307	return max;
AnnaBridge	171:3a7713b1edbc	1308	}
AnnaBridge	171:3a7713b1edbc	1309	else if (val < min)
AnnaBridge	171:3a7713b1edbc	1310	{
AnnaBridge	171:3a7713b1edbc	1311	return min;
AnnaBridge	171:3a7713b1edbc	1312	}
AnnaBridge	171:3a7713b1edbc	1313	}
AnnaBridge	171:3a7713b1edbc	1314	return val;
AnnaBridge	171:3a7713b1edbc	1315	}
AnnaBridge	171:3a7713b1edbc	1316
AnnaBridge	171:3a7713b1edbc	1317	/**
AnnaBridge	171:3a7713b1edbc	1318	\brief Unsigned Saturate
AnnaBridge	171:3a7713b1edbc	1319	\details Saturates an unsigned value.
AnnaBridge	171:3a7713b1edbc	1320	\param [in] value Value to be saturated
AnnaBridge	171:3a7713b1edbc	1321	\param [in] sat Bit position to saturate to (0..31)
AnnaBridge	171:3a7713b1edbc	1322	\return Saturated value
AnnaBridge	171:3a7713b1edbc	1323	*/
AnnaBridge	171:3a7713b1edbc	1324	__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
AnnaBridge	171:3a7713b1edbc	1325	{
AnnaBridge	171:3a7713b1edbc	1326	if (sat <= 31U)
AnnaBridge	171:3a7713b1edbc	1327	{
AnnaBridge	171:3a7713b1edbc	1328	const uint32_t max = ((1U << sat) - 1U);
AnnaBridge	171:3a7713b1edbc	1329	if (val > (int32_t)max)
AnnaBridge	171:3a7713b1edbc	1330	{
AnnaBridge	171:3a7713b1edbc	1331	return max;
AnnaBridge	171:3a7713b1edbc	1332	}
AnnaBridge	171:3a7713b1edbc	1333	else if (val < 0)
AnnaBridge	171:3a7713b1edbc	1334	{
AnnaBridge	171:3a7713b1edbc	1335	return 0U;
AnnaBridge	171:3a7713b1edbc	1336	}
AnnaBridge	171:3a7713b1edbc	1337	}
AnnaBridge	171:3a7713b1edbc	1338	return (uint32_t)val;
AnnaBridge	171:3a7713b1edbc	1339	}
AnnaBridge	171:3a7713b1edbc	1340
AnnaBridge	171:3a7713b1edbc	1341	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	1342	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	1343	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge	171:3a7713b1edbc	1344
AnnaBridge	171:3a7713b1edbc	1345
AnnaBridge	171:3a7713b1edbc	1346	#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	1347	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge	171:3a7713b1edbc	1348	/**
AnnaBridge	171:3a7713b1edbc	1349	\brief Load-Acquire (8 bit)
AnnaBridge	171:3a7713b1edbc	1350	\details Executes a LDAB instruction for 8 bit value.
AnnaBridge	171:3a7713b1edbc	1351	\param [in] ptr Pointer to data
AnnaBridge	171:3a7713b1edbc	1352	\return value of type uint8_t at (*ptr)
AnnaBridge	171:3a7713b1edbc	1353	*/
AnnaBridge	171:3a7713b1edbc	1354	__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
AnnaBridge	171:3a7713b1edbc	1355	{
AnnaBridge	171:3a7713b1edbc	1356	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1357
AnnaBridge	171:3a7713b1edbc	1358	__ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	171:3a7713b1edbc	1359	return ((uint8_t) result);
AnnaBridge	171:3a7713b1edbc	1360	}
AnnaBridge	171:3a7713b1edbc	1361
AnnaBridge	171:3a7713b1edbc	1362
AnnaBridge	171:3a7713b1edbc	1363	/**
AnnaBridge	171:3a7713b1edbc	1364	\brief Load-Acquire (16 bit)
AnnaBridge	171:3a7713b1edbc	1365	\details Executes a LDAH instruction for 16 bit values.
AnnaBridge	171:3a7713b1edbc	1366	\param [in] ptr Pointer to data
AnnaBridge	171:3a7713b1edbc	1367	\return value of type uint16_t at (*ptr)
AnnaBridge	171:3a7713b1edbc	1368	*/
AnnaBridge	171:3a7713b1edbc	1369	__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
AnnaBridge	171:3a7713b1edbc	1370	{
AnnaBridge	171:3a7713b1edbc	1371	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1372
AnnaBridge	171:3a7713b1edbc	1373	__ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	171:3a7713b1edbc	1374	return ((uint16_t) result);
AnnaBridge	171:3a7713b1edbc	1375	}
AnnaBridge	171:3a7713b1edbc	1376
AnnaBridge	171:3a7713b1edbc	1377
AnnaBridge	171:3a7713b1edbc	1378	/**
AnnaBridge	171:3a7713b1edbc	1379	\brief Load-Acquire (32 bit)
AnnaBridge	171:3a7713b1edbc	1380	\details Executes a LDA instruction for 32 bit values.
AnnaBridge	171:3a7713b1edbc	1381	\param [in] ptr Pointer to data
AnnaBridge	171:3a7713b1edbc	1382	\return value of type uint32_t at (*ptr)
AnnaBridge	171:3a7713b1edbc	1383	*/
AnnaBridge	171:3a7713b1edbc	1384	__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
AnnaBridge	171:3a7713b1edbc	1385	{
AnnaBridge	171:3a7713b1edbc	1386	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1387
AnnaBridge	171:3a7713b1edbc	1388	__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	171:3a7713b1edbc	1389	return(result);
AnnaBridge	171:3a7713b1edbc	1390	}
AnnaBridge	171:3a7713b1edbc	1391
AnnaBridge	171:3a7713b1edbc	1392
AnnaBridge	171:3a7713b1edbc	1393	/**
AnnaBridge	171:3a7713b1edbc	1394	\brief Store-Release (8 bit)
AnnaBridge	171:3a7713b1edbc	1395	\details Executes a STLB instruction for 8 bit values.
AnnaBridge	171:3a7713b1edbc	1396	\param [in] value Value to store
AnnaBridge	171:3a7713b1edbc	1397	\param [in] ptr Pointer to location
AnnaBridge	171:3a7713b1edbc	1398	*/
AnnaBridge	171:3a7713b1edbc	1399	__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
AnnaBridge	171:3a7713b1edbc	1400	{
AnnaBridge	171:3a7713b1edbc	1401	__ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	171:3a7713b1edbc	1402	}
AnnaBridge	171:3a7713b1edbc	1403
AnnaBridge	171:3a7713b1edbc	1404
AnnaBridge	171:3a7713b1edbc	1405	/**
AnnaBridge	171:3a7713b1edbc	1406	\brief Store-Release (16 bit)
AnnaBridge	171:3a7713b1edbc	1407	\details Executes a STLH instruction for 16 bit values.
AnnaBridge	171:3a7713b1edbc	1408	\param [in] value Value to store
AnnaBridge	171:3a7713b1edbc	1409	\param [in] ptr Pointer to location
AnnaBridge	171:3a7713b1edbc	1410	*/
AnnaBridge	171:3a7713b1edbc	1411	__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
AnnaBridge	171:3a7713b1edbc	1412	{
AnnaBridge	171:3a7713b1edbc	1413	__ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	171:3a7713b1edbc	1414	}
AnnaBridge	171:3a7713b1edbc	1415
AnnaBridge	171:3a7713b1edbc	1416
AnnaBridge	171:3a7713b1edbc	1417	/**
AnnaBridge	171:3a7713b1edbc	1418	\brief Store-Release (32 bit)
AnnaBridge	171:3a7713b1edbc	1419	\details Executes a STL instruction for 32 bit values.
AnnaBridge	171:3a7713b1edbc	1420	\param [in] value Value to store
AnnaBridge	171:3a7713b1edbc	1421	\param [in] ptr Pointer to location
AnnaBridge	171:3a7713b1edbc	1422	*/
AnnaBridge	171:3a7713b1edbc	1423	__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
AnnaBridge	171:3a7713b1edbc	1424	{
AnnaBridge	171:3a7713b1edbc	1425	__ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	171:3a7713b1edbc	1426	}
AnnaBridge	171:3a7713b1edbc	1427
AnnaBridge	171:3a7713b1edbc	1428
AnnaBridge	171:3a7713b1edbc	1429	/**
AnnaBridge	171:3a7713b1edbc	1430	\brief Load-Acquire Exclusive (8 bit)
AnnaBridge	171:3a7713b1edbc	1431	\details Executes a LDAB exclusive instruction for 8 bit value.
AnnaBridge	171:3a7713b1edbc	1432	\param [in] ptr Pointer to data
AnnaBridge	171:3a7713b1edbc	1433	\return value of type uint8_t at (*ptr)
AnnaBridge	171:3a7713b1edbc	1434	*/
AnnaBridge	171:3a7713b1edbc	1435	__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
AnnaBridge	171:3a7713b1edbc	1436	{
AnnaBridge	171:3a7713b1edbc	1437	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1438
AnnaBridge	171:3a7713b1edbc	1439	__ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	171:3a7713b1edbc	1440	return ((uint8_t) result);
AnnaBridge	171:3a7713b1edbc	1441	}
AnnaBridge	171:3a7713b1edbc	1442
AnnaBridge	171:3a7713b1edbc	1443
AnnaBridge	171:3a7713b1edbc	1444	/**
AnnaBridge	171:3a7713b1edbc	1445	\brief Load-Acquire Exclusive (16 bit)
AnnaBridge	171:3a7713b1edbc	1446	\details Executes a LDAH exclusive instruction for 16 bit values.
AnnaBridge	171:3a7713b1edbc	1447	\param [in] ptr Pointer to data
AnnaBridge	171:3a7713b1edbc	1448	\return value of type uint16_t at (*ptr)
AnnaBridge	171:3a7713b1edbc	1449	*/
AnnaBridge	171:3a7713b1edbc	1450	__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
AnnaBridge	171:3a7713b1edbc	1451	{
AnnaBridge	171:3a7713b1edbc	1452	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1453
AnnaBridge	171:3a7713b1edbc	1454	__ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	171:3a7713b1edbc	1455	return ((uint16_t) result);
AnnaBridge	171:3a7713b1edbc	1456	}
AnnaBridge	171:3a7713b1edbc	1457
AnnaBridge	171:3a7713b1edbc	1458
AnnaBridge	171:3a7713b1edbc	1459	/**
AnnaBridge	171:3a7713b1edbc	1460	\brief Load-Acquire Exclusive (32 bit)
AnnaBridge	171:3a7713b1edbc	1461	\details Executes a LDA exclusive instruction for 32 bit values.
AnnaBridge	171:3a7713b1edbc	1462	\param [in] ptr Pointer to data
AnnaBridge	171:3a7713b1edbc	1463	\return value of type uint32_t at (*ptr)
AnnaBridge	171:3a7713b1edbc	1464	*/
AnnaBridge	171:3a7713b1edbc	1465	__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
AnnaBridge	171:3a7713b1edbc	1466	{
AnnaBridge	171:3a7713b1edbc	1467	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1468
AnnaBridge	171:3a7713b1edbc	1469	__ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	171:3a7713b1edbc	1470	return(result);
AnnaBridge	171:3a7713b1edbc	1471	}
AnnaBridge	171:3a7713b1edbc	1472
AnnaBridge	171:3a7713b1edbc	1473
AnnaBridge	171:3a7713b1edbc	1474	/**
AnnaBridge	171:3a7713b1edbc	1475	\brief Store-Release Exclusive (8 bit)
AnnaBridge	171:3a7713b1edbc	1476	\details Executes a STLB exclusive instruction for 8 bit values.
AnnaBridge	171:3a7713b1edbc	1477	\param [in] value Value to store
AnnaBridge	171:3a7713b1edbc	1478	\param [in] ptr Pointer to location
AnnaBridge	171:3a7713b1edbc	1479	\return 0 Function succeeded
AnnaBridge	171:3a7713b1edbc	1480	\return 1 Function failed
AnnaBridge	171:3a7713b1edbc	1481	*/
AnnaBridge	171:3a7713b1edbc	1482	__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
AnnaBridge	171:3a7713b1edbc	1483	{
AnnaBridge	171:3a7713b1edbc	1484	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1485
AnnaBridge	171:3a7713b1edbc	1486	__ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	171:3a7713b1edbc	1487	return(result);
AnnaBridge	171:3a7713b1edbc	1488	}
AnnaBridge	171:3a7713b1edbc	1489
AnnaBridge	171:3a7713b1edbc	1490
AnnaBridge	171:3a7713b1edbc	1491	/**
AnnaBridge	171:3a7713b1edbc	1492	\brief Store-Release Exclusive (16 bit)
AnnaBridge	171:3a7713b1edbc	1493	\details Executes a STLH exclusive instruction for 16 bit values.
AnnaBridge	171:3a7713b1edbc	1494	\param [in] value Value to store
AnnaBridge	171:3a7713b1edbc	1495	\param [in] ptr Pointer to location
AnnaBridge	171:3a7713b1edbc	1496	\return 0 Function succeeded
AnnaBridge	171:3a7713b1edbc	1497	\return 1 Function failed
AnnaBridge	171:3a7713b1edbc	1498	*/
AnnaBridge	171:3a7713b1edbc	1499	__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
AnnaBridge	171:3a7713b1edbc	1500	{
AnnaBridge	171:3a7713b1edbc	1501	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1502
AnnaBridge	171:3a7713b1edbc	1503	__ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	171:3a7713b1edbc	1504	return(result);
AnnaBridge	171:3a7713b1edbc	1505	}
AnnaBridge	171:3a7713b1edbc	1506
AnnaBridge	171:3a7713b1edbc	1507
AnnaBridge	171:3a7713b1edbc	1508	/**
AnnaBridge	171:3a7713b1edbc	1509	\brief Store-Release Exclusive (32 bit)
AnnaBridge	171:3a7713b1edbc	1510	\details Executes a STL exclusive instruction for 32 bit values.
AnnaBridge	171:3a7713b1edbc	1511	\param [in] value Value to store
AnnaBridge	171:3a7713b1edbc	1512	\param [in] ptr Pointer to location
AnnaBridge	171:3a7713b1edbc	1513	\return 0 Function succeeded
AnnaBridge	171:3a7713b1edbc	1514	\return 1 Function failed
AnnaBridge	171:3a7713b1edbc	1515	*/
AnnaBridge	171:3a7713b1edbc	1516	__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
AnnaBridge	171:3a7713b1edbc	1517	{
AnnaBridge	171:3a7713b1edbc	1518	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1519
AnnaBridge	171:3a7713b1edbc	1520	__ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	171:3a7713b1edbc	1521	return(result);
AnnaBridge	171:3a7713b1edbc	1522	}
AnnaBridge	171:3a7713b1edbc	1523
AnnaBridge	171:3a7713b1edbc	1524	#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	171:3a7713b1edbc	1525	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge	171:3a7713b1edbc	1526
AnnaBridge	171:3a7713b1edbc	1527	/@}/ /* end of group CMSIS_Core_InstructionInterface */
AnnaBridge	171:3a7713b1edbc	1528
AnnaBridge	171:3a7713b1edbc	1529
AnnaBridge	171:3a7713b1edbc	1530	/* ################### Compiler specific Intrinsics ########################### */
AnnaBridge	171:3a7713b1edbc	1531	/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
AnnaBridge	171:3a7713b1edbc	1532	Access to dedicated SIMD instructions
AnnaBridge	171:3a7713b1edbc	1533	@{
AnnaBridge	171:3a7713b1edbc	1534	*/
AnnaBridge	171:3a7713b1edbc	1535
AnnaBridge	171:3a7713b1edbc	1536	#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
AnnaBridge	171:3a7713b1edbc	1537
AnnaBridge	171:3a7713b1edbc	1538	__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1539	{
AnnaBridge	171:3a7713b1edbc	1540	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1541
AnnaBridge	171:3a7713b1edbc	1542	__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1543	return(result);
AnnaBridge	171:3a7713b1edbc	1544	}
AnnaBridge	171:3a7713b1edbc	1545
AnnaBridge	171:3a7713b1edbc	1546	__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1547	{
AnnaBridge	171:3a7713b1edbc	1548	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1549
AnnaBridge	171:3a7713b1edbc	1550	__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1551	return(result);
AnnaBridge	171:3a7713b1edbc	1552	}
AnnaBridge	171:3a7713b1edbc	1553
AnnaBridge	171:3a7713b1edbc	1554	__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1555	{
AnnaBridge	171:3a7713b1edbc	1556	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1557
AnnaBridge	171:3a7713b1edbc	1558	__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1559	return(result);
AnnaBridge	171:3a7713b1edbc	1560	}
AnnaBridge	171:3a7713b1edbc	1561
AnnaBridge	171:3a7713b1edbc	1562	__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1563	{
AnnaBridge	171:3a7713b1edbc	1564	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1565
AnnaBridge	171:3a7713b1edbc	1566	__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1567	return(result);
AnnaBridge	171:3a7713b1edbc	1568	}
AnnaBridge	171:3a7713b1edbc	1569
AnnaBridge	171:3a7713b1edbc	1570	__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1571	{
AnnaBridge	171:3a7713b1edbc	1572	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1573
AnnaBridge	171:3a7713b1edbc	1574	__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1575	return(result);
AnnaBridge	171:3a7713b1edbc	1576	}
AnnaBridge	171:3a7713b1edbc	1577
AnnaBridge	171:3a7713b1edbc	1578	__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1579	{
AnnaBridge	171:3a7713b1edbc	1580	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1581
AnnaBridge	171:3a7713b1edbc	1582	__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1583	return(result);
AnnaBridge	171:3a7713b1edbc	1584	}
AnnaBridge	171:3a7713b1edbc	1585
AnnaBridge	171:3a7713b1edbc	1586
AnnaBridge	171:3a7713b1edbc	1587	__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1588	{
AnnaBridge	171:3a7713b1edbc	1589	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1590
AnnaBridge	171:3a7713b1edbc	1591	__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1592	return(result);
AnnaBridge	171:3a7713b1edbc	1593	}
AnnaBridge	171:3a7713b1edbc	1594
AnnaBridge	171:3a7713b1edbc	1595	__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1596	{
AnnaBridge	171:3a7713b1edbc	1597	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1598
AnnaBridge	171:3a7713b1edbc	1599	__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1600	return(result);
AnnaBridge	171:3a7713b1edbc	1601	}
AnnaBridge	171:3a7713b1edbc	1602
AnnaBridge	171:3a7713b1edbc	1603	__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1604	{
AnnaBridge	171:3a7713b1edbc	1605	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1606
AnnaBridge	171:3a7713b1edbc	1607	__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1608	return(result);
AnnaBridge	171:3a7713b1edbc	1609	}
AnnaBridge	171:3a7713b1edbc	1610
AnnaBridge	171:3a7713b1edbc	1611	__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1612	{
AnnaBridge	171:3a7713b1edbc	1613	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1614
AnnaBridge	171:3a7713b1edbc	1615	__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1616	return(result);
AnnaBridge	171:3a7713b1edbc	1617	}
AnnaBridge	171:3a7713b1edbc	1618
AnnaBridge	171:3a7713b1edbc	1619	__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1620	{
AnnaBridge	171:3a7713b1edbc	1621	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1622
AnnaBridge	171:3a7713b1edbc	1623	__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1624	return(result);
AnnaBridge	171:3a7713b1edbc	1625	}
AnnaBridge	171:3a7713b1edbc	1626
AnnaBridge	171:3a7713b1edbc	1627	__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1628	{
AnnaBridge	171:3a7713b1edbc	1629	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1630
AnnaBridge	171:3a7713b1edbc	1631	__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1632	return(result);
AnnaBridge	171:3a7713b1edbc	1633	}
AnnaBridge	171:3a7713b1edbc	1634
AnnaBridge	171:3a7713b1edbc	1635
AnnaBridge	171:3a7713b1edbc	1636	__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1637	{
AnnaBridge	171:3a7713b1edbc	1638	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1639
AnnaBridge	171:3a7713b1edbc	1640	__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1641	return(result);
AnnaBridge	171:3a7713b1edbc	1642	}
AnnaBridge	171:3a7713b1edbc	1643
AnnaBridge	171:3a7713b1edbc	1644	__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1645	{
AnnaBridge	171:3a7713b1edbc	1646	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1647
AnnaBridge	171:3a7713b1edbc	1648	__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1649	return(result);
AnnaBridge	171:3a7713b1edbc	1650	}
AnnaBridge	171:3a7713b1edbc	1651
AnnaBridge	171:3a7713b1edbc	1652	__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1653	{
AnnaBridge	171:3a7713b1edbc	1654	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1655
AnnaBridge	171:3a7713b1edbc	1656	__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1657	return(result);
AnnaBridge	171:3a7713b1edbc	1658	}
AnnaBridge	171:3a7713b1edbc	1659
AnnaBridge	171:3a7713b1edbc	1660	__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1661	{
AnnaBridge	171:3a7713b1edbc	1662	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1663
AnnaBridge	171:3a7713b1edbc	1664	__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1665	return(result);
AnnaBridge	171:3a7713b1edbc	1666	}
AnnaBridge	171:3a7713b1edbc	1667
AnnaBridge	171:3a7713b1edbc	1668	__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1669	{
AnnaBridge	171:3a7713b1edbc	1670	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1671
AnnaBridge	171:3a7713b1edbc	1672	__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1673	return(result);
AnnaBridge	171:3a7713b1edbc	1674	}
AnnaBridge	171:3a7713b1edbc	1675
AnnaBridge	171:3a7713b1edbc	1676	__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1677	{
AnnaBridge	171:3a7713b1edbc	1678	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1679
AnnaBridge	171:3a7713b1edbc	1680	__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1681	return(result);
AnnaBridge	171:3a7713b1edbc	1682	}
AnnaBridge	171:3a7713b1edbc	1683
AnnaBridge	171:3a7713b1edbc	1684	__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1685	{
AnnaBridge	171:3a7713b1edbc	1686	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1687
AnnaBridge	171:3a7713b1edbc	1688	__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1689	return(result);
AnnaBridge	171:3a7713b1edbc	1690	}
AnnaBridge	171:3a7713b1edbc	1691
AnnaBridge	171:3a7713b1edbc	1692	__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1693	{
AnnaBridge	171:3a7713b1edbc	1694	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1695
AnnaBridge	171:3a7713b1edbc	1696	__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1697	return(result);
AnnaBridge	171:3a7713b1edbc	1698	}
AnnaBridge	171:3a7713b1edbc	1699
AnnaBridge	171:3a7713b1edbc	1700	__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1701	{
AnnaBridge	171:3a7713b1edbc	1702	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1703
AnnaBridge	171:3a7713b1edbc	1704	__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1705	return(result);
AnnaBridge	171:3a7713b1edbc	1706	}
AnnaBridge	171:3a7713b1edbc	1707
AnnaBridge	171:3a7713b1edbc	1708	__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1709	{
AnnaBridge	171:3a7713b1edbc	1710	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1711
AnnaBridge	171:3a7713b1edbc	1712	__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1713	return(result);
AnnaBridge	171:3a7713b1edbc	1714	}
AnnaBridge	171:3a7713b1edbc	1715
AnnaBridge	171:3a7713b1edbc	1716	__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1717	{
AnnaBridge	171:3a7713b1edbc	1718	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1719
AnnaBridge	171:3a7713b1edbc	1720	__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1721	return(result);
AnnaBridge	171:3a7713b1edbc	1722	}
AnnaBridge	171:3a7713b1edbc	1723
AnnaBridge	171:3a7713b1edbc	1724	__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1725	{
AnnaBridge	171:3a7713b1edbc	1726	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1727
AnnaBridge	171:3a7713b1edbc	1728	__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1729	return(result);
AnnaBridge	171:3a7713b1edbc	1730	}
AnnaBridge	171:3a7713b1edbc	1731
AnnaBridge	171:3a7713b1edbc	1732	__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1733	{
AnnaBridge	171:3a7713b1edbc	1734	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1735
AnnaBridge	171:3a7713b1edbc	1736	__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1737	return(result);
AnnaBridge	171:3a7713b1edbc	1738	}
AnnaBridge	171:3a7713b1edbc	1739
AnnaBridge	171:3a7713b1edbc	1740	__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1741	{
AnnaBridge	171:3a7713b1edbc	1742	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1743
AnnaBridge	171:3a7713b1edbc	1744	__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1745	return(result);
AnnaBridge	171:3a7713b1edbc	1746	}
AnnaBridge	171:3a7713b1edbc	1747
AnnaBridge	171:3a7713b1edbc	1748	__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1749	{
AnnaBridge	171:3a7713b1edbc	1750	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1751
AnnaBridge	171:3a7713b1edbc	1752	__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1753	return(result);
AnnaBridge	171:3a7713b1edbc	1754	}
AnnaBridge	171:3a7713b1edbc	1755
AnnaBridge	171:3a7713b1edbc	1756	__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1757	{
AnnaBridge	171:3a7713b1edbc	1758	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1759
AnnaBridge	171:3a7713b1edbc	1760	__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1761	return(result);
AnnaBridge	171:3a7713b1edbc	1762	}
AnnaBridge	171:3a7713b1edbc	1763
AnnaBridge	171:3a7713b1edbc	1764	__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1765	{
AnnaBridge	171:3a7713b1edbc	1766	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1767
AnnaBridge	171:3a7713b1edbc	1768	__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1769	return(result);
AnnaBridge	171:3a7713b1edbc	1770	}
AnnaBridge	171:3a7713b1edbc	1771
AnnaBridge	171:3a7713b1edbc	1772	__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1773	{
AnnaBridge	171:3a7713b1edbc	1774	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1775
AnnaBridge	171:3a7713b1edbc	1776	__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1777	return(result);
AnnaBridge	171:3a7713b1edbc	1778	}
AnnaBridge	171:3a7713b1edbc	1779
AnnaBridge	171:3a7713b1edbc	1780	__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1781	{
AnnaBridge	171:3a7713b1edbc	1782	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1783
AnnaBridge	171:3a7713b1edbc	1784	__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1785	return(result);
AnnaBridge	171:3a7713b1edbc	1786	}
AnnaBridge	171:3a7713b1edbc	1787
AnnaBridge	171:3a7713b1edbc	1788	__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1789	{
AnnaBridge	171:3a7713b1edbc	1790	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1791
AnnaBridge	171:3a7713b1edbc	1792	__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1793	return(result);
AnnaBridge	171:3a7713b1edbc	1794	}
AnnaBridge	171:3a7713b1edbc	1795
AnnaBridge	171:3a7713b1edbc	1796	__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1797	{
AnnaBridge	171:3a7713b1edbc	1798	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1799
AnnaBridge	171:3a7713b1edbc	1800	__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1801	return(result);
AnnaBridge	171:3a7713b1edbc	1802	}
AnnaBridge	171:3a7713b1edbc	1803
AnnaBridge	171:3a7713b1edbc	1804	__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1805	{
AnnaBridge	171:3a7713b1edbc	1806	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1807
AnnaBridge	171:3a7713b1edbc	1808	__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1809	return(result);
AnnaBridge	171:3a7713b1edbc	1810	}
AnnaBridge	171:3a7713b1edbc	1811
AnnaBridge	171:3a7713b1edbc	1812	__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1813	{
AnnaBridge	171:3a7713b1edbc	1814	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1815
AnnaBridge	171:3a7713b1edbc	1816	__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1817	return(result);
AnnaBridge	171:3a7713b1edbc	1818	}
AnnaBridge	171:3a7713b1edbc	1819
AnnaBridge	171:3a7713b1edbc	1820	__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1821	{
AnnaBridge	171:3a7713b1edbc	1822	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1823
AnnaBridge	171:3a7713b1edbc	1824	__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1825	return(result);
AnnaBridge	171:3a7713b1edbc	1826	}
AnnaBridge	171:3a7713b1edbc	1827
AnnaBridge	171:3a7713b1edbc	1828	__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1829	{
AnnaBridge	171:3a7713b1edbc	1830	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1831
AnnaBridge	171:3a7713b1edbc	1832	__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1833	return(result);
AnnaBridge	171:3a7713b1edbc	1834	}
AnnaBridge	171:3a7713b1edbc	1835
AnnaBridge	171:3a7713b1edbc	1836	__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	171:3a7713b1edbc	1837	{
AnnaBridge	171:3a7713b1edbc	1838	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1839
AnnaBridge	171:3a7713b1edbc	1840	__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	171:3a7713b1edbc	1841	return(result);
AnnaBridge	171:3a7713b1edbc	1842	}
AnnaBridge	171:3a7713b1edbc	1843
AnnaBridge	171:3a7713b1edbc	1844	#define __SSAT16(ARG1,ARG2) \
AnnaBridge	171:3a7713b1edbc	1845	({ \
AnnaBridge	171:3a7713b1edbc	1846	int32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	171:3a7713b1edbc	1847	__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	171:3a7713b1edbc	1848	__RES; \
AnnaBridge	171:3a7713b1edbc	1849	})
AnnaBridge	171:3a7713b1edbc	1850
AnnaBridge	171:3a7713b1edbc	1851	#define __USAT16(ARG1,ARG2) \
AnnaBridge	171:3a7713b1edbc	1852	({ \
AnnaBridge	171:3a7713b1edbc	1853	uint32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	171:3a7713b1edbc	1854	__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	171:3a7713b1edbc	1855	__RES; \
AnnaBridge	171:3a7713b1edbc	1856	})
AnnaBridge	171:3a7713b1edbc	1857
AnnaBridge	171:3a7713b1edbc	1858	__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
AnnaBridge	171:3a7713b1edbc	1859	{
AnnaBridge	171:3a7713b1edbc	1860	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1861
AnnaBridge	171:3a7713b1edbc	1862	__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge	171:3a7713b1edbc	1863	return(result);
AnnaBridge	171:3a7713b1edbc	1864	}
AnnaBridge	171:3a7713b1edbc	1865
AnnaBridge	171:3a7713b1edbc	1866	__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1867	{
AnnaBridge	171:3a7713b1edbc	1868	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1869
AnnaBridge	171:3a7713b1edbc	1870	__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1871	return(result);
AnnaBridge	171:3a7713b1edbc	1872	}
AnnaBridge	171:3a7713b1edbc	1873
AnnaBridge	171:3a7713b1edbc	1874	__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
AnnaBridge	171:3a7713b1edbc	1875	{
AnnaBridge	171:3a7713b1edbc	1876	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1877
AnnaBridge	171:3a7713b1edbc	1878	__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge	171:3a7713b1edbc	1879	return(result);
AnnaBridge	171:3a7713b1edbc	1880	}
AnnaBridge	171:3a7713b1edbc	1881
AnnaBridge	171:3a7713b1edbc	1882	__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1883	{
AnnaBridge	171:3a7713b1edbc	1884	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1885
AnnaBridge	171:3a7713b1edbc	1886	__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1887	return(result);
AnnaBridge	171:3a7713b1edbc	1888	}
AnnaBridge	171:3a7713b1edbc	1889
AnnaBridge	171:3a7713b1edbc	1890	__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1891	{
AnnaBridge	171:3a7713b1edbc	1892	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1893
AnnaBridge	171:3a7713b1edbc	1894	__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1895	return(result);
AnnaBridge	171:3a7713b1edbc	1896	}
AnnaBridge	171:3a7713b1edbc	1897
AnnaBridge	171:3a7713b1edbc	1898	__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1899	{
AnnaBridge	171:3a7713b1edbc	1900	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1901
AnnaBridge	171:3a7713b1edbc	1902	__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1903	return(result);
AnnaBridge	171:3a7713b1edbc	1904	}
AnnaBridge	171:3a7713b1edbc	1905
AnnaBridge	171:3a7713b1edbc	1906	__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	171:3a7713b1edbc	1907	{
AnnaBridge	171:3a7713b1edbc	1908	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1909
AnnaBridge	171:3a7713b1edbc	1910	__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	171:3a7713b1edbc	1911	return(result);
AnnaBridge	171:3a7713b1edbc	1912	}
AnnaBridge	171:3a7713b1edbc	1913
AnnaBridge	171:3a7713b1edbc	1914	__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	171:3a7713b1edbc	1915	{
AnnaBridge	171:3a7713b1edbc	1916	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1917
AnnaBridge	171:3a7713b1edbc	1918	__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	171:3a7713b1edbc	1919	return(result);
AnnaBridge	171:3a7713b1edbc	1920	}
AnnaBridge	171:3a7713b1edbc	1921
AnnaBridge	171:3a7713b1edbc	1922	__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	171:3a7713b1edbc	1923	{
AnnaBridge	171:3a7713b1edbc	1924	union llreg_u{
AnnaBridge	171:3a7713b1edbc	1925	uint32_t w32[2];
AnnaBridge	171:3a7713b1edbc	1926	uint64_t w64;
AnnaBridge	171:3a7713b1edbc	1927	} llr;
AnnaBridge	171:3a7713b1edbc	1928	llr.w64 = acc;
AnnaBridge	171:3a7713b1edbc	1929
AnnaBridge	171:3a7713b1edbc	1930	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	171:3a7713b1edbc	1931	__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	171:3a7713b1edbc	1932	#else /* Big endian */
AnnaBridge	171:3a7713b1edbc	1933	__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	171:3a7713b1edbc	1934	#endif
AnnaBridge	171:3a7713b1edbc	1935
AnnaBridge	171:3a7713b1edbc	1936	return(llr.w64);
AnnaBridge	171:3a7713b1edbc	1937	}
AnnaBridge	171:3a7713b1edbc	1938
AnnaBridge	171:3a7713b1edbc	1939	__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	171:3a7713b1edbc	1940	{
AnnaBridge	171:3a7713b1edbc	1941	union llreg_u{
AnnaBridge	171:3a7713b1edbc	1942	uint32_t w32[2];
AnnaBridge	171:3a7713b1edbc	1943	uint64_t w64;
AnnaBridge	171:3a7713b1edbc	1944	} llr;
AnnaBridge	171:3a7713b1edbc	1945	llr.w64 = acc;
AnnaBridge	171:3a7713b1edbc	1946
AnnaBridge	171:3a7713b1edbc	1947	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	171:3a7713b1edbc	1948	__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	171:3a7713b1edbc	1949	#else /* Big endian */
AnnaBridge	171:3a7713b1edbc	1950	__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	171:3a7713b1edbc	1951	#endif
AnnaBridge	171:3a7713b1edbc	1952
AnnaBridge	171:3a7713b1edbc	1953	return(llr.w64);
AnnaBridge	171:3a7713b1edbc	1954	}
AnnaBridge	171:3a7713b1edbc	1955
AnnaBridge	171:3a7713b1edbc	1956	__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1957	{
AnnaBridge	171:3a7713b1edbc	1958	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1959
AnnaBridge	171:3a7713b1edbc	1960	__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1961	return(result);
AnnaBridge	171:3a7713b1edbc	1962	}
AnnaBridge	171:3a7713b1edbc	1963
AnnaBridge	171:3a7713b1edbc	1964	__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	1965	{
AnnaBridge	171:3a7713b1edbc	1966	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1967
AnnaBridge	171:3a7713b1edbc	1968	__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	1969	return(result);
AnnaBridge	171:3a7713b1edbc	1970	}
AnnaBridge	171:3a7713b1edbc	1971
AnnaBridge	171:3a7713b1edbc	1972	__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	171:3a7713b1edbc	1973	{
AnnaBridge	171:3a7713b1edbc	1974	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1975
AnnaBridge	171:3a7713b1edbc	1976	__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	171:3a7713b1edbc	1977	return(result);
AnnaBridge	171:3a7713b1edbc	1978	}
AnnaBridge	171:3a7713b1edbc	1979
AnnaBridge	171:3a7713b1edbc	1980	__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	171:3a7713b1edbc	1981	{
AnnaBridge	171:3a7713b1edbc	1982	uint32_t result;
AnnaBridge	171:3a7713b1edbc	1983
AnnaBridge	171:3a7713b1edbc	1984	__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	171:3a7713b1edbc	1985	return(result);
AnnaBridge	171:3a7713b1edbc	1986	}
AnnaBridge	171:3a7713b1edbc	1987
AnnaBridge	171:3a7713b1edbc	1988	__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	171:3a7713b1edbc	1989	{
AnnaBridge	171:3a7713b1edbc	1990	union llreg_u{
AnnaBridge	171:3a7713b1edbc	1991	uint32_t w32[2];
AnnaBridge	171:3a7713b1edbc	1992	uint64_t w64;
AnnaBridge	171:3a7713b1edbc	1993	} llr;
AnnaBridge	171:3a7713b1edbc	1994	llr.w64 = acc;
AnnaBridge	171:3a7713b1edbc	1995
AnnaBridge	171:3a7713b1edbc	1996	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	171:3a7713b1edbc	1997	__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	171:3a7713b1edbc	1998	#else /* Big endian */
AnnaBridge	171:3a7713b1edbc	1999	__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	171:3a7713b1edbc	2000	#endif
AnnaBridge	171:3a7713b1edbc	2001
AnnaBridge	171:3a7713b1edbc	2002	return(llr.w64);
AnnaBridge	171:3a7713b1edbc	2003	}
AnnaBridge	171:3a7713b1edbc	2004
AnnaBridge	171:3a7713b1edbc	2005	__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	171:3a7713b1edbc	2006	{
AnnaBridge	171:3a7713b1edbc	2007	union llreg_u{
AnnaBridge	171:3a7713b1edbc	2008	uint32_t w32[2];
AnnaBridge	171:3a7713b1edbc	2009	uint64_t w64;
AnnaBridge	171:3a7713b1edbc	2010	} llr;
AnnaBridge	171:3a7713b1edbc	2011	llr.w64 = acc;
AnnaBridge	171:3a7713b1edbc	2012
AnnaBridge	171:3a7713b1edbc	2013	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	171:3a7713b1edbc	2014	__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	171:3a7713b1edbc	2015	#else /* Big endian */
AnnaBridge	171:3a7713b1edbc	2016	__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	171:3a7713b1edbc	2017	#endif
AnnaBridge	171:3a7713b1edbc	2018
AnnaBridge	171:3a7713b1edbc	2019	return(llr.w64);
AnnaBridge	171:3a7713b1edbc	2020	}
AnnaBridge	171:3a7713b1edbc	2021
AnnaBridge	171:3a7713b1edbc	2022	__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
AnnaBridge	171:3a7713b1edbc	2023	{
AnnaBridge	171:3a7713b1edbc	2024	uint32_t result;
AnnaBridge	171:3a7713b1edbc	2025
AnnaBridge	171:3a7713b1edbc	2026	__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	2027	return(result);
AnnaBridge	171:3a7713b1edbc	2028	}
AnnaBridge	171:3a7713b1edbc	2029
AnnaBridge	171:3a7713b1edbc	2030	__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
AnnaBridge	171:3a7713b1edbc	2031	{
AnnaBridge	171:3a7713b1edbc	2032	int32_t result;
AnnaBridge	171:3a7713b1edbc	2033
AnnaBridge	171:3a7713b1edbc	2034	__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	2035	return(result);
AnnaBridge	171:3a7713b1edbc	2036	}
AnnaBridge	171:3a7713b1edbc	2037
AnnaBridge	171:3a7713b1edbc	2038	__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
AnnaBridge	171:3a7713b1edbc	2039	{
AnnaBridge	171:3a7713b1edbc	2040	int32_t result;
AnnaBridge	171:3a7713b1edbc	2041
AnnaBridge	171:3a7713b1edbc	2042	__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	171:3a7713b1edbc	2043	return(result);
AnnaBridge	171:3a7713b1edbc	2044	}
AnnaBridge	171:3a7713b1edbc	2045
AnnaBridge	171:3a7713b1edbc	2046	#if 0
AnnaBridge	171:3a7713b1edbc	2047	#define __PKHBT(ARG1,ARG2,ARG3) \
AnnaBridge	171:3a7713b1edbc	2048	({ \
AnnaBridge	171:3a7713b1edbc	2049	uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge	171:3a7713b1edbc	2050	__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge	171:3a7713b1edbc	2051	__RES; \
AnnaBridge	171:3a7713b1edbc	2052	})
AnnaBridge	171:3a7713b1edbc	2053
AnnaBridge	171:3a7713b1edbc	2054	#define __PKHTB(ARG1,ARG2,ARG3) \
AnnaBridge	171:3a7713b1edbc	2055	({ \
AnnaBridge	171:3a7713b1edbc	2056	uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge	171:3a7713b1edbc	2057	if (ARG3 == 0) \
AnnaBridge	171:3a7713b1edbc	2058	__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
AnnaBridge	171:3a7713b1edbc	2059	else \
AnnaBridge	171:3a7713b1edbc	2060	__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge	171:3a7713b1edbc	2061	__RES; \
AnnaBridge	171:3a7713b1edbc	2062	})
AnnaBridge	171:3a7713b1edbc	2063	#endif
AnnaBridge	171:3a7713b1edbc	2064
AnnaBridge	171:3a7713b1edbc	2065	#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) \| \
AnnaBridge	171:3a7713b1edbc	2066	((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
AnnaBridge	171:3a7713b1edbc	2067
AnnaBridge	171:3a7713b1edbc	2068	#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) \| \
AnnaBridge	171:3a7713b1edbc	2069	((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
AnnaBridge	171:3a7713b1edbc	2070
AnnaBridge	171:3a7713b1edbc	2071	__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
AnnaBridge	171:3a7713b1edbc	2072	{
AnnaBridge	171:3a7713b1edbc	2073	int32_t result;
AnnaBridge	171:3a7713b1edbc	2074
AnnaBridge	171:3a7713b1edbc	2075	__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	171:3a7713b1edbc	2076	return(result);
AnnaBridge	171:3a7713b1edbc	2077	}
AnnaBridge	171:3a7713b1edbc	2078
AnnaBridge	171:3a7713b1edbc	2079	#endif /* (__ARM_FEATURE_DSP == 1) */
AnnaBridge	171:3a7713b1edbc	2080	/@} end of group CMSIS_SIMD_intrinsics /
AnnaBridge	171:3a7713b1edbc	2081
AnnaBridge	171:3a7713b1edbc	2082
AnnaBridge	171:3a7713b1edbc	2083	#pragma GCC diagnostic pop
AnnaBridge	171:3a7713b1edbc	2084
AnnaBridge	171:3a7713b1edbc	2085	#endif /* __CMSIS_GCC_H */