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TARGET_KW24D/TOOLCHAIN_IAR/MKW24D5.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 ** ###################################################################
AnnaBridge 171:3a7713b1edbc 3 ** Processor: MKW24D512VHA5
AnnaBridge 171:3a7713b1edbc 4 ** Compilers: Keil ARM C/C++ Compiler
AnnaBridge 171:3a7713b1edbc 5 ** Freescale C/C++ for Embedded ARM
AnnaBridge 171:3a7713b1edbc 6 ** GNU C Compiler
AnnaBridge 171:3a7713b1edbc 7 ** IAR ANSI C/C++ Compiler for ARM
AnnaBridge 171:3a7713b1edbc 8 **
AnnaBridge 171:3a7713b1edbc 9 ** Reference manual: MKW2xDRM Rev.2 July 2014
AnnaBridge 171:3a7713b1edbc 10 ** Version: rev. 2.0, 2014-11-26
AnnaBridge 171:3a7713b1edbc 11 ** Build: b160512
AnnaBridge 171:3a7713b1edbc 12 **
AnnaBridge 171:3a7713b1edbc 13 ** Abstract:
AnnaBridge 171:3a7713b1edbc 14 ** CMSIS Peripheral Access Layer for MKW24D5
AnnaBridge 171:3a7713b1edbc 15 **
AnnaBridge 171:3a7713b1edbc 16 ** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
AnnaBridge 171:3a7713b1edbc 17 ** All rights reserved.
AnnaBridge 171:3a7713b1edbc 18 **
AnnaBridge 171:3a7713b1edbc 19 ** Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 20 ** are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 21 **
AnnaBridge 171:3a7713b1edbc 22 ** o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 171:3a7713b1edbc 23 ** of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 24 **
AnnaBridge 171:3a7713b1edbc 25 ** o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 26 ** list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 171:3a7713b1edbc 27 ** other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 28 **
AnnaBridge 171:3a7713b1edbc 29 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge 171:3a7713b1edbc 30 ** contributors may be used to endorse or promote products derived from this
AnnaBridge 171:3a7713b1edbc 31 ** software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 32 **
AnnaBridge 171:3a7713b1edbc 33 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 171:3a7713b1edbc 34 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 171:3a7713b1edbc 35 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 36 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 37 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 171:3a7713b1edbc 38 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 171:3a7713b1edbc 39 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 171:3a7713b1edbc 40 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 171:3a7713b1edbc 41 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 171:3a7713b1edbc 42 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 43 **
AnnaBridge 171:3a7713b1edbc 44 ** http: www.freescale.com
AnnaBridge 171:3a7713b1edbc 45 ** mail: support@freescale.com
AnnaBridge 171:3a7713b1edbc 46 **
AnnaBridge 171:3a7713b1edbc 47 ** Revisions:
AnnaBridge 171:3a7713b1edbc 48 ** - rev. 1.0 (2013-11-22)
AnnaBridge 171:3a7713b1edbc 49 ** Initial version.
AnnaBridge 171:3a7713b1edbc 50 ** - rev. 2.0 (2014-11-26)
AnnaBridge 171:3a7713b1edbc 51 ** update of SystemInit() imlementation
AnnaBridge 171:3a7713b1edbc 52 ** Module access macro module_BASES replaced by module_BASE_PTRS.
AnnaBridge 171:3a7713b1edbc 53 ** Register accessor macros added to the memory map.
AnnaBridge 171:3a7713b1edbc 54 ** MCG - bit LOLS in MCG_S register renamed to LOLS0.
AnnaBridge 171:3a7713b1edbc 55 ** DAC0 registers removed.
AnnaBridge 171:3a7713b1edbc 56 **
AnnaBridge 171:3a7713b1edbc 57 ** ###################################################################
AnnaBridge 171:3a7713b1edbc 58 */
AnnaBridge 171:3a7713b1edbc 59
AnnaBridge 171:3a7713b1edbc 60 /*!
AnnaBridge 171:3a7713b1edbc 61 * @file MKW24D5.h
AnnaBridge 171:3a7713b1edbc 62 * @version 2.0
AnnaBridge 171:3a7713b1edbc 63 * @date 2014-11-26
AnnaBridge 171:3a7713b1edbc 64 * @brief CMSIS Peripheral Access Layer for MKW24D5
AnnaBridge 171:3a7713b1edbc 65 *
AnnaBridge 171:3a7713b1edbc 66 * CMSIS Peripheral Access Layer for MKW24D5
AnnaBridge 171:3a7713b1edbc 67 */
AnnaBridge 171:3a7713b1edbc 68
AnnaBridge 171:3a7713b1edbc 69 #ifndef _MKW24D5_H_
AnnaBridge 171:3a7713b1edbc 70 #define _MKW24D5_H_ /**< Symbol preventing repeated inclusion */
AnnaBridge 171:3a7713b1edbc 71
AnnaBridge 171:3a7713b1edbc 72 /** Memory map major version (memory maps with equal major version number are
AnnaBridge 171:3a7713b1edbc 73 * compatible) */
AnnaBridge 171:3a7713b1edbc 74 #define MCU_MEM_MAP_VERSION 0x0200U
AnnaBridge 171:3a7713b1edbc 75 /** Memory map minor version */
AnnaBridge 171:3a7713b1edbc 76 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U
AnnaBridge 171:3a7713b1edbc 77
AnnaBridge 171:3a7713b1edbc 78 /**
AnnaBridge 171:3a7713b1edbc 79 * @brief Macro to calculate address of an aliased word in the peripheral
AnnaBridge 171:3a7713b1edbc 80 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
AnnaBridge 171:3a7713b1edbc 81 * 0x400FFFFF).
AnnaBridge 171:3a7713b1edbc 82 * @param Reg Register to access.
AnnaBridge 171:3a7713b1edbc 83 * @param Bit Bit number to access.
AnnaBridge 171:3a7713b1edbc 84 * @return Address of the aliased word in the peripheral bitband area.
AnnaBridge 171:3a7713b1edbc 85 */
AnnaBridge 171:3a7713b1edbc 86 #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
AnnaBridge 171:3a7713b1edbc 87 /**
AnnaBridge 171:3a7713b1edbc 88 * @brief Macro to access a single bit of a peripheral register (bit band region
AnnaBridge 171:3a7713b1edbc 89 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
AnnaBridge 171:3a7713b1edbc 90 * be used for peripherals with 32bit access allowed.
AnnaBridge 171:3a7713b1edbc 91 * @param Reg Register to access.
AnnaBridge 171:3a7713b1edbc 92 * @param Bit Bit number to access.
AnnaBridge 171:3a7713b1edbc 93 * @return Value of the targeted bit in the bit band region.
AnnaBridge 171:3a7713b1edbc 94 */
AnnaBridge 171:3a7713b1edbc 95 #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
AnnaBridge 171:3a7713b1edbc 96 #define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
AnnaBridge 171:3a7713b1edbc 97 /**
AnnaBridge 171:3a7713b1edbc 98 * @brief Macro to access a single bit of a peripheral register (bit band region
AnnaBridge 171:3a7713b1edbc 99 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
AnnaBridge 171:3a7713b1edbc 100 * be used for peripherals with 16bit access allowed.
AnnaBridge 171:3a7713b1edbc 101 * @param Reg Register to access.
AnnaBridge 171:3a7713b1edbc 102 * @param Bit Bit number to access.
AnnaBridge 171:3a7713b1edbc 103 * @return Value of the targeted bit in the bit band region.
AnnaBridge 171:3a7713b1edbc 104 */
AnnaBridge 171:3a7713b1edbc 105 #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
AnnaBridge 171:3a7713b1edbc 106 /**
AnnaBridge 171:3a7713b1edbc 107 * @brief Macro to access a single bit of a peripheral register (bit band region
AnnaBridge 171:3a7713b1edbc 108 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
AnnaBridge 171:3a7713b1edbc 109 * be used for peripherals with 8bit access allowed.
AnnaBridge 171:3a7713b1edbc 110 * @param Reg Register to access.
AnnaBridge 171:3a7713b1edbc 111 * @param Bit Bit number to access.
AnnaBridge 171:3a7713b1edbc 112 * @return Value of the targeted bit in the bit band region.
AnnaBridge 171:3a7713b1edbc 113 */
AnnaBridge 171:3a7713b1edbc 114 #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
AnnaBridge 171:3a7713b1edbc 115
AnnaBridge 171:3a7713b1edbc 116 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 117 -- Interrupt vector numbers
AnnaBridge 171:3a7713b1edbc 118 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 119
AnnaBridge 171:3a7713b1edbc 120 /*!
AnnaBridge 171:3a7713b1edbc 121 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
AnnaBridge 171:3a7713b1edbc 122 * @{
AnnaBridge 171:3a7713b1edbc 123 */
AnnaBridge 171:3a7713b1edbc 124
AnnaBridge 171:3a7713b1edbc 125 /** Interrupt Number Definitions */
AnnaBridge 171:3a7713b1edbc 126 #define NUMBER_OF_INT_VECTORS 81 /**< Number of interrupts in the Vector table */
AnnaBridge 171:3a7713b1edbc 127
AnnaBridge 171:3a7713b1edbc 128 typedef enum IRQn {
AnnaBridge 171:3a7713b1edbc 129 /* Auxiliary constants */
AnnaBridge 171:3a7713b1edbc 130 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
AnnaBridge 171:3a7713b1edbc 131
AnnaBridge 171:3a7713b1edbc 132 /* Core interrupts */
AnnaBridge 171:3a7713b1edbc 133 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 134 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 135 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
AnnaBridge 171:3a7713b1edbc 136 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 137 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 138 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 139 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
AnnaBridge 171:3a7713b1edbc 140 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 141 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 142
AnnaBridge 171:3a7713b1edbc 143 /* Device specific interrupts */
AnnaBridge 171:3a7713b1edbc 144 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */
AnnaBridge 171:3a7713b1edbc 145 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */
AnnaBridge 171:3a7713b1edbc 146 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */
AnnaBridge 171:3a7713b1edbc 147 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */
AnnaBridge 171:3a7713b1edbc 148 DMA4_IRQn = 4, /**< DMA channel 4 transfer complete */
AnnaBridge 171:3a7713b1edbc 149 DMA5_IRQn = 5, /**< DMA channel 5 transfer complete */
AnnaBridge 171:3a7713b1edbc 150 DMA6_IRQn = 6, /**< DMA channel 6 transfer complete */
AnnaBridge 171:3a7713b1edbc 151 DMA7_IRQn = 7, /**< DMA channel 7 transfer complete */
AnnaBridge 171:3a7713b1edbc 152 DMA8_IRQn = 8, /**< DMA channel 8 transfer complete */
AnnaBridge 171:3a7713b1edbc 153 DMA9_IRQn = 9, /**< DMA channel 9 transfer complete */
AnnaBridge 171:3a7713b1edbc 154 DMA10_IRQn = 10, /**< DMA channel 10 transfer complete */
AnnaBridge 171:3a7713b1edbc 155 DMA11_IRQn = 11, /**< DMA channel 11 transfer complete */
AnnaBridge 171:3a7713b1edbc 156 DMA12_IRQn = 12, /**< DMA channel 12 transfer complete */
AnnaBridge 171:3a7713b1edbc 157 DMA13_IRQn = 13, /**< DMA channel 13 transfer complete */
AnnaBridge 171:3a7713b1edbc 158 DMA14_IRQn = 14, /**< DMA channel 14 transfer complete */
AnnaBridge 171:3a7713b1edbc 159 DMA15_IRQn = 15, /**< DMA channel 15 transfer complete */
AnnaBridge 171:3a7713b1edbc 160 DMA_Error_IRQn = 16, /**< DMA channel 0 - 15 error */
AnnaBridge 171:3a7713b1edbc 161 MCM_IRQn = 17, /**< MCM normal interrupt */
AnnaBridge 171:3a7713b1edbc 162 FTFL_IRQn = 18, /**< FTFL command complete */
AnnaBridge 171:3a7713b1edbc 163 FTFL_Collision_IRQn = 19, /**< FTFL read collision */
AnnaBridge 171:3a7713b1edbc 164 PMC_IRQn = 20, /**< PMC controller low-voltage detect, low-voltage warning */
AnnaBridge 171:3a7713b1edbc 165 LLWU_IRQn = 21, /**< Low leakage wakeup */
AnnaBridge 171:3a7713b1edbc 166 WDOG_EWM_IRQn = 22, /**< Single interrupt vector for WDOG and EWM */
AnnaBridge 171:3a7713b1edbc 167 RNG_IRQn = 23, /**< Randon number generator */
AnnaBridge 171:3a7713b1edbc 168 I2C0_IRQn = 24, /**< Inter-integrated circuit 0 */
AnnaBridge 171:3a7713b1edbc 169 I2C1_IRQn = 25, /**< Inter-integrated circuit 1 */
AnnaBridge 171:3a7713b1edbc 170 SPI0_IRQn = 26, /**< Serial peripheral Interface 0 */
AnnaBridge 171:3a7713b1edbc 171 SPI1_IRQn = 27, /**< Serial peripheral Interface 1 */
AnnaBridge 171:3a7713b1edbc 172 I2S0_Tx_IRQn = 28, /**< Integrated interchip sound 0 transmit interrupt */
AnnaBridge 171:3a7713b1edbc 173 I2S0_Rx_IRQn = 29, /**< Integrated interchip sound 0 receive interrupt */
AnnaBridge 171:3a7713b1edbc 174 Reserved46_IRQn = 30, /**< Reserved interrupt */
AnnaBridge 171:3a7713b1edbc 175 UART0_RX_TX_IRQn = 31, /**< UART0 receive/transmit interrupt */
AnnaBridge 171:3a7713b1edbc 176 UART0_ERR_IRQn = 32, /**< UART0 error interrupt */
AnnaBridge 171:3a7713b1edbc 177 UART1_RX_TX_IRQn = 33, /**< UART1 receive/transmit interrupt */
AnnaBridge 171:3a7713b1edbc 178 UART1_ERR_IRQn = 34, /**< UART1 error interrupt */
AnnaBridge 171:3a7713b1edbc 179 UART2_RX_TX_IRQn = 35, /**< UART2 receive/transmit interrupt */
AnnaBridge 171:3a7713b1edbc 180 UART2_ERR_IRQn = 36, /**< UART2 error interrupt */
AnnaBridge 171:3a7713b1edbc 181 Reserved53_IRQn = 37, /**< Reserved interrupt */
AnnaBridge 171:3a7713b1edbc 182 Reserved54_IRQn = 38, /**< Reserved interrupt */
AnnaBridge 171:3a7713b1edbc 183 ADC0_IRQn = 39, /**< Analog-to-digital converter 0 */
AnnaBridge 171:3a7713b1edbc 184 CMP0_IRQn = 40, /**< Comparator 0 */
AnnaBridge 171:3a7713b1edbc 185 CMP1_IRQn = 41, /**< Comparator 1 */
AnnaBridge 171:3a7713b1edbc 186 FTM0_IRQn = 42, /**< FlexTimer module 0 fault, overflow and channels interrupt */
AnnaBridge 171:3a7713b1edbc 187 FTM1_IRQn = 43, /**< FlexTimer module 1 fault, overflow and channels interrupt */
AnnaBridge 171:3a7713b1edbc 188 FTM2_IRQn = 44, /**< FlexTimer module 2 fault, overflow and channels interrupt */
AnnaBridge 171:3a7713b1edbc 189 CMT_IRQn = 45, /**< Carrier modulator transmitter */
AnnaBridge 171:3a7713b1edbc 190 RTC_IRQn = 46, /**< Real time clock */
AnnaBridge 171:3a7713b1edbc 191 RTC_Seconds_IRQn = 47, /**< Real time clock seconds */
AnnaBridge 171:3a7713b1edbc 192 PIT0_IRQn = 48, /**< Periodic interrupt timer channel 0 */
AnnaBridge 171:3a7713b1edbc 193 PIT1_IRQn = 49, /**< Periodic interrupt timer channel 1 */
AnnaBridge 171:3a7713b1edbc 194 PIT2_IRQn = 50, /**< Periodic interrupt timer channel 2 */
AnnaBridge 171:3a7713b1edbc 195 PIT3_IRQn = 51, /**< Periodic interrupt timer channel 3 */
AnnaBridge 171:3a7713b1edbc 196 PDB0_IRQn = 52, /**< Programmable delay block */
AnnaBridge 171:3a7713b1edbc 197 USB0_IRQn = 53, /**< USB OTG interrupt */
AnnaBridge 171:3a7713b1edbc 198 USBDCD_IRQn = 54, /**< USB charger detect */
AnnaBridge 171:3a7713b1edbc 199 Reserved71_IRQn = 55, /**< Reserved interrupt */
AnnaBridge 171:3a7713b1edbc 200 Reserved72_IRQn = 56, /**< Reserved interrupt */
AnnaBridge 171:3a7713b1edbc 201 MCG_IRQn = 57, /**< Multipurpose clock generator */
AnnaBridge 171:3a7713b1edbc 202 LPTMR0_IRQn = 58, /**< Low power timer interrupt */
AnnaBridge 171:3a7713b1edbc 203 PORTA_IRQn = 59, /**< Port A pin detect interrupt */
AnnaBridge 171:3a7713b1edbc 204 PORTB_IRQn = 60, /**< Port B pin detect interrupt */
AnnaBridge 171:3a7713b1edbc 205 PORTC_IRQn = 61, /**< Port C pin detect interrupt */
AnnaBridge 171:3a7713b1edbc 206 PORTD_IRQn = 62, /**< Port D pin detect interrupt */
AnnaBridge 171:3a7713b1edbc 207 PORTE_IRQn = 63, /**< Port E pin detect interrupt */
AnnaBridge 171:3a7713b1edbc 208 SWI_IRQn = 64 /**< Software interrupt */
AnnaBridge 171:3a7713b1edbc 209 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 210
AnnaBridge 171:3a7713b1edbc 211 /*!
AnnaBridge 171:3a7713b1edbc 212 * @}
AnnaBridge 171:3a7713b1edbc 213 */ /* end of group Interrupt_vector_numbers */
AnnaBridge 171:3a7713b1edbc 214
AnnaBridge 171:3a7713b1edbc 215
AnnaBridge 171:3a7713b1edbc 216 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 217 -- Cortex M4 Core Configuration
AnnaBridge 171:3a7713b1edbc 218 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 219
AnnaBridge 171:3a7713b1edbc 220 /*!
AnnaBridge 171:3a7713b1edbc 221 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
AnnaBridge 171:3a7713b1edbc 222 * @{
AnnaBridge 171:3a7713b1edbc 223 */
AnnaBridge 171:3a7713b1edbc 224
AnnaBridge 171:3a7713b1edbc 225 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
AnnaBridge 171:3a7713b1edbc 226 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
AnnaBridge 171:3a7713b1edbc 227 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
AnnaBridge 171:3a7713b1edbc 228 #define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */
AnnaBridge 171:3a7713b1edbc 229
AnnaBridge 171:3a7713b1edbc 230 #include "core_cm4.h" /* Core Peripheral Access Layer */
AnnaBridge 171:3a7713b1edbc 231 #include "system_MKW24D5.h" /* Device specific configuration file */
AnnaBridge 171:3a7713b1edbc 232
AnnaBridge 171:3a7713b1edbc 233 /*!
AnnaBridge 171:3a7713b1edbc 234 * @}
AnnaBridge 171:3a7713b1edbc 235 */ /* end of group Cortex_Core_Configuration */
AnnaBridge 171:3a7713b1edbc 236
AnnaBridge 171:3a7713b1edbc 237
AnnaBridge 171:3a7713b1edbc 238 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 239 -- Mapping Information
AnnaBridge 171:3a7713b1edbc 240 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 241
AnnaBridge 171:3a7713b1edbc 242 /*!
AnnaBridge 171:3a7713b1edbc 243 * @addtogroup Mapping_Information Mapping Information
AnnaBridge 171:3a7713b1edbc 244 * @{
AnnaBridge 171:3a7713b1edbc 245 */
AnnaBridge 171:3a7713b1edbc 246
AnnaBridge 171:3a7713b1edbc 247 /** Mapping Information */
AnnaBridge 171:3a7713b1edbc 248 /*!
AnnaBridge 171:3a7713b1edbc 249 * @addtogroup edma_request
AnnaBridge 171:3a7713b1edbc 250 * @{
AnnaBridge 171:3a7713b1edbc 251 */
AnnaBridge 171:3a7713b1edbc 252
AnnaBridge 171:3a7713b1edbc 253 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 254 * Definitions
AnnaBridge 171:3a7713b1edbc 255 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 256
AnnaBridge 171:3a7713b1edbc 257 /*!
AnnaBridge 171:3a7713b1edbc 258 * @brief Structure for the DMA hardware request
AnnaBridge 171:3a7713b1edbc 259 *
AnnaBridge 171:3a7713b1edbc 260 * Defines the structure for the DMA hardware request collections. The user can configure the
AnnaBridge 171:3a7713b1edbc 261 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
AnnaBridge 171:3a7713b1edbc 262 * of the hardware request varies according to the to SoC.
AnnaBridge 171:3a7713b1edbc 263 */
AnnaBridge 171:3a7713b1edbc 264 typedef enum _dma_request_source
AnnaBridge 171:3a7713b1edbc 265 {
AnnaBridge 171:3a7713b1edbc 266 kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
AnnaBridge 171:3a7713b1edbc 267 kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */
AnnaBridge 171:3a7713b1edbc 268 kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */
AnnaBridge 171:3a7713b1edbc 269 kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */
AnnaBridge 171:3a7713b1edbc 270 kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */
AnnaBridge 171:3a7713b1edbc 271 kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */
AnnaBridge 171:3a7713b1edbc 272 kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */
AnnaBridge 171:3a7713b1edbc 273 kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */
AnnaBridge 171:3a7713b1edbc 274 kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */
AnnaBridge 171:3a7713b1edbc 275 kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */
AnnaBridge 171:3a7713b1edbc 276 kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */
AnnaBridge 171:3a7713b1edbc 277 kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */
AnnaBridge 171:3a7713b1edbc 278 kDmaRequestMux0Reserved12 = 12|0x100U, /**< Reserved12 */
AnnaBridge 171:3a7713b1edbc 279 kDmaRequestMux0Reserved13 = 13|0x100U, /**< Reserved13 */
AnnaBridge 171:3a7713b1edbc 280 kDmaRequestMux0I2S0Rx = 14|0x100U, /**< I2S0 Receive. */
AnnaBridge 171:3a7713b1edbc 281 kDmaRequestMux0I2S0Tx = 15|0x100U, /**< I2S0 Transmit. */
AnnaBridge 171:3a7713b1edbc 282 kDmaRequestMux0SPI0Rx = 16|0x100U, /**< SPI0 Receive. */
AnnaBridge 171:3a7713b1edbc 283 kDmaRequestMux0SPI0Tx = 17|0x100U, /**< SPI0 Transmit. */
AnnaBridge 171:3a7713b1edbc 284 kDmaRequestMux0SPI1Rx = 18|0x100U, /**< SPI1 Receive. */
AnnaBridge 171:3a7713b1edbc 285 kDmaRequestMux0SPI1Tx = 19|0x100U, /**< SPI1 Transmit. */
AnnaBridge 171:3a7713b1edbc 286 kDmaRequestMux0Reserved20 = 20|0x100U, /**< Reserved20 */
AnnaBridge 171:3a7713b1edbc 287 kDmaRequestMux0Reserved21 = 21|0x100U, /**< Reserved21 */
AnnaBridge 171:3a7713b1edbc 288 kDmaRequestMux0I2C0 = 22|0x100U, /**< I2C0. */
AnnaBridge 171:3a7713b1edbc 289 kDmaRequestMux0I2C1 = 23|0x100U, /**< I2C1. */
AnnaBridge 171:3a7713b1edbc 290 kDmaRequestMux0FTM0Channel0 = 24|0x100U, /**< FTM0 C0V. */
AnnaBridge 171:3a7713b1edbc 291 kDmaRequestMux0FTM0Channel1 = 25|0x100U, /**< FTM0 C1V. */
AnnaBridge 171:3a7713b1edbc 292 kDmaRequestMux0FTM0Channel2 = 26|0x100U, /**< FTM0 C2V. */
AnnaBridge 171:3a7713b1edbc 293 kDmaRequestMux0FTM0Channel3 = 27|0x100U, /**< FTM0 C3V. */
AnnaBridge 171:3a7713b1edbc 294 kDmaRequestMux0FTM0Channel4 = 28|0x100U, /**< FTM0 C4V. */
AnnaBridge 171:3a7713b1edbc 295 kDmaRequestMux0FTM0Channel5 = 29|0x100U, /**< FTM0 C5V. */
AnnaBridge 171:3a7713b1edbc 296 kDmaRequestMux0FTM0Channel6 = 30|0x100U, /**< FTM0 C6V. */
AnnaBridge 171:3a7713b1edbc 297 kDmaRequestMux0FTM0Channel7 = 31|0x100U, /**< FTM0 C7V. */
AnnaBridge 171:3a7713b1edbc 298 kDmaRequestMux0FTM1Channel0 = 32|0x100U, /**< FTM1 C0V. */
AnnaBridge 171:3a7713b1edbc 299 kDmaRequestMux0FTM1Channel1 = 33|0x100U, /**< FTM1 C1V. */
AnnaBridge 171:3a7713b1edbc 300 kDmaRequestMux0FTM2Channel0 = 34|0x100U, /**< FTM2 C0V. */
AnnaBridge 171:3a7713b1edbc 301 kDmaRequestMux0FTM2Channel1 = 35|0x100U, /**< FTM2 C1V. */
AnnaBridge 171:3a7713b1edbc 302 kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */
AnnaBridge 171:3a7713b1edbc 303 kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */
AnnaBridge 171:3a7713b1edbc 304 kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */
AnnaBridge 171:3a7713b1edbc 305 kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */
AnnaBridge 171:3a7713b1edbc 306 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
AnnaBridge 171:3a7713b1edbc 307 kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */
AnnaBridge 171:3a7713b1edbc 308 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
AnnaBridge 171:3a7713b1edbc 309 kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */
AnnaBridge 171:3a7713b1edbc 310 kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */
AnnaBridge 171:3a7713b1edbc 311 kDmaRequestMux0Reserved45 = 45|0x100U, /**< Reserved45 */
AnnaBridge 171:3a7713b1edbc 312 kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */
AnnaBridge 171:3a7713b1edbc 313 kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */
AnnaBridge 171:3a7713b1edbc 314 kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */
AnnaBridge 171:3a7713b1edbc 315 kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
AnnaBridge 171:3a7713b1edbc 316 kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
AnnaBridge 171:3a7713b1edbc 317 kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
AnnaBridge 171:3a7713b1edbc 318 kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */
AnnaBridge 171:3a7713b1edbc 319 kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */
AnnaBridge 171:3a7713b1edbc 320 kDmaRequestMux0AlwaysOn54 = 54|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 321 kDmaRequestMux0AlwaysOn55 = 55|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 322 kDmaRequestMux0AlwaysOn56 = 56|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 323 kDmaRequestMux0AlwaysOn57 = 57|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 324 kDmaRequestMux0AlwaysOn58 = 58|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 325 kDmaRequestMux0AlwaysOn59 = 59|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 326 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 327 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 328 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 329 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 330 } dma_request_source_t;
AnnaBridge 171:3a7713b1edbc 331
AnnaBridge 171:3a7713b1edbc 332 /* @} */
AnnaBridge 171:3a7713b1edbc 333
AnnaBridge 171:3a7713b1edbc 334
AnnaBridge 171:3a7713b1edbc 335 /*!
AnnaBridge 171:3a7713b1edbc 336 * @}
AnnaBridge 171:3a7713b1edbc 337 */ /* end of group Mapping_Information */
AnnaBridge 171:3a7713b1edbc 338
AnnaBridge 171:3a7713b1edbc 339
AnnaBridge 171:3a7713b1edbc 340 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 341 -- Device Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 342 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 343
AnnaBridge 171:3a7713b1edbc 344 /*!
AnnaBridge 171:3a7713b1edbc 345 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 346 * @{
AnnaBridge 171:3a7713b1edbc 347 */
AnnaBridge 171:3a7713b1edbc 348
AnnaBridge 171:3a7713b1edbc 349
AnnaBridge 171:3a7713b1edbc 350 /*
AnnaBridge 171:3a7713b1edbc 351 ** Start of section using anonymous unions
AnnaBridge 171:3a7713b1edbc 352 */
AnnaBridge 171:3a7713b1edbc 353
AnnaBridge 171:3a7713b1edbc 354 #if defined(__ARMCC_VERSION)
AnnaBridge 171:3a7713b1edbc 355 #pragma push
AnnaBridge 171:3a7713b1edbc 356 #pragma anon_unions
AnnaBridge 171:3a7713b1edbc 357 #elif defined(__CWCC__)
AnnaBridge 171:3a7713b1edbc 358 #pragma push
AnnaBridge 171:3a7713b1edbc 359 #pragma cpp_extensions on
AnnaBridge 171:3a7713b1edbc 360 #elif defined(__GNUC__)
AnnaBridge 171:3a7713b1edbc 361 /* anonymous unions are enabled by default */
AnnaBridge 171:3a7713b1edbc 362 #elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge 171:3a7713b1edbc 363 #pragma language=extended
AnnaBridge 171:3a7713b1edbc 364 #else
AnnaBridge 171:3a7713b1edbc 365 #error Not supported compiler type
AnnaBridge 171:3a7713b1edbc 366 #endif
AnnaBridge 171:3a7713b1edbc 367
AnnaBridge 171:3a7713b1edbc 368 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 369 -- ADC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 370 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 371
AnnaBridge 171:3a7713b1edbc 372 /*!
AnnaBridge 171:3a7713b1edbc 373 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 374 * @{
AnnaBridge 171:3a7713b1edbc 375 */
AnnaBridge 171:3a7713b1edbc 376
AnnaBridge 171:3a7713b1edbc 377 /** ADC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 378 typedef struct {
AnnaBridge 171:3a7713b1edbc 379 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 380 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 381 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 382 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 383 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 384 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 385 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 386 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 387 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 388 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 389 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 390 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 391 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 392 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 393 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 394 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 395 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 396 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 397 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 398 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 399 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 400 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 401 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 402 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 403 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 404 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 405 } ADC_Type;
AnnaBridge 171:3a7713b1edbc 406
AnnaBridge 171:3a7713b1edbc 407 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 408 -- ADC Register Masks
AnnaBridge 171:3a7713b1edbc 409 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 410
AnnaBridge 171:3a7713b1edbc 411 /*!
AnnaBridge 171:3a7713b1edbc 412 * @addtogroup ADC_Register_Masks ADC Register Masks
AnnaBridge 171:3a7713b1edbc 413 * @{
AnnaBridge 171:3a7713b1edbc 414 */
AnnaBridge 171:3a7713b1edbc 415
AnnaBridge 171:3a7713b1edbc 416 /*! @name SC1 - ADC Status and Control Registers 1 */
AnnaBridge 171:3a7713b1edbc 417 #define ADC_SC1_ADCH_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 418 #define ADC_SC1_ADCH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 419 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
AnnaBridge 171:3a7713b1edbc 420 #define ADC_SC1_DIFF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 421 #define ADC_SC1_DIFF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 422 #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
AnnaBridge 171:3a7713b1edbc 423 #define ADC_SC1_AIEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 424 #define ADC_SC1_AIEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 425 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
AnnaBridge 171:3a7713b1edbc 426 #define ADC_SC1_COCO_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 427 #define ADC_SC1_COCO_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 428 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
AnnaBridge 171:3a7713b1edbc 429
AnnaBridge 171:3a7713b1edbc 430 /* The count of ADC_SC1 */
AnnaBridge 171:3a7713b1edbc 431 #define ADC_SC1_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 432
AnnaBridge 171:3a7713b1edbc 433 /*! @name CFG1 - ADC Configuration Register 1 */
AnnaBridge 171:3a7713b1edbc 434 #define ADC_CFG1_ADICLK_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 435 #define ADC_CFG1_ADICLK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 436 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
AnnaBridge 171:3a7713b1edbc 437 #define ADC_CFG1_MODE_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 438 #define ADC_CFG1_MODE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 439 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 440 #define ADC_CFG1_ADLSMP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 441 #define ADC_CFG1_ADLSMP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 442 #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
AnnaBridge 171:3a7713b1edbc 443 #define ADC_CFG1_ADIV_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 444 #define ADC_CFG1_ADIV_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 445 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
AnnaBridge 171:3a7713b1edbc 446 #define ADC_CFG1_ADLPC_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 447 #define ADC_CFG1_ADLPC_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 448 #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
AnnaBridge 171:3a7713b1edbc 449
AnnaBridge 171:3a7713b1edbc 450 /*! @name CFG2 - ADC Configuration Register 2 */
AnnaBridge 171:3a7713b1edbc 451 #define ADC_CFG2_ADLSTS_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 452 #define ADC_CFG2_ADLSTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 453 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
AnnaBridge 171:3a7713b1edbc 454 #define ADC_CFG2_ADHSC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 455 #define ADC_CFG2_ADHSC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 456 #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
AnnaBridge 171:3a7713b1edbc 457 #define ADC_CFG2_ADACKEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 458 #define ADC_CFG2_ADACKEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 459 #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
AnnaBridge 171:3a7713b1edbc 460 #define ADC_CFG2_MUXSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 461 #define ADC_CFG2_MUXSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 462 #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
AnnaBridge 171:3a7713b1edbc 463
AnnaBridge 171:3a7713b1edbc 464 /*! @name R - ADC Data Result Register */
AnnaBridge 171:3a7713b1edbc 465 #define ADC_R_D_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 466 #define ADC_R_D_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 467 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
AnnaBridge 171:3a7713b1edbc 468
AnnaBridge 171:3a7713b1edbc 469 /* The count of ADC_R */
AnnaBridge 171:3a7713b1edbc 470 #define ADC_R_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 471
AnnaBridge 171:3a7713b1edbc 472 /*! @name CV1 - Compare Value Registers */
AnnaBridge 171:3a7713b1edbc 473 #define ADC_CV1_CV_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 474 #define ADC_CV1_CV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 475 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
AnnaBridge 171:3a7713b1edbc 476
AnnaBridge 171:3a7713b1edbc 477 /*! @name CV2 - Compare Value Registers */
AnnaBridge 171:3a7713b1edbc 478 #define ADC_CV2_CV_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 479 #define ADC_CV2_CV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 480 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
AnnaBridge 171:3a7713b1edbc 481
AnnaBridge 171:3a7713b1edbc 482 /*! @name SC2 - Status and Control Register 2 */
AnnaBridge 171:3a7713b1edbc 483 #define ADC_SC2_REFSEL_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 484 #define ADC_SC2_REFSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 485 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
AnnaBridge 171:3a7713b1edbc 486 #define ADC_SC2_DMAEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 487 #define ADC_SC2_DMAEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 488 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 489 #define ADC_SC2_ACREN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 490 #define ADC_SC2_ACREN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 491 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
AnnaBridge 171:3a7713b1edbc 492 #define ADC_SC2_ACFGT_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 493 #define ADC_SC2_ACFGT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 494 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
AnnaBridge 171:3a7713b1edbc 495 #define ADC_SC2_ACFE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 496 #define ADC_SC2_ACFE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 497 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
AnnaBridge 171:3a7713b1edbc 498 #define ADC_SC2_ADTRG_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 499 #define ADC_SC2_ADTRG_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 500 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
AnnaBridge 171:3a7713b1edbc 501 #define ADC_SC2_ADACT_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 502 #define ADC_SC2_ADACT_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 503 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
AnnaBridge 171:3a7713b1edbc 504
AnnaBridge 171:3a7713b1edbc 505 /*! @name SC3 - Status and Control Register 3 */
AnnaBridge 171:3a7713b1edbc 506 #define ADC_SC3_AVGS_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 507 #define ADC_SC3_AVGS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 508 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
AnnaBridge 171:3a7713b1edbc 509 #define ADC_SC3_AVGE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 510 #define ADC_SC3_AVGE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 511 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
AnnaBridge 171:3a7713b1edbc 512 #define ADC_SC3_ADCO_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 513 #define ADC_SC3_ADCO_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 514 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
AnnaBridge 171:3a7713b1edbc 515 #define ADC_SC3_CALF_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 516 #define ADC_SC3_CALF_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 517 #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
AnnaBridge 171:3a7713b1edbc 518 #define ADC_SC3_CAL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 519 #define ADC_SC3_CAL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 520 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
AnnaBridge 171:3a7713b1edbc 521
AnnaBridge 171:3a7713b1edbc 522 /*! @name OFS - ADC Offset Correction Register */
AnnaBridge 171:3a7713b1edbc 523 #define ADC_OFS_OFS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 524 #define ADC_OFS_OFS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 525 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
AnnaBridge 171:3a7713b1edbc 526
AnnaBridge 171:3a7713b1edbc 527 /*! @name PG - ADC Plus-Side Gain Register */
AnnaBridge 171:3a7713b1edbc 528 #define ADC_PG_PG_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 529 #define ADC_PG_PG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 530 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
AnnaBridge 171:3a7713b1edbc 531
AnnaBridge 171:3a7713b1edbc 532 /*! @name MG - ADC Minus-Side Gain Register */
AnnaBridge 171:3a7713b1edbc 533 #define ADC_MG_MG_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 534 #define ADC_MG_MG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 535 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
AnnaBridge 171:3a7713b1edbc 536
AnnaBridge 171:3a7713b1edbc 537 /*! @name CLPD - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 538 #define ADC_CLPD_CLPD_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 539 #define ADC_CLPD_CLPD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 540 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
AnnaBridge 171:3a7713b1edbc 541
AnnaBridge 171:3a7713b1edbc 542 /*! @name CLPS - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 543 #define ADC_CLPS_CLPS_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 544 #define ADC_CLPS_CLPS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 545 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
AnnaBridge 171:3a7713b1edbc 546
AnnaBridge 171:3a7713b1edbc 547 /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 548 #define ADC_CLP4_CLP4_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 549 #define ADC_CLP4_CLP4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 550 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
AnnaBridge 171:3a7713b1edbc 551
AnnaBridge 171:3a7713b1edbc 552 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 553 #define ADC_CLP3_CLP3_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 554 #define ADC_CLP3_CLP3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 555 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
AnnaBridge 171:3a7713b1edbc 556
AnnaBridge 171:3a7713b1edbc 557 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 558 #define ADC_CLP2_CLP2_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 559 #define ADC_CLP2_CLP2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 560 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
AnnaBridge 171:3a7713b1edbc 561
AnnaBridge 171:3a7713b1edbc 562 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 563 #define ADC_CLP1_CLP1_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 564 #define ADC_CLP1_CLP1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 565 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
AnnaBridge 171:3a7713b1edbc 566
AnnaBridge 171:3a7713b1edbc 567 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 568 #define ADC_CLP0_CLP0_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 569 #define ADC_CLP0_CLP0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 570 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
AnnaBridge 171:3a7713b1edbc 571
AnnaBridge 171:3a7713b1edbc 572 /*! @name CLMD - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 573 #define ADC_CLMD_CLMD_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 574 #define ADC_CLMD_CLMD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 575 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
AnnaBridge 171:3a7713b1edbc 576
AnnaBridge 171:3a7713b1edbc 577 /*! @name CLMS - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 578 #define ADC_CLMS_CLMS_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 579 #define ADC_CLMS_CLMS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 580 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
AnnaBridge 171:3a7713b1edbc 581
AnnaBridge 171:3a7713b1edbc 582 /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 583 #define ADC_CLM4_CLM4_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 584 #define ADC_CLM4_CLM4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 585 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
AnnaBridge 171:3a7713b1edbc 586
AnnaBridge 171:3a7713b1edbc 587 /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 588 #define ADC_CLM3_CLM3_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 589 #define ADC_CLM3_CLM3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 590 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
AnnaBridge 171:3a7713b1edbc 591
AnnaBridge 171:3a7713b1edbc 592 /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 593 #define ADC_CLM2_CLM2_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 594 #define ADC_CLM2_CLM2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 595 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
AnnaBridge 171:3a7713b1edbc 596
AnnaBridge 171:3a7713b1edbc 597 /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 598 #define ADC_CLM1_CLM1_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 599 #define ADC_CLM1_CLM1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 600 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
AnnaBridge 171:3a7713b1edbc 601
AnnaBridge 171:3a7713b1edbc 602 /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 603 #define ADC_CLM0_CLM0_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 604 #define ADC_CLM0_CLM0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 605 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
AnnaBridge 171:3a7713b1edbc 606
AnnaBridge 171:3a7713b1edbc 607
AnnaBridge 171:3a7713b1edbc 608 /*!
AnnaBridge 171:3a7713b1edbc 609 * @}
AnnaBridge 171:3a7713b1edbc 610 */ /* end of group ADC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 611
AnnaBridge 171:3a7713b1edbc 612
AnnaBridge 171:3a7713b1edbc 613 /* ADC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 614 /** Peripheral ADC0 base address */
AnnaBridge 171:3a7713b1edbc 615 #define ADC0_BASE (0x4003B000u)
AnnaBridge 171:3a7713b1edbc 616 /** Peripheral ADC0 base pointer */
AnnaBridge 171:3a7713b1edbc 617 #define ADC0 ((ADC_Type *)ADC0_BASE)
AnnaBridge 171:3a7713b1edbc 618 /** Array initializer of ADC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 619 #define ADC_BASE_ADDRS { ADC0_BASE }
AnnaBridge 171:3a7713b1edbc 620 /** Array initializer of ADC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 621 #define ADC_BASE_PTRS { ADC0 }
AnnaBridge 171:3a7713b1edbc 622 /** Interrupt vectors for the ADC peripheral type */
AnnaBridge 171:3a7713b1edbc 623 #define ADC_IRQS { ADC0_IRQn }
AnnaBridge 171:3a7713b1edbc 624
AnnaBridge 171:3a7713b1edbc 625 /*!
AnnaBridge 171:3a7713b1edbc 626 * @}
AnnaBridge 171:3a7713b1edbc 627 */ /* end of group ADC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 628
AnnaBridge 171:3a7713b1edbc 629
AnnaBridge 171:3a7713b1edbc 630 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 631 -- CAU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 632 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 633
AnnaBridge 171:3a7713b1edbc 634 /*!
AnnaBridge 171:3a7713b1edbc 635 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 636 * @{
AnnaBridge 171:3a7713b1edbc 637 */
AnnaBridge 171:3a7713b1edbc 638
AnnaBridge 171:3a7713b1edbc 639 /** CAU - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 640 typedef struct {
AnnaBridge 171:3a7713b1edbc 641 __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 642 uint8_t RESERVED_0[2048];
AnnaBridge 171:3a7713b1edbc 643 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
AnnaBridge 171:3a7713b1edbc 644 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
AnnaBridge 171:3a7713b1edbc 645 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 646 uint8_t RESERVED_1[20];
AnnaBridge 171:3a7713b1edbc 647 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
AnnaBridge 171:3a7713b1edbc 648 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
AnnaBridge 171:3a7713b1edbc 649 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 650 uint8_t RESERVED_2[20];
AnnaBridge 171:3a7713b1edbc 651 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
AnnaBridge 171:3a7713b1edbc 652 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
AnnaBridge 171:3a7713b1edbc 653 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 654 uint8_t RESERVED_3[20];
AnnaBridge 171:3a7713b1edbc 655 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
AnnaBridge 171:3a7713b1edbc 656 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
AnnaBridge 171:3a7713b1edbc 657 __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 658 uint8_t RESERVED_4[84];
AnnaBridge 171:3a7713b1edbc 659 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
AnnaBridge 171:3a7713b1edbc 660 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
AnnaBridge 171:3a7713b1edbc 661 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 662 uint8_t RESERVED_5[20];
AnnaBridge 171:3a7713b1edbc 663 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
AnnaBridge 171:3a7713b1edbc 664 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
AnnaBridge 171:3a7713b1edbc 665 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 666 uint8_t RESERVED_6[276];
AnnaBridge 171:3a7713b1edbc 667 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
AnnaBridge 171:3a7713b1edbc 668 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
AnnaBridge 171:3a7713b1edbc 669 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 670 uint8_t RESERVED_7[20];
AnnaBridge 171:3a7713b1edbc 671 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
AnnaBridge 171:3a7713b1edbc 672 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
AnnaBridge 171:3a7713b1edbc 673 __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 674 } CAU_Type;
AnnaBridge 171:3a7713b1edbc 675
AnnaBridge 171:3a7713b1edbc 676 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 677 -- CAU Register Masks
AnnaBridge 171:3a7713b1edbc 678 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 679
AnnaBridge 171:3a7713b1edbc 680 /*!
AnnaBridge 171:3a7713b1edbc 681 * @addtogroup CAU_Register_Masks CAU Register Masks
AnnaBridge 171:3a7713b1edbc 682 * @{
AnnaBridge 171:3a7713b1edbc 683 */
AnnaBridge 171:3a7713b1edbc 684
AnnaBridge 171:3a7713b1edbc 685 /*! @name DIRECT - Direct access register 0..Direct access register 15 */
AnnaBridge 171:3a7713b1edbc 686 #define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 687 #define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 688 #define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
AnnaBridge 171:3a7713b1edbc 689 #define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 690 #define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 691 #define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
AnnaBridge 171:3a7713b1edbc 692 #define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 693 #define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 694 #define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
AnnaBridge 171:3a7713b1edbc 695 #define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 696 #define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 697 #define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
AnnaBridge 171:3a7713b1edbc 698 #define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 699 #define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 700 #define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
AnnaBridge 171:3a7713b1edbc 701 #define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 702 #define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 703 #define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
AnnaBridge 171:3a7713b1edbc 704 #define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 705 #define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 706 #define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
AnnaBridge 171:3a7713b1edbc 707 #define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 708 #define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 709 #define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
AnnaBridge 171:3a7713b1edbc 710 #define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 711 #define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 712 #define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
AnnaBridge 171:3a7713b1edbc 713 #define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 714 #define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 715 #define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
AnnaBridge 171:3a7713b1edbc 716 #define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 717 #define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 718 #define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
AnnaBridge 171:3a7713b1edbc 719 #define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 720 #define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 721 #define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
AnnaBridge 171:3a7713b1edbc 722 #define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 723 #define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 724 #define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
AnnaBridge 171:3a7713b1edbc 725 #define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 726 #define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 727 #define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
AnnaBridge 171:3a7713b1edbc 728 #define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 729 #define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 730 #define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
AnnaBridge 171:3a7713b1edbc 731 #define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 732 #define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 733 #define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
AnnaBridge 171:3a7713b1edbc 734
AnnaBridge 171:3a7713b1edbc 735 /* The count of CAU_DIRECT */
AnnaBridge 171:3a7713b1edbc 736 #define CAU_DIRECT_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 737
AnnaBridge 171:3a7713b1edbc 738 /*! @name LDR_CASR - Status register - Load Register command */
AnnaBridge 171:3a7713b1edbc 739 #define CAU_LDR_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 740 #define CAU_LDR_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 741 #define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 742 #define CAU_LDR_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 743 #define CAU_LDR_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 744 #define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 745 #define CAU_LDR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 746 #define CAU_LDR_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 747 #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 748
AnnaBridge 171:3a7713b1edbc 749 /*! @name LDR_CAA - Accumulator register - Load Register command */
AnnaBridge 171:3a7713b1edbc 750 #define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 751 #define CAU_LDR_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 752 #define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 753
AnnaBridge 171:3a7713b1edbc 754 /*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */
AnnaBridge 171:3a7713b1edbc 755 #define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 756 #define CAU_LDR_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 757 #define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 758 #define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 759 #define CAU_LDR_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 760 #define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 761 #define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 762 #define CAU_LDR_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 763 #define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 764 #define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 765 #define CAU_LDR_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 766 #define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 767 #define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 768 #define CAU_LDR_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 769 #define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 770 #define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 771 #define CAU_LDR_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 772 #define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 773 #define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 774 #define CAU_LDR_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 775 #define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 776 #define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 777 #define CAU_LDR_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 778 #define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 779 #define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 780 #define CAU_LDR_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 781 #define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 782
AnnaBridge 171:3a7713b1edbc 783 /* The count of CAU_LDR_CA */
AnnaBridge 171:3a7713b1edbc 784 #define CAU_LDR_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 785
AnnaBridge 171:3a7713b1edbc 786 /*! @name STR_CASR - Status register - Store Register command */
AnnaBridge 171:3a7713b1edbc 787 #define CAU_STR_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 788 #define CAU_STR_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 789 #define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 790 #define CAU_STR_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 791 #define CAU_STR_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 792 #define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 793 #define CAU_STR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 794 #define CAU_STR_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 795 #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 796
AnnaBridge 171:3a7713b1edbc 797 /*! @name STR_CAA - Accumulator register - Store Register command */
AnnaBridge 171:3a7713b1edbc 798 #define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 799 #define CAU_STR_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 800 #define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 801
AnnaBridge 171:3a7713b1edbc 802 /*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */
AnnaBridge 171:3a7713b1edbc 803 #define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 804 #define CAU_STR_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 805 #define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 806 #define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 807 #define CAU_STR_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 808 #define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 809 #define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 810 #define CAU_STR_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 811 #define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 812 #define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 813 #define CAU_STR_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 814 #define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 815 #define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 816 #define CAU_STR_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 817 #define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 818 #define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 819 #define CAU_STR_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 820 #define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 821 #define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 822 #define CAU_STR_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 823 #define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 824 #define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 825 #define CAU_STR_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 826 #define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 827 #define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 828 #define CAU_STR_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 829 #define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 830
AnnaBridge 171:3a7713b1edbc 831 /* The count of CAU_STR_CA */
AnnaBridge 171:3a7713b1edbc 832 #define CAU_STR_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 833
AnnaBridge 171:3a7713b1edbc 834 /*! @name ADR_CASR - Status register - Add Register command */
AnnaBridge 171:3a7713b1edbc 835 #define CAU_ADR_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 836 #define CAU_ADR_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 837 #define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 838 #define CAU_ADR_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 839 #define CAU_ADR_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 840 #define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 841 #define CAU_ADR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 842 #define CAU_ADR_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 843 #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 844
AnnaBridge 171:3a7713b1edbc 845 /*! @name ADR_CAA - Accumulator register - Add to register command */
AnnaBridge 171:3a7713b1edbc 846 #define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 847 #define CAU_ADR_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 848 #define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 849
AnnaBridge 171:3a7713b1edbc 850 /*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */
AnnaBridge 171:3a7713b1edbc 851 #define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 852 #define CAU_ADR_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 853 #define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 854 #define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 855 #define CAU_ADR_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 856 #define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 857 #define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 858 #define CAU_ADR_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 859 #define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 860 #define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 861 #define CAU_ADR_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 862 #define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 863 #define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 864 #define CAU_ADR_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 865 #define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 866 #define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 867 #define CAU_ADR_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 868 #define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 869 #define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 870 #define CAU_ADR_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 871 #define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 872 #define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 873 #define CAU_ADR_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 874 #define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 875 #define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 876 #define CAU_ADR_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 877 #define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 878
AnnaBridge 171:3a7713b1edbc 879 /* The count of CAU_ADR_CA */
AnnaBridge 171:3a7713b1edbc 880 #define CAU_ADR_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 881
AnnaBridge 171:3a7713b1edbc 882 /*! @name RADR_CASR - Status register - Reverse and Add to Register command */
AnnaBridge 171:3a7713b1edbc 883 #define CAU_RADR_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 884 #define CAU_RADR_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 885 #define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 886 #define CAU_RADR_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 887 #define CAU_RADR_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 888 #define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 889 #define CAU_RADR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 890 #define CAU_RADR_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 891 #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 892
AnnaBridge 171:3a7713b1edbc 893 /*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */
AnnaBridge 171:3a7713b1edbc 894 #define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 895 #define CAU_RADR_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 896 #define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 897
AnnaBridge 171:3a7713b1edbc 898 /*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */
AnnaBridge 171:3a7713b1edbc 899 #define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 900 #define CAU_RADR_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 901 #define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 902 #define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 903 #define CAU_RADR_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 904 #define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 905 #define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 906 #define CAU_RADR_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 907 #define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 908 #define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 909 #define CAU_RADR_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 910 #define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 911 #define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 912 #define CAU_RADR_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 913 #define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 914 #define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 915 #define CAU_RADR_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 916 #define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 917 #define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 918 #define CAU_RADR_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 919 #define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 920 #define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 921 #define CAU_RADR_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 922 #define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 923 #define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 924 #define CAU_RADR_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 925 #define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 926
AnnaBridge 171:3a7713b1edbc 927 /* The count of CAU_RADR_CA */
AnnaBridge 171:3a7713b1edbc 928 #define CAU_RADR_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 929
AnnaBridge 171:3a7713b1edbc 930 /*! @name XOR_CASR - Status register - Exclusive Or command */
AnnaBridge 171:3a7713b1edbc 931 #define CAU_XOR_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 932 #define CAU_XOR_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 933 #define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 934 #define CAU_XOR_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 935 #define CAU_XOR_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 936 #define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 937 #define CAU_XOR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 938 #define CAU_XOR_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 939 #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 940
AnnaBridge 171:3a7713b1edbc 941 /*! @name XOR_CAA - Accumulator register - Exclusive Or command */
AnnaBridge 171:3a7713b1edbc 942 #define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 943 #define CAU_XOR_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 944 #define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 945
AnnaBridge 171:3a7713b1edbc 946 /*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */
AnnaBridge 171:3a7713b1edbc 947 #define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 948 #define CAU_XOR_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 949 #define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 950 #define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 951 #define CAU_XOR_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 952 #define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 953 #define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 954 #define CAU_XOR_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 955 #define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 956 #define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 957 #define CAU_XOR_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 958 #define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 959 #define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 960 #define CAU_XOR_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 961 #define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 962 #define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 963 #define CAU_XOR_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 964 #define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 965 #define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 966 #define CAU_XOR_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 967 #define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 968 #define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 969 #define CAU_XOR_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 970 #define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 971 #define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 972 #define CAU_XOR_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 973 #define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 974
AnnaBridge 171:3a7713b1edbc 975 /* The count of CAU_XOR_CA */
AnnaBridge 171:3a7713b1edbc 976 #define CAU_XOR_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 977
AnnaBridge 171:3a7713b1edbc 978 /*! @name ROTL_CASR - Status register - Rotate Left command */
AnnaBridge 171:3a7713b1edbc 979 #define CAU_ROTL_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 980 #define CAU_ROTL_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 981 #define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 982 #define CAU_ROTL_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 983 #define CAU_ROTL_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 984 #define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 985 #define CAU_ROTL_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 986 #define CAU_ROTL_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 987 #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 988
AnnaBridge 171:3a7713b1edbc 989 /*! @name ROTL_CAA - Accumulator register - Rotate Left command */
AnnaBridge 171:3a7713b1edbc 990 #define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 991 #define CAU_ROTL_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 992 #define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 993
AnnaBridge 171:3a7713b1edbc 994 /*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */
AnnaBridge 171:3a7713b1edbc 995 #define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 996 #define CAU_ROTL_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 997 #define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 998 #define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 999 #define CAU_ROTL_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1000 #define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 1001 #define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1002 #define CAU_ROTL_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1003 #define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 1004 #define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1005 #define CAU_ROTL_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1006 #define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 1007 #define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1008 #define CAU_ROTL_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1009 #define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 1010 #define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1011 #define CAU_ROTL_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1012 #define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 1013 #define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1014 #define CAU_ROTL_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1015 #define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 1016 #define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1017 #define CAU_ROTL_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1018 #define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 1019 #define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1020 #define CAU_ROTL_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1021 #define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 1022
AnnaBridge 171:3a7713b1edbc 1023 /* The count of CAU_ROTL_CA */
AnnaBridge 171:3a7713b1edbc 1024 #define CAU_ROTL_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 1025
AnnaBridge 171:3a7713b1edbc 1026 /*! @name AESC_CASR - Status register - AES Column Operation command */
AnnaBridge 171:3a7713b1edbc 1027 #define CAU_AESC_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1028 #define CAU_AESC_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1029 #define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 1030 #define CAU_AESC_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1031 #define CAU_AESC_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1032 #define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 1033 #define CAU_AESC_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 1034 #define CAU_AESC_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1035 #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 1036
AnnaBridge 171:3a7713b1edbc 1037 /*! @name AESC_CAA - Accumulator register - AES Column Operation command */
AnnaBridge 171:3a7713b1edbc 1038 #define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1039 #define CAU_AESC_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1040 #define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 1041
AnnaBridge 171:3a7713b1edbc 1042 /*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */
AnnaBridge 171:3a7713b1edbc 1043 #define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1044 #define CAU_AESC_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1045 #define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 1046 #define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1047 #define CAU_AESC_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1048 #define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 1049 #define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1050 #define CAU_AESC_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1051 #define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 1052 #define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1053 #define CAU_AESC_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1054 #define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 1055 #define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1056 #define CAU_AESC_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1057 #define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 1058 #define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1059 #define CAU_AESC_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1060 #define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 1061 #define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1062 #define CAU_AESC_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1063 #define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 1064 #define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1065 #define CAU_AESC_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1066 #define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 1067 #define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1068 #define CAU_AESC_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1069 #define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 1070
AnnaBridge 171:3a7713b1edbc 1071 /* The count of CAU_AESC_CA */
AnnaBridge 171:3a7713b1edbc 1072 #define CAU_AESC_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 1073
AnnaBridge 171:3a7713b1edbc 1074 /*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */
AnnaBridge 171:3a7713b1edbc 1075 #define CAU_AESIC_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1076 #define CAU_AESIC_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1077 #define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 1078 #define CAU_AESIC_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1079 #define CAU_AESIC_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1080 #define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 1081 #define CAU_AESIC_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 1082 #define CAU_AESIC_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1083 #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 1084
AnnaBridge 171:3a7713b1edbc 1085 /*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */
AnnaBridge 171:3a7713b1edbc 1086 #define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1087 #define CAU_AESIC_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1088 #define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 1089
AnnaBridge 171:3a7713b1edbc 1090 /*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */
AnnaBridge 171:3a7713b1edbc 1091 #define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1092 #define CAU_AESIC_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1093 #define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 1094 #define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1095 #define CAU_AESIC_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1096 #define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 1097 #define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1098 #define CAU_AESIC_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1099 #define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 1100 #define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1101 #define CAU_AESIC_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1102 #define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 1103 #define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1104 #define CAU_AESIC_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1105 #define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 1106 #define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1107 #define CAU_AESIC_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1108 #define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 1109 #define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1110 #define CAU_AESIC_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1111 #define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 1112 #define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1113 #define CAU_AESIC_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1114 #define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 1115 #define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1116 #define CAU_AESIC_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1117 #define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 1118
AnnaBridge 171:3a7713b1edbc 1119 /* The count of CAU_AESIC_CA */
AnnaBridge 171:3a7713b1edbc 1120 #define CAU_AESIC_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 1121
AnnaBridge 171:3a7713b1edbc 1122
AnnaBridge 171:3a7713b1edbc 1123 /*!
AnnaBridge 171:3a7713b1edbc 1124 * @}
AnnaBridge 171:3a7713b1edbc 1125 */ /* end of group CAU_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1126
AnnaBridge 171:3a7713b1edbc 1127
AnnaBridge 171:3a7713b1edbc 1128 /* CAU - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1129 /** Peripheral CAU base address */
AnnaBridge 171:3a7713b1edbc 1130 #define CAU_BASE (0xE0081000u)
AnnaBridge 171:3a7713b1edbc 1131 /** Peripheral CAU base pointer */
AnnaBridge 171:3a7713b1edbc 1132 #define CAU ((CAU_Type *)CAU_BASE)
AnnaBridge 171:3a7713b1edbc 1133 /** Array initializer of CAU peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 1134 #define CAU_BASE_ADDRS { CAU_BASE }
AnnaBridge 171:3a7713b1edbc 1135 /** Array initializer of CAU peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1136 #define CAU_BASE_PTRS { CAU }
AnnaBridge 171:3a7713b1edbc 1137
AnnaBridge 171:3a7713b1edbc 1138 /*!
AnnaBridge 171:3a7713b1edbc 1139 * @}
AnnaBridge 171:3a7713b1edbc 1140 */ /* end of group CAU_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1141
AnnaBridge 171:3a7713b1edbc 1142
AnnaBridge 171:3a7713b1edbc 1143 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1144 -- CMP Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1145 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1146
AnnaBridge 171:3a7713b1edbc 1147 /*!
AnnaBridge 171:3a7713b1edbc 1148 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1149 * @{
AnnaBridge 171:3a7713b1edbc 1150 */
AnnaBridge 171:3a7713b1edbc 1151
AnnaBridge 171:3a7713b1edbc 1152 /** CMP - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1153 typedef struct {
AnnaBridge 171:3a7713b1edbc 1154 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1155 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 1156 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 1157 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 1158 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1159 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 1160 } CMP_Type;
AnnaBridge 171:3a7713b1edbc 1161
AnnaBridge 171:3a7713b1edbc 1162 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1163 -- CMP Register Masks
AnnaBridge 171:3a7713b1edbc 1164 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1165
AnnaBridge 171:3a7713b1edbc 1166 /*!
AnnaBridge 171:3a7713b1edbc 1167 * @addtogroup CMP_Register_Masks CMP Register Masks
AnnaBridge 171:3a7713b1edbc 1168 * @{
AnnaBridge 171:3a7713b1edbc 1169 */
AnnaBridge 171:3a7713b1edbc 1170
AnnaBridge 171:3a7713b1edbc 1171 /*! @name CR0 - CMP Control Register 0 */
AnnaBridge 171:3a7713b1edbc 1172 #define CMP_CR0_HYSTCTR_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 1173 #define CMP_CR0_HYSTCTR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1174 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
AnnaBridge 171:3a7713b1edbc 1175 #define CMP_CR0_FILTER_CNT_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 1176 #define CMP_CR0_FILTER_CNT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1177 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
AnnaBridge 171:3a7713b1edbc 1178
AnnaBridge 171:3a7713b1edbc 1179 /*! @name CR1 - CMP Control Register 1 */
AnnaBridge 171:3a7713b1edbc 1180 #define CMP_CR1_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1181 #define CMP_CR1_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1182 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
AnnaBridge 171:3a7713b1edbc 1183 #define CMP_CR1_OPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1184 #define CMP_CR1_OPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1185 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
AnnaBridge 171:3a7713b1edbc 1186 #define CMP_CR1_COS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1187 #define CMP_CR1_COS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1188 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
AnnaBridge 171:3a7713b1edbc 1189 #define CMP_CR1_INV_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1190 #define CMP_CR1_INV_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1191 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
AnnaBridge 171:3a7713b1edbc 1192 #define CMP_CR1_PMODE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1193 #define CMP_CR1_PMODE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1194 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
AnnaBridge 171:3a7713b1edbc 1195 #define CMP_CR1_WE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1196 #define CMP_CR1_WE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1197 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
AnnaBridge 171:3a7713b1edbc 1198 #define CMP_CR1_SE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1199 #define CMP_CR1_SE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1200 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
AnnaBridge 171:3a7713b1edbc 1201
AnnaBridge 171:3a7713b1edbc 1202 /*! @name FPR - CMP Filter Period Register */
AnnaBridge 171:3a7713b1edbc 1203 #define CMP_FPR_FILT_PER_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1204 #define CMP_FPR_FILT_PER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1205 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
AnnaBridge 171:3a7713b1edbc 1206
AnnaBridge 171:3a7713b1edbc 1207 /*! @name SCR - CMP Status and Control Register */
AnnaBridge 171:3a7713b1edbc 1208 #define CMP_SCR_COUT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1209 #define CMP_SCR_COUT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1210 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
AnnaBridge 171:3a7713b1edbc 1211 #define CMP_SCR_CFF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1212 #define CMP_SCR_CFF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1213 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
AnnaBridge 171:3a7713b1edbc 1214 #define CMP_SCR_CFR_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1215 #define CMP_SCR_CFR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1216 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
AnnaBridge 171:3a7713b1edbc 1217 #define CMP_SCR_IEF_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1218 #define CMP_SCR_IEF_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1219 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
AnnaBridge 171:3a7713b1edbc 1220 #define CMP_SCR_IER_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1221 #define CMP_SCR_IER_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1222 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
AnnaBridge 171:3a7713b1edbc 1223 #define CMP_SCR_DMAEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1224 #define CMP_SCR_DMAEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1225 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 1226
AnnaBridge 171:3a7713b1edbc 1227 /*! @name DACCR - DAC Control Register */
AnnaBridge 171:3a7713b1edbc 1228 #define CMP_DACCR_VOSEL_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 1229 #define CMP_DACCR_VOSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1230 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
AnnaBridge 171:3a7713b1edbc 1231 #define CMP_DACCR_VRSEL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1232 #define CMP_DACCR_VRSEL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1233 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
AnnaBridge 171:3a7713b1edbc 1234 #define CMP_DACCR_DACEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1235 #define CMP_DACCR_DACEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1236 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
AnnaBridge 171:3a7713b1edbc 1237
AnnaBridge 171:3a7713b1edbc 1238 /*! @name MUXCR - MUX Control Register */
AnnaBridge 171:3a7713b1edbc 1239 #define CMP_MUXCR_MSEL_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 1240 #define CMP_MUXCR_MSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1241 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
AnnaBridge 171:3a7713b1edbc 1242 #define CMP_MUXCR_PSEL_MASK (0x38U)
AnnaBridge 171:3a7713b1edbc 1243 #define CMP_MUXCR_PSEL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1244 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
AnnaBridge 171:3a7713b1edbc 1245 #define CMP_MUXCR_PSTM_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1246 #define CMP_MUXCR_PSTM_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1247 #define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
AnnaBridge 171:3a7713b1edbc 1248
AnnaBridge 171:3a7713b1edbc 1249
AnnaBridge 171:3a7713b1edbc 1250 /*!
AnnaBridge 171:3a7713b1edbc 1251 * @}
AnnaBridge 171:3a7713b1edbc 1252 */ /* end of group CMP_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1253
AnnaBridge 171:3a7713b1edbc 1254
AnnaBridge 171:3a7713b1edbc 1255 /* CMP - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1256 /** Peripheral CMP0 base address */
AnnaBridge 171:3a7713b1edbc 1257 #define CMP0_BASE (0x40073000u)
AnnaBridge 171:3a7713b1edbc 1258 /** Peripheral CMP0 base pointer */
AnnaBridge 171:3a7713b1edbc 1259 #define CMP0 ((CMP_Type *)CMP0_BASE)
AnnaBridge 171:3a7713b1edbc 1260 /** Peripheral CMP1 base address */
AnnaBridge 171:3a7713b1edbc 1261 #define CMP1_BASE (0x40073008u)
AnnaBridge 171:3a7713b1edbc 1262 /** Peripheral CMP1 base pointer */
AnnaBridge 171:3a7713b1edbc 1263 #define CMP1 ((CMP_Type *)CMP1_BASE)
AnnaBridge 171:3a7713b1edbc 1264 /** Array initializer of CMP peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 1265 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE }
AnnaBridge 171:3a7713b1edbc 1266 /** Array initializer of CMP peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1267 #define CMP_BASE_PTRS { CMP0, CMP1 }
AnnaBridge 171:3a7713b1edbc 1268 /** Interrupt vectors for the CMP peripheral type */
AnnaBridge 171:3a7713b1edbc 1269 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
AnnaBridge 171:3a7713b1edbc 1270
AnnaBridge 171:3a7713b1edbc 1271 /*!
AnnaBridge 171:3a7713b1edbc 1272 * @}
AnnaBridge 171:3a7713b1edbc 1273 */ /* end of group CMP_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1274
AnnaBridge 171:3a7713b1edbc 1275
AnnaBridge 171:3a7713b1edbc 1276 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1277 -- CMT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1278 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1279
AnnaBridge 171:3a7713b1edbc 1280 /*!
AnnaBridge 171:3a7713b1edbc 1281 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1282 * @{
AnnaBridge 171:3a7713b1edbc 1283 */
AnnaBridge 171:3a7713b1edbc 1284
AnnaBridge 171:3a7713b1edbc 1285 /** CMT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1286 typedef struct {
AnnaBridge 171:3a7713b1edbc 1287 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1288 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 1289 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 1290 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 1291 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1292 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 1293 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 1294 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 1295 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1296 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 1297 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 1298 __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 1299 } CMT_Type;
AnnaBridge 171:3a7713b1edbc 1300
AnnaBridge 171:3a7713b1edbc 1301 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1302 -- CMT Register Masks
AnnaBridge 171:3a7713b1edbc 1303 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1304
AnnaBridge 171:3a7713b1edbc 1305 /*!
AnnaBridge 171:3a7713b1edbc 1306 * @addtogroup CMT_Register_Masks CMT Register Masks
AnnaBridge 171:3a7713b1edbc 1307 * @{
AnnaBridge 171:3a7713b1edbc 1308 */
AnnaBridge 171:3a7713b1edbc 1309
AnnaBridge 171:3a7713b1edbc 1310 /*! @name CGH1 - CMT Carrier Generator High Data Register 1 */
AnnaBridge 171:3a7713b1edbc 1311 #define CMT_CGH1_PH_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1312 #define CMT_CGH1_PH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1313 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
AnnaBridge 171:3a7713b1edbc 1314
AnnaBridge 171:3a7713b1edbc 1315 /*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */
AnnaBridge 171:3a7713b1edbc 1316 #define CMT_CGL1_PL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1317 #define CMT_CGL1_PL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1318 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
AnnaBridge 171:3a7713b1edbc 1319
AnnaBridge 171:3a7713b1edbc 1320 /*! @name CGH2 - CMT Carrier Generator High Data Register 2 */
AnnaBridge 171:3a7713b1edbc 1321 #define CMT_CGH2_SH_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1322 #define CMT_CGH2_SH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1323 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
AnnaBridge 171:3a7713b1edbc 1324
AnnaBridge 171:3a7713b1edbc 1325 /*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */
AnnaBridge 171:3a7713b1edbc 1326 #define CMT_CGL2_SL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1327 #define CMT_CGL2_SL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1328 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
AnnaBridge 171:3a7713b1edbc 1329
AnnaBridge 171:3a7713b1edbc 1330 /*! @name OC - CMT Output Control Register */
AnnaBridge 171:3a7713b1edbc 1331 #define CMT_OC_IROPEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1332 #define CMT_OC_IROPEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1333 #define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
AnnaBridge 171:3a7713b1edbc 1334 #define CMT_OC_CMTPOL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1335 #define CMT_OC_CMTPOL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1336 #define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
AnnaBridge 171:3a7713b1edbc 1337 #define CMT_OC_IROL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1338 #define CMT_OC_IROL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1339 #define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
AnnaBridge 171:3a7713b1edbc 1340
AnnaBridge 171:3a7713b1edbc 1341 /*! @name MSC - CMT Modulator Status and Control Register */
AnnaBridge 171:3a7713b1edbc 1342 #define CMT_MSC_MCGEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1343 #define CMT_MSC_MCGEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1344 #define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
AnnaBridge 171:3a7713b1edbc 1345 #define CMT_MSC_EOCIE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1346 #define CMT_MSC_EOCIE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1347 #define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
AnnaBridge 171:3a7713b1edbc 1348 #define CMT_MSC_FSK_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1349 #define CMT_MSC_FSK_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1350 #define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
AnnaBridge 171:3a7713b1edbc 1351 #define CMT_MSC_BASE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1352 #define CMT_MSC_BASE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1353 #define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
AnnaBridge 171:3a7713b1edbc 1354 #define CMT_MSC_EXSPC_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1355 #define CMT_MSC_EXSPC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1356 #define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
AnnaBridge 171:3a7713b1edbc 1357 #define CMT_MSC_CMTDIV_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 1358 #define CMT_MSC_CMTDIV_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1359 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
AnnaBridge 171:3a7713b1edbc 1360 #define CMT_MSC_EOCF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1361 #define CMT_MSC_EOCF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1362 #define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
AnnaBridge 171:3a7713b1edbc 1363
AnnaBridge 171:3a7713b1edbc 1364 /*! @name CMD1 - CMT Modulator Data Register Mark High */
AnnaBridge 171:3a7713b1edbc 1365 #define CMT_CMD1_MB_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1366 #define CMT_CMD1_MB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1367 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
AnnaBridge 171:3a7713b1edbc 1368
AnnaBridge 171:3a7713b1edbc 1369 /*! @name CMD2 - CMT Modulator Data Register Mark Low */
AnnaBridge 171:3a7713b1edbc 1370 #define CMT_CMD2_MB_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1371 #define CMT_CMD2_MB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1372 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
AnnaBridge 171:3a7713b1edbc 1373
AnnaBridge 171:3a7713b1edbc 1374 /*! @name CMD3 - CMT Modulator Data Register Space High */
AnnaBridge 171:3a7713b1edbc 1375 #define CMT_CMD3_SB_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1376 #define CMT_CMD3_SB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1377 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
AnnaBridge 171:3a7713b1edbc 1378
AnnaBridge 171:3a7713b1edbc 1379 /*! @name CMD4 - CMT Modulator Data Register Space Low */
AnnaBridge 171:3a7713b1edbc 1380 #define CMT_CMD4_SB_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1381 #define CMT_CMD4_SB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1382 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
AnnaBridge 171:3a7713b1edbc 1383
AnnaBridge 171:3a7713b1edbc 1384 /*! @name PPS - CMT Primary Prescaler Register */
AnnaBridge 171:3a7713b1edbc 1385 #define CMT_PPS_PPSDIV_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 1386 #define CMT_PPS_PPSDIV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1387 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
AnnaBridge 171:3a7713b1edbc 1388
AnnaBridge 171:3a7713b1edbc 1389 /*! @name DMA - CMT Direct Memory Access Register */
AnnaBridge 171:3a7713b1edbc 1390 #define CMT_DMA_DMA_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1391 #define CMT_DMA_DMA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1392 #define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
AnnaBridge 171:3a7713b1edbc 1393
AnnaBridge 171:3a7713b1edbc 1394
AnnaBridge 171:3a7713b1edbc 1395 /*!
AnnaBridge 171:3a7713b1edbc 1396 * @}
AnnaBridge 171:3a7713b1edbc 1397 */ /* end of group CMT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1398
AnnaBridge 171:3a7713b1edbc 1399
AnnaBridge 171:3a7713b1edbc 1400 /* CMT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1401 /** Peripheral CMT base address */
AnnaBridge 171:3a7713b1edbc 1402 #define CMT_BASE (0x40062000u)
AnnaBridge 171:3a7713b1edbc 1403 /** Peripheral CMT base pointer */
AnnaBridge 171:3a7713b1edbc 1404 #define CMT ((CMT_Type *)CMT_BASE)
AnnaBridge 171:3a7713b1edbc 1405 /** Array initializer of CMT peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 1406 #define CMT_BASE_ADDRS { CMT_BASE }
AnnaBridge 171:3a7713b1edbc 1407 /** Array initializer of CMT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1408 #define CMT_BASE_PTRS { CMT }
AnnaBridge 171:3a7713b1edbc 1409 /** Interrupt vectors for the CMT peripheral type */
AnnaBridge 171:3a7713b1edbc 1410 #define CMT_IRQS { CMT_IRQn }
AnnaBridge 171:3a7713b1edbc 1411
AnnaBridge 171:3a7713b1edbc 1412 /*!
AnnaBridge 171:3a7713b1edbc 1413 * @}
AnnaBridge 171:3a7713b1edbc 1414 */ /* end of group CMT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1415
AnnaBridge 171:3a7713b1edbc 1416
AnnaBridge 171:3a7713b1edbc 1417 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1418 -- CRC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1419 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1420
AnnaBridge 171:3a7713b1edbc 1421 /*!
AnnaBridge 171:3a7713b1edbc 1422 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1423 * @{
AnnaBridge 171:3a7713b1edbc 1424 */
AnnaBridge 171:3a7713b1edbc 1425
AnnaBridge 171:3a7713b1edbc 1426 /** CRC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1427 typedef struct {
AnnaBridge 171:3a7713b1edbc 1428 union { /* offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1429 struct { /* offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1430 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1431 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 1432 } ACCESS16BIT;
AnnaBridge 171:3a7713b1edbc 1433 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1434 struct { /* offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1435 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1436 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 1437 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 1438 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 1439 } ACCESS8BIT;
AnnaBridge 171:3a7713b1edbc 1440 };
AnnaBridge 171:3a7713b1edbc 1441 union { /* offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1442 struct { /* offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1443 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1444 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 1445 } GPOLY_ACCESS16BIT;
AnnaBridge 171:3a7713b1edbc 1446 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1447 struct { /* offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1448 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1449 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 1450 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 1451 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 1452 } GPOLY_ACCESS8BIT;
AnnaBridge 171:3a7713b1edbc 1453 };
AnnaBridge 171:3a7713b1edbc 1454 union { /* offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1455 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1456 struct { /* offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1457 uint8_t RESERVED_0[3];
AnnaBridge 171:3a7713b1edbc 1458 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
AnnaBridge 171:3a7713b1edbc 1459 } CTRL_ACCESS8BIT;
AnnaBridge 171:3a7713b1edbc 1460 };
AnnaBridge 171:3a7713b1edbc 1461 } CRC_Type;
AnnaBridge 171:3a7713b1edbc 1462
AnnaBridge 171:3a7713b1edbc 1463 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1464 -- CRC Register Masks
AnnaBridge 171:3a7713b1edbc 1465 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1466
AnnaBridge 171:3a7713b1edbc 1467 /*!
AnnaBridge 171:3a7713b1edbc 1468 * @addtogroup CRC_Register_Masks CRC Register Masks
AnnaBridge 171:3a7713b1edbc 1469 * @{
AnnaBridge 171:3a7713b1edbc 1470 */
AnnaBridge 171:3a7713b1edbc 1471
AnnaBridge 171:3a7713b1edbc 1472 /*! @name DATAL - CRC_DATAL register. */
AnnaBridge 171:3a7713b1edbc 1473 #define CRC_DATAL_DATAL_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 1474 #define CRC_DATAL_DATAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1475 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
AnnaBridge 171:3a7713b1edbc 1476
AnnaBridge 171:3a7713b1edbc 1477 /*! @name DATAH - CRC_DATAH register. */
AnnaBridge 171:3a7713b1edbc 1478 #define CRC_DATAH_DATAH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 1479 #define CRC_DATAH_DATAH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1480 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
AnnaBridge 171:3a7713b1edbc 1481
AnnaBridge 171:3a7713b1edbc 1482 /*! @name DATA - CRC Data register */
AnnaBridge 171:3a7713b1edbc 1483 #define CRC_DATA_LL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1484 #define CRC_DATA_LL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1485 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
AnnaBridge 171:3a7713b1edbc 1486 #define CRC_DATA_LU_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 1487 #define CRC_DATA_LU_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1488 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
AnnaBridge 171:3a7713b1edbc 1489 #define CRC_DATA_HL_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 1490 #define CRC_DATA_HL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1491 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
AnnaBridge 171:3a7713b1edbc 1492 #define CRC_DATA_HU_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 1493 #define CRC_DATA_HU_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1494 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
AnnaBridge 171:3a7713b1edbc 1495
AnnaBridge 171:3a7713b1edbc 1496 /*! @name DATALL - CRC_DATALL register. */
AnnaBridge 171:3a7713b1edbc 1497 #define CRC_DATALL_DATALL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1498 #define CRC_DATALL_DATALL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1499 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
AnnaBridge 171:3a7713b1edbc 1500
AnnaBridge 171:3a7713b1edbc 1501 /*! @name DATALU - CRC_DATALU register. */
AnnaBridge 171:3a7713b1edbc 1502 #define CRC_DATALU_DATALU_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1503 #define CRC_DATALU_DATALU_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1504 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
AnnaBridge 171:3a7713b1edbc 1505
AnnaBridge 171:3a7713b1edbc 1506 /*! @name DATAHL - CRC_DATAHL register. */
AnnaBridge 171:3a7713b1edbc 1507 #define CRC_DATAHL_DATAHL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1508 #define CRC_DATAHL_DATAHL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1509 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
AnnaBridge 171:3a7713b1edbc 1510
AnnaBridge 171:3a7713b1edbc 1511 /*! @name DATAHU - CRC_DATAHU register. */
AnnaBridge 171:3a7713b1edbc 1512 #define CRC_DATAHU_DATAHU_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1513 #define CRC_DATAHU_DATAHU_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1514 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
AnnaBridge 171:3a7713b1edbc 1515
AnnaBridge 171:3a7713b1edbc 1516 /*! @name GPOLYL - CRC_GPOLYL register. */
AnnaBridge 171:3a7713b1edbc 1517 #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 1518 #define CRC_GPOLYL_GPOLYL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1519 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
AnnaBridge 171:3a7713b1edbc 1520
AnnaBridge 171:3a7713b1edbc 1521 /*! @name GPOLYH - CRC_GPOLYH register. */
AnnaBridge 171:3a7713b1edbc 1522 #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 1523 #define CRC_GPOLYH_GPOLYH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1524 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
AnnaBridge 171:3a7713b1edbc 1525
AnnaBridge 171:3a7713b1edbc 1526 /*! @name GPOLY - CRC Polynomial register */
AnnaBridge 171:3a7713b1edbc 1527 #define CRC_GPOLY_LOW_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 1528 #define CRC_GPOLY_LOW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1529 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
AnnaBridge 171:3a7713b1edbc 1530 #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 1531 #define CRC_GPOLY_HIGH_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1532 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
AnnaBridge 171:3a7713b1edbc 1533
AnnaBridge 171:3a7713b1edbc 1534 /*! @name GPOLYLL - CRC_GPOLYLL register. */
AnnaBridge 171:3a7713b1edbc 1535 #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1536 #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1537 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
AnnaBridge 171:3a7713b1edbc 1538
AnnaBridge 171:3a7713b1edbc 1539 /*! @name GPOLYLU - CRC_GPOLYLU register. */
AnnaBridge 171:3a7713b1edbc 1540 #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1541 #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1542 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
AnnaBridge 171:3a7713b1edbc 1543
AnnaBridge 171:3a7713b1edbc 1544 /*! @name GPOLYHL - CRC_GPOLYHL register. */
AnnaBridge 171:3a7713b1edbc 1545 #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1546 #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1547 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
AnnaBridge 171:3a7713b1edbc 1548
AnnaBridge 171:3a7713b1edbc 1549 /*! @name GPOLYHU - CRC_GPOLYHU register. */
AnnaBridge 171:3a7713b1edbc 1550 #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1551 #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1552 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
AnnaBridge 171:3a7713b1edbc 1553
AnnaBridge 171:3a7713b1edbc 1554 /*! @name CTRL - CRC Control register */
AnnaBridge 171:3a7713b1edbc 1555 #define CRC_CTRL_TCRC_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1556 #define CRC_CTRL_TCRC_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1557 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
AnnaBridge 171:3a7713b1edbc 1558 #define CRC_CTRL_WAS_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1559 #define CRC_CTRL_WAS_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1560 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
AnnaBridge 171:3a7713b1edbc 1561 #define CRC_CTRL_FXOR_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1562 #define CRC_CTRL_FXOR_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1563 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
AnnaBridge 171:3a7713b1edbc 1564 #define CRC_CTRL_TOTR_MASK (0x30000000U)
AnnaBridge 171:3a7713b1edbc 1565 #define CRC_CTRL_TOTR_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1566 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
AnnaBridge 171:3a7713b1edbc 1567 #define CRC_CTRL_TOT_MASK (0xC0000000U)
AnnaBridge 171:3a7713b1edbc 1568 #define CRC_CTRL_TOT_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1569 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
AnnaBridge 171:3a7713b1edbc 1570
AnnaBridge 171:3a7713b1edbc 1571 /*! @name CTRLHU - CRC_CTRLHU register. */
AnnaBridge 171:3a7713b1edbc 1572 #define CRC_CTRLHU_TCRC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1573 #define CRC_CTRLHU_TCRC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1574 #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
AnnaBridge 171:3a7713b1edbc 1575 #define CRC_CTRLHU_WAS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1576 #define CRC_CTRLHU_WAS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1577 #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
AnnaBridge 171:3a7713b1edbc 1578 #define CRC_CTRLHU_FXOR_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1579 #define CRC_CTRLHU_FXOR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1580 #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
AnnaBridge 171:3a7713b1edbc 1581 #define CRC_CTRLHU_TOTR_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 1582 #define CRC_CTRLHU_TOTR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1583 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
AnnaBridge 171:3a7713b1edbc 1584 #define CRC_CTRLHU_TOT_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 1585 #define CRC_CTRLHU_TOT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1586 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
AnnaBridge 171:3a7713b1edbc 1587
AnnaBridge 171:3a7713b1edbc 1588
AnnaBridge 171:3a7713b1edbc 1589 /*!
AnnaBridge 171:3a7713b1edbc 1590 * @}
AnnaBridge 171:3a7713b1edbc 1591 */ /* end of group CRC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1592
AnnaBridge 171:3a7713b1edbc 1593
AnnaBridge 171:3a7713b1edbc 1594 /* CRC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1595 /** Peripheral CRC base address */
AnnaBridge 171:3a7713b1edbc 1596 #define CRC_BASE (0x40032000u)
AnnaBridge 171:3a7713b1edbc 1597 /** Peripheral CRC base pointer */
AnnaBridge 171:3a7713b1edbc 1598 #define CRC0 ((CRC_Type *)CRC_BASE)
AnnaBridge 171:3a7713b1edbc 1599 /** Array initializer of CRC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 1600 #define CRC_BASE_ADDRS { CRC_BASE }
AnnaBridge 171:3a7713b1edbc 1601 /** Array initializer of CRC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1602 #define CRC_BASE_PTRS { CRC0 }
AnnaBridge 171:3a7713b1edbc 1603
AnnaBridge 171:3a7713b1edbc 1604 /*!
AnnaBridge 171:3a7713b1edbc 1605 * @}
AnnaBridge 171:3a7713b1edbc 1606 */ /* end of group CRC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1607
AnnaBridge 171:3a7713b1edbc 1608
AnnaBridge 171:3a7713b1edbc 1609 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1610 -- DMA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1611 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1612
AnnaBridge 171:3a7713b1edbc 1613 /*!
AnnaBridge 171:3a7713b1edbc 1614 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1615 * @{
AnnaBridge 171:3a7713b1edbc 1616 */
AnnaBridge 171:3a7713b1edbc 1617
AnnaBridge 171:3a7713b1edbc 1618 /** DMA - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1619 typedef struct {
AnnaBridge 171:3a7713b1edbc 1620 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1621 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1622 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 1623 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 1624 uint8_t RESERVED_1[4];
AnnaBridge 171:3a7713b1edbc 1625 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 1626 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 1627 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
AnnaBridge 171:3a7713b1edbc 1628 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
AnnaBridge 171:3a7713b1edbc 1629 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
AnnaBridge 171:3a7713b1edbc 1630 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 1631 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
AnnaBridge 171:3a7713b1edbc 1632 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
AnnaBridge 171:3a7713b1edbc 1633 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
AnnaBridge 171:3a7713b1edbc 1634 uint8_t RESERVED_2[4];
AnnaBridge 171:3a7713b1edbc 1635 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 1636 uint8_t RESERVED_3[4];
AnnaBridge 171:3a7713b1edbc 1637 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 1638 uint8_t RESERVED_4[4];
AnnaBridge 171:3a7713b1edbc 1639 __IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 1640 uint8_t RESERVED_5[200];
AnnaBridge 171:3a7713b1edbc 1641 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
AnnaBridge 171:3a7713b1edbc 1642 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
AnnaBridge 171:3a7713b1edbc 1643 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
AnnaBridge 171:3a7713b1edbc 1644 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
AnnaBridge 171:3a7713b1edbc 1645 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
AnnaBridge 171:3a7713b1edbc 1646 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
AnnaBridge 171:3a7713b1edbc 1647 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
AnnaBridge 171:3a7713b1edbc 1648 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
AnnaBridge 171:3a7713b1edbc 1649 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
AnnaBridge 171:3a7713b1edbc 1650 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
AnnaBridge 171:3a7713b1edbc 1651 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
AnnaBridge 171:3a7713b1edbc 1652 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
AnnaBridge 171:3a7713b1edbc 1653 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
AnnaBridge 171:3a7713b1edbc 1654 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
AnnaBridge 171:3a7713b1edbc 1655 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
AnnaBridge 171:3a7713b1edbc 1656 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
AnnaBridge 171:3a7713b1edbc 1657 uint8_t RESERVED_6[3824];
AnnaBridge 171:3a7713b1edbc 1658 struct { /* offset: 0x1000, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1659 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1660 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1661 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1662 union { /* offset: 0x1008, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1663 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1664 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1665 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1666 };
AnnaBridge 171:3a7713b1edbc 1667 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1668 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1669 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1670 union { /* offset: 0x1016, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1671 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1672 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1673 };
AnnaBridge 171:3a7713b1edbc 1674 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1675 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1676 union { /* offset: 0x101E, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1677 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1678 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1679 };
AnnaBridge 171:3a7713b1edbc 1680 } TCD[16];
AnnaBridge 171:3a7713b1edbc 1681 } DMA_Type;
AnnaBridge 171:3a7713b1edbc 1682
AnnaBridge 171:3a7713b1edbc 1683 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1684 -- DMA Register Masks
AnnaBridge 171:3a7713b1edbc 1685 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1686
AnnaBridge 171:3a7713b1edbc 1687 /*!
AnnaBridge 171:3a7713b1edbc 1688 * @addtogroup DMA_Register_Masks DMA Register Masks
AnnaBridge 171:3a7713b1edbc 1689 * @{
AnnaBridge 171:3a7713b1edbc 1690 */
AnnaBridge 171:3a7713b1edbc 1691
AnnaBridge 171:3a7713b1edbc 1692 /*! @name CR - Control Register */
AnnaBridge 171:3a7713b1edbc 1693 #define DMA_CR_EDBG_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1694 #define DMA_CR_EDBG_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1695 #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
AnnaBridge 171:3a7713b1edbc 1696 #define DMA_CR_ERCA_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1697 #define DMA_CR_ERCA_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1698 #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
AnnaBridge 171:3a7713b1edbc 1699 #define DMA_CR_HOE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1700 #define DMA_CR_HOE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1701 #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
AnnaBridge 171:3a7713b1edbc 1702 #define DMA_CR_HALT_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1703 #define DMA_CR_HALT_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1704 #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
AnnaBridge 171:3a7713b1edbc 1705 #define DMA_CR_CLM_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1706 #define DMA_CR_CLM_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1707 #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
AnnaBridge 171:3a7713b1edbc 1708 #define DMA_CR_EMLM_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1709 #define DMA_CR_EMLM_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1710 #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
AnnaBridge 171:3a7713b1edbc 1711 #define DMA_CR_ECX_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1712 #define DMA_CR_ECX_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1713 #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
AnnaBridge 171:3a7713b1edbc 1714 #define DMA_CR_CX_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1715 #define DMA_CR_CX_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1716 #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
AnnaBridge 171:3a7713b1edbc 1717
AnnaBridge 171:3a7713b1edbc 1718 /*! @name ES - Error Status Register */
AnnaBridge 171:3a7713b1edbc 1719 #define DMA_ES_DBE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1720 #define DMA_ES_DBE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1721 #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
AnnaBridge 171:3a7713b1edbc 1722 #define DMA_ES_SBE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1723 #define DMA_ES_SBE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1724 #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
AnnaBridge 171:3a7713b1edbc 1725 #define DMA_ES_SGE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1726 #define DMA_ES_SGE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1727 #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
AnnaBridge 171:3a7713b1edbc 1728 #define DMA_ES_NCE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1729 #define DMA_ES_NCE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1730 #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
AnnaBridge 171:3a7713b1edbc 1731 #define DMA_ES_DOE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1732 #define DMA_ES_DOE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1733 #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
AnnaBridge 171:3a7713b1edbc 1734 #define DMA_ES_DAE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1735 #define DMA_ES_DAE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1736 #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
AnnaBridge 171:3a7713b1edbc 1737 #define DMA_ES_SOE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1738 #define DMA_ES_SOE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1739 #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
AnnaBridge 171:3a7713b1edbc 1740 #define DMA_ES_SAE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1741 #define DMA_ES_SAE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1742 #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
AnnaBridge 171:3a7713b1edbc 1743 #define DMA_ES_ERRCHN_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 1744 #define DMA_ES_ERRCHN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1745 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
AnnaBridge 171:3a7713b1edbc 1746 #define DMA_ES_CPE_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1747 #define DMA_ES_CPE_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1748 #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
AnnaBridge 171:3a7713b1edbc 1749 #define DMA_ES_ECX_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1750 #define DMA_ES_ECX_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1751 #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
AnnaBridge 171:3a7713b1edbc 1752 #define DMA_ES_VLD_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 1753 #define DMA_ES_VLD_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 1754 #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
AnnaBridge 171:3a7713b1edbc 1755
AnnaBridge 171:3a7713b1edbc 1756 /*! @name ERQ - Enable Request Register */
AnnaBridge 171:3a7713b1edbc 1757 #define DMA_ERQ_ERQ0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1758 #define DMA_ERQ_ERQ0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1759 #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
AnnaBridge 171:3a7713b1edbc 1760 #define DMA_ERQ_ERQ1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1761 #define DMA_ERQ_ERQ1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1762 #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
AnnaBridge 171:3a7713b1edbc 1763 #define DMA_ERQ_ERQ2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1764 #define DMA_ERQ_ERQ2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1765 #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
AnnaBridge 171:3a7713b1edbc 1766 #define DMA_ERQ_ERQ3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1767 #define DMA_ERQ_ERQ3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1768 #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
AnnaBridge 171:3a7713b1edbc 1769 #define DMA_ERQ_ERQ4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1770 #define DMA_ERQ_ERQ4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1771 #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
AnnaBridge 171:3a7713b1edbc 1772 #define DMA_ERQ_ERQ5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1773 #define DMA_ERQ_ERQ5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1774 #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
AnnaBridge 171:3a7713b1edbc 1775 #define DMA_ERQ_ERQ6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1776 #define DMA_ERQ_ERQ6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1777 #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
AnnaBridge 171:3a7713b1edbc 1778 #define DMA_ERQ_ERQ7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1779 #define DMA_ERQ_ERQ7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1780 #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
AnnaBridge 171:3a7713b1edbc 1781 #define DMA_ERQ_ERQ8_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1782 #define DMA_ERQ_ERQ8_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1783 #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
AnnaBridge 171:3a7713b1edbc 1784 #define DMA_ERQ_ERQ9_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1785 #define DMA_ERQ_ERQ9_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1786 #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
AnnaBridge 171:3a7713b1edbc 1787 #define DMA_ERQ_ERQ10_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1788 #define DMA_ERQ_ERQ10_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1789 #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
AnnaBridge 171:3a7713b1edbc 1790 #define DMA_ERQ_ERQ11_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 1791 #define DMA_ERQ_ERQ11_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 1792 #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
AnnaBridge 171:3a7713b1edbc 1793 #define DMA_ERQ_ERQ12_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1794 #define DMA_ERQ_ERQ12_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1795 #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
AnnaBridge 171:3a7713b1edbc 1796 #define DMA_ERQ_ERQ13_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1797 #define DMA_ERQ_ERQ13_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1798 #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
AnnaBridge 171:3a7713b1edbc 1799 #define DMA_ERQ_ERQ14_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1800 #define DMA_ERQ_ERQ14_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1801 #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
AnnaBridge 171:3a7713b1edbc 1802 #define DMA_ERQ_ERQ15_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 1803 #define DMA_ERQ_ERQ15_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 1804 #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
AnnaBridge 171:3a7713b1edbc 1805
AnnaBridge 171:3a7713b1edbc 1806 /*! @name EEI - Enable Error Interrupt Register */
AnnaBridge 171:3a7713b1edbc 1807 #define DMA_EEI_EEI0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1808 #define DMA_EEI_EEI0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1809 #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
AnnaBridge 171:3a7713b1edbc 1810 #define DMA_EEI_EEI1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1811 #define DMA_EEI_EEI1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1812 #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
AnnaBridge 171:3a7713b1edbc 1813 #define DMA_EEI_EEI2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1814 #define DMA_EEI_EEI2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1815 #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
AnnaBridge 171:3a7713b1edbc 1816 #define DMA_EEI_EEI3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1817 #define DMA_EEI_EEI3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1818 #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
AnnaBridge 171:3a7713b1edbc 1819 #define DMA_EEI_EEI4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1820 #define DMA_EEI_EEI4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1821 #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
AnnaBridge 171:3a7713b1edbc 1822 #define DMA_EEI_EEI5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1823 #define DMA_EEI_EEI5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1824 #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
AnnaBridge 171:3a7713b1edbc 1825 #define DMA_EEI_EEI6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1826 #define DMA_EEI_EEI6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1827 #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
AnnaBridge 171:3a7713b1edbc 1828 #define DMA_EEI_EEI7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1829 #define DMA_EEI_EEI7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1830 #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
AnnaBridge 171:3a7713b1edbc 1831 #define DMA_EEI_EEI8_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1832 #define DMA_EEI_EEI8_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1833 #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
AnnaBridge 171:3a7713b1edbc 1834 #define DMA_EEI_EEI9_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1835 #define DMA_EEI_EEI9_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1836 #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
AnnaBridge 171:3a7713b1edbc 1837 #define DMA_EEI_EEI10_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1838 #define DMA_EEI_EEI10_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1839 #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
AnnaBridge 171:3a7713b1edbc 1840 #define DMA_EEI_EEI11_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 1841 #define DMA_EEI_EEI11_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 1842 #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
AnnaBridge 171:3a7713b1edbc 1843 #define DMA_EEI_EEI12_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1844 #define DMA_EEI_EEI12_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1845 #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
AnnaBridge 171:3a7713b1edbc 1846 #define DMA_EEI_EEI13_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1847 #define DMA_EEI_EEI13_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1848 #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
AnnaBridge 171:3a7713b1edbc 1849 #define DMA_EEI_EEI14_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1850 #define DMA_EEI_EEI14_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1851 #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
AnnaBridge 171:3a7713b1edbc 1852 #define DMA_EEI_EEI15_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 1853 #define DMA_EEI_EEI15_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 1854 #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
AnnaBridge 171:3a7713b1edbc 1855
AnnaBridge 171:3a7713b1edbc 1856 /*! @name CEEI - Clear Enable Error Interrupt Register */
AnnaBridge 171:3a7713b1edbc 1857 #define DMA_CEEI_CEEI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 1858 #define DMA_CEEI_CEEI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1859 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
AnnaBridge 171:3a7713b1edbc 1860 #define DMA_CEEI_CAEE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1861 #define DMA_CEEI_CAEE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1862 #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
AnnaBridge 171:3a7713b1edbc 1863 #define DMA_CEEI_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1864 #define DMA_CEEI_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1865 #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 1866
AnnaBridge 171:3a7713b1edbc 1867 /*! @name SEEI - Set Enable Error Interrupt Register */
AnnaBridge 171:3a7713b1edbc 1868 #define DMA_SEEI_SEEI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 1869 #define DMA_SEEI_SEEI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1870 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
AnnaBridge 171:3a7713b1edbc 1871 #define DMA_SEEI_SAEE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1872 #define DMA_SEEI_SAEE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1873 #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
AnnaBridge 171:3a7713b1edbc 1874 #define DMA_SEEI_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1875 #define DMA_SEEI_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1876 #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 1877
AnnaBridge 171:3a7713b1edbc 1878 /*! @name CERQ - Clear Enable Request Register */
AnnaBridge 171:3a7713b1edbc 1879 #define DMA_CERQ_CERQ_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 1880 #define DMA_CERQ_CERQ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1881 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
AnnaBridge 171:3a7713b1edbc 1882 #define DMA_CERQ_CAER_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1883 #define DMA_CERQ_CAER_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1884 #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
AnnaBridge 171:3a7713b1edbc 1885 #define DMA_CERQ_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1886 #define DMA_CERQ_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1887 #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 1888
AnnaBridge 171:3a7713b1edbc 1889 /*! @name SERQ - Set Enable Request Register */
AnnaBridge 171:3a7713b1edbc 1890 #define DMA_SERQ_SERQ_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 1891 #define DMA_SERQ_SERQ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1892 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
AnnaBridge 171:3a7713b1edbc 1893 #define DMA_SERQ_SAER_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1894 #define DMA_SERQ_SAER_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1895 #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
AnnaBridge 171:3a7713b1edbc 1896 #define DMA_SERQ_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1897 #define DMA_SERQ_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1898 #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 1899
AnnaBridge 171:3a7713b1edbc 1900 /*! @name CDNE - Clear DONE Status Bit Register */
AnnaBridge 171:3a7713b1edbc 1901 #define DMA_CDNE_CDNE_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 1902 #define DMA_CDNE_CDNE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1903 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
AnnaBridge 171:3a7713b1edbc 1904 #define DMA_CDNE_CADN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1905 #define DMA_CDNE_CADN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1906 #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
AnnaBridge 171:3a7713b1edbc 1907 #define DMA_CDNE_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1908 #define DMA_CDNE_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1909 #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 1910
AnnaBridge 171:3a7713b1edbc 1911 /*! @name SSRT - Set START Bit Register */
AnnaBridge 171:3a7713b1edbc 1912 #define DMA_SSRT_SSRT_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 1913 #define DMA_SSRT_SSRT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1914 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
AnnaBridge 171:3a7713b1edbc 1915 #define DMA_SSRT_SAST_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1916 #define DMA_SSRT_SAST_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1917 #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
AnnaBridge 171:3a7713b1edbc 1918 #define DMA_SSRT_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1919 #define DMA_SSRT_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1920 #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 1921
AnnaBridge 171:3a7713b1edbc 1922 /*! @name CERR - Clear Error Register */
AnnaBridge 171:3a7713b1edbc 1923 #define DMA_CERR_CERR_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 1924 #define DMA_CERR_CERR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1925 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
AnnaBridge 171:3a7713b1edbc 1926 #define DMA_CERR_CAEI_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1927 #define DMA_CERR_CAEI_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1928 #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
AnnaBridge 171:3a7713b1edbc 1929 #define DMA_CERR_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1930 #define DMA_CERR_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1931 #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 1932
AnnaBridge 171:3a7713b1edbc 1933 /*! @name CINT - Clear Interrupt Request Register */
AnnaBridge 171:3a7713b1edbc 1934 #define DMA_CINT_CINT_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 1935 #define DMA_CINT_CINT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1936 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
AnnaBridge 171:3a7713b1edbc 1937 #define DMA_CINT_CAIR_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1938 #define DMA_CINT_CAIR_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1939 #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
AnnaBridge 171:3a7713b1edbc 1940 #define DMA_CINT_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1941 #define DMA_CINT_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1942 #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 1943
AnnaBridge 171:3a7713b1edbc 1944 /*! @name INT - Interrupt Request Register */
AnnaBridge 171:3a7713b1edbc 1945 #define DMA_INT_INT0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1946 #define DMA_INT_INT0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1947 #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
AnnaBridge 171:3a7713b1edbc 1948 #define DMA_INT_INT1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1949 #define DMA_INT_INT1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1950 #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
AnnaBridge 171:3a7713b1edbc 1951 #define DMA_INT_INT2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1952 #define DMA_INT_INT2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1953 #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
AnnaBridge 171:3a7713b1edbc 1954 #define DMA_INT_INT3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1955 #define DMA_INT_INT3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1956 #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
AnnaBridge 171:3a7713b1edbc 1957 #define DMA_INT_INT4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1958 #define DMA_INT_INT4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1959 #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
AnnaBridge 171:3a7713b1edbc 1960 #define DMA_INT_INT5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1961 #define DMA_INT_INT5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1962 #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
AnnaBridge 171:3a7713b1edbc 1963 #define DMA_INT_INT6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1964 #define DMA_INT_INT6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1965 #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
AnnaBridge 171:3a7713b1edbc 1966 #define DMA_INT_INT7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1967 #define DMA_INT_INT7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1968 #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
AnnaBridge 171:3a7713b1edbc 1969 #define DMA_INT_INT8_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1970 #define DMA_INT_INT8_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1971 #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
AnnaBridge 171:3a7713b1edbc 1972 #define DMA_INT_INT9_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1973 #define DMA_INT_INT9_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1974 #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
AnnaBridge 171:3a7713b1edbc 1975 #define DMA_INT_INT10_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1976 #define DMA_INT_INT10_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1977 #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
AnnaBridge 171:3a7713b1edbc 1978 #define DMA_INT_INT11_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 1979 #define DMA_INT_INT11_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 1980 #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
AnnaBridge 171:3a7713b1edbc 1981 #define DMA_INT_INT12_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1982 #define DMA_INT_INT12_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1983 #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
AnnaBridge 171:3a7713b1edbc 1984 #define DMA_INT_INT13_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1985 #define DMA_INT_INT13_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1986 #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
AnnaBridge 171:3a7713b1edbc 1987 #define DMA_INT_INT14_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1988 #define DMA_INT_INT14_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1989 #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
AnnaBridge 171:3a7713b1edbc 1990 #define DMA_INT_INT15_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 1991 #define DMA_INT_INT15_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 1992 #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
AnnaBridge 171:3a7713b1edbc 1993
AnnaBridge 171:3a7713b1edbc 1994 /*! @name ERR - Error Register */
AnnaBridge 171:3a7713b1edbc 1995 #define DMA_ERR_ERR0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1996 #define DMA_ERR_ERR0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1997 #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
AnnaBridge 171:3a7713b1edbc 1998 #define DMA_ERR_ERR1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1999 #define DMA_ERR_ERR1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2000 #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
AnnaBridge 171:3a7713b1edbc 2001 #define DMA_ERR_ERR2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2002 #define DMA_ERR_ERR2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2003 #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
AnnaBridge 171:3a7713b1edbc 2004 #define DMA_ERR_ERR3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2005 #define DMA_ERR_ERR3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2006 #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
AnnaBridge 171:3a7713b1edbc 2007 #define DMA_ERR_ERR4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 2008 #define DMA_ERR_ERR4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2009 #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
AnnaBridge 171:3a7713b1edbc 2010 #define DMA_ERR_ERR5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2011 #define DMA_ERR_ERR5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2012 #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
AnnaBridge 171:3a7713b1edbc 2013 #define DMA_ERR_ERR6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2014 #define DMA_ERR_ERR6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2015 #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
AnnaBridge 171:3a7713b1edbc 2016 #define DMA_ERR_ERR7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2017 #define DMA_ERR_ERR7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2018 #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
AnnaBridge 171:3a7713b1edbc 2019 #define DMA_ERR_ERR8_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 2020 #define DMA_ERR_ERR8_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2021 #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
AnnaBridge 171:3a7713b1edbc 2022 #define DMA_ERR_ERR9_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 2023 #define DMA_ERR_ERR9_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 2024 #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
AnnaBridge 171:3a7713b1edbc 2025 #define DMA_ERR_ERR10_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 2026 #define DMA_ERR_ERR10_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 2027 #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
AnnaBridge 171:3a7713b1edbc 2028 #define DMA_ERR_ERR11_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 2029 #define DMA_ERR_ERR11_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 2030 #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
AnnaBridge 171:3a7713b1edbc 2031 #define DMA_ERR_ERR12_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 2032 #define DMA_ERR_ERR12_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 2033 #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
AnnaBridge 171:3a7713b1edbc 2034 #define DMA_ERR_ERR13_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 2035 #define DMA_ERR_ERR13_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 2036 #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
AnnaBridge 171:3a7713b1edbc 2037 #define DMA_ERR_ERR14_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 2038 #define DMA_ERR_ERR14_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 2039 #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
AnnaBridge 171:3a7713b1edbc 2040 #define DMA_ERR_ERR15_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 2041 #define DMA_ERR_ERR15_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 2042 #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
AnnaBridge 171:3a7713b1edbc 2043
AnnaBridge 171:3a7713b1edbc 2044 /*! @name HRS - Hardware Request Status Register */
AnnaBridge 171:3a7713b1edbc 2045 #define DMA_HRS_HRS0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2046 #define DMA_HRS_HRS0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2047 #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
AnnaBridge 171:3a7713b1edbc 2048 #define DMA_HRS_HRS1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2049 #define DMA_HRS_HRS1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2050 #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
AnnaBridge 171:3a7713b1edbc 2051 #define DMA_HRS_HRS2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2052 #define DMA_HRS_HRS2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2053 #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
AnnaBridge 171:3a7713b1edbc 2054 #define DMA_HRS_HRS3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2055 #define DMA_HRS_HRS3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2056 #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
AnnaBridge 171:3a7713b1edbc 2057 #define DMA_HRS_HRS4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 2058 #define DMA_HRS_HRS4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2059 #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
AnnaBridge 171:3a7713b1edbc 2060 #define DMA_HRS_HRS5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2061 #define DMA_HRS_HRS5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2062 #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
AnnaBridge 171:3a7713b1edbc 2063 #define DMA_HRS_HRS6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2064 #define DMA_HRS_HRS6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2065 #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
AnnaBridge 171:3a7713b1edbc 2066 #define DMA_HRS_HRS7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2067 #define DMA_HRS_HRS7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2068 #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
AnnaBridge 171:3a7713b1edbc 2069 #define DMA_HRS_HRS8_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 2070 #define DMA_HRS_HRS8_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2071 #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
AnnaBridge 171:3a7713b1edbc 2072 #define DMA_HRS_HRS9_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 2073 #define DMA_HRS_HRS9_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 2074 #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
AnnaBridge 171:3a7713b1edbc 2075 #define DMA_HRS_HRS10_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 2076 #define DMA_HRS_HRS10_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 2077 #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
AnnaBridge 171:3a7713b1edbc 2078 #define DMA_HRS_HRS11_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 2079 #define DMA_HRS_HRS11_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 2080 #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
AnnaBridge 171:3a7713b1edbc 2081 #define DMA_HRS_HRS12_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 2082 #define DMA_HRS_HRS12_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 2083 #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
AnnaBridge 171:3a7713b1edbc 2084 #define DMA_HRS_HRS13_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 2085 #define DMA_HRS_HRS13_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 2086 #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
AnnaBridge 171:3a7713b1edbc 2087 #define DMA_HRS_HRS14_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 2088 #define DMA_HRS_HRS14_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 2089 #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
AnnaBridge 171:3a7713b1edbc 2090 #define DMA_HRS_HRS15_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 2091 #define DMA_HRS_HRS15_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 2092 #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
AnnaBridge 171:3a7713b1edbc 2093
AnnaBridge 171:3a7713b1edbc 2094 /*! @name DCHPRI3 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 2095 #define DMA_DCHPRI3_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 2096 #define DMA_DCHPRI3_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2097 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 2098 #define DMA_DCHPRI3_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2099 #define DMA_DCHPRI3_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2100 #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 2101 #define DMA_DCHPRI3_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2102 #define DMA_DCHPRI3_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2103 #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 2104
AnnaBridge 171:3a7713b1edbc 2105 /*! @name DCHPRI2 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 2106 #define DMA_DCHPRI2_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 2107 #define DMA_DCHPRI2_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2108 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 2109 #define DMA_DCHPRI2_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2110 #define DMA_DCHPRI2_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2111 #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 2112 #define DMA_DCHPRI2_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2113 #define DMA_DCHPRI2_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2114 #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 2115
AnnaBridge 171:3a7713b1edbc 2116 /*! @name DCHPRI1 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 2117 #define DMA_DCHPRI1_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 2118 #define DMA_DCHPRI1_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2119 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 2120 #define DMA_DCHPRI1_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2121 #define DMA_DCHPRI1_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2122 #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 2123 #define DMA_DCHPRI1_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2124 #define DMA_DCHPRI1_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2125 #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 2126
AnnaBridge 171:3a7713b1edbc 2127 /*! @name DCHPRI0 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 2128 #define DMA_DCHPRI0_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 2129 #define DMA_DCHPRI0_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2130 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 2131 #define DMA_DCHPRI0_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2132 #define DMA_DCHPRI0_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2133 #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 2134 #define DMA_DCHPRI0_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2135 #define DMA_DCHPRI0_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2136 #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 2137
AnnaBridge 171:3a7713b1edbc 2138 /*! @name DCHPRI7 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 2139 #define DMA_DCHPRI7_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 2140 #define DMA_DCHPRI7_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2141 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 2142 #define DMA_DCHPRI7_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2143 #define DMA_DCHPRI7_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2144 #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 2145 #define DMA_DCHPRI7_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2146 #define DMA_DCHPRI7_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2147 #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 2148
AnnaBridge 171:3a7713b1edbc 2149 /*! @name DCHPRI6 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 2150 #define DMA_DCHPRI6_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 2151 #define DMA_DCHPRI6_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2152 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 2153 #define DMA_DCHPRI6_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2154 #define DMA_DCHPRI6_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2155 #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 2156 #define DMA_DCHPRI6_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2157 #define DMA_DCHPRI6_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2158 #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 2159
AnnaBridge 171:3a7713b1edbc 2160 /*! @name DCHPRI5 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 2161 #define DMA_DCHPRI5_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 2162 #define DMA_DCHPRI5_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2163 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 2164 #define DMA_DCHPRI5_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2165 #define DMA_DCHPRI5_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2166 #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 2167 #define DMA_DCHPRI5_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2168 #define DMA_DCHPRI5_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2169 #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 2170
AnnaBridge 171:3a7713b1edbc 2171 /*! @name DCHPRI4 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 2172 #define DMA_DCHPRI4_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 2173 #define DMA_DCHPRI4_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2174 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 2175 #define DMA_DCHPRI4_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2176 #define DMA_DCHPRI4_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2177 #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 2178 #define DMA_DCHPRI4_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2179 #define DMA_DCHPRI4_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2180 #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 2181
AnnaBridge 171:3a7713b1edbc 2182 /*! @name DCHPRI11 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 2183 #define DMA_DCHPRI11_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 2184 #define DMA_DCHPRI11_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2185 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 2186 #define DMA_DCHPRI11_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2187 #define DMA_DCHPRI11_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2188 #define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 2189 #define DMA_DCHPRI11_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2190 #define DMA_DCHPRI11_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2191 #define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 2192
AnnaBridge 171:3a7713b1edbc 2193 /*! @name DCHPRI10 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 2194 #define DMA_DCHPRI10_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 2195 #define DMA_DCHPRI10_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2196 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 2197 #define DMA_DCHPRI10_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2198 #define DMA_DCHPRI10_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2199 #define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 2200 #define DMA_DCHPRI10_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2201 #define DMA_DCHPRI10_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2202 #define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 2203
AnnaBridge 171:3a7713b1edbc 2204 /*! @name DCHPRI9 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 2205 #define DMA_DCHPRI9_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 2206 #define DMA_DCHPRI9_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2207 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 2208 #define DMA_DCHPRI9_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2209 #define DMA_DCHPRI9_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2210 #define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 2211 #define DMA_DCHPRI9_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2212 #define DMA_DCHPRI9_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2213 #define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 2214
AnnaBridge 171:3a7713b1edbc 2215 /*! @name DCHPRI8 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 2216 #define DMA_DCHPRI8_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 2217 #define DMA_DCHPRI8_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2218 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 2219 #define DMA_DCHPRI8_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2220 #define DMA_DCHPRI8_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2221 #define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 2222 #define DMA_DCHPRI8_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2223 #define DMA_DCHPRI8_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2224 #define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 2225
AnnaBridge 171:3a7713b1edbc 2226 /*! @name DCHPRI15 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 2227 #define DMA_DCHPRI15_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 2228 #define DMA_DCHPRI15_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2229 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 2230 #define DMA_DCHPRI15_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2231 #define DMA_DCHPRI15_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2232 #define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 2233 #define DMA_DCHPRI15_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2234 #define DMA_DCHPRI15_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2235 #define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 2236
AnnaBridge 171:3a7713b1edbc 2237 /*! @name DCHPRI14 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 2238 #define DMA_DCHPRI14_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 2239 #define DMA_DCHPRI14_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2240 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 2241 #define DMA_DCHPRI14_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2242 #define DMA_DCHPRI14_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2243 #define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 2244 #define DMA_DCHPRI14_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2245 #define DMA_DCHPRI14_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2246 #define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 2247
AnnaBridge 171:3a7713b1edbc 2248 /*! @name DCHPRI13 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 2249 #define DMA_DCHPRI13_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 2250 #define DMA_DCHPRI13_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2251 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 2252 #define DMA_DCHPRI13_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2253 #define DMA_DCHPRI13_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2254 #define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 2255 #define DMA_DCHPRI13_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2256 #define DMA_DCHPRI13_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2257 #define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 2258
AnnaBridge 171:3a7713b1edbc 2259 /*! @name DCHPRI12 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 2260 #define DMA_DCHPRI12_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 2261 #define DMA_DCHPRI12_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2262 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 2263 #define DMA_DCHPRI12_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2264 #define DMA_DCHPRI12_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2265 #define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 2266 #define DMA_DCHPRI12_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2267 #define DMA_DCHPRI12_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2268 #define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 2269
AnnaBridge 171:3a7713b1edbc 2270 /*! @name SADDR - TCD Source Address */
AnnaBridge 171:3a7713b1edbc 2271 #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2272 #define DMA_SADDR_SADDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2273 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
AnnaBridge 171:3a7713b1edbc 2274
AnnaBridge 171:3a7713b1edbc 2275 /* The count of DMA_SADDR */
AnnaBridge 171:3a7713b1edbc 2276 #define DMA_SADDR_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2277
AnnaBridge 171:3a7713b1edbc 2278 /*! @name SOFF - TCD Signed Source Address Offset */
AnnaBridge 171:3a7713b1edbc 2279 #define DMA_SOFF_SOFF_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 2280 #define DMA_SOFF_SOFF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2281 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
AnnaBridge 171:3a7713b1edbc 2282
AnnaBridge 171:3a7713b1edbc 2283 /* The count of DMA_SOFF */
AnnaBridge 171:3a7713b1edbc 2284 #define DMA_SOFF_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2285
AnnaBridge 171:3a7713b1edbc 2286 /*! @name ATTR - TCD Transfer Attributes */
AnnaBridge 171:3a7713b1edbc 2287 #define DMA_ATTR_DSIZE_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2288 #define DMA_ATTR_DSIZE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2289 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 2290 #define DMA_ATTR_DMOD_MASK (0xF8U)
AnnaBridge 171:3a7713b1edbc 2291 #define DMA_ATTR_DMOD_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2292 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
AnnaBridge 171:3a7713b1edbc 2293 #define DMA_ATTR_SSIZE_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 2294 #define DMA_ATTR_SSIZE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2295 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 2296 #define DMA_ATTR_SMOD_MASK (0xF800U)
AnnaBridge 171:3a7713b1edbc 2297 #define DMA_ATTR_SMOD_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 2298 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
AnnaBridge 171:3a7713b1edbc 2299
AnnaBridge 171:3a7713b1edbc 2300 /* The count of DMA_ATTR */
AnnaBridge 171:3a7713b1edbc 2301 #define DMA_ATTR_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2302
AnnaBridge 171:3a7713b1edbc 2303 /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) */
AnnaBridge 171:3a7713b1edbc 2304 #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2305 #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2306 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
AnnaBridge 171:3a7713b1edbc 2307
AnnaBridge 171:3a7713b1edbc 2308 /* The count of DMA_NBYTES_MLNO */
AnnaBridge 171:3a7713b1edbc 2309 #define DMA_NBYTES_MLNO_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2310
AnnaBridge 171:3a7713b1edbc 2311 /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */
AnnaBridge 171:3a7713b1edbc 2312 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2313 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2314 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
AnnaBridge 171:3a7713b1edbc 2315 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 2316 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 2317 #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
AnnaBridge 171:3a7713b1edbc 2318 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 2319 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 2320 #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
AnnaBridge 171:3a7713b1edbc 2321
AnnaBridge 171:3a7713b1edbc 2322 /* The count of DMA_NBYTES_MLOFFNO */
AnnaBridge 171:3a7713b1edbc 2323 #define DMA_NBYTES_MLOFFNO_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2324
AnnaBridge 171:3a7713b1edbc 2325 /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */
AnnaBridge 171:3a7713b1edbc 2326 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 2327 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2328 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
AnnaBridge 171:3a7713b1edbc 2329 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
AnnaBridge 171:3a7713b1edbc 2330 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 2331 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
AnnaBridge 171:3a7713b1edbc 2332 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 2333 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 2334 #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
AnnaBridge 171:3a7713b1edbc 2335 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 2336 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 2337 #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
AnnaBridge 171:3a7713b1edbc 2338
AnnaBridge 171:3a7713b1edbc 2339 /* The count of DMA_NBYTES_MLOFFYES */
AnnaBridge 171:3a7713b1edbc 2340 #define DMA_NBYTES_MLOFFYES_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2341
AnnaBridge 171:3a7713b1edbc 2342 /*! @name SLAST - TCD Last Source Address Adjustment */
AnnaBridge 171:3a7713b1edbc 2343 #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2344 #define DMA_SLAST_SLAST_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2345 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
AnnaBridge 171:3a7713b1edbc 2346
AnnaBridge 171:3a7713b1edbc 2347 /* The count of DMA_SLAST */
AnnaBridge 171:3a7713b1edbc 2348 #define DMA_SLAST_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2349
AnnaBridge 171:3a7713b1edbc 2350 /*! @name DADDR - TCD Destination Address */
AnnaBridge 171:3a7713b1edbc 2351 #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2352 #define DMA_DADDR_DADDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2353 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
AnnaBridge 171:3a7713b1edbc 2354
AnnaBridge 171:3a7713b1edbc 2355 /* The count of DMA_DADDR */
AnnaBridge 171:3a7713b1edbc 2356 #define DMA_DADDR_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2357
AnnaBridge 171:3a7713b1edbc 2358 /*! @name DOFF - TCD Signed Destination Address Offset */
AnnaBridge 171:3a7713b1edbc 2359 #define DMA_DOFF_DOFF_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 2360 #define DMA_DOFF_DOFF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2361 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
AnnaBridge 171:3a7713b1edbc 2362
AnnaBridge 171:3a7713b1edbc 2363 /* The count of DMA_DOFF */
AnnaBridge 171:3a7713b1edbc 2364 #define DMA_DOFF_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2365
AnnaBridge 171:3a7713b1edbc 2366 /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
AnnaBridge 171:3a7713b1edbc 2367 #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
AnnaBridge 171:3a7713b1edbc 2368 #define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2369 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
AnnaBridge 171:3a7713b1edbc 2370 #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 2371 #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 2372 #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
AnnaBridge 171:3a7713b1edbc 2373
AnnaBridge 171:3a7713b1edbc 2374 /* The count of DMA_CITER_ELINKNO */
AnnaBridge 171:3a7713b1edbc 2375 #define DMA_CITER_ELINKNO_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2376
AnnaBridge 171:3a7713b1edbc 2377 /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
AnnaBridge 171:3a7713b1edbc 2378 #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 2379 #define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2380 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
AnnaBridge 171:3a7713b1edbc 2381 #define DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U)
AnnaBridge 171:3a7713b1edbc 2382 #define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 2383 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
AnnaBridge 171:3a7713b1edbc 2384 #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 2385 #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 2386 #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
AnnaBridge 171:3a7713b1edbc 2387
AnnaBridge 171:3a7713b1edbc 2388 /* The count of DMA_CITER_ELINKYES */
AnnaBridge 171:3a7713b1edbc 2389 #define DMA_CITER_ELINKYES_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2390
AnnaBridge 171:3a7713b1edbc 2391 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
AnnaBridge 171:3a7713b1edbc 2392 #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2393 #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2394 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
AnnaBridge 171:3a7713b1edbc 2395
AnnaBridge 171:3a7713b1edbc 2396 /* The count of DMA_DLAST_SGA */
AnnaBridge 171:3a7713b1edbc 2397 #define DMA_DLAST_SGA_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2398
AnnaBridge 171:3a7713b1edbc 2399 /*! @name CSR - TCD Control and Status */
AnnaBridge 171:3a7713b1edbc 2400 #define DMA_CSR_START_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2401 #define DMA_CSR_START_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2402 #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
AnnaBridge 171:3a7713b1edbc 2403 #define DMA_CSR_INTMAJOR_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2404 #define DMA_CSR_INTMAJOR_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2405 #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
AnnaBridge 171:3a7713b1edbc 2406 #define DMA_CSR_INTHALF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2407 #define DMA_CSR_INTHALF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2408 #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
AnnaBridge 171:3a7713b1edbc 2409 #define DMA_CSR_DREQ_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2410 #define DMA_CSR_DREQ_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2411 #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
AnnaBridge 171:3a7713b1edbc 2412 #define DMA_CSR_ESG_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 2413 #define DMA_CSR_ESG_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2414 #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
AnnaBridge 171:3a7713b1edbc 2415 #define DMA_CSR_MAJORELINK_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2416 #define DMA_CSR_MAJORELINK_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2417 #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
AnnaBridge 171:3a7713b1edbc 2418 #define DMA_CSR_ACTIVE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2419 #define DMA_CSR_ACTIVE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2420 #define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
AnnaBridge 171:3a7713b1edbc 2421 #define DMA_CSR_DONE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2422 #define DMA_CSR_DONE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2423 #define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
AnnaBridge 171:3a7713b1edbc 2424 #define DMA_CSR_MAJORLINKCH_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 2425 #define DMA_CSR_MAJORLINKCH_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2426 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
AnnaBridge 171:3a7713b1edbc 2427 #define DMA_CSR_BWC_MASK (0xC000U)
AnnaBridge 171:3a7713b1edbc 2428 #define DMA_CSR_BWC_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 2429 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
AnnaBridge 171:3a7713b1edbc 2430
AnnaBridge 171:3a7713b1edbc 2431 /* The count of DMA_CSR */
AnnaBridge 171:3a7713b1edbc 2432 #define DMA_CSR_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2433
AnnaBridge 171:3a7713b1edbc 2434 /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
AnnaBridge 171:3a7713b1edbc 2435 #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
AnnaBridge 171:3a7713b1edbc 2436 #define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2437 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
AnnaBridge 171:3a7713b1edbc 2438 #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 2439 #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 2440 #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
AnnaBridge 171:3a7713b1edbc 2441
AnnaBridge 171:3a7713b1edbc 2442 /* The count of DMA_BITER_ELINKNO */
AnnaBridge 171:3a7713b1edbc 2443 #define DMA_BITER_ELINKNO_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2444
AnnaBridge 171:3a7713b1edbc 2445 /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
AnnaBridge 171:3a7713b1edbc 2446 #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 2447 #define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2448 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
AnnaBridge 171:3a7713b1edbc 2449 #define DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U)
AnnaBridge 171:3a7713b1edbc 2450 #define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 2451 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
AnnaBridge 171:3a7713b1edbc 2452 #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 2453 #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 2454 #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
AnnaBridge 171:3a7713b1edbc 2455
AnnaBridge 171:3a7713b1edbc 2456 /* The count of DMA_BITER_ELINKYES */
AnnaBridge 171:3a7713b1edbc 2457 #define DMA_BITER_ELINKYES_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2458
AnnaBridge 171:3a7713b1edbc 2459
AnnaBridge 171:3a7713b1edbc 2460 /*!
AnnaBridge 171:3a7713b1edbc 2461 * @}
AnnaBridge 171:3a7713b1edbc 2462 */ /* end of group DMA_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2463
AnnaBridge 171:3a7713b1edbc 2464
AnnaBridge 171:3a7713b1edbc 2465 /* DMA - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2466 /** Peripheral DMA base address */
AnnaBridge 171:3a7713b1edbc 2467 #define DMA_BASE (0x40008000u)
AnnaBridge 171:3a7713b1edbc 2468 /** Peripheral DMA base pointer */
AnnaBridge 171:3a7713b1edbc 2469 #define DMA0 ((DMA_Type *)DMA_BASE)
AnnaBridge 171:3a7713b1edbc 2470 /** Array initializer of DMA peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 2471 #define DMA_BASE_ADDRS { DMA_BASE }
AnnaBridge 171:3a7713b1edbc 2472 /** Array initializer of DMA peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2473 #define DMA_BASE_PTRS { DMA0 }
AnnaBridge 171:3a7713b1edbc 2474 /** Interrupt vectors for the DMA peripheral type */
AnnaBridge 171:3a7713b1edbc 2475 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
AnnaBridge 171:3a7713b1edbc 2476 #define DMA_ERROR_IRQS { DMA_Error_IRQn }
AnnaBridge 171:3a7713b1edbc 2477
AnnaBridge 171:3a7713b1edbc 2478 /*!
AnnaBridge 171:3a7713b1edbc 2479 * @}
AnnaBridge 171:3a7713b1edbc 2480 */ /* end of group DMA_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2481
AnnaBridge 171:3a7713b1edbc 2482
AnnaBridge 171:3a7713b1edbc 2483 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2484 -- DMAMUX Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2485 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2486
AnnaBridge 171:3a7713b1edbc 2487 /*!
AnnaBridge 171:3a7713b1edbc 2488 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2489 * @{
AnnaBridge 171:3a7713b1edbc 2490 */
AnnaBridge 171:3a7713b1edbc 2491
AnnaBridge 171:3a7713b1edbc 2492 /** DMAMUX - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2493 typedef struct {
AnnaBridge 171:3a7713b1edbc 2494 __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
AnnaBridge 171:3a7713b1edbc 2495 } DMAMUX_Type;
AnnaBridge 171:3a7713b1edbc 2496
AnnaBridge 171:3a7713b1edbc 2497 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2498 -- DMAMUX Register Masks
AnnaBridge 171:3a7713b1edbc 2499 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2500
AnnaBridge 171:3a7713b1edbc 2501 /*!
AnnaBridge 171:3a7713b1edbc 2502 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
AnnaBridge 171:3a7713b1edbc 2503 * @{
AnnaBridge 171:3a7713b1edbc 2504 */
AnnaBridge 171:3a7713b1edbc 2505
AnnaBridge 171:3a7713b1edbc 2506 /*! @name CHCFG - Channel Configuration register */
AnnaBridge 171:3a7713b1edbc 2507 #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 2508 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2509 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
AnnaBridge 171:3a7713b1edbc 2510 #define DMAMUX_CHCFG_TRIG_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2511 #define DMAMUX_CHCFG_TRIG_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2512 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 2513 #define DMAMUX_CHCFG_ENBL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2514 #define DMAMUX_CHCFG_ENBL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2515 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
AnnaBridge 171:3a7713b1edbc 2516
AnnaBridge 171:3a7713b1edbc 2517 /* The count of DMAMUX_CHCFG */
AnnaBridge 171:3a7713b1edbc 2518 #define DMAMUX_CHCFG_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2519
AnnaBridge 171:3a7713b1edbc 2520
AnnaBridge 171:3a7713b1edbc 2521 /*!
AnnaBridge 171:3a7713b1edbc 2522 * @}
AnnaBridge 171:3a7713b1edbc 2523 */ /* end of group DMAMUX_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2524
AnnaBridge 171:3a7713b1edbc 2525
AnnaBridge 171:3a7713b1edbc 2526 /* DMAMUX - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2527 /** Peripheral DMAMUX base address */
AnnaBridge 171:3a7713b1edbc 2528 #define DMAMUX_BASE (0x40021000u)
AnnaBridge 171:3a7713b1edbc 2529 /** Peripheral DMAMUX base pointer */
AnnaBridge 171:3a7713b1edbc 2530 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
AnnaBridge 171:3a7713b1edbc 2531 /** Array initializer of DMAMUX peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 2532 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
AnnaBridge 171:3a7713b1edbc 2533 /** Array initializer of DMAMUX peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2534 #define DMAMUX_BASE_PTRS { DMAMUX }
AnnaBridge 171:3a7713b1edbc 2535
AnnaBridge 171:3a7713b1edbc 2536 /*!
AnnaBridge 171:3a7713b1edbc 2537 * @}
AnnaBridge 171:3a7713b1edbc 2538 */ /* end of group DMAMUX_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2539
AnnaBridge 171:3a7713b1edbc 2540
AnnaBridge 171:3a7713b1edbc 2541 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2542 -- EWM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2543 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2544
AnnaBridge 171:3a7713b1edbc 2545 /*!
AnnaBridge 171:3a7713b1edbc 2546 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2547 * @{
AnnaBridge 171:3a7713b1edbc 2548 */
AnnaBridge 171:3a7713b1edbc 2549
AnnaBridge 171:3a7713b1edbc 2550 /** EWM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2551 typedef struct {
AnnaBridge 171:3a7713b1edbc 2552 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 2553 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 2554 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 2555 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 2556 } EWM_Type;
AnnaBridge 171:3a7713b1edbc 2557
AnnaBridge 171:3a7713b1edbc 2558 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2559 -- EWM Register Masks
AnnaBridge 171:3a7713b1edbc 2560 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2561
AnnaBridge 171:3a7713b1edbc 2562 /*!
AnnaBridge 171:3a7713b1edbc 2563 * @addtogroup EWM_Register_Masks EWM Register Masks
AnnaBridge 171:3a7713b1edbc 2564 * @{
AnnaBridge 171:3a7713b1edbc 2565 */
AnnaBridge 171:3a7713b1edbc 2566
AnnaBridge 171:3a7713b1edbc 2567 /*! @name CTRL - Control Register */
AnnaBridge 171:3a7713b1edbc 2568 #define EWM_CTRL_EWMEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2569 #define EWM_CTRL_EWMEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2570 #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
AnnaBridge 171:3a7713b1edbc 2571 #define EWM_CTRL_ASSIN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2572 #define EWM_CTRL_ASSIN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2573 #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
AnnaBridge 171:3a7713b1edbc 2574 #define EWM_CTRL_INEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2575 #define EWM_CTRL_INEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2576 #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
AnnaBridge 171:3a7713b1edbc 2577 #define EWM_CTRL_INTEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2578 #define EWM_CTRL_INTEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2579 #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
AnnaBridge 171:3a7713b1edbc 2580
AnnaBridge 171:3a7713b1edbc 2581 /*! @name SERV - Service Register */
AnnaBridge 171:3a7713b1edbc 2582 #define EWM_SERV_SERVICE_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2583 #define EWM_SERV_SERVICE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2584 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
AnnaBridge 171:3a7713b1edbc 2585
AnnaBridge 171:3a7713b1edbc 2586 /*! @name CMPL - Compare Low Register */
AnnaBridge 171:3a7713b1edbc 2587 #define EWM_CMPL_COMPAREL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2588 #define EWM_CMPL_COMPAREL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2589 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
AnnaBridge 171:3a7713b1edbc 2590
AnnaBridge 171:3a7713b1edbc 2591 /*! @name CMPH - Compare High Register */
AnnaBridge 171:3a7713b1edbc 2592 #define EWM_CMPH_COMPAREH_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2593 #define EWM_CMPH_COMPAREH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2594 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
AnnaBridge 171:3a7713b1edbc 2595
AnnaBridge 171:3a7713b1edbc 2596
AnnaBridge 171:3a7713b1edbc 2597 /*!
AnnaBridge 171:3a7713b1edbc 2598 * @}
AnnaBridge 171:3a7713b1edbc 2599 */ /* end of group EWM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2600
AnnaBridge 171:3a7713b1edbc 2601
AnnaBridge 171:3a7713b1edbc 2602 /* EWM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2603 /** Peripheral EWM base address */
AnnaBridge 171:3a7713b1edbc 2604 #define EWM_BASE (0x40061000u)
AnnaBridge 171:3a7713b1edbc 2605 /** Peripheral EWM base pointer */
AnnaBridge 171:3a7713b1edbc 2606 #define EWM ((EWM_Type *)EWM_BASE)
AnnaBridge 171:3a7713b1edbc 2607 /** Array initializer of EWM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 2608 #define EWM_BASE_ADDRS { EWM_BASE }
AnnaBridge 171:3a7713b1edbc 2609 /** Array initializer of EWM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2610 #define EWM_BASE_PTRS { EWM }
AnnaBridge 171:3a7713b1edbc 2611 /** Interrupt vectors for the EWM peripheral type */
AnnaBridge 171:3a7713b1edbc 2612 #define EWM_IRQS { WDOG_EWM_IRQn }
AnnaBridge 171:3a7713b1edbc 2613
AnnaBridge 171:3a7713b1edbc 2614 /*!
AnnaBridge 171:3a7713b1edbc 2615 * @}
AnnaBridge 171:3a7713b1edbc 2616 */ /* end of group EWM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2617
AnnaBridge 171:3a7713b1edbc 2618
AnnaBridge 171:3a7713b1edbc 2619 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2620 -- FMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2621 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2622
AnnaBridge 171:3a7713b1edbc 2623 /*!
AnnaBridge 171:3a7713b1edbc 2624 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2625 * @{
AnnaBridge 171:3a7713b1edbc 2626 */
AnnaBridge 171:3a7713b1edbc 2627
AnnaBridge 171:3a7713b1edbc 2628 /** FMC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2629 typedef struct {
AnnaBridge 171:3a7713b1edbc 2630 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 2631 __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 2632 __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 2633 uint8_t RESERVED_0[244];
AnnaBridge 171:3a7713b1edbc 2634 __IO uint32_t TAGVD[4][2]; /**< Cache Tag Storage, array offset: 0x100, array step: index*0x8, index2*0x4 */
AnnaBridge 171:3a7713b1edbc 2635 uint8_t RESERVED_1[224];
AnnaBridge 171:3a7713b1edbc 2636 struct { /* offset: 0x200, array step: index*0x10, index2*0x8 */
AnnaBridge 171:3a7713b1edbc 2637 __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x10, index2*0x8 */
AnnaBridge 171:3a7713b1edbc 2638 __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x10, index2*0x8 */
AnnaBridge 171:3a7713b1edbc 2639 } SET[4][2];
AnnaBridge 171:3a7713b1edbc 2640 } FMC_Type;
AnnaBridge 171:3a7713b1edbc 2641
AnnaBridge 171:3a7713b1edbc 2642 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2643 -- FMC Register Masks
AnnaBridge 171:3a7713b1edbc 2644 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2645
AnnaBridge 171:3a7713b1edbc 2646 /*!
AnnaBridge 171:3a7713b1edbc 2647 * @addtogroup FMC_Register_Masks FMC Register Masks
AnnaBridge 171:3a7713b1edbc 2648 * @{
AnnaBridge 171:3a7713b1edbc 2649 */
AnnaBridge 171:3a7713b1edbc 2650
AnnaBridge 171:3a7713b1edbc 2651 /*! @name PFAPR - Flash Access Protection Register */
AnnaBridge 171:3a7713b1edbc 2652 #define FMC_PFAPR_M0AP_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 2653 #define FMC_PFAPR_M0AP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2654 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
AnnaBridge 171:3a7713b1edbc 2655 #define FMC_PFAPR_M1AP_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 2656 #define FMC_PFAPR_M1AP_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2657 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
AnnaBridge 171:3a7713b1edbc 2658 #define FMC_PFAPR_M2AP_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 2659 #define FMC_PFAPR_M2AP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2660 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
AnnaBridge 171:3a7713b1edbc 2661 #define FMC_PFAPR_M3AP_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 2662 #define FMC_PFAPR_M3AP_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2663 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
AnnaBridge 171:3a7713b1edbc 2664 #define FMC_PFAPR_M4AP_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 2665 #define FMC_PFAPR_M4AP_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2666 #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
AnnaBridge 171:3a7713b1edbc 2667 #define FMC_PFAPR_M5AP_MASK (0xC00U)
AnnaBridge 171:3a7713b1edbc 2668 #define FMC_PFAPR_M5AP_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 2669 #define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
AnnaBridge 171:3a7713b1edbc 2670 #define FMC_PFAPR_M6AP_MASK (0x3000U)
AnnaBridge 171:3a7713b1edbc 2671 #define FMC_PFAPR_M6AP_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 2672 #define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
AnnaBridge 171:3a7713b1edbc 2673 #define FMC_PFAPR_M7AP_MASK (0xC000U)
AnnaBridge 171:3a7713b1edbc 2674 #define FMC_PFAPR_M7AP_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 2675 #define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
AnnaBridge 171:3a7713b1edbc 2676 #define FMC_PFAPR_M0PFD_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 2677 #define FMC_PFAPR_M0PFD_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2678 #define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
AnnaBridge 171:3a7713b1edbc 2679 #define FMC_PFAPR_M1PFD_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 2680 #define FMC_PFAPR_M1PFD_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 2681 #define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
AnnaBridge 171:3a7713b1edbc 2682 #define FMC_PFAPR_M2PFD_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 2683 #define FMC_PFAPR_M2PFD_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 2684 #define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
AnnaBridge 171:3a7713b1edbc 2685 #define FMC_PFAPR_M3PFD_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 2686 #define FMC_PFAPR_M3PFD_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 2687 #define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
AnnaBridge 171:3a7713b1edbc 2688 #define FMC_PFAPR_M4PFD_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 2689 #define FMC_PFAPR_M4PFD_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 2690 #define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
AnnaBridge 171:3a7713b1edbc 2691 #define FMC_PFAPR_M5PFD_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 2692 #define FMC_PFAPR_M5PFD_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 2693 #define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
AnnaBridge 171:3a7713b1edbc 2694 #define FMC_PFAPR_M6PFD_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 2695 #define FMC_PFAPR_M6PFD_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 2696 #define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
AnnaBridge 171:3a7713b1edbc 2697 #define FMC_PFAPR_M7PFD_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 2698 #define FMC_PFAPR_M7PFD_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 2699 #define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
AnnaBridge 171:3a7713b1edbc 2700
AnnaBridge 171:3a7713b1edbc 2701 /*! @name PFB0CR - Flash Bank 0 Control Register */
AnnaBridge 171:3a7713b1edbc 2702 #define FMC_PFB0CR_B0SEBE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2703 #define FMC_PFB0CR_B0SEBE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2704 #define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)
AnnaBridge 171:3a7713b1edbc 2705 #define FMC_PFB0CR_B0IPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2706 #define FMC_PFB0CR_B0IPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2707 #define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
AnnaBridge 171:3a7713b1edbc 2708 #define FMC_PFB0CR_B0DPE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2709 #define FMC_PFB0CR_B0DPE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2710 #define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
AnnaBridge 171:3a7713b1edbc 2711 #define FMC_PFB0CR_B0ICE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2712 #define FMC_PFB0CR_B0ICE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2713 #define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)
AnnaBridge 171:3a7713b1edbc 2714 #define FMC_PFB0CR_B0DCE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 2715 #define FMC_PFB0CR_B0DCE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2716 #define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)
AnnaBridge 171:3a7713b1edbc 2717 #define FMC_PFB0CR_CRC_MASK (0xE0U)
AnnaBridge 171:3a7713b1edbc 2718 #define FMC_PFB0CR_CRC_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2719 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
AnnaBridge 171:3a7713b1edbc 2720 #define FMC_PFB0CR_B0MW_MASK (0x60000U)
AnnaBridge 171:3a7713b1edbc 2721 #define FMC_PFB0CR_B0MW_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 2722 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
AnnaBridge 171:3a7713b1edbc 2723 #define FMC_PFB0CR_S_B_INV_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 2724 #define FMC_PFB0CR_S_B_INV_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 2725 #define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)
AnnaBridge 171:3a7713b1edbc 2726 #define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 2727 #define FMC_PFB0CR_CINV_WAY_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 2728 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
AnnaBridge 171:3a7713b1edbc 2729 #define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 2730 #define FMC_PFB0CR_CLCK_WAY_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2731 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)
AnnaBridge 171:3a7713b1edbc 2732 #define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 2733 #define FMC_PFB0CR_B0RWSC_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2734 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
AnnaBridge 171:3a7713b1edbc 2735
AnnaBridge 171:3a7713b1edbc 2736 /*! @name PFB1CR - Flash Bank 1 Control Register */
AnnaBridge 171:3a7713b1edbc 2737 #define FMC_PFB1CR_B1SEBE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2738 #define FMC_PFB1CR_B1SEBE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2739 #define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK)
AnnaBridge 171:3a7713b1edbc 2740 #define FMC_PFB1CR_B1IPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2741 #define FMC_PFB1CR_B1IPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2742 #define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK)
AnnaBridge 171:3a7713b1edbc 2743 #define FMC_PFB1CR_B1DPE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2744 #define FMC_PFB1CR_B1DPE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2745 #define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK)
AnnaBridge 171:3a7713b1edbc 2746 #define FMC_PFB1CR_B1ICE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2747 #define FMC_PFB1CR_B1ICE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2748 #define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK)
AnnaBridge 171:3a7713b1edbc 2749 #define FMC_PFB1CR_B1DCE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 2750 #define FMC_PFB1CR_B1DCE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2751 #define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK)
AnnaBridge 171:3a7713b1edbc 2752 #define FMC_PFB1CR_B1MW_MASK (0x60000U)
AnnaBridge 171:3a7713b1edbc 2753 #define FMC_PFB1CR_B1MW_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 2754 #define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK)
AnnaBridge 171:3a7713b1edbc 2755 #define FMC_PFB1CR_B1RWSC_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 2756 #define FMC_PFB1CR_B1RWSC_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2757 #define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK)
AnnaBridge 171:3a7713b1edbc 2758
AnnaBridge 171:3a7713b1edbc 2759 /*! @name TAGVD - Cache Tag Storage */
AnnaBridge 171:3a7713b1edbc 2760 #define FMC_TAGVD_valid_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2761 #define FMC_TAGVD_valid_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2762 #define FMC_TAGVD_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVD_valid_SHIFT)) & FMC_TAGVD_valid_MASK)
AnnaBridge 171:3a7713b1edbc 2763 #define FMC_TAGVD_tag_MASK (0x7FFF0U)
AnnaBridge 171:3a7713b1edbc 2764 #define FMC_TAGVD_tag_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2765 #define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVD_tag_SHIFT)) & FMC_TAGVD_tag_MASK)
AnnaBridge 171:3a7713b1edbc 2766
AnnaBridge 171:3a7713b1edbc 2767 /* The count of FMC_TAGVD */
AnnaBridge 171:3a7713b1edbc 2768 #define FMC_TAGVD_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 2769
AnnaBridge 171:3a7713b1edbc 2770 /* The count of FMC_TAGVD */
AnnaBridge 171:3a7713b1edbc 2771 #define FMC_TAGVD_COUNT2 (2U)
AnnaBridge 171:3a7713b1edbc 2772
AnnaBridge 171:3a7713b1edbc 2773 /*! @name DATA_U - Cache Data Storage (upper word) */
AnnaBridge 171:3a7713b1edbc 2774 #define FMC_DATA_U_data_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2775 #define FMC_DATA_U_data_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2776 #define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_U_data_SHIFT)) & FMC_DATA_U_data_MASK)
AnnaBridge 171:3a7713b1edbc 2777
AnnaBridge 171:3a7713b1edbc 2778 /* The count of FMC_DATA_U */
AnnaBridge 171:3a7713b1edbc 2779 #define FMC_DATA_U_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 2780
AnnaBridge 171:3a7713b1edbc 2781 /* The count of FMC_DATA_U */
AnnaBridge 171:3a7713b1edbc 2782 #define FMC_DATA_U_COUNT2 (2U)
AnnaBridge 171:3a7713b1edbc 2783
AnnaBridge 171:3a7713b1edbc 2784 /*! @name DATA_L - Cache Data Storage (lower word) */
AnnaBridge 171:3a7713b1edbc 2785 #define FMC_DATA_L_data_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2786 #define FMC_DATA_L_data_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2787 #define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_L_data_SHIFT)) & FMC_DATA_L_data_MASK)
AnnaBridge 171:3a7713b1edbc 2788
AnnaBridge 171:3a7713b1edbc 2789 /* The count of FMC_DATA_L */
AnnaBridge 171:3a7713b1edbc 2790 #define FMC_DATA_L_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 2791
AnnaBridge 171:3a7713b1edbc 2792 /* The count of FMC_DATA_L */
AnnaBridge 171:3a7713b1edbc 2793 #define FMC_DATA_L_COUNT2 (2U)
AnnaBridge 171:3a7713b1edbc 2794
AnnaBridge 171:3a7713b1edbc 2795
AnnaBridge 171:3a7713b1edbc 2796 /*!
AnnaBridge 171:3a7713b1edbc 2797 * @}
AnnaBridge 171:3a7713b1edbc 2798 */ /* end of group FMC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2799
AnnaBridge 171:3a7713b1edbc 2800
AnnaBridge 171:3a7713b1edbc 2801 /* FMC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2802 /** Peripheral FMC base address */
AnnaBridge 171:3a7713b1edbc 2803 #define FMC_BASE (0x4001F000u)
AnnaBridge 171:3a7713b1edbc 2804 /** Peripheral FMC base pointer */
AnnaBridge 171:3a7713b1edbc 2805 #define FMC ((FMC_Type *)FMC_BASE)
AnnaBridge 171:3a7713b1edbc 2806 /** Array initializer of FMC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 2807 #define FMC_BASE_ADDRS { FMC_BASE }
AnnaBridge 171:3a7713b1edbc 2808 /** Array initializer of FMC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2809 #define FMC_BASE_PTRS { FMC }
AnnaBridge 171:3a7713b1edbc 2810
AnnaBridge 171:3a7713b1edbc 2811 /*!
AnnaBridge 171:3a7713b1edbc 2812 * @}
AnnaBridge 171:3a7713b1edbc 2813 */ /* end of group FMC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2814
AnnaBridge 171:3a7713b1edbc 2815
AnnaBridge 171:3a7713b1edbc 2816 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2817 -- FTFL Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2818 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2819
AnnaBridge 171:3a7713b1edbc 2820 /*!
AnnaBridge 171:3a7713b1edbc 2821 * @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2822 * @{
AnnaBridge 171:3a7713b1edbc 2823 */
AnnaBridge 171:3a7713b1edbc 2824
AnnaBridge 171:3a7713b1edbc 2825 /** FTFL - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2826 typedef struct {
AnnaBridge 171:3a7713b1edbc 2827 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 2828 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 2829 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 2830 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 2831 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 2832 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 2833 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 2834 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 2835 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 2836 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 2837 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 2838 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 2839 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 2840 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 2841 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
AnnaBridge 171:3a7713b1edbc 2842 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
AnnaBridge 171:3a7713b1edbc 2843 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 2844 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
AnnaBridge 171:3a7713b1edbc 2845 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
AnnaBridge 171:3a7713b1edbc 2846 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
AnnaBridge 171:3a7713b1edbc 2847 uint8_t RESERVED_0[2];
AnnaBridge 171:3a7713b1edbc 2848 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
AnnaBridge 171:3a7713b1edbc 2849 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
AnnaBridge 171:3a7713b1edbc 2850 } FTFL_Type;
AnnaBridge 171:3a7713b1edbc 2851
AnnaBridge 171:3a7713b1edbc 2852 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2853 -- FTFL Register Masks
AnnaBridge 171:3a7713b1edbc 2854 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2855
AnnaBridge 171:3a7713b1edbc 2856 /*!
AnnaBridge 171:3a7713b1edbc 2857 * @addtogroup FTFL_Register_Masks FTFL Register Masks
AnnaBridge 171:3a7713b1edbc 2858 * @{
AnnaBridge 171:3a7713b1edbc 2859 */
AnnaBridge 171:3a7713b1edbc 2860
AnnaBridge 171:3a7713b1edbc 2861 /*! @name FSTAT - Flash Status Register */
AnnaBridge 171:3a7713b1edbc 2862 #define FTFL_FSTAT_MGSTAT0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2863 #define FTFL_FSTAT_MGSTAT0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2864 #define FTFL_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_MGSTAT0_SHIFT)) & FTFL_FSTAT_MGSTAT0_MASK)
AnnaBridge 171:3a7713b1edbc 2865 #define FTFL_FSTAT_FPVIOL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 2866 #define FTFL_FSTAT_FPVIOL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2867 #define FTFL_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_FPVIOL_SHIFT)) & FTFL_FSTAT_FPVIOL_MASK)
AnnaBridge 171:3a7713b1edbc 2868 #define FTFL_FSTAT_ACCERR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2869 #define FTFL_FSTAT_ACCERR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2870 #define FTFL_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_ACCERR_SHIFT)) & FTFL_FSTAT_ACCERR_MASK)
AnnaBridge 171:3a7713b1edbc 2871 #define FTFL_FSTAT_RDCOLERR_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2872 #define FTFL_FSTAT_RDCOLERR_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2873 #define FTFL_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_RDCOLERR_SHIFT)) & FTFL_FSTAT_RDCOLERR_MASK)
AnnaBridge 171:3a7713b1edbc 2874 #define FTFL_FSTAT_CCIF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2875 #define FTFL_FSTAT_CCIF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2876 #define FTFL_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSTAT_CCIF_SHIFT)) & FTFL_FSTAT_CCIF_MASK)
AnnaBridge 171:3a7713b1edbc 2877
AnnaBridge 171:3a7713b1edbc 2878 /*! @name FCNFG - Flash Configuration Register */
AnnaBridge 171:3a7713b1edbc 2879 #define FTFL_FCNFG_EEERDY_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2880 #define FTFL_FCNFG_EEERDY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2881 #define FTFL_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_EEERDY_SHIFT)) & FTFL_FCNFG_EEERDY_MASK)
AnnaBridge 171:3a7713b1edbc 2882 #define FTFL_FCNFG_RAMRDY_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2883 #define FTFL_FCNFG_RAMRDY_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2884 #define FTFL_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_RAMRDY_SHIFT)) & FTFL_FCNFG_RAMRDY_MASK)
AnnaBridge 171:3a7713b1edbc 2885 #define FTFL_FCNFG_PFLSH_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2886 #define FTFL_FCNFG_PFLSH_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2887 #define FTFL_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_PFLSH_SHIFT)) & FTFL_FCNFG_PFLSH_MASK)
AnnaBridge 171:3a7713b1edbc 2888 #define FTFL_FCNFG_SWAP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2889 #define FTFL_FCNFG_SWAP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2890 #define FTFL_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_SWAP_SHIFT)) & FTFL_FCNFG_SWAP_MASK)
AnnaBridge 171:3a7713b1edbc 2891 #define FTFL_FCNFG_ERSSUSP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 2892 #define FTFL_FCNFG_ERSSUSP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2893 #define FTFL_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_ERSSUSP_SHIFT)) & FTFL_FCNFG_ERSSUSP_MASK)
AnnaBridge 171:3a7713b1edbc 2894 #define FTFL_FCNFG_ERSAREQ_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2895 #define FTFL_FCNFG_ERSAREQ_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2896 #define FTFL_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_ERSAREQ_SHIFT)) & FTFL_FCNFG_ERSAREQ_MASK)
AnnaBridge 171:3a7713b1edbc 2897 #define FTFL_FCNFG_RDCOLLIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2898 #define FTFL_FCNFG_RDCOLLIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2899 #define FTFL_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_RDCOLLIE_SHIFT)) & FTFL_FCNFG_RDCOLLIE_MASK)
AnnaBridge 171:3a7713b1edbc 2900 #define FTFL_FCNFG_CCIE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2901 #define FTFL_FCNFG_CCIE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2902 #define FTFL_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCNFG_CCIE_SHIFT)) & FTFL_FCNFG_CCIE_MASK)
AnnaBridge 171:3a7713b1edbc 2903
AnnaBridge 171:3a7713b1edbc 2904 /*! @name FSEC - Flash Security Register */
AnnaBridge 171:3a7713b1edbc 2905 #define FTFL_FSEC_SEC_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 2906 #define FTFL_FSEC_SEC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2907 #define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_SEC_SHIFT)) & FTFL_FSEC_SEC_MASK)
AnnaBridge 171:3a7713b1edbc 2908 #define FTFL_FSEC_FSLACC_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 2909 #define FTFL_FSEC_FSLACC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2910 #define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_FSLACC_SHIFT)) & FTFL_FSEC_FSLACC_MASK)
AnnaBridge 171:3a7713b1edbc 2911 #define FTFL_FSEC_MEEN_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 2912 #define FTFL_FSEC_MEEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2913 #define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_MEEN_SHIFT)) & FTFL_FSEC_MEEN_MASK)
AnnaBridge 171:3a7713b1edbc 2914 #define FTFL_FSEC_KEYEN_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 2915 #define FTFL_FSEC_KEYEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2916 #define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FSEC_KEYEN_SHIFT)) & FTFL_FSEC_KEYEN_MASK)
AnnaBridge 171:3a7713b1edbc 2917
AnnaBridge 171:3a7713b1edbc 2918 /*! @name FOPT - Flash Option Register */
AnnaBridge 171:3a7713b1edbc 2919 #define FTFL_FOPT_OPT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2920 #define FTFL_FOPT_OPT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2921 #define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FOPT_OPT_SHIFT)) & FTFL_FOPT_OPT_MASK)
AnnaBridge 171:3a7713b1edbc 2922
AnnaBridge 171:3a7713b1edbc 2923 /*! @name FCCOB3 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2924 #define FTFL_FCCOB3_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2925 #define FTFL_FCCOB3_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2926 #define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB3_CCOBn_SHIFT)) & FTFL_FCCOB3_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2927
AnnaBridge 171:3a7713b1edbc 2928 /*! @name FCCOB2 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2929 #define FTFL_FCCOB2_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2930 #define FTFL_FCCOB2_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2931 #define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB2_CCOBn_SHIFT)) & FTFL_FCCOB2_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2932
AnnaBridge 171:3a7713b1edbc 2933 /*! @name FCCOB1 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2934 #define FTFL_FCCOB1_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2935 #define FTFL_FCCOB1_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2936 #define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB1_CCOBn_SHIFT)) & FTFL_FCCOB1_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2937
AnnaBridge 171:3a7713b1edbc 2938 /*! @name FCCOB0 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2939 #define FTFL_FCCOB0_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2940 #define FTFL_FCCOB0_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2941 #define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB0_CCOBn_SHIFT)) & FTFL_FCCOB0_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2942
AnnaBridge 171:3a7713b1edbc 2943 /*! @name FCCOB7 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2944 #define FTFL_FCCOB7_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2945 #define FTFL_FCCOB7_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2946 #define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB7_CCOBn_SHIFT)) & FTFL_FCCOB7_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2947
AnnaBridge 171:3a7713b1edbc 2948 /*! @name FCCOB6 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2949 #define FTFL_FCCOB6_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2950 #define FTFL_FCCOB6_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2951 #define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB6_CCOBn_SHIFT)) & FTFL_FCCOB6_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2952
AnnaBridge 171:3a7713b1edbc 2953 /*! @name FCCOB5 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2954 #define FTFL_FCCOB5_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2955 #define FTFL_FCCOB5_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2956 #define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB5_CCOBn_SHIFT)) & FTFL_FCCOB5_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2957
AnnaBridge 171:3a7713b1edbc 2958 /*! @name FCCOB4 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2959 #define FTFL_FCCOB4_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2960 #define FTFL_FCCOB4_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2961 #define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB4_CCOBn_SHIFT)) & FTFL_FCCOB4_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2962
AnnaBridge 171:3a7713b1edbc 2963 /*! @name FCCOBB - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2964 #define FTFL_FCCOBB_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2965 #define FTFL_FCCOBB_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2966 #define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOBB_CCOBn_SHIFT)) & FTFL_FCCOBB_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2967
AnnaBridge 171:3a7713b1edbc 2968 /*! @name FCCOBA - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2969 #define FTFL_FCCOBA_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2970 #define FTFL_FCCOBA_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2971 #define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOBA_CCOBn_SHIFT)) & FTFL_FCCOBA_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2972
AnnaBridge 171:3a7713b1edbc 2973 /*! @name FCCOB9 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2974 #define FTFL_FCCOB9_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2975 #define FTFL_FCCOB9_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2976 #define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB9_CCOBn_SHIFT)) & FTFL_FCCOB9_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2977
AnnaBridge 171:3a7713b1edbc 2978 /*! @name FCCOB8 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2979 #define FTFL_FCCOB8_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2980 #define FTFL_FCCOB8_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2981 #define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FCCOB8_CCOBn_SHIFT)) & FTFL_FCCOB8_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2982
AnnaBridge 171:3a7713b1edbc 2983 /*! @name FPROT3 - Program Flash Protection Registers */
AnnaBridge 171:3a7713b1edbc 2984 #define FTFL_FPROT3_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2985 #define FTFL_FPROT3_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2986 #define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT3_PROT_SHIFT)) & FTFL_FPROT3_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 2987
AnnaBridge 171:3a7713b1edbc 2988 /*! @name FPROT2 - Program Flash Protection Registers */
AnnaBridge 171:3a7713b1edbc 2989 #define FTFL_FPROT2_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2990 #define FTFL_FPROT2_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2991 #define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT2_PROT_SHIFT)) & FTFL_FPROT2_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 2992
AnnaBridge 171:3a7713b1edbc 2993 /*! @name FPROT1 - Program Flash Protection Registers */
AnnaBridge 171:3a7713b1edbc 2994 #define FTFL_FPROT1_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2995 #define FTFL_FPROT1_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2996 #define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT1_PROT_SHIFT)) & FTFL_FPROT1_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 2997
AnnaBridge 171:3a7713b1edbc 2998 /*! @name FPROT0 - Program Flash Protection Registers */
AnnaBridge 171:3a7713b1edbc 2999 #define FTFL_FPROT0_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3000 #define FTFL_FPROT0_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3001 #define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FPROT0_PROT_SHIFT)) & FTFL_FPROT0_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 3002
AnnaBridge 171:3a7713b1edbc 3003 /*! @name FEPROT - EEPROM Protection Register */
AnnaBridge 171:3a7713b1edbc 3004 #define FTFL_FEPROT_EPROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3005 #define FTFL_FEPROT_EPROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3006 #define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FEPROT_EPROT_SHIFT)) & FTFL_FEPROT_EPROT_MASK)
AnnaBridge 171:3a7713b1edbc 3007
AnnaBridge 171:3a7713b1edbc 3008 /*! @name FDPROT - Data Flash Protection Register */
AnnaBridge 171:3a7713b1edbc 3009 #define FTFL_FDPROT_DPROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3010 #define FTFL_FDPROT_DPROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3011 #define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFL_FDPROT_DPROT_SHIFT)) & FTFL_FDPROT_DPROT_MASK)
AnnaBridge 171:3a7713b1edbc 3012
AnnaBridge 171:3a7713b1edbc 3013
AnnaBridge 171:3a7713b1edbc 3014 /*!
AnnaBridge 171:3a7713b1edbc 3015 * @}
AnnaBridge 171:3a7713b1edbc 3016 */ /* end of group FTFL_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3017
AnnaBridge 171:3a7713b1edbc 3018
AnnaBridge 171:3a7713b1edbc 3019 /* FTFL - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3020 /** Peripheral FTFL base address */
AnnaBridge 171:3a7713b1edbc 3021 #define FTFL_BASE (0x40020000u)
AnnaBridge 171:3a7713b1edbc 3022 /** Peripheral FTFL base pointer */
AnnaBridge 171:3a7713b1edbc 3023 #define FTFL ((FTFL_Type *)FTFL_BASE)
AnnaBridge 171:3a7713b1edbc 3024 /** Array initializer of FTFL peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3025 #define FTFL_BASE_ADDRS { FTFL_BASE }
AnnaBridge 171:3a7713b1edbc 3026 /** Array initializer of FTFL peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3027 #define FTFL_BASE_PTRS { FTFL }
AnnaBridge 171:3a7713b1edbc 3028 /** Interrupt vectors for the FTFL peripheral type */
AnnaBridge 171:3a7713b1edbc 3029 #define FTFL_COMMAND_COMPLETE_IRQS { FTFL_IRQn }
AnnaBridge 171:3a7713b1edbc 3030 #define FTFL_READ_COLLISION_IRQS { FTFL_Collision_IRQn }
AnnaBridge 171:3a7713b1edbc 3031
AnnaBridge 171:3a7713b1edbc 3032 /*!
AnnaBridge 171:3a7713b1edbc 3033 * @}
AnnaBridge 171:3a7713b1edbc 3034 */ /* end of group FTFL_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3035
AnnaBridge 171:3a7713b1edbc 3036
AnnaBridge 171:3a7713b1edbc 3037 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3038 -- FTM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3039 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3040
AnnaBridge 171:3a7713b1edbc 3041 /*!
AnnaBridge 171:3a7713b1edbc 3042 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3043 * @{
AnnaBridge 171:3a7713b1edbc 3044 */
AnnaBridge 171:3a7713b1edbc 3045
AnnaBridge 171:3a7713b1edbc 3046 /** FTM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3047 typedef struct {
AnnaBridge 171:3a7713b1edbc 3048 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3049 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3050 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3051 struct { /* offset: 0xC, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 3052 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 3053 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 3054 } CONTROLS[8];
AnnaBridge 171:3a7713b1edbc 3055 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 3056 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 3057 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 3058 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 3059 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 3060 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 3061 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 3062 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 3063 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 3064 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
AnnaBridge 171:3a7713b1edbc 3065 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
AnnaBridge 171:3a7713b1edbc 3066 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
AnnaBridge 171:3a7713b1edbc 3067 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
AnnaBridge 171:3a7713b1edbc 3068 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 3069 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 3070 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 3071 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 3072 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 3073 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 3074 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
AnnaBridge 171:3a7713b1edbc 3075 } FTM_Type;
AnnaBridge 171:3a7713b1edbc 3076
AnnaBridge 171:3a7713b1edbc 3077 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3078 -- FTM Register Masks
AnnaBridge 171:3a7713b1edbc 3079 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3080
AnnaBridge 171:3a7713b1edbc 3081 /*!
AnnaBridge 171:3a7713b1edbc 3082 * @addtogroup FTM_Register_Masks FTM Register Masks
AnnaBridge 171:3a7713b1edbc 3083 * @{
AnnaBridge 171:3a7713b1edbc 3084 */
AnnaBridge 171:3a7713b1edbc 3085
AnnaBridge 171:3a7713b1edbc 3086 /*! @name SC - Status And Control */
AnnaBridge 171:3a7713b1edbc 3087 #define FTM_SC_PS_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 3088 #define FTM_SC_PS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3089 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
AnnaBridge 171:3a7713b1edbc 3090 #define FTM_SC_CLKS_MASK (0x18U)
AnnaBridge 171:3a7713b1edbc 3091 #define FTM_SC_CLKS_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3092 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
AnnaBridge 171:3a7713b1edbc 3093 #define FTM_SC_CPWMS_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3094 #define FTM_SC_CPWMS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3095 #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
AnnaBridge 171:3a7713b1edbc 3096 #define FTM_SC_TOIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3097 #define FTM_SC_TOIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3098 #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
AnnaBridge 171:3a7713b1edbc 3099 #define FTM_SC_TOF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3100 #define FTM_SC_TOF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3101 #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
AnnaBridge 171:3a7713b1edbc 3102
AnnaBridge 171:3a7713b1edbc 3103 /*! @name CNT - Counter */
AnnaBridge 171:3a7713b1edbc 3104 #define FTM_CNT_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 3105 #define FTM_CNT_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3106 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 3107
AnnaBridge 171:3a7713b1edbc 3108 /*! @name MOD - Modulo */
AnnaBridge 171:3a7713b1edbc 3109 #define FTM_MOD_MOD_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 3110 #define FTM_MOD_MOD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3111 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
AnnaBridge 171:3a7713b1edbc 3112
AnnaBridge 171:3a7713b1edbc 3113 /*! @name CnSC - Channel (n) Status And Control */
AnnaBridge 171:3a7713b1edbc 3114 #define FTM_CnSC_DMA_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3115 #define FTM_CnSC_DMA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3116 #define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
AnnaBridge 171:3a7713b1edbc 3117 #define FTM_CnSC_ELSA_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3118 #define FTM_CnSC_ELSA_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3119 #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
AnnaBridge 171:3a7713b1edbc 3120 #define FTM_CnSC_ELSB_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3121 #define FTM_CnSC_ELSB_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3122 #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
AnnaBridge 171:3a7713b1edbc 3123 #define FTM_CnSC_MSA_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3124 #define FTM_CnSC_MSA_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3125 #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
AnnaBridge 171:3a7713b1edbc 3126 #define FTM_CnSC_MSB_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3127 #define FTM_CnSC_MSB_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3128 #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
AnnaBridge 171:3a7713b1edbc 3129 #define FTM_CnSC_CHIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3130 #define FTM_CnSC_CHIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3131 #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
AnnaBridge 171:3a7713b1edbc 3132 #define FTM_CnSC_CHF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3133 #define FTM_CnSC_CHF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3134 #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
AnnaBridge 171:3a7713b1edbc 3135
AnnaBridge 171:3a7713b1edbc 3136 /* The count of FTM_CnSC */
AnnaBridge 171:3a7713b1edbc 3137 #define FTM_CnSC_COUNT (8U)
AnnaBridge 171:3a7713b1edbc 3138
AnnaBridge 171:3a7713b1edbc 3139 /*! @name CnV - Channel (n) Value */
AnnaBridge 171:3a7713b1edbc 3140 #define FTM_CnV_VAL_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 3141 #define FTM_CnV_VAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3142 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
AnnaBridge 171:3a7713b1edbc 3143
AnnaBridge 171:3a7713b1edbc 3144 /* The count of FTM_CnV */
AnnaBridge 171:3a7713b1edbc 3145 #define FTM_CnV_COUNT (8U)
AnnaBridge 171:3a7713b1edbc 3146
AnnaBridge 171:3a7713b1edbc 3147 /*! @name CNTIN - Counter Initial Value */
AnnaBridge 171:3a7713b1edbc 3148 #define FTM_CNTIN_INIT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 3149 #define FTM_CNTIN_INIT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3150 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
AnnaBridge 171:3a7713b1edbc 3151
AnnaBridge 171:3a7713b1edbc 3152 /*! @name STATUS - Capture And Compare Status */
AnnaBridge 171:3a7713b1edbc 3153 #define FTM_STATUS_CH0F_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3154 #define FTM_STATUS_CH0F_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3155 #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
AnnaBridge 171:3a7713b1edbc 3156 #define FTM_STATUS_CH1F_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3157 #define FTM_STATUS_CH1F_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3158 #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
AnnaBridge 171:3a7713b1edbc 3159 #define FTM_STATUS_CH2F_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3160 #define FTM_STATUS_CH2F_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3161 #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
AnnaBridge 171:3a7713b1edbc 3162 #define FTM_STATUS_CH3F_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3163 #define FTM_STATUS_CH3F_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3164 #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
AnnaBridge 171:3a7713b1edbc 3165 #define FTM_STATUS_CH4F_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3166 #define FTM_STATUS_CH4F_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3167 #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
AnnaBridge 171:3a7713b1edbc 3168 #define FTM_STATUS_CH5F_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3169 #define FTM_STATUS_CH5F_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3170 #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
AnnaBridge 171:3a7713b1edbc 3171 #define FTM_STATUS_CH6F_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3172 #define FTM_STATUS_CH6F_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3173 #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
AnnaBridge 171:3a7713b1edbc 3174 #define FTM_STATUS_CH7F_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3175 #define FTM_STATUS_CH7F_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3176 #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
AnnaBridge 171:3a7713b1edbc 3177
AnnaBridge 171:3a7713b1edbc 3178 /*! @name MODE - Features Mode Selection */
AnnaBridge 171:3a7713b1edbc 3179 #define FTM_MODE_FTMEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3180 #define FTM_MODE_FTMEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3181 #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
AnnaBridge 171:3a7713b1edbc 3182 #define FTM_MODE_INIT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3183 #define FTM_MODE_INIT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3184 #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
AnnaBridge 171:3a7713b1edbc 3185 #define FTM_MODE_WPDIS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3186 #define FTM_MODE_WPDIS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3187 #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
AnnaBridge 171:3a7713b1edbc 3188 #define FTM_MODE_PWMSYNC_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3189 #define FTM_MODE_PWMSYNC_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3190 #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
AnnaBridge 171:3a7713b1edbc 3191 #define FTM_MODE_CAPTEST_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3192 #define FTM_MODE_CAPTEST_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3193 #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
AnnaBridge 171:3a7713b1edbc 3194 #define FTM_MODE_FAULTM_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 3195 #define FTM_MODE_FAULTM_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3196 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
AnnaBridge 171:3a7713b1edbc 3197 #define FTM_MODE_FAULTIE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3198 #define FTM_MODE_FAULTIE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3199 #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
AnnaBridge 171:3a7713b1edbc 3200
AnnaBridge 171:3a7713b1edbc 3201 /*! @name SYNC - Synchronization */
AnnaBridge 171:3a7713b1edbc 3202 #define FTM_SYNC_CNTMIN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3203 #define FTM_SYNC_CNTMIN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3204 #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
AnnaBridge 171:3a7713b1edbc 3205 #define FTM_SYNC_CNTMAX_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3206 #define FTM_SYNC_CNTMAX_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3207 #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
AnnaBridge 171:3a7713b1edbc 3208 #define FTM_SYNC_REINIT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3209 #define FTM_SYNC_REINIT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3210 #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
AnnaBridge 171:3a7713b1edbc 3211 #define FTM_SYNC_SYNCHOM_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3212 #define FTM_SYNC_SYNCHOM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3213 #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
AnnaBridge 171:3a7713b1edbc 3214 #define FTM_SYNC_TRIG0_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3215 #define FTM_SYNC_TRIG0_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3216 #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
AnnaBridge 171:3a7713b1edbc 3217 #define FTM_SYNC_TRIG1_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3218 #define FTM_SYNC_TRIG1_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3219 #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
AnnaBridge 171:3a7713b1edbc 3220 #define FTM_SYNC_TRIG2_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3221 #define FTM_SYNC_TRIG2_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3222 #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
AnnaBridge 171:3a7713b1edbc 3223 #define FTM_SYNC_SWSYNC_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3224 #define FTM_SYNC_SWSYNC_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3225 #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
AnnaBridge 171:3a7713b1edbc 3226
AnnaBridge 171:3a7713b1edbc 3227 /*! @name OUTINIT - Initial State For Channels Output */
AnnaBridge 171:3a7713b1edbc 3228 #define FTM_OUTINIT_CH0OI_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3229 #define FTM_OUTINIT_CH0OI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3230 #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
AnnaBridge 171:3a7713b1edbc 3231 #define FTM_OUTINIT_CH1OI_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3232 #define FTM_OUTINIT_CH1OI_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3233 #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
AnnaBridge 171:3a7713b1edbc 3234 #define FTM_OUTINIT_CH2OI_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3235 #define FTM_OUTINIT_CH2OI_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3236 #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
AnnaBridge 171:3a7713b1edbc 3237 #define FTM_OUTINIT_CH3OI_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3238 #define FTM_OUTINIT_CH3OI_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3239 #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
AnnaBridge 171:3a7713b1edbc 3240 #define FTM_OUTINIT_CH4OI_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3241 #define FTM_OUTINIT_CH4OI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3242 #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
AnnaBridge 171:3a7713b1edbc 3243 #define FTM_OUTINIT_CH5OI_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3244 #define FTM_OUTINIT_CH5OI_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3245 #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
AnnaBridge 171:3a7713b1edbc 3246 #define FTM_OUTINIT_CH6OI_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3247 #define FTM_OUTINIT_CH6OI_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3248 #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
AnnaBridge 171:3a7713b1edbc 3249 #define FTM_OUTINIT_CH7OI_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3250 #define FTM_OUTINIT_CH7OI_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3251 #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
AnnaBridge 171:3a7713b1edbc 3252
AnnaBridge 171:3a7713b1edbc 3253 /*! @name OUTMASK - Output Mask */
AnnaBridge 171:3a7713b1edbc 3254 #define FTM_OUTMASK_CH0OM_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3255 #define FTM_OUTMASK_CH0OM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3256 #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
AnnaBridge 171:3a7713b1edbc 3257 #define FTM_OUTMASK_CH1OM_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3258 #define FTM_OUTMASK_CH1OM_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3259 #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
AnnaBridge 171:3a7713b1edbc 3260 #define FTM_OUTMASK_CH2OM_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3261 #define FTM_OUTMASK_CH2OM_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3262 #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
AnnaBridge 171:3a7713b1edbc 3263 #define FTM_OUTMASK_CH3OM_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3264 #define FTM_OUTMASK_CH3OM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3265 #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
AnnaBridge 171:3a7713b1edbc 3266 #define FTM_OUTMASK_CH4OM_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3267 #define FTM_OUTMASK_CH4OM_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3268 #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
AnnaBridge 171:3a7713b1edbc 3269 #define FTM_OUTMASK_CH5OM_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3270 #define FTM_OUTMASK_CH5OM_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3271 #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
AnnaBridge 171:3a7713b1edbc 3272 #define FTM_OUTMASK_CH6OM_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3273 #define FTM_OUTMASK_CH6OM_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3274 #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
AnnaBridge 171:3a7713b1edbc 3275 #define FTM_OUTMASK_CH7OM_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3276 #define FTM_OUTMASK_CH7OM_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3277 #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
AnnaBridge 171:3a7713b1edbc 3278
AnnaBridge 171:3a7713b1edbc 3279 /*! @name COMBINE - Function For Linked Channels */
AnnaBridge 171:3a7713b1edbc 3280 #define FTM_COMBINE_COMBINE0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3281 #define FTM_COMBINE_COMBINE0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3282 #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
AnnaBridge 171:3a7713b1edbc 3283 #define FTM_COMBINE_COMP0_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3284 #define FTM_COMBINE_COMP0_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3285 #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
AnnaBridge 171:3a7713b1edbc 3286 #define FTM_COMBINE_DECAPEN0_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3287 #define FTM_COMBINE_DECAPEN0_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3288 #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
AnnaBridge 171:3a7713b1edbc 3289 #define FTM_COMBINE_DECAP0_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3290 #define FTM_COMBINE_DECAP0_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3291 #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
AnnaBridge 171:3a7713b1edbc 3292 #define FTM_COMBINE_DTEN0_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3293 #define FTM_COMBINE_DTEN0_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3294 #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
AnnaBridge 171:3a7713b1edbc 3295 #define FTM_COMBINE_SYNCEN0_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3296 #define FTM_COMBINE_SYNCEN0_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3297 #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
AnnaBridge 171:3a7713b1edbc 3298 #define FTM_COMBINE_FAULTEN0_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3299 #define FTM_COMBINE_FAULTEN0_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3300 #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
AnnaBridge 171:3a7713b1edbc 3301 #define FTM_COMBINE_COMBINE1_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 3302 #define FTM_COMBINE_COMBINE1_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 3303 #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
AnnaBridge 171:3a7713b1edbc 3304 #define FTM_COMBINE_COMP1_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 3305 #define FTM_COMBINE_COMP1_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 3306 #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
AnnaBridge 171:3a7713b1edbc 3307 #define FTM_COMBINE_DECAPEN1_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 3308 #define FTM_COMBINE_DECAPEN1_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 3309 #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
AnnaBridge 171:3a7713b1edbc 3310 #define FTM_COMBINE_DECAP1_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 3311 #define FTM_COMBINE_DECAP1_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 3312 #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
AnnaBridge 171:3a7713b1edbc 3313 #define FTM_COMBINE_DTEN1_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 3314 #define FTM_COMBINE_DTEN1_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 3315 #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
AnnaBridge 171:3a7713b1edbc 3316 #define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 3317 #define FTM_COMBINE_SYNCEN1_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 3318 #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
AnnaBridge 171:3a7713b1edbc 3319 #define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 3320 #define FTM_COMBINE_FAULTEN1_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 3321 #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
AnnaBridge 171:3a7713b1edbc 3322 #define FTM_COMBINE_COMBINE2_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 3323 #define FTM_COMBINE_COMBINE2_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3324 #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
AnnaBridge 171:3a7713b1edbc 3325 #define FTM_COMBINE_COMP2_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 3326 #define FTM_COMBINE_COMP2_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 3327 #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
AnnaBridge 171:3a7713b1edbc 3328 #define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 3329 #define FTM_COMBINE_DECAPEN2_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 3330 #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
AnnaBridge 171:3a7713b1edbc 3331 #define FTM_COMBINE_DECAP2_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 3332 #define FTM_COMBINE_DECAP2_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 3333 #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
AnnaBridge 171:3a7713b1edbc 3334 #define FTM_COMBINE_DTEN2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 3335 #define FTM_COMBINE_DTEN2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 3336 #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
AnnaBridge 171:3a7713b1edbc 3337 #define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 3338 #define FTM_COMBINE_SYNCEN2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 3339 #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
AnnaBridge 171:3a7713b1edbc 3340 #define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 3341 #define FTM_COMBINE_FAULTEN2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 3342 #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
AnnaBridge 171:3a7713b1edbc 3343 #define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 3344 #define FTM_COMBINE_COMBINE3_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 3345 #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
AnnaBridge 171:3a7713b1edbc 3346 #define FTM_COMBINE_COMP3_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 3347 #define FTM_COMBINE_COMP3_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 3348 #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
AnnaBridge 171:3a7713b1edbc 3349 #define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 3350 #define FTM_COMBINE_DECAPEN3_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 3351 #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
AnnaBridge 171:3a7713b1edbc 3352 #define FTM_COMBINE_DECAP3_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 3353 #define FTM_COMBINE_DECAP3_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 3354 #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
AnnaBridge 171:3a7713b1edbc 3355 #define FTM_COMBINE_DTEN3_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 3356 #define FTM_COMBINE_DTEN3_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 3357 #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
AnnaBridge 171:3a7713b1edbc 3358 #define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 3359 #define FTM_COMBINE_SYNCEN3_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 3360 #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
AnnaBridge 171:3a7713b1edbc 3361 #define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 3362 #define FTM_COMBINE_FAULTEN3_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 3363 #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
AnnaBridge 171:3a7713b1edbc 3364
AnnaBridge 171:3a7713b1edbc 3365 /*! @name DEADTIME - Deadtime Insertion Control */
AnnaBridge 171:3a7713b1edbc 3366 #define FTM_DEADTIME_DTVAL_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 3367 #define FTM_DEADTIME_DTVAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3368 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
AnnaBridge 171:3a7713b1edbc 3369 #define FTM_DEADTIME_DTPS_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 3370 #define FTM_DEADTIME_DTPS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3371 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
AnnaBridge 171:3a7713b1edbc 3372
AnnaBridge 171:3a7713b1edbc 3373 /*! @name EXTTRIG - FTM External Trigger */
AnnaBridge 171:3a7713b1edbc 3374 #define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3375 #define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3376 #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 3377 #define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3378 #define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3379 #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 3380 #define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3381 #define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3382 #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 3383 #define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3384 #define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3385 #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 3386 #define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3387 #define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3388 #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 3389 #define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3390 #define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3391 #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 3392 #define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3393 #define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3394 #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
AnnaBridge 171:3a7713b1edbc 3395 #define FTM_EXTTRIG_TRIGF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3396 #define FTM_EXTTRIG_TRIGF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3397 #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
AnnaBridge 171:3a7713b1edbc 3398
AnnaBridge 171:3a7713b1edbc 3399 /*! @name POL - Channels Polarity */
AnnaBridge 171:3a7713b1edbc 3400 #define FTM_POL_POL0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3401 #define FTM_POL_POL0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3402 #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
AnnaBridge 171:3a7713b1edbc 3403 #define FTM_POL_POL1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3404 #define FTM_POL_POL1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3405 #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
AnnaBridge 171:3a7713b1edbc 3406 #define FTM_POL_POL2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3407 #define FTM_POL_POL2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3408 #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
AnnaBridge 171:3a7713b1edbc 3409 #define FTM_POL_POL3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3410 #define FTM_POL_POL3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3411 #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
AnnaBridge 171:3a7713b1edbc 3412 #define FTM_POL_POL4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3413 #define FTM_POL_POL4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3414 #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
AnnaBridge 171:3a7713b1edbc 3415 #define FTM_POL_POL5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3416 #define FTM_POL_POL5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3417 #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
AnnaBridge 171:3a7713b1edbc 3418 #define FTM_POL_POL6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3419 #define FTM_POL_POL6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3420 #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
AnnaBridge 171:3a7713b1edbc 3421 #define FTM_POL_POL7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3422 #define FTM_POL_POL7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3423 #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
AnnaBridge 171:3a7713b1edbc 3424
AnnaBridge 171:3a7713b1edbc 3425 /*! @name FMS - Fault Mode Status */
AnnaBridge 171:3a7713b1edbc 3426 #define FTM_FMS_FAULTF0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3427 #define FTM_FMS_FAULTF0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3428 #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
AnnaBridge 171:3a7713b1edbc 3429 #define FTM_FMS_FAULTF1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3430 #define FTM_FMS_FAULTF1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3431 #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
AnnaBridge 171:3a7713b1edbc 3432 #define FTM_FMS_FAULTF2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3433 #define FTM_FMS_FAULTF2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3434 #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
AnnaBridge 171:3a7713b1edbc 3435 #define FTM_FMS_FAULTF3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3436 #define FTM_FMS_FAULTF3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3437 #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
AnnaBridge 171:3a7713b1edbc 3438 #define FTM_FMS_FAULTIN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3439 #define FTM_FMS_FAULTIN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3440 #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
AnnaBridge 171:3a7713b1edbc 3441 #define FTM_FMS_WPEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3442 #define FTM_FMS_WPEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3443 #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
AnnaBridge 171:3a7713b1edbc 3444 #define FTM_FMS_FAULTF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3445 #define FTM_FMS_FAULTF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3446 #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
AnnaBridge 171:3a7713b1edbc 3447
AnnaBridge 171:3a7713b1edbc 3448 /*! @name FILTER - Input Capture Filter Control */
AnnaBridge 171:3a7713b1edbc 3449 #define FTM_FILTER_CH0FVAL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 3450 #define FTM_FILTER_CH0FVAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3451 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
AnnaBridge 171:3a7713b1edbc 3452 #define FTM_FILTER_CH1FVAL_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 3453 #define FTM_FILTER_CH1FVAL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3454 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
AnnaBridge 171:3a7713b1edbc 3455 #define FTM_FILTER_CH2FVAL_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 3456 #define FTM_FILTER_CH2FVAL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 3457 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
AnnaBridge 171:3a7713b1edbc 3458 #define FTM_FILTER_CH3FVAL_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 3459 #define FTM_FILTER_CH3FVAL_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 3460 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
AnnaBridge 171:3a7713b1edbc 3461
AnnaBridge 171:3a7713b1edbc 3462 /*! @name FLTCTRL - Fault Control */
AnnaBridge 171:3a7713b1edbc 3463 #define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3464 #define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3465 #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
AnnaBridge 171:3a7713b1edbc 3466 #define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3467 #define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3468 #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
AnnaBridge 171:3a7713b1edbc 3469 #define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3470 #define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3471 #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
AnnaBridge 171:3a7713b1edbc 3472 #define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3473 #define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3474 #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
AnnaBridge 171:3a7713b1edbc 3475 #define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3476 #define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3477 #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
AnnaBridge 171:3a7713b1edbc 3478 #define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3479 #define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3480 #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
AnnaBridge 171:3a7713b1edbc 3481 #define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3482 #define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3483 #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
AnnaBridge 171:3a7713b1edbc 3484 #define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3485 #define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3486 #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
AnnaBridge 171:3a7713b1edbc 3487 #define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 3488 #define FTM_FLTCTRL_FFVAL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 3489 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
AnnaBridge 171:3a7713b1edbc 3490
AnnaBridge 171:3a7713b1edbc 3491 /*! @name QDCTRL - Quadrature Decoder Control And Status */
AnnaBridge 171:3a7713b1edbc 3492 #define FTM_QDCTRL_QUADEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3493 #define FTM_QDCTRL_QUADEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3494 #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
AnnaBridge 171:3a7713b1edbc 3495 #define FTM_QDCTRL_TOFDIR_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3496 #define FTM_QDCTRL_TOFDIR_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3497 #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
AnnaBridge 171:3a7713b1edbc 3498 #define FTM_QDCTRL_QUADIR_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3499 #define FTM_QDCTRL_QUADIR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3500 #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
AnnaBridge 171:3a7713b1edbc 3501 #define FTM_QDCTRL_QUADMODE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3502 #define FTM_QDCTRL_QUADMODE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3503 #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
AnnaBridge 171:3a7713b1edbc 3504 #define FTM_QDCTRL_PHBPOL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3505 #define FTM_QDCTRL_PHBPOL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3506 #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
AnnaBridge 171:3a7713b1edbc 3507 #define FTM_QDCTRL_PHAPOL_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3508 #define FTM_QDCTRL_PHAPOL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3509 #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
AnnaBridge 171:3a7713b1edbc 3510 #define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3511 #define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3512 #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
AnnaBridge 171:3a7713b1edbc 3513 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3514 #define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3515 #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
AnnaBridge 171:3a7713b1edbc 3516
AnnaBridge 171:3a7713b1edbc 3517 /*! @name CONF - Configuration */
AnnaBridge 171:3a7713b1edbc 3518 #define FTM_CONF_NUMTOF_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 3519 #define FTM_CONF_NUMTOF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3520 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
AnnaBridge 171:3a7713b1edbc 3521 #define FTM_CONF_BDMMODE_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 3522 #define FTM_CONF_BDMMODE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3523 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
AnnaBridge 171:3a7713b1edbc 3524 #define FTM_CONF_GTBEEN_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 3525 #define FTM_CONF_GTBEEN_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 3526 #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
AnnaBridge 171:3a7713b1edbc 3527 #define FTM_CONF_GTBEOUT_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 3528 #define FTM_CONF_GTBEOUT_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 3529 #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
AnnaBridge 171:3a7713b1edbc 3530
AnnaBridge 171:3a7713b1edbc 3531 /*! @name FLTPOL - FTM Fault Input Polarity */
AnnaBridge 171:3a7713b1edbc 3532 #define FTM_FLTPOL_FLT0POL_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3533 #define FTM_FLTPOL_FLT0POL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3534 #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
AnnaBridge 171:3a7713b1edbc 3535 #define FTM_FLTPOL_FLT1POL_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3536 #define FTM_FLTPOL_FLT1POL_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3537 #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
AnnaBridge 171:3a7713b1edbc 3538 #define FTM_FLTPOL_FLT2POL_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3539 #define FTM_FLTPOL_FLT2POL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3540 #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
AnnaBridge 171:3a7713b1edbc 3541 #define FTM_FLTPOL_FLT3POL_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3542 #define FTM_FLTPOL_FLT3POL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3543 #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
AnnaBridge 171:3a7713b1edbc 3544
AnnaBridge 171:3a7713b1edbc 3545 /*! @name SYNCONF - Synchronization Configuration */
AnnaBridge 171:3a7713b1edbc 3546 #define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3547 #define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3548 #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
AnnaBridge 171:3a7713b1edbc 3549 #define FTM_SYNCONF_CNTINC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3550 #define FTM_SYNCONF_CNTINC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3551 #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
AnnaBridge 171:3a7713b1edbc 3552 #define FTM_SYNCONF_INVC_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3553 #define FTM_SYNCONF_INVC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3554 #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
AnnaBridge 171:3a7713b1edbc 3555 #define FTM_SYNCONF_SWOC_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3556 #define FTM_SYNCONF_SWOC_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3557 #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
AnnaBridge 171:3a7713b1edbc 3558 #define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3559 #define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3560 #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
AnnaBridge 171:3a7713b1edbc 3561 #define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 3562 #define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 3563 #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
AnnaBridge 171:3a7713b1edbc 3564 #define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 3565 #define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 3566 #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
AnnaBridge 171:3a7713b1edbc 3567 #define FTM_SYNCONF_SWOM_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 3568 #define FTM_SYNCONF_SWOM_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 3569 #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
AnnaBridge 171:3a7713b1edbc 3570 #define FTM_SYNCONF_SWINVC_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 3571 #define FTM_SYNCONF_SWINVC_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 3572 #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
AnnaBridge 171:3a7713b1edbc 3573 #define FTM_SYNCONF_SWSOC_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 3574 #define FTM_SYNCONF_SWSOC_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 3575 #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
AnnaBridge 171:3a7713b1edbc 3576 #define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 3577 #define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3578 #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
AnnaBridge 171:3a7713b1edbc 3579 #define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 3580 #define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 3581 #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
AnnaBridge 171:3a7713b1edbc 3582 #define FTM_SYNCONF_HWOM_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 3583 #define FTM_SYNCONF_HWOM_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 3584 #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
AnnaBridge 171:3a7713b1edbc 3585 #define FTM_SYNCONF_HWINVC_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 3586 #define FTM_SYNCONF_HWINVC_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 3587 #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
AnnaBridge 171:3a7713b1edbc 3588 #define FTM_SYNCONF_HWSOC_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 3589 #define FTM_SYNCONF_HWSOC_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 3590 #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
AnnaBridge 171:3a7713b1edbc 3591
AnnaBridge 171:3a7713b1edbc 3592 /*! @name INVCTRL - FTM Inverting Control */
AnnaBridge 171:3a7713b1edbc 3593 #define FTM_INVCTRL_INV0EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3594 #define FTM_INVCTRL_INV0EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3595 #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
AnnaBridge 171:3a7713b1edbc 3596 #define FTM_INVCTRL_INV1EN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3597 #define FTM_INVCTRL_INV1EN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3598 #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
AnnaBridge 171:3a7713b1edbc 3599 #define FTM_INVCTRL_INV2EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3600 #define FTM_INVCTRL_INV2EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3601 #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
AnnaBridge 171:3a7713b1edbc 3602 #define FTM_INVCTRL_INV3EN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3603 #define FTM_INVCTRL_INV3EN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3604 #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
AnnaBridge 171:3a7713b1edbc 3605
AnnaBridge 171:3a7713b1edbc 3606 /*! @name SWOCTRL - FTM Software Output Control */
AnnaBridge 171:3a7713b1edbc 3607 #define FTM_SWOCTRL_CH0OC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3608 #define FTM_SWOCTRL_CH0OC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3609 #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
AnnaBridge 171:3a7713b1edbc 3610 #define FTM_SWOCTRL_CH1OC_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3611 #define FTM_SWOCTRL_CH1OC_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3612 #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
AnnaBridge 171:3a7713b1edbc 3613 #define FTM_SWOCTRL_CH2OC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3614 #define FTM_SWOCTRL_CH2OC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3615 #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
AnnaBridge 171:3a7713b1edbc 3616 #define FTM_SWOCTRL_CH3OC_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3617 #define FTM_SWOCTRL_CH3OC_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3618 #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
AnnaBridge 171:3a7713b1edbc 3619 #define FTM_SWOCTRL_CH4OC_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3620 #define FTM_SWOCTRL_CH4OC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3621 #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
AnnaBridge 171:3a7713b1edbc 3622 #define FTM_SWOCTRL_CH5OC_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3623 #define FTM_SWOCTRL_CH5OC_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3624 #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
AnnaBridge 171:3a7713b1edbc 3625 #define FTM_SWOCTRL_CH6OC_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3626 #define FTM_SWOCTRL_CH6OC_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3627 #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
AnnaBridge 171:3a7713b1edbc 3628 #define FTM_SWOCTRL_CH7OC_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3629 #define FTM_SWOCTRL_CH7OC_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3630 #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
AnnaBridge 171:3a7713b1edbc 3631 #define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 3632 #define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 3633 #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
AnnaBridge 171:3a7713b1edbc 3634 #define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 3635 #define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 3636 #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
AnnaBridge 171:3a7713b1edbc 3637 #define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 3638 #define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 3639 #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
AnnaBridge 171:3a7713b1edbc 3640 #define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 3641 #define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 3642 #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
AnnaBridge 171:3a7713b1edbc 3643 #define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 3644 #define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 3645 #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
AnnaBridge 171:3a7713b1edbc 3646 #define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 3647 #define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 3648 #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
AnnaBridge 171:3a7713b1edbc 3649 #define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 3650 #define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 3651 #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
AnnaBridge 171:3a7713b1edbc 3652 #define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 3653 #define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 3654 #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
AnnaBridge 171:3a7713b1edbc 3655
AnnaBridge 171:3a7713b1edbc 3656 /*! @name PWMLOAD - FTM PWM Load */
AnnaBridge 171:3a7713b1edbc 3657 #define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3658 #define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3659 #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
AnnaBridge 171:3a7713b1edbc 3660 #define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3661 #define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3662 #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
AnnaBridge 171:3a7713b1edbc 3663 #define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3664 #define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3665 #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
AnnaBridge 171:3a7713b1edbc 3666 #define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3667 #define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3668 #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
AnnaBridge 171:3a7713b1edbc 3669 #define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3670 #define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3671 #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
AnnaBridge 171:3a7713b1edbc 3672 #define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3673 #define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3674 #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
AnnaBridge 171:3a7713b1edbc 3675 #define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3676 #define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3677 #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
AnnaBridge 171:3a7713b1edbc 3678 #define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3679 #define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3680 #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
AnnaBridge 171:3a7713b1edbc 3681 #define FTM_PWMLOAD_LDOK_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 3682 #define FTM_PWMLOAD_LDOK_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 3683 #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
AnnaBridge 171:3a7713b1edbc 3684
AnnaBridge 171:3a7713b1edbc 3685
AnnaBridge 171:3a7713b1edbc 3686 /*!
AnnaBridge 171:3a7713b1edbc 3687 * @}
AnnaBridge 171:3a7713b1edbc 3688 */ /* end of group FTM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3689
AnnaBridge 171:3a7713b1edbc 3690
AnnaBridge 171:3a7713b1edbc 3691 /* FTM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3692 /** Peripheral FTM0 base address */
AnnaBridge 171:3a7713b1edbc 3693 #define FTM0_BASE (0x40038000u)
AnnaBridge 171:3a7713b1edbc 3694 /** Peripheral FTM0 base pointer */
AnnaBridge 171:3a7713b1edbc 3695 #define FTM0 ((FTM_Type *)FTM0_BASE)
AnnaBridge 171:3a7713b1edbc 3696 /** Peripheral FTM1 base address */
AnnaBridge 171:3a7713b1edbc 3697 #define FTM1_BASE (0x40039000u)
AnnaBridge 171:3a7713b1edbc 3698 /** Peripheral FTM1 base pointer */
AnnaBridge 171:3a7713b1edbc 3699 #define FTM1 ((FTM_Type *)FTM1_BASE)
AnnaBridge 171:3a7713b1edbc 3700 /** Peripheral FTM2 base address */
AnnaBridge 171:3a7713b1edbc 3701 #define FTM2_BASE (0x4003A000u)
AnnaBridge 171:3a7713b1edbc 3702 /** Peripheral FTM2 base pointer */
AnnaBridge 171:3a7713b1edbc 3703 #define FTM2 ((FTM_Type *)FTM2_BASE)
AnnaBridge 171:3a7713b1edbc 3704 /** Array initializer of FTM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3705 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE }
AnnaBridge 171:3a7713b1edbc 3706 /** Array initializer of FTM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3707 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2 }
AnnaBridge 171:3a7713b1edbc 3708 /** Interrupt vectors for the FTM peripheral type */
AnnaBridge 171:3a7713b1edbc 3709 #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn }
AnnaBridge 171:3a7713b1edbc 3710
AnnaBridge 171:3a7713b1edbc 3711 /*!
AnnaBridge 171:3a7713b1edbc 3712 * @}
AnnaBridge 171:3a7713b1edbc 3713 */ /* end of group FTM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3714
AnnaBridge 171:3a7713b1edbc 3715
AnnaBridge 171:3a7713b1edbc 3716 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3717 -- GPIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3718 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3719
AnnaBridge 171:3a7713b1edbc 3720 /*!
AnnaBridge 171:3a7713b1edbc 3721 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3722 * @{
AnnaBridge 171:3a7713b1edbc 3723 */
AnnaBridge 171:3a7713b1edbc 3724
AnnaBridge 171:3a7713b1edbc 3725 /** GPIO - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3726 typedef struct {
AnnaBridge 171:3a7713b1edbc 3727 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3728 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3729 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3730 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 3731 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 3732 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 3733 } GPIO_Type;
AnnaBridge 171:3a7713b1edbc 3734
AnnaBridge 171:3a7713b1edbc 3735 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3736 -- GPIO Register Masks
AnnaBridge 171:3a7713b1edbc 3737 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3738
AnnaBridge 171:3a7713b1edbc 3739 /*!
AnnaBridge 171:3a7713b1edbc 3740 * @addtogroup GPIO_Register_Masks GPIO Register Masks
AnnaBridge 171:3a7713b1edbc 3741 * @{
AnnaBridge 171:3a7713b1edbc 3742 */
AnnaBridge 171:3a7713b1edbc 3743
AnnaBridge 171:3a7713b1edbc 3744 /*! @name PDOR - Port Data Output Register */
AnnaBridge 171:3a7713b1edbc 3745 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3746 #define GPIO_PDOR_PDO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3747 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
AnnaBridge 171:3a7713b1edbc 3748
AnnaBridge 171:3a7713b1edbc 3749 /*! @name PSOR - Port Set Output Register */
AnnaBridge 171:3a7713b1edbc 3750 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3751 #define GPIO_PSOR_PTSO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3752 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
AnnaBridge 171:3a7713b1edbc 3753
AnnaBridge 171:3a7713b1edbc 3754 /*! @name PCOR - Port Clear Output Register */
AnnaBridge 171:3a7713b1edbc 3755 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3756 #define GPIO_PCOR_PTCO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3757 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
AnnaBridge 171:3a7713b1edbc 3758
AnnaBridge 171:3a7713b1edbc 3759 /*! @name PTOR - Port Toggle Output Register */
AnnaBridge 171:3a7713b1edbc 3760 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3761 #define GPIO_PTOR_PTTO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3762 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
AnnaBridge 171:3a7713b1edbc 3763
AnnaBridge 171:3a7713b1edbc 3764 /*! @name PDIR - Port Data Input Register */
AnnaBridge 171:3a7713b1edbc 3765 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3766 #define GPIO_PDIR_PDI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3767 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
AnnaBridge 171:3a7713b1edbc 3768
AnnaBridge 171:3a7713b1edbc 3769 /*! @name PDDR - Port Data Direction Register */
AnnaBridge 171:3a7713b1edbc 3770 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3771 #define GPIO_PDDR_PDD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3772 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
AnnaBridge 171:3a7713b1edbc 3773
AnnaBridge 171:3a7713b1edbc 3774
AnnaBridge 171:3a7713b1edbc 3775 /*!
AnnaBridge 171:3a7713b1edbc 3776 * @}
AnnaBridge 171:3a7713b1edbc 3777 */ /* end of group GPIO_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3778
AnnaBridge 171:3a7713b1edbc 3779
AnnaBridge 171:3a7713b1edbc 3780 /* GPIO - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3781 /** Peripheral GPIOA base address */
AnnaBridge 171:3a7713b1edbc 3782 #define GPIOA_BASE (0x400FF000u)
AnnaBridge 171:3a7713b1edbc 3783 /** Peripheral GPIOA base pointer */
AnnaBridge 171:3a7713b1edbc 3784 #define GPIOA ((GPIO_Type *)GPIOA_BASE)
AnnaBridge 171:3a7713b1edbc 3785 /** Peripheral GPIOB base address */
AnnaBridge 171:3a7713b1edbc 3786 #define GPIOB_BASE (0x400FF040u)
AnnaBridge 171:3a7713b1edbc 3787 /** Peripheral GPIOB base pointer */
AnnaBridge 171:3a7713b1edbc 3788 #define GPIOB ((GPIO_Type *)GPIOB_BASE)
AnnaBridge 171:3a7713b1edbc 3789 /** Peripheral GPIOC base address */
AnnaBridge 171:3a7713b1edbc 3790 #define GPIOC_BASE (0x400FF080u)
AnnaBridge 171:3a7713b1edbc 3791 /** Peripheral GPIOC base pointer */
AnnaBridge 171:3a7713b1edbc 3792 #define GPIOC ((GPIO_Type *)GPIOC_BASE)
AnnaBridge 171:3a7713b1edbc 3793 /** Peripheral GPIOD base address */
AnnaBridge 171:3a7713b1edbc 3794 #define GPIOD_BASE (0x400FF0C0u)
AnnaBridge 171:3a7713b1edbc 3795 /** Peripheral GPIOD base pointer */
AnnaBridge 171:3a7713b1edbc 3796 #define GPIOD ((GPIO_Type *)GPIOD_BASE)
AnnaBridge 171:3a7713b1edbc 3797 /** Peripheral GPIOE base address */
AnnaBridge 171:3a7713b1edbc 3798 #define GPIOE_BASE (0x400FF100u)
AnnaBridge 171:3a7713b1edbc 3799 /** Peripheral GPIOE base pointer */
AnnaBridge 171:3a7713b1edbc 3800 #define GPIOE ((GPIO_Type *)GPIOE_BASE)
AnnaBridge 171:3a7713b1edbc 3801 /** Array initializer of GPIO peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3802 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
AnnaBridge 171:3a7713b1edbc 3803 /** Array initializer of GPIO peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3804 #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
AnnaBridge 171:3a7713b1edbc 3805
AnnaBridge 171:3a7713b1edbc 3806 /*!
AnnaBridge 171:3a7713b1edbc 3807 * @}
AnnaBridge 171:3a7713b1edbc 3808 */ /* end of group GPIO_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3809
AnnaBridge 171:3a7713b1edbc 3810
AnnaBridge 171:3a7713b1edbc 3811 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3812 -- I2C Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3813 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3814
AnnaBridge 171:3a7713b1edbc 3815 /*!
AnnaBridge 171:3a7713b1edbc 3816 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3817 * @{
AnnaBridge 171:3a7713b1edbc 3818 */
AnnaBridge 171:3a7713b1edbc 3819
AnnaBridge 171:3a7713b1edbc 3820 /** I2C - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3821 typedef struct {
AnnaBridge 171:3a7713b1edbc 3822 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3823 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 3824 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 3825 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 3826 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3827 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 3828 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 3829 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 3830 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3831 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 3832 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 3833 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 3834 } I2C_Type;
AnnaBridge 171:3a7713b1edbc 3835
AnnaBridge 171:3a7713b1edbc 3836 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3837 -- I2C Register Masks
AnnaBridge 171:3a7713b1edbc 3838 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3839
AnnaBridge 171:3a7713b1edbc 3840 /*!
AnnaBridge 171:3a7713b1edbc 3841 * @addtogroup I2C_Register_Masks I2C Register Masks
AnnaBridge 171:3a7713b1edbc 3842 * @{
AnnaBridge 171:3a7713b1edbc 3843 */
AnnaBridge 171:3a7713b1edbc 3844
AnnaBridge 171:3a7713b1edbc 3845 /*! @name A1 - I2C Address Register 1 */
AnnaBridge 171:3a7713b1edbc 3846 #define I2C_A1_AD_MASK (0xFEU)
AnnaBridge 171:3a7713b1edbc 3847 #define I2C_A1_AD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3848 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
AnnaBridge 171:3a7713b1edbc 3849
AnnaBridge 171:3a7713b1edbc 3850 /*! @name F - I2C Frequency Divider register */
AnnaBridge 171:3a7713b1edbc 3851 #define I2C_F_ICR_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 3852 #define I2C_F_ICR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3853 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
AnnaBridge 171:3a7713b1edbc 3854 #define I2C_F_MULT_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 3855 #define I2C_F_MULT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3856 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
AnnaBridge 171:3a7713b1edbc 3857
AnnaBridge 171:3a7713b1edbc 3858 /*! @name C1 - I2C Control Register 1 */
AnnaBridge 171:3a7713b1edbc 3859 #define I2C_C1_DMAEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3860 #define I2C_C1_DMAEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3861 #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 3862 #define I2C_C1_WUEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3863 #define I2C_C1_WUEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3864 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
AnnaBridge 171:3a7713b1edbc 3865 #define I2C_C1_RSTA_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3866 #define I2C_C1_RSTA_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3867 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
AnnaBridge 171:3a7713b1edbc 3868 #define I2C_C1_TXAK_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3869 #define I2C_C1_TXAK_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3870 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
AnnaBridge 171:3a7713b1edbc 3871 #define I2C_C1_TX_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3872 #define I2C_C1_TX_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3873 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
AnnaBridge 171:3a7713b1edbc 3874 #define I2C_C1_MST_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3875 #define I2C_C1_MST_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3876 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
AnnaBridge 171:3a7713b1edbc 3877 #define I2C_C1_IICIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3878 #define I2C_C1_IICIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3879 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
AnnaBridge 171:3a7713b1edbc 3880 #define I2C_C1_IICEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3881 #define I2C_C1_IICEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3882 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
AnnaBridge 171:3a7713b1edbc 3883
AnnaBridge 171:3a7713b1edbc 3884 /*! @name S - I2C Status register */
AnnaBridge 171:3a7713b1edbc 3885 #define I2C_S_RXAK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3886 #define I2C_S_RXAK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3887 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
AnnaBridge 171:3a7713b1edbc 3888 #define I2C_S_IICIF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3889 #define I2C_S_IICIF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3890 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
AnnaBridge 171:3a7713b1edbc 3891 #define I2C_S_SRW_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3892 #define I2C_S_SRW_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3893 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
AnnaBridge 171:3a7713b1edbc 3894 #define I2C_S_RAM_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3895 #define I2C_S_RAM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3896 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
AnnaBridge 171:3a7713b1edbc 3897 #define I2C_S_ARBL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3898 #define I2C_S_ARBL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3899 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
AnnaBridge 171:3a7713b1edbc 3900 #define I2C_S_BUSY_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3901 #define I2C_S_BUSY_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3902 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
AnnaBridge 171:3a7713b1edbc 3903 #define I2C_S_IAAS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3904 #define I2C_S_IAAS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3905 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
AnnaBridge 171:3a7713b1edbc 3906 #define I2C_S_TCF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3907 #define I2C_S_TCF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3908 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
AnnaBridge 171:3a7713b1edbc 3909
AnnaBridge 171:3a7713b1edbc 3910 /*! @name D - I2C Data I/O register */
AnnaBridge 171:3a7713b1edbc 3911 #define I2C_D_DATA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3912 #define I2C_D_DATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3913 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
AnnaBridge 171:3a7713b1edbc 3914
AnnaBridge 171:3a7713b1edbc 3915 /*! @name C2 - I2C Control Register 2 */
AnnaBridge 171:3a7713b1edbc 3916 #define I2C_C2_AD_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 3917 #define I2C_C2_AD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3918 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
AnnaBridge 171:3a7713b1edbc 3919 #define I2C_C2_RMEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3920 #define I2C_C2_RMEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3921 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
AnnaBridge 171:3a7713b1edbc 3922 #define I2C_C2_SBRC_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3923 #define I2C_C2_SBRC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3924 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
AnnaBridge 171:3a7713b1edbc 3925 #define I2C_C2_HDRS_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3926 #define I2C_C2_HDRS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3927 #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
AnnaBridge 171:3a7713b1edbc 3928 #define I2C_C2_ADEXT_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3929 #define I2C_C2_ADEXT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3930 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
AnnaBridge 171:3a7713b1edbc 3931 #define I2C_C2_GCAEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3932 #define I2C_C2_GCAEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3933 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
AnnaBridge 171:3a7713b1edbc 3934
AnnaBridge 171:3a7713b1edbc 3935 /*! @name FLT - I2C Programmable Input Glitch Filter register */
AnnaBridge 171:3a7713b1edbc 3936 #define I2C_FLT_FLT_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 3937 #define I2C_FLT_FLT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3938 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
AnnaBridge 171:3a7713b1edbc 3939
AnnaBridge 171:3a7713b1edbc 3940 /*! @name RA - I2C Range Address register */
AnnaBridge 171:3a7713b1edbc 3941 #define I2C_RA_RAD_MASK (0xFEU)
AnnaBridge 171:3a7713b1edbc 3942 #define I2C_RA_RAD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3943 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
AnnaBridge 171:3a7713b1edbc 3944
AnnaBridge 171:3a7713b1edbc 3945 /*! @name SMB - I2C SMBus Control and Status register */
AnnaBridge 171:3a7713b1edbc 3946 #define I2C_SMB_SHTF2IE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3947 #define I2C_SMB_SHTF2IE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3948 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
AnnaBridge 171:3a7713b1edbc 3949 #define I2C_SMB_SHTF2_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3950 #define I2C_SMB_SHTF2_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3951 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
AnnaBridge 171:3a7713b1edbc 3952 #define I2C_SMB_SHTF1_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3953 #define I2C_SMB_SHTF1_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3954 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
AnnaBridge 171:3a7713b1edbc 3955 #define I2C_SMB_SLTF_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3956 #define I2C_SMB_SLTF_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3957 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
AnnaBridge 171:3a7713b1edbc 3958 #define I2C_SMB_TCKSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3959 #define I2C_SMB_TCKSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3960 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 3961 #define I2C_SMB_SIICAEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3962 #define I2C_SMB_SIICAEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3963 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
AnnaBridge 171:3a7713b1edbc 3964 #define I2C_SMB_ALERTEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3965 #define I2C_SMB_ALERTEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3966 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
AnnaBridge 171:3a7713b1edbc 3967 #define I2C_SMB_FACK_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3968 #define I2C_SMB_FACK_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3969 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
AnnaBridge 171:3a7713b1edbc 3970
AnnaBridge 171:3a7713b1edbc 3971 /*! @name A2 - I2C Address Register 2 */
AnnaBridge 171:3a7713b1edbc 3972 #define I2C_A2_SAD_MASK (0xFEU)
AnnaBridge 171:3a7713b1edbc 3973 #define I2C_A2_SAD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3974 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
AnnaBridge 171:3a7713b1edbc 3975
AnnaBridge 171:3a7713b1edbc 3976 /*! @name SLTH - I2C SCL Low Timeout Register High */
AnnaBridge 171:3a7713b1edbc 3977 #define I2C_SLTH_SSLT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3978 #define I2C_SLTH_SSLT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3979 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
AnnaBridge 171:3a7713b1edbc 3980
AnnaBridge 171:3a7713b1edbc 3981 /*! @name SLTL - I2C SCL Low Timeout Register Low */
AnnaBridge 171:3a7713b1edbc 3982 #define I2C_SLTL_SSLT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3983 #define I2C_SLTL_SSLT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3984 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
AnnaBridge 171:3a7713b1edbc 3985
AnnaBridge 171:3a7713b1edbc 3986
AnnaBridge 171:3a7713b1edbc 3987 /*!
AnnaBridge 171:3a7713b1edbc 3988 * @}
AnnaBridge 171:3a7713b1edbc 3989 */ /* end of group I2C_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3990
AnnaBridge 171:3a7713b1edbc 3991
AnnaBridge 171:3a7713b1edbc 3992 /* I2C - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3993 /** Peripheral I2C0 base address */
AnnaBridge 171:3a7713b1edbc 3994 #define I2C0_BASE (0x40066000u)
AnnaBridge 171:3a7713b1edbc 3995 /** Peripheral I2C0 base pointer */
AnnaBridge 171:3a7713b1edbc 3996 #define I2C0 ((I2C_Type *)I2C0_BASE)
AnnaBridge 171:3a7713b1edbc 3997 /** Peripheral I2C1 base address */
AnnaBridge 171:3a7713b1edbc 3998 #define I2C1_BASE (0x40067000u)
AnnaBridge 171:3a7713b1edbc 3999 /** Peripheral I2C1 base pointer */
AnnaBridge 171:3a7713b1edbc 4000 #define I2C1 ((I2C_Type *)I2C1_BASE)
AnnaBridge 171:3a7713b1edbc 4001 /** Array initializer of I2C peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 4002 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
AnnaBridge 171:3a7713b1edbc 4003 /** Array initializer of I2C peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4004 #define I2C_BASE_PTRS { I2C0, I2C1 }
AnnaBridge 171:3a7713b1edbc 4005 /** Interrupt vectors for the I2C peripheral type */
AnnaBridge 171:3a7713b1edbc 4006 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
AnnaBridge 171:3a7713b1edbc 4007
AnnaBridge 171:3a7713b1edbc 4008 /*!
AnnaBridge 171:3a7713b1edbc 4009 * @}
AnnaBridge 171:3a7713b1edbc 4010 */ /* end of group I2C_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4011
AnnaBridge 171:3a7713b1edbc 4012
AnnaBridge 171:3a7713b1edbc 4013 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4014 -- I2S Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4015 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4016
AnnaBridge 171:3a7713b1edbc 4017 /*!
AnnaBridge 171:3a7713b1edbc 4018 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4019 * @{
AnnaBridge 171:3a7713b1edbc 4020 */
AnnaBridge 171:3a7713b1edbc 4021
AnnaBridge 171:3a7713b1edbc 4022 /** I2S - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4023 typedef struct {
AnnaBridge 171:3a7713b1edbc 4024 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 4025 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 4026 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 4027 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 4028 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 4029 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 4030 uint8_t RESERVED_0[8];
AnnaBridge 171:3a7713b1edbc 4031 __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 4032 uint8_t RESERVED_1[28];
AnnaBridge 171:3a7713b1edbc 4033 __I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 4034 uint8_t RESERVED_2[28];
AnnaBridge 171:3a7713b1edbc 4035 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 4036 uint8_t RESERVED_3[28];
AnnaBridge 171:3a7713b1edbc 4037 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 4038 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 4039 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 4040 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 4041 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 4042 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 4043 uint8_t RESERVED_4[8];
AnnaBridge 171:3a7713b1edbc 4044 __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 4045 uint8_t RESERVED_5[28];
AnnaBridge 171:3a7713b1edbc 4046 __I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 4047 uint8_t RESERVED_6[28];
AnnaBridge 171:3a7713b1edbc 4048 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
AnnaBridge 171:3a7713b1edbc 4049 uint8_t RESERVED_7[28];
AnnaBridge 171:3a7713b1edbc 4050 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
AnnaBridge 171:3a7713b1edbc 4051 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
AnnaBridge 171:3a7713b1edbc 4052 } I2S_Type;
AnnaBridge 171:3a7713b1edbc 4053
AnnaBridge 171:3a7713b1edbc 4054 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4055 -- I2S Register Masks
AnnaBridge 171:3a7713b1edbc 4056 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4057
AnnaBridge 171:3a7713b1edbc 4058 /*!
AnnaBridge 171:3a7713b1edbc 4059 * @addtogroup I2S_Register_Masks I2S Register Masks
AnnaBridge 171:3a7713b1edbc 4060 * @{
AnnaBridge 171:3a7713b1edbc 4061 */
AnnaBridge 171:3a7713b1edbc 4062
AnnaBridge 171:3a7713b1edbc 4063 /*! @name TCSR - SAI Transmit Control Register */
AnnaBridge 171:3a7713b1edbc 4064 #define I2S_TCSR_FRDE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4065 #define I2S_TCSR_FRDE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4066 #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
AnnaBridge 171:3a7713b1edbc 4067 #define I2S_TCSR_FWDE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4068 #define I2S_TCSR_FWDE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4069 #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
AnnaBridge 171:3a7713b1edbc 4070 #define I2S_TCSR_FRIE_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 4071 #define I2S_TCSR_FRIE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4072 #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
AnnaBridge 171:3a7713b1edbc 4073 #define I2S_TCSR_FWIE_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 4074 #define I2S_TCSR_FWIE_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 4075 #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
AnnaBridge 171:3a7713b1edbc 4076 #define I2S_TCSR_FEIE_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 4077 #define I2S_TCSR_FEIE_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 4078 #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
AnnaBridge 171:3a7713b1edbc 4079 #define I2S_TCSR_SEIE_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 4080 #define I2S_TCSR_SEIE_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 4081 #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
AnnaBridge 171:3a7713b1edbc 4082 #define I2S_TCSR_WSIE_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 4083 #define I2S_TCSR_WSIE_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 4084 #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
AnnaBridge 171:3a7713b1edbc 4085 #define I2S_TCSR_FRF_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 4086 #define I2S_TCSR_FRF_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4087 #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
AnnaBridge 171:3a7713b1edbc 4088 #define I2S_TCSR_FWF_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 4089 #define I2S_TCSR_FWF_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 4090 #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
AnnaBridge 171:3a7713b1edbc 4091 #define I2S_TCSR_FEF_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 4092 #define I2S_TCSR_FEF_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 4093 #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
AnnaBridge 171:3a7713b1edbc 4094 #define I2S_TCSR_SEF_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 4095 #define I2S_TCSR_SEF_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 4096 #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
AnnaBridge 171:3a7713b1edbc 4097 #define I2S_TCSR_WSF_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 4098 #define I2S_TCSR_WSF_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 4099 #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
AnnaBridge 171:3a7713b1edbc 4100 #define I2S_TCSR_SR_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 4101 #define I2S_TCSR_SR_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4102 #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
AnnaBridge 171:3a7713b1edbc 4103 #define I2S_TCSR_FR_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 4104 #define I2S_TCSR_FR_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 4105 #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
AnnaBridge 171:3a7713b1edbc 4106 #define I2S_TCSR_BCE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 4107 #define I2S_TCSR_BCE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 4108 #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
AnnaBridge 171:3a7713b1edbc 4109 #define I2S_TCSR_DBGE_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 4110 #define I2S_TCSR_DBGE_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 4111 #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
AnnaBridge 171:3a7713b1edbc 4112 #define I2S_TCSR_STOPE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 4113 #define I2S_TCSR_STOPE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 4114 #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
AnnaBridge 171:3a7713b1edbc 4115 #define I2S_TCSR_TE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 4116 #define I2S_TCSR_TE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 4117 #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
AnnaBridge 171:3a7713b1edbc 4118
AnnaBridge 171:3a7713b1edbc 4119 /*! @name TCR1 - SAI Transmit Configuration 1 Register */
AnnaBridge 171:3a7713b1edbc 4120 #define I2S_TCR1_TFW_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 4121 #define I2S_TCR1_TFW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4122 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
AnnaBridge 171:3a7713b1edbc 4123
AnnaBridge 171:3a7713b1edbc 4124 /*! @name TCR2 - SAI Transmit Configuration 2 Register */
AnnaBridge 171:3a7713b1edbc 4125 #define I2S_TCR2_DIV_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 4126 #define I2S_TCR2_DIV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4127 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
AnnaBridge 171:3a7713b1edbc 4128 #define I2S_TCR2_BCD_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 4129 #define I2S_TCR2_BCD_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4130 #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
AnnaBridge 171:3a7713b1edbc 4131 #define I2S_TCR2_BCP_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 4132 #define I2S_TCR2_BCP_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 4133 #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
AnnaBridge 171:3a7713b1edbc 4134 #define I2S_TCR2_MSEL_MASK (0xC000000U)
AnnaBridge 171:3a7713b1edbc 4135 #define I2S_TCR2_MSEL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 4136 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
AnnaBridge 171:3a7713b1edbc 4137 #define I2S_TCR2_BCI_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 4138 #define I2S_TCR2_BCI_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 4139 #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
AnnaBridge 171:3a7713b1edbc 4140 #define I2S_TCR2_BCS_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 4141 #define I2S_TCR2_BCS_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 4142 #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
AnnaBridge 171:3a7713b1edbc 4143 #define I2S_TCR2_SYNC_MASK (0xC0000000U)
AnnaBridge 171:3a7713b1edbc 4144 #define I2S_TCR2_SYNC_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 4145 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
AnnaBridge 171:3a7713b1edbc 4146
AnnaBridge 171:3a7713b1edbc 4147 /*! @name TCR3 - SAI Transmit Configuration 3 Register */
AnnaBridge 171:3a7713b1edbc 4148 #define I2S_TCR3_WDFL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4149 #define I2S_TCR3_WDFL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4150 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
AnnaBridge 171:3a7713b1edbc 4151 #define I2S_TCR3_TCE_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 4152 #define I2S_TCR3_TCE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4153 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
AnnaBridge 171:3a7713b1edbc 4154
AnnaBridge 171:3a7713b1edbc 4155 /*! @name TCR4 - SAI Transmit Configuration 4 Register */
AnnaBridge 171:3a7713b1edbc 4156 #define I2S_TCR4_FSD_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4157 #define I2S_TCR4_FSD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4158 #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
AnnaBridge 171:3a7713b1edbc 4159 #define I2S_TCR4_FSP_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4160 #define I2S_TCR4_FSP_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4161 #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
AnnaBridge 171:3a7713b1edbc 4162 #define I2S_TCR4_FSE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4163 #define I2S_TCR4_FSE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4164 #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
AnnaBridge 171:3a7713b1edbc 4165 #define I2S_TCR4_MF_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4166 #define I2S_TCR4_MF_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4167 #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
AnnaBridge 171:3a7713b1edbc 4168 #define I2S_TCR4_SYWD_MASK (0x1F00U)
AnnaBridge 171:3a7713b1edbc 4169 #define I2S_TCR4_SYWD_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4170 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
AnnaBridge 171:3a7713b1edbc 4171 #define I2S_TCR4_FRSZ_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 4172 #define I2S_TCR4_FRSZ_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4173 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
AnnaBridge 171:3a7713b1edbc 4174
AnnaBridge 171:3a7713b1edbc 4175 /*! @name TCR5 - SAI Transmit Configuration 5 Register */
AnnaBridge 171:3a7713b1edbc 4176 #define I2S_TCR5_FBT_MASK (0x1F00U)
AnnaBridge 171:3a7713b1edbc 4177 #define I2S_TCR5_FBT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4178 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
AnnaBridge 171:3a7713b1edbc 4179 #define I2S_TCR5_W0W_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 4180 #define I2S_TCR5_W0W_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4181 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
AnnaBridge 171:3a7713b1edbc 4182 #define I2S_TCR5_WNW_MASK (0x1F000000U)
AnnaBridge 171:3a7713b1edbc 4183 #define I2S_TCR5_WNW_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4184 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
AnnaBridge 171:3a7713b1edbc 4185
AnnaBridge 171:3a7713b1edbc 4186 /*! @name TDR - SAI Transmit Data Register */
AnnaBridge 171:3a7713b1edbc 4187 #define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4188 #define I2S_TDR_TDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4189 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
AnnaBridge 171:3a7713b1edbc 4190
AnnaBridge 171:3a7713b1edbc 4191 /* The count of I2S_TDR */
AnnaBridge 171:3a7713b1edbc 4192 #define I2S_TDR_COUNT (1U)
AnnaBridge 171:3a7713b1edbc 4193
AnnaBridge 171:3a7713b1edbc 4194 /*! @name TFR - SAI Transmit FIFO Register */
AnnaBridge 171:3a7713b1edbc 4195 #define I2S_TFR_RFP_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4196 #define I2S_TFR_RFP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4197 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
AnnaBridge 171:3a7713b1edbc 4198 #define I2S_TFR_WFP_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 4199 #define I2S_TFR_WFP_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4200 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
AnnaBridge 171:3a7713b1edbc 4201
AnnaBridge 171:3a7713b1edbc 4202 /* The count of I2S_TFR */
AnnaBridge 171:3a7713b1edbc 4203 #define I2S_TFR_COUNT (1U)
AnnaBridge 171:3a7713b1edbc 4204
AnnaBridge 171:3a7713b1edbc 4205 /*! @name TMR - SAI Transmit Mask Register */
AnnaBridge 171:3a7713b1edbc 4206 #define I2S_TMR_TWM_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 4207 #define I2S_TMR_TWM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4208 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
AnnaBridge 171:3a7713b1edbc 4209
AnnaBridge 171:3a7713b1edbc 4210 /*! @name RCSR - SAI Receive Control Register */
AnnaBridge 171:3a7713b1edbc 4211 #define I2S_RCSR_FRDE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4212 #define I2S_RCSR_FRDE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4213 #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
AnnaBridge 171:3a7713b1edbc 4214 #define I2S_RCSR_FWDE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4215 #define I2S_RCSR_FWDE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4216 #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
AnnaBridge 171:3a7713b1edbc 4217 #define I2S_RCSR_FRIE_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 4218 #define I2S_RCSR_FRIE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4219 #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
AnnaBridge 171:3a7713b1edbc 4220 #define I2S_RCSR_FWIE_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 4221 #define I2S_RCSR_FWIE_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 4222 #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
AnnaBridge 171:3a7713b1edbc 4223 #define I2S_RCSR_FEIE_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 4224 #define I2S_RCSR_FEIE_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 4225 #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
AnnaBridge 171:3a7713b1edbc 4226 #define I2S_RCSR_SEIE_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 4227 #define I2S_RCSR_SEIE_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 4228 #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
AnnaBridge 171:3a7713b1edbc 4229 #define I2S_RCSR_WSIE_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 4230 #define I2S_RCSR_WSIE_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 4231 #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
AnnaBridge 171:3a7713b1edbc 4232 #define I2S_RCSR_FRF_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 4233 #define I2S_RCSR_FRF_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4234 #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
AnnaBridge 171:3a7713b1edbc 4235 #define I2S_RCSR_FWF_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 4236 #define I2S_RCSR_FWF_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 4237 #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
AnnaBridge 171:3a7713b1edbc 4238 #define I2S_RCSR_FEF_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 4239 #define I2S_RCSR_FEF_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 4240 #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
AnnaBridge 171:3a7713b1edbc 4241 #define I2S_RCSR_SEF_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 4242 #define I2S_RCSR_SEF_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 4243 #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
AnnaBridge 171:3a7713b1edbc 4244 #define I2S_RCSR_WSF_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 4245 #define I2S_RCSR_WSF_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 4246 #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
AnnaBridge 171:3a7713b1edbc 4247 #define I2S_RCSR_SR_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 4248 #define I2S_RCSR_SR_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4249 #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
AnnaBridge 171:3a7713b1edbc 4250 #define I2S_RCSR_FR_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 4251 #define I2S_RCSR_FR_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 4252 #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
AnnaBridge 171:3a7713b1edbc 4253 #define I2S_RCSR_BCE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 4254 #define I2S_RCSR_BCE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 4255 #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
AnnaBridge 171:3a7713b1edbc 4256 #define I2S_RCSR_DBGE_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 4257 #define I2S_RCSR_DBGE_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 4258 #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
AnnaBridge 171:3a7713b1edbc 4259 #define I2S_RCSR_STOPE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 4260 #define I2S_RCSR_STOPE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 4261 #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
AnnaBridge 171:3a7713b1edbc 4262 #define I2S_RCSR_RE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 4263 #define I2S_RCSR_RE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 4264 #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
AnnaBridge 171:3a7713b1edbc 4265
AnnaBridge 171:3a7713b1edbc 4266 /*! @name RCR1 - SAI Receive Configuration 1 Register */
AnnaBridge 171:3a7713b1edbc 4267 #define I2S_RCR1_RFW_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 4268 #define I2S_RCR1_RFW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4269 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
AnnaBridge 171:3a7713b1edbc 4270
AnnaBridge 171:3a7713b1edbc 4271 /*! @name RCR2 - SAI Receive Configuration 2 Register */
AnnaBridge 171:3a7713b1edbc 4272 #define I2S_RCR2_DIV_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 4273 #define I2S_RCR2_DIV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4274 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
AnnaBridge 171:3a7713b1edbc 4275 #define I2S_RCR2_BCD_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 4276 #define I2S_RCR2_BCD_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4277 #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
AnnaBridge 171:3a7713b1edbc 4278 #define I2S_RCR2_BCP_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 4279 #define I2S_RCR2_BCP_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 4280 #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
AnnaBridge 171:3a7713b1edbc 4281 #define I2S_RCR2_MSEL_MASK (0xC000000U)
AnnaBridge 171:3a7713b1edbc 4282 #define I2S_RCR2_MSEL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 4283 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
AnnaBridge 171:3a7713b1edbc 4284 #define I2S_RCR2_BCI_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 4285 #define I2S_RCR2_BCI_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 4286 #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
AnnaBridge 171:3a7713b1edbc 4287 #define I2S_RCR2_BCS_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 4288 #define I2S_RCR2_BCS_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 4289 #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
AnnaBridge 171:3a7713b1edbc 4290 #define I2S_RCR2_SYNC_MASK (0xC0000000U)
AnnaBridge 171:3a7713b1edbc 4291 #define I2S_RCR2_SYNC_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 4292 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
AnnaBridge 171:3a7713b1edbc 4293
AnnaBridge 171:3a7713b1edbc 4294 /*! @name RCR3 - SAI Receive Configuration 3 Register */
AnnaBridge 171:3a7713b1edbc 4295 #define I2S_RCR3_WDFL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4296 #define I2S_RCR3_WDFL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4297 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
AnnaBridge 171:3a7713b1edbc 4298 #define I2S_RCR3_RCE_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 4299 #define I2S_RCR3_RCE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4300 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
AnnaBridge 171:3a7713b1edbc 4301
AnnaBridge 171:3a7713b1edbc 4302 /*! @name RCR4 - SAI Receive Configuration 4 Register */
AnnaBridge 171:3a7713b1edbc 4303 #define I2S_RCR4_FSD_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4304 #define I2S_RCR4_FSD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4305 #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
AnnaBridge 171:3a7713b1edbc 4306 #define I2S_RCR4_FSP_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4307 #define I2S_RCR4_FSP_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4308 #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
AnnaBridge 171:3a7713b1edbc 4309 #define I2S_RCR4_FSE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4310 #define I2S_RCR4_FSE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4311 #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
AnnaBridge 171:3a7713b1edbc 4312 #define I2S_RCR4_MF_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4313 #define I2S_RCR4_MF_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4314 #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
AnnaBridge 171:3a7713b1edbc 4315 #define I2S_RCR4_SYWD_MASK (0x1F00U)
AnnaBridge 171:3a7713b1edbc 4316 #define I2S_RCR4_SYWD_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4317 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
AnnaBridge 171:3a7713b1edbc 4318 #define I2S_RCR4_FRSZ_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 4319 #define I2S_RCR4_FRSZ_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4320 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
AnnaBridge 171:3a7713b1edbc 4321
AnnaBridge 171:3a7713b1edbc 4322 /*! @name RCR5 - SAI Receive Configuration 5 Register */
AnnaBridge 171:3a7713b1edbc 4323 #define I2S_RCR5_FBT_MASK (0x1F00U)
AnnaBridge 171:3a7713b1edbc 4324 #define I2S_RCR5_FBT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4325 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
AnnaBridge 171:3a7713b1edbc 4326 #define I2S_RCR5_W0W_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 4327 #define I2S_RCR5_W0W_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4328 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
AnnaBridge 171:3a7713b1edbc 4329 #define I2S_RCR5_WNW_MASK (0x1F000000U)
AnnaBridge 171:3a7713b1edbc 4330 #define I2S_RCR5_WNW_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4331 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
AnnaBridge 171:3a7713b1edbc 4332
AnnaBridge 171:3a7713b1edbc 4333 /*! @name RDR - SAI Receive Data Register */
AnnaBridge 171:3a7713b1edbc 4334 #define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4335 #define I2S_RDR_RDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4336 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
AnnaBridge 171:3a7713b1edbc 4337
AnnaBridge 171:3a7713b1edbc 4338 /* The count of I2S_RDR */
AnnaBridge 171:3a7713b1edbc 4339 #define I2S_RDR_COUNT (1U)
AnnaBridge 171:3a7713b1edbc 4340
AnnaBridge 171:3a7713b1edbc 4341 /*! @name RFR - SAI Receive FIFO Register */
AnnaBridge 171:3a7713b1edbc 4342 #define I2S_RFR_RFP_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4343 #define I2S_RFR_RFP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4344 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
AnnaBridge 171:3a7713b1edbc 4345 #define I2S_RFR_WFP_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 4346 #define I2S_RFR_WFP_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4347 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
AnnaBridge 171:3a7713b1edbc 4348
AnnaBridge 171:3a7713b1edbc 4349 /* The count of I2S_RFR */
AnnaBridge 171:3a7713b1edbc 4350 #define I2S_RFR_COUNT (1U)
AnnaBridge 171:3a7713b1edbc 4351
AnnaBridge 171:3a7713b1edbc 4352 /*! @name RMR - SAI Receive Mask Register */
AnnaBridge 171:3a7713b1edbc 4353 #define I2S_RMR_RWM_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 4354 #define I2S_RMR_RWM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4355 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
AnnaBridge 171:3a7713b1edbc 4356
AnnaBridge 171:3a7713b1edbc 4357 /*! @name MCR - SAI MCLK Control Register */
AnnaBridge 171:3a7713b1edbc 4358 #define I2S_MCR_MICS_MASK (0x3000000U)
AnnaBridge 171:3a7713b1edbc 4359 #define I2S_MCR_MICS_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4360 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
AnnaBridge 171:3a7713b1edbc 4361 #define I2S_MCR_MOE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 4362 #define I2S_MCR_MOE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 4363 #define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
AnnaBridge 171:3a7713b1edbc 4364 #define I2S_MCR_DUF_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 4365 #define I2S_MCR_DUF_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 4366 #define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
AnnaBridge 171:3a7713b1edbc 4367
AnnaBridge 171:3a7713b1edbc 4368 /*! @name MDR - SAI MCLK Divide Register */
AnnaBridge 171:3a7713b1edbc 4369 #define I2S_MDR_DIVIDE_MASK (0xFFFU)
AnnaBridge 171:3a7713b1edbc 4370 #define I2S_MDR_DIVIDE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4371 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
AnnaBridge 171:3a7713b1edbc 4372 #define I2S_MDR_FRACT_MASK (0xFF000U)
AnnaBridge 171:3a7713b1edbc 4373 #define I2S_MDR_FRACT_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 4374 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
AnnaBridge 171:3a7713b1edbc 4375
AnnaBridge 171:3a7713b1edbc 4376
AnnaBridge 171:3a7713b1edbc 4377 /*!
AnnaBridge 171:3a7713b1edbc 4378 * @}
AnnaBridge 171:3a7713b1edbc 4379 */ /* end of group I2S_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4380
AnnaBridge 171:3a7713b1edbc 4381
AnnaBridge 171:3a7713b1edbc 4382 /* I2S - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4383 /** Peripheral I2S0 base address */
AnnaBridge 171:3a7713b1edbc 4384 #define I2S0_BASE (0x4002F000u)
AnnaBridge 171:3a7713b1edbc 4385 /** Peripheral I2S0 base pointer */
AnnaBridge 171:3a7713b1edbc 4386 #define I2S0 ((I2S_Type *)I2S0_BASE)
AnnaBridge 171:3a7713b1edbc 4387 /** Array initializer of I2S peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 4388 #define I2S_BASE_ADDRS { I2S0_BASE }
AnnaBridge 171:3a7713b1edbc 4389 /** Array initializer of I2S peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4390 #define I2S_BASE_PTRS { I2S0 }
AnnaBridge 171:3a7713b1edbc 4391 /** Interrupt vectors for the I2S peripheral type */
AnnaBridge 171:3a7713b1edbc 4392 #define I2S_RX_IRQS { I2S0_Rx_IRQn }
AnnaBridge 171:3a7713b1edbc 4393 #define I2S_TX_IRQS { I2S0_Tx_IRQn }
AnnaBridge 171:3a7713b1edbc 4394
AnnaBridge 171:3a7713b1edbc 4395 /*!
AnnaBridge 171:3a7713b1edbc 4396 * @}
AnnaBridge 171:3a7713b1edbc 4397 */ /* end of group I2S_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4398
AnnaBridge 171:3a7713b1edbc 4399
AnnaBridge 171:3a7713b1edbc 4400 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4401 -- LLWU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4402 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4403
AnnaBridge 171:3a7713b1edbc 4404 /*!
AnnaBridge 171:3a7713b1edbc 4405 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4406 * @{
AnnaBridge 171:3a7713b1edbc 4407 */
AnnaBridge 171:3a7713b1edbc 4408
AnnaBridge 171:3a7713b1edbc 4409 /** LLWU - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4410 typedef struct {
AnnaBridge 171:3a7713b1edbc 4411 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 4412 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 4413 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 4414 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 4415 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 4416 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 4417 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 4418 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 4419 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 4420 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 4421 __IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 4422 } LLWU_Type;
AnnaBridge 171:3a7713b1edbc 4423
AnnaBridge 171:3a7713b1edbc 4424 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4425 -- LLWU Register Masks
AnnaBridge 171:3a7713b1edbc 4426 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4427
AnnaBridge 171:3a7713b1edbc 4428 /*!
AnnaBridge 171:3a7713b1edbc 4429 * @addtogroup LLWU_Register_Masks LLWU Register Masks
AnnaBridge 171:3a7713b1edbc 4430 * @{
AnnaBridge 171:3a7713b1edbc 4431 */
AnnaBridge 171:3a7713b1edbc 4432
AnnaBridge 171:3a7713b1edbc 4433 /*! @name PE1 - LLWU Pin Enable 1 register */
AnnaBridge 171:3a7713b1edbc 4434 #define LLWU_PE1_WUPE0_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 4435 #define LLWU_PE1_WUPE0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4436 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
AnnaBridge 171:3a7713b1edbc 4437 #define LLWU_PE1_WUPE1_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 4438 #define LLWU_PE1_WUPE1_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4439 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
AnnaBridge 171:3a7713b1edbc 4440 #define LLWU_PE1_WUPE2_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4441 #define LLWU_PE1_WUPE2_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4442 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
AnnaBridge 171:3a7713b1edbc 4443 #define LLWU_PE1_WUPE3_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 4444 #define LLWU_PE1_WUPE3_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4445 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
AnnaBridge 171:3a7713b1edbc 4446
AnnaBridge 171:3a7713b1edbc 4447 /*! @name PE2 - LLWU Pin Enable 2 register */
AnnaBridge 171:3a7713b1edbc 4448 #define LLWU_PE2_WUPE4_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 4449 #define LLWU_PE2_WUPE4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4450 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
AnnaBridge 171:3a7713b1edbc 4451 #define LLWU_PE2_WUPE5_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 4452 #define LLWU_PE2_WUPE5_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4453 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
AnnaBridge 171:3a7713b1edbc 4454 #define LLWU_PE2_WUPE6_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4455 #define LLWU_PE2_WUPE6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4456 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
AnnaBridge 171:3a7713b1edbc 4457 #define LLWU_PE2_WUPE7_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 4458 #define LLWU_PE2_WUPE7_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4459 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
AnnaBridge 171:3a7713b1edbc 4460
AnnaBridge 171:3a7713b1edbc 4461 /*! @name PE3 - LLWU Pin Enable 3 register */
AnnaBridge 171:3a7713b1edbc 4462 #define LLWU_PE3_WUPE8_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 4463 #define LLWU_PE3_WUPE8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4464 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
AnnaBridge 171:3a7713b1edbc 4465 #define LLWU_PE3_WUPE9_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 4466 #define LLWU_PE3_WUPE9_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4467 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
AnnaBridge 171:3a7713b1edbc 4468 #define LLWU_PE3_WUPE10_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4469 #define LLWU_PE3_WUPE10_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4470 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
AnnaBridge 171:3a7713b1edbc 4471 #define LLWU_PE3_WUPE11_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 4472 #define LLWU_PE3_WUPE11_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4473 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
AnnaBridge 171:3a7713b1edbc 4474
AnnaBridge 171:3a7713b1edbc 4475 /*! @name PE4 - LLWU Pin Enable 4 register */
AnnaBridge 171:3a7713b1edbc 4476 #define LLWU_PE4_WUPE12_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 4477 #define LLWU_PE4_WUPE12_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4478 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
AnnaBridge 171:3a7713b1edbc 4479 #define LLWU_PE4_WUPE13_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 4480 #define LLWU_PE4_WUPE13_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4481 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
AnnaBridge 171:3a7713b1edbc 4482 #define LLWU_PE4_WUPE14_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4483 #define LLWU_PE4_WUPE14_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4484 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
AnnaBridge 171:3a7713b1edbc 4485 #define LLWU_PE4_WUPE15_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 4486 #define LLWU_PE4_WUPE15_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4487 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
AnnaBridge 171:3a7713b1edbc 4488
AnnaBridge 171:3a7713b1edbc 4489 /*! @name ME - LLWU Module Enable register */
AnnaBridge 171:3a7713b1edbc 4490 #define LLWU_ME_WUME0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4491 #define LLWU_ME_WUME0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4492 #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
AnnaBridge 171:3a7713b1edbc 4493 #define LLWU_ME_WUME1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4494 #define LLWU_ME_WUME1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4495 #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
AnnaBridge 171:3a7713b1edbc 4496 #define LLWU_ME_WUME2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4497 #define LLWU_ME_WUME2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4498 #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
AnnaBridge 171:3a7713b1edbc 4499 #define LLWU_ME_WUME3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4500 #define LLWU_ME_WUME3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4501 #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
AnnaBridge 171:3a7713b1edbc 4502 #define LLWU_ME_WUME4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4503 #define LLWU_ME_WUME4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4504 #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
AnnaBridge 171:3a7713b1edbc 4505 #define LLWU_ME_WUME5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4506 #define LLWU_ME_WUME5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4507 #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
AnnaBridge 171:3a7713b1edbc 4508 #define LLWU_ME_WUME6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4509 #define LLWU_ME_WUME6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4510 #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
AnnaBridge 171:3a7713b1edbc 4511 #define LLWU_ME_WUME7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4512 #define LLWU_ME_WUME7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4513 #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
AnnaBridge 171:3a7713b1edbc 4514
AnnaBridge 171:3a7713b1edbc 4515 /*! @name F1 - LLWU Flag 1 register */
AnnaBridge 171:3a7713b1edbc 4516 #define LLWU_F1_WUF0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4517 #define LLWU_F1_WUF0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4518 #define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
AnnaBridge 171:3a7713b1edbc 4519 #define LLWU_F1_WUF1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4520 #define LLWU_F1_WUF1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4521 #define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
AnnaBridge 171:3a7713b1edbc 4522 #define LLWU_F1_WUF2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4523 #define LLWU_F1_WUF2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4524 #define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
AnnaBridge 171:3a7713b1edbc 4525 #define LLWU_F1_WUF3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4526 #define LLWU_F1_WUF3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4527 #define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
AnnaBridge 171:3a7713b1edbc 4528 #define LLWU_F1_WUF4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4529 #define LLWU_F1_WUF4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4530 #define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
AnnaBridge 171:3a7713b1edbc 4531 #define LLWU_F1_WUF5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4532 #define LLWU_F1_WUF5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4533 #define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
AnnaBridge 171:3a7713b1edbc 4534 #define LLWU_F1_WUF6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4535 #define LLWU_F1_WUF6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4536 #define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
AnnaBridge 171:3a7713b1edbc 4537 #define LLWU_F1_WUF7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4538 #define LLWU_F1_WUF7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4539 #define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
AnnaBridge 171:3a7713b1edbc 4540
AnnaBridge 171:3a7713b1edbc 4541 /*! @name F2 - LLWU Flag 2 register */
AnnaBridge 171:3a7713b1edbc 4542 #define LLWU_F2_WUF8_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4543 #define LLWU_F2_WUF8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4544 #define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
AnnaBridge 171:3a7713b1edbc 4545 #define LLWU_F2_WUF9_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4546 #define LLWU_F2_WUF9_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4547 #define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
AnnaBridge 171:3a7713b1edbc 4548 #define LLWU_F2_WUF10_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4549 #define LLWU_F2_WUF10_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4550 #define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
AnnaBridge 171:3a7713b1edbc 4551 #define LLWU_F2_WUF11_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4552 #define LLWU_F2_WUF11_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4553 #define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
AnnaBridge 171:3a7713b1edbc 4554 #define LLWU_F2_WUF12_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4555 #define LLWU_F2_WUF12_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4556 #define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
AnnaBridge 171:3a7713b1edbc 4557 #define LLWU_F2_WUF13_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4558 #define LLWU_F2_WUF13_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4559 #define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
AnnaBridge 171:3a7713b1edbc 4560 #define LLWU_F2_WUF14_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4561 #define LLWU_F2_WUF14_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4562 #define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
AnnaBridge 171:3a7713b1edbc 4563 #define LLWU_F2_WUF15_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4564 #define LLWU_F2_WUF15_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4565 #define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
AnnaBridge 171:3a7713b1edbc 4566
AnnaBridge 171:3a7713b1edbc 4567 /*! @name F3 - LLWU Flag 3 register */
AnnaBridge 171:3a7713b1edbc 4568 #define LLWU_F3_MWUF0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4569 #define LLWU_F3_MWUF0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4570 #define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
AnnaBridge 171:3a7713b1edbc 4571 #define LLWU_F3_MWUF1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4572 #define LLWU_F3_MWUF1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4573 #define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
AnnaBridge 171:3a7713b1edbc 4574 #define LLWU_F3_MWUF2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4575 #define LLWU_F3_MWUF2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4576 #define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
AnnaBridge 171:3a7713b1edbc 4577 #define LLWU_F3_MWUF3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4578 #define LLWU_F3_MWUF3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4579 #define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
AnnaBridge 171:3a7713b1edbc 4580 #define LLWU_F3_MWUF4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4581 #define LLWU_F3_MWUF4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4582 #define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
AnnaBridge 171:3a7713b1edbc 4583 #define LLWU_F3_MWUF5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4584 #define LLWU_F3_MWUF5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4585 #define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
AnnaBridge 171:3a7713b1edbc 4586 #define LLWU_F3_MWUF6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4587 #define LLWU_F3_MWUF6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4588 #define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
AnnaBridge 171:3a7713b1edbc 4589 #define LLWU_F3_MWUF7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4590 #define LLWU_F3_MWUF7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4591 #define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
AnnaBridge 171:3a7713b1edbc 4592
AnnaBridge 171:3a7713b1edbc 4593 /*! @name FILT1 - LLWU Pin Filter 1 register */
AnnaBridge 171:3a7713b1edbc 4594 #define LLWU_FILT1_FILTSEL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4595 #define LLWU_FILT1_FILTSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4596 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 4597 #define LLWU_FILT1_FILTE_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 4598 #define LLWU_FILT1_FILTE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4599 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
AnnaBridge 171:3a7713b1edbc 4600 #define LLWU_FILT1_FILTF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4601 #define LLWU_FILT1_FILTF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4602 #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
AnnaBridge 171:3a7713b1edbc 4603
AnnaBridge 171:3a7713b1edbc 4604 /*! @name FILT2 - LLWU Pin Filter 2 register */
AnnaBridge 171:3a7713b1edbc 4605 #define LLWU_FILT2_FILTSEL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4606 #define LLWU_FILT2_FILTSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4607 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 4608 #define LLWU_FILT2_FILTE_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 4609 #define LLWU_FILT2_FILTE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4610 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
AnnaBridge 171:3a7713b1edbc 4611 #define LLWU_FILT2_FILTF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4612 #define LLWU_FILT2_FILTF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4613 #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
AnnaBridge 171:3a7713b1edbc 4614
AnnaBridge 171:3a7713b1edbc 4615 /*! @name RST - LLWU Reset Enable register */
AnnaBridge 171:3a7713b1edbc 4616 #define LLWU_RST_RSTFILT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4617 #define LLWU_RST_RSTFILT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4618 #define LLWU_RST_RSTFILT(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_RSTFILT_SHIFT)) & LLWU_RST_RSTFILT_MASK)
AnnaBridge 171:3a7713b1edbc 4619 #define LLWU_RST_LLRSTE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4620 #define LLWU_RST_LLRSTE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4621 #define LLWU_RST_LLRSTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_LLRSTE_SHIFT)) & LLWU_RST_LLRSTE_MASK)
AnnaBridge 171:3a7713b1edbc 4622
AnnaBridge 171:3a7713b1edbc 4623
AnnaBridge 171:3a7713b1edbc 4624 /*!
AnnaBridge 171:3a7713b1edbc 4625 * @}
AnnaBridge 171:3a7713b1edbc 4626 */ /* end of group LLWU_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4627
AnnaBridge 171:3a7713b1edbc 4628
AnnaBridge 171:3a7713b1edbc 4629 /* LLWU - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4630 /** Peripheral LLWU base address */
AnnaBridge 171:3a7713b1edbc 4631 #define LLWU_BASE (0x4007C000u)
AnnaBridge 171:3a7713b1edbc 4632 /** Peripheral LLWU base pointer */
AnnaBridge 171:3a7713b1edbc 4633 #define LLWU ((LLWU_Type *)LLWU_BASE)
AnnaBridge 171:3a7713b1edbc 4634 /** Array initializer of LLWU peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 4635 #define LLWU_BASE_ADDRS { LLWU_BASE }
AnnaBridge 171:3a7713b1edbc 4636 /** Array initializer of LLWU peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4637 #define LLWU_BASE_PTRS { LLWU }
AnnaBridge 171:3a7713b1edbc 4638 /** Interrupt vectors for the LLWU peripheral type */
AnnaBridge 171:3a7713b1edbc 4639 #define LLWU_IRQS { LLWU_IRQn }
AnnaBridge 171:3a7713b1edbc 4640
AnnaBridge 171:3a7713b1edbc 4641 /*!
AnnaBridge 171:3a7713b1edbc 4642 * @}
AnnaBridge 171:3a7713b1edbc 4643 */ /* end of group LLWU_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4644
AnnaBridge 171:3a7713b1edbc 4645
AnnaBridge 171:3a7713b1edbc 4646 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4647 -- LPTMR Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4648 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4649
AnnaBridge 171:3a7713b1edbc 4650 /*!
AnnaBridge 171:3a7713b1edbc 4651 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4652 * @{
AnnaBridge 171:3a7713b1edbc 4653 */
AnnaBridge 171:3a7713b1edbc 4654
AnnaBridge 171:3a7713b1edbc 4655 /** LPTMR - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4656 typedef struct {
AnnaBridge 171:3a7713b1edbc 4657 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 4658 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 4659 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 4660 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 4661 } LPTMR_Type;
AnnaBridge 171:3a7713b1edbc 4662
AnnaBridge 171:3a7713b1edbc 4663 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4664 -- LPTMR Register Masks
AnnaBridge 171:3a7713b1edbc 4665 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4666
AnnaBridge 171:3a7713b1edbc 4667 /*!
AnnaBridge 171:3a7713b1edbc 4668 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
AnnaBridge 171:3a7713b1edbc 4669 * @{
AnnaBridge 171:3a7713b1edbc 4670 */
AnnaBridge 171:3a7713b1edbc 4671
AnnaBridge 171:3a7713b1edbc 4672 /*! @name CSR - Low Power Timer Control Status Register */
AnnaBridge 171:3a7713b1edbc 4673 #define LPTMR_CSR_TEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4674 #define LPTMR_CSR_TEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4675 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
AnnaBridge 171:3a7713b1edbc 4676 #define LPTMR_CSR_TMS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4677 #define LPTMR_CSR_TMS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4678 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
AnnaBridge 171:3a7713b1edbc 4679 #define LPTMR_CSR_TFC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4680 #define LPTMR_CSR_TFC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4681 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
AnnaBridge 171:3a7713b1edbc 4682 #define LPTMR_CSR_TPP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4683 #define LPTMR_CSR_TPP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4684 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
AnnaBridge 171:3a7713b1edbc 4685 #define LPTMR_CSR_TPS_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4686 #define LPTMR_CSR_TPS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4687 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
AnnaBridge 171:3a7713b1edbc 4688 #define LPTMR_CSR_TIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4689 #define LPTMR_CSR_TIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4690 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
AnnaBridge 171:3a7713b1edbc 4691 #define LPTMR_CSR_TCF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4692 #define LPTMR_CSR_TCF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4693 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
AnnaBridge 171:3a7713b1edbc 4694
AnnaBridge 171:3a7713b1edbc 4695 /*! @name PSR - Low Power Timer Prescale Register */
AnnaBridge 171:3a7713b1edbc 4696 #define LPTMR_PSR_PCS_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 4697 #define LPTMR_PSR_PCS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4698 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
AnnaBridge 171:3a7713b1edbc 4699 #define LPTMR_PSR_PBYP_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4700 #define LPTMR_PSR_PBYP_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4701 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
AnnaBridge 171:3a7713b1edbc 4702 #define LPTMR_PSR_PRESCALE_MASK (0x78U)
AnnaBridge 171:3a7713b1edbc 4703 #define LPTMR_PSR_PRESCALE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4704 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
AnnaBridge 171:3a7713b1edbc 4705
AnnaBridge 171:3a7713b1edbc 4706 /*! @name CMR - Low Power Timer Compare Register */
AnnaBridge 171:3a7713b1edbc 4707 #define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 4708 #define LPTMR_CMR_COMPARE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4709 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
AnnaBridge 171:3a7713b1edbc 4710
AnnaBridge 171:3a7713b1edbc 4711 /*! @name CNR - Low Power Timer Counter Register */
AnnaBridge 171:3a7713b1edbc 4712 #define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 4713 #define LPTMR_CNR_COUNTER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4714 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
AnnaBridge 171:3a7713b1edbc 4715
AnnaBridge 171:3a7713b1edbc 4716
AnnaBridge 171:3a7713b1edbc 4717 /*!
AnnaBridge 171:3a7713b1edbc 4718 * @}
AnnaBridge 171:3a7713b1edbc 4719 */ /* end of group LPTMR_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4720
AnnaBridge 171:3a7713b1edbc 4721
AnnaBridge 171:3a7713b1edbc 4722 /* LPTMR - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4723 /** Peripheral LPTMR0 base address */
AnnaBridge 171:3a7713b1edbc 4724 #define LPTMR0_BASE (0x40040000u)
AnnaBridge 171:3a7713b1edbc 4725 /** Peripheral LPTMR0 base pointer */
AnnaBridge 171:3a7713b1edbc 4726 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
AnnaBridge 171:3a7713b1edbc 4727 /** Array initializer of LPTMR peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 4728 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
AnnaBridge 171:3a7713b1edbc 4729 /** Array initializer of LPTMR peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4730 #define LPTMR_BASE_PTRS { LPTMR0 }
AnnaBridge 171:3a7713b1edbc 4731 /** Interrupt vectors for the LPTMR peripheral type */
AnnaBridge 171:3a7713b1edbc 4732 #define LPTMR_IRQS { LPTMR0_IRQn }
AnnaBridge 171:3a7713b1edbc 4733
AnnaBridge 171:3a7713b1edbc 4734 /*!
AnnaBridge 171:3a7713b1edbc 4735 * @}
AnnaBridge 171:3a7713b1edbc 4736 */ /* end of group LPTMR_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4737
AnnaBridge 171:3a7713b1edbc 4738
AnnaBridge 171:3a7713b1edbc 4739 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4740 -- MCG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4741 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4742
AnnaBridge 171:3a7713b1edbc 4743 /*!
AnnaBridge 171:3a7713b1edbc 4744 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4745 * @{
AnnaBridge 171:3a7713b1edbc 4746 */
AnnaBridge 171:3a7713b1edbc 4747
AnnaBridge 171:3a7713b1edbc 4748 /** MCG - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4749 typedef struct {
AnnaBridge 171:3a7713b1edbc 4750 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 4751 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 4752 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 4753 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 4754 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 4755 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 4756 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 4757 uint8_t RESERVED_0[1];
AnnaBridge 171:3a7713b1edbc 4758 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 4759 uint8_t RESERVED_1[1];
AnnaBridge 171:3a7713b1edbc 4760 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 4761 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 4762 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 4763 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 4764 __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
AnnaBridge 171:3a7713b1edbc 4765 __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
AnnaBridge 171:3a7713b1edbc 4766 } MCG_Type;
AnnaBridge 171:3a7713b1edbc 4767
AnnaBridge 171:3a7713b1edbc 4768 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4769 -- MCG Register Masks
AnnaBridge 171:3a7713b1edbc 4770 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4771
AnnaBridge 171:3a7713b1edbc 4772 /*!
AnnaBridge 171:3a7713b1edbc 4773 * @addtogroup MCG_Register_Masks MCG Register Masks
AnnaBridge 171:3a7713b1edbc 4774 * @{
AnnaBridge 171:3a7713b1edbc 4775 */
AnnaBridge 171:3a7713b1edbc 4776
AnnaBridge 171:3a7713b1edbc 4777 /*! @name C1 - MCG Control 1 Register */
AnnaBridge 171:3a7713b1edbc 4778 #define MCG_C1_IREFSTEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4779 #define MCG_C1_IREFSTEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4780 #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
AnnaBridge 171:3a7713b1edbc 4781 #define MCG_C1_IRCLKEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4782 #define MCG_C1_IRCLKEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4783 #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
AnnaBridge 171:3a7713b1edbc 4784 #define MCG_C1_IREFS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4785 #define MCG_C1_IREFS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4786 #define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
AnnaBridge 171:3a7713b1edbc 4787 #define MCG_C1_FRDIV_MASK (0x38U)
AnnaBridge 171:3a7713b1edbc 4788 #define MCG_C1_FRDIV_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4789 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
AnnaBridge 171:3a7713b1edbc 4790 #define MCG_C1_CLKS_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 4791 #define MCG_C1_CLKS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4792 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
AnnaBridge 171:3a7713b1edbc 4793
AnnaBridge 171:3a7713b1edbc 4794 /*! @name C2 - MCG Control 2 Register */
AnnaBridge 171:3a7713b1edbc 4795 #define MCG_C2_IRCS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4796 #define MCG_C2_IRCS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4797 #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
AnnaBridge 171:3a7713b1edbc 4798 #define MCG_C2_LP_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4799 #define MCG_C2_LP_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4800 #define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
AnnaBridge 171:3a7713b1edbc 4801 #define MCG_C2_EREFS0_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4802 #define MCG_C2_EREFS0_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4803 #define MCG_C2_EREFS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK)
AnnaBridge 171:3a7713b1edbc 4804 #define MCG_C2_HGO0_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4805 #define MCG_C2_HGO0_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4806 #define MCG_C2_HGO0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK)
AnnaBridge 171:3a7713b1edbc 4807 #define MCG_C2_RANGE0_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4808 #define MCG_C2_RANGE0_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4809 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK)
AnnaBridge 171:3a7713b1edbc 4810 #define MCG_C2_LOCRE0_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4811 #define MCG_C2_LOCRE0_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4812 #define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
AnnaBridge 171:3a7713b1edbc 4813
AnnaBridge 171:3a7713b1edbc 4814 /*! @name C3 - MCG Control 3 Register */
AnnaBridge 171:3a7713b1edbc 4815 #define MCG_C3_SCTRIM_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 4816 #define MCG_C3_SCTRIM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4817 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
AnnaBridge 171:3a7713b1edbc 4818
AnnaBridge 171:3a7713b1edbc 4819 /*! @name C4 - MCG Control 4 Register */
AnnaBridge 171:3a7713b1edbc 4820 #define MCG_C4_SCFTRIM_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4821 #define MCG_C4_SCFTRIM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4822 #define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
AnnaBridge 171:3a7713b1edbc 4823 #define MCG_C4_FCTRIM_MASK (0x1EU)
AnnaBridge 171:3a7713b1edbc 4824 #define MCG_C4_FCTRIM_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4825 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
AnnaBridge 171:3a7713b1edbc 4826 #define MCG_C4_DRST_DRS_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 4827 #define MCG_C4_DRST_DRS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4828 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
AnnaBridge 171:3a7713b1edbc 4829 #define MCG_C4_DMX32_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4830 #define MCG_C4_DMX32_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4831 #define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
AnnaBridge 171:3a7713b1edbc 4832
AnnaBridge 171:3a7713b1edbc 4833 /*! @name C5 - MCG Control 5 Register */
AnnaBridge 171:3a7713b1edbc 4834 #define MCG_C5_PRDIV0_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 4835 #define MCG_C5_PRDIV0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4836 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
AnnaBridge 171:3a7713b1edbc 4837 #define MCG_C5_PLLSTEN0_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4838 #define MCG_C5_PLLSTEN0_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4839 #define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
AnnaBridge 171:3a7713b1edbc 4840 #define MCG_C5_PLLCLKEN0_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4841 #define MCG_C5_PLLCLKEN0_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4842 #define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
AnnaBridge 171:3a7713b1edbc 4843
AnnaBridge 171:3a7713b1edbc 4844 /*! @name C6 - MCG Control 6 Register */
AnnaBridge 171:3a7713b1edbc 4845 #define MCG_C6_VDIV0_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 4846 #define MCG_C6_VDIV0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4847 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
AnnaBridge 171:3a7713b1edbc 4848 #define MCG_C6_CME0_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4849 #define MCG_C6_CME0_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4850 #define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
AnnaBridge 171:3a7713b1edbc 4851 #define MCG_C6_PLLS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4852 #define MCG_C6_PLLS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4853 #define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
AnnaBridge 171:3a7713b1edbc 4854 #define MCG_C6_LOLIE0_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4855 #define MCG_C6_LOLIE0_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4856 #define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
AnnaBridge 171:3a7713b1edbc 4857
AnnaBridge 171:3a7713b1edbc 4858 /*! @name S - MCG Status Register */
AnnaBridge 171:3a7713b1edbc 4859 #define MCG_S_IRCST_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4860 #define MCG_S_IRCST_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4861 #define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
AnnaBridge 171:3a7713b1edbc 4862 #define MCG_S_OSCINIT0_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4863 #define MCG_S_OSCINIT0_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4864 #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
AnnaBridge 171:3a7713b1edbc 4865 #define MCG_S_CLKST_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 4866 #define MCG_S_CLKST_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4867 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
AnnaBridge 171:3a7713b1edbc 4868 #define MCG_S_IREFST_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4869 #define MCG_S_IREFST_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4870 #define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
AnnaBridge 171:3a7713b1edbc 4871 #define MCG_S_PLLST_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4872 #define MCG_S_PLLST_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4873 #define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
AnnaBridge 171:3a7713b1edbc 4874 #define MCG_S_LOCK0_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4875 #define MCG_S_LOCK0_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4876 #define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
AnnaBridge 171:3a7713b1edbc 4877 #define MCG_S_LOLS0_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4878 #define MCG_S_LOLS0_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4879 #define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
AnnaBridge 171:3a7713b1edbc 4880
AnnaBridge 171:3a7713b1edbc 4881 /*! @name SC - MCG Status and Control Register */
AnnaBridge 171:3a7713b1edbc 4882 #define MCG_SC_LOCS0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4883 #define MCG_SC_LOCS0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4884 #define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
AnnaBridge 171:3a7713b1edbc 4885 #define MCG_SC_FCRDIV_MASK (0xEU)
AnnaBridge 171:3a7713b1edbc 4886 #define MCG_SC_FCRDIV_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4887 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
AnnaBridge 171:3a7713b1edbc 4888 #define MCG_SC_FLTPRSRV_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4889 #define MCG_SC_FLTPRSRV_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4890 #define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
AnnaBridge 171:3a7713b1edbc 4891 #define MCG_SC_ATMF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4892 #define MCG_SC_ATMF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4893 #define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
AnnaBridge 171:3a7713b1edbc 4894 #define MCG_SC_ATMS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4895 #define MCG_SC_ATMS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4896 #define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
AnnaBridge 171:3a7713b1edbc 4897 #define MCG_SC_ATME_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4898 #define MCG_SC_ATME_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4899 #define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
AnnaBridge 171:3a7713b1edbc 4900
AnnaBridge 171:3a7713b1edbc 4901 /*! @name ATCVH - MCG Auto Trim Compare Value High Register */
AnnaBridge 171:3a7713b1edbc 4902 #define MCG_ATCVH_ATCVH_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 4903 #define MCG_ATCVH_ATCVH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4904 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
AnnaBridge 171:3a7713b1edbc 4905
AnnaBridge 171:3a7713b1edbc 4906 /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
AnnaBridge 171:3a7713b1edbc 4907 #define MCG_ATCVL_ATCVL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 4908 #define MCG_ATCVL_ATCVL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4909 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
AnnaBridge 171:3a7713b1edbc 4910
AnnaBridge 171:3a7713b1edbc 4911 /*! @name C7 - MCG Control 7 Register */
AnnaBridge 171:3a7713b1edbc 4912 #define MCG_C7_OSCSEL_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4913 #define MCG_C7_OSCSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4914 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
AnnaBridge 171:3a7713b1edbc 4915
AnnaBridge 171:3a7713b1edbc 4916 /*! @name C8 - MCG Control 8 Register */
AnnaBridge 171:3a7713b1edbc 4917 #define MCG_C8_LOCS1_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4918 #define MCG_C8_LOCS1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4919 #define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
AnnaBridge 171:3a7713b1edbc 4920 #define MCG_C8_CME1_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4921 #define MCG_C8_CME1_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4922 #define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
AnnaBridge 171:3a7713b1edbc 4923 #define MCG_C8_LOLRE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4924 #define MCG_C8_LOLRE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4925 #define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
AnnaBridge 171:3a7713b1edbc 4926 #define MCG_C8_LOCRE1_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4927 #define MCG_C8_LOCRE1_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4928 #define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
AnnaBridge 171:3a7713b1edbc 4929
AnnaBridge 171:3a7713b1edbc 4930
AnnaBridge 171:3a7713b1edbc 4931 /*!
AnnaBridge 171:3a7713b1edbc 4932 * @}
AnnaBridge 171:3a7713b1edbc 4933 */ /* end of group MCG_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4934
AnnaBridge 171:3a7713b1edbc 4935
AnnaBridge 171:3a7713b1edbc 4936 /* MCG - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4937 /** Peripheral MCG base address */
AnnaBridge 171:3a7713b1edbc 4938 #define MCG_BASE (0x40064000u)
AnnaBridge 171:3a7713b1edbc 4939 /** Peripheral MCG base pointer */
AnnaBridge 171:3a7713b1edbc 4940 #define MCG ((MCG_Type *)MCG_BASE)
AnnaBridge 171:3a7713b1edbc 4941 /** Array initializer of MCG peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 4942 #define MCG_BASE_ADDRS { MCG_BASE }
AnnaBridge 171:3a7713b1edbc 4943 /** Array initializer of MCG peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4944 #define MCG_BASE_PTRS { MCG }
AnnaBridge 171:3a7713b1edbc 4945 /** Interrupt vectors for the MCG peripheral type */
AnnaBridge 171:3a7713b1edbc 4946 #define MCG_IRQS { MCG_IRQn }
AnnaBridge 171:3a7713b1edbc 4947 /* MCG C2[EREFS] backward compatibility */
AnnaBridge 171:3a7713b1edbc 4948 #define MCG_C2_EREFS_MASK (MCG_C2_EREFS0_MASK)
AnnaBridge 171:3a7713b1edbc 4949 #define MCG_C2_EREFS_SHIFT (MCG_C2_EREFS0_SHIFT)
AnnaBridge 171:3a7713b1edbc 4950 #define MCG_C2_EREFS_WIDTH (MCG_C2_EREFS0_WIDTH)
AnnaBridge 171:3a7713b1edbc 4951 #define MCG_C2_EREFS(x) (MCG_C2_EREFS0(x))
AnnaBridge 171:3a7713b1edbc 4952
AnnaBridge 171:3a7713b1edbc 4953 /* MCG C2[HGO] backward compatibility */
AnnaBridge 171:3a7713b1edbc 4954 #define MCG_C2_HGO_MASK (MCG_C2_HGO0_MASK)
AnnaBridge 171:3a7713b1edbc 4955 #define MCG_C2_HGO_SHIFT (MCG_C2_HGO0_SHIFT)
AnnaBridge 171:3a7713b1edbc 4956 #define MCG_C2_HGO_WIDTH (MCG_C2_HGO0_WIDTH)
AnnaBridge 171:3a7713b1edbc 4957 #define MCG_C2_HGO(x) (MCG_C2_HGO0(x))
AnnaBridge 171:3a7713b1edbc 4958
AnnaBridge 171:3a7713b1edbc 4959 /* MCG C2[RANGE] backward compatibility */
AnnaBridge 171:3a7713b1edbc 4960 #define MCG_C2_RANGE_MASK (MCG_C2_RANGE0_MASK)
AnnaBridge 171:3a7713b1edbc 4961 #define MCG_C2_RANGE_SHIFT (MCG_C2_RANGE0_SHIFT)
AnnaBridge 171:3a7713b1edbc 4962 #define MCG_C2_RANGE_WIDTH (MCG_C2_RANGE0_WIDTH)
AnnaBridge 171:3a7713b1edbc 4963 #define MCG_C2_RANGE(x) (MCG_C2_RANGE0(x))
AnnaBridge 171:3a7713b1edbc 4964
AnnaBridge 171:3a7713b1edbc 4965
AnnaBridge 171:3a7713b1edbc 4966 /*!
AnnaBridge 171:3a7713b1edbc 4967 * @}
AnnaBridge 171:3a7713b1edbc 4968 */ /* end of group MCG_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4969
AnnaBridge 171:3a7713b1edbc 4970
AnnaBridge 171:3a7713b1edbc 4971 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4972 -- MCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4973 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4974
AnnaBridge 171:3a7713b1edbc 4975 /*!
AnnaBridge 171:3a7713b1edbc 4976 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4977 * @{
AnnaBridge 171:3a7713b1edbc 4978 */
AnnaBridge 171:3a7713b1edbc 4979
AnnaBridge 171:3a7713b1edbc 4980 /** MCM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4981 typedef struct {
AnnaBridge 171:3a7713b1edbc 4982 uint8_t RESERVED_0[8];
AnnaBridge 171:3a7713b1edbc 4983 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 4984 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 4985 __IO uint32_t PLACR; /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 4986 } MCM_Type;
AnnaBridge 171:3a7713b1edbc 4987
AnnaBridge 171:3a7713b1edbc 4988 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4989 -- MCM Register Masks
AnnaBridge 171:3a7713b1edbc 4990 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4991
AnnaBridge 171:3a7713b1edbc 4992 /*!
AnnaBridge 171:3a7713b1edbc 4993 * @addtogroup MCM_Register_Masks MCM Register Masks
AnnaBridge 171:3a7713b1edbc 4994 * @{
AnnaBridge 171:3a7713b1edbc 4995 */
AnnaBridge 171:3a7713b1edbc 4996
AnnaBridge 171:3a7713b1edbc 4997 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
AnnaBridge 171:3a7713b1edbc 4998 #define MCM_PLASC_ASC_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 4999 #define MCM_PLASC_ASC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5000 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
AnnaBridge 171:3a7713b1edbc 5001
AnnaBridge 171:3a7713b1edbc 5002 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
AnnaBridge 171:3a7713b1edbc 5003 #define MCM_PLAMC_AMC_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5004 #define MCM_PLAMC_AMC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5005 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
AnnaBridge 171:3a7713b1edbc 5006
AnnaBridge 171:3a7713b1edbc 5007 /*! @name PLACR - Crossbar Switch (AXBS) Control Register */
AnnaBridge 171:3a7713b1edbc 5008 #define MCM_PLACR_ARB_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 5009 #define MCM_PLACR_ARB_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 5010 #define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK)
AnnaBridge 171:3a7713b1edbc 5011
AnnaBridge 171:3a7713b1edbc 5012
AnnaBridge 171:3a7713b1edbc 5013 /*!
AnnaBridge 171:3a7713b1edbc 5014 * @}
AnnaBridge 171:3a7713b1edbc 5015 */ /* end of group MCM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5016
AnnaBridge 171:3a7713b1edbc 5017
AnnaBridge 171:3a7713b1edbc 5018 /* MCM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5019 /** Peripheral MCM base address */
AnnaBridge 171:3a7713b1edbc 5020 #define MCM_BASE (0xE0080000u)
AnnaBridge 171:3a7713b1edbc 5021 /** Peripheral MCM base pointer */
AnnaBridge 171:3a7713b1edbc 5022 #define MCM ((MCM_Type *)MCM_BASE)
AnnaBridge 171:3a7713b1edbc 5023 /** Array initializer of MCM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5024 #define MCM_BASE_ADDRS { MCM_BASE }
AnnaBridge 171:3a7713b1edbc 5025 /** Array initializer of MCM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5026 #define MCM_BASE_PTRS { MCM }
AnnaBridge 171:3a7713b1edbc 5027 /** Interrupt vectors for the MCM peripheral type */
AnnaBridge 171:3a7713b1edbc 5028 #define MCM_IRQS { MCM_IRQn }
AnnaBridge 171:3a7713b1edbc 5029
AnnaBridge 171:3a7713b1edbc 5030 /*!
AnnaBridge 171:3a7713b1edbc 5031 * @}
AnnaBridge 171:3a7713b1edbc 5032 */ /* end of group MCM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5033
AnnaBridge 171:3a7713b1edbc 5034
AnnaBridge 171:3a7713b1edbc 5035 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5036 -- NV Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5037 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5038
AnnaBridge 171:3a7713b1edbc 5039 /*!
AnnaBridge 171:3a7713b1edbc 5040 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5041 * @{
AnnaBridge 171:3a7713b1edbc 5042 */
AnnaBridge 171:3a7713b1edbc 5043
AnnaBridge 171:3a7713b1edbc 5044 /** NV - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5045 typedef struct {
AnnaBridge 171:3a7713b1edbc 5046 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 5047 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 5048 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 5049 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 5050 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 5051 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 5052 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 5053 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 5054 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 5055 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 5056 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 5057 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 5058 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 5059 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 5060 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
AnnaBridge 171:3a7713b1edbc 5061 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
AnnaBridge 171:3a7713b1edbc 5062 } NV_Type;
AnnaBridge 171:3a7713b1edbc 5063
AnnaBridge 171:3a7713b1edbc 5064 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5065 -- NV Register Masks
AnnaBridge 171:3a7713b1edbc 5066 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5067
AnnaBridge 171:3a7713b1edbc 5068 /*!
AnnaBridge 171:3a7713b1edbc 5069 * @addtogroup NV_Register_Masks NV Register Masks
AnnaBridge 171:3a7713b1edbc 5070 * @{
AnnaBridge 171:3a7713b1edbc 5071 */
AnnaBridge 171:3a7713b1edbc 5072
AnnaBridge 171:3a7713b1edbc 5073 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */
AnnaBridge 171:3a7713b1edbc 5074 #define NV_BACKKEY3_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5075 #define NV_BACKKEY3_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5076 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 5077
AnnaBridge 171:3a7713b1edbc 5078 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */
AnnaBridge 171:3a7713b1edbc 5079 #define NV_BACKKEY2_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5080 #define NV_BACKKEY2_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5081 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 5082
AnnaBridge 171:3a7713b1edbc 5083 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */
AnnaBridge 171:3a7713b1edbc 5084 #define NV_BACKKEY1_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5085 #define NV_BACKKEY1_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5086 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 5087
AnnaBridge 171:3a7713b1edbc 5088 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */
AnnaBridge 171:3a7713b1edbc 5089 #define NV_BACKKEY0_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5090 #define NV_BACKKEY0_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5091 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 5092
AnnaBridge 171:3a7713b1edbc 5093 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */
AnnaBridge 171:3a7713b1edbc 5094 #define NV_BACKKEY7_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5095 #define NV_BACKKEY7_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5096 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 5097
AnnaBridge 171:3a7713b1edbc 5098 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */
AnnaBridge 171:3a7713b1edbc 5099 #define NV_BACKKEY6_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5100 #define NV_BACKKEY6_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5101 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 5102
AnnaBridge 171:3a7713b1edbc 5103 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */
AnnaBridge 171:3a7713b1edbc 5104 #define NV_BACKKEY5_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5105 #define NV_BACKKEY5_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5106 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 5107
AnnaBridge 171:3a7713b1edbc 5108 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */
AnnaBridge 171:3a7713b1edbc 5109 #define NV_BACKKEY4_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5110 #define NV_BACKKEY4_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5111 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 5112
AnnaBridge 171:3a7713b1edbc 5113 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
AnnaBridge 171:3a7713b1edbc 5114 #define NV_FPROT3_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5115 #define NV_FPROT3_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5116 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 5117
AnnaBridge 171:3a7713b1edbc 5118 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
AnnaBridge 171:3a7713b1edbc 5119 #define NV_FPROT2_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5120 #define NV_FPROT2_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5121 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 5122
AnnaBridge 171:3a7713b1edbc 5123 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
AnnaBridge 171:3a7713b1edbc 5124 #define NV_FPROT1_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5125 #define NV_FPROT1_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5126 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 5127
AnnaBridge 171:3a7713b1edbc 5128 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
AnnaBridge 171:3a7713b1edbc 5129 #define NV_FPROT0_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5130 #define NV_FPROT0_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5131 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 5132
AnnaBridge 171:3a7713b1edbc 5133 /*! @name FSEC - Non-volatile Flash Security Register */
AnnaBridge 171:3a7713b1edbc 5134 #define NV_FSEC_SEC_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 5135 #define NV_FSEC_SEC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5136 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
AnnaBridge 171:3a7713b1edbc 5137 #define NV_FSEC_FSLACC_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 5138 #define NV_FSEC_FSLACC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5139 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
AnnaBridge 171:3a7713b1edbc 5140 #define NV_FSEC_MEEN_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 5141 #define NV_FSEC_MEEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5142 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
AnnaBridge 171:3a7713b1edbc 5143 #define NV_FSEC_KEYEN_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 5144 #define NV_FSEC_KEYEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5145 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
AnnaBridge 171:3a7713b1edbc 5146
AnnaBridge 171:3a7713b1edbc 5147 /*! @name FOPT - Non-volatile Flash Option Register */
AnnaBridge 171:3a7713b1edbc 5148 #define NV_FOPT_LPBOOT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5149 #define NV_FOPT_LPBOOT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5150 #define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
AnnaBridge 171:3a7713b1edbc 5151 #define NV_FOPT_EZPORT_DIS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5152 #define NV_FOPT_EZPORT_DIS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5153 #define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 5154 #define NV_FOPT_NMI_DIS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5155 #define NV_FOPT_NMI_DIS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5156 #define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 5157
AnnaBridge 171:3a7713b1edbc 5158 /*! @name FEPROT - Non-volatile EERAM Protection Register */
AnnaBridge 171:3a7713b1edbc 5159 #define NV_FEPROT_EPROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5160 #define NV_FEPROT_EPROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5161 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK)
AnnaBridge 171:3a7713b1edbc 5162
AnnaBridge 171:3a7713b1edbc 5163 /*! @name FDPROT - Non-volatile D-Flash Protection Register */
AnnaBridge 171:3a7713b1edbc 5164 #define NV_FDPROT_DPROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5165 #define NV_FDPROT_DPROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5166 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK)
AnnaBridge 171:3a7713b1edbc 5167
AnnaBridge 171:3a7713b1edbc 5168
AnnaBridge 171:3a7713b1edbc 5169 /*!
AnnaBridge 171:3a7713b1edbc 5170 * @}
AnnaBridge 171:3a7713b1edbc 5171 */ /* end of group NV_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5172
AnnaBridge 171:3a7713b1edbc 5173
AnnaBridge 171:3a7713b1edbc 5174 /* NV - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5175 /** Peripheral FTFL_FlashConfig base address */
AnnaBridge 171:3a7713b1edbc 5176 #define FTFL_FlashConfig_BASE (0x400u)
AnnaBridge 171:3a7713b1edbc 5177 /** Peripheral FTFL_FlashConfig base pointer */
AnnaBridge 171:3a7713b1edbc 5178 #define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE)
AnnaBridge 171:3a7713b1edbc 5179 /** Array initializer of NV peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5180 #define NV_BASE_ADDRS { FTFL_FlashConfig_BASE }
AnnaBridge 171:3a7713b1edbc 5181 /** Array initializer of NV peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5182 #define NV_BASE_PTRS { FTFL_FlashConfig }
AnnaBridge 171:3a7713b1edbc 5183
AnnaBridge 171:3a7713b1edbc 5184 /*!
AnnaBridge 171:3a7713b1edbc 5185 * @}
AnnaBridge 171:3a7713b1edbc 5186 */ /* end of group NV_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5187
AnnaBridge 171:3a7713b1edbc 5188
AnnaBridge 171:3a7713b1edbc 5189 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5190 -- OSC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5191 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5192
AnnaBridge 171:3a7713b1edbc 5193 /*!
AnnaBridge 171:3a7713b1edbc 5194 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5195 * @{
AnnaBridge 171:3a7713b1edbc 5196 */
AnnaBridge 171:3a7713b1edbc 5197
AnnaBridge 171:3a7713b1edbc 5198 /** OSC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5199 typedef struct {
AnnaBridge 171:3a7713b1edbc 5200 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 5201 } OSC_Type;
AnnaBridge 171:3a7713b1edbc 5202
AnnaBridge 171:3a7713b1edbc 5203 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5204 -- OSC Register Masks
AnnaBridge 171:3a7713b1edbc 5205 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5206
AnnaBridge 171:3a7713b1edbc 5207 /*!
AnnaBridge 171:3a7713b1edbc 5208 * @addtogroup OSC_Register_Masks OSC Register Masks
AnnaBridge 171:3a7713b1edbc 5209 * @{
AnnaBridge 171:3a7713b1edbc 5210 */
AnnaBridge 171:3a7713b1edbc 5211
AnnaBridge 171:3a7713b1edbc 5212 /*! @name CR - OSC Control Register */
AnnaBridge 171:3a7713b1edbc 5213 #define OSC_CR_SC16P_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5214 #define OSC_CR_SC16P_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5215 #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
AnnaBridge 171:3a7713b1edbc 5216 #define OSC_CR_SC8P_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5217 #define OSC_CR_SC8P_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5218 #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
AnnaBridge 171:3a7713b1edbc 5219 #define OSC_CR_SC4P_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5220 #define OSC_CR_SC4P_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5221 #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
AnnaBridge 171:3a7713b1edbc 5222 #define OSC_CR_SC2P_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5223 #define OSC_CR_SC2P_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5224 #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
AnnaBridge 171:3a7713b1edbc 5225 #define OSC_CR_EREFSTEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5226 #define OSC_CR_EREFSTEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5227 #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
AnnaBridge 171:3a7713b1edbc 5228 #define OSC_CR_ERCLKEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5229 #define OSC_CR_ERCLKEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5230 #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
AnnaBridge 171:3a7713b1edbc 5231
AnnaBridge 171:3a7713b1edbc 5232
AnnaBridge 171:3a7713b1edbc 5233 /*!
AnnaBridge 171:3a7713b1edbc 5234 * @}
AnnaBridge 171:3a7713b1edbc 5235 */ /* end of group OSC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5236
AnnaBridge 171:3a7713b1edbc 5237
AnnaBridge 171:3a7713b1edbc 5238 /* OSC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5239 /** Peripheral OSC base address */
AnnaBridge 171:3a7713b1edbc 5240 #define OSC_BASE (0x40065000u)
AnnaBridge 171:3a7713b1edbc 5241 /** Peripheral OSC base pointer */
AnnaBridge 171:3a7713b1edbc 5242 #define OSC ((OSC_Type *)OSC_BASE)
AnnaBridge 171:3a7713b1edbc 5243 /** Array initializer of OSC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5244 #define OSC_BASE_ADDRS { OSC_BASE }
AnnaBridge 171:3a7713b1edbc 5245 /** Array initializer of OSC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5246 #define OSC_BASE_PTRS { OSC }
AnnaBridge 171:3a7713b1edbc 5247
AnnaBridge 171:3a7713b1edbc 5248 /*!
AnnaBridge 171:3a7713b1edbc 5249 * @}
AnnaBridge 171:3a7713b1edbc 5250 */ /* end of group OSC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5251
AnnaBridge 171:3a7713b1edbc 5252
AnnaBridge 171:3a7713b1edbc 5253 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5254 -- PDB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5255 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5256
AnnaBridge 171:3a7713b1edbc 5257 /*!
AnnaBridge 171:3a7713b1edbc 5258 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5259 * @{
AnnaBridge 171:3a7713b1edbc 5260 */
AnnaBridge 171:3a7713b1edbc 5261
AnnaBridge 171:3a7713b1edbc 5262 /** PDB - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5263 typedef struct {
AnnaBridge 171:3a7713b1edbc 5264 __IO uint32_t SC; /**< Status and Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 5265 __IO uint32_t MOD; /**< Modulus Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 5266 __I uint32_t CNT; /**< Counter Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 5267 __IO uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 5268 struct { /* offset: 0x10, array step: 0x28 */
AnnaBridge 171:3a7713b1edbc 5269 __IO uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x28 */
AnnaBridge 171:3a7713b1edbc 5270 __IO uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x28 */
AnnaBridge 171:3a7713b1edbc 5271 __IO uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4 */
AnnaBridge 171:3a7713b1edbc 5272 uint8_t RESERVED_0[24];
AnnaBridge 171:3a7713b1edbc 5273 } CH[2];
AnnaBridge 171:3a7713b1edbc 5274 uint8_t RESERVED_0[240];
AnnaBridge 171:3a7713b1edbc 5275 struct { /* offset: 0x150, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 5276 __IO uint32_t INTC; /**< DAC Interval Trigger n Control Register, array offset: 0x150, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 5277 __IO uint32_t INT; /**< DAC Interval n Register, array offset: 0x154, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 5278 } DAC[1];
AnnaBridge 171:3a7713b1edbc 5279 uint8_t RESERVED_1[56];
AnnaBridge 171:3a7713b1edbc 5280 __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */
AnnaBridge 171:3a7713b1edbc 5281 __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 5282 } PDB_Type;
AnnaBridge 171:3a7713b1edbc 5283
AnnaBridge 171:3a7713b1edbc 5284 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5285 -- PDB Register Masks
AnnaBridge 171:3a7713b1edbc 5286 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5287
AnnaBridge 171:3a7713b1edbc 5288 /*!
AnnaBridge 171:3a7713b1edbc 5289 * @addtogroup PDB_Register_Masks PDB Register Masks
AnnaBridge 171:3a7713b1edbc 5290 * @{
AnnaBridge 171:3a7713b1edbc 5291 */
AnnaBridge 171:3a7713b1edbc 5292
AnnaBridge 171:3a7713b1edbc 5293 /*! @name SC - Status and Control Register */
AnnaBridge 171:3a7713b1edbc 5294 #define PDB_SC_LDOK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5295 #define PDB_SC_LDOK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5296 #define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
AnnaBridge 171:3a7713b1edbc 5297 #define PDB_SC_CONT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5298 #define PDB_SC_CONT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5299 #define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
AnnaBridge 171:3a7713b1edbc 5300 #define PDB_SC_MULT_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 5301 #define PDB_SC_MULT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5302 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
AnnaBridge 171:3a7713b1edbc 5303 #define PDB_SC_PDBIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5304 #define PDB_SC_PDBIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5305 #define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
AnnaBridge 171:3a7713b1edbc 5306 #define PDB_SC_PDBIF_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5307 #define PDB_SC_PDBIF_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5308 #define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
AnnaBridge 171:3a7713b1edbc 5309 #define PDB_SC_PDBEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5310 #define PDB_SC_PDBEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5311 #define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
AnnaBridge 171:3a7713b1edbc 5312 #define PDB_SC_TRGSEL_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 5313 #define PDB_SC_TRGSEL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5314 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 5315 #define PDB_SC_PRESCALER_MASK (0x7000U)
AnnaBridge 171:3a7713b1edbc 5316 #define PDB_SC_PRESCALER_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 5317 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
AnnaBridge 171:3a7713b1edbc 5318 #define PDB_SC_DMAEN_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 5319 #define PDB_SC_DMAEN_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 5320 #define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 5321 #define PDB_SC_SWTRIG_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 5322 #define PDB_SC_SWTRIG_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5323 #define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
AnnaBridge 171:3a7713b1edbc 5324 #define PDB_SC_PDBEIE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 5325 #define PDB_SC_PDBEIE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 5326 #define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
AnnaBridge 171:3a7713b1edbc 5327 #define PDB_SC_LDMOD_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 5328 #define PDB_SC_LDMOD_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 5329 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
AnnaBridge 171:3a7713b1edbc 5330
AnnaBridge 171:3a7713b1edbc 5331 /*! @name MOD - Modulus Register */
AnnaBridge 171:3a7713b1edbc 5332 #define PDB_MOD_MOD_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5333 #define PDB_MOD_MOD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5334 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
AnnaBridge 171:3a7713b1edbc 5335
AnnaBridge 171:3a7713b1edbc 5336 /*! @name CNT - Counter Register */
AnnaBridge 171:3a7713b1edbc 5337 #define PDB_CNT_CNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5338 #define PDB_CNT_CNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5339 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
AnnaBridge 171:3a7713b1edbc 5340
AnnaBridge 171:3a7713b1edbc 5341 /*! @name IDLY - Interrupt Delay Register */
AnnaBridge 171:3a7713b1edbc 5342 #define PDB_IDLY_IDLY_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5343 #define PDB_IDLY_IDLY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5344 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
AnnaBridge 171:3a7713b1edbc 5345
AnnaBridge 171:3a7713b1edbc 5346 /*! @name C1 - Channel n Control Register 1 */
AnnaBridge 171:3a7713b1edbc 5347 #define PDB_C1_EN_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5348 #define PDB_C1_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5349 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5350 #define PDB_C1_TOS_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 5351 #define PDB_C1_TOS_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5352 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
AnnaBridge 171:3a7713b1edbc 5353 #define PDB_C1_BB_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 5354 #define PDB_C1_BB_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5355 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
AnnaBridge 171:3a7713b1edbc 5356
AnnaBridge 171:3a7713b1edbc 5357 /* The count of PDB_C1 */
AnnaBridge 171:3a7713b1edbc 5358 #define PDB_C1_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 5359
AnnaBridge 171:3a7713b1edbc 5360 /*! @name S - Channel n Status Register */
AnnaBridge 171:3a7713b1edbc 5361 #define PDB_S_ERR_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5362 #define PDB_S_ERR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5363 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
AnnaBridge 171:3a7713b1edbc 5364 #define PDB_S_CF_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 5365 #define PDB_S_CF_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5366 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
AnnaBridge 171:3a7713b1edbc 5367
AnnaBridge 171:3a7713b1edbc 5368 /* The count of PDB_S */
AnnaBridge 171:3a7713b1edbc 5369 #define PDB_S_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 5370
AnnaBridge 171:3a7713b1edbc 5371 /*! @name DLY - Channel n Delay 0 Register..Channel n Delay 1 Register */
AnnaBridge 171:3a7713b1edbc 5372 #define PDB_DLY_DLY_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5373 #define PDB_DLY_DLY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5374 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
AnnaBridge 171:3a7713b1edbc 5375
AnnaBridge 171:3a7713b1edbc 5376 /* The count of PDB_DLY */
AnnaBridge 171:3a7713b1edbc 5377 #define PDB_DLY_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 5378
AnnaBridge 171:3a7713b1edbc 5379 /* The count of PDB_DLY */
AnnaBridge 171:3a7713b1edbc 5380 #define PDB_DLY_COUNT2 (2U)
AnnaBridge 171:3a7713b1edbc 5381
AnnaBridge 171:3a7713b1edbc 5382 /*! @name INTC - DAC Interval Trigger n Control Register */
AnnaBridge 171:3a7713b1edbc 5383 #define PDB_INTC_TOE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5384 #define PDB_INTC_TOE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5385 #define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
AnnaBridge 171:3a7713b1edbc 5386 #define PDB_INTC_EXT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5387 #define PDB_INTC_EXT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5388 #define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
AnnaBridge 171:3a7713b1edbc 5389
AnnaBridge 171:3a7713b1edbc 5390 /* The count of PDB_INTC */
AnnaBridge 171:3a7713b1edbc 5391 #define PDB_INTC_COUNT (1U)
AnnaBridge 171:3a7713b1edbc 5392
AnnaBridge 171:3a7713b1edbc 5393 /*! @name INT - DAC Interval n Register */
AnnaBridge 171:3a7713b1edbc 5394 #define PDB_INT_INT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5395 #define PDB_INT_INT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5396 #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
AnnaBridge 171:3a7713b1edbc 5397
AnnaBridge 171:3a7713b1edbc 5398 /* The count of PDB_INT */
AnnaBridge 171:3a7713b1edbc 5399 #define PDB_INT_COUNT (1U)
AnnaBridge 171:3a7713b1edbc 5400
AnnaBridge 171:3a7713b1edbc 5401 /*! @name POEN - Pulse-Out n Enable Register */
AnnaBridge 171:3a7713b1edbc 5402 #define PDB_POEN_POEN_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5403 #define PDB_POEN_POEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5404 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
AnnaBridge 171:3a7713b1edbc 5405
AnnaBridge 171:3a7713b1edbc 5406 /*! @name PODLY - Pulse-Out n Delay Register */
AnnaBridge 171:3a7713b1edbc 5407 #define PDB_PODLY_DLY2_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5408 #define PDB_PODLY_DLY2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5409 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
AnnaBridge 171:3a7713b1edbc 5410 #define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 5411 #define PDB_PODLY_DLY1_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5412 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
AnnaBridge 171:3a7713b1edbc 5413
AnnaBridge 171:3a7713b1edbc 5414 /* The count of PDB_PODLY */
AnnaBridge 171:3a7713b1edbc 5415 #define PDB_PODLY_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 5416
AnnaBridge 171:3a7713b1edbc 5417
AnnaBridge 171:3a7713b1edbc 5418 /*!
AnnaBridge 171:3a7713b1edbc 5419 * @}
AnnaBridge 171:3a7713b1edbc 5420 */ /* end of group PDB_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5421
AnnaBridge 171:3a7713b1edbc 5422
AnnaBridge 171:3a7713b1edbc 5423 /* PDB - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5424 /** Peripheral PDB0 base address */
AnnaBridge 171:3a7713b1edbc 5425 #define PDB0_BASE (0x40036000u)
AnnaBridge 171:3a7713b1edbc 5426 /** Peripheral PDB0 base pointer */
AnnaBridge 171:3a7713b1edbc 5427 #define PDB0 ((PDB_Type *)PDB0_BASE)
AnnaBridge 171:3a7713b1edbc 5428 /** Array initializer of PDB peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5429 #define PDB_BASE_ADDRS { PDB0_BASE }
AnnaBridge 171:3a7713b1edbc 5430 /** Array initializer of PDB peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5431 #define PDB_BASE_PTRS { PDB0 }
AnnaBridge 171:3a7713b1edbc 5432 /** Interrupt vectors for the PDB peripheral type */
AnnaBridge 171:3a7713b1edbc 5433 #define PDB_IRQS { PDB0_IRQn }
AnnaBridge 171:3a7713b1edbc 5434
AnnaBridge 171:3a7713b1edbc 5435 /*!
AnnaBridge 171:3a7713b1edbc 5436 * @}
AnnaBridge 171:3a7713b1edbc 5437 */ /* end of group PDB_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5438
AnnaBridge 171:3a7713b1edbc 5439
AnnaBridge 171:3a7713b1edbc 5440 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5441 -- PIT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5442 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5443
AnnaBridge 171:3a7713b1edbc 5444 /*!
AnnaBridge 171:3a7713b1edbc 5445 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5446 * @{
AnnaBridge 171:3a7713b1edbc 5447 */
AnnaBridge 171:3a7713b1edbc 5448
AnnaBridge 171:3a7713b1edbc 5449 /** PIT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5450 typedef struct {
AnnaBridge 171:3a7713b1edbc 5451 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 5452 uint8_t RESERVED_0[252];
AnnaBridge 171:3a7713b1edbc 5453 struct { /* offset: 0x100, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 5454 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 5455 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 5456 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 5457 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 5458 } CHANNEL[4];
AnnaBridge 171:3a7713b1edbc 5459 } PIT_Type;
AnnaBridge 171:3a7713b1edbc 5460
AnnaBridge 171:3a7713b1edbc 5461 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5462 -- PIT Register Masks
AnnaBridge 171:3a7713b1edbc 5463 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5464
AnnaBridge 171:3a7713b1edbc 5465 /*!
AnnaBridge 171:3a7713b1edbc 5466 * @addtogroup PIT_Register_Masks PIT Register Masks
AnnaBridge 171:3a7713b1edbc 5467 * @{
AnnaBridge 171:3a7713b1edbc 5468 */
AnnaBridge 171:3a7713b1edbc 5469
AnnaBridge 171:3a7713b1edbc 5470 /*! @name MCR - PIT Module Control Register */
AnnaBridge 171:3a7713b1edbc 5471 #define PIT_MCR_FRZ_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5472 #define PIT_MCR_FRZ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5473 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
AnnaBridge 171:3a7713b1edbc 5474 #define PIT_MCR_MDIS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5475 #define PIT_MCR_MDIS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5476 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
AnnaBridge 171:3a7713b1edbc 5477
AnnaBridge 171:3a7713b1edbc 5478 /*! @name LDVAL - Timer Load Value Register */
AnnaBridge 171:3a7713b1edbc 5479 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5480 #define PIT_LDVAL_TSV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5481 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
AnnaBridge 171:3a7713b1edbc 5482
AnnaBridge 171:3a7713b1edbc 5483 /* The count of PIT_LDVAL */
AnnaBridge 171:3a7713b1edbc 5484 #define PIT_LDVAL_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 5485
AnnaBridge 171:3a7713b1edbc 5486 /*! @name CVAL - Current Timer Value Register */
AnnaBridge 171:3a7713b1edbc 5487 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5488 #define PIT_CVAL_TVL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5489 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
AnnaBridge 171:3a7713b1edbc 5490
AnnaBridge 171:3a7713b1edbc 5491 /* The count of PIT_CVAL */
AnnaBridge 171:3a7713b1edbc 5492 #define PIT_CVAL_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 5493
AnnaBridge 171:3a7713b1edbc 5494 /*! @name TCTRL - Timer Control Register */
AnnaBridge 171:3a7713b1edbc 5495 #define PIT_TCTRL_TEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5496 #define PIT_TCTRL_TEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5497 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
AnnaBridge 171:3a7713b1edbc 5498 #define PIT_TCTRL_TIE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5499 #define PIT_TCTRL_TIE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5500 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
AnnaBridge 171:3a7713b1edbc 5501 #define PIT_TCTRL_CHN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5502 #define PIT_TCTRL_CHN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5503 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
AnnaBridge 171:3a7713b1edbc 5504
AnnaBridge 171:3a7713b1edbc 5505 /* The count of PIT_TCTRL */
AnnaBridge 171:3a7713b1edbc 5506 #define PIT_TCTRL_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 5507
AnnaBridge 171:3a7713b1edbc 5508 /*! @name TFLG - Timer Flag Register */
AnnaBridge 171:3a7713b1edbc 5509 #define PIT_TFLG_TIF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5510 #define PIT_TFLG_TIF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5511 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
AnnaBridge 171:3a7713b1edbc 5512
AnnaBridge 171:3a7713b1edbc 5513 /* The count of PIT_TFLG */
AnnaBridge 171:3a7713b1edbc 5514 #define PIT_TFLG_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 5515
AnnaBridge 171:3a7713b1edbc 5516
AnnaBridge 171:3a7713b1edbc 5517 /*!
AnnaBridge 171:3a7713b1edbc 5518 * @}
AnnaBridge 171:3a7713b1edbc 5519 */ /* end of group PIT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5520
AnnaBridge 171:3a7713b1edbc 5521
AnnaBridge 171:3a7713b1edbc 5522 /* PIT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5523 /** Peripheral PIT base address */
AnnaBridge 171:3a7713b1edbc 5524 #define PIT_BASE (0x40037000u)
AnnaBridge 171:3a7713b1edbc 5525 /** Peripheral PIT base pointer */
AnnaBridge 171:3a7713b1edbc 5526 #define PIT ((PIT_Type *)PIT_BASE)
AnnaBridge 171:3a7713b1edbc 5527 /** Array initializer of PIT peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5528 #define PIT_BASE_ADDRS { PIT_BASE }
AnnaBridge 171:3a7713b1edbc 5529 /** Array initializer of PIT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5530 #define PIT_BASE_PTRS { PIT }
AnnaBridge 171:3a7713b1edbc 5531 /** Interrupt vectors for the PIT peripheral type */
AnnaBridge 171:3a7713b1edbc 5532 #define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
AnnaBridge 171:3a7713b1edbc 5533
AnnaBridge 171:3a7713b1edbc 5534 /*!
AnnaBridge 171:3a7713b1edbc 5535 * @}
AnnaBridge 171:3a7713b1edbc 5536 */ /* end of group PIT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5537
AnnaBridge 171:3a7713b1edbc 5538
AnnaBridge 171:3a7713b1edbc 5539 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5540 -- PMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5541 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5542
AnnaBridge 171:3a7713b1edbc 5543 /*!
AnnaBridge 171:3a7713b1edbc 5544 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5545 * @{
AnnaBridge 171:3a7713b1edbc 5546 */
AnnaBridge 171:3a7713b1edbc 5547
AnnaBridge 171:3a7713b1edbc 5548 /** PMC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5549 typedef struct {
AnnaBridge 171:3a7713b1edbc 5550 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 5551 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 5552 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 5553 } PMC_Type;
AnnaBridge 171:3a7713b1edbc 5554
AnnaBridge 171:3a7713b1edbc 5555 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5556 -- PMC Register Masks
AnnaBridge 171:3a7713b1edbc 5557 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5558
AnnaBridge 171:3a7713b1edbc 5559 /*!
AnnaBridge 171:3a7713b1edbc 5560 * @addtogroup PMC_Register_Masks PMC Register Masks
AnnaBridge 171:3a7713b1edbc 5561 * @{
AnnaBridge 171:3a7713b1edbc 5562 */
AnnaBridge 171:3a7713b1edbc 5563
AnnaBridge 171:3a7713b1edbc 5564 /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
AnnaBridge 171:3a7713b1edbc 5565 #define PMC_LVDSC1_LVDV_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 5566 #define PMC_LVDSC1_LVDV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5567 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
AnnaBridge 171:3a7713b1edbc 5568 #define PMC_LVDSC1_LVDRE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5569 #define PMC_LVDSC1_LVDRE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5570 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
AnnaBridge 171:3a7713b1edbc 5571 #define PMC_LVDSC1_LVDIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5572 #define PMC_LVDSC1_LVDIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5573 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
AnnaBridge 171:3a7713b1edbc 5574 #define PMC_LVDSC1_LVDACK_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5575 #define PMC_LVDSC1_LVDACK_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5576 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
AnnaBridge 171:3a7713b1edbc 5577 #define PMC_LVDSC1_LVDF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5578 #define PMC_LVDSC1_LVDF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5579 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
AnnaBridge 171:3a7713b1edbc 5580
AnnaBridge 171:3a7713b1edbc 5581 /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
AnnaBridge 171:3a7713b1edbc 5582 #define PMC_LVDSC2_LVWV_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 5583 #define PMC_LVDSC2_LVWV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5584 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
AnnaBridge 171:3a7713b1edbc 5585 #define PMC_LVDSC2_LVWIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5586 #define PMC_LVDSC2_LVWIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5587 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
AnnaBridge 171:3a7713b1edbc 5588 #define PMC_LVDSC2_LVWACK_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5589 #define PMC_LVDSC2_LVWACK_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5590 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
AnnaBridge 171:3a7713b1edbc 5591 #define PMC_LVDSC2_LVWF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5592 #define PMC_LVDSC2_LVWF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5593 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
AnnaBridge 171:3a7713b1edbc 5594
AnnaBridge 171:3a7713b1edbc 5595 /*! @name REGSC - Regulator Status And Control register */
AnnaBridge 171:3a7713b1edbc 5596 #define PMC_REGSC_BGBE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5597 #define PMC_REGSC_BGBE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5598 #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
AnnaBridge 171:3a7713b1edbc 5599 #define PMC_REGSC_REGONS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5600 #define PMC_REGSC_REGONS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5601 #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
AnnaBridge 171:3a7713b1edbc 5602 #define PMC_REGSC_ACKISO_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5603 #define PMC_REGSC_ACKISO_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5604 #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
AnnaBridge 171:3a7713b1edbc 5605 #define PMC_REGSC_BGEN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5606 #define PMC_REGSC_BGEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5607 #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
AnnaBridge 171:3a7713b1edbc 5608
AnnaBridge 171:3a7713b1edbc 5609
AnnaBridge 171:3a7713b1edbc 5610 /*!
AnnaBridge 171:3a7713b1edbc 5611 * @}
AnnaBridge 171:3a7713b1edbc 5612 */ /* end of group PMC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5613
AnnaBridge 171:3a7713b1edbc 5614
AnnaBridge 171:3a7713b1edbc 5615 /* PMC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5616 /** Peripheral PMC base address */
AnnaBridge 171:3a7713b1edbc 5617 #define PMC_BASE (0x4007D000u)
AnnaBridge 171:3a7713b1edbc 5618 /** Peripheral PMC base pointer */
AnnaBridge 171:3a7713b1edbc 5619 #define PMC ((PMC_Type *)PMC_BASE)
AnnaBridge 171:3a7713b1edbc 5620 /** Array initializer of PMC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5621 #define PMC_BASE_ADDRS { PMC_BASE }
AnnaBridge 171:3a7713b1edbc 5622 /** Array initializer of PMC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5623 #define PMC_BASE_PTRS { PMC }
AnnaBridge 171:3a7713b1edbc 5624 /** Interrupt vectors for the PMC peripheral type */
AnnaBridge 171:3a7713b1edbc 5625 #define PMC_IRQS { PMC_IRQn }
AnnaBridge 171:3a7713b1edbc 5626
AnnaBridge 171:3a7713b1edbc 5627 /*!
AnnaBridge 171:3a7713b1edbc 5628 * @}
AnnaBridge 171:3a7713b1edbc 5629 */ /* end of group PMC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5630
AnnaBridge 171:3a7713b1edbc 5631
AnnaBridge 171:3a7713b1edbc 5632 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5633 -- PORT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5634 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5635
AnnaBridge 171:3a7713b1edbc 5636 /*!
AnnaBridge 171:3a7713b1edbc 5637 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5638 * @{
AnnaBridge 171:3a7713b1edbc 5639 */
AnnaBridge 171:3a7713b1edbc 5640
AnnaBridge 171:3a7713b1edbc 5641 /** PORT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5642 typedef struct {
AnnaBridge 171:3a7713b1edbc 5643 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 5644 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 5645 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 5646 uint8_t RESERVED_0[24];
AnnaBridge 171:3a7713b1edbc 5647 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 5648 uint8_t RESERVED_1[28];
AnnaBridge 171:3a7713b1edbc 5649 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
AnnaBridge 171:3a7713b1edbc 5650 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
AnnaBridge 171:3a7713b1edbc 5651 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
AnnaBridge 171:3a7713b1edbc 5652 } PORT_Type;
AnnaBridge 171:3a7713b1edbc 5653
AnnaBridge 171:3a7713b1edbc 5654 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5655 -- PORT Register Masks
AnnaBridge 171:3a7713b1edbc 5656 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5657
AnnaBridge 171:3a7713b1edbc 5658 /*!
AnnaBridge 171:3a7713b1edbc 5659 * @addtogroup PORT_Register_Masks PORT Register Masks
AnnaBridge 171:3a7713b1edbc 5660 * @{
AnnaBridge 171:3a7713b1edbc 5661 */
AnnaBridge 171:3a7713b1edbc 5662
AnnaBridge 171:3a7713b1edbc 5663 /*! @name PCR - Pin Control Register n */
AnnaBridge 171:3a7713b1edbc 5664 #define PORT_PCR_PS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5665 #define PORT_PCR_PS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5666 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
AnnaBridge 171:3a7713b1edbc 5667 #define PORT_PCR_PE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5668 #define PORT_PCR_PE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5669 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
AnnaBridge 171:3a7713b1edbc 5670 #define PORT_PCR_SRE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5671 #define PORT_PCR_SRE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5672 #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
AnnaBridge 171:3a7713b1edbc 5673 #define PORT_PCR_PFE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5674 #define PORT_PCR_PFE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5675 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
AnnaBridge 171:3a7713b1edbc 5676 #define PORT_PCR_ODE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5677 #define PORT_PCR_ODE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5678 #define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
AnnaBridge 171:3a7713b1edbc 5679 #define PORT_PCR_DSE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5680 #define PORT_PCR_DSE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5681 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
AnnaBridge 171:3a7713b1edbc 5682 #define PORT_PCR_MUX_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 5683 #define PORT_PCR_MUX_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5684 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
AnnaBridge 171:3a7713b1edbc 5685 #define PORT_PCR_LK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 5686 #define PORT_PCR_LK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 5687 #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
AnnaBridge 171:3a7713b1edbc 5688 #define PORT_PCR_IRQC_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 5689 #define PORT_PCR_IRQC_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5690 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
AnnaBridge 171:3a7713b1edbc 5691 #define PORT_PCR_ISF_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 5692 #define PORT_PCR_ISF_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 5693 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
AnnaBridge 171:3a7713b1edbc 5694
AnnaBridge 171:3a7713b1edbc 5695 /* The count of PORT_PCR */
AnnaBridge 171:3a7713b1edbc 5696 #define PORT_PCR_COUNT (32U)
AnnaBridge 171:3a7713b1edbc 5697
AnnaBridge 171:3a7713b1edbc 5698 /*! @name GPCLR - Global Pin Control Low Register */
AnnaBridge 171:3a7713b1edbc 5699 #define PORT_GPCLR_GPWD_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5700 #define PORT_GPCLR_GPWD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5701 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
AnnaBridge 171:3a7713b1edbc 5702 #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 5703 #define PORT_GPCLR_GPWE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5704 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
AnnaBridge 171:3a7713b1edbc 5705
AnnaBridge 171:3a7713b1edbc 5706 /*! @name GPCHR - Global Pin Control High Register */
AnnaBridge 171:3a7713b1edbc 5707 #define PORT_GPCHR_GPWD_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5708 #define PORT_GPCHR_GPWD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5709 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
AnnaBridge 171:3a7713b1edbc 5710 #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 5711 #define PORT_GPCHR_GPWE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5712 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
AnnaBridge 171:3a7713b1edbc 5713
AnnaBridge 171:3a7713b1edbc 5714 /*! @name ISFR - Interrupt Status Flag Register */
AnnaBridge 171:3a7713b1edbc 5715 #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5716 #define PORT_ISFR_ISF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5717 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
AnnaBridge 171:3a7713b1edbc 5718
AnnaBridge 171:3a7713b1edbc 5719 /*! @name DFER - Digital Filter Enable Register */
AnnaBridge 171:3a7713b1edbc 5720 #define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5721 #define PORT_DFER_DFE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5722 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
AnnaBridge 171:3a7713b1edbc 5723
AnnaBridge 171:3a7713b1edbc 5724 /*! @name DFCR - Digital Filter Clock Register */
AnnaBridge 171:3a7713b1edbc 5725 #define PORT_DFCR_CS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5726 #define PORT_DFCR_CS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5727 #define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
AnnaBridge 171:3a7713b1edbc 5728
AnnaBridge 171:3a7713b1edbc 5729 /*! @name DFWR - Digital Filter Width Register */
AnnaBridge 171:3a7713b1edbc 5730 #define PORT_DFWR_FILT_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 5731 #define PORT_DFWR_FILT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5732 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
AnnaBridge 171:3a7713b1edbc 5733
AnnaBridge 171:3a7713b1edbc 5734
AnnaBridge 171:3a7713b1edbc 5735 /*!
AnnaBridge 171:3a7713b1edbc 5736 * @}
AnnaBridge 171:3a7713b1edbc 5737 */ /* end of group PORT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5738
AnnaBridge 171:3a7713b1edbc 5739
AnnaBridge 171:3a7713b1edbc 5740 /* PORT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5741 /** Peripheral PORTA base address */
AnnaBridge 171:3a7713b1edbc 5742 #define PORTA_BASE (0x40049000u)
AnnaBridge 171:3a7713b1edbc 5743 /** Peripheral PORTA base pointer */
AnnaBridge 171:3a7713b1edbc 5744 #define PORTA ((PORT_Type *)PORTA_BASE)
AnnaBridge 171:3a7713b1edbc 5745 /** Peripheral PORTB base address */
AnnaBridge 171:3a7713b1edbc 5746 #define PORTB_BASE (0x4004A000u)
AnnaBridge 171:3a7713b1edbc 5747 /** Peripheral PORTB base pointer */
AnnaBridge 171:3a7713b1edbc 5748 #define PORTB ((PORT_Type *)PORTB_BASE)
AnnaBridge 171:3a7713b1edbc 5749 /** Peripheral PORTC base address */
AnnaBridge 171:3a7713b1edbc 5750 #define PORTC_BASE (0x4004B000u)
AnnaBridge 171:3a7713b1edbc 5751 /** Peripheral PORTC base pointer */
AnnaBridge 171:3a7713b1edbc 5752 #define PORTC ((PORT_Type *)PORTC_BASE)
AnnaBridge 171:3a7713b1edbc 5753 /** Peripheral PORTD base address */
AnnaBridge 171:3a7713b1edbc 5754 #define PORTD_BASE (0x4004C000u)
AnnaBridge 171:3a7713b1edbc 5755 /** Peripheral PORTD base pointer */
AnnaBridge 171:3a7713b1edbc 5756 #define PORTD ((PORT_Type *)PORTD_BASE)
AnnaBridge 171:3a7713b1edbc 5757 /** Peripheral PORTE base address */
AnnaBridge 171:3a7713b1edbc 5758 #define PORTE_BASE (0x4004D000u)
AnnaBridge 171:3a7713b1edbc 5759 /** Peripheral PORTE base pointer */
AnnaBridge 171:3a7713b1edbc 5760 #define PORTE ((PORT_Type *)PORTE_BASE)
AnnaBridge 171:3a7713b1edbc 5761 /** Array initializer of PORT peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5762 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
AnnaBridge 171:3a7713b1edbc 5763 /** Array initializer of PORT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5764 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
AnnaBridge 171:3a7713b1edbc 5765 /** Interrupt vectors for the PORT peripheral type */
AnnaBridge 171:3a7713b1edbc 5766 #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
AnnaBridge 171:3a7713b1edbc 5767
AnnaBridge 171:3a7713b1edbc 5768 /*!
AnnaBridge 171:3a7713b1edbc 5769 * @}
AnnaBridge 171:3a7713b1edbc 5770 */ /* end of group PORT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5771
AnnaBridge 171:3a7713b1edbc 5772
AnnaBridge 171:3a7713b1edbc 5773 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5774 -- RCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5775 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5776
AnnaBridge 171:3a7713b1edbc 5777 /*!
AnnaBridge 171:3a7713b1edbc 5778 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5779 * @{
AnnaBridge 171:3a7713b1edbc 5780 */
AnnaBridge 171:3a7713b1edbc 5781
AnnaBridge 171:3a7713b1edbc 5782 /** RCM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5783 typedef struct {
AnnaBridge 171:3a7713b1edbc 5784 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 5785 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 5786 uint8_t RESERVED_0[2];
AnnaBridge 171:3a7713b1edbc 5787 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 5788 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 5789 uint8_t RESERVED_1[1];
AnnaBridge 171:3a7713b1edbc 5790 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 5791 } RCM_Type;
AnnaBridge 171:3a7713b1edbc 5792
AnnaBridge 171:3a7713b1edbc 5793 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5794 -- RCM Register Masks
AnnaBridge 171:3a7713b1edbc 5795 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5796
AnnaBridge 171:3a7713b1edbc 5797 /*!
AnnaBridge 171:3a7713b1edbc 5798 * @addtogroup RCM_Register_Masks RCM Register Masks
AnnaBridge 171:3a7713b1edbc 5799 * @{
AnnaBridge 171:3a7713b1edbc 5800 */
AnnaBridge 171:3a7713b1edbc 5801
AnnaBridge 171:3a7713b1edbc 5802 /*! @name SRS0 - System Reset Status Register 0 */
AnnaBridge 171:3a7713b1edbc 5803 #define RCM_SRS0_WAKEUP_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5804 #define RCM_SRS0_WAKEUP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5805 #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
AnnaBridge 171:3a7713b1edbc 5806 #define RCM_SRS0_LVD_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5807 #define RCM_SRS0_LVD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5808 #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
AnnaBridge 171:3a7713b1edbc 5809 #define RCM_SRS0_LOC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5810 #define RCM_SRS0_LOC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5811 #define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
AnnaBridge 171:3a7713b1edbc 5812 #define RCM_SRS0_LOL_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5813 #define RCM_SRS0_LOL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5814 #define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
AnnaBridge 171:3a7713b1edbc 5815 #define RCM_SRS0_WDOG_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5816 #define RCM_SRS0_WDOG_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5817 #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
AnnaBridge 171:3a7713b1edbc 5818 #define RCM_SRS0_PIN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5819 #define RCM_SRS0_PIN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5820 #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
AnnaBridge 171:3a7713b1edbc 5821 #define RCM_SRS0_POR_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5822 #define RCM_SRS0_POR_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5823 #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
AnnaBridge 171:3a7713b1edbc 5824
AnnaBridge 171:3a7713b1edbc 5825 /*! @name SRS1 - System Reset Status Register 1 */
AnnaBridge 171:3a7713b1edbc 5826 #define RCM_SRS1_JTAG_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5827 #define RCM_SRS1_JTAG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5828 #define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
AnnaBridge 171:3a7713b1edbc 5829 #define RCM_SRS1_LOCKUP_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5830 #define RCM_SRS1_LOCKUP_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5831 #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
AnnaBridge 171:3a7713b1edbc 5832 #define RCM_SRS1_SW_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5833 #define RCM_SRS1_SW_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5834 #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
AnnaBridge 171:3a7713b1edbc 5835 #define RCM_SRS1_MDM_AP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5836 #define RCM_SRS1_MDM_AP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5837 #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
AnnaBridge 171:3a7713b1edbc 5838 #define RCM_SRS1_EZPT_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5839 #define RCM_SRS1_EZPT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5840 #define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
AnnaBridge 171:3a7713b1edbc 5841 #define RCM_SRS1_SACKERR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5842 #define RCM_SRS1_SACKERR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5843 #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
AnnaBridge 171:3a7713b1edbc 5844
AnnaBridge 171:3a7713b1edbc 5845 /*! @name RPFC - Reset Pin Filter Control register */
AnnaBridge 171:3a7713b1edbc 5846 #define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 5847 #define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5848 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
AnnaBridge 171:3a7713b1edbc 5849 #define RCM_RPFC_RSTFLTSS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5850 #define RCM_RPFC_RSTFLTSS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5851 #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
AnnaBridge 171:3a7713b1edbc 5852
AnnaBridge 171:3a7713b1edbc 5853 /*! @name RPFW - Reset Pin Filter Width register */
AnnaBridge 171:3a7713b1edbc 5854 #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 5855 #define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5856 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 5857
AnnaBridge 171:3a7713b1edbc 5858 /*! @name MR - Mode Register */
AnnaBridge 171:3a7713b1edbc 5859 #define RCM_MR_EZP_MS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5860 #define RCM_MR_EZP_MS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5861 #define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
AnnaBridge 171:3a7713b1edbc 5862
AnnaBridge 171:3a7713b1edbc 5863
AnnaBridge 171:3a7713b1edbc 5864 /*!
AnnaBridge 171:3a7713b1edbc 5865 * @}
AnnaBridge 171:3a7713b1edbc 5866 */ /* end of group RCM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5867
AnnaBridge 171:3a7713b1edbc 5868
AnnaBridge 171:3a7713b1edbc 5869 /* RCM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5870 /** Peripheral RCM base address */
AnnaBridge 171:3a7713b1edbc 5871 #define RCM_BASE (0x4007F000u)
AnnaBridge 171:3a7713b1edbc 5872 /** Peripheral RCM base pointer */
AnnaBridge 171:3a7713b1edbc 5873 #define RCM ((RCM_Type *)RCM_BASE)
AnnaBridge 171:3a7713b1edbc 5874 /** Array initializer of RCM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5875 #define RCM_BASE_ADDRS { RCM_BASE }
AnnaBridge 171:3a7713b1edbc 5876 /** Array initializer of RCM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5877 #define RCM_BASE_PTRS { RCM }
AnnaBridge 171:3a7713b1edbc 5878
AnnaBridge 171:3a7713b1edbc 5879 /*!
AnnaBridge 171:3a7713b1edbc 5880 * @}
AnnaBridge 171:3a7713b1edbc 5881 */ /* end of group RCM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5882
AnnaBridge 171:3a7713b1edbc 5883
AnnaBridge 171:3a7713b1edbc 5884 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5885 -- RFSYS Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5886 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5887
AnnaBridge 171:3a7713b1edbc 5888 /*!
AnnaBridge 171:3a7713b1edbc 5889 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5890 * @{
AnnaBridge 171:3a7713b1edbc 5891 */
AnnaBridge 171:3a7713b1edbc 5892
AnnaBridge 171:3a7713b1edbc 5893 /** RFSYS - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5894 typedef struct {
AnnaBridge 171:3a7713b1edbc 5895 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 5896 } RFSYS_Type;
AnnaBridge 171:3a7713b1edbc 5897
AnnaBridge 171:3a7713b1edbc 5898 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5899 -- RFSYS Register Masks
AnnaBridge 171:3a7713b1edbc 5900 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5901
AnnaBridge 171:3a7713b1edbc 5902 /*!
AnnaBridge 171:3a7713b1edbc 5903 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
AnnaBridge 171:3a7713b1edbc 5904 * @{
AnnaBridge 171:3a7713b1edbc 5905 */
AnnaBridge 171:3a7713b1edbc 5906
AnnaBridge 171:3a7713b1edbc 5907 /*! @name REG - Register file register */
AnnaBridge 171:3a7713b1edbc 5908 #define RFSYS_REG_LL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5909 #define RFSYS_REG_LL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5910 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
AnnaBridge 171:3a7713b1edbc 5911 #define RFSYS_REG_LH_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 5912 #define RFSYS_REG_LH_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5913 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
AnnaBridge 171:3a7713b1edbc 5914 #define RFSYS_REG_HL_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 5915 #define RFSYS_REG_HL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5916 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
AnnaBridge 171:3a7713b1edbc 5917 #define RFSYS_REG_HH_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 5918 #define RFSYS_REG_HH_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 5919 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
AnnaBridge 171:3a7713b1edbc 5920
AnnaBridge 171:3a7713b1edbc 5921 /* The count of RFSYS_REG */
AnnaBridge 171:3a7713b1edbc 5922 #define RFSYS_REG_COUNT (8U)
AnnaBridge 171:3a7713b1edbc 5923
AnnaBridge 171:3a7713b1edbc 5924
AnnaBridge 171:3a7713b1edbc 5925 /*!
AnnaBridge 171:3a7713b1edbc 5926 * @}
AnnaBridge 171:3a7713b1edbc 5927 */ /* end of group RFSYS_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5928
AnnaBridge 171:3a7713b1edbc 5929
AnnaBridge 171:3a7713b1edbc 5930 /* RFSYS - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5931 /** Peripheral RFSYS base address */
AnnaBridge 171:3a7713b1edbc 5932 #define RFSYS_BASE (0x40041000u)
AnnaBridge 171:3a7713b1edbc 5933 /** Peripheral RFSYS base pointer */
AnnaBridge 171:3a7713b1edbc 5934 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
AnnaBridge 171:3a7713b1edbc 5935 /** Array initializer of RFSYS peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5936 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
AnnaBridge 171:3a7713b1edbc 5937 /** Array initializer of RFSYS peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5938 #define RFSYS_BASE_PTRS { RFSYS }
AnnaBridge 171:3a7713b1edbc 5939
AnnaBridge 171:3a7713b1edbc 5940 /*!
AnnaBridge 171:3a7713b1edbc 5941 * @}
AnnaBridge 171:3a7713b1edbc 5942 */ /* end of group RFSYS_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5943
AnnaBridge 171:3a7713b1edbc 5944
AnnaBridge 171:3a7713b1edbc 5945 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5946 -- RFVBAT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5947 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5948
AnnaBridge 171:3a7713b1edbc 5949 /*!
AnnaBridge 171:3a7713b1edbc 5950 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5951 * @{
AnnaBridge 171:3a7713b1edbc 5952 */
AnnaBridge 171:3a7713b1edbc 5953
AnnaBridge 171:3a7713b1edbc 5954 /** RFVBAT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5955 typedef struct {
AnnaBridge 171:3a7713b1edbc 5956 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 5957 } RFVBAT_Type;
AnnaBridge 171:3a7713b1edbc 5958
AnnaBridge 171:3a7713b1edbc 5959 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5960 -- RFVBAT Register Masks
AnnaBridge 171:3a7713b1edbc 5961 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5962
AnnaBridge 171:3a7713b1edbc 5963 /*!
AnnaBridge 171:3a7713b1edbc 5964 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
AnnaBridge 171:3a7713b1edbc 5965 * @{
AnnaBridge 171:3a7713b1edbc 5966 */
AnnaBridge 171:3a7713b1edbc 5967
AnnaBridge 171:3a7713b1edbc 5968 /*! @name REG - VBAT register file register */
AnnaBridge 171:3a7713b1edbc 5969 #define RFVBAT_REG_LL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5970 #define RFVBAT_REG_LL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5971 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
AnnaBridge 171:3a7713b1edbc 5972 #define RFVBAT_REG_LH_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 5973 #define RFVBAT_REG_LH_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5974 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
AnnaBridge 171:3a7713b1edbc 5975 #define RFVBAT_REG_HL_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 5976 #define RFVBAT_REG_HL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5977 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
AnnaBridge 171:3a7713b1edbc 5978 #define RFVBAT_REG_HH_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 5979 #define RFVBAT_REG_HH_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 5980 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
AnnaBridge 171:3a7713b1edbc 5981
AnnaBridge 171:3a7713b1edbc 5982 /* The count of RFVBAT_REG */
AnnaBridge 171:3a7713b1edbc 5983 #define RFVBAT_REG_COUNT (8U)
AnnaBridge 171:3a7713b1edbc 5984
AnnaBridge 171:3a7713b1edbc 5985
AnnaBridge 171:3a7713b1edbc 5986 /*!
AnnaBridge 171:3a7713b1edbc 5987 * @}
AnnaBridge 171:3a7713b1edbc 5988 */ /* end of group RFVBAT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5989
AnnaBridge 171:3a7713b1edbc 5990
AnnaBridge 171:3a7713b1edbc 5991 /* RFVBAT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5992 /** Peripheral RFVBAT base address */
AnnaBridge 171:3a7713b1edbc 5993 #define RFVBAT_BASE (0x4003E000u)
AnnaBridge 171:3a7713b1edbc 5994 /** Peripheral RFVBAT base pointer */
AnnaBridge 171:3a7713b1edbc 5995 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
AnnaBridge 171:3a7713b1edbc 5996 /** Array initializer of RFVBAT peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5997 #define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
AnnaBridge 171:3a7713b1edbc 5998 /** Array initializer of RFVBAT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5999 #define RFVBAT_BASE_PTRS { RFVBAT }
AnnaBridge 171:3a7713b1edbc 6000
AnnaBridge 171:3a7713b1edbc 6001 /*!
AnnaBridge 171:3a7713b1edbc 6002 * @}
AnnaBridge 171:3a7713b1edbc 6003 */ /* end of group RFVBAT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 6004
AnnaBridge 171:3a7713b1edbc 6005
AnnaBridge 171:3a7713b1edbc 6006 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6007 -- RNG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6008 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6009
AnnaBridge 171:3a7713b1edbc 6010 /*!
AnnaBridge 171:3a7713b1edbc 6011 * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6012 * @{
AnnaBridge 171:3a7713b1edbc 6013 */
AnnaBridge 171:3a7713b1edbc 6014
AnnaBridge 171:3a7713b1edbc 6015 /** RNG - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 6016 typedef struct {
AnnaBridge 171:3a7713b1edbc 6017 __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 6018 __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 6019 __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 6020 __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 6021 } RNG_Type;
AnnaBridge 171:3a7713b1edbc 6022
AnnaBridge 171:3a7713b1edbc 6023 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6024 -- RNG Register Masks
AnnaBridge 171:3a7713b1edbc 6025 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6026
AnnaBridge 171:3a7713b1edbc 6027 /*!
AnnaBridge 171:3a7713b1edbc 6028 * @addtogroup RNG_Register_Masks RNG Register Masks
AnnaBridge 171:3a7713b1edbc 6029 * @{
AnnaBridge 171:3a7713b1edbc 6030 */
AnnaBridge 171:3a7713b1edbc 6031
AnnaBridge 171:3a7713b1edbc 6032 /*! @name CR - RNGA Control Register */
AnnaBridge 171:3a7713b1edbc 6033 #define RNG_CR_GO_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6034 #define RNG_CR_GO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6035 #define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)
AnnaBridge 171:3a7713b1edbc 6036 #define RNG_CR_HA_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6037 #define RNG_CR_HA_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6038 #define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)
AnnaBridge 171:3a7713b1edbc 6039 #define RNG_CR_INTM_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6040 #define RNG_CR_INTM_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6041 #define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)
AnnaBridge 171:3a7713b1edbc 6042 #define RNG_CR_CLRI_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6043 #define RNG_CR_CLRI_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6044 #define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)
AnnaBridge 171:3a7713b1edbc 6045 #define RNG_CR_SLP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6046 #define RNG_CR_SLP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6047 #define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)
AnnaBridge 171:3a7713b1edbc 6048
AnnaBridge 171:3a7713b1edbc 6049 /*! @name SR - RNGA Status Register */
AnnaBridge 171:3a7713b1edbc 6050 #define RNG_SR_SECV_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6051 #define RNG_SR_SECV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6052 #define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)
AnnaBridge 171:3a7713b1edbc 6053 #define RNG_SR_LRS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6054 #define RNG_SR_LRS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6055 #define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)
AnnaBridge 171:3a7713b1edbc 6056 #define RNG_SR_ORU_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6057 #define RNG_SR_ORU_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6058 #define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)
AnnaBridge 171:3a7713b1edbc 6059 #define RNG_SR_ERRI_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6060 #define RNG_SR_ERRI_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6061 #define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)
AnnaBridge 171:3a7713b1edbc 6062 #define RNG_SR_SLP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6063 #define RNG_SR_SLP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6064 #define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)
AnnaBridge 171:3a7713b1edbc 6065 #define RNG_SR_OREG_LVL_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 6066 #define RNG_SR_OREG_LVL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6067 #define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
AnnaBridge 171:3a7713b1edbc 6068 #define RNG_SR_OREG_SIZE_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 6069 #define RNG_SR_OREG_SIZE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6070 #define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
AnnaBridge 171:3a7713b1edbc 6071
AnnaBridge 171:3a7713b1edbc 6072 /*! @name ER - RNGA Entropy Register */
AnnaBridge 171:3a7713b1edbc 6073 #define RNG_ER_EXT_ENT_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6074 #define RNG_ER_EXT_ENT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6075 #define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK)
AnnaBridge 171:3a7713b1edbc 6076
AnnaBridge 171:3a7713b1edbc 6077 /*! @name OR - RNGA Output Register */
AnnaBridge 171:3a7713b1edbc 6078 #define RNG_OR_RANDOUT_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6079 #define RNG_OR_RANDOUT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6080 #define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)
AnnaBridge 171:3a7713b1edbc 6081
AnnaBridge 171:3a7713b1edbc 6082
AnnaBridge 171:3a7713b1edbc 6083 /*!
AnnaBridge 171:3a7713b1edbc 6084 * @}
AnnaBridge 171:3a7713b1edbc 6085 */ /* end of group RNG_Register_Masks */
AnnaBridge 171:3a7713b1edbc 6086
AnnaBridge 171:3a7713b1edbc 6087
AnnaBridge 171:3a7713b1edbc 6088 /* RNG - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 6089 /** Peripheral RNG base address */
AnnaBridge 171:3a7713b1edbc 6090 #define RNG_BASE (0x40029000u)
AnnaBridge 171:3a7713b1edbc 6091 /** Peripheral RNG base pointer */
AnnaBridge 171:3a7713b1edbc 6092 #define RNG ((RNG_Type *)RNG_BASE)
AnnaBridge 171:3a7713b1edbc 6093 /** Array initializer of RNG peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 6094 #define RNG_BASE_ADDRS { RNG_BASE }
AnnaBridge 171:3a7713b1edbc 6095 /** Array initializer of RNG peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 6096 #define RNG_BASE_PTRS { RNG }
AnnaBridge 171:3a7713b1edbc 6097 /** Interrupt vectors for the RNG peripheral type */
AnnaBridge 171:3a7713b1edbc 6098 #define RNG_IRQS { RNG_IRQn }
AnnaBridge 171:3a7713b1edbc 6099
AnnaBridge 171:3a7713b1edbc 6100 /*!
AnnaBridge 171:3a7713b1edbc 6101 * @}
AnnaBridge 171:3a7713b1edbc 6102 */ /* end of group RNG_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 6103
AnnaBridge 171:3a7713b1edbc 6104
AnnaBridge 171:3a7713b1edbc 6105 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6106 -- RTC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6107 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6108
AnnaBridge 171:3a7713b1edbc 6109 /*!
AnnaBridge 171:3a7713b1edbc 6110 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6111 * @{
AnnaBridge 171:3a7713b1edbc 6112 */
AnnaBridge 171:3a7713b1edbc 6113
AnnaBridge 171:3a7713b1edbc 6114 /** RTC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 6115 typedef struct {
AnnaBridge 171:3a7713b1edbc 6116 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 6117 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 6118 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 6119 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 6120 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 6121 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 6122 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 6123 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 6124 __I uint32_t TTSR; /**< RTC Tamper Time Seconds Register, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 6125 __IO uint32_t MER; /**< RTC Monotonic Enable Register, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 6126 __IO uint32_t MCLR; /**< RTC Monotonic Counter Low Register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 6127 __IO uint32_t MCHR; /**< RTC Monotonic Counter High Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 6128 uint8_t RESERVED_0[2000];
AnnaBridge 171:3a7713b1edbc 6129 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
AnnaBridge 171:3a7713b1edbc 6130 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
AnnaBridge 171:3a7713b1edbc 6131 } RTC_Type;
AnnaBridge 171:3a7713b1edbc 6132
AnnaBridge 171:3a7713b1edbc 6133 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6134 -- RTC Register Masks
AnnaBridge 171:3a7713b1edbc 6135 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6136
AnnaBridge 171:3a7713b1edbc 6137 /*!
AnnaBridge 171:3a7713b1edbc 6138 * @addtogroup RTC_Register_Masks RTC Register Masks
AnnaBridge 171:3a7713b1edbc 6139 * @{
AnnaBridge 171:3a7713b1edbc 6140 */
AnnaBridge 171:3a7713b1edbc 6141
AnnaBridge 171:3a7713b1edbc 6142 /*! @name TSR - RTC Time Seconds Register */
AnnaBridge 171:3a7713b1edbc 6143 #define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6144 #define RTC_TSR_TSR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6145 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
AnnaBridge 171:3a7713b1edbc 6146
AnnaBridge 171:3a7713b1edbc 6147 /*! @name TPR - RTC Time Prescaler Register */
AnnaBridge 171:3a7713b1edbc 6148 #define RTC_TPR_TPR_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6149 #define RTC_TPR_TPR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6150 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
AnnaBridge 171:3a7713b1edbc 6151
AnnaBridge 171:3a7713b1edbc 6152 /*! @name TAR - RTC Time Alarm Register */
AnnaBridge 171:3a7713b1edbc 6153 #define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6154 #define RTC_TAR_TAR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6155 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
AnnaBridge 171:3a7713b1edbc 6156
AnnaBridge 171:3a7713b1edbc 6157 /*! @name TCR - RTC Time Compensation Register */
AnnaBridge 171:3a7713b1edbc 6158 #define RTC_TCR_TCR_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6159 #define RTC_TCR_TCR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6160 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
AnnaBridge 171:3a7713b1edbc 6161 #define RTC_TCR_CIR_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 6162 #define RTC_TCR_CIR_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6163 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
AnnaBridge 171:3a7713b1edbc 6164 #define RTC_TCR_TCV_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 6165 #define RTC_TCR_TCV_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6166 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
AnnaBridge 171:3a7713b1edbc 6167 #define RTC_TCR_CIC_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 6168 #define RTC_TCR_CIC_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6169 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
AnnaBridge 171:3a7713b1edbc 6170
AnnaBridge 171:3a7713b1edbc 6171 /*! @name CR - RTC Control Register */
AnnaBridge 171:3a7713b1edbc 6172 #define RTC_CR_SWR_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6173 #define RTC_CR_SWR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6174 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
AnnaBridge 171:3a7713b1edbc 6175 #define RTC_CR_WPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6176 #define RTC_CR_WPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6177 #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
AnnaBridge 171:3a7713b1edbc 6178 #define RTC_CR_SUP_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6179 #define RTC_CR_SUP_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6180 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
AnnaBridge 171:3a7713b1edbc 6181 #define RTC_CR_UM_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6182 #define RTC_CR_UM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6183 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
AnnaBridge 171:3a7713b1edbc 6184 #define RTC_CR_WPS_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6185 #define RTC_CR_WPS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6186 #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
AnnaBridge 171:3a7713b1edbc 6187 #define RTC_CR_OSCE_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 6188 #define RTC_CR_OSCE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6189 #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
AnnaBridge 171:3a7713b1edbc 6190 #define RTC_CR_CLKO_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 6191 #define RTC_CR_CLKO_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 6192 #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
AnnaBridge 171:3a7713b1edbc 6193 #define RTC_CR_SC16P_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 6194 #define RTC_CR_SC16P_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 6195 #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
AnnaBridge 171:3a7713b1edbc 6196 #define RTC_CR_SC8P_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 6197 #define RTC_CR_SC8P_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 6198 #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
AnnaBridge 171:3a7713b1edbc 6199 #define RTC_CR_SC4P_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 6200 #define RTC_CR_SC4P_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6201 #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
AnnaBridge 171:3a7713b1edbc 6202 #define RTC_CR_SC2P_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 6203 #define RTC_CR_SC2P_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 6204 #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
AnnaBridge 171:3a7713b1edbc 6205
AnnaBridge 171:3a7713b1edbc 6206 /*! @name SR - RTC Status Register */
AnnaBridge 171:3a7713b1edbc 6207 #define RTC_SR_TIF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6208 #define RTC_SR_TIF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6209 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
AnnaBridge 171:3a7713b1edbc 6210 #define RTC_SR_TOF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6211 #define RTC_SR_TOF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6212 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
AnnaBridge 171:3a7713b1edbc 6213 #define RTC_SR_TAF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6214 #define RTC_SR_TAF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6215 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
AnnaBridge 171:3a7713b1edbc 6216 #define RTC_SR_MOF_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6217 #define RTC_SR_MOF_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6218 #define RTC_SR_MOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_MOF_SHIFT)) & RTC_SR_MOF_MASK)
AnnaBridge 171:3a7713b1edbc 6219 #define RTC_SR_TCE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6220 #define RTC_SR_TCE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6221 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
AnnaBridge 171:3a7713b1edbc 6222
AnnaBridge 171:3a7713b1edbc 6223 /*! @name LR - RTC Lock Register */
AnnaBridge 171:3a7713b1edbc 6224 #define RTC_LR_TCL_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6225 #define RTC_LR_TCL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6226 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
AnnaBridge 171:3a7713b1edbc 6227 #define RTC_LR_CRL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6228 #define RTC_LR_CRL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6229 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
AnnaBridge 171:3a7713b1edbc 6230 #define RTC_LR_SRL_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6231 #define RTC_LR_SRL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6232 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
AnnaBridge 171:3a7713b1edbc 6233 #define RTC_LR_LRL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6234 #define RTC_LR_LRL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6235 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
AnnaBridge 171:3a7713b1edbc 6236 #define RTC_LR_TTSL_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 6237 #define RTC_LR_TTSL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6238 #define RTC_LR_TTSL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TTSL_SHIFT)) & RTC_LR_TTSL_MASK)
AnnaBridge 171:3a7713b1edbc 6239 #define RTC_LR_MEL_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 6240 #define RTC_LR_MEL_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 6241 #define RTC_LR_MEL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MEL_SHIFT)) & RTC_LR_MEL_MASK)
AnnaBridge 171:3a7713b1edbc 6242 #define RTC_LR_MCLL_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 6243 #define RTC_LR_MCLL_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 6244 #define RTC_LR_MCLL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCLL_SHIFT)) & RTC_LR_MCLL_MASK)
AnnaBridge 171:3a7713b1edbc 6245 #define RTC_LR_MCHL_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 6246 #define RTC_LR_MCHL_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 6247 #define RTC_LR_MCHL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCHL_SHIFT)) & RTC_LR_MCHL_MASK)
AnnaBridge 171:3a7713b1edbc 6248
AnnaBridge 171:3a7713b1edbc 6249 /*! @name IER - RTC Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 6250 #define RTC_IER_TIIE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6251 #define RTC_IER_TIIE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6252 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
AnnaBridge 171:3a7713b1edbc 6253 #define RTC_IER_TOIE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6254 #define RTC_IER_TOIE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6255 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
AnnaBridge 171:3a7713b1edbc 6256 #define RTC_IER_TAIE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6257 #define RTC_IER_TAIE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6258 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
AnnaBridge 171:3a7713b1edbc 6259 #define RTC_IER_MOIE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6260 #define RTC_IER_MOIE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6261 #define RTC_IER_MOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_MOIE_SHIFT)) & RTC_IER_MOIE_MASK)
AnnaBridge 171:3a7713b1edbc 6262 #define RTC_IER_TSIE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6263 #define RTC_IER_TSIE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6264 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
AnnaBridge 171:3a7713b1edbc 6265 #define RTC_IER_WPON_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6266 #define RTC_IER_WPON_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6267 #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
AnnaBridge 171:3a7713b1edbc 6268
AnnaBridge 171:3a7713b1edbc 6269 /*! @name TTSR - RTC Tamper Time Seconds Register */
AnnaBridge 171:3a7713b1edbc 6270 #define RTC_TTSR_TTS_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6271 #define RTC_TTSR_TTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6272 #define RTC_TTSR_TTS(x) (((uint32_t)(((uint32_t)(x)) << RTC_TTSR_TTS_SHIFT)) & RTC_TTSR_TTS_MASK)
AnnaBridge 171:3a7713b1edbc 6273
AnnaBridge 171:3a7713b1edbc 6274 /*! @name MER - RTC Monotonic Enable Register */
AnnaBridge 171:3a7713b1edbc 6275 #define RTC_MER_MCE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6276 #define RTC_MER_MCE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6277 #define RTC_MER_MCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_MER_MCE_SHIFT)) & RTC_MER_MCE_MASK)
AnnaBridge 171:3a7713b1edbc 6278
AnnaBridge 171:3a7713b1edbc 6279 /*! @name MCLR - RTC Monotonic Counter Low Register */
AnnaBridge 171:3a7713b1edbc 6280 #define RTC_MCLR_MCL_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6281 #define RTC_MCLR_MCL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6282 #define RTC_MCLR_MCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MCLR_MCL_SHIFT)) & RTC_MCLR_MCL_MASK)
AnnaBridge 171:3a7713b1edbc 6283
AnnaBridge 171:3a7713b1edbc 6284 /*! @name MCHR - RTC Monotonic Counter High Register */
AnnaBridge 171:3a7713b1edbc 6285 #define RTC_MCHR_MCH_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6286 #define RTC_MCHR_MCH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6287 #define RTC_MCHR_MCH(x) (((uint32_t)(((uint32_t)(x)) << RTC_MCHR_MCH_SHIFT)) & RTC_MCHR_MCH_MASK)
AnnaBridge 171:3a7713b1edbc 6288
AnnaBridge 171:3a7713b1edbc 6289 /*! @name WAR - RTC Write Access Register */
AnnaBridge 171:3a7713b1edbc 6290 #define RTC_WAR_TSRW_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6291 #define RTC_WAR_TSRW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6292 #define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
AnnaBridge 171:3a7713b1edbc 6293 #define RTC_WAR_TPRW_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6294 #define RTC_WAR_TPRW_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6295 #define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
AnnaBridge 171:3a7713b1edbc 6296 #define RTC_WAR_TARW_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6297 #define RTC_WAR_TARW_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6298 #define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
AnnaBridge 171:3a7713b1edbc 6299 #define RTC_WAR_TCRW_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6300 #define RTC_WAR_TCRW_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6301 #define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
AnnaBridge 171:3a7713b1edbc 6302 #define RTC_WAR_CRW_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6303 #define RTC_WAR_CRW_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6304 #define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
AnnaBridge 171:3a7713b1edbc 6305 #define RTC_WAR_SRW_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6306 #define RTC_WAR_SRW_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6307 #define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
AnnaBridge 171:3a7713b1edbc 6308 #define RTC_WAR_LRW_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6309 #define RTC_WAR_LRW_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6310 #define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
AnnaBridge 171:3a7713b1edbc 6311 #define RTC_WAR_IERW_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6312 #define RTC_WAR_IERW_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6313 #define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
AnnaBridge 171:3a7713b1edbc 6314 #define RTC_WAR_TTSW_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 6315 #define RTC_WAR_TTSW_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6316 #define RTC_WAR_TTSW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TTSW_SHIFT)) & RTC_WAR_TTSW_MASK)
AnnaBridge 171:3a7713b1edbc 6317 #define RTC_WAR_MERW_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 6318 #define RTC_WAR_MERW_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 6319 #define RTC_WAR_MERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MERW_SHIFT)) & RTC_WAR_MERW_MASK)
AnnaBridge 171:3a7713b1edbc 6320 #define RTC_WAR_MCLW_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 6321 #define RTC_WAR_MCLW_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 6322 #define RTC_WAR_MCLW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCLW_SHIFT)) & RTC_WAR_MCLW_MASK)
AnnaBridge 171:3a7713b1edbc 6323 #define RTC_WAR_MCHW_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 6324 #define RTC_WAR_MCHW_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 6325 #define RTC_WAR_MCHW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCHW_SHIFT)) & RTC_WAR_MCHW_MASK)
AnnaBridge 171:3a7713b1edbc 6326
AnnaBridge 171:3a7713b1edbc 6327 /*! @name RAR - RTC Read Access Register */
AnnaBridge 171:3a7713b1edbc 6328 #define RTC_RAR_TSRR_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6329 #define RTC_RAR_TSRR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6330 #define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
AnnaBridge 171:3a7713b1edbc 6331 #define RTC_RAR_TPRR_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6332 #define RTC_RAR_TPRR_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6333 #define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
AnnaBridge 171:3a7713b1edbc 6334 #define RTC_RAR_TARR_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6335 #define RTC_RAR_TARR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6336 #define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
AnnaBridge 171:3a7713b1edbc 6337 #define RTC_RAR_TCRR_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6338 #define RTC_RAR_TCRR_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6339 #define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
AnnaBridge 171:3a7713b1edbc 6340 #define RTC_RAR_CRR_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6341 #define RTC_RAR_CRR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6342 #define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
AnnaBridge 171:3a7713b1edbc 6343 #define RTC_RAR_SRR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6344 #define RTC_RAR_SRR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6345 #define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
AnnaBridge 171:3a7713b1edbc 6346 #define RTC_RAR_LRR_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6347 #define RTC_RAR_LRR_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6348 #define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
AnnaBridge 171:3a7713b1edbc 6349 #define RTC_RAR_IERR_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6350 #define RTC_RAR_IERR_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6351 #define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
AnnaBridge 171:3a7713b1edbc 6352 #define RTC_RAR_TTSR_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 6353 #define RTC_RAR_TTSR_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6354 #define RTC_RAR_TTSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TTSR_SHIFT)) & RTC_RAR_TTSR_MASK)
AnnaBridge 171:3a7713b1edbc 6355 #define RTC_RAR_MERR_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 6356 #define RTC_RAR_MERR_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 6357 #define RTC_RAR_MERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MERR_SHIFT)) & RTC_RAR_MERR_MASK)
AnnaBridge 171:3a7713b1edbc 6358 #define RTC_RAR_MCLR_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 6359 #define RTC_RAR_MCLR_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 6360 #define RTC_RAR_MCLR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCLR_SHIFT)) & RTC_RAR_MCLR_MASK)
AnnaBridge 171:3a7713b1edbc 6361 #define RTC_RAR_MCHR_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 6362 #define RTC_RAR_MCHR_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 6363 #define RTC_RAR_MCHR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCHR_SHIFT)) & RTC_RAR_MCHR_MASK)
AnnaBridge 171:3a7713b1edbc 6364
AnnaBridge 171:3a7713b1edbc 6365
AnnaBridge 171:3a7713b1edbc 6366 /*!
AnnaBridge 171:3a7713b1edbc 6367 * @}
AnnaBridge 171:3a7713b1edbc 6368 */ /* end of group RTC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 6369
AnnaBridge 171:3a7713b1edbc 6370
AnnaBridge 171:3a7713b1edbc 6371 /* RTC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 6372 /** Peripheral RTC base address */
AnnaBridge 171:3a7713b1edbc 6373 #define RTC_BASE (0x4003D000u)
AnnaBridge 171:3a7713b1edbc 6374 /** Peripheral RTC base pointer */
AnnaBridge 171:3a7713b1edbc 6375 #define RTC ((RTC_Type *)RTC_BASE)
AnnaBridge 171:3a7713b1edbc 6376 /** Array initializer of RTC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 6377 #define RTC_BASE_ADDRS { RTC_BASE }
AnnaBridge 171:3a7713b1edbc 6378 /** Array initializer of RTC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 6379 #define RTC_BASE_PTRS { RTC }
AnnaBridge 171:3a7713b1edbc 6380 /** Interrupt vectors for the RTC peripheral type */
AnnaBridge 171:3a7713b1edbc 6381 #define RTC_IRQS { RTC_IRQn }
AnnaBridge 171:3a7713b1edbc 6382 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
AnnaBridge 171:3a7713b1edbc 6383
AnnaBridge 171:3a7713b1edbc 6384 /*!
AnnaBridge 171:3a7713b1edbc 6385 * @}
AnnaBridge 171:3a7713b1edbc 6386 */ /* end of group RTC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 6387
AnnaBridge 171:3a7713b1edbc 6388
AnnaBridge 171:3a7713b1edbc 6389 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6390 -- SIM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6391 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6392
AnnaBridge 171:3a7713b1edbc 6393 /*!
AnnaBridge 171:3a7713b1edbc 6394 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6395 * @{
AnnaBridge 171:3a7713b1edbc 6396 */
AnnaBridge 171:3a7713b1edbc 6397
AnnaBridge 171:3a7713b1edbc 6398 /** SIM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 6399 typedef struct {
AnnaBridge 171:3a7713b1edbc 6400 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 6401 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 6402 uint8_t RESERVED_0[4092];
AnnaBridge 171:3a7713b1edbc 6403 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
AnnaBridge 171:3a7713b1edbc 6404 uint8_t RESERVED_1[4];
AnnaBridge 171:3a7713b1edbc 6405 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
AnnaBridge 171:3a7713b1edbc 6406 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
AnnaBridge 171:3a7713b1edbc 6407 uint8_t RESERVED_2[4];
AnnaBridge 171:3a7713b1edbc 6408 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
AnnaBridge 171:3a7713b1edbc 6409 uint8_t RESERVED_3[8];
AnnaBridge 171:3a7713b1edbc 6410 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
AnnaBridge 171:3a7713b1edbc 6411 uint8_t RESERVED_4[12];
AnnaBridge 171:3a7713b1edbc 6412 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
AnnaBridge 171:3a7713b1edbc 6413 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
AnnaBridge 171:3a7713b1edbc 6414 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
AnnaBridge 171:3a7713b1edbc 6415 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
AnnaBridge 171:3a7713b1edbc 6416 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
AnnaBridge 171:3a7713b1edbc 6417 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
AnnaBridge 171:3a7713b1edbc 6418 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
AnnaBridge 171:3a7713b1edbc 6419 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
AnnaBridge 171:3a7713b1edbc 6420 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
AnnaBridge 171:3a7713b1edbc 6421 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
AnnaBridge 171:3a7713b1edbc 6422 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
AnnaBridge 171:3a7713b1edbc 6423 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
AnnaBridge 171:3a7713b1edbc 6424 } SIM_Type;
AnnaBridge 171:3a7713b1edbc 6425
AnnaBridge 171:3a7713b1edbc 6426 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6427 -- SIM Register Masks
AnnaBridge 171:3a7713b1edbc 6428 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6429
AnnaBridge 171:3a7713b1edbc 6430 /*!
AnnaBridge 171:3a7713b1edbc 6431 * @addtogroup SIM_Register_Masks SIM Register Masks
AnnaBridge 171:3a7713b1edbc 6432 * @{
AnnaBridge 171:3a7713b1edbc 6433 */
AnnaBridge 171:3a7713b1edbc 6434
AnnaBridge 171:3a7713b1edbc 6435 /*! @name SOPT1 - System Options Register 1 */
AnnaBridge 171:3a7713b1edbc 6436 #define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 6437 #define SIM_SOPT1_RAMSIZE_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6438 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 6439 #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 6440 #define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 6441 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
AnnaBridge 171:3a7713b1edbc 6442 #define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 6443 #define SIM_SOPT1_USBVSTBY_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 6444 #define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
AnnaBridge 171:3a7713b1edbc 6445 #define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 6446 #define SIM_SOPT1_USBSSTBY_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 6447 #define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
AnnaBridge 171:3a7713b1edbc 6448 #define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 6449 #define SIM_SOPT1_USBREGEN_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 6450 #define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
AnnaBridge 171:3a7713b1edbc 6451
AnnaBridge 171:3a7713b1edbc 6452 /*! @name SOPT1CFG - SOPT1 Configuration Register */
AnnaBridge 171:3a7713b1edbc 6453 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 6454 #define SIM_SOPT1CFG_URWE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6455 #define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
AnnaBridge 171:3a7713b1edbc 6456 #define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 6457 #define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 6458 #define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
AnnaBridge 171:3a7713b1edbc 6459 #define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 6460 #define SIM_SOPT1CFG_USSWE_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 6461 #define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
AnnaBridge 171:3a7713b1edbc 6462
AnnaBridge 171:3a7713b1edbc 6463 /*! @name SOPT2 - System Options Register 2 */
AnnaBridge 171:3a7713b1edbc 6464 #define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6465 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6466 #define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 6467 #define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
AnnaBridge 171:3a7713b1edbc 6468 #define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6469 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 6470 #define SIM_SOPT2_PTD7PAD_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 6471 #define SIM_SOPT2_PTD7PAD_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 6472 #define SIM_SOPT2_PTD7PAD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PTD7PAD_SHIFT)) & SIM_SOPT2_PTD7PAD_MASK)
AnnaBridge 171:3a7713b1edbc 6473 #define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 6474 #define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6475 #define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 6476 #define SIM_SOPT2_PLLFLLSEL_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 6477 #define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6478 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
AnnaBridge 171:3a7713b1edbc 6479 #define SIM_SOPT2_USBSRC_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 6480 #define SIM_SOPT2_USBSRC_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 6481 #define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
AnnaBridge 171:3a7713b1edbc 6482
AnnaBridge 171:3a7713b1edbc 6483 /*! @name SOPT4 - System Options Register 4 */
AnnaBridge 171:3a7713b1edbc 6484 #define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6485 #define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6486 #define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
AnnaBridge 171:3a7713b1edbc 6487 #define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6488 #define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6489 #define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
AnnaBridge 171:3a7713b1edbc 6490 #define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6491 #define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6492 #define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
AnnaBridge 171:3a7713b1edbc 6493 #define SIM_SOPT4_FTM2FLT0_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 6494 #define SIM_SOPT4_FTM2FLT0_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6495 #define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
AnnaBridge 171:3a7713b1edbc 6496 #define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 6497 #define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 6498 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 6499 #define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U)
AnnaBridge 171:3a7713b1edbc 6500 #define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 6501 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 6502 #define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 6503 #define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6504 #define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 6505 #define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 6506 #define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 6507 #define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 6508 #define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 6509 #define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 6510 #define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 6511 #define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 6512 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 6513 #define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 6514 #define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 6515 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 6516 #define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
AnnaBridge 171:3a7713b1edbc 6517
AnnaBridge 171:3a7713b1edbc 6518 /*! @name SOPT5 - System Options Register 5 */
AnnaBridge 171:3a7713b1edbc 6519 #define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 6520 #define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6521 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 6522 #define SIM_SOPT5_UART0RXSRC_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 6523 #define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6524 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 6525 #define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 6526 #define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6527 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 6528 #define SIM_SOPT5_UART1RXSRC_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 6529 #define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6530 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 6531
AnnaBridge 171:3a7713b1edbc 6532 /*! @name SOPT7 - System Options Register 7 */
AnnaBridge 171:3a7713b1edbc 6533 #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 6534 #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6535 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 6536 #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6537 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6538 #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 6539 #define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6540 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6541 #define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
AnnaBridge 171:3a7713b1edbc 6542
AnnaBridge 171:3a7713b1edbc 6543 /*! @name SDID - System Device Identification Register */
AnnaBridge 171:3a7713b1edbc 6544 #define SIM_SDID_PINID_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 6545 #define SIM_SDID_PINID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6546 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
AnnaBridge 171:3a7713b1edbc 6547 #define SIM_SDID_FAMID_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 6548 #define SIM_SDID_FAMID_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6549 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
AnnaBridge 171:3a7713b1edbc 6550 #define SIM_SDID_DIEID_MASK (0xF80U)
AnnaBridge 171:3a7713b1edbc 6551 #define SIM_SDID_DIEID_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6552 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
AnnaBridge 171:3a7713b1edbc 6553 #define SIM_SDID_REVID_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 6554 #define SIM_SDID_REVID_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6555 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
AnnaBridge 171:3a7713b1edbc 6556
AnnaBridge 171:3a7713b1edbc 6557 /*! @name SCGC4 - System Clock Gating Control Register 4 */
AnnaBridge 171:3a7713b1edbc 6558 #define SIM_SCGC4_EWM_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6559 #define SIM_SCGC4_EWM_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6560 #define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
AnnaBridge 171:3a7713b1edbc 6561 #define SIM_SCGC4_CMT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6562 #define SIM_SCGC4_CMT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6563 #define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
AnnaBridge 171:3a7713b1edbc 6564 #define SIM_SCGC4_I2C0_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6565 #define SIM_SCGC4_I2C0_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6566 #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
AnnaBridge 171:3a7713b1edbc 6567 #define SIM_SCGC4_I2C1_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6568 #define SIM_SCGC4_I2C1_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6569 #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
AnnaBridge 171:3a7713b1edbc 6570 #define SIM_SCGC4_UART0_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 6571 #define SIM_SCGC4_UART0_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 6572 #define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
AnnaBridge 171:3a7713b1edbc 6573 #define SIM_SCGC4_UART1_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 6574 #define SIM_SCGC4_UART1_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 6575 #define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
AnnaBridge 171:3a7713b1edbc 6576 #define SIM_SCGC4_UART2_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 6577 #define SIM_SCGC4_UART2_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6578 #define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
AnnaBridge 171:3a7713b1edbc 6579 #define SIM_SCGC4_UART3_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 6580 #define SIM_SCGC4_UART3_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 6581 #define SIM_SCGC4_UART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
AnnaBridge 171:3a7713b1edbc 6582 #define SIM_SCGC4_USBOTG_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 6583 #define SIM_SCGC4_USBOTG_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 6584 #define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
AnnaBridge 171:3a7713b1edbc 6585 #define SIM_SCGC4_CMP_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 6586 #define SIM_SCGC4_CMP_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 6587 #define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
AnnaBridge 171:3a7713b1edbc 6588 #define SIM_SCGC4_VREF_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 6589 #define SIM_SCGC4_VREF_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 6590 #define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
AnnaBridge 171:3a7713b1edbc 6591
AnnaBridge 171:3a7713b1edbc 6592 /*! @name SCGC5 - System Clock Gating Control Register 5 */
AnnaBridge 171:3a7713b1edbc 6593 #define SIM_SCGC5_LPTMR_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6594 #define SIM_SCGC5_LPTMR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6595 #define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
AnnaBridge 171:3a7713b1edbc 6596 #define SIM_SCGC5_PORTA_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 6597 #define SIM_SCGC5_PORTA_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 6598 #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
AnnaBridge 171:3a7713b1edbc 6599 #define SIM_SCGC5_PORTB_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 6600 #define SIM_SCGC5_PORTB_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 6601 #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
AnnaBridge 171:3a7713b1edbc 6602 #define SIM_SCGC5_PORTC_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 6603 #define SIM_SCGC5_PORTC_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 6604 #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
AnnaBridge 171:3a7713b1edbc 6605 #define SIM_SCGC5_PORTD_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 6606 #define SIM_SCGC5_PORTD_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6607 #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
AnnaBridge 171:3a7713b1edbc 6608 #define SIM_SCGC5_PORTE_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 6609 #define SIM_SCGC5_PORTE_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 6610 #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
AnnaBridge 171:3a7713b1edbc 6611
AnnaBridge 171:3a7713b1edbc 6612 /*! @name SCGC6 - System Clock Gating Control Register 6 */
AnnaBridge 171:3a7713b1edbc 6613 #define SIM_SCGC6_FTFL_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6614 #define SIM_SCGC6_FTFL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6615 #define SIM_SCGC6_FTFL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTFL_SHIFT)) & SIM_SCGC6_FTFL_MASK)
AnnaBridge 171:3a7713b1edbc 6616 #define SIM_SCGC6_DMAMUX_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6617 #define SIM_SCGC6_DMAMUX_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6618 #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
AnnaBridge 171:3a7713b1edbc 6619 #define SIM_SCGC6_RNGA_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 6620 #define SIM_SCGC6_RNGA_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 6621 #define SIM_SCGC6_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK)
AnnaBridge 171:3a7713b1edbc 6622 #define SIM_SCGC6_SPI0_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 6623 #define SIM_SCGC6_SPI0_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6624 #define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
AnnaBridge 171:3a7713b1edbc 6625 #define SIM_SCGC6_SPI1_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 6626 #define SIM_SCGC6_SPI1_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 6627 #define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
AnnaBridge 171:3a7713b1edbc 6628 #define SIM_SCGC6_I2S_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 6629 #define SIM_SCGC6_I2S_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 6630 #define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
AnnaBridge 171:3a7713b1edbc 6631 #define SIM_SCGC6_CRC_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 6632 #define SIM_SCGC6_CRC_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 6633 #define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
AnnaBridge 171:3a7713b1edbc 6634 #define SIM_SCGC6_USBDCD_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 6635 #define SIM_SCGC6_USBDCD_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 6636 #define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
AnnaBridge 171:3a7713b1edbc 6637 #define SIM_SCGC6_PDB_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 6638 #define SIM_SCGC6_PDB_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 6639 #define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
AnnaBridge 171:3a7713b1edbc 6640 #define SIM_SCGC6_PIT_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 6641 #define SIM_SCGC6_PIT_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 6642 #define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
AnnaBridge 171:3a7713b1edbc 6643 #define SIM_SCGC6_FTM0_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 6644 #define SIM_SCGC6_FTM0_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6645 #define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
AnnaBridge 171:3a7713b1edbc 6646 #define SIM_SCGC6_FTM1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 6647 #define SIM_SCGC6_FTM1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 6648 #define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
AnnaBridge 171:3a7713b1edbc 6649 #define SIM_SCGC6_FTM2_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 6650 #define SIM_SCGC6_FTM2_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 6651 #define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
AnnaBridge 171:3a7713b1edbc 6652 #define SIM_SCGC6_ADC0_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 6653 #define SIM_SCGC6_ADC0_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 6654 #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
AnnaBridge 171:3a7713b1edbc 6655 #define SIM_SCGC6_RTC_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 6656 #define SIM_SCGC6_RTC_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 6657 #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
AnnaBridge 171:3a7713b1edbc 6658
AnnaBridge 171:3a7713b1edbc 6659 /*! @name SCGC7 - System Clock Gating Control Register 7 */
AnnaBridge 171:3a7713b1edbc 6660 #define SIM_SCGC7_DMA_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6661 #define SIM_SCGC7_DMA_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6662 #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
AnnaBridge 171:3a7713b1edbc 6663
AnnaBridge 171:3a7713b1edbc 6664 /*! @name CLKDIV1 - System Clock Divider Register 1 */
AnnaBridge 171:3a7713b1edbc 6665 #define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 6666 #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6667 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
AnnaBridge 171:3a7713b1edbc 6668 #define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 6669 #define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6670 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
AnnaBridge 171:3a7713b1edbc 6671 #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 6672 #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 6673 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
AnnaBridge 171:3a7713b1edbc 6674
AnnaBridge 171:3a7713b1edbc 6675 /*! @name CLKDIV2 - System Clock Divider Register 2 */
AnnaBridge 171:3a7713b1edbc 6676 #define SIM_CLKDIV2_USBFRAC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6677 #define SIM_CLKDIV2_USBFRAC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6678 #define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
AnnaBridge 171:3a7713b1edbc 6679 #define SIM_CLKDIV2_USBDIV_MASK (0xEU)
AnnaBridge 171:3a7713b1edbc 6680 #define SIM_CLKDIV2_USBDIV_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6681 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
AnnaBridge 171:3a7713b1edbc 6682
AnnaBridge 171:3a7713b1edbc 6683 /*! @name FCFG1 - Flash Configuration Register 1 */
AnnaBridge 171:3a7713b1edbc 6684 #define SIM_FCFG1_FLASHDIS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6685 #define SIM_FCFG1_FLASHDIS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6686 #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
AnnaBridge 171:3a7713b1edbc 6687 #define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6688 #define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6689 #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
AnnaBridge 171:3a7713b1edbc 6690 #define SIM_FCFG1_DEPART_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 6691 #define SIM_FCFG1_DEPART_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6692 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
AnnaBridge 171:3a7713b1edbc 6693 #define SIM_FCFG1_EESIZE_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 6694 #define SIM_FCFG1_EESIZE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6695 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
AnnaBridge 171:3a7713b1edbc 6696 #define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 6697 #define SIM_FCFG1_PFSIZE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6698 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 6699 #define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 6700 #define SIM_FCFG1_NVMSIZE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 6701 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 6702
AnnaBridge 171:3a7713b1edbc 6703 /*! @name FCFG2 - Flash Configuration Register 2 */
AnnaBridge 171:3a7713b1edbc 6704 #define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
AnnaBridge 171:3a7713b1edbc 6705 #define SIM_FCFG2_MAXADDR1_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6706 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
AnnaBridge 171:3a7713b1edbc 6707 #define SIM_FCFG2_PFLSH_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 6708 #define SIM_FCFG2_PFLSH_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 6709 #define SIM_FCFG2_PFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
AnnaBridge 171:3a7713b1edbc 6710 #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
AnnaBridge 171:3a7713b1edbc 6711 #define SIM_FCFG2_MAXADDR0_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6712 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
AnnaBridge 171:3a7713b1edbc 6713 #define SIM_FCFG2_SWAPPFLSH_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 6714 #define SIM_FCFG2_SWAPPFLSH_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 6715 #define SIM_FCFG2_SWAPPFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAPPFLSH_SHIFT)) & SIM_FCFG2_SWAPPFLSH_MASK)
AnnaBridge 171:3a7713b1edbc 6716
AnnaBridge 171:3a7713b1edbc 6717 /*! @name UIDH - Unique Identification Register High */
AnnaBridge 171:3a7713b1edbc 6718 #define SIM_UIDH_UID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6719 #define SIM_UIDH_UID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6720 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
AnnaBridge 171:3a7713b1edbc 6721
AnnaBridge 171:3a7713b1edbc 6722 /*! @name UIDMH - Unique Identification Register Mid-High */
AnnaBridge 171:3a7713b1edbc 6723 #define SIM_UIDMH_UID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6724 #define SIM_UIDMH_UID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6725 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
AnnaBridge 171:3a7713b1edbc 6726
AnnaBridge 171:3a7713b1edbc 6727 /*! @name UIDML - Unique Identification Register Mid Low */
AnnaBridge 171:3a7713b1edbc 6728 #define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6729 #define SIM_UIDML_UID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6730 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
AnnaBridge 171:3a7713b1edbc 6731
AnnaBridge 171:3a7713b1edbc 6732 /*! @name UIDL - Unique Identification Register Low */
AnnaBridge 171:3a7713b1edbc 6733 #define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6734 #define SIM_UIDL_UID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6735 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
AnnaBridge 171:3a7713b1edbc 6736
AnnaBridge 171:3a7713b1edbc 6737
AnnaBridge 171:3a7713b1edbc 6738 /*!
AnnaBridge 171:3a7713b1edbc 6739 * @}
AnnaBridge 171:3a7713b1edbc 6740 */ /* end of group SIM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 6741
AnnaBridge 171:3a7713b1edbc 6742
AnnaBridge 171:3a7713b1edbc 6743 /* SIM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 6744 /** Peripheral SIM base address */
AnnaBridge 171:3a7713b1edbc 6745 #define SIM_BASE (0x40047000u)
AnnaBridge 171:3a7713b1edbc 6746 /** Peripheral SIM base pointer */
AnnaBridge 171:3a7713b1edbc 6747 #define SIM ((SIM_Type *)SIM_BASE)
AnnaBridge 171:3a7713b1edbc 6748 /** Array initializer of SIM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 6749 #define SIM_BASE_ADDRS { SIM_BASE }
AnnaBridge 171:3a7713b1edbc 6750 /** Array initializer of SIM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 6751 #define SIM_BASE_PTRS { SIM }
AnnaBridge 171:3a7713b1edbc 6752
AnnaBridge 171:3a7713b1edbc 6753 /*!
AnnaBridge 171:3a7713b1edbc 6754 * @}
AnnaBridge 171:3a7713b1edbc 6755 */ /* end of group SIM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 6756
AnnaBridge 171:3a7713b1edbc 6757
AnnaBridge 171:3a7713b1edbc 6758 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6759 -- SMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6760 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6761
AnnaBridge 171:3a7713b1edbc 6762 /*!
AnnaBridge 171:3a7713b1edbc 6763 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6764 * @{
AnnaBridge 171:3a7713b1edbc 6765 */
AnnaBridge 171:3a7713b1edbc 6766
AnnaBridge 171:3a7713b1edbc 6767 /** SMC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 6768 typedef struct {
AnnaBridge 171:3a7713b1edbc 6769 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 6770 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 6771 __IO uint8_t VLLSCTRL; /**< VLLS Control register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 6772 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 6773 } SMC_Type;
AnnaBridge 171:3a7713b1edbc 6774
AnnaBridge 171:3a7713b1edbc 6775 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6776 -- SMC Register Masks
AnnaBridge 171:3a7713b1edbc 6777 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6778
AnnaBridge 171:3a7713b1edbc 6779 /*!
AnnaBridge 171:3a7713b1edbc 6780 * @addtogroup SMC_Register_Masks SMC Register Masks
AnnaBridge 171:3a7713b1edbc 6781 * @{
AnnaBridge 171:3a7713b1edbc 6782 */
AnnaBridge 171:3a7713b1edbc 6783
AnnaBridge 171:3a7713b1edbc 6784 /*! @name PMPROT - Power Mode Protection register */
AnnaBridge 171:3a7713b1edbc 6785 #define SMC_PMPROT_AVLLS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6786 #define SMC_PMPROT_AVLLS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6787 #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
AnnaBridge 171:3a7713b1edbc 6788 #define SMC_PMPROT_ALLS_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6789 #define SMC_PMPROT_ALLS_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6790 #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
AnnaBridge 171:3a7713b1edbc 6791 #define SMC_PMPROT_AVLP_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6792 #define SMC_PMPROT_AVLP_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6793 #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
AnnaBridge 171:3a7713b1edbc 6794
AnnaBridge 171:3a7713b1edbc 6795 /*! @name PMCTRL - Power Mode Control register */
AnnaBridge 171:3a7713b1edbc 6796 #define SMC_PMCTRL_STOPM_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 6797 #define SMC_PMCTRL_STOPM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6798 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
AnnaBridge 171:3a7713b1edbc 6799 #define SMC_PMCTRL_STOPA_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6800 #define SMC_PMCTRL_STOPA_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6801 #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
AnnaBridge 171:3a7713b1edbc 6802 #define SMC_PMCTRL_RUNM_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 6803 #define SMC_PMCTRL_RUNM_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6804 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
AnnaBridge 171:3a7713b1edbc 6805 #define SMC_PMCTRL_LPWUI_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6806 #define SMC_PMCTRL_LPWUI_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6807 #define SMC_PMCTRL_LPWUI(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_LPWUI_SHIFT)) & SMC_PMCTRL_LPWUI_MASK)
AnnaBridge 171:3a7713b1edbc 6808
AnnaBridge 171:3a7713b1edbc 6809 /*! @name VLLSCTRL - VLLS Control register */
AnnaBridge 171:3a7713b1edbc 6810 #define SMC_VLLSCTRL_VLLSM_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 6811 #define SMC_VLLSCTRL_VLLSM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6812 #define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_VLLSM_SHIFT)) & SMC_VLLSCTRL_VLLSM_MASK)
AnnaBridge 171:3a7713b1edbc 6813 #define SMC_VLLSCTRL_RAM2PO_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6814 #define SMC_VLLSCTRL_RAM2PO_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6815 #define SMC_VLLSCTRL_RAM2PO(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_RAM2PO_SHIFT)) & SMC_VLLSCTRL_RAM2PO_MASK)
AnnaBridge 171:3a7713b1edbc 6816 #define SMC_VLLSCTRL_PORPO_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6817 #define SMC_VLLSCTRL_PORPO_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6818 #define SMC_VLLSCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_PORPO_SHIFT)) & SMC_VLLSCTRL_PORPO_MASK)
AnnaBridge 171:3a7713b1edbc 6819
AnnaBridge 171:3a7713b1edbc 6820 /*! @name PMSTAT - Power Mode Status register */
AnnaBridge 171:3a7713b1edbc 6821 #define SMC_PMSTAT_PMSTAT_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 6822 #define SMC_PMSTAT_PMSTAT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6823 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
AnnaBridge 171:3a7713b1edbc 6824
AnnaBridge 171:3a7713b1edbc 6825
AnnaBridge 171:3a7713b1edbc 6826 /*!
AnnaBridge 171:3a7713b1edbc 6827 * @}
AnnaBridge 171:3a7713b1edbc 6828 */ /* end of group SMC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 6829
AnnaBridge 171:3a7713b1edbc 6830
AnnaBridge 171:3a7713b1edbc 6831 /* SMC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 6832 /** Peripheral SMC base address */
AnnaBridge 171:3a7713b1edbc 6833 #define SMC_BASE (0x4007E000u)
AnnaBridge 171:3a7713b1edbc 6834 /** Peripheral SMC base pointer */
AnnaBridge 171:3a7713b1edbc 6835 #define SMC ((SMC_Type *)SMC_BASE)
AnnaBridge 171:3a7713b1edbc 6836 /** Array initializer of SMC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 6837 #define SMC_BASE_ADDRS { SMC_BASE }
AnnaBridge 171:3a7713b1edbc 6838 /** Array initializer of SMC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 6839 #define SMC_BASE_PTRS { SMC }
AnnaBridge 171:3a7713b1edbc 6840
AnnaBridge 171:3a7713b1edbc 6841 /*!
AnnaBridge 171:3a7713b1edbc 6842 * @}
AnnaBridge 171:3a7713b1edbc 6843 */ /* end of group SMC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 6844
AnnaBridge 171:3a7713b1edbc 6845
AnnaBridge 171:3a7713b1edbc 6846 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6847 -- SPI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6848 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6849
AnnaBridge 171:3a7713b1edbc 6850 /*!
AnnaBridge 171:3a7713b1edbc 6851 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6852 * @{
AnnaBridge 171:3a7713b1edbc 6853 */
AnnaBridge 171:3a7713b1edbc 6854
AnnaBridge 171:3a7713b1edbc 6855 /** SPI - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 6856 typedef struct {
AnnaBridge 171:3a7713b1edbc 6857 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 6858 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 6859 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 6860 union { /* offset: 0xC */
AnnaBridge 171:3a7713b1edbc 6861 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 6862 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 6863 };
AnnaBridge 171:3a7713b1edbc 6864 uint8_t RESERVED_1[24];
AnnaBridge 171:3a7713b1edbc 6865 __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 6866 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 6867 union { /* offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 6868 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 6869 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 6870 };
AnnaBridge 171:3a7713b1edbc 6871 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 6872 __I uint32_t TXFR0; /**< DSPI Transmit FIFO Registers, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 6873 __I uint32_t TXFR1; /**< DSPI Transmit FIFO Registers, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 6874 __I uint32_t TXFR2; /**< DSPI Transmit FIFO Registers, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 6875 __I uint32_t TXFR3; /**< DSPI Transmit FIFO Registers, offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 6876 uint8_t RESERVED_2[48];
AnnaBridge 171:3a7713b1edbc 6877 __I uint32_t RXFR0; /**< DSPI Receive FIFO Registers, offset: 0x7C */
AnnaBridge 171:3a7713b1edbc 6878 __I uint32_t RXFR1; /**< DSPI Receive FIFO Registers, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 6879 __I uint32_t RXFR2; /**< DSPI Receive FIFO Registers, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 6880 __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 6881 } SPI_Type;
AnnaBridge 171:3a7713b1edbc 6882
AnnaBridge 171:3a7713b1edbc 6883 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6884 -- SPI Register Masks
AnnaBridge 171:3a7713b1edbc 6885 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6886
AnnaBridge 171:3a7713b1edbc 6887 /*!
AnnaBridge 171:3a7713b1edbc 6888 * @addtogroup SPI_Register_Masks SPI Register Masks
AnnaBridge 171:3a7713b1edbc 6889 * @{
AnnaBridge 171:3a7713b1edbc 6890 */
AnnaBridge 171:3a7713b1edbc 6891
AnnaBridge 171:3a7713b1edbc 6892 /*! @name MCR - Module Configuration Register */
AnnaBridge 171:3a7713b1edbc 6893 #define SPI_MCR_HALT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6894 #define SPI_MCR_HALT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6895 #define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
AnnaBridge 171:3a7713b1edbc 6896 #define SPI_MCR_SMPL_PT_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 6897 #define SPI_MCR_SMPL_PT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6898 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
AnnaBridge 171:3a7713b1edbc 6899 #define SPI_MCR_CLR_RXF_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 6900 #define SPI_MCR_CLR_RXF_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 6901 #define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
AnnaBridge 171:3a7713b1edbc 6902 #define SPI_MCR_CLR_TXF_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 6903 #define SPI_MCR_CLR_TXF_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 6904 #define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
AnnaBridge 171:3a7713b1edbc 6905 #define SPI_MCR_DIS_RXF_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 6906 #define SPI_MCR_DIS_RXF_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6907 #define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
AnnaBridge 171:3a7713b1edbc 6908 #define SPI_MCR_DIS_TXF_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 6909 #define SPI_MCR_DIS_TXF_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 6910 #define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
AnnaBridge 171:3a7713b1edbc 6911 #define SPI_MCR_MDIS_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 6912 #define SPI_MCR_MDIS_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 6913 #define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
AnnaBridge 171:3a7713b1edbc 6914 #define SPI_MCR_DOZE_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 6915 #define SPI_MCR_DOZE_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 6916 #define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
AnnaBridge 171:3a7713b1edbc 6917 #define SPI_MCR_PCSIS_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 6918 #define SPI_MCR_PCSIS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6919 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
AnnaBridge 171:3a7713b1edbc 6920 #define SPI_MCR_ROOE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 6921 #define SPI_MCR_ROOE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6922 #define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
AnnaBridge 171:3a7713b1edbc 6923 #define SPI_MCR_MTFE_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 6924 #define SPI_MCR_MTFE_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 6925 #define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
AnnaBridge 171:3a7713b1edbc 6926 #define SPI_MCR_FRZ_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 6927 #define SPI_MCR_FRZ_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 6928 #define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
AnnaBridge 171:3a7713b1edbc 6929 #define SPI_MCR_DCONF_MASK (0x30000000U)
AnnaBridge 171:3a7713b1edbc 6930 #define SPI_MCR_DCONF_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 6931 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
AnnaBridge 171:3a7713b1edbc 6932 #define SPI_MCR_CONT_SCKE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 6933 #define SPI_MCR_CONT_SCKE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 6934 #define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
AnnaBridge 171:3a7713b1edbc 6935 #define SPI_MCR_MSTR_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 6936 #define SPI_MCR_MSTR_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 6937 #define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
AnnaBridge 171:3a7713b1edbc 6938
AnnaBridge 171:3a7713b1edbc 6939 /*! @name TCR - Transfer Count Register */
AnnaBridge 171:3a7713b1edbc 6940 #define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 6941 #define SPI_TCR_SPI_TCNT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6942 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
AnnaBridge 171:3a7713b1edbc 6943
AnnaBridge 171:3a7713b1edbc 6944 /*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
AnnaBridge 171:3a7713b1edbc 6945 #define SPI_CTAR_BR_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 6946 #define SPI_CTAR_BR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6947 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
AnnaBridge 171:3a7713b1edbc 6948 #define SPI_CTAR_DT_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 6949 #define SPI_CTAR_DT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6950 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
AnnaBridge 171:3a7713b1edbc 6951 #define SPI_CTAR_ASC_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 6952 #define SPI_CTAR_ASC_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6953 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
AnnaBridge 171:3a7713b1edbc 6954 #define SPI_CTAR_CSSCK_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 6955 #define SPI_CTAR_CSSCK_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6956 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
AnnaBridge 171:3a7713b1edbc 6957 #define SPI_CTAR_PBR_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 6958 #define SPI_CTAR_PBR_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6959 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
AnnaBridge 171:3a7713b1edbc 6960 #define SPI_CTAR_PDT_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 6961 #define SPI_CTAR_PDT_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 6962 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
AnnaBridge 171:3a7713b1edbc 6963 #define SPI_CTAR_PASC_MASK (0x300000U)
AnnaBridge 171:3a7713b1edbc 6964 #define SPI_CTAR_PASC_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 6965 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
AnnaBridge 171:3a7713b1edbc 6966 #define SPI_CTAR_PCSSCK_MASK (0xC00000U)
AnnaBridge 171:3a7713b1edbc 6967 #define SPI_CTAR_PCSSCK_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 6968 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
AnnaBridge 171:3a7713b1edbc 6969 #define SPI_CTAR_LSBFE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 6970 #define SPI_CTAR_LSBFE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6971 #define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
AnnaBridge 171:3a7713b1edbc 6972 #define SPI_CTAR_CPHA_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 6973 #define SPI_CTAR_CPHA_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 6974 #define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
AnnaBridge 171:3a7713b1edbc 6975 #define SPI_CTAR_CPOL_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 6976 #define SPI_CTAR_CPOL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 6977 #define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
AnnaBridge 171:3a7713b1edbc 6978 #define SPI_CTAR_FMSZ_MASK (0x78000000U)
AnnaBridge 171:3a7713b1edbc 6979 #define SPI_CTAR_FMSZ_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 6980 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
AnnaBridge 171:3a7713b1edbc 6981 #define SPI_CTAR_DBR_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 6982 #define SPI_CTAR_DBR_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 6983 #define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
AnnaBridge 171:3a7713b1edbc 6984
AnnaBridge 171:3a7713b1edbc 6985 /* The count of SPI_CTAR */
AnnaBridge 171:3a7713b1edbc 6986 #define SPI_CTAR_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 6987
AnnaBridge 171:3a7713b1edbc 6988 /*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
AnnaBridge 171:3a7713b1edbc 6989 #define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 6990 #define SPI_CTAR_SLAVE_CPHA_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 6991 #define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
AnnaBridge 171:3a7713b1edbc 6992 #define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 6993 #define SPI_CTAR_SLAVE_CPOL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 6994 #define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
AnnaBridge 171:3a7713b1edbc 6995 #define SPI_CTAR_SLAVE_FMSZ_MASK (0xF8000000U)
AnnaBridge 171:3a7713b1edbc 6996 #define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 6997 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
AnnaBridge 171:3a7713b1edbc 6998
AnnaBridge 171:3a7713b1edbc 6999 /* The count of SPI_CTAR_SLAVE */
AnnaBridge 171:3a7713b1edbc 7000 #define SPI_CTAR_SLAVE_COUNT (1U)
AnnaBridge 171:3a7713b1edbc 7001
AnnaBridge 171:3a7713b1edbc 7002 /*! @name SR - DSPI Status Register */
AnnaBridge 171:3a7713b1edbc 7003 #define SPI_SR_POPNXTPTR_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 7004 #define SPI_SR_POPNXTPTR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7005 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
AnnaBridge 171:3a7713b1edbc 7006 #define SPI_SR_RXCTR_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 7007 #define SPI_SR_RXCTR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7008 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
AnnaBridge 171:3a7713b1edbc 7009 #define SPI_SR_TXNXTPTR_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 7010 #define SPI_SR_TXNXTPTR_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7011 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
AnnaBridge 171:3a7713b1edbc 7012 #define SPI_SR_TXCTR_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 7013 #define SPI_SR_TXCTR_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 7014 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
AnnaBridge 171:3a7713b1edbc 7015 #define SPI_SR_RFDF_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 7016 #define SPI_SR_RFDF_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 7017 #define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
AnnaBridge 171:3a7713b1edbc 7018 #define SPI_SR_RFOF_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 7019 #define SPI_SR_RFOF_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 7020 #define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
AnnaBridge 171:3a7713b1edbc 7021 #define SPI_SR_TFFF_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 7022 #define SPI_SR_TFFF_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 7023 #define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
AnnaBridge 171:3a7713b1edbc 7024 #define SPI_SR_TFUF_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 7025 #define SPI_SR_TFUF_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 7026 #define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
AnnaBridge 171:3a7713b1edbc 7027 #define SPI_SR_EOQF_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 7028 #define SPI_SR_EOQF_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 7029 #define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
AnnaBridge 171:3a7713b1edbc 7030 #define SPI_SR_TXRXS_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 7031 #define SPI_SR_TXRXS_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 7032 #define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
AnnaBridge 171:3a7713b1edbc 7033 #define SPI_SR_TCF_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 7034 #define SPI_SR_TCF_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 7035 #define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
AnnaBridge 171:3a7713b1edbc 7036
AnnaBridge 171:3a7713b1edbc 7037 /*! @name RSER - DMA/Interrupt Request Select and Enable Register */
AnnaBridge 171:3a7713b1edbc 7038 #define SPI_RSER_RFDF_DIRS_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 7039 #define SPI_RSER_RFDF_DIRS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7040 #define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
AnnaBridge 171:3a7713b1edbc 7041 #define SPI_RSER_RFDF_RE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 7042 #define SPI_RSER_RFDF_RE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 7043 #define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 7044 #define SPI_RSER_RFOF_RE_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 7045 #define SPI_RSER_RFOF_RE_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 7046 #define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 7047 #define SPI_RSER_TFFF_DIRS_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 7048 #define SPI_RSER_TFFF_DIRS_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 7049 #define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
AnnaBridge 171:3a7713b1edbc 7050 #define SPI_RSER_TFFF_RE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 7051 #define SPI_RSER_TFFF_RE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 7052 #define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 7053 #define SPI_RSER_TFUF_RE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 7054 #define SPI_RSER_TFUF_RE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 7055 #define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 7056 #define SPI_RSER_EOQF_RE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 7057 #define SPI_RSER_EOQF_RE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 7058 #define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 7059 #define SPI_RSER_TCF_RE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 7060 #define SPI_RSER_TCF_RE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 7061 #define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 7062
AnnaBridge 171:3a7713b1edbc 7063 /*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
AnnaBridge 171:3a7713b1edbc 7064 #define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7065 #define SPI_PUSHR_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7066 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 7067 #define SPI_PUSHR_PCS_MASK (0x3F0000U)
AnnaBridge 171:3a7713b1edbc 7068 #define SPI_PUSHR_PCS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7069 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
AnnaBridge 171:3a7713b1edbc 7070 #define SPI_PUSHR_CTCNT_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 7071 #define SPI_PUSHR_CTCNT_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 7072 #define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
AnnaBridge 171:3a7713b1edbc 7073 #define SPI_PUSHR_EOQ_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 7074 #define SPI_PUSHR_EOQ_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 7075 #define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
AnnaBridge 171:3a7713b1edbc 7076 #define SPI_PUSHR_CTAS_MASK (0x70000000U)
AnnaBridge 171:3a7713b1edbc 7077 #define SPI_PUSHR_CTAS_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 7078 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
AnnaBridge 171:3a7713b1edbc 7079 #define SPI_PUSHR_CONT_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 7080 #define SPI_PUSHR_CONT_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 7081 #define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
AnnaBridge 171:3a7713b1edbc 7082
AnnaBridge 171:3a7713b1edbc 7083 /*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */
AnnaBridge 171:3a7713b1edbc 7084 #define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 7085 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7086 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 7087
AnnaBridge 171:3a7713b1edbc 7088 /*! @name POPR - POP RX FIFO Register */
AnnaBridge 171:3a7713b1edbc 7089 #define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 7090 #define SPI_POPR_RXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7091 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 7092
AnnaBridge 171:3a7713b1edbc 7093 /*! @name TXFR0 - DSPI Transmit FIFO Registers */
AnnaBridge 171:3a7713b1edbc 7094 #define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7095 #define SPI_TXFR0_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7096 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 7097 #define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 7098 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7099 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 7100
AnnaBridge 171:3a7713b1edbc 7101 /*! @name TXFR1 - DSPI Transmit FIFO Registers */
AnnaBridge 171:3a7713b1edbc 7102 #define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7103 #define SPI_TXFR1_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7104 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 7105 #define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 7106 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7107 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 7108
AnnaBridge 171:3a7713b1edbc 7109 /*! @name TXFR2 - DSPI Transmit FIFO Registers */
AnnaBridge 171:3a7713b1edbc 7110 #define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7111 #define SPI_TXFR2_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7112 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 7113 #define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 7114 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7115 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 7116
AnnaBridge 171:3a7713b1edbc 7117 /*! @name TXFR3 - DSPI Transmit FIFO Registers */
AnnaBridge 171:3a7713b1edbc 7118 #define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7119 #define SPI_TXFR3_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7120 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 7121 #define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 7122 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7123 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 7124
AnnaBridge 171:3a7713b1edbc 7125 /*! @name RXFR0 - DSPI Receive FIFO Registers */
AnnaBridge 171:3a7713b1edbc 7126 #define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 7127 #define SPI_RXFR0_RXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7128 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 7129
AnnaBridge 171:3a7713b1edbc 7130 /*! @name RXFR1 - DSPI Receive FIFO Registers */
AnnaBridge 171:3a7713b1edbc 7131 #define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 7132 #define SPI_RXFR1_RXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7133 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 7134
AnnaBridge 171:3a7713b1edbc 7135 /*! @name RXFR2 - DSPI Receive FIFO Registers */
AnnaBridge 171:3a7713b1edbc 7136 #define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 7137 #define SPI_RXFR2_RXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7138 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 7139
AnnaBridge 171:3a7713b1edbc 7140 /*! @name RXFR3 - DSPI Receive FIFO Registers */
AnnaBridge 171:3a7713b1edbc 7141 #define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 7142 #define SPI_RXFR3_RXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7143 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 7144
AnnaBridge 171:3a7713b1edbc 7145
AnnaBridge 171:3a7713b1edbc 7146 /*!
AnnaBridge 171:3a7713b1edbc 7147 * @}
AnnaBridge 171:3a7713b1edbc 7148 */ /* end of group SPI_Register_Masks */
AnnaBridge 171:3a7713b1edbc 7149
AnnaBridge 171:3a7713b1edbc 7150
AnnaBridge 171:3a7713b1edbc 7151 /* SPI - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 7152 /** Peripheral SPI0 base address */
AnnaBridge 171:3a7713b1edbc 7153 #define SPI0_BASE (0x4002C000u)
AnnaBridge 171:3a7713b1edbc 7154 /** Peripheral SPI0 base pointer */
AnnaBridge 171:3a7713b1edbc 7155 #define SPI0 ((SPI_Type *)SPI0_BASE)
AnnaBridge 171:3a7713b1edbc 7156 /** Peripheral SPI1 base address */
AnnaBridge 171:3a7713b1edbc 7157 #define SPI1_BASE (0x4002D000u)
AnnaBridge 171:3a7713b1edbc 7158 /** Peripheral SPI1 base pointer */
AnnaBridge 171:3a7713b1edbc 7159 #define SPI1 ((SPI_Type *)SPI1_BASE)
AnnaBridge 171:3a7713b1edbc 7160 /** Array initializer of SPI peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 7161 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
AnnaBridge 171:3a7713b1edbc 7162 /** Array initializer of SPI peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 7163 #define SPI_BASE_PTRS { SPI0, SPI1 }
AnnaBridge 171:3a7713b1edbc 7164 /** Interrupt vectors for the SPI peripheral type */
AnnaBridge 171:3a7713b1edbc 7165 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
AnnaBridge 171:3a7713b1edbc 7166
AnnaBridge 171:3a7713b1edbc 7167 /*!
AnnaBridge 171:3a7713b1edbc 7168 * @}
AnnaBridge 171:3a7713b1edbc 7169 */ /* end of group SPI_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 7170
AnnaBridge 171:3a7713b1edbc 7171
AnnaBridge 171:3a7713b1edbc 7172 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7173 -- UART Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7174 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7175
AnnaBridge 171:3a7713b1edbc 7176 /*!
AnnaBridge 171:3a7713b1edbc 7177 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7178 * @{
AnnaBridge 171:3a7713b1edbc 7179 */
AnnaBridge 171:3a7713b1edbc 7180
AnnaBridge 171:3a7713b1edbc 7181 /** UART - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 7182 typedef struct {
AnnaBridge 171:3a7713b1edbc 7183 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 7184 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 7185 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 7186 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 7187 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 7188 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 7189 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 7190 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 7191 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 7192 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 7193 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 7194 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 7195 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 7196 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 7197 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
AnnaBridge 171:3a7713b1edbc 7198 uint8_t RESERVED_0[1];
AnnaBridge 171:3a7713b1edbc 7199 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 7200 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
AnnaBridge 171:3a7713b1edbc 7201 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
AnnaBridge 171:3a7713b1edbc 7202 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
AnnaBridge 171:3a7713b1edbc 7203 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 7204 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
AnnaBridge 171:3a7713b1edbc 7205 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
AnnaBridge 171:3a7713b1edbc 7206 uint8_t RESERVED_1[1];
AnnaBridge 171:3a7713b1edbc 7207 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 7208 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
AnnaBridge 171:3a7713b1edbc 7209 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
AnnaBridge 171:3a7713b1edbc 7210 union { /* offset: 0x1B */
AnnaBridge 171:3a7713b1edbc 7211 __IO uint8_t WP7816T0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
AnnaBridge 171:3a7713b1edbc 7212 __IO uint8_t WP7816T1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
AnnaBridge 171:3a7713b1edbc 7213 };
AnnaBridge 171:3a7713b1edbc 7214 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 7215 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
AnnaBridge 171:3a7713b1edbc 7216 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
AnnaBridge 171:3a7713b1edbc 7217 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
AnnaBridge 171:3a7713b1edbc 7218 } UART_Type;
AnnaBridge 171:3a7713b1edbc 7219
AnnaBridge 171:3a7713b1edbc 7220 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7221 -- UART Register Masks
AnnaBridge 171:3a7713b1edbc 7222 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7223
AnnaBridge 171:3a7713b1edbc 7224 /*!
AnnaBridge 171:3a7713b1edbc 7225 * @addtogroup UART_Register_Masks UART Register Masks
AnnaBridge 171:3a7713b1edbc 7226 * @{
AnnaBridge 171:3a7713b1edbc 7227 */
AnnaBridge 171:3a7713b1edbc 7228
AnnaBridge 171:3a7713b1edbc 7229 /*! @name BDH - UART Baud Rate Registers: High */
AnnaBridge 171:3a7713b1edbc 7230 #define UART_BDH_SBR_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 7231 #define UART_BDH_SBR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7232 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
AnnaBridge 171:3a7713b1edbc 7233 #define UART_BDH_RXEDGIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7234 #define UART_BDH_RXEDGIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7235 #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
AnnaBridge 171:3a7713b1edbc 7236 #define UART_BDH_LBKDIE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7237 #define UART_BDH_LBKDIE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7238 #define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
AnnaBridge 171:3a7713b1edbc 7239
AnnaBridge 171:3a7713b1edbc 7240 /*! @name BDL - UART Baud Rate Registers: Low */
AnnaBridge 171:3a7713b1edbc 7241 #define UART_BDL_SBR_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7242 #define UART_BDL_SBR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7243 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
AnnaBridge 171:3a7713b1edbc 7244
AnnaBridge 171:3a7713b1edbc 7245 /*! @name C1 - UART Control Register 1 */
AnnaBridge 171:3a7713b1edbc 7246 #define UART_C1_PT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7247 #define UART_C1_PT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7248 #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
AnnaBridge 171:3a7713b1edbc 7249 #define UART_C1_PE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7250 #define UART_C1_PE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7251 #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
AnnaBridge 171:3a7713b1edbc 7252 #define UART_C1_ILT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7253 #define UART_C1_ILT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7254 #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
AnnaBridge 171:3a7713b1edbc 7255 #define UART_C1_WAKE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7256 #define UART_C1_WAKE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7257 #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
AnnaBridge 171:3a7713b1edbc 7258 #define UART_C1_M_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7259 #define UART_C1_M_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7260 #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
AnnaBridge 171:3a7713b1edbc 7261 #define UART_C1_RSRC_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7262 #define UART_C1_RSRC_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7263 #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
AnnaBridge 171:3a7713b1edbc 7264 #define UART_C1_UARTSWAI_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7265 #define UART_C1_UARTSWAI_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7266 #define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
AnnaBridge 171:3a7713b1edbc 7267 #define UART_C1_LOOPS_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7268 #define UART_C1_LOOPS_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7269 #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
AnnaBridge 171:3a7713b1edbc 7270
AnnaBridge 171:3a7713b1edbc 7271 /*! @name C2 - UART Control Register 2 */
AnnaBridge 171:3a7713b1edbc 7272 #define UART_C2_SBK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7273 #define UART_C2_SBK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7274 #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
AnnaBridge 171:3a7713b1edbc 7275 #define UART_C2_RWU_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7276 #define UART_C2_RWU_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7277 #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
AnnaBridge 171:3a7713b1edbc 7278 #define UART_C2_RE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7279 #define UART_C2_RE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7280 #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
AnnaBridge 171:3a7713b1edbc 7281 #define UART_C2_TE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7282 #define UART_C2_TE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7283 #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
AnnaBridge 171:3a7713b1edbc 7284 #define UART_C2_ILIE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7285 #define UART_C2_ILIE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7286 #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
AnnaBridge 171:3a7713b1edbc 7287 #define UART_C2_RIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7288 #define UART_C2_RIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7289 #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
AnnaBridge 171:3a7713b1edbc 7290 #define UART_C2_TCIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7291 #define UART_C2_TCIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7292 #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
AnnaBridge 171:3a7713b1edbc 7293 #define UART_C2_TIE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7294 #define UART_C2_TIE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7295 #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
AnnaBridge 171:3a7713b1edbc 7296
AnnaBridge 171:3a7713b1edbc 7297 /*! @name S1 - UART Status Register 1 */
AnnaBridge 171:3a7713b1edbc 7298 #define UART_S1_PF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7299 #define UART_S1_PF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7300 #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
AnnaBridge 171:3a7713b1edbc 7301 #define UART_S1_FE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7302 #define UART_S1_FE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7303 #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
AnnaBridge 171:3a7713b1edbc 7304 #define UART_S1_NF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7305 #define UART_S1_NF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7306 #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
AnnaBridge 171:3a7713b1edbc 7307 #define UART_S1_OR_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7308 #define UART_S1_OR_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7309 #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
AnnaBridge 171:3a7713b1edbc 7310 #define UART_S1_IDLE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7311 #define UART_S1_IDLE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7312 #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
AnnaBridge 171:3a7713b1edbc 7313 #define UART_S1_RDRF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7314 #define UART_S1_RDRF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7315 #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
AnnaBridge 171:3a7713b1edbc 7316 #define UART_S1_TC_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7317 #define UART_S1_TC_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7318 #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
AnnaBridge 171:3a7713b1edbc 7319 #define UART_S1_TDRE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7320 #define UART_S1_TDRE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7321 #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
AnnaBridge 171:3a7713b1edbc 7322
AnnaBridge 171:3a7713b1edbc 7323 /*! @name S2 - UART Status Register 2 */
AnnaBridge 171:3a7713b1edbc 7324 #define UART_S2_RAF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7325 #define UART_S2_RAF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7326 #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
AnnaBridge 171:3a7713b1edbc 7327 #define UART_S2_LBKDE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7328 #define UART_S2_LBKDE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7329 #define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
AnnaBridge 171:3a7713b1edbc 7330 #define UART_S2_BRK13_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7331 #define UART_S2_BRK13_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7332 #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
AnnaBridge 171:3a7713b1edbc 7333 #define UART_S2_RWUID_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7334 #define UART_S2_RWUID_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7335 #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
AnnaBridge 171:3a7713b1edbc 7336 #define UART_S2_RXINV_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7337 #define UART_S2_RXINV_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7338 #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
AnnaBridge 171:3a7713b1edbc 7339 #define UART_S2_MSBF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7340 #define UART_S2_MSBF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7341 #define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
AnnaBridge 171:3a7713b1edbc 7342 #define UART_S2_RXEDGIF_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7343 #define UART_S2_RXEDGIF_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7344 #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
AnnaBridge 171:3a7713b1edbc 7345 #define UART_S2_LBKDIF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7346 #define UART_S2_LBKDIF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7347 #define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
AnnaBridge 171:3a7713b1edbc 7348
AnnaBridge 171:3a7713b1edbc 7349 /*! @name C3 - UART Control Register 3 */
AnnaBridge 171:3a7713b1edbc 7350 #define UART_C3_PEIE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7351 #define UART_C3_PEIE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7352 #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
AnnaBridge 171:3a7713b1edbc 7353 #define UART_C3_FEIE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7354 #define UART_C3_FEIE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7355 #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
AnnaBridge 171:3a7713b1edbc 7356 #define UART_C3_NEIE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7357 #define UART_C3_NEIE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7358 #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
AnnaBridge 171:3a7713b1edbc 7359 #define UART_C3_ORIE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7360 #define UART_C3_ORIE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7361 #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
AnnaBridge 171:3a7713b1edbc 7362 #define UART_C3_TXINV_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7363 #define UART_C3_TXINV_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7364 #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
AnnaBridge 171:3a7713b1edbc 7365 #define UART_C3_TXDIR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7366 #define UART_C3_TXDIR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7367 #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
AnnaBridge 171:3a7713b1edbc 7368 #define UART_C3_T8_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7369 #define UART_C3_T8_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7370 #define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
AnnaBridge 171:3a7713b1edbc 7371 #define UART_C3_R8_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7372 #define UART_C3_R8_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7373 #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
AnnaBridge 171:3a7713b1edbc 7374
AnnaBridge 171:3a7713b1edbc 7375 /*! @name D - UART Data Register */
AnnaBridge 171:3a7713b1edbc 7376 #define UART_D_RT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7377 #define UART_D_RT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7378 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
AnnaBridge 171:3a7713b1edbc 7379
AnnaBridge 171:3a7713b1edbc 7380 /*! @name MA1 - UART Match Address Registers 1 */
AnnaBridge 171:3a7713b1edbc 7381 #define UART_MA1_MA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7382 #define UART_MA1_MA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7383 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
AnnaBridge 171:3a7713b1edbc 7384
AnnaBridge 171:3a7713b1edbc 7385 /*! @name MA2 - UART Match Address Registers 2 */
AnnaBridge 171:3a7713b1edbc 7386 #define UART_MA2_MA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7387 #define UART_MA2_MA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7388 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
AnnaBridge 171:3a7713b1edbc 7389
AnnaBridge 171:3a7713b1edbc 7390 /*! @name C4 - UART Control Register 4 */
AnnaBridge 171:3a7713b1edbc 7391 #define UART_C4_BRFA_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 7392 #define UART_C4_BRFA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7393 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
AnnaBridge 171:3a7713b1edbc 7394 #define UART_C4_M10_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7395 #define UART_C4_M10_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7396 #define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
AnnaBridge 171:3a7713b1edbc 7397 #define UART_C4_MAEN2_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7398 #define UART_C4_MAEN2_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7399 #define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
AnnaBridge 171:3a7713b1edbc 7400 #define UART_C4_MAEN1_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7401 #define UART_C4_MAEN1_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7402 #define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
AnnaBridge 171:3a7713b1edbc 7403
AnnaBridge 171:3a7713b1edbc 7404 /*! @name C5 - UART Control Register 5 */
AnnaBridge 171:3a7713b1edbc 7405 #define UART_C5_RDMAS_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7406 #define UART_C5_RDMAS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7407 #define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
AnnaBridge 171:3a7713b1edbc 7408 #define UART_C5_TDMAS_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7409 #define UART_C5_TDMAS_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7410 #define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
AnnaBridge 171:3a7713b1edbc 7411
AnnaBridge 171:3a7713b1edbc 7412 /*! @name ED - UART Extended Data Register */
AnnaBridge 171:3a7713b1edbc 7413 #define UART_ED_PARITYE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7414 #define UART_ED_PARITYE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7415 #define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
AnnaBridge 171:3a7713b1edbc 7416 #define UART_ED_NOISY_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7417 #define UART_ED_NOISY_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7418 #define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
AnnaBridge 171:3a7713b1edbc 7419
AnnaBridge 171:3a7713b1edbc 7420 /*! @name MODEM - UART Modem Register */
AnnaBridge 171:3a7713b1edbc 7421 #define UART_MODEM_TXCTSE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7422 #define UART_MODEM_TXCTSE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7423 #define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
AnnaBridge 171:3a7713b1edbc 7424 #define UART_MODEM_TXRTSE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7425 #define UART_MODEM_TXRTSE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7426 #define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
AnnaBridge 171:3a7713b1edbc 7427 #define UART_MODEM_TXRTSPOL_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7428 #define UART_MODEM_TXRTSPOL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7429 #define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
AnnaBridge 171:3a7713b1edbc 7430 #define UART_MODEM_RXRTSE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7431 #define UART_MODEM_RXRTSE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7432 #define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
AnnaBridge 171:3a7713b1edbc 7433
AnnaBridge 171:3a7713b1edbc 7434 /*! @name IR - UART Infrared Register */
AnnaBridge 171:3a7713b1edbc 7435 #define UART_IR_TNP_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 7436 #define UART_IR_TNP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7437 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
AnnaBridge 171:3a7713b1edbc 7438 #define UART_IR_IREN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7439 #define UART_IR_IREN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7440 #define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
AnnaBridge 171:3a7713b1edbc 7441
AnnaBridge 171:3a7713b1edbc 7442 /*! @name PFIFO - UART FIFO Parameters */
AnnaBridge 171:3a7713b1edbc 7443 #define UART_PFIFO_RXFIFOSIZE_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 7444 #define UART_PFIFO_RXFIFOSIZE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7445 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 7446 #define UART_PFIFO_RXFE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7447 #define UART_PFIFO_RXFE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7448 #define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
AnnaBridge 171:3a7713b1edbc 7449 #define UART_PFIFO_TXFIFOSIZE_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 7450 #define UART_PFIFO_TXFIFOSIZE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7451 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 7452 #define UART_PFIFO_TXFE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7453 #define UART_PFIFO_TXFE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7454 #define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
AnnaBridge 171:3a7713b1edbc 7455
AnnaBridge 171:3a7713b1edbc 7456 /*! @name CFIFO - UART FIFO Control Register */
AnnaBridge 171:3a7713b1edbc 7457 #define UART_CFIFO_RXUFE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7458 #define UART_CFIFO_RXUFE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7459 #define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
AnnaBridge 171:3a7713b1edbc 7460 #define UART_CFIFO_TXOFE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7461 #define UART_CFIFO_TXOFE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7462 #define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
AnnaBridge 171:3a7713b1edbc 7463 #define UART_CFIFO_RXOFE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7464 #define UART_CFIFO_RXOFE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7465 #define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK)
AnnaBridge 171:3a7713b1edbc 7466 #define UART_CFIFO_RXFLUSH_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7467 #define UART_CFIFO_RXFLUSH_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7468 #define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
AnnaBridge 171:3a7713b1edbc 7469 #define UART_CFIFO_TXFLUSH_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7470 #define UART_CFIFO_TXFLUSH_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7471 #define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
AnnaBridge 171:3a7713b1edbc 7472
AnnaBridge 171:3a7713b1edbc 7473 /*! @name SFIFO - UART FIFO Status Register */
AnnaBridge 171:3a7713b1edbc 7474 #define UART_SFIFO_RXUF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7475 #define UART_SFIFO_RXUF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7476 #define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
AnnaBridge 171:3a7713b1edbc 7477 #define UART_SFIFO_TXOF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7478 #define UART_SFIFO_TXOF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7479 #define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
AnnaBridge 171:3a7713b1edbc 7480 #define UART_SFIFO_RXOF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7481 #define UART_SFIFO_RXOF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7482 #define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK)
AnnaBridge 171:3a7713b1edbc 7483 #define UART_SFIFO_RXEMPT_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7484 #define UART_SFIFO_RXEMPT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7485 #define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
AnnaBridge 171:3a7713b1edbc 7486 #define UART_SFIFO_TXEMPT_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7487 #define UART_SFIFO_TXEMPT_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7488 #define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
AnnaBridge 171:3a7713b1edbc 7489
AnnaBridge 171:3a7713b1edbc 7490 /*! @name TWFIFO - UART FIFO Transmit Watermark */
AnnaBridge 171:3a7713b1edbc 7491 #define UART_TWFIFO_TXWATER_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7492 #define UART_TWFIFO_TXWATER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7493 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
AnnaBridge 171:3a7713b1edbc 7494
AnnaBridge 171:3a7713b1edbc 7495 /*! @name TCFIFO - UART FIFO Transmit Count */
AnnaBridge 171:3a7713b1edbc 7496 #define UART_TCFIFO_TXCOUNT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7497 #define UART_TCFIFO_TXCOUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7498 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
AnnaBridge 171:3a7713b1edbc 7499
AnnaBridge 171:3a7713b1edbc 7500 /*! @name RWFIFO - UART FIFO Receive Watermark */
AnnaBridge 171:3a7713b1edbc 7501 #define UART_RWFIFO_RXWATER_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7502 #define UART_RWFIFO_RXWATER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7503 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
AnnaBridge 171:3a7713b1edbc 7504
AnnaBridge 171:3a7713b1edbc 7505 /*! @name RCFIFO - UART FIFO Receive Count */
AnnaBridge 171:3a7713b1edbc 7506 #define UART_RCFIFO_RXCOUNT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7507 #define UART_RCFIFO_RXCOUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7508 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
AnnaBridge 171:3a7713b1edbc 7509
AnnaBridge 171:3a7713b1edbc 7510 /*! @name C7816 - UART 7816 Control Register */
AnnaBridge 171:3a7713b1edbc 7511 #define UART_C7816_ISO_7816E_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7512 #define UART_C7816_ISO_7816E_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7513 #define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
AnnaBridge 171:3a7713b1edbc 7514 #define UART_C7816_TTYPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7515 #define UART_C7816_TTYPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7516 #define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
AnnaBridge 171:3a7713b1edbc 7517 #define UART_C7816_INIT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7518 #define UART_C7816_INIT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7519 #define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
AnnaBridge 171:3a7713b1edbc 7520 #define UART_C7816_ANACK_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7521 #define UART_C7816_ANACK_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7522 #define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
AnnaBridge 171:3a7713b1edbc 7523 #define UART_C7816_ONACK_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7524 #define UART_C7816_ONACK_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7525 #define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
AnnaBridge 171:3a7713b1edbc 7526
AnnaBridge 171:3a7713b1edbc 7527 /*! @name IE7816 - UART 7816 Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 7528 #define UART_IE7816_RXTE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7529 #define UART_IE7816_RXTE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7530 #define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
AnnaBridge 171:3a7713b1edbc 7531 #define UART_IE7816_TXTE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7532 #define UART_IE7816_TXTE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7533 #define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
AnnaBridge 171:3a7713b1edbc 7534 #define UART_IE7816_GTVE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7535 #define UART_IE7816_GTVE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7536 #define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
AnnaBridge 171:3a7713b1edbc 7537 #define UART_IE7816_INITDE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7538 #define UART_IE7816_INITDE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7539 #define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
AnnaBridge 171:3a7713b1edbc 7540 #define UART_IE7816_BWTE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7541 #define UART_IE7816_BWTE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7542 #define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
AnnaBridge 171:3a7713b1edbc 7543 #define UART_IE7816_CWTE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7544 #define UART_IE7816_CWTE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7545 #define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
AnnaBridge 171:3a7713b1edbc 7546 #define UART_IE7816_WTE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7547 #define UART_IE7816_WTE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7548 #define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
AnnaBridge 171:3a7713b1edbc 7549
AnnaBridge 171:3a7713b1edbc 7550 /*! @name IS7816 - UART 7816 Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 7551 #define UART_IS7816_RXT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7552 #define UART_IS7816_RXT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7553 #define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
AnnaBridge 171:3a7713b1edbc 7554 #define UART_IS7816_TXT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7555 #define UART_IS7816_TXT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7556 #define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
AnnaBridge 171:3a7713b1edbc 7557 #define UART_IS7816_GTV_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7558 #define UART_IS7816_GTV_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7559 #define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
AnnaBridge 171:3a7713b1edbc 7560 #define UART_IS7816_INITD_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7561 #define UART_IS7816_INITD_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7562 #define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
AnnaBridge 171:3a7713b1edbc 7563 #define UART_IS7816_BWT_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7564 #define UART_IS7816_BWT_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7565 #define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
AnnaBridge 171:3a7713b1edbc 7566 #define UART_IS7816_CWT_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7567 #define UART_IS7816_CWT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7568 #define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
AnnaBridge 171:3a7713b1edbc 7569 #define UART_IS7816_WT_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7570 #define UART_IS7816_WT_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7571 #define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
AnnaBridge 171:3a7713b1edbc 7572
AnnaBridge 171:3a7713b1edbc 7573 /*! @name WP7816T0 - UART 7816 Wait Parameter Register */
AnnaBridge 171:3a7713b1edbc 7574 #define UART_WP7816T0_WI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7575 #define UART_WP7816T0_WI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7576 #define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T0_WI_SHIFT)) & UART_WP7816T0_WI_MASK)
AnnaBridge 171:3a7713b1edbc 7577
AnnaBridge 171:3a7713b1edbc 7578 /*! @name WP7816T1 - UART 7816 Wait Parameter Register */
AnnaBridge 171:3a7713b1edbc 7579 #define UART_WP7816T1_BWI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 7580 #define UART_WP7816T1_BWI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7581 #define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_BWI_SHIFT)) & UART_WP7816T1_BWI_MASK)
AnnaBridge 171:3a7713b1edbc 7582 #define UART_WP7816T1_CWI_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 7583 #define UART_WP7816T1_CWI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7584 #define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_CWI_SHIFT)) & UART_WP7816T1_CWI_MASK)
AnnaBridge 171:3a7713b1edbc 7585
AnnaBridge 171:3a7713b1edbc 7586 /*! @name WN7816 - UART 7816 Wait N Register */
AnnaBridge 171:3a7713b1edbc 7587 #define UART_WN7816_GTN_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7588 #define UART_WN7816_GTN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7589 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
AnnaBridge 171:3a7713b1edbc 7590
AnnaBridge 171:3a7713b1edbc 7591 /*! @name WF7816 - UART 7816 Wait FD Register */
AnnaBridge 171:3a7713b1edbc 7592 #define UART_WF7816_GTFD_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7593 #define UART_WF7816_GTFD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7594 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
AnnaBridge 171:3a7713b1edbc 7595
AnnaBridge 171:3a7713b1edbc 7596 /*! @name ET7816 - UART 7816 Error Threshold Register */
AnnaBridge 171:3a7713b1edbc 7597 #define UART_ET7816_RXTHRESHOLD_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 7598 #define UART_ET7816_RXTHRESHOLD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7599 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
AnnaBridge 171:3a7713b1edbc 7600 #define UART_ET7816_TXTHRESHOLD_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 7601 #define UART_ET7816_TXTHRESHOLD_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7602 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
AnnaBridge 171:3a7713b1edbc 7603
AnnaBridge 171:3a7713b1edbc 7604 /*! @name TL7816 - UART 7816 Transmit Length Register */
AnnaBridge 171:3a7713b1edbc 7605 #define UART_TL7816_TLEN_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7606 #define UART_TL7816_TLEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7607 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
AnnaBridge 171:3a7713b1edbc 7608
AnnaBridge 171:3a7713b1edbc 7609
AnnaBridge 171:3a7713b1edbc 7610 /*!
AnnaBridge 171:3a7713b1edbc 7611 * @}
AnnaBridge 171:3a7713b1edbc 7612 */ /* end of group UART_Register_Masks */
AnnaBridge 171:3a7713b1edbc 7613
AnnaBridge 171:3a7713b1edbc 7614
AnnaBridge 171:3a7713b1edbc 7615 /* UART - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 7616 /** Peripheral UART0 base address */
AnnaBridge 171:3a7713b1edbc 7617 #define UART0_BASE (0x4006A000u)
AnnaBridge 171:3a7713b1edbc 7618 /** Peripheral UART0 base pointer */
AnnaBridge 171:3a7713b1edbc 7619 #define UART0 ((UART_Type *)UART0_BASE)
AnnaBridge 171:3a7713b1edbc 7620 /** Peripheral UART1 base address */
AnnaBridge 171:3a7713b1edbc 7621 #define UART1_BASE (0x4006B000u)
AnnaBridge 171:3a7713b1edbc 7622 /** Peripheral UART1 base pointer */
AnnaBridge 171:3a7713b1edbc 7623 #define UART1 ((UART_Type *)UART1_BASE)
AnnaBridge 171:3a7713b1edbc 7624 /** Peripheral UART2 base address */
AnnaBridge 171:3a7713b1edbc 7625 #define UART2_BASE (0x4006C000u)
AnnaBridge 171:3a7713b1edbc 7626 /** Peripheral UART2 base pointer */
AnnaBridge 171:3a7713b1edbc 7627 #define UART2 ((UART_Type *)UART2_BASE)
AnnaBridge 171:3a7713b1edbc 7628 /** Array initializer of UART peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 7629 #define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE }
AnnaBridge 171:3a7713b1edbc 7630 /** Array initializer of UART peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 7631 #define UART_BASE_PTRS { UART0, UART1, UART2 }
AnnaBridge 171:3a7713b1edbc 7632 /** Interrupt vectors for the UART peripheral type */
AnnaBridge 171:3a7713b1edbc 7633 #define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn }
AnnaBridge 171:3a7713b1edbc 7634 #define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn }
AnnaBridge 171:3a7713b1edbc 7635
AnnaBridge 171:3a7713b1edbc 7636 /*!
AnnaBridge 171:3a7713b1edbc 7637 * @}
AnnaBridge 171:3a7713b1edbc 7638 */ /* end of group UART_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 7639
AnnaBridge 171:3a7713b1edbc 7640
AnnaBridge 171:3a7713b1edbc 7641 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7642 -- USB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7643 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7644
AnnaBridge 171:3a7713b1edbc 7645 /*!
AnnaBridge 171:3a7713b1edbc 7646 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7647 * @{
AnnaBridge 171:3a7713b1edbc 7648 */
AnnaBridge 171:3a7713b1edbc 7649
AnnaBridge 171:3a7713b1edbc 7650 /** USB - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 7651 typedef struct {
AnnaBridge 171:3a7713b1edbc 7652 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 7653 uint8_t RESERVED_0[3];
AnnaBridge 171:3a7713b1edbc 7654 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 7655 uint8_t RESERVED_1[3];
AnnaBridge 171:3a7713b1edbc 7656 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 7657 uint8_t RESERVED_2[3];
AnnaBridge 171:3a7713b1edbc 7658 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 7659 uint8_t RESERVED_3[3];
AnnaBridge 171:3a7713b1edbc 7660 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 7661 uint8_t RESERVED_4[3];
AnnaBridge 171:3a7713b1edbc 7662 __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 7663 uint8_t RESERVED_5[3];
AnnaBridge 171:3a7713b1edbc 7664 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 7665 uint8_t RESERVED_6[3];
AnnaBridge 171:3a7713b1edbc 7666 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 7667 uint8_t RESERVED_7[99];
AnnaBridge 171:3a7713b1edbc 7668 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 7669 uint8_t RESERVED_8[3];
AnnaBridge 171:3a7713b1edbc 7670 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 7671 uint8_t RESERVED_9[3];
AnnaBridge 171:3a7713b1edbc 7672 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 7673 uint8_t RESERVED_10[3];
AnnaBridge 171:3a7713b1edbc 7674 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 7675 uint8_t RESERVED_11[3];
AnnaBridge 171:3a7713b1edbc 7676 __I uint8_t STAT; /**< Status register, offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 7677 uint8_t RESERVED_12[3];
AnnaBridge 171:3a7713b1edbc 7678 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 7679 uint8_t RESERVED_13[3];
AnnaBridge 171:3a7713b1edbc 7680 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
AnnaBridge 171:3a7713b1edbc 7681 uint8_t RESERVED_14[3];
AnnaBridge 171:3a7713b1edbc 7682 __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
AnnaBridge 171:3a7713b1edbc 7683 uint8_t RESERVED_15[3];
AnnaBridge 171:3a7713b1edbc 7684 __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 7685 uint8_t RESERVED_16[3];
AnnaBridge 171:3a7713b1edbc 7686 __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
AnnaBridge 171:3a7713b1edbc 7687 uint8_t RESERVED_17[3];
AnnaBridge 171:3a7713b1edbc 7688 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
AnnaBridge 171:3a7713b1edbc 7689 uint8_t RESERVED_18[3];
AnnaBridge 171:3a7713b1edbc 7690 __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
AnnaBridge 171:3a7713b1edbc 7691 uint8_t RESERVED_19[3];
AnnaBridge 171:3a7713b1edbc 7692 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
AnnaBridge 171:3a7713b1edbc 7693 uint8_t RESERVED_20[3];
AnnaBridge 171:3a7713b1edbc 7694 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
AnnaBridge 171:3a7713b1edbc 7695 uint8_t RESERVED_21[11];
AnnaBridge 171:3a7713b1edbc 7696 struct { /* offset: 0xC0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 7697 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 7698 uint8_t RESERVED_0[3];
AnnaBridge 171:3a7713b1edbc 7699 } ENDPOINT[16];
AnnaBridge 171:3a7713b1edbc 7700 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
AnnaBridge 171:3a7713b1edbc 7701 uint8_t RESERVED_22[3];
AnnaBridge 171:3a7713b1edbc 7702 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
AnnaBridge 171:3a7713b1edbc 7703 uint8_t RESERVED_23[3];
AnnaBridge 171:3a7713b1edbc 7704 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
AnnaBridge 171:3a7713b1edbc 7705 uint8_t RESERVED_24[3];
AnnaBridge 171:3a7713b1edbc 7706 __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
AnnaBridge 171:3a7713b1edbc 7707 uint8_t RESERVED_25[7];
AnnaBridge 171:3a7713b1edbc 7708 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
AnnaBridge 171:3a7713b1edbc 7709 } USB_Type;
AnnaBridge 171:3a7713b1edbc 7710
AnnaBridge 171:3a7713b1edbc 7711 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7712 -- USB Register Masks
AnnaBridge 171:3a7713b1edbc 7713 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7714
AnnaBridge 171:3a7713b1edbc 7715 /*!
AnnaBridge 171:3a7713b1edbc 7716 * @addtogroup USB_Register_Masks USB Register Masks
AnnaBridge 171:3a7713b1edbc 7717 * @{
AnnaBridge 171:3a7713b1edbc 7718 */
AnnaBridge 171:3a7713b1edbc 7719
AnnaBridge 171:3a7713b1edbc 7720 /*! @name PERID - Peripheral ID register */
AnnaBridge 171:3a7713b1edbc 7721 #define USB_PERID_ID_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 7722 #define USB_PERID_ID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7723 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
AnnaBridge 171:3a7713b1edbc 7724
AnnaBridge 171:3a7713b1edbc 7725 /*! @name IDCOMP - Peripheral ID Complement register */
AnnaBridge 171:3a7713b1edbc 7726 #define USB_IDCOMP_NID_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 7727 #define USB_IDCOMP_NID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7728 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
AnnaBridge 171:3a7713b1edbc 7729
AnnaBridge 171:3a7713b1edbc 7730 /*! @name REV - Peripheral Revision register */
AnnaBridge 171:3a7713b1edbc 7731 #define USB_REV_REV_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7732 #define USB_REV_REV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7733 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
AnnaBridge 171:3a7713b1edbc 7734
AnnaBridge 171:3a7713b1edbc 7735 /*! @name ADDINFO - Peripheral Additional Info register */
AnnaBridge 171:3a7713b1edbc 7736 #define USB_ADDINFO_IEHOST_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7737 #define USB_ADDINFO_IEHOST_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7738 #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
AnnaBridge 171:3a7713b1edbc 7739 #define USB_ADDINFO_IRQNUM_MASK (0xF8U)
AnnaBridge 171:3a7713b1edbc 7740 #define USB_ADDINFO_IRQNUM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7741 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK)
AnnaBridge 171:3a7713b1edbc 7742
AnnaBridge 171:3a7713b1edbc 7743 /*! @name OTGISTAT - OTG Interrupt Status register */
AnnaBridge 171:3a7713b1edbc 7744 #define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7745 #define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7746 #define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
AnnaBridge 171:3a7713b1edbc 7747 #define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7748 #define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7749 #define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
AnnaBridge 171:3a7713b1edbc 7750 #define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7751 #define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7752 #define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
AnnaBridge 171:3a7713b1edbc 7753 #define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7754 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7755 #define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
AnnaBridge 171:3a7713b1edbc 7756 #define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7757 #define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7758 #define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
AnnaBridge 171:3a7713b1edbc 7759 #define USB_OTGISTAT_IDCHG_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7760 #define USB_OTGISTAT_IDCHG_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7761 #define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
AnnaBridge 171:3a7713b1edbc 7762
AnnaBridge 171:3a7713b1edbc 7763 /*! @name OTGICR - OTG Interrupt Control Register */
AnnaBridge 171:3a7713b1edbc 7764 #define USB_OTGICR_AVBUSEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7765 #define USB_OTGICR_AVBUSEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7766 #define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
AnnaBridge 171:3a7713b1edbc 7767 #define USB_OTGICR_BSESSEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7768 #define USB_OTGICR_BSESSEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7769 #define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
AnnaBridge 171:3a7713b1edbc 7770 #define USB_OTGICR_SESSVLDEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7771 #define USB_OTGICR_SESSVLDEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7772 #define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
AnnaBridge 171:3a7713b1edbc 7773 #define USB_OTGICR_LINESTATEEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7774 #define USB_OTGICR_LINESTATEEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7775 #define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
AnnaBridge 171:3a7713b1edbc 7776 #define USB_OTGICR_ONEMSECEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7777 #define USB_OTGICR_ONEMSECEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7778 #define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
AnnaBridge 171:3a7713b1edbc 7779 #define USB_OTGICR_IDEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7780 #define USB_OTGICR_IDEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7781 #define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
AnnaBridge 171:3a7713b1edbc 7782
AnnaBridge 171:3a7713b1edbc 7783 /*! @name OTGSTAT - OTG Status register */
AnnaBridge 171:3a7713b1edbc 7784 #define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7785 #define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7786 #define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
AnnaBridge 171:3a7713b1edbc 7787 #define USB_OTGSTAT_BSESSEND_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7788 #define USB_OTGSTAT_BSESSEND_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7789 #define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
AnnaBridge 171:3a7713b1edbc 7790 #define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7791 #define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7792 #define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
AnnaBridge 171:3a7713b1edbc 7793 #define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7794 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7795 #define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
AnnaBridge 171:3a7713b1edbc 7796 #define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7797 #define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7798 #define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
AnnaBridge 171:3a7713b1edbc 7799 #define USB_OTGSTAT_ID_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7800 #define USB_OTGSTAT_ID_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7801 #define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
AnnaBridge 171:3a7713b1edbc 7802
AnnaBridge 171:3a7713b1edbc 7803 /*! @name OTGCTL - OTG Control register */
AnnaBridge 171:3a7713b1edbc 7804 #define USB_OTGCTL_OTGEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7805 #define USB_OTGCTL_OTGEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7806 #define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
AnnaBridge 171:3a7713b1edbc 7807 #define USB_OTGCTL_DMLOW_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7808 #define USB_OTGCTL_DMLOW_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7809 #define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
AnnaBridge 171:3a7713b1edbc 7810 #define USB_OTGCTL_DPLOW_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7811 #define USB_OTGCTL_DPLOW_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7812 #define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
AnnaBridge 171:3a7713b1edbc 7813 #define USB_OTGCTL_DPHIGH_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7814 #define USB_OTGCTL_DPHIGH_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7815 #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
AnnaBridge 171:3a7713b1edbc 7816
AnnaBridge 171:3a7713b1edbc 7817 /*! @name ISTAT - Interrupt Status register */
AnnaBridge 171:3a7713b1edbc 7818 #define USB_ISTAT_USBRST_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7819 #define USB_ISTAT_USBRST_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7820 #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
AnnaBridge 171:3a7713b1edbc 7821 #define USB_ISTAT_ERROR_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7822 #define USB_ISTAT_ERROR_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7823 #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
AnnaBridge 171:3a7713b1edbc 7824 #define USB_ISTAT_SOFTOK_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7825 #define USB_ISTAT_SOFTOK_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7826 #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
AnnaBridge 171:3a7713b1edbc 7827 #define USB_ISTAT_TOKDNE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7828 #define USB_ISTAT_TOKDNE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7829 #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
AnnaBridge 171:3a7713b1edbc 7830 #define USB_ISTAT_SLEEP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7831 #define USB_ISTAT_SLEEP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7832 #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
AnnaBridge 171:3a7713b1edbc 7833 #define USB_ISTAT_RESUME_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7834 #define USB_ISTAT_RESUME_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7835 #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
AnnaBridge 171:3a7713b1edbc 7836 #define USB_ISTAT_ATTACH_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7837 #define USB_ISTAT_ATTACH_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7838 #define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
AnnaBridge 171:3a7713b1edbc 7839 #define USB_ISTAT_STALL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7840 #define USB_ISTAT_STALL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7841 #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
AnnaBridge 171:3a7713b1edbc 7842
AnnaBridge 171:3a7713b1edbc 7843 /*! @name INTEN - Interrupt Enable register */
AnnaBridge 171:3a7713b1edbc 7844 #define USB_INTEN_USBRSTEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7845 #define USB_INTEN_USBRSTEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7846 #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
AnnaBridge 171:3a7713b1edbc 7847 #define USB_INTEN_ERROREN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7848 #define USB_INTEN_ERROREN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7849 #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
AnnaBridge 171:3a7713b1edbc 7850 #define USB_INTEN_SOFTOKEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7851 #define USB_INTEN_SOFTOKEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7852 #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
AnnaBridge 171:3a7713b1edbc 7853 #define USB_INTEN_TOKDNEEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7854 #define USB_INTEN_TOKDNEEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7855 #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
AnnaBridge 171:3a7713b1edbc 7856 #define USB_INTEN_SLEEPEN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7857 #define USB_INTEN_SLEEPEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7858 #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
AnnaBridge 171:3a7713b1edbc 7859 #define USB_INTEN_RESUMEEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7860 #define USB_INTEN_RESUMEEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7861 #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
AnnaBridge 171:3a7713b1edbc 7862 #define USB_INTEN_ATTACHEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7863 #define USB_INTEN_ATTACHEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7864 #define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
AnnaBridge 171:3a7713b1edbc 7865 #define USB_INTEN_STALLEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7866 #define USB_INTEN_STALLEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7867 #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
AnnaBridge 171:3a7713b1edbc 7868
AnnaBridge 171:3a7713b1edbc 7869 /*! @name ERRSTAT - Error Interrupt Status register */
AnnaBridge 171:3a7713b1edbc 7870 #define USB_ERRSTAT_PIDERR_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7871 #define USB_ERRSTAT_PIDERR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7872 #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
AnnaBridge 171:3a7713b1edbc 7873 #define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7874 #define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7875 #define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
AnnaBridge 171:3a7713b1edbc 7876 #define USB_ERRSTAT_CRC16_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7877 #define USB_ERRSTAT_CRC16_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7878 #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
AnnaBridge 171:3a7713b1edbc 7879 #define USB_ERRSTAT_DFN8_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7880 #define USB_ERRSTAT_DFN8_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7881 #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
AnnaBridge 171:3a7713b1edbc 7882 #define USB_ERRSTAT_BTOERR_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7883 #define USB_ERRSTAT_BTOERR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7884 #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
AnnaBridge 171:3a7713b1edbc 7885 #define USB_ERRSTAT_DMAERR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7886 #define USB_ERRSTAT_DMAERR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7887 #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
AnnaBridge 171:3a7713b1edbc 7888 #define USB_ERRSTAT_BTSERR_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7889 #define USB_ERRSTAT_BTSERR_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7890 #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
AnnaBridge 171:3a7713b1edbc 7891
AnnaBridge 171:3a7713b1edbc 7892 /*! @name ERREN - Error Interrupt Enable register */
AnnaBridge 171:3a7713b1edbc 7893 #define USB_ERREN_PIDERREN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7894 #define USB_ERREN_PIDERREN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7895 #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
AnnaBridge 171:3a7713b1edbc 7896 #define USB_ERREN_CRC5EOFEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7897 #define USB_ERREN_CRC5EOFEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7898 #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
AnnaBridge 171:3a7713b1edbc 7899 #define USB_ERREN_CRC16EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7900 #define USB_ERREN_CRC16EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7901 #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
AnnaBridge 171:3a7713b1edbc 7902 #define USB_ERREN_DFN8EN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7903 #define USB_ERREN_DFN8EN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7904 #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
AnnaBridge 171:3a7713b1edbc 7905 #define USB_ERREN_BTOERREN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7906 #define USB_ERREN_BTOERREN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7907 #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
AnnaBridge 171:3a7713b1edbc 7908 #define USB_ERREN_DMAERREN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7909 #define USB_ERREN_DMAERREN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7910 #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
AnnaBridge 171:3a7713b1edbc 7911 #define USB_ERREN_BTSERREN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7912 #define USB_ERREN_BTSERREN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7913 #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
AnnaBridge 171:3a7713b1edbc 7914
AnnaBridge 171:3a7713b1edbc 7915 /*! @name STAT - Status register */
AnnaBridge 171:3a7713b1edbc 7916 #define USB_STAT_ODD_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7917 #define USB_STAT_ODD_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7918 #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
AnnaBridge 171:3a7713b1edbc 7919 #define USB_STAT_TX_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7920 #define USB_STAT_TX_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7921 #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
AnnaBridge 171:3a7713b1edbc 7922 #define USB_STAT_ENDP_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 7923 #define USB_STAT_ENDP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7924 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
AnnaBridge 171:3a7713b1edbc 7925
AnnaBridge 171:3a7713b1edbc 7926 /*! @name CTL - Control register */
AnnaBridge 171:3a7713b1edbc 7927 #define USB_CTL_USBENSOFEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7928 #define USB_CTL_USBENSOFEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7929 #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
AnnaBridge 171:3a7713b1edbc 7930 #define USB_CTL_ODDRST_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7931 #define USB_CTL_ODDRST_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7932 #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
AnnaBridge 171:3a7713b1edbc 7933 #define USB_CTL_RESUME_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7934 #define USB_CTL_RESUME_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7935 #define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
AnnaBridge 171:3a7713b1edbc 7936 #define USB_CTL_HOSTMODEEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7937 #define USB_CTL_HOSTMODEEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7938 #define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
AnnaBridge 171:3a7713b1edbc 7939 #define USB_CTL_RESET_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7940 #define USB_CTL_RESET_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7941 #define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
AnnaBridge 171:3a7713b1edbc 7942 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7943 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7944 #define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
AnnaBridge 171:3a7713b1edbc 7945 #define USB_CTL_SE0_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7946 #define USB_CTL_SE0_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7947 #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
AnnaBridge 171:3a7713b1edbc 7948 #define USB_CTL_JSTATE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7949 #define USB_CTL_JSTATE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7950 #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
AnnaBridge 171:3a7713b1edbc 7951
AnnaBridge 171:3a7713b1edbc 7952 /*! @name ADDR - Address register */
AnnaBridge 171:3a7713b1edbc 7953 #define USB_ADDR_ADDR_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 7954 #define USB_ADDR_ADDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7955 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
AnnaBridge 171:3a7713b1edbc 7956 #define USB_ADDR_LSEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7957 #define USB_ADDR_LSEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7958 #define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
AnnaBridge 171:3a7713b1edbc 7959
AnnaBridge 171:3a7713b1edbc 7960 /*! @name BDTPAGE1 - BDT Page Register 1 */
AnnaBridge 171:3a7713b1edbc 7961 #define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
AnnaBridge 171:3a7713b1edbc 7962 #define USB_BDTPAGE1_BDTBA_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7963 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
AnnaBridge 171:3a7713b1edbc 7964
AnnaBridge 171:3a7713b1edbc 7965 /*! @name FRMNUML - Frame Number Register Low */
AnnaBridge 171:3a7713b1edbc 7966 #define USB_FRMNUML_FRM_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7967 #define USB_FRMNUML_FRM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7968 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
AnnaBridge 171:3a7713b1edbc 7969
AnnaBridge 171:3a7713b1edbc 7970 /*! @name FRMNUMH - Frame Number Register High */
AnnaBridge 171:3a7713b1edbc 7971 #define USB_FRMNUMH_FRM_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 7972 #define USB_FRMNUMH_FRM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7973 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
AnnaBridge 171:3a7713b1edbc 7974
AnnaBridge 171:3a7713b1edbc 7975 /*! @name TOKEN - Token register */
AnnaBridge 171:3a7713b1edbc 7976 #define USB_TOKEN_TOKENENDPT_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 7977 #define USB_TOKEN_TOKENENDPT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7978 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
AnnaBridge 171:3a7713b1edbc 7979 #define USB_TOKEN_TOKENPID_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 7980 #define USB_TOKEN_TOKENPID_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7981 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
AnnaBridge 171:3a7713b1edbc 7982
AnnaBridge 171:3a7713b1edbc 7983 /*! @name SOFTHLD - SOF Threshold Register */
AnnaBridge 171:3a7713b1edbc 7984 #define USB_SOFTHLD_CNT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7985 #define USB_SOFTHLD_CNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7986 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
AnnaBridge 171:3a7713b1edbc 7987
AnnaBridge 171:3a7713b1edbc 7988 /*! @name BDTPAGE2 - BDT Page Register 2 */
AnnaBridge 171:3a7713b1edbc 7989 #define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7990 #define USB_BDTPAGE2_BDTBA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7991 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
AnnaBridge 171:3a7713b1edbc 7992
AnnaBridge 171:3a7713b1edbc 7993 /*! @name BDTPAGE3 - BDT Page Register 3 */
AnnaBridge 171:3a7713b1edbc 7994 #define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7995 #define USB_BDTPAGE3_BDTBA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7996 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
AnnaBridge 171:3a7713b1edbc 7997
AnnaBridge 171:3a7713b1edbc 7998 /*! @name ENDPT - Endpoint Control register */
AnnaBridge 171:3a7713b1edbc 7999 #define USB_ENDPT_EPHSHK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8000 #define USB_ENDPT_EPHSHK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8001 #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
AnnaBridge 171:3a7713b1edbc 8002 #define USB_ENDPT_EPSTALL_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8003 #define USB_ENDPT_EPSTALL_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8004 #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
AnnaBridge 171:3a7713b1edbc 8005 #define USB_ENDPT_EPTXEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8006 #define USB_ENDPT_EPTXEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8007 #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
AnnaBridge 171:3a7713b1edbc 8008 #define USB_ENDPT_EPRXEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8009 #define USB_ENDPT_EPRXEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8010 #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
AnnaBridge 171:3a7713b1edbc 8011 #define USB_ENDPT_EPCTLDIS_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8012 #define USB_ENDPT_EPCTLDIS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8013 #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
AnnaBridge 171:3a7713b1edbc 8014 #define USB_ENDPT_RETRYDIS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8015 #define USB_ENDPT_RETRYDIS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8016 #define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
AnnaBridge 171:3a7713b1edbc 8017 #define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8018 #define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8019 #define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
AnnaBridge 171:3a7713b1edbc 8020
AnnaBridge 171:3a7713b1edbc 8021 /* The count of USB_ENDPT */
AnnaBridge 171:3a7713b1edbc 8022 #define USB_ENDPT_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 8023
AnnaBridge 171:3a7713b1edbc 8024 /*! @name USBCTRL - USB Control register */
AnnaBridge 171:3a7713b1edbc 8025 #define USB_USBCTRL_PDE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8026 #define USB_USBCTRL_PDE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8027 #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
AnnaBridge 171:3a7713b1edbc 8028 #define USB_USBCTRL_SUSP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8029 #define USB_USBCTRL_SUSP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8030 #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
AnnaBridge 171:3a7713b1edbc 8031
AnnaBridge 171:3a7713b1edbc 8032 /*! @name OBSERVE - USB OTG Observe register */
AnnaBridge 171:3a7713b1edbc 8033 #define USB_OBSERVE_DMPD_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8034 #define USB_OBSERVE_DMPD_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8035 #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
AnnaBridge 171:3a7713b1edbc 8036 #define USB_OBSERVE_DPPD_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8037 #define USB_OBSERVE_DPPD_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8038 #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
AnnaBridge 171:3a7713b1edbc 8039 #define USB_OBSERVE_DPPU_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8040 #define USB_OBSERVE_DPPU_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8041 #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
AnnaBridge 171:3a7713b1edbc 8042
AnnaBridge 171:3a7713b1edbc 8043 /*! @name CONTROL - USB OTG Control register */
AnnaBridge 171:3a7713b1edbc 8044 #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8045 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8046 #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
AnnaBridge 171:3a7713b1edbc 8047
AnnaBridge 171:3a7713b1edbc 8048 /*! @name USBTRC0 - USB Transceiver Control Register 0 */
AnnaBridge 171:3a7713b1edbc 8049 #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8050 #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8051 #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
AnnaBridge 171:3a7713b1edbc 8052 #define USB_USBTRC0_SYNC_DET_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8053 #define USB_USBTRC0_SYNC_DET_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8054 #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
AnnaBridge 171:3a7713b1edbc 8055 #define USB_USBTRC0_USBRESMEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8056 #define USB_USBTRC0_USBRESMEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8057 #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
AnnaBridge 171:3a7713b1edbc 8058 #define USB_USBTRC0_USBRESET_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8059 #define USB_USBTRC0_USBRESET_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8060 #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
AnnaBridge 171:3a7713b1edbc 8061
AnnaBridge 171:3a7713b1edbc 8062 /*! @name USBFRMADJUST - Frame Adjust Register */
AnnaBridge 171:3a7713b1edbc 8063 #define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8064 #define USB_USBFRMADJUST_ADJ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8065 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
AnnaBridge 171:3a7713b1edbc 8066
AnnaBridge 171:3a7713b1edbc 8067
AnnaBridge 171:3a7713b1edbc 8068 /*!
AnnaBridge 171:3a7713b1edbc 8069 * @}
AnnaBridge 171:3a7713b1edbc 8070 */ /* end of group USB_Register_Masks */
AnnaBridge 171:3a7713b1edbc 8071
AnnaBridge 171:3a7713b1edbc 8072
AnnaBridge 171:3a7713b1edbc 8073 /* USB - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 8074 /** Peripheral USB0 base address */
AnnaBridge 171:3a7713b1edbc 8075 #define USB0_BASE (0x40072000u)
AnnaBridge 171:3a7713b1edbc 8076 /** Peripheral USB0 base pointer */
AnnaBridge 171:3a7713b1edbc 8077 #define USB0 ((USB_Type *)USB0_BASE)
AnnaBridge 171:3a7713b1edbc 8078 /** Array initializer of USB peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 8079 #define USB_BASE_ADDRS { USB0_BASE }
AnnaBridge 171:3a7713b1edbc 8080 /** Array initializer of USB peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 8081 #define USB_BASE_PTRS { USB0 }
AnnaBridge 171:3a7713b1edbc 8082 /** Interrupt vectors for the USB peripheral type */
AnnaBridge 171:3a7713b1edbc 8083 #define USB_IRQS { USB0_IRQn }
AnnaBridge 171:3a7713b1edbc 8084
AnnaBridge 171:3a7713b1edbc 8085 /*!
AnnaBridge 171:3a7713b1edbc 8086 * @}
AnnaBridge 171:3a7713b1edbc 8087 */ /* end of group USB_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 8088
AnnaBridge 171:3a7713b1edbc 8089
AnnaBridge 171:3a7713b1edbc 8090 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8091 -- USBDCD Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8092 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8093
AnnaBridge 171:3a7713b1edbc 8094 /*!
AnnaBridge 171:3a7713b1edbc 8095 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8096 * @{
AnnaBridge 171:3a7713b1edbc 8097 */
AnnaBridge 171:3a7713b1edbc 8098
AnnaBridge 171:3a7713b1edbc 8099 /** USBDCD - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 8100 typedef struct {
AnnaBridge 171:3a7713b1edbc 8101 __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 8102 __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 8103 __I uint32_t STATUS; /**< Status register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 8104 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 8105 __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 8106 __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 8107 __IO uint32_t TIMER2; /**< TIMER2 register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 8108 } USBDCD_Type;
AnnaBridge 171:3a7713b1edbc 8109
AnnaBridge 171:3a7713b1edbc 8110 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8111 -- USBDCD Register Masks
AnnaBridge 171:3a7713b1edbc 8112 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8113
AnnaBridge 171:3a7713b1edbc 8114 /*!
AnnaBridge 171:3a7713b1edbc 8115 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
AnnaBridge 171:3a7713b1edbc 8116 * @{
AnnaBridge 171:3a7713b1edbc 8117 */
AnnaBridge 171:3a7713b1edbc 8118
AnnaBridge 171:3a7713b1edbc 8119 /*! @name CONTROL - Control register */
AnnaBridge 171:3a7713b1edbc 8120 #define USBDCD_CONTROL_IACK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8121 #define USBDCD_CONTROL_IACK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8122 #define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
AnnaBridge 171:3a7713b1edbc 8123 #define USBDCD_CONTROL_IF_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 8124 #define USBDCD_CONTROL_IF_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8125 #define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
AnnaBridge 171:3a7713b1edbc 8126 #define USBDCD_CONTROL_IE_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 8127 #define USBDCD_CONTROL_IE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8128 #define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
AnnaBridge 171:3a7713b1edbc 8129 #define USBDCD_CONTROL_START_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 8130 #define USBDCD_CONTROL_START_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8131 #define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
AnnaBridge 171:3a7713b1edbc 8132 #define USBDCD_CONTROL_SR_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 8133 #define USBDCD_CONTROL_SR_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 8134 #define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
AnnaBridge 171:3a7713b1edbc 8135
AnnaBridge 171:3a7713b1edbc 8136 /*! @name CLOCK - Clock register */
AnnaBridge 171:3a7713b1edbc 8137 #define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8138 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8139 #define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
AnnaBridge 171:3a7713b1edbc 8140 #define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
AnnaBridge 171:3a7713b1edbc 8141 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8142 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
AnnaBridge 171:3a7713b1edbc 8143
AnnaBridge 171:3a7713b1edbc 8144 /*! @name STATUS - Status register */
AnnaBridge 171:3a7713b1edbc 8145 #define USBDCD_STATUS_SEQ_RES_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 8146 #define USBDCD_STATUS_SEQ_RES_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8147 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
AnnaBridge 171:3a7713b1edbc 8148 #define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 8149 #define USBDCD_STATUS_SEQ_STAT_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 8150 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
AnnaBridge 171:3a7713b1edbc 8151 #define USBDCD_STATUS_ERR_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 8152 #define USBDCD_STATUS_ERR_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 8153 #define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
AnnaBridge 171:3a7713b1edbc 8154 #define USBDCD_STATUS_TO_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 8155 #define USBDCD_STATUS_TO_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 8156 #define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
AnnaBridge 171:3a7713b1edbc 8157 #define USBDCD_STATUS_ACTIVE_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 8158 #define USBDCD_STATUS_ACTIVE_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 8159 #define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
AnnaBridge 171:3a7713b1edbc 8160
AnnaBridge 171:3a7713b1edbc 8161 /*! @name TIMER0 - TIMER0 register */
AnnaBridge 171:3a7713b1edbc 8162 #define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU)
AnnaBridge 171:3a7713b1edbc 8163 #define USBDCD_TIMER0_TUNITCON_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8164 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
AnnaBridge 171:3a7713b1edbc 8165 #define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 8166 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8167 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
AnnaBridge 171:3a7713b1edbc 8168
AnnaBridge 171:3a7713b1edbc 8169 /*! @name TIMER1 - TIMER1 register */
AnnaBridge 171:3a7713b1edbc 8170 #define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 8171 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8172 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
AnnaBridge 171:3a7713b1edbc 8173 #define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 8174 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8175 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
AnnaBridge 171:3a7713b1edbc 8176
AnnaBridge 171:3a7713b1edbc 8177 /*! @name TIMER2 - TIMER2 register */
AnnaBridge 171:3a7713b1edbc 8178 #define USBDCD_TIMER2_CHECK_DM_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 8179 #define USBDCD_TIMER2_CHECK_DM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8180 #define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_CHECK_DM_SHIFT)) & USBDCD_TIMER2_CHECK_DM_MASK)
AnnaBridge 171:3a7713b1edbc 8181 #define USBDCD_TIMER2_TVDPSRC_CON_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 8182 #define USBDCD_TIMER2_TVDPSRC_CON_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8183 #define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_TVDPSRC_CON_MASK)
AnnaBridge 171:3a7713b1edbc 8184
AnnaBridge 171:3a7713b1edbc 8185
AnnaBridge 171:3a7713b1edbc 8186 /*!
AnnaBridge 171:3a7713b1edbc 8187 * @}
AnnaBridge 171:3a7713b1edbc 8188 */ /* end of group USBDCD_Register_Masks */
AnnaBridge 171:3a7713b1edbc 8189
AnnaBridge 171:3a7713b1edbc 8190
AnnaBridge 171:3a7713b1edbc 8191 /* USBDCD - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 8192 /** Peripheral USBDCD base address */
AnnaBridge 171:3a7713b1edbc 8193 #define USBDCD_BASE (0x40035000u)
AnnaBridge 171:3a7713b1edbc 8194 /** Peripheral USBDCD base pointer */
AnnaBridge 171:3a7713b1edbc 8195 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
AnnaBridge 171:3a7713b1edbc 8196 /** Array initializer of USBDCD peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 8197 #define USBDCD_BASE_ADDRS { USBDCD_BASE }
AnnaBridge 171:3a7713b1edbc 8198 /** Array initializer of USBDCD peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 8199 #define USBDCD_BASE_PTRS { USBDCD }
AnnaBridge 171:3a7713b1edbc 8200 /** Interrupt vectors for the USBDCD peripheral type */
AnnaBridge 171:3a7713b1edbc 8201 #define USBDCD_IRQS { USBDCD_IRQn }
AnnaBridge 171:3a7713b1edbc 8202
AnnaBridge 171:3a7713b1edbc 8203 /*!
AnnaBridge 171:3a7713b1edbc 8204 * @}
AnnaBridge 171:3a7713b1edbc 8205 */ /* end of group USBDCD_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 8206
AnnaBridge 171:3a7713b1edbc 8207
AnnaBridge 171:3a7713b1edbc 8208 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8209 -- WDOG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8210 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8211
AnnaBridge 171:3a7713b1edbc 8212 /*!
AnnaBridge 171:3a7713b1edbc 8213 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8214 * @{
AnnaBridge 171:3a7713b1edbc 8215 */
AnnaBridge 171:3a7713b1edbc 8216
AnnaBridge 171:3a7713b1edbc 8217 /** WDOG - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 8218 typedef struct {
AnnaBridge 171:3a7713b1edbc 8219 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 8220 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 8221 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 8222 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 8223 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 8224 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 8225 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 8226 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
AnnaBridge 171:3a7713b1edbc 8227 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 8228 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
AnnaBridge 171:3a7713b1edbc 8229 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 8230 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
AnnaBridge 171:3a7713b1edbc 8231 } WDOG_Type;
AnnaBridge 171:3a7713b1edbc 8232
AnnaBridge 171:3a7713b1edbc 8233 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8234 -- WDOG Register Masks
AnnaBridge 171:3a7713b1edbc 8235 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8236
AnnaBridge 171:3a7713b1edbc 8237 /*!
AnnaBridge 171:3a7713b1edbc 8238 * @addtogroup WDOG_Register_Masks WDOG Register Masks
AnnaBridge 171:3a7713b1edbc 8239 * @{
AnnaBridge 171:3a7713b1edbc 8240 */
AnnaBridge 171:3a7713b1edbc 8241
AnnaBridge 171:3a7713b1edbc 8242 /*! @name STCTRLH - Watchdog Status and Control Register High */
AnnaBridge 171:3a7713b1edbc 8243 #define WDOG_STCTRLH_WDOGEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8244 #define WDOG_STCTRLH_WDOGEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8245 #define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
AnnaBridge 171:3a7713b1edbc 8246 #define WDOG_STCTRLH_CLKSRC_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8247 #define WDOG_STCTRLH_CLKSRC_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8248 #define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
AnnaBridge 171:3a7713b1edbc 8249 #define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8250 #define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8251 #define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
AnnaBridge 171:3a7713b1edbc 8252 #define WDOG_STCTRLH_WINEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8253 #define WDOG_STCTRLH_WINEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8254 #define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
AnnaBridge 171:3a7713b1edbc 8255 #define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8256 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8257 #define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
AnnaBridge 171:3a7713b1edbc 8258 #define WDOG_STCTRLH_DBGEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8259 #define WDOG_STCTRLH_DBGEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8260 #define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
AnnaBridge 171:3a7713b1edbc 8261 #define WDOG_STCTRLH_STOPEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8262 #define WDOG_STCTRLH_STOPEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8263 #define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
AnnaBridge 171:3a7713b1edbc 8264 #define WDOG_STCTRLH_WAITEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8265 #define WDOG_STCTRLH_WAITEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8266 #define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
AnnaBridge 171:3a7713b1edbc 8267 #define WDOG_STCTRLH_TESTWDOG_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 8268 #define WDOG_STCTRLH_TESTWDOG_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 8269 #define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
AnnaBridge 171:3a7713b1edbc 8270 #define WDOG_STCTRLH_TESTSEL_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 8271 #define WDOG_STCTRLH_TESTSEL_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 8272 #define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8273 #define WDOG_STCTRLH_BYTESEL_MASK (0x3000U)
AnnaBridge 171:3a7713b1edbc 8274 #define WDOG_STCTRLH_BYTESEL_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 8275 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
AnnaBridge 171:3a7713b1edbc 8276 #define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 8277 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 8278 #define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
AnnaBridge 171:3a7713b1edbc 8279
AnnaBridge 171:3a7713b1edbc 8280 /*! @name STCTRLL - Watchdog Status and Control Register Low */
AnnaBridge 171:3a7713b1edbc 8281 #define WDOG_STCTRLL_INTFLG_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 8282 #define WDOG_STCTRLL_INTFLG_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 8283 #define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
AnnaBridge 171:3a7713b1edbc 8284
AnnaBridge 171:3a7713b1edbc 8285 /*! @name TOVALH - Watchdog Time-out Value Register High */
AnnaBridge 171:3a7713b1edbc 8286 #define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 8287 #define WDOG_TOVALH_TOVALHIGH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8288 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
AnnaBridge 171:3a7713b1edbc 8289
AnnaBridge 171:3a7713b1edbc 8290 /*! @name TOVALL - Watchdog Time-out Value Register Low */
AnnaBridge 171:3a7713b1edbc 8291 #define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 8292 #define WDOG_TOVALL_TOVALLOW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8293 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
AnnaBridge 171:3a7713b1edbc 8294
AnnaBridge 171:3a7713b1edbc 8295 /*! @name WINH - Watchdog Window Register High */
AnnaBridge 171:3a7713b1edbc 8296 #define WDOG_WINH_WINHIGH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 8297 #define WDOG_WINH_WINHIGH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8298 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
AnnaBridge 171:3a7713b1edbc 8299
AnnaBridge 171:3a7713b1edbc 8300 /*! @name WINL - Watchdog Window Register Low */
AnnaBridge 171:3a7713b1edbc 8301 #define WDOG_WINL_WINLOW_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 8302 #define WDOG_WINL_WINLOW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8303 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
AnnaBridge 171:3a7713b1edbc 8304
AnnaBridge 171:3a7713b1edbc 8305 /*! @name REFRESH - Watchdog Refresh register */
AnnaBridge 171:3a7713b1edbc 8306 #define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 8307 #define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8308 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
AnnaBridge 171:3a7713b1edbc 8309
AnnaBridge 171:3a7713b1edbc 8310 /*! @name UNLOCK - Watchdog Unlock register */
AnnaBridge 171:3a7713b1edbc 8311 #define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 8312 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8313 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
AnnaBridge 171:3a7713b1edbc 8314
AnnaBridge 171:3a7713b1edbc 8315 /*! @name TMROUTH - Watchdog Timer Output Register High */
AnnaBridge 171:3a7713b1edbc 8316 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 8317 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8318 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
AnnaBridge 171:3a7713b1edbc 8319
AnnaBridge 171:3a7713b1edbc 8320 /*! @name TMROUTL - Watchdog Timer Output Register Low */
AnnaBridge 171:3a7713b1edbc 8321 #define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 8322 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8323 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
AnnaBridge 171:3a7713b1edbc 8324
AnnaBridge 171:3a7713b1edbc 8325 /*! @name RSTCNT - Watchdog Reset Count register */
AnnaBridge 171:3a7713b1edbc 8326 #define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 8327 #define WDOG_RSTCNT_RSTCNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8328 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
AnnaBridge 171:3a7713b1edbc 8329
AnnaBridge 171:3a7713b1edbc 8330 /*! @name PRESC - Watchdog Prescaler register */
AnnaBridge 171:3a7713b1edbc 8331 #define WDOG_PRESC_PRESCVAL_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 8332 #define WDOG_PRESC_PRESCVAL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8333 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
AnnaBridge 171:3a7713b1edbc 8334
AnnaBridge 171:3a7713b1edbc 8335
AnnaBridge 171:3a7713b1edbc 8336 /*!
AnnaBridge 171:3a7713b1edbc 8337 * @}
AnnaBridge 171:3a7713b1edbc 8338 */ /* end of group WDOG_Register_Masks */
AnnaBridge 171:3a7713b1edbc 8339
AnnaBridge 171:3a7713b1edbc 8340
AnnaBridge 171:3a7713b1edbc 8341 /* WDOG - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 8342 /** Peripheral WDOG base address */
AnnaBridge 171:3a7713b1edbc 8343 #define WDOG_BASE (0x40052000u)
AnnaBridge 171:3a7713b1edbc 8344 /** Peripheral WDOG base pointer */
AnnaBridge 171:3a7713b1edbc 8345 #define WDOG ((WDOG_Type *)WDOG_BASE)
AnnaBridge 171:3a7713b1edbc 8346 /** Array initializer of WDOG peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 8347 #define WDOG_BASE_ADDRS { WDOG_BASE }
AnnaBridge 171:3a7713b1edbc 8348 /** Array initializer of WDOG peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 8349 #define WDOG_BASE_PTRS { WDOG }
AnnaBridge 171:3a7713b1edbc 8350 /** Interrupt vectors for the WDOG peripheral type */
AnnaBridge 171:3a7713b1edbc 8351 #define WDOG_IRQS { WDOG_EWM_IRQn }
AnnaBridge 171:3a7713b1edbc 8352
AnnaBridge 171:3a7713b1edbc 8353 /*!
AnnaBridge 171:3a7713b1edbc 8354 * @}
AnnaBridge 171:3a7713b1edbc 8355 */ /* end of group WDOG_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 8356
AnnaBridge 171:3a7713b1edbc 8357
AnnaBridge 171:3a7713b1edbc 8358 /*
AnnaBridge 171:3a7713b1edbc 8359 ** End of section using anonymous unions
AnnaBridge 171:3a7713b1edbc 8360 */
AnnaBridge 171:3a7713b1edbc 8361
AnnaBridge 171:3a7713b1edbc 8362 #if defined(__ARMCC_VERSION)
AnnaBridge 171:3a7713b1edbc 8363 #pragma pop
AnnaBridge 171:3a7713b1edbc 8364 #elif defined(__CWCC__)
AnnaBridge 171:3a7713b1edbc 8365 #pragma pop
AnnaBridge 171:3a7713b1edbc 8366 #elif defined(__GNUC__)
AnnaBridge 171:3a7713b1edbc 8367 /* leave anonymous unions enabled */
AnnaBridge 171:3a7713b1edbc 8368 #elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge 171:3a7713b1edbc 8369 #pragma language=default
AnnaBridge 171:3a7713b1edbc 8370 #else
AnnaBridge 171:3a7713b1edbc 8371 #error Not supported compiler type
AnnaBridge 171:3a7713b1edbc 8372 #endif
AnnaBridge 171:3a7713b1edbc 8373
AnnaBridge 171:3a7713b1edbc 8374 /*!
AnnaBridge 171:3a7713b1edbc 8375 * @}
AnnaBridge 171:3a7713b1edbc 8376 */ /* end of group Peripheral_access_layer */
AnnaBridge 171:3a7713b1edbc 8377
AnnaBridge 171:3a7713b1edbc 8378
AnnaBridge 171:3a7713b1edbc 8379 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8380 -- SDK Compatibility
AnnaBridge 171:3a7713b1edbc 8381 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8382
AnnaBridge 171:3a7713b1edbc 8383 /*!
AnnaBridge 171:3a7713b1edbc 8384 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
AnnaBridge 171:3a7713b1edbc 8385 * @{
AnnaBridge 171:3a7713b1edbc 8386 */
AnnaBridge 171:3a7713b1edbc 8387
AnnaBridge 171:3a7713b1edbc 8388 #define MCG_S_LOLS_MASK MCG_S_LOLS0_MASK
AnnaBridge 171:3a7713b1edbc 8389 #define MCG_S_LOLS_SHIFT MCG_S_LOLS0_SHIFT
AnnaBridge 171:3a7713b1edbc 8390 #define DAC0_IRQn This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8391 #define DAC_DATL_REG(base,index) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8392 #define DAC_DATH_REG(base,index) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8393 #define DAC_SR_REG(base) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8394 #define DAC_C0_REG(base) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8395 #define DAC_C1_REG(base) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8396 #define DAC_C2_REG(base) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8397 #define DAC_DATL_DATA0_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8398 #define DAC_DATL_DATA0_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8399 #define DAC_DATL_DATA0(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8400 #define DAC_DATH_DATA1_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8401 #define DAC_DATH_DATA1_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8402 #define DAC_DATH_DATA1(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8403 #define DAC_SR_DACBFRPBF_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8404 #define DAC_SR_DACBFRPBF_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8405 #define DAC_SR_DACBFRPTF_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8406 #define DAC_SR_DACBFRPTF_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8407 #define DAC_SR_DACBFWMF_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8408 #define DAC_SR_DACBFWMF_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8409 #define DAC_C0_DACBBIEN_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8410 #define DAC_C0_DACBBIEN_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8411 #define DAC_C0_DACBTIEN_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8412 #define DAC_C0_DACBTIEN_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8413 #define DAC_C0_DACBWIEN_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8414 #define DAC_C0_DACBWIEN_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8415 #define DAC_C0_LPEN_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8416 #define DAC_C0_LPEN_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8417 #define DAC_C0_DACSWTRG_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8418 #define DAC_C0_DACSWTRG_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8419 #define DAC_C0_DACTRGSEL_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8420 #define DAC_C0_DACTRGSEL_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8421 #define DAC_C0_DACRFS_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8422 #define DAC_C0_DACRFS_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8423 #define DAC_C0_DACEN_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8424 #define DAC_C0_DACEN_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8425 #define DAC_C1_DACBFEN_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8426 #define DAC_C1_DACBFEN_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8427 #define DAC_C1_DACBFMD_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8428 #define DAC_C1_DACBFMD_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8429 #define DAC_C1_DACBFMD(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8430 #define DAC_C1_DACBFWM_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8431 #define DAC_C1_DACBFWM_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8432 #define DAC_C1_DACBFWM(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8433 #define DAC_C1_DMAEN_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8434 #define DAC_C1_DMAEN_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8435 #define DAC_C2_DACBFUP_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8436 #define DAC_C2_DACBFUP_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8437 #define DAC_C2_DACBFUP(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8438 #define DAC_C2_DACBFRP_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8439 #define DAC_C2_DACBFRP_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8440 #define DAC_C2_DACBFRP(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8441 #define DAC0_BASE This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8442 #define DAC0 This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8443 #define DAC_BASE_ADDRS This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8444 #define DAC_IRQS This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8445 #define DAC0_DAT0L This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8446 #define DAC0_DAT0H This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8447 #define DAC0_DAT1L This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8448 #define DAC0_DAT1H This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8449 #define DAC0_DAT2L This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8450 #define DAC0_DAT2H This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8451 #define DAC0_DAT3L This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8452 #define DAC0_DAT3H This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8453 #define DAC0_DAT4L This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8454 #define DAC0_DAT4H This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8455 #define DAC0_DAT5L This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8456 #define DAC0_DAT5H This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8457 #define DAC0_DAT6L This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8458 #define DAC0_DAT6H This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8459 #define DAC0_DAT7L This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8460 #define DAC0_DAT7H This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8461 #define DAC0_DAT8L This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8462 #define DAC0_DAT8H This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8463 #define DAC0_DAT9L This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8464 #define DAC0_DAT9H This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8465 #define DAC0_DAT10L This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8466 #define DAC0_DAT10H This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8467 #define DAC0_DAT11L This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8468 #define DAC0_DAT11H This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8469 #define DAC0_DAT12L This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8470 #define DAC0_DAT12H This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8471 #define DAC0_DAT13L This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8472 #define DAC0_DAT13H This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8473 #define DAC0_DAT14L This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8474 #define DAC0_DAT14H This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8475 #define DAC0_DAT15L This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8476 #define DAC0_DAT15H This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8477 #define DAC0_SR This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8478 #define DAC0_C0 This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8479 #define DAC0_C1 This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8480 #define DAC0_C2 This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8481 #define DAC0_DATL(index) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8482 #define DAC0_DATH(index) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8483 #define DMA_EARS_REG(base) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8484 #define DMA_EARS_EDREQ_0_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8485 #define DMA_EARS_EDREQ_0_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8486 #define DMA_EARS_EDREQ_1_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8487 #define DMA_EARS_EDREQ_1_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8488 #define DMA_EARS_EDREQ_2_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8489 #define DMA_EARS_EDREQ_2_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8490 #define DMA_EARS_EDREQ_3_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8491 #define DMA_EARS_EDREQ_3_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8492 #define DMA_EARS_EDREQ_4_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8493 #define DMA_EARS_EDREQ_4_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8494 #define DMA_EARS_EDREQ_5_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8495 #define DMA_EARS_EDREQ_5_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8496 #define DMA_EARS_EDREQ_6_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8497 #define DMA_EARS_EDREQ_6_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8498 #define DMA_EARS_EDREQ_7_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8499 #define DMA_EARS_EDREQ_7_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8500 #define DMA_EARS_EDREQ_8_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8501 #define DMA_EARS_EDREQ_8_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8502 #define DMA_EARS_EDREQ_9_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8503 #define DMA_EARS_EDREQ_9_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8504 #define DMA_EARS_EDREQ_10_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8505 #define DMA_EARS_EDREQ_10_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8506 #define DMA_EARS_EDREQ_11_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8507 #define DMA_EARS_EDREQ_11_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8508 #define DMA_EARS_EDREQ_12_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8509 #define DMA_EARS_EDREQ_12_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8510 #define DMA_EARS_EDREQ_13_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8511 #define DMA_EARS_EDREQ_13_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8512 #define DMA_EARS_EDREQ_14_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8513 #define DMA_EARS_EDREQ_14_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8514 #define DMA_EARS_EDREQ_15_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8515 #define DMA_EARS_EDREQ_15_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8516 #define DMA_EARS This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8517 #define DSPI0 SPI0
AnnaBridge 171:3a7713b1edbc 8518 #define DSPI1 SPI1
AnnaBridge 171:3a7713b1edbc 8519 #define DMAMUX0 DMAMUX
AnnaBridge 171:3a7713b1edbc 8520 #define WP7816_T_TYPE0 WP7816T0
AnnaBridge 171:3a7713b1edbc 8521 #define WP7816_T_TYPE1 WP7816T1
AnnaBridge 171:3a7713b1edbc 8522 #define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
AnnaBridge 171:3a7713b1edbc 8523 #define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
AnnaBridge 171:3a7713b1edbc 8524 #define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK
AnnaBridge 171:3a7713b1edbc 8525 #define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
AnnaBridge 171:3a7713b1edbc 8526 #define UART_WP7816_T_TYPE0_WI(X) UART_WP7816T0_WI(X)
AnnaBridge 171:3a7713b1edbc 8527 #define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
AnnaBridge 171:3a7713b1edbc 8528 #define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
AnnaBridge 171:3a7713b1edbc 8529 #define UART_WP7816_T_TYPE1_BWI(X) UART_WP7816T1_BWI(X)
AnnaBridge 171:3a7713b1edbc 8530 #define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
AnnaBridge 171:3a7713b1edbc 8531 #define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
AnnaBridge 171:3a7713b1edbc 8532 #define UART_WP7816_T_TYPE1_CWI(X) UART_WP7816T1_CWI(X)
AnnaBridge 171:3a7713b1edbc 8533 #define SIM_SCGC6_DAC0_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8534 #define SIM_SCGC6_DAC0_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 8535 #define Watchdog_IRQn WDOG_EWM_IRQn
AnnaBridge 171:3a7713b1edbc 8536 #define Watchdog_IRQHandler WDOG_EWM_IRQHandler
AnnaBridge 171:3a7713b1edbc 8537 #define LPTimer_IRQn LPTMR0_IRQn
AnnaBridge 171:3a7713b1edbc 8538 #define LPTimer_IRQHandler LPTMR0_IRQHandler
AnnaBridge 171:3a7713b1edbc 8539 #define LLW_IRQn LLWU_IRQn
AnnaBridge 171:3a7713b1edbc 8540 #define LLW_IRQHandler LLWU_IRQHandler
AnnaBridge 171:3a7713b1edbc 8541
AnnaBridge 171:3a7713b1edbc 8542 /*!
AnnaBridge 171:3a7713b1edbc 8543 * @}
AnnaBridge 171:3a7713b1edbc 8544 */ /* end of group SDK_Compatibility_Symbols */
AnnaBridge 171:3a7713b1edbc 8545
AnnaBridge 171:3a7713b1edbc 8546
AnnaBridge 171:3a7713b1edbc 8547 #endif /* _MKW24D5_H_ */
AnnaBridge 171:3a7713b1edbc 8548