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TARGET_K82F/TOOLCHAIN_IAR/MK82F25615.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 171:3a7713b1edbc | 1 | /* |
AnnaBridge | 171:3a7713b1edbc | 2 | ** ################################################################### |
AnnaBridge | 171:3a7713b1edbc | 3 | ** Processors: MK82FN256CAx15 |
AnnaBridge | 171:3a7713b1edbc | 4 | ** MK82FN256VDC15 |
AnnaBridge | 171:3a7713b1edbc | 5 | ** MK82FN256VLL15 |
AnnaBridge | 171:3a7713b1edbc | 6 | ** MK82FN256VLQ15 |
AnnaBridge | 171:3a7713b1edbc | 7 | ** |
AnnaBridge | 171:3a7713b1edbc | 8 | ** Compilers: Keil ARM C/C++ Compiler |
AnnaBridge | 171:3a7713b1edbc | 9 | ** Freescale C/C++ for Embedded ARM |
AnnaBridge | 171:3a7713b1edbc | 10 | ** GNU C Compiler |
AnnaBridge | 171:3a7713b1edbc | 11 | ** IAR ANSI C/C++ Compiler for ARM |
AnnaBridge | 171:3a7713b1edbc | 12 | ** |
AnnaBridge | 171:3a7713b1edbc | 13 | ** Reference manual: K82P121M150SF5RM, Rev. 0, May 2015 |
AnnaBridge | 171:3a7713b1edbc | 14 | ** Version: rev. 1.2, 2015-07-29 |
AnnaBridge | 171:3a7713b1edbc | 15 | ** Build: b151218 |
AnnaBridge | 171:3a7713b1edbc | 16 | ** |
AnnaBridge | 171:3a7713b1edbc | 17 | ** Abstract: |
AnnaBridge | 171:3a7713b1edbc | 18 | ** CMSIS Peripheral Access Layer for MK82F25615 |
AnnaBridge | 171:3a7713b1edbc | 19 | ** |
AnnaBridge | 171:3a7713b1edbc | 20 | ** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. |
AnnaBridge | 171:3a7713b1edbc | 21 | ** All rights reserved. |
AnnaBridge | 171:3a7713b1edbc | 22 | ** |
AnnaBridge | 171:3a7713b1edbc | 23 | ** Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 24 | ** are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 25 | ** |
AnnaBridge | 171:3a7713b1edbc | 26 | ** o Redistributions of source code must retain the above copyright notice, this list |
AnnaBridge | 171:3a7713b1edbc | 27 | ** of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 28 | ** |
AnnaBridge | 171:3a7713b1edbc | 29 | ** o Redistributions in binary form must reproduce the above copyright notice, this |
AnnaBridge | 171:3a7713b1edbc | 30 | ** list of conditions and the following disclaimer in the documentation and/or |
AnnaBridge | 171:3a7713b1edbc | 31 | ** other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 32 | ** |
AnnaBridge | 171:3a7713b1edbc | 33 | ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
AnnaBridge | 171:3a7713b1edbc | 34 | ** contributors may be used to endorse or promote products derived from this |
AnnaBridge | 171:3a7713b1edbc | 35 | ** software without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 36 | ** |
AnnaBridge | 171:3a7713b1edbc | 37 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
AnnaBridge | 171:3a7713b1edbc | 38 | ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
AnnaBridge | 171:3a7713b1edbc | 39 | ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 40 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
AnnaBridge | 171:3a7713b1edbc | 41 | ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
AnnaBridge | 171:3a7713b1edbc | 42 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
AnnaBridge | 171:3a7713b1edbc | 43 | ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
AnnaBridge | 171:3a7713b1edbc | 44 | ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
AnnaBridge | 171:3a7713b1edbc | 45 | ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
AnnaBridge | 171:3a7713b1edbc | 46 | ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 47 | ** |
AnnaBridge | 171:3a7713b1edbc | 48 | ** http: www.freescale.com |
AnnaBridge | 171:3a7713b1edbc | 49 | ** mail: support@freescale.com |
AnnaBridge | 171:3a7713b1edbc | 50 | ** |
AnnaBridge | 171:3a7713b1edbc | 51 | ** Revisions: |
AnnaBridge | 171:3a7713b1edbc | 52 | ** - rev. 1.0 (2015-04-09) |
AnnaBridge | 171:3a7713b1edbc | 53 | ** Initial version |
AnnaBridge | 171:3a7713b1edbc | 54 | ** - rev. 1.1 (2015-05-28) |
AnnaBridge | 171:3a7713b1edbc | 55 | ** Update according to the reference manual Rev. 0. |
AnnaBridge | 171:3a7713b1edbc | 56 | ** - rev. 1.2 (2015-07-29) |
AnnaBridge | 171:3a7713b1edbc | 57 | ** Correction of backward compatibility. |
AnnaBridge | 171:3a7713b1edbc | 58 | ** |
AnnaBridge | 171:3a7713b1edbc | 59 | ** ################################################################### |
AnnaBridge | 171:3a7713b1edbc | 60 | */ |
AnnaBridge | 171:3a7713b1edbc | 61 | |
AnnaBridge | 171:3a7713b1edbc | 62 | /*! |
AnnaBridge | 171:3a7713b1edbc | 63 | * @file MK82F25615.h |
AnnaBridge | 171:3a7713b1edbc | 64 | * @version 1.2 |
AnnaBridge | 171:3a7713b1edbc | 65 | * @date 2015-07-29 |
AnnaBridge | 171:3a7713b1edbc | 66 | * @brief CMSIS Peripheral Access Layer for MK82F25615 |
AnnaBridge | 171:3a7713b1edbc | 67 | * |
AnnaBridge | 171:3a7713b1edbc | 68 | * CMSIS Peripheral Access Layer for MK82F25615 |
AnnaBridge | 171:3a7713b1edbc | 69 | */ |
AnnaBridge | 171:3a7713b1edbc | 70 | |
AnnaBridge | 171:3a7713b1edbc | 71 | #ifndef _MK82F25615_H_ |
AnnaBridge | 171:3a7713b1edbc | 72 | #define _MK82F25615_H_ /**< Symbol preventing repeated inclusion */ |
AnnaBridge | 171:3a7713b1edbc | 73 | |
AnnaBridge | 171:3a7713b1edbc | 74 | /** Memory map major version (memory maps with equal major version number are |
AnnaBridge | 171:3a7713b1edbc | 75 | * compatible) */ |
AnnaBridge | 171:3a7713b1edbc | 76 | #define MCU_MEM_MAP_VERSION 0x0100U |
AnnaBridge | 171:3a7713b1edbc | 77 | /** Memory map minor version */ |
AnnaBridge | 171:3a7713b1edbc | 78 | #define MCU_MEM_MAP_VERSION_MINOR 0x0002U |
AnnaBridge | 171:3a7713b1edbc | 79 | |
AnnaBridge | 171:3a7713b1edbc | 80 | /** |
AnnaBridge | 171:3a7713b1edbc | 81 | * @brief Macro to calculate address of an aliased word in the peripheral |
AnnaBridge | 171:3a7713b1edbc | 82 | * bitband area for a peripheral register and bit (bit band region 0x40000000 to |
AnnaBridge | 171:3a7713b1edbc | 83 | * 0x400FFFFF). |
AnnaBridge | 171:3a7713b1edbc | 84 | * @param Reg Register to access. |
AnnaBridge | 171:3a7713b1edbc | 85 | * @param Bit Bit number to access. |
AnnaBridge | 171:3a7713b1edbc | 86 | * @return Address of the aliased word in the peripheral bitband area. |
AnnaBridge | 171:3a7713b1edbc | 87 | */ |
AnnaBridge | 171:3a7713b1edbc | 88 | #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))) |
AnnaBridge | 171:3a7713b1edbc | 89 | /** |
AnnaBridge | 171:3a7713b1edbc | 90 | * @brief Macro to access a single bit of a peripheral register (bit band region |
AnnaBridge | 171:3a7713b1edbc | 91 | * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can |
AnnaBridge | 171:3a7713b1edbc | 92 | * be used for peripherals with 32bit access allowed. |
AnnaBridge | 171:3a7713b1edbc | 93 | * @param Reg Register to access. |
AnnaBridge | 171:3a7713b1edbc | 94 | * @param Bit Bit number to access. |
AnnaBridge | 171:3a7713b1edbc | 95 | * @return Value of the targeted bit in the bit band region. |
AnnaBridge | 171:3a7713b1edbc | 96 | */ |
AnnaBridge | 171:3a7713b1edbc | 97 | #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) |
AnnaBridge | 171:3a7713b1edbc | 98 | #define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit))) |
AnnaBridge | 171:3a7713b1edbc | 99 | /** |
AnnaBridge | 171:3a7713b1edbc | 100 | * @brief Macro to access a single bit of a peripheral register (bit band region |
AnnaBridge | 171:3a7713b1edbc | 101 | * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can |
AnnaBridge | 171:3a7713b1edbc | 102 | * be used for peripherals with 16bit access allowed. |
AnnaBridge | 171:3a7713b1edbc | 103 | * @param Reg Register to access. |
AnnaBridge | 171:3a7713b1edbc | 104 | * @param Bit Bit number to access. |
AnnaBridge | 171:3a7713b1edbc | 105 | * @return Value of the targeted bit in the bit band region. |
AnnaBridge | 171:3a7713b1edbc | 106 | */ |
AnnaBridge | 171:3a7713b1edbc | 107 | #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) |
AnnaBridge | 171:3a7713b1edbc | 108 | /** |
AnnaBridge | 171:3a7713b1edbc | 109 | * @brief Macro to access a single bit of a peripheral register (bit band region |
AnnaBridge | 171:3a7713b1edbc | 110 | * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can |
AnnaBridge | 171:3a7713b1edbc | 111 | * be used for peripherals with 8bit access allowed. |
AnnaBridge | 171:3a7713b1edbc | 112 | * @param Reg Register to access. |
AnnaBridge | 171:3a7713b1edbc | 113 | * @param Bit Bit number to access. |
AnnaBridge | 171:3a7713b1edbc | 114 | * @return Value of the targeted bit in the bit band region. |
AnnaBridge | 171:3a7713b1edbc | 115 | */ |
AnnaBridge | 171:3a7713b1edbc | 116 | #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) |
AnnaBridge | 171:3a7713b1edbc | 117 | |
AnnaBridge | 171:3a7713b1edbc | 118 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 119 | -- Interrupt vector numbers |
AnnaBridge | 171:3a7713b1edbc | 120 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 121 | |
AnnaBridge | 171:3a7713b1edbc | 122 | /*! |
AnnaBridge | 171:3a7713b1edbc | 123 | * @addtogroup Interrupt_vector_numbers Interrupt vector numbers |
AnnaBridge | 171:3a7713b1edbc | 124 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 125 | */ |
AnnaBridge | 171:3a7713b1edbc | 126 | |
AnnaBridge | 171:3a7713b1edbc | 127 | /** Interrupt Number Definitions */ |
AnnaBridge | 171:3a7713b1edbc | 128 | #define NUMBER_OF_INT_VECTORS 123 /**< Number of interrupts in the Vector table */ |
AnnaBridge | 171:3a7713b1edbc | 129 | |
AnnaBridge | 171:3a7713b1edbc | 130 | typedef enum IRQn { |
AnnaBridge | 171:3a7713b1edbc | 131 | /* Auxiliary constants */ |
AnnaBridge | 171:3a7713b1edbc | 132 | NotAvail_IRQn = -128, /**< Not available device specific interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 133 | |
AnnaBridge | 171:3a7713b1edbc | 134 | /* Core interrupts */ |
AnnaBridge | 171:3a7713b1edbc | 135 | NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 136 | HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 137 | MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 138 | BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 139 | UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 140 | SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 141 | DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 142 | PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 143 | SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 144 | |
AnnaBridge | 171:3a7713b1edbc | 145 | /* Device specific interrupts */ |
AnnaBridge | 171:3a7713b1edbc | 146 | DMA0_DMA16_IRQn = 0, /**< DMA channel 0,16 transfer complete */ |
AnnaBridge | 171:3a7713b1edbc | 147 | DMA1_DMA17_IRQn = 1, /**< DMA channel 1,17 transfer complete */ |
AnnaBridge | 171:3a7713b1edbc | 148 | DMA2_DMA18_IRQn = 2, /**< DMA channel 2,18 transfer complete */ |
AnnaBridge | 171:3a7713b1edbc | 149 | DMA3_DMA19_IRQn = 3, /**< DMA channel 3,19 transfer complete */ |
AnnaBridge | 171:3a7713b1edbc | 150 | DMA4_DMA20_IRQn = 4, /**< DMA channel 4,20 transfer complete */ |
AnnaBridge | 171:3a7713b1edbc | 151 | DMA5_DMA21_IRQn = 5, /**< DMA channel 5,21 transfer complete */ |
AnnaBridge | 171:3a7713b1edbc | 152 | DMA6_DMA22_IRQn = 6, /**< DMA channel 6,22 transfer complete */ |
AnnaBridge | 171:3a7713b1edbc | 153 | DMA7_DMA23_IRQn = 7, /**< DMA channel 7,23 transfer complete */ |
AnnaBridge | 171:3a7713b1edbc | 154 | DMA8_DMA24_IRQn = 8, /**< DMA channel 8,24 transfer complete */ |
AnnaBridge | 171:3a7713b1edbc | 155 | DMA9_DMA25_IRQn = 9, /**< DMA channel 9,25 transfer complete */ |
AnnaBridge | 171:3a7713b1edbc | 156 | DMA10_DMA26_IRQn = 10, /**< DMA channel 10,26 transfer complete */ |
AnnaBridge | 171:3a7713b1edbc | 157 | DMA11_DMA27_IRQn = 11, /**< DMA channel 11,27 transfer complete */ |
AnnaBridge | 171:3a7713b1edbc | 158 | DMA12_DMA28_IRQn = 12, /**< DMA channel 12,28 transfer complete */ |
AnnaBridge | 171:3a7713b1edbc | 159 | DMA13_DMA29_IRQn = 13, /**< DMA channel 13,29 transfer complete */ |
AnnaBridge | 171:3a7713b1edbc | 160 | DMA14_DMA30_IRQn = 14, /**< DMA channel 14,30 transfer complete */ |
AnnaBridge | 171:3a7713b1edbc | 161 | DMA15_DMA31_IRQn = 15, /**< DMA channel 15,31 transfer complete */ |
AnnaBridge | 171:3a7713b1edbc | 162 | DMA_Error_IRQn = 16, /**< DMA channel 0 - 31 error */ |
AnnaBridge | 171:3a7713b1edbc | 163 | MCM_IRQn = 17, /**< MCM normal interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 164 | FTFA_IRQn = 18, /**< FTFA command complete */ |
AnnaBridge | 171:3a7713b1edbc | 165 | Read_Collision_IRQn = 19, /**< FTFA read collision */ |
AnnaBridge | 171:3a7713b1edbc | 166 | LVD_LVW_IRQn = 20, /**< PMC controller low-voltage detect, low-voltage warning */ |
AnnaBridge | 171:3a7713b1edbc | 167 | LLWU_IRQn = 21, /**< Low leakage wakeup unit */ |
AnnaBridge | 171:3a7713b1edbc | 168 | WDOG_EWM_IRQn = 22, /**< Single interrupt vector for WDOG and EWM */ |
AnnaBridge | 171:3a7713b1edbc | 169 | TRNG0_IRQn = 23, /**< True randon number generator */ |
AnnaBridge | 171:3a7713b1edbc | 170 | I2C0_IRQn = 24, /**< Inter-integrated circuit 0 */ |
AnnaBridge | 171:3a7713b1edbc | 171 | I2C1_IRQn = 25, /**< Inter-integrated circuit 1 */ |
AnnaBridge | 171:3a7713b1edbc | 172 | SPI0_IRQn = 26, /**< Serial peripheral Interface 0 */ |
AnnaBridge | 171:3a7713b1edbc | 173 | SPI1_IRQn = 27, /**< Serial peripheral Interface 1 */ |
AnnaBridge | 171:3a7713b1edbc | 174 | I2S0_Tx_IRQn = 28, /**< Integrated interchip sound 0 transmit interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 175 | I2S0_Rx_IRQn = 29, /**< Integrated interchip sound 0 receive interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 176 | LPUART0_IRQn = 30, /**< LPUART0 receive/transmit/error interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 177 | LPUART1_IRQn = 31, /**< LPUART1 receive/transmit/error interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 178 | LPUART2_IRQn = 32, /**< LPUART2 receive/transmit/error interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 179 | LPUART3_IRQn = 33, /**< LPUART3 receive/transmit/error interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 180 | LPUART4_IRQn = 34, /**< LPUART4 receive/transmit/error interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 181 | Reserved51_IRQn = 35, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 182 | Reserved52_IRQn = 36, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 183 | EMVSIM0_IRQn = 37, /**< EMVSIM0 common interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 184 | EMVSIM1_IRQn = 38, /**< EMVSIM1 common interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 185 | ADC0_IRQn = 39, /**< Analog-to-digital converter 0 */ |
AnnaBridge | 171:3a7713b1edbc | 186 | CMP0_IRQn = 40, /**< Comparator 0 */ |
AnnaBridge | 171:3a7713b1edbc | 187 | CMP1_IRQn = 41, /**< Comparator 1 */ |
AnnaBridge | 171:3a7713b1edbc | 188 | FTM0_IRQn = 42, /**< FlexTimer module 0 fault, overflow and channels interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 189 | FTM1_IRQn = 43, /**< FlexTimer module 1 fault, overflow and channels interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 190 | FTM2_IRQn = 44, /**< FlexTimer module 2 fault, overflow and channels interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 191 | CMT_IRQn = 45, /**< Carrier modulator transmitter */ |
AnnaBridge | 171:3a7713b1edbc | 192 | RTC_IRQn = 46, /**< Real time clock */ |
AnnaBridge | 171:3a7713b1edbc | 193 | RTC_Seconds_IRQn = 47, /**< Real time clock seconds */ |
AnnaBridge | 171:3a7713b1edbc | 194 | PIT0CH0_IRQn = 48, /**< Periodic interrupt timer 0 channel 0 */ |
AnnaBridge | 171:3a7713b1edbc | 195 | PIT0CH1_IRQn = 49, /**< Periodic interrupt timer 0 channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 196 | PIT0CH2_IRQn = 50, /**< Periodic interrupt timer 0 channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 197 | PIT0CH3_IRQn = 51, /**< Periodic interrupt timer 0 channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 198 | PDB0_IRQn = 52, /**< Programmable delay block */ |
AnnaBridge | 171:3a7713b1edbc | 199 | USB0_IRQn = 53, /**< USB OTG interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 200 | USBDCD_IRQn = 54, /**< USB charger detect */ |
AnnaBridge | 171:3a7713b1edbc | 201 | Reserved71_IRQn = 55, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 202 | DAC0_IRQn = 56, /**< Digital-to-analog converter 0 */ |
AnnaBridge | 171:3a7713b1edbc | 203 | MCG_IRQn = 57, /**< Multipurpose clock generator */ |
AnnaBridge | 171:3a7713b1edbc | 204 | LPTMR0_LPTMR1_IRQn = 58, /**< Single interrupt vector for Low Power Timer 0 and 1 */ |
AnnaBridge | 171:3a7713b1edbc | 205 | PORTA_IRQn = 59, /**< Port A pin detect interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 206 | PORTB_IRQn = 60, /**< Port B pin detect interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 207 | PORTC_IRQn = 61, /**< Port C pin detect interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 208 | PORTD_IRQn = 62, /**< Port D pin detect interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 209 | PORTE_IRQn = 63, /**< Port E pin detect interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 210 | SWI_IRQn = 64, /**< Software interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 211 | SPI2_IRQn = 65, /**< Serial peripheral Interface 2 */ |
AnnaBridge | 171:3a7713b1edbc | 212 | Reserved82_IRQn = 66, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 213 | Reserved83_IRQn = 67, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 214 | Reserved84_IRQn = 68, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 215 | Reserved85_IRQn = 69, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 216 | FLEXIO0_IRQn = 70, /**< FLEXIO0 */ |
AnnaBridge | 171:3a7713b1edbc | 217 | FTM3_IRQn = 71, /**< FlexTimer module 3 fault, overflow and channels interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 218 | Reserved88_IRQn = 72, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 219 | Reserved89_IRQn = 73, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 220 | I2C2_IRQn = 74, /**< Inter-integrated circuit 2 */ |
AnnaBridge | 171:3a7713b1edbc | 221 | Reserved91_IRQn = 75, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 222 | Reserved92_IRQn = 76, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 223 | Reserved93_IRQn = 77, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 224 | Reserved94_IRQn = 78, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 225 | Reserved95_IRQn = 79, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 226 | Reserved96_IRQn = 80, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 227 | SDHC_IRQn = 81, /**< Secured digital host controller */ |
AnnaBridge | 171:3a7713b1edbc | 228 | Reserved98_IRQn = 82, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 229 | Reserved99_IRQn = 83, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 230 | Reserved100_IRQn = 84, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 231 | Reserved101_IRQn = 85, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 232 | Reserved102_IRQn = 86, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 233 | TSI0_IRQn = 87, /**< Touch Sensing Input */ |
AnnaBridge | 171:3a7713b1edbc | 234 | TPM1_IRQn = 88, /**< TPM1 single interrupt vector for all sources */ |
AnnaBridge | 171:3a7713b1edbc | 235 | TPM2_IRQn = 89, /**< TPM2 single interrupt vector for all sources */ |
AnnaBridge | 171:3a7713b1edbc | 236 | Reserved106_IRQn = 90, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 237 | I2C3_IRQn = 91, /**< Inter-integrated circuit 3 */ |
AnnaBridge | 171:3a7713b1edbc | 238 | Reserved108_IRQn = 92, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 239 | Reserved109_IRQn = 93, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 240 | Reserved110_IRQn = 94, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 241 | Reserved111_IRQn = 95, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 242 | Reserved112_IRQn = 96, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 243 | Reserved113_IRQn = 97, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 244 | Reserved114_IRQn = 98, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 245 | Reserved115_IRQn = 99, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 246 | QuadSPI0_IRQn = 100, /**< qspi */ |
AnnaBridge | 171:3a7713b1edbc | 247 | Reserved117_IRQn = 101, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 248 | Reserved118_IRQn = 102, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 249 | Reserved119_IRQn = 103, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 250 | LTC0_IRQn = 104, /**< LP Trusted Cryptography */ |
AnnaBridge | 171:3a7713b1edbc | 251 | Reserved121_IRQn = 105, /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 252 | Reserved122_IRQn = 106 /**< Reserved interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 253 | } IRQn_Type; |
AnnaBridge | 171:3a7713b1edbc | 254 | |
AnnaBridge | 171:3a7713b1edbc | 255 | /*! |
AnnaBridge | 171:3a7713b1edbc | 256 | * @} |
AnnaBridge | 171:3a7713b1edbc | 257 | */ /* end of group Interrupt_vector_numbers */ |
AnnaBridge | 171:3a7713b1edbc | 258 | |
AnnaBridge | 171:3a7713b1edbc | 259 | |
AnnaBridge | 171:3a7713b1edbc | 260 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 261 | -- Cortex M4 Core Configuration |
AnnaBridge | 171:3a7713b1edbc | 262 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 263 | |
AnnaBridge | 171:3a7713b1edbc | 264 | /*! |
AnnaBridge | 171:3a7713b1edbc | 265 | * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration |
AnnaBridge | 171:3a7713b1edbc | 266 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 267 | */ |
AnnaBridge | 171:3a7713b1edbc | 268 | |
AnnaBridge | 171:3a7713b1edbc | 269 | #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ |
AnnaBridge | 171:3a7713b1edbc | 270 | #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ |
AnnaBridge | 171:3a7713b1edbc | 271 | #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ |
AnnaBridge | 171:3a7713b1edbc | 272 | #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ |
AnnaBridge | 171:3a7713b1edbc | 273 | |
AnnaBridge | 171:3a7713b1edbc | 274 | #include "core_cm4.h" /* Core Peripheral Access Layer */ |
AnnaBridge | 171:3a7713b1edbc | 275 | #include "system_MK82F25615.h" /* Device specific configuration file */ |
AnnaBridge | 171:3a7713b1edbc | 276 | |
AnnaBridge | 171:3a7713b1edbc | 277 | /*! |
AnnaBridge | 171:3a7713b1edbc | 278 | * @} |
AnnaBridge | 171:3a7713b1edbc | 279 | */ /* end of group Cortex_Core_Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 280 | |
AnnaBridge | 171:3a7713b1edbc | 281 | |
AnnaBridge | 171:3a7713b1edbc | 282 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 283 | -- Mapping Information |
AnnaBridge | 171:3a7713b1edbc | 284 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 285 | |
AnnaBridge | 171:3a7713b1edbc | 286 | /*! |
AnnaBridge | 171:3a7713b1edbc | 287 | * @addtogroup Mapping_Information Mapping Information |
AnnaBridge | 171:3a7713b1edbc | 288 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 289 | */ |
AnnaBridge | 171:3a7713b1edbc | 290 | |
AnnaBridge | 171:3a7713b1edbc | 291 | /** Mapping Information */ |
AnnaBridge | 171:3a7713b1edbc | 292 | /*! |
AnnaBridge | 171:3a7713b1edbc | 293 | * @addtogroup edma_request |
AnnaBridge | 171:3a7713b1edbc | 294 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 295 | */ |
AnnaBridge | 171:3a7713b1edbc | 296 | |
AnnaBridge | 171:3a7713b1edbc | 297 | /******************************************************************************* |
AnnaBridge | 171:3a7713b1edbc | 298 | * Definitions |
AnnaBridge | 171:3a7713b1edbc | 299 | ******************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 300 | |
AnnaBridge | 171:3a7713b1edbc | 301 | /*! |
AnnaBridge | 171:3a7713b1edbc | 302 | * @brief Structure for the DMA hardware request |
AnnaBridge | 171:3a7713b1edbc | 303 | * |
AnnaBridge | 171:3a7713b1edbc | 304 | * Defines the structure for the DMA hardware request collections. The user can configure the |
AnnaBridge | 171:3a7713b1edbc | 305 | * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index |
AnnaBridge | 171:3a7713b1edbc | 306 | * of the hardware request varies according to the to SoC. |
AnnaBridge | 171:3a7713b1edbc | 307 | */ |
AnnaBridge | 171:3a7713b1edbc | 308 | typedef enum _dma_request_source |
AnnaBridge | 171:3a7713b1edbc | 309 | { |
AnnaBridge | 171:3a7713b1edbc | 310 | kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */ |
AnnaBridge | 171:3a7713b1edbc | 311 | kDmaRequestMux0TSI0 = 1|0x100U, /**< TSI0. */ |
AnnaBridge | 171:3a7713b1edbc | 312 | kDmaRequestMux0LPUART0Rx = 2|0x100U, /**< LPUART0 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 313 | kDmaRequestMux0LPUART0Tx = 3|0x100U, /**< LPUART0 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 314 | kDmaRequestMux0LPUART1Rx = 4|0x100U, /**< LPUART1 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 315 | kDmaRequestMux0LPUART1Tx = 5|0x100U, /**< LPUART1 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 316 | kDmaRequestMux0LPUART2Rx = 6|0x100U, /**< LPUART2 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 317 | kDmaRequestMux0LPUART2Tx = 7|0x100U, /**< LPUART2 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 318 | kDmaRequestMux0LPUART3Rx = 8|0x100U, /**< LPUART3 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 319 | kDmaRequestMux0LPUART3Tx = 9|0x100U, /**< LPUART3 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 320 | kDmaRequestMux0LPUART4Rx = 10|0x100U, /**< LPUART4 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 321 | kDmaRequestMux0LPUART4Tx = 11|0x100U, /**< LPUART4 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 322 | kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 323 | kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 324 | kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 325 | kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 326 | kDmaRequestMux0SPI1Rx = 16|0x100U, /**< SPI1 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 327 | kDmaRequestMux0SPI1Tx = 17|0x100U, /**< SPI1 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 328 | kDmaRequestMux0I2C0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */ |
AnnaBridge | 171:3a7713b1edbc | 329 | kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0 and I2C3. */ |
AnnaBridge | 171:3a7713b1edbc | 330 | kDmaRequestMux0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */ |
AnnaBridge | 171:3a7713b1edbc | 331 | kDmaRequestMux0I2C1I2C2 = 19|0x100U, /**< I2C1 and I2C2. */ |
AnnaBridge | 171:3a7713b1edbc | 332 | kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1 and I2C2. */ |
AnnaBridge | 171:3a7713b1edbc | 333 | kDmaRequestMux0I2C2 = 19|0x100U, /**< I2C1 and I2C2. */ |
AnnaBridge | 171:3a7713b1edbc | 334 | kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */ |
AnnaBridge | 171:3a7713b1edbc | 335 | kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */ |
AnnaBridge | 171:3a7713b1edbc | 336 | kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */ |
AnnaBridge | 171:3a7713b1edbc | 337 | kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */ |
AnnaBridge | 171:3a7713b1edbc | 338 | kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */ |
AnnaBridge | 171:3a7713b1edbc | 339 | kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */ |
AnnaBridge | 171:3a7713b1edbc | 340 | kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */ |
AnnaBridge | 171:3a7713b1edbc | 341 | kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */ |
AnnaBridge | 171:3a7713b1edbc | 342 | kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */ |
AnnaBridge | 171:3a7713b1edbc | 343 | kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */ |
AnnaBridge | 171:3a7713b1edbc | 344 | kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */ |
AnnaBridge | 171:3a7713b1edbc | 345 | kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */ |
AnnaBridge | 171:3a7713b1edbc | 346 | kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */ |
AnnaBridge | 171:3a7713b1edbc | 347 | kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */ |
AnnaBridge | 171:3a7713b1edbc | 348 | kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */ |
AnnaBridge | 171:3a7713b1edbc | 349 | kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */ |
AnnaBridge | 171:3a7713b1edbc | 350 | kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */ |
AnnaBridge | 171:3a7713b1edbc | 351 | kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */ |
AnnaBridge | 171:3a7713b1edbc | 352 | kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V. */ |
AnnaBridge | 171:3a7713b1edbc | 353 | kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V. */ |
AnnaBridge | 171:3a7713b1edbc | 354 | kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */ |
AnnaBridge | 171:3a7713b1edbc | 355 | kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */ |
AnnaBridge | 171:3a7713b1edbc | 356 | kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */ |
AnnaBridge | 171:3a7713b1edbc | 357 | kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */ |
AnnaBridge | 171:3a7713b1edbc | 358 | kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */ |
AnnaBridge | 171:3a7713b1edbc | 359 | kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */ |
AnnaBridge | 171:3a7713b1edbc | 360 | kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */ |
AnnaBridge | 171:3a7713b1edbc | 361 | kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */ |
AnnaBridge | 171:3a7713b1edbc | 362 | kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */ |
AnnaBridge | 171:3a7713b1edbc | 363 | kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */ |
AnnaBridge | 171:3a7713b1edbc | 364 | kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */ |
AnnaBridge | 171:3a7713b1edbc | 365 | kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */ |
AnnaBridge | 171:3a7713b1edbc | 366 | kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */ |
AnnaBridge | 171:3a7713b1edbc | 367 | kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */ |
AnnaBridge | 171:3a7713b1edbc | 368 | kDmaRequestMux0Reserved54 = 54|0x100U, /**< Reserved54 */ |
AnnaBridge | 171:3a7713b1edbc | 369 | kDmaRequestMux0Reserved55 = 55|0x100U, /**< Reserved55 */ |
AnnaBridge | 171:3a7713b1edbc | 370 | kDmaRequestMux0Reserved56 = 56|0x100U, /**< Reserved56 */ |
AnnaBridge | 171:3a7713b1edbc | 371 | kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */ |
AnnaBridge | 171:3a7713b1edbc | 372 | kDmaRequestMux0SPI2Rx = 58|0x100U, /**< SPI2 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 373 | kDmaRequestMux0SPI2Tx = 59|0x100U, /**< SPI2 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 374 | kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */ |
AnnaBridge | 171:3a7713b1edbc | 375 | kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */ |
AnnaBridge | 171:3a7713b1edbc | 376 | kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */ |
AnnaBridge | 171:3a7713b1edbc | 377 | kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */ |
AnnaBridge | 171:3a7713b1edbc | 378 | kDmaRequestMux0Group1Disable = 0|0x200U, /**< DMAMUX TriggerDisabled. */ |
AnnaBridge | 171:3a7713b1edbc | 379 | kDmaRequestMux0Group1FlexIO0Channel0 = 1|0x200U, /**< FLEXIO0. */ |
AnnaBridge | 171:3a7713b1edbc | 380 | kDmaRequestMux0Group1FlexIO0Channel1 = 2|0x200U, /**< FLEXIO0. */ |
AnnaBridge | 171:3a7713b1edbc | 381 | kDmaRequestMux0Group1FlexIO0Channel2 = 3|0x200U, /**< FLEXIO0. */ |
AnnaBridge | 171:3a7713b1edbc | 382 | kDmaRequestMux0Group1FlexIO0Channel3 = 4|0x200U, /**< FLEXIO0. */ |
AnnaBridge | 171:3a7713b1edbc | 383 | kDmaRequestMux0Group1FlexIO0Channel4 = 5|0x200U, /**< FLEXIO0. */ |
AnnaBridge | 171:3a7713b1edbc | 384 | kDmaRequestMux0Group1FlexIO0Channel5 = 6|0x200U, /**< FLEXIO0. */ |
AnnaBridge | 171:3a7713b1edbc | 385 | kDmaRequestMux0Group1FlexIO0Channel6 = 7|0x200U, /**< FLEXIO0. */ |
AnnaBridge | 171:3a7713b1edbc | 386 | kDmaRequestMux0Group1FlexIO0Channel7 = 8|0x200U, /**< FLEXIO0. */ |
AnnaBridge | 171:3a7713b1edbc | 387 | kDmaRequestMux0Group1Reserved9 = 9|0x200U, /**< Reserved9 */ |
AnnaBridge | 171:3a7713b1edbc | 388 | kDmaRequestMux0Group1Reserved10 = 10|0x200U, /**< Reserved10 */ |
AnnaBridge | 171:3a7713b1edbc | 389 | kDmaRequestMux0Group1Reserved11 = 11|0x200U, /**< Reserved11 */ |
AnnaBridge | 171:3a7713b1edbc | 390 | kDmaRequestMux0Group1Reserved12 = 12|0x200U, /**< Reserved12 */ |
AnnaBridge | 171:3a7713b1edbc | 391 | kDmaRequestMux0Group1Reserved13 = 13|0x200U, /**< Reserved13 */ |
AnnaBridge | 171:3a7713b1edbc | 392 | kDmaRequestMux0Group1Reserved14 = 14|0x200U, /**< Reserved14 */ |
AnnaBridge | 171:3a7713b1edbc | 393 | kDmaRequestMux0Group1Reserved15 = 15|0x200U, /**< Reserved15 */ |
AnnaBridge | 171:3a7713b1edbc | 394 | kDmaRequestMux0Group1Reserved16 = 16|0x200U, /**< Reserved16 */ |
AnnaBridge | 171:3a7713b1edbc | 395 | kDmaRequestMux0Group1LTC0InputFIFO = 17|0x200U, /**< LTC0 Input FIFO. */ |
AnnaBridge | 171:3a7713b1edbc | 396 | kDmaRequestMux0Group1LTC0OutputFIFO = 18|0x200U, /**< LTC0 Output FIFO. */ |
AnnaBridge | 171:3a7713b1edbc | 397 | kDmaRequestMux0Group1LTC0PKHA = 19|0x200U, /**< LTC0 PKHA. */ |
AnnaBridge | 171:3a7713b1edbc | 398 | kDmaRequestMux0Group1EMVSIM0Rx = 20|0x200U, /**< EMVSIM0 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 399 | kDmaRequestMux0Group1EMVSIM0Tx = 21|0x200U, /**< EMVSIM0 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 400 | kDmaRequestMux0Group1EMVSIM1Rx = 22|0x200U, /**< EMVSIM1 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 401 | kDmaRequestMux0Group1EMVSIM1Tx = 23|0x200U, /**< EMVSIM1 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 402 | kDmaRequestMux0Group1QSPI0Rx = 24|0x200U, /**< QuadSPI0 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 403 | kDmaRequestMux0Group1QSPI0Tx = 25|0x200U, /**< QuadSPI0 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 404 | kDmaRequestMux0Group1Reserved26 = 26|0x200U, /**< Reserved26 */ |
AnnaBridge | 171:3a7713b1edbc | 405 | kDmaRequestMux0Group1Reserved27 = 27|0x200U, /**< Reserved27 */ |
AnnaBridge | 171:3a7713b1edbc | 406 | kDmaRequestMux0Group1SPI0Rx = 28|0x200U, /**< SPI0 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 407 | kDmaRequestMux0Group1SPI0Tx = 29|0x200U, /**< SPI0 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 408 | kDmaRequestMux0Group1SPI1Rx = 30|0x200U, /**< SPI1 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 409 | kDmaRequestMux0Group1SPI1Tx = 31|0x200U, /**< SPI1 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 410 | kDmaRequestMux0Group1Reserved32 = 32|0x200U, /**< Reserved32 */ |
AnnaBridge | 171:3a7713b1edbc | 411 | kDmaRequestMux0Group1Reserved33 = 33|0x200U, /**< Reserved33 */ |
AnnaBridge | 171:3a7713b1edbc | 412 | kDmaRequestMux0Group1Reserved34 = 34|0x200U, /**< Reserved34 */ |
AnnaBridge | 171:3a7713b1edbc | 413 | kDmaRequestMux0Group1Reserved35 = 35|0x200U, /**< Reserved35 */ |
AnnaBridge | 171:3a7713b1edbc | 414 | kDmaRequestMux0Group1Reserved36 = 36|0x200U, /**< Reserved36 */ |
AnnaBridge | 171:3a7713b1edbc | 415 | kDmaRequestMux0Group1Reserved37 = 37|0x200U, /**< Reserved37 */ |
AnnaBridge | 171:3a7713b1edbc | 416 | kDmaRequestMux0Group1Reserved38 = 38|0x200U, /**< Reserved38 */ |
AnnaBridge | 171:3a7713b1edbc | 417 | kDmaRequestMux0Group1Reserved39 = 39|0x200U, /**< Reserved39 */ |
AnnaBridge | 171:3a7713b1edbc | 418 | kDmaRequestMux0Group1Reserved40 = 40|0x200U, /**< Reserved40 */ |
AnnaBridge | 171:3a7713b1edbc | 419 | kDmaRequestMux0Group1Reserved41 = 41|0x200U, /**< Reserved41 */ |
AnnaBridge | 171:3a7713b1edbc | 420 | kDmaRequestMux0Group1TPM1Channel0 = 42|0x200U, /**< TPM1 C0V. */ |
AnnaBridge | 171:3a7713b1edbc | 421 | kDmaRequestMux0Group1TPM1Channel1 = 43|0x200U, /**< TPM1 C1V. */ |
AnnaBridge | 171:3a7713b1edbc | 422 | kDmaRequestMux0Group1TPM2Channel0 = 44|0x200U, /**< TPM2 C0V. */ |
AnnaBridge | 171:3a7713b1edbc | 423 | kDmaRequestMux0Group1TPM2Channel1 = 45|0x200U, /**< TPM2 C1V. */ |
AnnaBridge | 171:3a7713b1edbc | 424 | kDmaRequestMux0Group1Reserved46 = 46|0x200U, /**< Reserved46 */ |
AnnaBridge | 171:3a7713b1edbc | 425 | kDmaRequestMux0Group1Reserved47 = 47|0x200U, /**< Reserved47 */ |
AnnaBridge | 171:3a7713b1edbc | 426 | kDmaRequestMux0Group1Reserved48 = 48|0x200U, /**< Reserved48 */ |
AnnaBridge | 171:3a7713b1edbc | 427 | kDmaRequestMux0Group1Reserved49 = 49|0x200U, /**< Reserved49 */ |
AnnaBridge | 171:3a7713b1edbc | 428 | kDmaRequestMux0Group1Reserved50 = 50|0x200U, /**< Reserved50 */ |
AnnaBridge | 171:3a7713b1edbc | 429 | kDmaRequestMux0Group1Reserved51 = 51|0x200U, /**< Reserved51 */ |
AnnaBridge | 171:3a7713b1edbc | 430 | kDmaRequestMux0Group1Reserved52 = 52|0x200U, /**< Reserved52 */ |
AnnaBridge | 171:3a7713b1edbc | 431 | kDmaRequestMux0Group1Reserved53 = 53|0x200U, /**< Reserved53 */ |
AnnaBridge | 171:3a7713b1edbc | 432 | kDmaRequestMux0Group1Reserved54 = 54|0x200U, /**< Reserved54 */ |
AnnaBridge | 171:3a7713b1edbc | 433 | kDmaRequestMux0Group1TPM1Overflow = 55|0x200U, /**< TPM1. */ |
AnnaBridge | 171:3a7713b1edbc | 434 | kDmaRequestMux0Group1TPM2Overflow = 56|0x200U, /**< TPM2. */ |
AnnaBridge | 171:3a7713b1edbc | 435 | kDmaRequestMux0Group1Reserved57 = 57|0x200U, /**< Reserved57 */ |
AnnaBridge | 171:3a7713b1edbc | 436 | kDmaRequestMux0Group1Reserved58 = 58|0x200U, /**< Reserved58 */ |
AnnaBridge | 171:3a7713b1edbc | 437 | kDmaRequestMux0Group1Reserved59 = 59|0x200U, /**< Reserved59 */ |
AnnaBridge | 171:3a7713b1edbc | 438 | kDmaRequestMux0Group1AlwaysOn60 = 60|0x200U, /**< DMAMUX Always Enabled slot. */ |
AnnaBridge | 171:3a7713b1edbc | 439 | kDmaRequestMux0Group1AlwaysOn61 = 61|0x200U, /**< DMAMUX Always Enabled slot. */ |
AnnaBridge | 171:3a7713b1edbc | 440 | kDmaRequestMux0Group1AlwaysOn62 = 62|0x200U, /**< DMAMUX Always Enabled slot. */ |
AnnaBridge | 171:3a7713b1edbc | 441 | kDmaRequestMux0Group1AlwaysOn63 = 63|0x200U, /**< DMAMUX Always Enabled slot. */ |
AnnaBridge | 171:3a7713b1edbc | 442 | } dma_request_source_t; |
AnnaBridge | 171:3a7713b1edbc | 443 | |
AnnaBridge | 171:3a7713b1edbc | 444 | /* @} */ |
AnnaBridge | 171:3a7713b1edbc | 445 | |
AnnaBridge | 171:3a7713b1edbc | 446 | |
AnnaBridge | 171:3a7713b1edbc | 447 | /*! |
AnnaBridge | 171:3a7713b1edbc | 448 | * @} |
AnnaBridge | 171:3a7713b1edbc | 449 | */ /* end of group Mapping_Information */ |
AnnaBridge | 171:3a7713b1edbc | 450 | |
AnnaBridge | 171:3a7713b1edbc | 451 | |
AnnaBridge | 171:3a7713b1edbc | 452 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 453 | -- Device Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 454 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 455 | |
AnnaBridge | 171:3a7713b1edbc | 456 | /*! |
AnnaBridge | 171:3a7713b1edbc | 457 | * @addtogroup Peripheral_access_layer Device Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 458 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 459 | */ |
AnnaBridge | 171:3a7713b1edbc | 460 | |
AnnaBridge | 171:3a7713b1edbc | 461 | |
AnnaBridge | 171:3a7713b1edbc | 462 | /* |
AnnaBridge | 171:3a7713b1edbc | 463 | ** Start of section using anonymous unions |
AnnaBridge | 171:3a7713b1edbc | 464 | */ |
AnnaBridge | 171:3a7713b1edbc | 465 | |
AnnaBridge | 171:3a7713b1edbc | 466 | #if defined(__ARMCC_VERSION) |
AnnaBridge | 171:3a7713b1edbc | 467 | #pragma push |
AnnaBridge | 171:3a7713b1edbc | 468 | #pragma anon_unions |
AnnaBridge | 171:3a7713b1edbc | 469 | #elif defined(__CWCC__) |
AnnaBridge | 171:3a7713b1edbc | 470 | #pragma push |
AnnaBridge | 171:3a7713b1edbc | 471 | #pragma cpp_extensions on |
AnnaBridge | 171:3a7713b1edbc | 472 | #elif defined(__GNUC__) |
AnnaBridge | 171:3a7713b1edbc | 473 | /* anonymous unions are enabled by default */ |
AnnaBridge | 171:3a7713b1edbc | 474 | #elif defined(__IAR_SYSTEMS_ICC__) |
AnnaBridge | 171:3a7713b1edbc | 475 | #pragma language=extended |
AnnaBridge | 171:3a7713b1edbc | 476 | #else |
AnnaBridge | 171:3a7713b1edbc | 477 | #error Not supported compiler type |
AnnaBridge | 171:3a7713b1edbc | 478 | #endif |
AnnaBridge | 171:3a7713b1edbc | 479 | |
AnnaBridge | 171:3a7713b1edbc | 480 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 481 | -- ADC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 482 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 483 | |
AnnaBridge | 171:3a7713b1edbc | 484 | /*! |
AnnaBridge | 171:3a7713b1edbc | 485 | * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 486 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 487 | */ |
AnnaBridge | 171:3a7713b1edbc | 488 | |
AnnaBridge | 171:3a7713b1edbc | 489 | /** ADC - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 490 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 491 | __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 492 | __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 493 | __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 494 | __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 495 | __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 496 | __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 497 | __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 498 | __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 499 | __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ |
AnnaBridge | 171:3a7713b1edbc | 500 | __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ |
AnnaBridge | 171:3a7713b1edbc | 501 | __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ |
AnnaBridge | 171:3a7713b1edbc | 502 | __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 503 | __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ |
AnnaBridge | 171:3a7713b1edbc | 504 | __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ |
AnnaBridge | 171:3a7713b1edbc | 505 | __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ |
AnnaBridge | 171:3a7713b1edbc | 506 | __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ |
AnnaBridge | 171:3a7713b1edbc | 507 | __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ |
AnnaBridge | 171:3a7713b1edbc | 508 | __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ |
AnnaBridge | 171:3a7713b1edbc | 509 | uint8_t RESERVED_0[4]; |
AnnaBridge | 171:3a7713b1edbc | 510 | __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ |
AnnaBridge | 171:3a7713b1edbc | 511 | __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ |
AnnaBridge | 171:3a7713b1edbc | 512 | __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ |
AnnaBridge | 171:3a7713b1edbc | 513 | __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ |
AnnaBridge | 171:3a7713b1edbc | 514 | __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ |
AnnaBridge | 171:3a7713b1edbc | 515 | __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ |
AnnaBridge | 171:3a7713b1edbc | 516 | __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ |
AnnaBridge | 171:3a7713b1edbc | 517 | } ADC_Type; |
AnnaBridge | 171:3a7713b1edbc | 518 | |
AnnaBridge | 171:3a7713b1edbc | 519 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 520 | -- ADC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 521 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 522 | |
AnnaBridge | 171:3a7713b1edbc | 523 | /*! |
AnnaBridge | 171:3a7713b1edbc | 524 | * @addtogroup ADC_Register_Masks ADC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 525 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 526 | */ |
AnnaBridge | 171:3a7713b1edbc | 527 | |
AnnaBridge | 171:3a7713b1edbc | 528 | /*! @name SC1 - ADC Status and Control Registers 1 */ |
AnnaBridge | 171:3a7713b1edbc | 529 | #define ADC_SC1_ADCH_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 530 | #define ADC_SC1_ADCH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 531 | #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 532 | #define ADC_SC1_DIFF_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 533 | #define ADC_SC1_DIFF_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 534 | #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 535 | #define ADC_SC1_AIEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 536 | #define ADC_SC1_AIEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 537 | #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 538 | #define ADC_SC1_COCO_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 539 | #define ADC_SC1_COCO_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 540 | #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 541 | |
AnnaBridge | 171:3a7713b1edbc | 542 | /* The count of ADC_SC1 */ |
AnnaBridge | 171:3a7713b1edbc | 543 | #define ADC_SC1_COUNT (2U) |
AnnaBridge | 171:3a7713b1edbc | 544 | |
AnnaBridge | 171:3a7713b1edbc | 545 | /*! @name CFG1 - ADC Configuration Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 546 | #define ADC_CFG1_ADICLK_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 547 | #define ADC_CFG1_ADICLK_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 548 | #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 549 | #define ADC_CFG1_MODE_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 550 | #define ADC_CFG1_MODE_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 551 | #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 552 | #define ADC_CFG1_ADLSMP_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 553 | #define ADC_CFG1_ADLSMP_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 554 | #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 555 | #define ADC_CFG1_ADIV_MASK (0x60U) |
AnnaBridge | 171:3a7713b1edbc | 556 | #define ADC_CFG1_ADIV_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 557 | #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 558 | #define ADC_CFG1_ADLPC_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 559 | #define ADC_CFG1_ADLPC_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 560 | #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 561 | |
AnnaBridge | 171:3a7713b1edbc | 562 | /*! @name CFG2 - ADC Configuration Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 563 | #define ADC_CFG2_ADLSTS_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 564 | #define ADC_CFG2_ADLSTS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 565 | #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 566 | #define ADC_CFG2_ADHSC_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 567 | #define ADC_CFG2_ADHSC_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 568 | #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 569 | #define ADC_CFG2_ADACKEN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 570 | #define ADC_CFG2_ADACKEN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 571 | #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 572 | #define ADC_CFG2_MUXSEL_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 573 | #define ADC_CFG2_MUXSEL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 574 | #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 575 | |
AnnaBridge | 171:3a7713b1edbc | 576 | /*! @name R - ADC Data Result Register */ |
AnnaBridge | 171:3a7713b1edbc | 577 | #define ADC_R_D_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 578 | #define ADC_R_D_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 579 | #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) |
AnnaBridge | 171:3a7713b1edbc | 580 | |
AnnaBridge | 171:3a7713b1edbc | 581 | /* The count of ADC_R */ |
AnnaBridge | 171:3a7713b1edbc | 582 | #define ADC_R_COUNT (2U) |
AnnaBridge | 171:3a7713b1edbc | 583 | |
AnnaBridge | 171:3a7713b1edbc | 584 | /*! @name CV1 - Compare Value Registers */ |
AnnaBridge | 171:3a7713b1edbc | 585 | #define ADC_CV1_CV_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 586 | #define ADC_CV1_CV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 587 | #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 588 | |
AnnaBridge | 171:3a7713b1edbc | 589 | /*! @name CV2 - Compare Value Registers */ |
AnnaBridge | 171:3a7713b1edbc | 590 | #define ADC_CV2_CV_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 591 | #define ADC_CV2_CV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 592 | #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 593 | |
AnnaBridge | 171:3a7713b1edbc | 594 | /*! @name SC2 - Status and Control Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 595 | #define ADC_SC2_REFSEL_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 596 | #define ADC_SC2_REFSEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 597 | #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 598 | #define ADC_SC2_DMAEN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 599 | #define ADC_SC2_DMAEN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 600 | #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 601 | #define ADC_SC2_ACREN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 602 | #define ADC_SC2_ACREN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 603 | #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 604 | #define ADC_SC2_ACFGT_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 605 | #define ADC_SC2_ACFGT_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 606 | #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 607 | #define ADC_SC2_ACFE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 608 | #define ADC_SC2_ACFE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 609 | #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 610 | #define ADC_SC2_ADTRG_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 611 | #define ADC_SC2_ADTRG_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 612 | #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 613 | #define ADC_SC2_ADACT_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 614 | #define ADC_SC2_ADACT_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 615 | #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 616 | |
AnnaBridge | 171:3a7713b1edbc | 617 | /*! @name SC3 - Status and Control Register 3 */ |
AnnaBridge | 171:3a7713b1edbc | 618 | #define ADC_SC3_AVGS_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 619 | #define ADC_SC3_AVGS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 620 | #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 621 | #define ADC_SC3_AVGE_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 622 | #define ADC_SC3_AVGE_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 623 | #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 624 | #define ADC_SC3_ADCO_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 625 | #define ADC_SC3_ADCO_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 626 | #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 627 | #define ADC_SC3_CALF_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 628 | #define ADC_SC3_CALF_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 629 | #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 630 | #define ADC_SC3_CAL_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 631 | #define ADC_SC3_CAL_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 632 | #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 633 | |
AnnaBridge | 171:3a7713b1edbc | 634 | /*! @name OFS - ADC Offset Correction Register */ |
AnnaBridge | 171:3a7713b1edbc | 635 | #define ADC_OFS_OFS_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 636 | #define ADC_OFS_OFS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 637 | #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 638 | |
AnnaBridge | 171:3a7713b1edbc | 639 | /*! @name PG - ADC Plus-Side Gain Register */ |
AnnaBridge | 171:3a7713b1edbc | 640 | #define ADC_PG_PG_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 641 | #define ADC_PG_PG_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 642 | #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 643 | |
AnnaBridge | 171:3a7713b1edbc | 644 | /*! @name MG - ADC Minus-Side Gain Register */ |
AnnaBridge | 171:3a7713b1edbc | 645 | #define ADC_MG_MG_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 646 | #define ADC_MG_MG_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 647 | #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 648 | |
AnnaBridge | 171:3a7713b1edbc | 649 | /*! @name CLPD - ADC Plus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 650 | #define ADC_CLPD_CLPD_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 651 | #define ADC_CLPD_CLPD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 652 | #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 653 | |
AnnaBridge | 171:3a7713b1edbc | 654 | /*! @name CLPS - ADC Plus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 655 | #define ADC_CLPS_CLPS_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 656 | #define ADC_CLPS_CLPS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 657 | #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 658 | |
AnnaBridge | 171:3a7713b1edbc | 659 | /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 660 | #define ADC_CLP4_CLP4_MASK (0x3FFU) |
AnnaBridge | 171:3a7713b1edbc | 661 | #define ADC_CLP4_CLP4_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 662 | #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 663 | |
AnnaBridge | 171:3a7713b1edbc | 664 | /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 665 | #define ADC_CLP3_CLP3_MASK (0x1FFU) |
AnnaBridge | 171:3a7713b1edbc | 666 | #define ADC_CLP3_CLP3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 667 | #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 668 | |
AnnaBridge | 171:3a7713b1edbc | 669 | /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 670 | #define ADC_CLP2_CLP2_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 671 | #define ADC_CLP2_CLP2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 672 | #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 673 | |
AnnaBridge | 171:3a7713b1edbc | 674 | /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 675 | #define ADC_CLP1_CLP1_MASK (0x7FU) |
AnnaBridge | 171:3a7713b1edbc | 676 | #define ADC_CLP1_CLP1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 677 | #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 678 | |
AnnaBridge | 171:3a7713b1edbc | 679 | /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 680 | #define ADC_CLP0_CLP0_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 681 | #define ADC_CLP0_CLP0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 682 | #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 683 | |
AnnaBridge | 171:3a7713b1edbc | 684 | /*! @name CLMD - ADC Minus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 685 | #define ADC_CLMD_CLMD_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 686 | #define ADC_CLMD_CLMD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 687 | #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 688 | |
AnnaBridge | 171:3a7713b1edbc | 689 | /*! @name CLMS - ADC Minus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 690 | #define ADC_CLMS_CLMS_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 691 | #define ADC_CLMS_CLMS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 692 | #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 693 | |
AnnaBridge | 171:3a7713b1edbc | 694 | /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 695 | #define ADC_CLM4_CLM4_MASK (0x3FFU) |
AnnaBridge | 171:3a7713b1edbc | 696 | #define ADC_CLM4_CLM4_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 697 | #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 698 | |
AnnaBridge | 171:3a7713b1edbc | 699 | /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 700 | #define ADC_CLM3_CLM3_MASK (0x1FFU) |
AnnaBridge | 171:3a7713b1edbc | 701 | #define ADC_CLM3_CLM3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 702 | #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 703 | |
AnnaBridge | 171:3a7713b1edbc | 704 | /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 705 | #define ADC_CLM2_CLM2_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 706 | #define ADC_CLM2_CLM2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 707 | #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 708 | |
AnnaBridge | 171:3a7713b1edbc | 709 | /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 710 | #define ADC_CLM1_CLM1_MASK (0x7FU) |
AnnaBridge | 171:3a7713b1edbc | 711 | #define ADC_CLM1_CLM1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 712 | #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 713 | |
AnnaBridge | 171:3a7713b1edbc | 714 | /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 715 | #define ADC_CLM0_CLM0_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 716 | #define ADC_CLM0_CLM0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 717 | #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 718 | |
AnnaBridge | 171:3a7713b1edbc | 719 | |
AnnaBridge | 171:3a7713b1edbc | 720 | /*! |
AnnaBridge | 171:3a7713b1edbc | 721 | * @} |
AnnaBridge | 171:3a7713b1edbc | 722 | */ /* end of group ADC_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 723 | |
AnnaBridge | 171:3a7713b1edbc | 724 | |
AnnaBridge | 171:3a7713b1edbc | 725 | /* ADC - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 726 | /** Peripheral ADC0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 727 | #define ADC0_BASE (0x4003B000u) |
AnnaBridge | 171:3a7713b1edbc | 728 | /** Peripheral ADC0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 729 | #define ADC0 ((ADC_Type *)ADC0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 730 | /** Array initializer of ADC peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 731 | #define ADC_BASE_ADDRS { ADC0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 732 | /** Array initializer of ADC peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 733 | #define ADC_BASE_PTRS { ADC0 } |
AnnaBridge | 171:3a7713b1edbc | 734 | /** Interrupt vectors for the ADC peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 735 | #define ADC_IRQS { ADC0_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 736 | |
AnnaBridge | 171:3a7713b1edbc | 737 | /*! |
AnnaBridge | 171:3a7713b1edbc | 738 | * @} |
AnnaBridge | 171:3a7713b1edbc | 739 | */ /* end of group ADC_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 740 | |
AnnaBridge | 171:3a7713b1edbc | 741 | |
AnnaBridge | 171:3a7713b1edbc | 742 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 743 | -- AIPS Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 744 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 745 | |
AnnaBridge | 171:3a7713b1edbc | 746 | /*! |
AnnaBridge | 171:3a7713b1edbc | 747 | * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 748 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 749 | */ |
AnnaBridge | 171:3a7713b1edbc | 750 | |
AnnaBridge | 171:3a7713b1edbc | 751 | /** AIPS - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 752 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 753 | __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 754 | uint8_t RESERVED_0[28]; |
AnnaBridge | 171:3a7713b1edbc | 755 | __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 756 | __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 757 | __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */ |
AnnaBridge | 171:3a7713b1edbc | 758 | __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */ |
AnnaBridge | 171:3a7713b1edbc | 759 | uint8_t RESERVED_1[16]; |
AnnaBridge | 171:3a7713b1edbc | 760 | __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */ |
AnnaBridge | 171:3a7713b1edbc | 761 | __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */ |
AnnaBridge | 171:3a7713b1edbc | 762 | __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */ |
AnnaBridge | 171:3a7713b1edbc | 763 | __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */ |
AnnaBridge | 171:3a7713b1edbc | 764 | __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */ |
AnnaBridge | 171:3a7713b1edbc | 765 | __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */ |
AnnaBridge | 171:3a7713b1edbc | 766 | __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */ |
AnnaBridge | 171:3a7713b1edbc | 767 | __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */ |
AnnaBridge | 171:3a7713b1edbc | 768 | __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */ |
AnnaBridge | 171:3a7713b1edbc | 769 | __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */ |
AnnaBridge | 171:3a7713b1edbc | 770 | __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */ |
AnnaBridge | 171:3a7713b1edbc | 771 | __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */ |
AnnaBridge | 171:3a7713b1edbc | 772 | } AIPS_Type; |
AnnaBridge | 171:3a7713b1edbc | 773 | |
AnnaBridge | 171:3a7713b1edbc | 774 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 775 | -- AIPS Register Masks |
AnnaBridge | 171:3a7713b1edbc | 776 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 777 | |
AnnaBridge | 171:3a7713b1edbc | 778 | /*! |
AnnaBridge | 171:3a7713b1edbc | 779 | * @addtogroup AIPS_Register_Masks AIPS Register Masks |
AnnaBridge | 171:3a7713b1edbc | 780 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 781 | */ |
AnnaBridge | 171:3a7713b1edbc | 782 | |
AnnaBridge | 171:3a7713b1edbc | 783 | /*! @name MPRA - Master Privilege Register A */ |
AnnaBridge | 171:3a7713b1edbc | 784 | #define AIPS_MPRA_MPL4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 785 | #define AIPS_MPRA_MPL4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 786 | #define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 787 | #define AIPS_MPRA_MTW4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 788 | #define AIPS_MPRA_MTW4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 789 | #define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 790 | #define AIPS_MPRA_MTR4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 791 | #define AIPS_MPRA_MTR4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 792 | #define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 793 | #define AIPS_MPRA_MPL3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 794 | #define AIPS_MPRA_MPL3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 795 | #define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 796 | #define AIPS_MPRA_MTW3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 797 | #define AIPS_MPRA_MTW3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 798 | #define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 799 | #define AIPS_MPRA_MTR3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 800 | #define AIPS_MPRA_MTR3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 801 | #define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 802 | #define AIPS_MPRA_MPL2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 803 | #define AIPS_MPRA_MPL2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 804 | #define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 805 | #define AIPS_MPRA_MTW2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 806 | #define AIPS_MPRA_MTW2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 807 | #define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 808 | #define AIPS_MPRA_MTR2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 809 | #define AIPS_MPRA_MTR2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 810 | #define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 811 | #define AIPS_MPRA_MPL1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 812 | #define AIPS_MPRA_MPL1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 813 | #define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 814 | #define AIPS_MPRA_MTW1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 815 | #define AIPS_MPRA_MTW1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 816 | #define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 817 | #define AIPS_MPRA_MTR1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 818 | #define AIPS_MPRA_MTR1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 819 | #define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 820 | #define AIPS_MPRA_MPL0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 821 | #define AIPS_MPRA_MPL0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 822 | #define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 823 | #define AIPS_MPRA_MTW0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 824 | #define AIPS_MPRA_MTW0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 825 | #define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 826 | #define AIPS_MPRA_MTR0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 827 | #define AIPS_MPRA_MTR0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 828 | #define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 829 | |
AnnaBridge | 171:3a7713b1edbc | 830 | /*! @name PACRA - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 831 | #define AIPS_PACRA_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 832 | #define AIPS_PACRA_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 833 | #define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 834 | #define AIPS_PACRA_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 835 | #define AIPS_PACRA_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 836 | #define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 837 | #define AIPS_PACRA_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 838 | #define AIPS_PACRA_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 839 | #define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 840 | #define AIPS_PACRA_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 841 | #define AIPS_PACRA_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 842 | #define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 843 | #define AIPS_PACRA_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 844 | #define AIPS_PACRA_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 845 | #define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 846 | #define AIPS_PACRA_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 847 | #define AIPS_PACRA_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 848 | #define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 849 | #define AIPS_PACRA_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 850 | #define AIPS_PACRA_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 851 | #define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 852 | #define AIPS_PACRA_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 853 | #define AIPS_PACRA_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 854 | #define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 855 | #define AIPS_PACRA_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 856 | #define AIPS_PACRA_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 857 | #define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 858 | #define AIPS_PACRA_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 859 | #define AIPS_PACRA_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 860 | #define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 861 | #define AIPS_PACRA_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 862 | #define AIPS_PACRA_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 863 | #define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 864 | #define AIPS_PACRA_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 865 | #define AIPS_PACRA_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 866 | #define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 867 | #define AIPS_PACRA_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 868 | #define AIPS_PACRA_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 869 | #define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 870 | #define AIPS_PACRA_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 871 | #define AIPS_PACRA_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 872 | #define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 873 | #define AIPS_PACRA_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 874 | #define AIPS_PACRA_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 875 | #define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 876 | #define AIPS_PACRA_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 877 | #define AIPS_PACRA_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 878 | #define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 879 | #define AIPS_PACRA_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 880 | #define AIPS_PACRA_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 881 | #define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 882 | #define AIPS_PACRA_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 883 | #define AIPS_PACRA_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 884 | #define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 885 | #define AIPS_PACRA_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 886 | #define AIPS_PACRA_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 887 | #define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 888 | #define AIPS_PACRA_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 889 | #define AIPS_PACRA_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 890 | #define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 891 | #define AIPS_PACRA_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 892 | #define AIPS_PACRA_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 893 | #define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 894 | #define AIPS_PACRA_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 895 | #define AIPS_PACRA_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 896 | #define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 897 | #define AIPS_PACRA_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 898 | #define AIPS_PACRA_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 899 | #define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 900 | #define AIPS_PACRA_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 901 | #define AIPS_PACRA_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 902 | #define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 903 | |
AnnaBridge | 171:3a7713b1edbc | 904 | /*! @name PACRB - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 905 | #define AIPS_PACRB_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 906 | #define AIPS_PACRB_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 907 | #define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 908 | #define AIPS_PACRB_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 909 | #define AIPS_PACRB_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 910 | #define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 911 | #define AIPS_PACRB_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 912 | #define AIPS_PACRB_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 913 | #define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 914 | #define AIPS_PACRB_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 915 | #define AIPS_PACRB_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 916 | #define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 917 | #define AIPS_PACRB_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 918 | #define AIPS_PACRB_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 919 | #define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 920 | #define AIPS_PACRB_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 921 | #define AIPS_PACRB_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 922 | #define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 923 | #define AIPS_PACRB_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 924 | #define AIPS_PACRB_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 925 | #define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 926 | #define AIPS_PACRB_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 927 | #define AIPS_PACRB_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 928 | #define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 929 | #define AIPS_PACRB_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 930 | #define AIPS_PACRB_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 931 | #define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 932 | #define AIPS_PACRB_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 933 | #define AIPS_PACRB_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 934 | #define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 935 | #define AIPS_PACRB_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 936 | #define AIPS_PACRB_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 937 | #define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 938 | #define AIPS_PACRB_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 939 | #define AIPS_PACRB_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 940 | #define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 941 | #define AIPS_PACRB_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 942 | #define AIPS_PACRB_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 943 | #define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 944 | #define AIPS_PACRB_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 945 | #define AIPS_PACRB_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 946 | #define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 947 | #define AIPS_PACRB_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 948 | #define AIPS_PACRB_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 949 | #define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 950 | #define AIPS_PACRB_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 951 | #define AIPS_PACRB_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 952 | #define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 953 | #define AIPS_PACRB_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 954 | #define AIPS_PACRB_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 955 | #define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 956 | #define AIPS_PACRB_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 957 | #define AIPS_PACRB_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 958 | #define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 959 | #define AIPS_PACRB_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 960 | #define AIPS_PACRB_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 961 | #define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 962 | #define AIPS_PACRB_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 963 | #define AIPS_PACRB_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 964 | #define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 965 | #define AIPS_PACRB_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 966 | #define AIPS_PACRB_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 967 | #define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 968 | #define AIPS_PACRB_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 969 | #define AIPS_PACRB_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 970 | #define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 971 | #define AIPS_PACRB_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 972 | #define AIPS_PACRB_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 973 | #define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 974 | #define AIPS_PACRB_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 975 | #define AIPS_PACRB_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 976 | #define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 977 | |
AnnaBridge | 171:3a7713b1edbc | 978 | /*! @name PACRC - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 979 | #define AIPS_PACRC_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 980 | #define AIPS_PACRC_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 981 | #define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 982 | #define AIPS_PACRC_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 983 | #define AIPS_PACRC_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 984 | #define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 985 | #define AIPS_PACRC_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 986 | #define AIPS_PACRC_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 987 | #define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 988 | #define AIPS_PACRC_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 989 | #define AIPS_PACRC_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 990 | #define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 991 | #define AIPS_PACRC_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 992 | #define AIPS_PACRC_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 993 | #define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 994 | #define AIPS_PACRC_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 995 | #define AIPS_PACRC_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 996 | #define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 997 | #define AIPS_PACRC_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 998 | #define AIPS_PACRC_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 999 | #define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1000 | #define AIPS_PACRC_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1001 | #define AIPS_PACRC_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1002 | #define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1003 | #define AIPS_PACRC_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1004 | #define AIPS_PACRC_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1005 | #define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1006 | #define AIPS_PACRC_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1007 | #define AIPS_PACRC_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1008 | #define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1009 | #define AIPS_PACRC_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1010 | #define AIPS_PACRC_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1011 | #define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1012 | #define AIPS_PACRC_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1013 | #define AIPS_PACRC_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1014 | #define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1015 | #define AIPS_PACRC_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1016 | #define AIPS_PACRC_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1017 | #define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1018 | #define AIPS_PACRC_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1019 | #define AIPS_PACRC_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1020 | #define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1021 | #define AIPS_PACRC_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1022 | #define AIPS_PACRC_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1023 | #define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1024 | #define AIPS_PACRC_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1025 | #define AIPS_PACRC_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1026 | #define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1027 | #define AIPS_PACRC_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1028 | #define AIPS_PACRC_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1029 | #define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1030 | #define AIPS_PACRC_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1031 | #define AIPS_PACRC_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1032 | #define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1033 | #define AIPS_PACRC_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1034 | #define AIPS_PACRC_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1035 | #define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1036 | #define AIPS_PACRC_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1037 | #define AIPS_PACRC_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1038 | #define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1039 | #define AIPS_PACRC_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1040 | #define AIPS_PACRC_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1041 | #define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1042 | #define AIPS_PACRC_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1043 | #define AIPS_PACRC_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1044 | #define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1045 | #define AIPS_PACRC_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1046 | #define AIPS_PACRC_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1047 | #define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1048 | #define AIPS_PACRC_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1049 | #define AIPS_PACRC_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1050 | #define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1051 | |
AnnaBridge | 171:3a7713b1edbc | 1052 | /*! @name PACRD - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1053 | #define AIPS_PACRD_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1054 | #define AIPS_PACRD_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1055 | #define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1056 | #define AIPS_PACRD_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1057 | #define AIPS_PACRD_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1058 | #define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1059 | #define AIPS_PACRD_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1060 | #define AIPS_PACRD_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1061 | #define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1062 | #define AIPS_PACRD_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1063 | #define AIPS_PACRD_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1064 | #define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1065 | #define AIPS_PACRD_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1066 | #define AIPS_PACRD_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1067 | #define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1068 | #define AIPS_PACRD_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1069 | #define AIPS_PACRD_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1070 | #define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1071 | #define AIPS_PACRD_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1072 | #define AIPS_PACRD_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1073 | #define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1074 | #define AIPS_PACRD_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1075 | #define AIPS_PACRD_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1076 | #define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1077 | #define AIPS_PACRD_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1078 | #define AIPS_PACRD_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1079 | #define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1080 | #define AIPS_PACRD_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1081 | #define AIPS_PACRD_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1082 | #define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1083 | #define AIPS_PACRD_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1084 | #define AIPS_PACRD_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1085 | #define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1086 | #define AIPS_PACRD_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1087 | #define AIPS_PACRD_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1088 | #define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1089 | #define AIPS_PACRD_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1090 | #define AIPS_PACRD_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1091 | #define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1092 | #define AIPS_PACRD_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1093 | #define AIPS_PACRD_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1094 | #define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1095 | #define AIPS_PACRD_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1096 | #define AIPS_PACRD_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1097 | #define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1098 | #define AIPS_PACRD_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1099 | #define AIPS_PACRD_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1100 | #define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1101 | #define AIPS_PACRD_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1102 | #define AIPS_PACRD_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1103 | #define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1104 | #define AIPS_PACRD_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1105 | #define AIPS_PACRD_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1106 | #define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1107 | #define AIPS_PACRD_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1108 | #define AIPS_PACRD_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1109 | #define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1110 | #define AIPS_PACRD_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1111 | #define AIPS_PACRD_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1112 | #define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1113 | #define AIPS_PACRD_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1114 | #define AIPS_PACRD_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1115 | #define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1116 | #define AIPS_PACRD_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1117 | #define AIPS_PACRD_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1118 | #define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1119 | #define AIPS_PACRD_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1120 | #define AIPS_PACRD_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1121 | #define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1122 | #define AIPS_PACRD_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1123 | #define AIPS_PACRD_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1124 | #define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1125 | |
AnnaBridge | 171:3a7713b1edbc | 1126 | /*! @name PACRE - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1127 | #define AIPS_PACRE_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1128 | #define AIPS_PACRE_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1129 | #define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1130 | #define AIPS_PACRE_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1131 | #define AIPS_PACRE_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1132 | #define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1133 | #define AIPS_PACRE_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1134 | #define AIPS_PACRE_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1135 | #define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1136 | #define AIPS_PACRE_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1137 | #define AIPS_PACRE_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1138 | #define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1139 | #define AIPS_PACRE_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1140 | #define AIPS_PACRE_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1141 | #define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1142 | #define AIPS_PACRE_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1143 | #define AIPS_PACRE_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1144 | #define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1145 | #define AIPS_PACRE_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1146 | #define AIPS_PACRE_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1147 | #define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1148 | #define AIPS_PACRE_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1149 | #define AIPS_PACRE_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1150 | #define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1151 | #define AIPS_PACRE_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1152 | #define AIPS_PACRE_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1153 | #define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1154 | #define AIPS_PACRE_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1155 | #define AIPS_PACRE_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1156 | #define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1157 | #define AIPS_PACRE_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1158 | #define AIPS_PACRE_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1159 | #define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1160 | #define AIPS_PACRE_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1161 | #define AIPS_PACRE_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1162 | #define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1163 | #define AIPS_PACRE_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1164 | #define AIPS_PACRE_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1165 | #define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1166 | #define AIPS_PACRE_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1167 | #define AIPS_PACRE_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1168 | #define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1169 | #define AIPS_PACRE_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1170 | #define AIPS_PACRE_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1171 | #define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1172 | #define AIPS_PACRE_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1173 | #define AIPS_PACRE_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1174 | #define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1175 | #define AIPS_PACRE_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1176 | #define AIPS_PACRE_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1177 | #define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1178 | #define AIPS_PACRE_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1179 | #define AIPS_PACRE_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1180 | #define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1181 | #define AIPS_PACRE_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1182 | #define AIPS_PACRE_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1183 | #define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1184 | #define AIPS_PACRE_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1185 | #define AIPS_PACRE_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1186 | #define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1187 | #define AIPS_PACRE_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1188 | #define AIPS_PACRE_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1189 | #define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1190 | #define AIPS_PACRE_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1191 | #define AIPS_PACRE_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1192 | #define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1193 | #define AIPS_PACRE_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1194 | #define AIPS_PACRE_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1195 | #define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1196 | #define AIPS_PACRE_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1197 | #define AIPS_PACRE_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1198 | #define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1199 | |
AnnaBridge | 171:3a7713b1edbc | 1200 | /*! @name PACRF - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1201 | #define AIPS_PACRF_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1202 | #define AIPS_PACRF_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1203 | #define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1204 | #define AIPS_PACRF_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1205 | #define AIPS_PACRF_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1206 | #define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1207 | #define AIPS_PACRF_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1208 | #define AIPS_PACRF_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1209 | #define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1210 | #define AIPS_PACRF_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1211 | #define AIPS_PACRF_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1212 | #define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1213 | #define AIPS_PACRF_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1214 | #define AIPS_PACRF_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1215 | #define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1216 | #define AIPS_PACRF_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1217 | #define AIPS_PACRF_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1218 | #define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1219 | #define AIPS_PACRF_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1220 | #define AIPS_PACRF_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1221 | #define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1222 | #define AIPS_PACRF_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1223 | #define AIPS_PACRF_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1224 | #define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1225 | #define AIPS_PACRF_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1226 | #define AIPS_PACRF_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1227 | #define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1228 | #define AIPS_PACRF_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1229 | #define AIPS_PACRF_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1230 | #define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1231 | #define AIPS_PACRF_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1232 | #define AIPS_PACRF_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1233 | #define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1234 | #define AIPS_PACRF_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1235 | #define AIPS_PACRF_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1236 | #define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1237 | #define AIPS_PACRF_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1238 | #define AIPS_PACRF_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1239 | #define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1240 | #define AIPS_PACRF_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1241 | #define AIPS_PACRF_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1242 | #define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1243 | #define AIPS_PACRF_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1244 | #define AIPS_PACRF_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1245 | #define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1246 | #define AIPS_PACRF_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1247 | #define AIPS_PACRF_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1248 | #define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1249 | #define AIPS_PACRF_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1250 | #define AIPS_PACRF_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1251 | #define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1252 | #define AIPS_PACRF_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1253 | #define AIPS_PACRF_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1254 | #define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1255 | #define AIPS_PACRF_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1256 | #define AIPS_PACRF_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1257 | #define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1258 | #define AIPS_PACRF_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1259 | #define AIPS_PACRF_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1260 | #define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1261 | #define AIPS_PACRF_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1262 | #define AIPS_PACRF_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1263 | #define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1264 | #define AIPS_PACRF_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1265 | #define AIPS_PACRF_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1266 | #define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1267 | #define AIPS_PACRF_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1268 | #define AIPS_PACRF_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1269 | #define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1270 | #define AIPS_PACRF_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1271 | #define AIPS_PACRF_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1272 | #define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1273 | |
AnnaBridge | 171:3a7713b1edbc | 1274 | /*! @name PACRG - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1275 | #define AIPS_PACRG_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1276 | #define AIPS_PACRG_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1277 | #define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1278 | #define AIPS_PACRG_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1279 | #define AIPS_PACRG_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1280 | #define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1281 | #define AIPS_PACRG_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1282 | #define AIPS_PACRG_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1283 | #define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1284 | #define AIPS_PACRG_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1285 | #define AIPS_PACRG_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1286 | #define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1287 | #define AIPS_PACRG_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1288 | #define AIPS_PACRG_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1289 | #define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1290 | #define AIPS_PACRG_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1291 | #define AIPS_PACRG_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1292 | #define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1293 | #define AIPS_PACRG_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1294 | #define AIPS_PACRG_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1295 | #define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1296 | #define AIPS_PACRG_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1297 | #define AIPS_PACRG_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1298 | #define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1299 | #define AIPS_PACRG_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1300 | #define AIPS_PACRG_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1301 | #define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1302 | #define AIPS_PACRG_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1303 | #define AIPS_PACRG_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1304 | #define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1305 | #define AIPS_PACRG_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1306 | #define AIPS_PACRG_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1307 | #define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1308 | #define AIPS_PACRG_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1309 | #define AIPS_PACRG_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1310 | #define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1311 | #define AIPS_PACRG_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1312 | #define AIPS_PACRG_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1313 | #define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1314 | #define AIPS_PACRG_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1315 | #define AIPS_PACRG_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1316 | #define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1317 | #define AIPS_PACRG_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1318 | #define AIPS_PACRG_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1319 | #define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1320 | #define AIPS_PACRG_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1321 | #define AIPS_PACRG_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1322 | #define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1323 | #define AIPS_PACRG_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1324 | #define AIPS_PACRG_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1325 | #define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1326 | #define AIPS_PACRG_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1327 | #define AIPS_PACRG_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1328 | #define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1329 | #define AIPS_PACRG_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1330 | #define AIPS_PACRG_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1331 | #define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1332 | #define AIPS_PACRG_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1333 | #define AIPS_PACRG_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1334 | #define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1335 | #define AIPS_PACRG_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1336 | #define AIPS_PACRG_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1337 | #define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1338 | #define AIPS_PACRG_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1339 | #define AIPS_PACRG_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1340 | #define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1341 | #define AIPS_PACRG_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1342 | #define AIPS_PACRG_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1343 | #define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1344 | #define AIPS_PACRG_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1345 | #define AIPS_PACRG_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1346 | #define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1347 | |
AnnaBridge | 171:3a7713b1edbc | 1348 | /*! @name PACRH - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1349 | #define AIPS_PACRH_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1350 | #define AIPS_PACRH_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1351 | #define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1352 | #define AIPS_PACRH_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1353 | #define AIPS_PACRH_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1354 | #define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1355 | #define AIPS_PACRH_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1356 | #define AIPS_PACRH_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1357 | #define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1358 | #define AIPS_PACRH_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1359 | #define AIPS_PACRH_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1360 | #define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1361 | #define AIPS_PACRH_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1362 | #define AIPS_PACRH_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1363 | #define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1364 | #define AIPS_PACRH_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1365 | #define AIPS_PACRH_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1366 | #define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1367 | #define AIPS_PACRH_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1368 | #define AIPS_PACRH_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1369 | #define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1370 | #define AIPS_PACRH_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1371 | #define AIPS_PACRH_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1372 | #define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1373 | #define AIPS_PACRH_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1374 | #define AIPS_PACRH_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1375 | #define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1376 | #define AIPS_PACRH_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1377 | #define AIPS_PACRH_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1378 | #define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1379 | #define AIPS_PACRH_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1380 | #define AIPS_PACRH_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1381 | #define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1382 | #define AIPS_PACRH_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1383 | #define AIPS_PACRH_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1384 | #define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1385 | #define AIPS_PACRH_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1386 | #define AIPS_PACRH_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1387 | #define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1388 | #define AIPS_PACRH_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1389 | #define AIPS_PACRH_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1390 | #define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1391 | #define AIPS_PACRH_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1392 | #define AIPS_PACRH_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1393 | #define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1394 | #define AIPS_PACRH_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1395 | #define AIPS_PACRH_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1396 | #define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1397 | #define AIPS_PACRH_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1398 | #define AIPS_PACRH_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1399 | #define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1400 | #define AIPS_PACRH_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1401 | #define AIPS_PACRH_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1402 | #define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1403 | #define AIPS_PACRH_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1404 | #define AIPS_PACRH_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1405 | #define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1406 | #define AIPS_PACRH_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1407 | #define AIPS_PACRH_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1408 | #define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1409 | #define AIPS_PACRH_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1410 | #define AIPS_PACRH_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1411 | #define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1412 | #define AIPS_PACRH_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1413 | #define AIPS_PACRH_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1414 | #define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1415 | #define AIPS_PACRH_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1416 | #define AIPS_PACRH_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1417 | #define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1418 | #define AIPS_PACRH_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1419 | #define AIPS_PACRH_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1420 | #define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1421 | |
AnnaBridge | 171:3a7713b1edbc | 1422 | /*! @name PACRI - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1423 | #define AIPS_PACRI_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1424 | #define AIPS_PACRI_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1425 | #define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1426 | #define AIPS_PACRI_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1427 | #define AIPS_PACRI_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1428 | #define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1429 | #define AIPS_PACRI_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1430 | #define AIPS_PACRI_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1431 | #define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1432 | #define AIPS_PACRI_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1433 | #define AIPS_PACRI_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1434 | #define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1435 | #define AIPS_PACRI_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1436 | #define AIPS_PACRI_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1437 | #define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1438 | #define AIPS_PACRI_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1439 | #define AIPS_PACRI_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1440 | #define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1441 | #define AIPS_PACRI_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1442 | #define AIPS_PACRI_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1443 | #define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1444 | #define AIPS_PACRI_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1445 | #define AIPS_PACRI_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1446 | #define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1447 | #define AIPS_PACRI_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1448 | #define AIPS_PACRI_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1449 | #define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1450 | #define AIPS_PACRI_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1451 | #define AIPS_PACRI_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1452 | #define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1453 | #define AIPS_PACRI_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1454 | #define AIPS_PACRI_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1455 | #define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1456 | #define AIPS_PACRI_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1457 | #define AIPS_PACRI_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1458 | #define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1459 | #define AIPS_PACRI_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1460 | #define AIPS_PACRI_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1461 | #define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1462 | #define AIPS_PACRI_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1463 | #define AIPS_PACRI_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1464 | #define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1465 | #define AIPS_PACRI_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1466 | #define AIPS_PACRI_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1467 | #define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1468 | #define AIPS_PACRI_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1469 | #define AIPS_PACRI_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1470 | #define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1471 | #define AIPS_PACRI_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1472 | #define AIPS_PACRI_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1473 | #define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1474 | #define AIPS_PACRI_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1475 | #define AIPS_PACRI_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1476 | #define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1477 | #define AIPS_PACRI_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1478 | #define AIPS_PACRI_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1479 | #define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1480 | #define AIPS_PACRI_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1481 | #define AIPS_PACRI_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1482 | #define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1483 | #define AIPS_PACRI_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1484 | #define AIPS_PACRI_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1485 | #define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1486 | #define AIPS_PACRI_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1487 | #define AIPS_PACRI_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1488 | #define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1489 | #define AIPS_PACRI_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1490 | #define AIPS_PACRI_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1491 | #define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1492 | #define AIPS_PACRI_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1493 | #define AIPS_PACRI_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1494 | #define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1495 | |
AnnaBridge | 171:3a7713b1edbc | 1496 | /*! @name PACRJ - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1497 | #define AIPS_PACRJ_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1498 | #define AIPS_PACRJ_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1499 | #define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1500 | #define AIPS_PACRJ_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1501 | #define AIPS_PACRJ_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1502 | #define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1503 | #define AIPS_PACRJ_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1504 | #define AIPS_PACRJ_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1505 | #define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1506 | #define AIPS_PACRJ_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1507 | #define AIPS_PACRJ_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1508 | #define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1509 | #define AIPS_PACRJ_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1510 | #define AIPS_PACRJ_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1511 | #define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1512 | #define AIPS_PACRJ_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1513 | #define AIPS_PACRJ_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1514 | #define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1515 | #define AIPS_PACRJ_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1516 | #define AIPS_PACRJ_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1517 | #define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1518 | #define AIPS_PACRJ_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1519 | #define AIPS_PACRJ_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1520 | #define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1521 | #define AIPS_PACRJ_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1522 | #define AIPS_PACRJ_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1523 | #define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1524 | #define AIPS_PACRJ_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1525 | #define AIPS_PACRJ_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1526 | #define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1527 | #define AIPS_PACRJ_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1528 | #define AIPS_PACRJ_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1529 | #define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1530 | #define AIPS_PACRJ_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1531 | #define AIPS_PACRJ_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1532 | #define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1533 | #define AIPS_PACRJ_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1534 | #define AIPS_PACRJ_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1535 | #define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1536 | #define AIPS_PACRJ_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1537 | #define AIPS_PACRJ_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1538 | #define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1539 | #define AIPS_PACRJ_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1540 | #define AIPS_PACRJ_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1541 | #define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1542 | #define AIPS_PACRJ_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1543 | #define AIPS_PACRJ_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1544 | #define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1545 | #define AIPS_PACRJ_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1546 | #define AIPS_PACRJ_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1547 | #define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1548 | #define AIPS_PACRJ_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1549 | #define AIPS_PACRJ_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1550 | #define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1551 | #define AIPS_PACRJ_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1552 | #define AIPS_PACRJ_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1553 | #define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1554 | #define AIPS_PACRJ_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1555 | #define AIPS_PACRJ_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1556 | #define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1557 | #define AIPS_PACRJ_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1558 | #define AIPS_PACRJ_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1559 | #define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1560 | #define AIPS_PACRJ_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1561 | #define AIPS_PACRJ_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1562 | #define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1563 | #define AIPS_PACRJ_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1564 | #define AIPS_PACRJ_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1565 | #define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1566 | #define AIPS_PACRJ_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1567 | #define AIPS_PACRJ_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1568 | #define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1569 | |
AnnaBridge | 171:3a7713b1edbc | 1570 | /*! @name PACRK - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1571 | #define AIPS_PACRK_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1572 | #define AIPS_PACRK_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1573 | #define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1574 | #define AIPS_PACRK_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1575 | #define AIPS_PACRK_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1576 | #define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1577 | #define AIPS_PACRK_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1578 | #define AIPS_PACRK_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1579 | #define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1580 | #define AIPS_PACRK_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1581 | #define AIPS_PACRK_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1582 | #define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1583 | #define AIPS_PACRK_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1584 | #define AIPS_PACRK_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1585 | #define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1586 | #define AIPS_PACRK_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1587 | #define AIPS_PACRK_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1588 | #define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1589 | #define AIPS_PACRK_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1590 | #define AIPS_PACRK_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1591 | #define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1592 | #define AIPS_PACRK_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1593 | #define AIPS_PACRK_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1594 | #define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1595 | #define AIPS_PACRK_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1596 | #define AIPS_PACRK_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1597 | #define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1598 | #define AIPS_PACRK_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1599 | #define AIPS_PACRK_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1600 | #define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1601 | #define AIPS_PACRK_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1602 | #define AIPS_PACRK_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1603 | #define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1604 | #define AIPS_PACRK_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1605 | #define AIPS_PACRK_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1606 | #define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1607 | #define AIPS_PACRK_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1608 | #define AIPS_PACRK_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1609 | #define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1610 | #define AIPS_PACRK_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1611 | #define AIPS_PACRK_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1612 | #define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1613 | #define AIPS_PACRK_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1614 | #define AIPS_PACRK_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1615 | #define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1616 | #define AIPS_PACRK_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1617 | #define AIPS_PACRK_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1618 | #define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1619 | #define AIPS_PACRK_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1620 | #define AIPS_PACRK_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1621 | #define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1622 | #define AIPS_PACRK_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1623 | #define AIPS_PACRK_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1624 | #define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1625 | #define AIPS_PACRK_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1626 | #define AIPS_PACRK_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1627 | #define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1628 | #define AIPS_PACRK_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1629 | #define AIPS_PACRK_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1630 | #define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1631 | #define AIPS_PACRK_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1632 | #define AIPS_PACRK_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1633 | #define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1634 | #define AIPS_PACRK_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1635 | #define AIPS_PACRK_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1636 | #define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1637 | #define AIPS_PACRK_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1638 | #define AIPS_PACRK_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1639 | #define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1640 | #define AIPS_PACRK_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1641 | #define AIPS_PACRK_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1642 | #define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1643 | |
AnnaBridge | 171:3a7713b1edbc | 1644 | /*! @name PACRL - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1645 | #define AIPS_PACRL_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1646 | #define AIPS_PACRL_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1647 | #define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1648 | #define AIPS_PACRL_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1649 | #define AIPS_PACRL_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1650 | #define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1651 | #define AIPS_PACRL_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1652 | #define AIPS_PACRL_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1653 | #define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1654 | #define AIPS_PACRL_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1655 | #define AIPS_PACRL_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1656 | #define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1657 | #define AIPS_PACRL_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1658 | #define AIPS_PACRL_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1659 | #define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1660 | #define AIPS_PACRL_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1661 | #define AIPS_PACRL_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1662 | #define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1663 | #define AIPS_PACRL_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1664 | #define AIPS_PACRL_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1665 | #define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1666 | #define AIPS_PACRL_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1667 | #define AIPS_PACRL_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1668 | #define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1669 | #define AIPS_PACRL_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1670 | #define AIPS_PACRL_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1671 | #define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1672 | #define AIPS_PACRL_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1673 | #define AIPS_PACRL_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1674 | #define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1675 | #define AIPS_PACRL_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1676 | #define AIPS_PACRL_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1677 | #define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1678 | #define AIPS_PACRL_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1679 | #define AIPS_PACRL_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1680 | #define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1681 | #define AIPS_PACRL_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1682 | #define AIPS_PACRL_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1683 | #define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1684 | #define AIPS_PACRL_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1685 | #define AIPS_PACRL_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1686 | #define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1687 | #define AIPS_PACRL_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1688 | #define AIPS_PACRL_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1689 | #define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1690 | #define AIPS_PACRL_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1691 | #define AIPS_PACRL_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1692 | #define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1693 | #define AIPS_PACRL_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1694 | #define AIPS_PACRL_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1695 | #define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1696 | #define AIPS_PACRL_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1697 | #define AIPS_PACRL_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1698 | #define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1699 | #define AIPS_PACRL_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1700 | #define AIPS_PACRL_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1701 | #define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1702 | #define AIPS_PACRL_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1703 | #define AIPS_PACRL_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1704 | #define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1705 | #define AIPS_PACRL_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1706 | #define AIPS_PACRL_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1707 | #define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1708 | #define AIPS_PACRL_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1709 | #define AIPS_PACRL_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1710 | #define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1711 | #define AIPS_PACRL_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1712 | #define AIPS_PACRL_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1713 | #define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1714 | #define AIPS_PACRL_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1715 | #define AIPS_PACRL_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1716 | #define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1717 | |
AnnaBridge | 171:3a7713b1edbc | 1718 | /*! @name PACRM - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1719 | #define AIPS_PACRM_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1720 | #define AIPS_PACRM_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1721 | #define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1722 | #define AIPS_PACRM_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1723 | #define AIPS_PACRM_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1724 | #define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1725 | #define AIPS_PACRM_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1726 | #define AIPS_PACRM_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1727 | #define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1728 | #define AIPS_PACRM_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1729 | #define AIPS_PACRM_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1730 | #define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1731 | #define AIPS_PACRM_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1732 | #define AIPS_PACRM_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1733 | #define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1734 | #define AIPS_PACRM_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1735 | #define AIPS_PACRM_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1736 | #define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1737 | #define AIPS_PACRM_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1738 | #define AIPS_PACRM_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1739 | #define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1740 | #define AIPS_PACRM_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1741 | #define AIPS_PACRM_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1742 | #define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1743 | #define AIPS_PACRM_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1744 | #define AIPS_PACRM_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1745 | #define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1746 | #define AIPS_PACRM_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1747 | #define AIPS_PACRM_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1748 | #define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1749 | #define AIPS_PACRM_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1750 | #define AIPS_PACRM_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1751 | #define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1752 | #define AIPS_PACRM_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1753 | #define AIPS_PACRM_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1754 | #define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1755 | #define AIPS_PACRM_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1756 | #define AIPS_PACRM_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1757 | #define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1758 | #define AIPS_PACRM_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1759 | #define AIPS_PACRM_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1760 | #define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1761 | #define AIPS_PACRM_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1762 | #define AIPS_PACRM_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1763 | #define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1764 | #define AIPS_PACRM_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1765 | #define AIPS_PACRM_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1766 | #define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1767 | #define AIPS_PACRM_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1768 | #define AIPS_PACRM_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1769 | #define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1770 | #define AIPS_PACRM_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1771 | #define AIPS_PACRM_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1772 | #define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1773 | #define AIPS_PACRM_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1774 | #define AIPS_PACRM_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1775 | #define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1776 | #define AIPS_PACRM_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1777 | #define AIPS_PACRM_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1778 | #define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1779 | #define AIPS_PACRM_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1780 | #define AIPS_PACRM_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1781 | #define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1782 | #define AIPS_PACRM_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1783 | #define AIPS_PACRM_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1784 | #define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1785 | #define AIPS_PACRM_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1786 | #define AIPS_PACRM_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1787 | #define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1788 | #define AIPS_PACRM_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1789 | #define AIPS_PACRM_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1790 | #define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1791 | |
AnnaBridge | 171:3a7713b1edbc | 1792 | /*! @name PACRN - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1793 | #define AIPS_PACRN_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1794 | #define AIPS_PACRN_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1795 | #define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1796 | #define AIPS_PACRN_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1797 | #define AIPS_PACRN_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1798 | #define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1799 | #define AIPS_PACRN_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1800 | #define AIPS_PACRN_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1801 | #define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1802 | #define AIPS_PACRN_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1803 | #define AIPS_PACRN_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1804 | #define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1805 | #define AIPS_PACRN_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1806 | #define AIPS_PACRN_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1807 | #define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1808 | #define AIPS_PACRN_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1809 | #define AIPS_PACRN_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1810 | #define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1811 | #define AIPS_PACRN_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1812 | #define AIPS_PACRN_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1813 | #define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1814 | #define AIPS_PACRN_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1815 | #define AIPS_PACRN_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1816 | #define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1817 | #define AIPS_PACRN_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1818 | #define AIPS_PACRN_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1819 | #define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1820 | #define AIPS_PACRN_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1821 | #define AIPS_PACRN_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1822 | #define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1823 | #define AIPS_PACRN_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1824 | #define AIPS_PACRN_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1825 | #define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1826 | #define AIPS_PACRN_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1827 | #define AIPS_PACRN_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1828 | #define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1829 | #define AIPS_PACRN_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1830 | #define AIPS_PACRN_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1831 | #define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1832 | #define AIPS_PACRN_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1833 | #define AIPS_PACRN_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1834 | #define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1835 | #define AIPS_PACRN_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1836 | #define AIPS_PACRN_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1837 | #define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1838 | #define AIPS_PACRN_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1839 | #define AIPS_PACRN_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1840 | #define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1841 | #define AIPS_PACRN_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1842 | #define AIPS_PACRN_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1843 | #define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1844 | #define AIPS_PACRN_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1845 | #define AIPS_PACRN_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1846 | #define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1847 | #define AIPS_PACRN_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1848 | #define AIPS_PACRN_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1849 | #define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1850 | #define AIPS_PACRN_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1851 | #define AIPS_PACRN_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1852 | #define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1853 | #define AIPS_PACRN_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1854 | #define AIPS_PACRN_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1855 | #define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1856 | #define AIPS_PACRN_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1857 | #define AIPS_PACRN_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1858 | #define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1859 | #define AIPS_PACRN_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1860 | #define AIPS_PACRN_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1861 | #define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1862 | #define AIPS_PACRN_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1863 | #define AIPS_PACRN_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1864 | #define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1865 | |
AnnaBridge | 171:3a7713b1edbc | 1866 | /*! @name PACRO - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1867 | #define AIPS_PACRO_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1868 | #define AIPS_PACRO_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1869 | #define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1870 | #define AIPS_PACRO_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1871 | #define AIPS_PACRO_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1872 | #define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1873 | #define AIPS_PACRO_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1874 | #define AIPS_PACRO_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1875 | #define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1876 | #define AIPS_PACRO_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1877 | #define AIPS_PACRO_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1878 | #define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1879 | #define AIPS_PACRO_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1880 | #define AIPS_PACRO_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1881 | #define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1882 | #define AIPS_PACRO_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1883 | #define AIPS_PACRO_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1884 | #define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1885 | #define AIPS_PACRO_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1886 | #define AIPS_PACRO_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1887 | #define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1888 | #define AIPS_PACRO_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1889 | #define AIPS_PACRO_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1890 | #define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1891 | #define AIPS_PACRO_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1892 | #define AIPS_PACRO_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1893 | #define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1894 | #define AIPS_PACRO_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1895 | #define AIPS_PACRO_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1896 | #define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1897 | #define AIPS_PACRO_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1898 | #define AIPS_PACRO_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1899 | #define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1900 | #define AIPS_PACRO_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1901 | #define AIPS_PACRO_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1902 | #define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1903 | #define AIPS_PACRO_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1904 | #define AIPS_PACRO_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1905 | #define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1906 | #define AIPS_PACRO_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1907 | #define AIPS_PACRO_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1908 | #define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1909 | #define AIPS_PACRO_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1910 | #define AIPS_PACRO_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1911 | #define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1912 | #define AIPS_PACRO_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1913 | #define AIPS_PACRO_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1914 | #define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1915 | #define AIPS_PACRO_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1916 | #define AIPS_PACRO_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1917 | #define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1918 | #define AIPS_PACRO_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1919 | #define AIPS_PACRO_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1920 | #define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1921 | #define AIPS_PACRO_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1922 | #define AIPS_PACRO_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1923 | #define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1924 | #define AIPS_PACRO_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1925 | #define AIPS_PACRO_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1926 | #define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1927 | #define AIPS_PACRO_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1928 | #define AIPS_PACRO_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1929 | #define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1930 | #define AIPS_PACRO_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1931 | #define AIPS_PACRO_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1932 | #define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1933 | #define AIPS_PACRO_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1934 | #define AIPS_PACRO_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1935 | #define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1936 | #define AIPS_PACRO_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1937 | #define AIPS_PACRO_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1938 | #define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1939 | |
AnnaBridge | 171:3a7713b1edbc | 1940 | /*! @name PACRP - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1941 | #define AIPS_PACRP_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1942 | #define AIPS_PACRP_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1943 | #define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1944 | #define AIPS_PACRP_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1945 | #define AIPS_PACRP_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1946 | #define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1947 | #define AIPS_PACRP_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1948 | #define AIPS_PACRP_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1949 | #define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1950 | #define AIPS_PACRP_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1951 | #define AIPS_PACRP_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1952 | #define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1953 | #define AIPS_PACRP_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1954 | #define AIPS_PACRP_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1955 | #define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1956 | #define AIPS_PACRP_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1957 | #define AIPS_PACRP_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1958 | #define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1959 | #define AIPS_PACRP_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1960 | #define AIPS_PACRP_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1961 | #define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1962 | #define AIPS_PACRP_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1963 | #define AIPS_PACRP_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1964 | #define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1965 | #define AIPS_PACRP_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1966 | #define AIPS_PACRP_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1967 | #define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1968 | #define AIPS_PACRP_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1969 | #define AIPS_PACRP_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1970 | #define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1971 | #define AIPS_PACRP_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1972 | #define AIPS_PACRP_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1973 | #define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1974 | #define AIPS_PACRP_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1975 | #define AIPS_PACRP_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1976 | #define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1977 | #define AIPS_PACRP_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1978 | #define AIPS_PACRP_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1979 | #define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1980 | #define AIPS_PACRP_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1981 | #define AIPS_PACRP_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1982 | #define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1983 | #define AIPS_PACRP_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1984 | #define AIPS_PACRP_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1985 | #define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1986 | #define AIPS_PACRP_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1987 | #define AIPS_PACRP_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1988 | #define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1989 | #define AIPS_PACRP_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1990 | #define AIPS_PACRP_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1991 | #define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1992 | #define AIPS_PACRP_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1993 | #define AIPS_PACRP_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1994 | #define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1995 | #define AIPS_PACRP_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1996 | #define AIPS_PACRP_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1997 | #define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1998 | #define AIPS_PACRP_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1999 | #define AIPS_PACRP_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 2000 | #define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2001 | #define AIPS_PACRP_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 2002 | #define AIPS_PACRP_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 2003 | #define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2004 | #define AIPS_PACRP_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 2005 | #define AIPS_PACRP_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 2006 | #define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2007 | #define AIPS_PACRP_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 2008 | #define AIPS_PACRP_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 2009 | #define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2010 | #define AIPS_PACRP_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 2011 | #define AIPS_PACRP_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 2012 | #define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2013 | |
AnnaBridge | 171:3a7713b1edbc | 2014 | |
AnnaBridge | 171:3a7713b1edbc | 2015 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2016 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2017 | */ /* end of group AIPS_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 2018 | |
AnnaBridge | 171:3a7713b1edbc | 2019 | |
AnnaBridge | 171:3a7713b1edbc | 2020 | /* AIPS - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 2021 | /** Peripheral AIPS0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 2022 | #define AIPS0_BASE (0x40000000u) |
AnnaBridge | 171:3a7713b1edbc | 2023 | /** Peripheral AIPS0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 2024 | #define AIPS0 ((AIPS_Type *)AIPS0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 2025 | /** Peripheral AIPS1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 2026 | #define AIPS1_BASE (0x40080000u) |
AnnaBridge | 171:3a7713b1edbc | 2027 | /** Peripheral AIPS1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 2028 | #define AIPS1 ((AIPS_Type *)AIPS1_BASE) |
AnnaBridge | 171:3a7713b1edbc | 2029 | /** Array initializer of AIPS peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 2030 | #define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE } |
AnnaBridge | 171:3a7713b1edbc | 2031 | /** Array initializer of AIPS peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 2032 | #define AIPS_BASE_PTRS { AIPS0, AIPS1 } |
AnnaBridge | 171:3a7713b1edbc | 2033 | |
AnnaBridge | 171:3a7713b1edbc | 2034 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2035 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2036 | */ /* end of group AIPS_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 2037 | |
AnnaBridge | 171:3a7713b1edbc | 2038 | |
AnnaBridge | 171:3a7713b1edbc | 2039 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 2040 | -- AXBS Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 2041 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 2042 | |
AnnaBridge | 171:3a7713b1edbc | 2043 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2044 | * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 2045 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2046 | */ |
AnnaBridge | 171:3a7713b1edbc | 2047 | |
AnnaBridge | 171:3a7713b1edbc | 2048 | /** AXBS - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 2049 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 2050 | struct { /* offset: 0x0, array step: 0x100 */ |
AnnaBridge | 171:3a7713b1edbc | 2051 | __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */ |
AnnaBridge | 171:3a7713b1edbc | 2052 | uint8_t RESERVED_0[12]; |
AnnaBridge | 171:3a7713b1edbc | 2053 | __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */ |
AnnaBridge | 171:3a7713b1edbc | 2054 | uint8_t RESERVED_1[236]; |
AnnaBridge | 171:3a7713b1edbc | 2055 | } SLAVE[6]; |
AnnaBridge | 171:3a7713b1edbc | 2056 | uint8_t RESERVED_0[512]; |
AnnaBridge | 171:3a7713b1edbc | 2057 | __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */ |
AnnaBridge | 171:3a7713b1edbc | 2058 | uint8_t RESERVED_1[252]; |
AnnaBridge | 171:3a7713b1edbc | 2059 | __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */ |
AnnaBridge | 171:3a7713b1edbc | 2060 | uint8_t RESERVED_2[252]; |
AnnaBridge | 171:3a7713b1edbc | 2061 | __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */ |
AnnaBridge | 171:3a7713b1edbc | 2062 | uint8_t RESERVED_3[252]; |
AnnaBridge | 171:3a7713b1edbc | 2063 | __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */ |
AnnaBridge | 171:3a7713b1edbc | 2064 | uint8_t RESERVED_4[252]; |
AnnaBridge | 171:3a7713b1edbc | 2065 | __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ |
AnnaBridge | 171:3a7713b1edbc | 2066 | } AXBS_Type; |
AnnaBridge | 171:3a7713b1edbc | 2067 | |
AnnaBridge | 171:3a7713b1edbc | 2068 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 2069 | -- AXBS Register Masks |
AnnaBridge | 171:3a7713b1edbc | 2070 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 2071 | |
AnnaBridge | 171:3a7713b1edbc | 2072 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2073 | * @addtogroup AXBS_Register_Masks AXBS Register Masks |
AnnaBridge | 171:3a7713b1edbc | 2074 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2075 | */ |
AnnaBridge | 171:3a7713b1edbc | 2076 | |
AnnaBridge | 171:3a7713b1edbc | 2077 | /*! @name PRS - Priority Registers Slave */ |
AnnaBridge | 171:3a7713b1edbc | 2078 | #define AXBS_PRS_M0_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2079 | #define AXBS_PRS_M0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2080 | #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2081 | #define AXBS_PRS_M1_MASK (0x70U) |
AnnaBridge | 171:3a7713b1edbc | 2082 | #define AXBS_PRS_M1_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 2083 | #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2084 | #define AXBS_PRS_M2_MASK (0x700U) |
AnnaBridge | 171:3a7713b1edbc | 2085 | #define AXBS_PRS_M2_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 2086 | #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2087 | #define AXBS_PRS_M3_MASK (0x7000U) |
AnnaBridge | 171:3a7713b1edbc | 2088 | #define AXBS_PRS_M3_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 2089 | #define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2090 | #define AXBS_PRS_M4_MASK (0x70000U) |
AnnaBridge | 171:3a7713b1edbc | 2091 | #define AXBS_PRS_M4_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 2092 | #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2093 | |
AnnaBridge | 171:3a7713b1edbc | 2094 | /* The count of AXBS_PRS */ |
AnnaBridge | 171:3a7713b1edbc | 2095 | #define AXBS_PRS_COUNT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2096 | |
AnnaBridge | 171:3a7713b1edbc | 2097 | /*! @name CRS - Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 2098 | #define AXBS_CRS_PARK_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2099 | #define AXBS_CRS_PARK_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2100 | #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2101 | #define AXBS_CRS_PCTL_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 2102 | #define AXBS_CRS_PCTL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 2103 | #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2104 | #define AXBS_CRS_ARB_MASK (0x300U) |
AnnaBridge | 171:3a7713b1edbc | 2105 | #define AXBS_CRS_ARB_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 2106 | #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2107 | #define AXBS_CRS_HLP_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 2108 | #define AXBS_CRS_HLP_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 2109 | #define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2110 | #define AXBS_CRS_RO_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 2111 | #define AXBS_CRS_RO_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 2112 | #define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2113 | |
AnnaBridge | 171:3a7713b1edbc | 2114 | /* The count of AXBS_CRS */ |
AnnaBridge | 171:3a7713b1edbc | 2115 | #define AXBS_CRS_COUNT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2116 | |
AnnaBridge | 171:3a7713b1edbc | 2117 | /*! @name MGPCR0 - Master General Purpose Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 2118 | #define AXBS_MGPCR0_AULB_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2119 | #define AXBS_MGPCR0_AULB_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2120 | #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2121 | |
AnnaBridge | 171:3a7713b1edbc | 2122 | /*! @name MGPCR1 - Master General Purpose Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 2123 | #define AXBS_MGPCR1_AULB_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2124 | #define AXBS_MGPCR1_AULB_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2125 | #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2126 | |
AnnaBridge | 171:3a7713b1edbc | 2127 | /*! @name MGPCR2 - Master General Purpose Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 2128 | #define AXBS_MGPCR2_AULB_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2129 | #define AXBS_MGPCR2_AULB_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2130 | #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2131 | |
AnnaBridge | 171:3a7713b1edbc | 2132 | /*! @name MGPCR3 - Master General Purpose Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 2133 | #define AXBS_MGPCR3_AULB_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2134 | #define AXBS_MGPCR3_AULB_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2135 | #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2136 | |
AnnaBridge | 171:3a7713b1edbc | 2137 | /*! @name MGPCR4 - Master General Purpose Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 2138 | #define AXBS_MGPCR4_AULB_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2139 | #define AXBS_MGPCR4_AULB_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2140 | #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2141 | |
AnnaBridge | 171:3a7713b1edbc | 2142 | |
AnnaBridge | 171:3a7713b1edbc | 2143 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2144 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2145 | */ /* end of group AXBS_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 2146 | |
AnnaBridge | 171:3a7713b1edbc | 2147 | |
AnnaBridge | 171:3a7713b1edbc | 2148 | /* AXBS - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 2149 | /** Peripheral AXBS base address */ |
AnnaBridge | 171:3a7713b1edbc | 2150 | #define AXBS_BASE (0x40004000u) |
AnnaBridge | 171:3a7713b1edbc | 2151 | /** Peripheral AXBS base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 2152 | #define AXBS ((AXBS_Type *)AXBS_BASE) |
AnnaBridge | 171:3a7713b1edbc | 2153 | /** Array initializer of AXBS peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 2154 | #define AXBS_BASE_ADDRS { AXBS_BASE } |
AnnaBridge | 171:3a7713b1edbc | 2155 | /** Array initializer of AXBS peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 2156 | #define AXBS_BASE_PTRS { AXBS } |
AnnaBridge | 171:3a7713b1edbc | 2157 | |
AnnaBridge | 171:3a7713b1edbc | 2158 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2159 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2160 | */ /* end of group AXBS_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 2161 | |
AnnaBridge | 171:3a7713b1edbc | 2162 | |
AnnaBridge | 171:3a7713b1edbc | 2163 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 2164 | -- CAU Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 2165 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 2166 | |
AnnaBridge | 171:3a7713b1edbc | 2167 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2168 | * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 2169 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2170 | */ |
AnnaBridge | 171:3a7713b1edbc | 2171 | |
AnnaBridge | 171:3a7713b1edbc | 2172 | /** CAU - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 2173 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 2174 | __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2175 | uint8_t RESERVED_0[2048]; |
AnnaBridge | 171:3a7713b1edbc | 2176 | __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */ |
AnnaBridge | 171:3a7713b1edbc | 2177 | __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */ |
AnnaBridge | 171:3a7713b1edbc | 2178 | __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2179 | uint8_t RESERVED_1[20]; |
AnnaBridge | 171:3a7713b1edbc | 2180 | __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */ |
AnnaBridge | 171:3a7713b1edbc | 2181 | __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */ |
AnnaBridge | 171:3a7713b1edbc | 2182 | __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2183 | uint8_t RESERVED_2[20]; |
AnnaBridge | 171:3a7713b1edbc | 2184 | __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */ |
AnnaBridge | 171:3a7713b1edbc | 2185 | __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */ |
AnnaBridge | 171:3a7713b1edbc | 2186 | __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2187 | uint8_t RESERVED_3[20]; |
AnnaBridge | 171:3a7713b1edbc | 2188 | __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */ |
AnnaBridge | 171:3a7713b1edbc | 2189 | __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */ |
AnnaBridge | 171:3a7713b1edbc | 2190 | __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2191 | uint8_t RESERVED_4[84]; |
AnnaBridge | 171:3a7713b1edbc | 2192 | __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */ |
AnnaBridge | 171:3a7713b1edbc | 2193 | __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */ |
AnnaBridge | 171:3a7713b1edbc | 2194 | __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2195 | uint8_t RESERVED_5[20]; |
AnnaBridge | 171:3a7713b1edbc | 2196 | __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */ |
AnnaBridge | 171:3a7713b1edbc | 2197 | __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */ |
AnnaBridge | 171:3a7713b1edbc | 2198 | __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2199 | uint8_t RESERVED_6[276]; |
AnnaBridge | 171:3a7713b1edbc | 2200 | __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */ |
AnnaBridge | 171:3a7713b1edbc | 2201 | __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */ |
AnnaBridge | 171:3a7713b1edbc | 2202 | __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2203 | uint8_t RESERVED_7[20]; |
AnnaBridge | 171:3a7713b1edbc | 2204 | __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */ |
AnnaBridge | 171:3a7713b1edbc | 2205 | __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */ |
AnnaBridge | 171:3a7713b1edbc | 2206 | __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2207 | } CAU_Type; |
AnnaBridge | 171:3a7713b1edbc | 2208 | |
AnnaBridge | 171:3a7713b1edbc | 2209 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 2210 | -- CAU Register Masks |
AnnaBridge | 171:3a7713b1edbc | 2211 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 2212 | |
AnnaBridge | 171:3a7713b1edbc | 2213 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2214 | * @addtogroup CAU_Register_Masks CAU Register Masks |
AnnaBridge | 171:3a7713b1edbc | 2215 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2216 | */ |
AnnaBridge | 171:3a7713b1edbc | 2217 | |
AnnaBridge | 171:3a7713b1edbc | 2218 | /*! @name DIRECT - Direct access register 0..Direct access register 15 */ |
AnnaBridge | 171:3a7713b1edbc | 2219 | #define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2220 | #define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2221 | #define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2222 | #define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2223 | #define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2224 | #define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2225 | #define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2226 | #define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2227 | #define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2228 | #define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2229 | #define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2230 | #define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2231 | #define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2232 | #define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2233 | #define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2234 | #define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2235 | #define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2236 | #define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2237 | #define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2238 | #define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2239 | #define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2240 | #define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2241 | #define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2242 | #define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2243 | #define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2244 | #define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2245 | #define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2246 | #define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2247 | #define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2248 | #define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2249 | #define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2250 | #define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2251 | #define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2252 | #define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2253 | #define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2254 | #define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2255 | #define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2256 | #define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2257 | #define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2258 | #define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2259 | #define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2260 | #define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2261 | #define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2262 | #define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2263 | #define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2264 | #define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2265 | #define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2266 | #define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2267 | |
AnnaBridge | 171:3a7713b1edbc | 2268 | /* The count of CAU_DIRECT */ |
AnnaBridge | 171:3a7713b1edbc | 2269 | #define CAU_DIRECT_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 2270 | |
AnnaBridge | 171:3a7713b1edbc | 2271 | /*! @name LDR_CASR - Status register - Load Register command */ |
AnnaBridge | 171:3a7713b1edbc | 2272 | #define CAU_LDR_CASR_IC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2273 | #define CAU_LDR_CASR_IC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2274 | #define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2275 | #define CAU_LDR_CASR_DPE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2276 | #define CAU_LDR_CASR_DPE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2277 | #define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2278 | #define CAU_LDR_CASR_VER_MASK (0xF0000000U) |
AnnaBridge | 171:3a7713b1edbc | 2279 | #define CAU_LDR_CASR_VER_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 2280 | #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2281 | |
AnnaBridge | 171:3a7713b1edbc | 2282 | /*! @name LDR_CAA - Accumulator register - Load Register command */ |
AnnaBridge | 171:3a7713b1edbc | 2283 | #define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2284 | #define CAU_LDR_CAA_ACC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2285 | #define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2286 | |
AnnaBridge | 171:3a7713b1edbc | 2287 | /*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */ |
AnnaBridge | 171:3a7713b1edbc | 2288 | #define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2289 | #define CAU_LDR_CA_CA0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2290 | #define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2291 | #define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2292 | #define CAU_LDR_CA_CA1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2293 | #define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2294 | #define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2295 | #define CAU_LDR_CA_CA2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2296 | #define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2297 | #define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2298 | #define CAU_LDR_CA_CA3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2299 | #define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2300 | #define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2301 | #define CAU_LDR_CA_CA4_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2302 | #define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2303 | #define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2304 | #define CAU_LDR_CA_CA5_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2305 | #define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2306 | #define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2307 | #define CAU_LDR_CA_CA6_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2308 | #define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2309 | #define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2310 | #define CAU_LDR_CA_CA7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2311 | #define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2312 | #define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2313 | #define CAU_LDR_CA_CA8_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2314 | #define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2315 | |
AnnaBridge | 171:3a7713b1edbc | 2316 | /* The count of CAU_LDR_CA */ |
AnnaBridge | 171:3a7713b1edbc | 2317 | #define CAU_LDR_CA_COUNT (9U) |
AnnaBridge | 171:3a7713b1edbc | 2318 | |
AnnaBridge | 171:3a7713b1edbc | 2319 | /*! @name STR_CASR - Status register - Store Register command */ |
AnnaBridge | 171:3a7713b1edbc | 2320 | #define CAU_STR_CASR_IC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2321 | #define CAU_STR_CASR_IC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2322 | #define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2323 | #define CAU_STR_CASR_DPE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2324 | #define CAU_STR_CASR_DPE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2325 | #define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2326 | #define CAU_STR_CASR_VER_MASK (0xF0000000U) |
AnnaBridge | 171:3a7713b1edbc | 2327 | #define CAU_STR_CASR_VER_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 2328 | #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2329 | |
AnnaBridge | 171:3a7713b1edbc | 2330 | /*! @name STR_CAA - Accumulator register - Store Register command */ |
AnnaBridge | 171:3a7713b1edbc | 2331 | #define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2332 | #define CAU_STR_CAA_ACC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2333 | #define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2334 | |
AnnaBridge | 171:3a7713b1edbc | 2335 | /*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */ |
AnnaBridge | 171:3a7713b1edbc | 2336 | #define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2337 | #define CAU_STR_CA_CA0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2338 | #define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2339 | #define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2340 | #define CAU_STR_CA_CA1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2341 | #define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2342 | #define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2343 | #define CAU_STR_CA_CA2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2344 | #define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2345 | #define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2346 | #define CAU_STR_CA_CA3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2347 | #define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2348 | #define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2349 | #define CAU_STR_CA_CA4_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2350 | #define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2351 | #define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2352 | #define CAU_STR_CA_CA5_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2353 | #define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2354 | #define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2355 | #define CAU_STR_CA_CA6_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2356 | #define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2357 | #define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2358 | #define CAU_STR_CA_CA7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2359 | #define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2360 | #define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2361 | #define CAU_STR_CA_CA8_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2362 | #define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2363 | |
AnnaBridge | 171:3a7713b1edbc | 2364 | /* The count of CAU_STR_CA */ |
AnnaBridge | 171:3a7713b1edbc | 2365 | #define CAU_STR_CA_COUNT (9U) |
AnnaBridge | 171:3a7713b1edbc | 2366 | |
AnnaBridge | 171:3a7713b1edbc | 2367 | /*! @name ADR_CASR - Status register - Add Register command */ |
AnnaBridge | 171:3a7713b1edbc | 2368 | #define CAU_ADR_CASR_IC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2369 | #define CAU_ADR_CASR_IC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2370 | #define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2371 | #define CAU_ADR_CASR_DPE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2372 | #define CAU_ADR_CASR_DPE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2373 | #define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2374 | #define CAU_ADR_CASR_VER_MASK (0xF0000000U) |
AnnaBridge | 171:3a7713b1edbc | 2375 | #define CAU_ADR_CASR_VER_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 2376 | #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2377 | |
AnnaBridge | 171:3a7713b1edbc | 2378 | /*! @name ADR_CAA - Accumulator register - Add to register command */ |
AnnaBridge | 171:3a7713b1edbc | 2379 | #define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2380 | #define CAU_ADR_CAA_ACC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2381 | #define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2382 | |
AnnaBridge | 171:3a7713b1edbc | 2383 | /*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */ |
AnnaBridge | 171:3a7713b1edbc | 2384 | #define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2385 | #define CAU_ADR_CA_CA0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2386 | #define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2387 | #define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2388 | #define CAU_ADR_CA_CA1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2389 | #define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2390 | #define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2391 | #define CAU_ADR_CA_CA2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2392 | #define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2393 | #define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2394 | #define CAU_ADR_CA_CA3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2395 | #define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2396 | #define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2397 | #define CAU_ADR_CA_CA4_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2398 | #define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2399 | #define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2400 | #define CAU_ADR_CA_CA5_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2401 | #define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2402 | #define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2403 | #define CAU_ADR_CA_CA6_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2404 | #define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2405 | #define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2406 | #define CAU_ADR_CA_CA7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2407 | #define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2408 | #define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2409 | #define CAU_ADR_CA_CA8_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2410 | #define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2411 | |
AnnaBridge | 171:3a7713b1edbc | 2412 | /* The count of CAU_ADR_CA */ |
AnnaBridge | 171:3a7713b1edbc | 2413 | #define CAU_ADR_CA_COUNT (9U) |
AnnaBridge | 171:3a7713b1edbc | 2414 | |
AnnaBridge | 171:3a7713b1edbc | 2415 | /*! @name RADR_CASR - Status register - Reverse and Add to Register command */ |
AnnaBridge | 171:3a7713b1edbc | 2416 | #define CAU_RADR_CASR_IC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2417 | #define CAU_RADR_CASR_IC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2418 | #define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2419 | #define CAU_RADR_CASR_DPE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2420 | #define CAU_RADR_CASR_DPE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2421 | #define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2422 | #define CAU_RADR_CASR_VER_MASK (0xF0000000U) |
AnnaBridge | 171:3a7713b1edbc | 2423 | #define CAU_RADR_CASR_VER_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 2424 | #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2425 | |
AnnaBridge | 171:3a7713b1edbc | 2426 | /*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */ |
AnnaBridge | 171:3a7713b1edbc | 2427 | #define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2428 | #define CAU_RADR_CAA_ACC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2429 | #define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2430 | |
AnnaBridge | 171:3a7713b1edbc | 2431 | /*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */ |
AnnaBridge | 171:3a7713b1edbc | 2432 | #define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2433 | #define CAU_RADR_CA_CA0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2434 | #define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2435 | #define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2436 | #define CAU_RADR_CA_CA1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2437 | #define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2438 | #define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2439 | #define CAU_RADR_CA_CA2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2440 | #define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2441 | #define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2442 | #define CAU_RADR_CA_CA3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2443 | #define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2444 | #define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2445 | #define CAU_RADR_CA_CA4_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2446 | #define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2447 | #define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2448 | #define CAU_RADR_CA_CA5_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2449 | #define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2450 | #define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2451 | #define CAU_RADR_CA_CA6_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2452 | #define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2453 | #define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2454 | #define CAU_RADR_CA_CA7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2455 | #define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2456 | #define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2457 | #define CAU_RADR_CA_CA8_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2458 | #define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2459 | |
AnnaBridge | 171:3a7713b1edbc | 2460 | /* The count of CAU_RADR_CA */ |
AnnaBridge | 171:3a7713b1edbc | 2461 | #define CAU_RADR_CA_COUNT (9U) |
AnnaBridge | 171:3a7713b1edbc | 2462 | |
AnnaBridge | 171:3a7713b1edbc | 2463 | /*! @name XOR_CASR - Status register - Exclusive Or command */ |
AnnaBridge | 171:3a7713b1edbc | 2464 | #define CAU_XOR_CASR_IC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2465 | #define CAU_XOR_CASR_IC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2466 | #define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2467 | #define CAU_XOR_CASR_DPE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2468 | #define CAU_XOR_CASR_DPE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2469 | #define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2470 | #define CAU_XOR_CASR_VER_MASK (0xF0000000U) |
AnnaBridge | 171:3a7713b1edbc | 2471 | #define CAU_XOR_CASR_VER_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 2472 | #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2473 | |
AnnaBridge | 171:3a7713b1edbc | 2474 | /*! @name XOR_CAA - Accumulator register - Exclusive Or command */ |
AnnaBridge | 171:3a7713b1edbc | 2475 | #define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2476 | #define CAU_XOR_CAA_ACC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2477 | #define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2478 | |
AnnaBridge | 171:3a7713b1edbc | 2479 | /*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */ |
AnnaBridge | 171:3a7713b1edbc | 2480 | #define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2481 | #define CAU_XOR_CA_CA0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2482 | #define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2483 | #define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2484 | #define CAU_XOR_CA_CA1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2485 | #define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2486 | #define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2487 | #define CAU_XOR_CA_CA2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2488 | #define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2489 | #define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2490 | #define CAU_XOR_CA_CA3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2491 | #define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2492 | #define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2493 | #define CAU_XOR_CA_CA4_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2494 | #define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2495 | #define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2496 | #define CAU_XOR_CA_CA5_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2497 | #define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2498 | #define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2499 | #define CAU_XOR_CA_CA6_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2500 | #define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2501 | #define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2502 | #define CAU_XOR_CA_CA7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2503 | #define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2504 | #define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2505 | #define CAU_XOR_CA_CA8_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2506 | #define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2507 | |
AnnaBridge | 171:3a7713b1edbc | 2508 | /* The count of CAU_XOR_CA */ |
AnnaBridge | 171:3a7713b1edbc | 2509 | #define CAU_XOR_CA_COUNT (9U) |
AnnaBridge | 171:3a7713b1edbc | 2510 | |
AnnaBridge | 171:3a7713b1edbc | 2511 | /*! @name ROTL_CASR - Status register - Rotate Left command */ |
AnnaBridge | 171:3a7713b1edbc | 2512 | #define CAU_ROTL_CASR_IC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2513 | #define CAU_ROTL_CASR_IC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2514 | #define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2515 | #define CAU_ROTL_CASR_DPE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2516 | #define CAU_ROTL_CASR_DPE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2517 | #define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2518 | #define CAU_ROTL_CASR_VER_MASK (0xF0000000U) |
AnnaBridge | 171:3a7713b1edbc | 2519 | #define CAU_ROTL_CASR_VER_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 2520 | #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2521 | |
AnnaBridge | 171:3a7713b1edbc | 2522 | /*! @name ROTL_CAA - Accumulator register - Rotate Left command */ |
AnnaBridge | 171:3a7713b1edbc | 2523 | #define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2524 | #define CAU_ROTL_CAA_ACC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2525 | #define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2526 | |
AnnaBridge | 171:3a7713b1edbc | 2527 | /*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */ |
AnnaBridge | 171:3a7713b1edbc | 2528 | #define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2529 | #define CAU_ROTL_CA_CA0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2530 | #define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2531 | #define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2532 | #define CAU_ROTL_CA_CA1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2533 | #define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2534 | #define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2535 | #define CAU_ROTL_CA_CA2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2536 | #define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2537 | #define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2538 | #define CAU_ROTL_CA_CA3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2539 | #define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2540 | #define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2541 | #define CAU_ROTL_CA_CA4_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2542 | #define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2543 | #define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2544 | #define CAU_ROTL_CA_CA5_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2545 | #define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2546 | #define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2547 | #define CAU_ROTL_CA_CA6_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2548 | #define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2549 | #define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2550 | #define CAU_ROTL_CA_CA7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2551 | #define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2552 | #define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2553 | #define CAU_ROTL_CA_CA8_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2554 | #define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2555 | |
AnnaBridge | 171:3a7713b1edbc | 2556 | /* The count of CAU_ROTL_CA */ |
AnnaBridge | 171:3a7713b1edbc | 2557 | #define CAU_ROTL_CA_COUNT (9U) |
AnnaBridge | 171:3a7713b1edbc | 2558 | |
AnnaBridge | 171:3a7713b1edbc | 2559 | /*! @name AESC_CASR - Status register - AES Column Operation command */ |
AnnaBridge | 171:3a7713b1edbc | 2560 | #define CAU_AESC_CASR_IC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2561 | #define CAU_AESC_CASR_IC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2562 | #define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2563 | #define CAU_AESC_CASR_DPE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2564 | #define CAU_AESC_CASR_DPE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2565 | #define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2566 | #define CAU_AESC_CASR_VER_MASK (0xF0000000U) |
AnnaBridge | 171:3a7713b1edbc | 2567 | #define CAU_AESC_CASR_VER_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 2568 | #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2569 | |
AnnaBridge | 171:3a7713b1edbc | 2570 | /*! @name AESC_CAA - Accumulator register - AES Column Operation command */ |
AnnaBridge | 171:3a7713b1edbc | 2571 | #define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2572 | #define CAU_AESC_CAA_ACC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2573 | #define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2574 | |
AnnaBridge | 171:3a7713b1edbc | 2575 | /*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */ |
AnnaBridge | 171:3a7713b1edbc | 2576 | #define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2577 | #define CAU_AESC_CA_CA0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2578 | #define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2579 | #define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2580 | #define CAU_AESC_CA_CA1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2581 | #define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2582 | #define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2583 | #define CAU_AESC_CA_CA2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2584 | #define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2585 | #define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2586 | #define CAU_AESC_CA_CA3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2587 | #define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2588 | #define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2589 | #define CAU_AESC_CA_CA4_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2590 | #define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2591 | #define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2592 | #define CAU_AESC_CA_CA5_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2593 | #define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2594 | #define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2595 | #define CAU_AESC_CA_CA6_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2596 | #define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2597 | #define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2598 | #define CAU_AESC_CA_CA7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2599 | #define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2600 | #define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2601 | #define CAU_AESC_CA_CA8_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2602 | #define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2603 | |
AnnaBridge | 171:3a7713b1edbc | 2604 | /* The count of CAU_AESC_CA */ |
AnnaBridge | 171:3a7713b1edbc | 2605 | #define CAU_AESC_CA_COUNT (9U) |
AnnaBridge | 171:3a7713b1edbc | 2606 | |
AnnaBridge | 171:3a7713b1edbc | 2607 | /*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */ |
AnnaBridge | 171:3a7713b1edbc | 2608 | #define CAU_AESIC_CASR_IC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2609 | #define CAU_AESIC_CASR_IC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2610 | #define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2611 | #define CAU_AESIC_CASR_DPE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2612 | #define CAU_AESIC_CASR_DPE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2613 | #define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2614 | #define CAU_AESIC_CASR_VER_MASK (0xF0000000U) |
AnnaBridge | 171:3a7713b1edbc | 2615 | #define CAU_AESIC_CASR_VER_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 2616 | #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2617 | |
AnnaBridge | 171:3a7713b1edbc | 2618 | /*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */ |
AnnaBridge | 171:3a7713b1edbc | 2619 | #define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2620 | #define CAU_AESIC_CAA_ACC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2621 | #define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2622 | |
AnnaBridge | 171:3a7713b1edbc | 2623 | /*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */ |
AnnaBridge | 171:3a7713b1edbc | 2624 | #define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2625 | #define CAU_AESIC_CA_CA0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2626 | #define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2627 | #define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2628 | #define CAU_AESIC_CA_CA1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2629 | #define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2630 | #define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2631 | #define CAU_AESIC_CA_CA2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2632 | #define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2633 | #define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2634 | #define CAU_AESIC_CA_CA3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2635 | #define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2636 | #define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2637 | #define CAU_AESIC_CA_CA4_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2638 | #define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2639 | #define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2640 | #define CAU_AESIC_CA_CA5_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2641 | #define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2642 | #define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2643 | #define CAU_AESIC_CA_CA6_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2644 | #define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2645 | #define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2646 | #define CAU_AESIC_CA_CA7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2647 | #define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2648 | #define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2649 | #define CAU_AESIC_CA_CA8_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2650 | #define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2651 | |
AnnaBridge | 171:3a7713b1edbc | 2652 | /* The count of CAU_AESIC_CA */ |
AnnaBridge | 171:3a7713b1edbc | 2653 | #define CAU_AESIC_CA_COUNT (9U) |
AnnaBridge | 171:3a7713b1edbc | 2654 | |
AnnaBridge | 171:3a7713b1edbc | 2655 | |
AnnaBridge | 171:3a7713b1edbc | 2656 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2657 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2658 | */ /* end of group CAU_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 2659 | |
AnnaBridge | 171:3a7713b1edbc | 2660 | |
AnnaBridge | 171:3a7713b1edbc | 2661 | /* CAU - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 2662 | /** Peripheral CAU base address */ |
AnnaBridge | 171:3a7713b1edbc | 2663 | #define CAU_BASE (0xE0081000u) |
AnnaBridge | 171:3a7713b1edbc | 2664 | /** Peripheral CAU base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 2665 | #define CAU ((CAU_Type *)CAU_BASE) |
AnnaBridge | 171:3a7713b1edbc | 2666 | /** Array initializer of CAU peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 2667 | #define CAU_BASE_ADDRS { CAU_BASE } |
AnnaBridge | 171:3a7713b1edbc | 2668 | /** Array initializer of CAU peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 2669 | #define CAU_BASE_PTRS { CAU } |
AnnaBridge | 171:3a7713b1edbc | 2670 | |
AnnaBridge | 171:3a7713b1edbc | 2671 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2672 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2673 | */ /* end of group CAU_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 2674 | |
AnnaBridge | 171:3a7713b1edbc | 2675 | |
AnnaBridge | 171:3a7713b1edbc | 2676 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 2677 | -- CMP Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 2678 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 2679 | |
AnnaBridge | 171:3a7713b1edbc | 2680 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2681 | * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 2682 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2683 | */ |
AnnaBridge | 171:3a7713b1edbc | 2684 | |
AnnaBridge | 171:3a7713b1edbc | 2685 | /** CMP - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 2686 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 2687 | __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 2688 | __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 2689 | __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 2690 | __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ |
AnnaBridge | 171:3a7713b1edbc | 2691 | __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2692 | __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ |
AnnaBridge | 171:3a7713b1edbc | 2693 | } CMP_Type; |
AnnaBridge | 171:3a7713b1edbc | 2694 | |
AnnaBridge | 171:3a7713b1edbc | 2695 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 2696 | -- CMP Register Masks |
AnnaBridge | 171:3a7713b1edbc | 2697 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 2698 | |
AnnaBridge | 171:3a7713b1edbc | 2699 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2700 | * @addtogroup CMP_Register_Masks CMP Register Masks |
AnnaBridge | 171:3a7713b1edbc | 2701 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2702 | */ |
AnnaBridge | 171:3a7713b1edbc | 2703 | |
AnnaBridge | 171:3a7713b1edbc | 2704 | /*! @name CR0 - CMP Control Register 0 */ |
AnnaBridge | 171:3a7713b1edbc | 2705 | #define CMP_CR0_HYSTCTR_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 2706 | #define CMP_CR0_HYSTCTR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2707 | #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2708 | #define CMP_CR0_FILTER_CNT_MASK (0x70U) |
AnnaBridge | 171:3a7713b1edbc | 2709 | #define CMP_CR0_FILTER_CNT_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 2710 | #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2711 | |
AnnaBridge | 171:3a7713b1edbc | 2712 | /*! @name CR1 - CMP Control Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 2713 | #define CMP_CR1_EN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2714 | #define CMP_CR1_EN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2715 | #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2716 | #define CMP_CR1_OPE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2717 | #define CMP_CR1_OPE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2718 | #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2719 | #define CMP_CR1_COS_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 2720 | #define CMP_CR1_COS_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 2721 | #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2722 | #define CMP_CR1_INV_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 2723 | #define CMP_CR1_INV_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 2724 | #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2725 | #define CMP_CR1_PMODE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 2726 | #define CMP_CR1_PMODE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 2727 | #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2728 | #define CMP_CR1_TRIGM_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 2729 | #define CMP_CR1_TRIGM_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 2730 | #define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2731 | #define CMP_CR1_WE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2732 | #define CMP_CR1_WE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2733 | #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2734 | #define CMP_CR1_SE_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2735 | #define CMP_CR1_SE_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2736 | #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2737 | |
AnnaBridge | 171:3a7713b1edbc | 2738 | /*! @name FPR - CMP Filter Period Register */ |
AnnaBridge | 171:3a7713b1edbc | 2739 | #define CMP_FPR_FILT_PER_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 2740 | #define CMP_FPR_FILT_PER_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2741 | #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2742 | |
AnnaBridge | 171:3a7713b1edbc | 2743 | /*! @name SCR - CMP Status and Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 2744 | #define CMP_SCR_COUT_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2745 | #define CMP_SCR_COUT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2746 | #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2747 | #define CMP_SCR_CFF_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2748 | #define CMP_SCR_CFF_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2749 | #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2750 | #define CMP_SCR_CFR_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 2751 | #define CMP_SCR_CFR_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 2752 | #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2753 | #define CMP_SCR_IEF_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 2754 | #define CMP_SCR_IEF_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 2755 | #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2756 | #define CMP_SCR_IER_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 2757 | #define CMP_SCR_IER_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 2758 | #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2759 | #define CMP_SCR_DMAEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2760 | #define CMP_SCR_DMAEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2761 | #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2762 | |
AnnaBridge | 171:3a7713b1edbc | 2763 | /*! @name DACCR - DAC Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 2764 | #define CMP_DACCR_VOSEL_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 2765 | #define CMP_DACCR_VOSEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2766 | #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2767 | #define CMP_DACCR_VRSEL_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2768 | #define CMP_DACCR_VRSEL_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2769 | #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2770 | #define CMP_DACCR_DACEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2771 | #define CMP_DACCR_DACEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2772 | #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2773 | |
AnnaBridge | 171:3a7713b1edbc | 2774 | /*! @name MUXCR - MUX Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 2775 | #define CMP_MUXCR_MSEL_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2776 | #define CMP_MUXCR_MSEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2777 | #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2778 | #define CMP_MUXCR_PSEL_MASK (0x38U) |
AnnaBridge | 171:3a7713b1edbc | 2779 | #define CMP_MUXCR_PSEL_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 2780 | #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2781 | |
AnnaBridge | 171:3a7713b1edbc | 2782 | |
AnnaBridge | 171:3a7713b1edbc | 2783 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2784 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2785 | */ /* end of group CMP_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 2786 | |
AnnaBridge | 171:3a7713b1edbc | 2787 | |
AnnaBridge | 171:3a7713b1edbc | 2788 | /* CMP - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 2789 | /** Peripheral CMP0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 2790 | #define CMP0_BASE (0x40073000u) |
AnnaBridge | 171:3a7713b1edbc | 2791 | /** Peripheral CMP0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 2792 | #define CMP0 ((CMP_Type *)CMP0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 2793 | /** Peripheral CMP1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 2794 | #define CMP1_BASE (0x40073008u) |
AnnaBridge | 171:3a7713b1edbc | 2795 | /** Peripheral CMP1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 2796 | #define CMP1 ((CMP_Type *)CMP1_BASE) |
AnnaBridge | 171:3a7713b1edbc | 2797 | /** Array initializer of CMP peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 2798 | #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } |
AnnaBridge | 171:3a7713b1edbc | 2799 | /** Array initializer of CMP peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 2800 | #define CMP_BASE_PTRS { CMP0, CMP1 } |
AnnaBridge | 171:3a7713b1edbc | 2801 | /** Interrupt vectors for the CMP peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 2802 | #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 2803 | |
AnnaBridge | 171:3a7713b1edbc | 2804 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2805 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2806 | */ /* end of group CMP_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 2807 | |
AnnaBridge | 171:3a7713b1edbc | 2808 | |
AnnaBridge | 171:3a7713b1edbc | 2809 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 2810 | -- CMT Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 2811 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 2812 | |
AnnaBridge | 171:3a7713b1edbc | 2813 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2814 | * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 2815 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2816 | */ |
AnnaBridge | 171:3a7713b1edbc | 2817 | |
AnnaBridge | 171:3a7713b1edbc | 2818 | /** CMT - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 2819 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 2820 | __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 2821 | __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 2822 | __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 2823 | __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */ |
AnnaBridge | 171:3a7713b1edbc | 2824 | __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2825 | __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */ |
AnnaBridge | 171:3a7713b1edbc | 2826 | __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */ |
AnnaBridge | 171:3a7713b1edbc | 2827 | __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */ |
AnnaBridge | 171:3a7713b1edbc | 2828 | __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 2829 | __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */ |
AnnaBridge | 171:3a7713b1edbc | 2830 | __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */ |
AnnaBridge | 171:3a7713b1edbc | 2831 | __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */ |
AnnaBridge | 171:3a7713b1edbc | 2832 | } CMT_Type; |
AnnaBridge | 171:3a7713b1edbc | 2833 | |
AnnaBridge | 171:3a7713b1edbc | 2834 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 2835 | -- CMT Register Masks |
AnnaBridge | 171:3a7713b1edbc | 2836 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 2837 | |
AnnaBridge | 171:3a7713b1edbc | 2838 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2839 | * @addtogroup CMT_Register_Masks CMT Register Masks |
AnnaBridge | 171:3a7713b1edbc | 2840 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2841 | */ |
AnnaBridge | 171:3a7713b1edbc | 2842 | |
AnnaBridge | 171:3a7713b1edbc | 2843 | /*! @name CGH1 - CMT Carrier Generator High Data Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 2844 | #define CMT_CGH1_PH_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 2845 | #define CMT_CGH1_PH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2846 | #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2847 | |
AnnaBridge | 171:3a7713b1edbc | 2848 | /*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 2849 | #define CMT_CGL1_PL_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 2850 | #define CMT_CGL1_PL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2851 | #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2852 | |
AnnaBridge | 171:3a7713b1edbc | 2853 | /*! @name CGH2 - CMT Carrier Generator High Data Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 2854 | #define CMT_CGH2_SH_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 2855 | #define CMT_CGH2_SH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2856 | #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2857 | |
AnnaBridge | 171:3a7713b1edbc | 2858 | /*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 2859 | #define CMT_CGL2_SL_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 2860 | #define CMT_CGL2_SL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2861 | #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2862 | |
AnnaBridge | 171:3a7713b1edbc | 2863 | /*! @name OC - CMT Output Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 2864 | #define CMT_OC_IROPEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 2865 | #define CMT_OC_IROPEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 2866 | #define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2867 | #define CMT_OC_CMTPOL_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2868 | #define CMT_OC_CMTPOL_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2869 | #define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2870 | #define CMT_OC_IROL_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2871 | #define CMT_OC_IROL_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2872 | #define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2873 | |
AnnaBridge | 171:3a7713b1edbc | 2874 | /*! @name MSC - CMT Modulator Status and Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 2875 | #define CMT_MSC_MCGEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2876 | #define CMT_MSC_MCGEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2877 | #define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2878 | #define CMT_MSC_EOCIE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2879 | #define CMT_MSC_EOCIE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2880 | #define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2881 | #define CMT_MSC_FSK_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 2882 | #define CMT_MSC_FSK_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 2883 | #define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2884 | #define CMT_MSC_BASE_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 2885 | #define CMT_MSC_BASE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 2886 | #define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2887 | #define CMT_MSC_EXSPC_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 2888 | #define CMT_MSC_EXSPC_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 2889 | #define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2890 | #define CMT_MSC_CMTDIV_MASK (0x60U) |
AnnaBridge | 171:3a7713b1edbc | 2891 | #define CMT_MSC_CMTDIV_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 2892 | #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2893 | #define CMT_MSC_EOCF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2894 | #define CMT_MSC_EOCF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2895 | #define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2896 | |
AnnaBridge | 171:3a7713b1edbc | 2897 | /*! @name CMD1 - CMT Modulator Data Register Mark High */ |
AnnaBridge | 171:3a7713b1edbc | 2898 | #define CMT_CMD1_MB_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 2899 | #define CMT_CMD1_MB_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2900 | #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2901 | |
AnnaBridge | 171:3a7713b1edbc | 2902 | /*! @name CMD2 - CMT Modulator Data Register Mark Low */ |
AnnaBridge | 171:3a7713b1edbc | 2903 | #define CMT_CMD2_MB_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 2904 | #define CMT_CMD2_MB_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2905 | #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2906 | |
AnnaBridge | 171:3a7713b1edbc | 2907 | /*! @name CMD3 - CMT Modulator Data Register Space High */ |
AnnaBridge | 171:3a7713b1edbc | 2908 | #define CMT_CMD3_SB_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 2909 | #define CMT_CMD3_SB_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2910 | #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2911 | |
AnnaBridge | 171:3a7713b1edbc | 2912 | /*! @name CMD4 - CMT Modulator Data Register Space Low */ |
AnnaBridge | 171:3a7713b1edbc | 2913 | #define CMT_CMD4_SB_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 2914 | #define CMT_CMD4_SB_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2915 | #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2916 | |
AnnaBridge | 171:3a7713b1edbc | 2917 | /*! @name PPS - CMT Primary Prescaler Register */ |
AnnaBridge | 171:3a7713b1edbc | 2918 | #define CMT_PPS_PPSDIV_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 2919 | #define CMT_PPS_PPSDIV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2920 | #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2921 | |
AnnaBridge | 171:3a7713b1edbc | 2922 | /*! @name DMA - CMT Direct Memory Access Register */ |
AnnaBridge | 171:3a7713b1edbc | 2923 | #define CMT_DMA_DMA_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2924 | #define CMT_DMA_DMA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2925 | #define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2926 | |
AnnaBridge | 171:3a7713b1edbc | 2927 | |
AnnaBridge | 171:3a7713b1edbc | 2928 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2929 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2930 | */ /* end of group CMT_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 2931 | |
AnnaBridge | 171:3a7713b1edbc | 2932 | |
AnnaBridge | 171:3a7713b1edbc | 2933 | /* CMT - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 2934 | /** Peripheral CMT base address */ |
AnnaBridge | 171:3a7713b1edbc | 2935 | #define CMT_BASE (0x40062000u) |
AnnaBridge | 171:3a7713b1edbc | 2936 | /** Peripheral CMT base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 2937 | #define CMT ((CMT_Type *)CMT_BASE) |
AnnaBridge | 171:3a7713b1edbc | 2938 | /** Array initializer of CMT peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 2939 | #define CMT_BASE_ADDRS { CMT_BASE } |
AnnaBridge | 171:3a7713b1edbc | 2940 | /** Array initializer of CMT peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 2941 | #define CMT_BASE_PTRS { CMT } |
AnnaBridge | 171:3a7713b1edbc | 2942 | /** Interrupt vectors for the CMT peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 2943 | #define CMT_IRQS { CMT_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 2944 | |
AnnaBridge | 171:3a7713b1edbc | 2945 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2946 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2947 | */ /* end of group CMT_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 2948 | |
AnnaBridge | 171:3a7713b1edbc | 2949 | |
AnnaBridge | 171:3a7713b1edbc | 2950 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 2951 | -- CRC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 2952 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 2953 | |
AnnaBridge | 171:3a7713b1edbc | 2954 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2955 | * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 2956 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2957 | */ |
AnnaBridge | 171:3a7713b1edbc | 2958 | |
AnnaBridge | 171:3a7713b1edbc | 2959 | /** CRC - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 2960 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 2961 | union { /* offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 2962 | struct { /* offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 2963 | __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 2964 | __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 2965 | } ACCESS16BIT; |
AnnaBridge | 171:3a7713b1edbc | 2966 | __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 2967 | struct { /* offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 2968 | __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 2969 | __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 2970 | __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 2971 | __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */ |
AnnaBridge | 171:3a7713b1edbc | 2972 | } ACCESS8BIT; |
AnnaBridge | 171:3a7713b1edbc | 2973 | }; |
AnnaBridge | 171:3a7713b1edbc | 2974 | union { /* offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2975 | struct { /* offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2976 | __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2977 | __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ |
AnnaBridge | 171:3a7713b1edbc | 2978 | } GPOLY_ACCESS16BIT; |
AnnaBridge | 171:3a7713b1edbc | 2979 | __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2980 | struct { /* offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2981 | __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2982 | __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ |
AnnaBridge | 171:3a7713b1edbc | 2983 | __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ |
AnnaBridge | 171:3a7713b1edbc | 2984 | __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ |
AnnaBridge | 171:3a7713b1edbc | 2985 | } GPOLY_ACCESS8BIT; |
AnnaBridge | 171:3a7713b1edbc | 2986 | }; |
AnnaBridge | 171:3a7713b1edbc | 2987 | union { /* offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 2988 | __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 2989 | struct { /* offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 2990 | uint8_t RESERVED_0[3]; |
AnnaBridge | 171:3a7713b1edbc | 2991 | __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ |
AnnaBridge | 171:3a7713b1edbc | 2992 | } CTRL_ACCESS8BIT; |
AnnaBridge | 171:3a7713b1edbc | 2993 | }; |
AnnaBridge | 171:3a7713b1edbc | 2994 | } CRC_Type; |
AnnaBridge | 171:3a7713b1edbc | 2995 | |
AnnaBridge | 171:3a7713b1edbc | 2996 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 2997 | -- CRC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 2998 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 2999 | |
AnnaBridge | 171:3a7713b1edbc | 3000 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3001 | * @addtogroup CRC_Register_Masks CRC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 3002 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3003 | */ |
AnnaBridge | 171:3a7713b1edbc | 3004 | |
AnnaBridge | 171:3a7713b1edbc | 3005 | /*! @name DATAL - CRC_DATAL register. */ |
AnnaBridge | 171:3a7713b1edbc | 3006 | #define CRC_DATAL_DATAL_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3007 | #define CRC_DATAL_DATAL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3008 | #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3009 | |
AnnaBridge | 171:3a7713b1edbc | 3010 | /*! @name DATAH - CRC_DATAH register. */ |
AnnaBridge | 171:3a7713b1edbc | 3011 | #define CRC_DATAH_DATAH_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3012 | #define CRC_DATAH_DATAH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3013 | #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3014 | |
AnnaBridge | 171:3a7713b1edbc | 3015 | /*! @name DATA - CRC Data register */ |
AnnaBridge | 171:3a7713b1edbc | 3016 | #define CRC_DATA_LL_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3017 | #define CRC_DATA_LL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3018 | #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3019 | #define CRC_DATA_LU_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 3020 | #define CRC_DATA_LU_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3021 | #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3022 | #define CRC_DATA_HL_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 3023 | #define CRC_DATA_HL_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 3024 | #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3025 | #define CRC_DATA_HU_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 3026 | #define CRC_DATA_HU_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 3027 | #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3028 | |
AnnaBridge | 171:3a7713b1edbc | 3029 | /*! @name DATALL - CRC_DATALL register. */ |
AnnaBridge | 171:3a7713b1edbc | 3030 | #define CRC_DATALL_DATALL_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3031 | #define CRC_DATALL_DATALL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3032 | #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3033 | |
AnnaBridge | 171:3a7713b1edbc | 3034 | /*! @name DATALU - CRC_DATALU register. */ |
AnnaBridge | 171:3a7713b1edbc | 3035 | #define CRC_DATALU_DATALU_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3036 | #define CRC_DATALU_DATALU_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3037 | #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3038 | |
AnnaBridge | 171:3a7713b1edbc | 3039 | /*! @name DATAHL - CRC_DATAHL register. */ |
AnnaBridge | 171:3a7713b1edbc | 3040 | #define CRC_DATAHL_DATAHL_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3041 | #define CRC_DATAHL_DATAHL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3042 | #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3043 | |
AnnaBridge | 171:3a7713b1edbc | 3044 | /*! @name DATAHU - CRC_DATAHU register. */ |
AnnaBridge | 171:3a7713b1edbc | 3045 | #define CRC_DATAHU_DATAHU_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3046 | #define CRC_DATAHU_DATAHU_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3047 | #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3048 | |
AnnaBridge | 171:3a7713b1edbc | 3049 | /*! @name GPOLYL - CRC_GPOLYL register. */ |
AnnaBridge | 171:3a7713b1edbc | 3050 | #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3051 | #define CRC_GPOLYL_GPOLYL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3052 | #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3053 | |
AnnaBridge | 171:3a7713b1edbc | 3054 | /*! @name GPOLYH - CRC_GPOLYH register. */ |
AnnaBridge | 171:3a7713b1edbc | 3055 | #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3056 | #define CRC_GPOLYH_GPOLYH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3057 | #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3058 | |
AnnaBridge | 171:3a7713b1edbc | 3059 | /*! @name GPOLY - CRC Polynomial register */ |
AnnaBridge | 171:3a7713b1edbc | 3060 | #define CRC_GPOLY_LOW_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3061 | #define CRC_GPOLY_LOW_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3062 | #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3063 | #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 3064 | #define CRC_GPOLY_HIGH_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 3065 | #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3066 | |
AnnaBridge | 171:3a7713b1edbc | 3067 | /*! @name GPOLYLL - CRC_GPOLYLL register. */ |
AnnaBridge | 171:3a7713b1edbc | 3068 | #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3069 | #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3070 | #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3071 | |
AnnaBridge | 171:3a7713b1edbc | 3072 | /*! @name GPOLYLU - CRC_GPOLYLU register. */ |
AnnaBridge | 171:3a7713b1edbc | 3073 | #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3074 | #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3075 | #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3076 | |
AnnaBridge | 171:3a7713b1edbc | 3077 | /*! @name GPOLYHL - CRC_GPOLYHL register. */ |
AnnaBridge | 171:3a7713b1edbc | 3078 | #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3079 | #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3080 | #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3081 | |
AnnaBridge | 171:3a7713b1edbc | 3082 | /*! @name GPOLYHU - CRC_GPOLYHU register. */ |
AnnaBridge | 171:3a7713b1edbc | 3083 | #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3084 | #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3085 | #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3086 | |
AnnaBridge | 171:3a7713b1edbc | 3087 | /*! @name CTRL - CRC Control register */ |
AnnaBridge | 171:3a7713b1edbc | 3088 | #define CRC_CTRL_TCRC_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 3089 | #define CRC_CTRL_TCRC_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 3090 | #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3091 | #define CRC_CTRL_WAS_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 3092 | #define CRC_CTRL_WAS_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 3093 | #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3094 | #define CRC_CTRL_FXOR_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 3095 | #define CRC_CTRL_FXOR_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 3096 | #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3097 | #define CRC_CTRL_TOTR_MASK (0x30000000U) |
AnnaBridge | 171:3a7713b1edbc | 3098 | #define CRC_CTRL_TOTR_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 3099 | #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3100 | #define CRC_CTRL_TOT_MASK (0xC0000000U) |
AnnaBridge | 171:3a7713b1edbc | 3101 | #define CRC_CTRL_TOT_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 3102 | #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3103 | |
AnnaBridge | 171:3a7713b1edbc | 3104 | /*! @name CTRLHU - CRC_CTRLHU register. */ |
AnnaBridge | 171:3a7713b1edbc | 3105 | #define CRC_CTRLHU_TCRC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 3106 | #define CRC_CTRLHU_TCRC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3107 | #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3108 | #define CRC_CTRLHU_WAS_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 3109 | #define CRC_CTRLHU_WAS_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 3110 | #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3111 | #define CRC_CTRLHU_FXOR_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 3112 | #define CRC_CTRLHU_FXOR_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 3113 | #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3114 | #define CRC_CTRLHU_TOTR_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 3115 | #define CRC_CTRLHU_TOTR_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 3116 | #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3117 | #define CRC_CTRLHU_TOT_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 3118 | #define CRC_CTRLHU_TOT_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 3119 | #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3120 | |
AnnaBridge | 171:3a7713b1edbc | 3121 | |
AnnaBridge | 171:3a7713b1edbc | 3122 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3123 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3124 | */ /* end of group CRC_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 3125 | |
AnnaBridge | 171:3a7713b1edbc | 3126 | |
AnnaBridge | 171:3a7713b1edbc | 3127 | /* CRC - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 3128 | /** Peripheral CRC base address */ |
AnnaBridge | 171:3a7713b1edbc | 3129 | #define CRC_BASE (0x40032000u) |
AnnaBridge | 171:3a7713b1edbc | 3130 | /** Peripheral CRC base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 3131 | #define CRC0 ((CRC_Type *)CRC_BASE) |
AnnaBridge | 171:3a7713b1edbc | 3132 | /** Array initializer of CRC peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 3133 | #define CRC_BASE_ADDRS { CRC_BASE } |
AnnaBridge | 171:3a7713b1edbc | 3134 | /** Array initializer of CRC peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 3135 | #define CRC_BASE_PTRS { CRC0 } |
AnnaBridge | 171:3a7713b1edbc | 3136 | |
AnnaBridge | 171:3a7713b1edbc | 3137 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3138 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3139 | */ /* end of group CRC_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 3140 | |
AnnaBridge | 171:3a7713b1edbc | 3141 | |
AnnaBridge | 171:3a7713b1edbc | 3142 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 3143 | -- DAC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 3144 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 3145 | |
AnnaBridge | 171:3a7713b1edbc | 3146 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3147 | * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 3148 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3149 | */ |
AnnaBridge | 171:3a7713b1edbc | 3150 | |
AnnaBridge | 171:3a7713b1edbc | 3151 | /** DAC - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 3152 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 3153 | struct { /* offset: 0x0, array step: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 3154 | __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 3155 | __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 3156 | } DAT[16]; |
AnnaBridge | 171:3a7713b1edbc | 3157 | __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3158 | __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ |
AnnaBridge | 171:3a7713b1edbc | 3159 | __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */ |
AnnaBridge | 171:3a7713b1edbc | 3160 | __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */ |
AnnaBridge | 171:3a7713b1edbc | 3161 | } DAC_Type; |
AnnaBridge | 171:3a7713b1edbc | 3162 | |
AnnaBridge | 171:3a7713b1edbc | 3163 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 3164 | -- DAC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 3165 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 3166 | |
AnnaBridge | 171:3a7713b1edbc | 3167 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3168 | * @addtogroup DAC_Register_Masks DAC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 3169 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3170 | */ |
AnnaBridge | 171:3a7713b1edbc | 3171 | |
AnnaBridge | 171:3a7713b1edbc | 3172 | /*! @name DATL - DAC Data Low Register */ |
AnnaBridge | 171:3a7713b1edbc | 3173 | #define DAC_DATL_DATA0_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3174 | #define DAC_DATL_DATA0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3175 | #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3176 | |
AnnaBridge | 171:3a7713b1edbc | 3177 | /* The count of DAC_DATL */ |
AnnaBridge | 171:3a7713b1edbc | 3178 | #define DAC_DATL_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 3179 | |
AnnaBridge | 171:3a7713b1edbc | 3180 | /*! @name DATH - DAC Data High Register */ |
AnnaBridge | 171:3a7713b1edbc | 3181 | #define DAC_DATH_DATA1_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 3182 | #define DAC_DATH_DATA1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3183 | #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3184 | |
AnnaBridge | 171:3a7713b1edbc | 3185 | /* The count of DAC_DATH */ |
AnnaBridge | 171:3a7713b1edbc | 3186 | #define DAC_DATH_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 3187 | |
AnnaBridge | 171:3a7713b1edbc | 3188 | /*! @name SR - DAC Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 3189 | #define DAC_SR_DACBFRPBF_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 3190 | #define DAC_SR_DACBFRPBF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3191 | #define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3192 | #define DAC_SR_DACBFRPTF_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 3193 | #define DAC_SR_DACBFRPTF_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 3194 | #define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3195 | #define DAC_SR_DACBFWMF_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 3196 | #define DAC_SR_DACBFWMF_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 3197 | #define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3198 | |
AnnaBridge | 171:3a7713b1edbc | 3199 | /*! @name C0 - DAC Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 3200 | #define DAC_C0_DACBBIEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 3201 | #define DAC_C0_DACBBIEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3202 | #define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3203 | #define DAC_C0_DACBTIEN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 3204 | #define DAC_C0_DACBTIEN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 3205 | #define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3206 | #define DAC_C0_DACBWIEN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 3207 | #define DAC_C0_DACBWIEN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 3208 | #define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3209 | #define DAC_C0_LPEN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 3210 | #define DAC_C0_LPEN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 3211 | #define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3212 | #define DAC_C0_DACSWTRG_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 3213 | #define DAC_C0_DACSWTRG_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 3214 | #define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3215 | #define DAC_C0_DACTRGSEL_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 3216 | #define DAC_C0_DACTRGSEL_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 3217 | #define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3218 | #define DAC_C0_DACRFS_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 3219 | #define DAC_C0_DACRFS_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 3220 | #define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3221 | #define DAC_C0_DACEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3222 | #define DAC_C0_DACEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3223 | #define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3224 | |
AnnaBridge | 171:3a7713b1edbc | 3225 | /*! @name C1 - DAC Control Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 3226 | #define DAC_C1_DACBFEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 3227 | #define DAC_C1_DACBFEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3228 | #define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3229 | #define DAC_C1_DACBFMD_MASK (0x6U) |
AnnaBridge | 171:3a7713b1edbc | 3230 | #define DAC_C1_DACBFMD_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 3231 | #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3232 | #define DAC_C1_DACBFWM_MASK (0x18U) |
AnnaBridge | 171:3a7713b1edbc | 3233 | #define DAC_C1_DACBFWM_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 3234 | #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3235 | #define DAC_C1_DMAEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3236 | #define DAC_C1_DMAEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3237 | #define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3238 | |
AnnaBridge | 171:3a7713b1edbc | 3239 | /*! @name C2 - DAC Control Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 3240 | #define DAC_C2_DACBFUP_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 3241 | #define DAC_C2_DACBFUP_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3242 | #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3243 | #define DAC_C2_DACBFRP_MASK (0xF0U) |
AnnaBridge | 171:3a7713b1edbc | 3244 | #define DAC_C2_DACBFRP_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 3245 | #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3246 | |
AnnaBridge | 171:3a7713b1edbc | 3247 | |
AnnaBridge | 171:3a7713b1edbc | 3248 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3249 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3250 | */ /* end of group DAC_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 3251 | |
AnnaBridge | 171:3a7713b1edbc | 3252 | |
AnnaBridge | 171:3a7713b1edbc | 3253 | /* DAC - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 3254 | /** Peripheral DAC0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 3255 | #define DAC0_BASE (0x400CC000u) |
AnnaBridge | 171:3a7713b1edbc | 3256 | /** Peripheral DAC0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 3257 | #define DAC0 ((DAC_Type *)DAC0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 3258 | /** Array initializer of DAC peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 3259 | #define DAC_BASE_ADDRS { DAC0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 3260 | /** Array initializer of DAC peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 3261 | #define DAC_BASE_PTRS { DAC0 } |
AnnaBridge | 171:3a7713b1edbc | 3262 | /** Interrupt vectors for the DAC peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 3263 | #define DAC_IRQS { DAC0_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 3264 | |
AnnaBridge | 171:3a7713b1edbc | 3265 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3266 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3267 | */ /* end of group DAC_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 3268 | |
AnnaBridge | 171:3a7713b1edbc | 3269 | |
AnnaBridge | 171:3a7713b1edbc | 3270 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 3271 | -- DMA Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 3272 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 3273 | |
AnnaBridge | 171:3a7713b1edbc | 3274 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3275 | * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 3276 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3277 | */ |
AnnaBridge | 171:3a7713b1edbc | 3278 | |
AnnaBridge | 171:3a7713b1edbc | 3279 | /** DMA - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 3280 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 3281 | __IO uint32_t CR; /**< Control Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 3282 | __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 3283 | uint8_t RESERVED_0[4]; |
AnnaBridge | 171:3a7713b1edbc | 3284 | __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 3285 | uint8_t RESERVED_1[4]; |
AnnaBridge | 171:3a7713b1edbc | 3286 | __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 3287 | __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 3288 | __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ |
AnnaBridge | 171:3a7713b1edbc | 3289 | __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ |
AnnaBridge | 171:3a7713b1edbc | 3290 | __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ |
AnnaBridge | 171:3a7713b1edbc | 3291 | __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 3292 | __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ |
AnnaBridge | 171:3a7713b1edbc | 3293 | __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ |
AnnaBridge | 171:3a7713b1edbc | 3294 | __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ |
AnnaBridge | 171:3a7713b1edbc | 3295 | uint8_t RESERVED_2[4]; |
AnnaBridge | 171:3a7713b1edbc | 3296 | __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 3297 | uint8_t RESERVED_3[4]; |
AnnaBridge | 171:3a7713b1edbc | 3298 | __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ |
AnnaBridge | 171:3a7713b1edbc | 3299 | uint8_t RESERVED_4[4]; |
AnnaBridge | 171:3a7713b1edbc | 3300 | __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 3301 | uint8_t RESERVED_5[12]; |
AnnaBridge | 171:3a7713b1edbc | 3302 | __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */ |
AnnaBridge | 171:3a7713b1edbc | 3303 | uint8_t RESERVED_6[184]; |
AnnaBridge | 171:3a7713b1edbc | 3304 | __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ |
AnnaBridge | 171:3a7713b1edbc | 3305 | __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ |
AnnaBridge | 171:3a7713b1edbc | 3306 | __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ |
AnnaBridge | 171:3a7713b1edbc | 3307 | __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ |
AnnaBridge | 171:3a7713b1edbc | 3308 | __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */ |
AnnaBridge | 171:3a7713b1edbc | 3309 | __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */ |
AnnaBridge | 171:3a7713b1edbc | 3310 | __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */ |
AnnaBridge | 171:3a7713b1edbc | 3311 | __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */ |
AnnaBridge | 171:3a7713b1edbc | 3312 | __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */ |
AnnaBridge | 171:3a7713b1edbc | 3313 | __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */ |
AnnaBridge | 171:3a7713b1edbc | 3314 | __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */ |
AnnaBridge | 171:3a7713b1edbc | 3315 | __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */ |
AnnaBridge | 171:3a7713b1edbc | 3316 | __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */ |
AnnaBridge | 171:3a7713b1edbc | 3317 | __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */ |
AnnaBridge | 171:3a7713b1edbc | 3318 | __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */ |
AnnaBridge | 171:3a7713b1edbc | 3319 | __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */ |
AnnaBridge | 171:3a7713b1edbc | 3320 | __IO uint8_t DCHPRI19; /**< Channel n Priority Register, offset: 0x110 */ |
AnnaBridge | 171:3a7713b1edbc | 3321 | __IO uint8_t DCHPRI18; /**< Channel n Priority Register, offset: 0x111 */ |
AnnaBridge | 171:3a7713b1edbc | 3322 | __IO uint8_t DCHPRI17; /**< Channel n Priority Register, offset: 0x112 */ |
AnnaBridge | 171:3a7713b1edbc | 3323 | __IO uint8_t DCHPRI16; /**< Channel n Priority Register, offset: 0x113 */ |
AnnaBridge | 171:3a7713b1edbc | 3324 | __IO uint8_t DCHPRI23; /**< Channel n Priority Register, offset: 0x114 */ |
AnnaBridge | 171:3a7713b1edbc | 3325 | __IO uint8_t DCHPRI22; /**< Channel n Priority Register, offset: 0x115 */ |
AnnaBridge | 171:3a7713b1edbc | 3326 | __IO uint8_t DCHPRI21; /**< Channel n Priority Register, offset: 0x116 */ |
AnnaBridge | 171:3a7713b1edbc | 3327 | __IO uint8_t DCHPRI20; /**< Channel n Priority Register, offset: 0x117 */ |
AnnaBridge | 171:3a7713b1edbc | 3328 | __IO uint8_t DCHPRI27; /**< Channel n Priority Register, offset: 0x118 */ |
AnnaBridge | 171:3a7713b1edbc | 3329 | __IO uint8_t DCHPRI26; /**< Channel n Priority Register, offset: 0x119 */ |
AnnaBridge | 171:3a7713b1edbc | 3330 | __IO uint8_t DCHPRI25; /**< Channel n Priority Register, offset: 0x11A */ |
AnnaBridge | 171:3a7713b1edbc | 3331 | __IO uint8_t DCHPRI24; /**< Channel n Priority Register, offset: 0x11B */ |
AnnaBridge | 171:3a7713b1edbc | 3332 | __IO uint8_t DCHPRI31; /**< Channel n Priority Register, offset: 0x11C */ |
AnnaBridge | 171:3a7713b1edbc | 3333 | __IO uint8_t DCHPRI30; /**< Channel n Priority Register, offset: 0x11D */ |
AnnaBridge | 171:3a7713b1edbc | 3334 | __IO uint8_t DCHPRI29; /**< Channel n Priority Register, offset: 0x11E */ |
AnnaBridge | 171:3a7713b1edbc | 3335 | __IO uint8_t DCHPRI28; /**< Channel n Priority Register, offset: 0x11F */ |
AnnaBridge | 171:3a7713b1edbc | 3336 | uint8_t RESERVED_7[3808]; |
AnnaBridge | 171:3a7713b1edbc | 3337 | struct { /* offset: 0x1000, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3338 | __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3339 | __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3340 | __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3341 | union { /* offset: 0x1008, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3342 | __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3343 | __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3344 | __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3345 | }; |
AnnaBridge | 171:3a7713b1edbc | 3346 | __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3347 | __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3348 | __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3349 | union { /* offset: 0x1016, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3350 | __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3351 | __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3352 | }; |
AnnaBridge | 171:3a7713b1edbc | 3353 | __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3354 | __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3355 | union { /* offset: 0x101E, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3356 | __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3357 | __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3358 | }; |
AnnaBridge | 171:3a7713b1edbc | 3359 | } TCD[32]; |
AnnaBridge | 171:3a7713b1edbc | 3360 | } DMA_Type; |
AnnaBridge | 171:3a7713b1edbc | 3361 | |
AnnaBridge | 171:3a7713b1edbc | 3362 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 3363 | -- DMA Register Masks |
AnnaBridge | 171:3a7713b1edbc | 3364 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 3365 | |
AnnaBridge | 171:3a7713b1edbc | 3366 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3367 | * @addtogroup DMA_Register_Masks DMA Register Masks |
AnnaBridge | 171:3a7713b1edbc | 3368 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3369 | */ |
AnnaBridge | 171:3a7713b1edbc | 3370 | |
AnnaBridge | 171:3a7713b1edbc | 3371 | /*! @name CR - Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 3372 | #define DMA_CR_EDBG_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 3373 | #define DMA_CR_EDBG_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 3374 | #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3375 | #define DMA_CR_ERCA_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 3376 | #define DMA_CR_ERCA_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 3377 | #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3378 | #define DMA_CR_ERGA_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 3379 | #define DMA_CR_ERGA_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 3380 | #define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3381 | #define DMA_CR_HOE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 3382 | #define DMA_CR_HOE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 3383 | #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3384 | #define DMA_CR_HALT_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 3385 | #define DMA_CR_HALT_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 3386 | #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3387 | #define DMA_CR_CLM_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 3388 | #define DMA_CR_CLM_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 3389 | #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3390 | #define DMA_CR_EMLM_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3391 | #define DMA_CR_EMLM_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3392 | #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3393 | #define DMA_CR_GRP0PRI_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 3394 | #define DMA_CR_GRP0PRI_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3395 | #define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3396 | #define DMA_CR_GRP1PRI_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 3397 | #define DMA_CR_GRP1PRI_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 3398 | #define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3399 | #define DMA_CR_ECX_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 3400 | #define DMA_CR_ECX_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 3401 | #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3402 | #define DMA_CR_CX_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 3403 | #define DMA_CR_CX_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 3404 | #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3405 | |
AnnaBridge | 171:3a7713b1edbc | 3406 | /*! @name ES - Error Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 3407 | #define DMA_ES_DBE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 3408 | #define DMA_ES_DBE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3409 | #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3410 | #define DMA_ES_SBE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 3411 | #define DMA_ES_SBE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 3412 | #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3413 | #define DMA_ES_SGE_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 3414 | #define DMA_ES_SGE_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 3415 | #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3416 | #define DMA_ES_NCE_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 3417 | #define DMA_ES_NCE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 3418 | #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3419 | #define DMA_ES_DOE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 3420 | #define DMA_ES_DOE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 3421 | #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3422 | #define DMA_ES_DAE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 3423 | #define DMA_ES_DAE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 3424 | #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3425 | #define DMA_ES_SOE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 3426 | #define DMA_ES_SOE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 3427 | #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3428 | #define DMA_ES_SAE_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3429 | #define DMA_ES_SAE_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3430 | #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3431 | #define DMA_ES_ERRCHN_MASK (0x1F00U) |
AnnaBridge | 171:3a7713b1edbc | 3432 | #define DMA_ES_ERRCHN_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3433 | #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3434 | #define DMA_ES_CPE_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 3435 | #define DMA_ES_CPE_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 3436 | #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3437 | #define DMA_ES_GPE_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 3438 | #define DMA_ES_GPE_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 3439 | #define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3440 | #define DMA_ES_ECX_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 3441 | #define DMA_ES_ECX_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 3442 | #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3443 | #define DMA_ES_VLD_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 3444 | #define DMA_ES_VLD_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 3445 | #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3446 | |
AnnaBridge | 171:3a7713b1edbc | 3447 | /*! @name ERQ - Enable Request Register */ |
AnnaBridge | 171:3a7713b1edbc | 3448 | #define DMA_ERQ_ERQ0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 3449 | #define DMA_ERQ_ERQ0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3450 | #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3451 | #define DMA_ERQ_ERQ1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 3452 | #define DMA_ERQ_ERQ1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 3453 | #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3454 | #define DMA_ERQ_ERQ2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 3455 | #define DMA_ERQ_ERQ2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 3456 | #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3457 | #define DMA_ERQ_ERQ3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 3458 | #define DMA_ERQ_ERQ3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 3459 | #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3460 | #define DMA_ERQ_ERQ4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 3461 | #define DMA_ERQ_ERQ4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 3462 | #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3463 | #define DMA_ERQ_ERQ5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 3464 | #define DMA_ERQ_ERQ5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 3465 | #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3466 | #define DMA_ERQ_ERQ6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 3467 | #define DMA_ERQ_ERQ6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 3468 | #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3469 | #define DMA_ERQ_ERQ7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3470 | #define DMA_ERQ_ERQ7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3471 | #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3472 | #define DMA_ERQ_ERQ8_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 3473 | #define DMA_ERQ_ERQ8_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3474 | #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3475 | #define DMA_ERQ_ERQ9_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 3476 | #define DMA_ERQ_ERQ9_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 3477 | #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3478 | #define DMA_ERQ_ERQ10_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 3479 | #define DMA_ERQ_ERQ10_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 3480 | #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3481 | #define DMA_ERQ_ERQ11_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 3482 | #define DMA_ERQ_ERQ11_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 3483 | #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3484 | #define DMA_ERQ_ERQ12_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 3485 | #define DMA_ERQ_ERQ12_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 3486 | #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3487 | #define DMA_ERQ_ERQ13_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 3488 | #define DMA_ERQ_ERQ13_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 3489 | #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3490 | #define DMA_ERQ_ERQ14_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 3491 | #define DMA_ERQ_ERQ14_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 3492 | #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3493 | #define DMA_ERQ_ERQ15_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 3494 | #define DMA_ERQ_ERQ15_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 3495 | #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3496 | #define DMA_ERQ_ERQ16_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 3497 | #define DMA_ERQ_ERQ16_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 3498 | #define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3499 | #define DMA_ERQ_ERQ17_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 3500 | #define DMA_ERQ_ERQ17_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 3501 | #define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3502 | #define DMA_ERQ_ERQ18_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 3503 | #define DMA_ERQ_ERQ18_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 3504 | #define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3505 | #define DMA_ERQ_ERQ19_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 3506 | #define DMA_ERQ_ERQ19_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 3507 | #define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3508 | #define DMA_ERQ_ERQ20_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 3509 | #define DMA_ERQ_ERQ20_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 3510 | #define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3511 | #define DMA_ERQ_ERQ21_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 3512 | #define DMA_ERQ_ERQ21_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 3513 | #define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3514 | #define DMA_ERQ_ERQ22_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 3515 | #define DMA_ERQ_ERQ22_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 3516 | #define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3517 | #define DMA_ERQ_ERQ23_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 3518 | #define DMA_ERQ_ERQ23_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 3519 | #define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3520 | #define DMA_ERQ_ERQ24_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 3521 | #define DMA_ERQ_ERQ24_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 3522 | #define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3523 | #define DMA_ERQ_ERQ25_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 3524 | #define DMA_ERQ_ERQ25_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 3525 | #define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3526 | #define DMA_ERQ_ERQ26_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 3527 | #define DMA_ERQ_ERQ26_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 3528 | #define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3529 | #define DMA_ERQ_ERQ27_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 3530 | #define DMA_ERQ_ERQ27_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 3531 | #define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3532 | #define DMA_ERQ_ERQ28_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 3533 | #define DMA_ERQ_ERQ28_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 3534 | #define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3535 | #define DMA_ERQ_ERQ29_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 3536 | #define DMA_ERQ_ERQ29_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 3537 | #define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3538 | #define DMA_ERQ_ERQ30_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 3539 | #define DMA_ERQ_ERQ30_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 3540 | #define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3541 | #define DMA_ERQ_ERQ31_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 3542 | #define DMA_ERQ_ERQ31_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 3543 | #define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3544 | |
AnnaBridge | 171:3a7713b1edbc | 3545 | /*! @name EEI - Enable Error Interrupt Register */ |
AnnaBridge | 171:3a7713b1edbc | 3546 | #define DMA_EEI_EEI0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 3547 | #define DMA_EEI_EEI0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3548 | #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3549 | #define DMA_EEI_EEI1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 3550 | #define DMA_EEI_EEI1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 3551 | #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3552 | #define DMA_EEI_EEI2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 3553 | #define DMA_EEI_EEI2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 3554 | #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3555 | #define DMA_EEI_EEI3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 3556 | #define DMA_EEI_EEI3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 3557 | #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3558 | #define DMA_EEI_EEI4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 3559 | #define DMA_EEI_EEI4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 3560 | #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3561 | #define DMA_EEI_EEI5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 3562 | #define DMA_EEI_EEI5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 3563 | #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3564 | #define DMA_EEI_EEI6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 3565 | #define DMA_EEI_EEI6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 3566 | #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3567 | #define DMA_EEI_EEI7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3568 | #define DMA_EEI_EEI7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3569 | #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3570 | #define DMA_EEI_EEI8_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 3571 | #define DMA_EEI_EEI8_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3572 | #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3573 | #define DMA_EEI_EEI9_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 3574 | #define DMA_EEI_EEI9_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 3575 | #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3576 | #define DMA_EEI_EEI10_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 3577 | #define DMA_EEI_EEI10_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 3578 | #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3579 | #define DMA_EEI_EEI11_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 3580 | #define DMA_EEI_EEI11_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 3581 | #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3582 | #define DMA_EEI_EEI12_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 3583 | #define DMA_EEI_EEI12_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 3584 | #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3585 | #define DMA_EEI_EEI13_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 3586 | #define DMA_EEI_EEI13_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 3587 | #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3588 | #define DMA_EEI_EEI14_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 3589 | #define DMA_EEI_EEI14_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 3590 | #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3591 | #define DMA_EEI_EEI15_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 3592 | #define DMA_EEI_EEI15_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 3593 | #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3594 | #define DMA_EEI_EEI16_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 3595 | #define DMA_EEI_EEI16_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 3596 | #define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3597 | #define DMA_EEI_EEI17_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 3598 | #define DMA_EEI_EEI17_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 3599 | #define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3600 | #define DMA_EEI_EEI18_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 3601 | #define DMA_EEI_EEI18_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 3602 | #define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3603 | #define DMA_EEI_EEI19_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 3604 | #define DMA_EEI_EEI19_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 3605 | #define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3606 | #define DMA_EEI_EEI20_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 3607 | #define DMA_EEI_EEI20_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 3608 | #define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3609 | #define DMA_EEI_EEI21_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 3610 | #define DMA_EEI_EEI21_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 3611 | #define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3612 | #define DMA_EEI_EEI22_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 3613 | #define DMA_EEI_EEI22_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 3614 | #define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3615 | #define DMA_EEI_EEI23_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 3616 | #define DMA_EEI_EEI23_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 3617 | #define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3618 | #define DMA_EEI_EEI24_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 3619 | #define DMA_EEI_EEI24_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 3620 | #define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3621 | #define DMA_EEI_EEI25_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 3622 | #define DMA_EEI_EEI25_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 3623 | #define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3624 | #define DMA_EEI_EEI26_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 3625 | #define DMA_EEI_EEI26_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 3626 | #define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3627 | #define DMA_EEI_EEI27_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 3628 | #define DMA_EEI_EEI27_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 3629 | #define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3630 | #define DMA_EEI_EEI28_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 3631 | #define DMA_EEI_EEI28_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 3632 | #define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3633 | #define DMA_EEI_EEI29_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 3634 | #define DMA_EEI_EEI29_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 3635 | #define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3636 | #define DMA_EEI_EEI30_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 3637 | #define DMA_EEI_EEI30_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 3638 | #define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3639 | #define DMA_EEI_EEI31_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 3640 | #define DMA_EEI_EEI31_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 3641 | #define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3642 | |
AnnaBridge | 171:3a7713b1edbc | 3643 | /*! @name CEEI - Clear Enable Error Interrupt Register */ |
AnnaBridge | 171:3a7713b1edbc | 3644 | #define DMA_CEEI_CEEI_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 3645 | #define DMA_CEEI_CEEI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3646 | #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3647 | #define DMA_CEEI_CAEE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 3648 | #define DMA_CEEI_CAEE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 3649 | #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3650 | #define DMA_CEEI_NOP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3651 | #define DMA_CEEI_NOP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3652 | #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3653 | |
AnnaBridge | 171:3a7713b1edbc | 3654 | /*! @name SEEI - Set Enable Error Interrupt Register */ |
AnnaBridge | 171:3a7713b1edbc | 3655 | #define DMA_SEEI_SEEI_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 3656 | #define DMA_SEEI_SEEI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3657 | #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3658 | #define DMA_SEEI_SAEE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 3659 | #define DMA_SEEI_SAEE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 3660 | #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3661 | #define DMA_SEEI_NOP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3662 | #define DMA_SEEI_NOP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3663 | #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3664 | |
AnnaBridge | 171:3a7713b1edbc | 3665 | /*! @name CERQ - Clear Enable Request Register */ |
AnnaBridge | 171:3a7713b1edbc | 3666 | #define DMA_CERQ_CERQ_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 3667 | #define DMA_CERQ_CERQ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3668 | #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3669 | #define DMA_CERQ_CAER_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 3670 | #define DMA_CERQ_CAER_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 3671 | #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3672 | #define DMA_CERQ_NOP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3673 | #define DMA_CERQ_NOP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3674 | #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3675 | |
AnnaBridge | 171:3a7713b1edbc | 3676 | /*! @name SERQ - Set Enable Request Register */ |
AnnaBridge | 171:3a7713b1edbc | 3677 | #define DMA_SERQ_SERQ_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 3678 | #define DMA_SERQ_SERQ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3679 | #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3680 | #define DMA_SERQ_SAER_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 3681 | #define DMA_SERQ_SAER_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 3682 | #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3683 | #define DMA_SERQ_NOP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3684 | #define DMA_SERQ_NOP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3685 | #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3686 | |
AnnaBridge | 171:3a7713b1edbc | 3687 | /*! @name CDNE - Clear DONE Status Bit Register */ |
AnnaBridge | 171:3a7713b1edbc | 3688 | #define DMA_CDNE_CDNE_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 3689 | #define DMA_CDNE_CDNE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3690 | #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3691 | #define DMA_CDNE_CADN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 3692 | #define DMA_CDNE_CADN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 3693 | #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3694 | #define DMA_CDNE_NOP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3695 | #define DMA_CDNE_NOP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3696 | #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3697 | |
AnnaBridge | 171:3a7713b1edbc | 3698 | /*! @name SSRT - Set START Bit Register */ |
AnnaBridge | 171:3a7713b1edbc | 3699 | #define DMA_SSRT_SSRT_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 3700 | #define DMA_SSRT_SSRT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3701 | #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3702 | #define DMA_SSRT_SAST_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 3703 | #define DMA_SSRT_SAST_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 3704 | #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3705 | #define DMA_SSRT_NOP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3706 | #define DMA_SSRT_NOP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3707 | #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3708 | |
AnnaBridge | 171:3a7713b1edbc | 3709 | /*! @name CERR - Clear Error Register */ |
AnnaBridge | 171:3a7713b1edbc | 3710 | #define DMA_CERR_CERR_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 3711 | #define DMA_CERR_CERR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3712 | #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3713 | #define DMA_CERR_CAEI_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 3714 | #define DMA_CERR_CAEI_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 3715 | #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3716 | #define DMA_CERR_NOP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3717 | #define DMA_CERR_NOP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3718 | #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3719 | |
AnnaBridge | 171:3a7713b1edbc | 3720 | /*! @name CINT - Clear Interrupt Request Register */ |
AnnaBridge | 171:3a7713b1edbc | 3721 | #define DMA_CINT_CINT_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 3722 | #define DMA_CINT_CINT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3723 | #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3724 | #define DMA_CINT_CAIR_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 3725 | #define DMA_CINT_CAIR_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 3726 | #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3727 | #define DMA_CINT_NOP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3728 | #define DMA_CINT_NOP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3729 | #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3730 | |
AnnaBridge | 171:3a7713b1edbc | 3731 | /*! @name INT - Interrupt Request Register */ |
AnnaBridge | 171:3a7713b1edbc | 3732 | #define DMA_INT_INT0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 3733 | #define DMA_INT_INT0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3734 | #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3735 | #define DMA_INT_INT1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 3736 | #define DMA_INT_INT1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 3737 | #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3738 | #define DMA_INT_INT2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 3739 | #define DMA_INT_INT2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 3740 | #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3741 | #define DMA_INT_INT3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 3742 | #define DMA_INT_INT3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 3743 | #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3744 | #define DMA_INT_INT4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 3745 | #define DMA_INT_INT4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 3746 | #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3747 | #define DMA_INT_INT5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 3748 | #define DMA_INT_INT5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 3749 | #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3750 | #define DMA_INT_INT6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 3751 | #define DMA_INT_INT6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 3752 | #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3753 | #define DMA_INT_INT7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3754 | #define DMA_INT_INT7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3755 | #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3756 | #define DMA_INT_INT8_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 3757 | #define DMA_INT_INT8_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3758 | #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3759 | #define DMA_INT_INT9_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 3760 | #define DMA_INT_INT9_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 3761 | #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3762 | #define DMA_INT_INT10_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 3763 | #define DMA_INT_INT10_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 3764 | #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3765 | #define DMA_INT_INT11_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 3766 | #define DMA_INT_INT11_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 3767 | #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3768 | #define DMA_INT_INT12_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 3769 | #define DMA_INT_INT12_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 3770 | #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3771 | #define DMA_INT_INT13_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 3772 | #define DMA_INT_INT13_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 3773 | #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3774 | #define DMA_INT_INT14_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 3775 | #define DMA_INT_INT14_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 3776 | #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3777 | #define DMA_INT_INT15_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 3778 | #define DMA_INT_INT15_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 3779 | #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3780 | #define DMA_INT_INT16_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 3781 | #define DMA_INT_INT16_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 3782 | #define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3783 | #define DMA_INT_INT17_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 3784 | #define DMA_INT_INT17_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 3785 | #define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3786 | #define DMA_INT_INT18_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 3787 | #define DMA_INT_INT18_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 3788 | #define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3789 | #define DMA_INT_INT19_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 3790 | #define DMA_INT_INT19_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 3791 | #define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3792 | #define DMA_INT_INT20_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 3793 | #define DMA_INT_INT20_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 3794 | #define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3795 | #define DMA_INT_INT21_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 3796 | #define DMA_INT_INT21_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 3797 | #define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3798 | #define DMA_INT_INT22_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 3799 | #define DMA_INT_INT22_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 3800 | #define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3801 | #define DMA_INT_INT23_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 3802 | #define DMA_INT_INT23_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 3803 | #define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3804 | #define DMA_INT_INT24_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 3805 | #define DMA_INT_INT24_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 3806 | #define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3807 | #define DMA_INT_INT25_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 3808 | #define DMA_INT_INT25_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 3809 | #define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3810 | #define DMA_INT_INT26_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 3811 | #define DMA_INT_INT26_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 3812 | #define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3813 | #define DMA_INT_INT27_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 3814 | #define DMA_INT_INT27_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 3815 | #define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3816 | #define DMA_INT_INT28_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 3817 | #define DMA_INT_INT28_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 3818 | #define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3819 | #define DMA_INT_INT29_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 3820 | #define DMA_INT_INT29_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 3821 | #define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3822 | #define DMA_INT_INT30_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 3823 | #define DMA_INT_INT30_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 3824 | #define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3825 | #define DMA_INT_INT31_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 3826 | #define DMA_INT_INT31_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 3827 | #define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3828 | |
AnnaBridge | 171:3a7713b1edbc | 3829 | /*! @name ERR - Error Register */ |
AnnaBridge | 171:3a7713b1edbc | 3830 | #define DMA_ERR_ERR0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 3831 | #define DMA_ERR_ERR0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3832 | #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3833 | #define DMA_ERR_ERR1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 3834 | #define DMA_ERR_ERR1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 3835 | #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3836 | #define DMA_ERR_ERR2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 3837 | #define DMA_ERR_ERR2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 3838 | #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3839 | #define DMA_ERR_ERR3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 3840 | #define DMA_ERR_ERR3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 3841 | #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3842 | #define DMA_ERR_ERR4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 3843 | #define DMA_ERR_ERR4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 3844 | #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3845 | #define DMA_ERR_ERR5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 3846 | #define DMA_ERR_ERR5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 3847 | #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3848 | #define DMA_ERR_ERR6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 3849 | #define DMA_ERR_ERR6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 3850 | #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3851 | #define DMA_ERR_ERR7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3852 | #define DMA_ERR_ERR7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3853 | #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3854 | #define DMA_ERR_ERR8_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 3855 | #define DMA_ERR_ERR8_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3856 | #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3857 | #define DMA_ERR_ERR9_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 3858 | #define DMA_ERR_ERR9_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 3859 | #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3860 | #define DMA_ERR_ERR10_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 3861 | #define DMA_ERR_ERR10_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 3862 | #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3863 | #define DMA_ERR_ERR11_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 3864 | #define DMA_ERR_ERR11_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 3865 | #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3866 | #define DMA_ERR_ERR12_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 3867 | #define DMA_ERR_ERR12_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 3868 | #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3869 | #define DMA_ERR_ERR13_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 3870 | #define DMA_ERR_ERR13_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 3871 | #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3872 | #define DMA_ERR_ERR14_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 3873 | #define DMA_ERR_ERR14_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 3874 | #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3875 | #define DMA_ERR_ERR15_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 3876 | #define DMA_ERR_ERR15_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 3877 | #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3878 | #define DMA_ERR_ERR16_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 3879 | #define DMA_ERR_ERR16_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 3880 | #define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3881 | #define DMA_ERR_ERR17_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 3882 | #define DMA_ERR_ERR17_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 3883 | #define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3884 | #define DMA_ERR_ERR18_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 3885 | #define DMA_ERR_ERR18_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 3886 | #define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3887 | #define DMA_ERR_ERR19_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 3888 | #define DMA_ERR_ERR19_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 3889 | #define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3890 | #define DMA_ERR_ERR20_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 3891 | #define DMA_ERR_ERR20_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 3892 | #define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3893 | #define DMA_ERR_ERR21_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 3894 | #define DMA_ERR_ERR21_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 3895 | #define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3896 | #define DMA_ERR_ERR22_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 3897 | #define DMA_ERR_ERR22_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 3898 | #define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3899 | #define DMA_ERR_ERR23_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 3900 | #define DMA_ERR_ERR23_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 3901 | #define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3902 | #define DMA_ERR_ERR24_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 3903 | #define DMA_ERR_ERR24_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 3904 | #define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3905 | #define DMA_ERR_ERR25_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 3906 | #define DMA_ERR_ERR25_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 3907 | #define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3908 | #define DMA_ERR_ERR26_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 3909 | #define DMA_ERR_ERR26_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 3910 | #define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3911 | #define DMA_ERR_ERR27_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 3912 | #define DMA_ERR_ERR27_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 3913 | #define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3914 | #define DMA_ERR_ERR28_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 3915 | #define DMA_ERR_ERR28_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 3916 | #define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3917 | #define DMA_ERR_ERR29_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 3918 | #define DMA_ERR_ERR29_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 3919 | #define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3920 | #define DMA_ERR_ERR30_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 3921 | #define DMA_ERR_ERR30_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 3922 | #define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3923 | #define DMA_ERR_ERR31_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 3924 | #define DMA_ERR_ERR31_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 3925 | #define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3926 | |
AnnaBridge | 171:3a7713b1edbc | 3927 | /*! @name HRS - Hardware Request Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 3928 | #define DMA_HRS_HRS0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 3929 | #define DMA_HRS_HRS0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3930 | #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3931 | #define DMA_HRS_HRS1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 3932 | #define DMA_HRS_HRS1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 3933 | #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3934 | #define DMA_HRS_HRS2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 3935 | #define DMA_HRS_HRS2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 3936 | #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3937 | #define DMA_HRS_HRS3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 3938 | #define DMA_HRS_HRS3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 3939 | #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3940 | #define DMA_HRS_HRS4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 3941 | #define DMA_HRS_HRS4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 3942 | #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3943 | #define DMA_HRS_HRS5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 3944 | #define DMA_HRS_HRS5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 3945 | #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3946 | #define DMA_HRS_HRS6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 3947 | #define DMA_HRS_HRS6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 3948 | #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3949 | #define DMA_HRS_HRS7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3950 | #define DMA_HRS_HRS7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3951 | #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3952 | #define DMA_HRS_HRS8_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 3953 | #define DMA_HRS_HRS8_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3954 | #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3955 | #define DMA_HRS_HRS9_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 3956 | #define DMA_HRS_HRS9_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 3957 | #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3958 | #define DMA_HRS_HRS10_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 3959 | #define DMA_HRS_HRS10_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 3960 | #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3961 | #define DMA_HRS_HRS11_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 3962 | #define DMA_HRS_HRS11_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 3963 | #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3964 | #define DMA_HRS_HRS12_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 3965 | #define DMA_HRS_HRS12_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 3966 | #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3967 | #define DMA_HRS_HRS13_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 3968 | #define DMA_HRS_HRS13_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 3969 | #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3970 | #define DMA_HRS_HRS14_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 3971 | #define DMA_HRS_HRS14_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 3972 | #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3973 | #define DMA_HRS_HRS15_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 3974 | #define DMA_HRS_HRS15_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 3975 | #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3976 | #define DMA_HRS_HRS16_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 3977 | #define DMA_HRS_HRS16_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 3978 | #define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3979 | #define DMA_HRS_HRS17_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 3980 | #define DMA_HRS_HRS17_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 3981 | #define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3982 | #define DMA_HRS_HRS18_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 3983 | #define DMA_HRS_HRS18_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 3984 | #define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3985 | #define DMA_HRS_HRS19_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 3986 | #define DMA_HRS_HRS19_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 3987 | #define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3988 | #define DMA_HRS_HRS20_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 3989 | #define DMA_HRS_HRS20_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 3990 | #define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3991 | #define DMA_HRS_HRS21_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 3992 | #define DMA_HRS_HRS21_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 3993 | #define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3994 | #define DMA_HRS_HRS22_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 3995 | #define DMA_HRS_HRS22_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 3996 | #define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3997 | #define DMA_HRS_HRS23_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 3998 | #define DMA_HRS_HRS23_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 3999 | #define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4000 | #define DMA_HRS_HRS24_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 4001 | #define DMA_HRS_HRS24_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 4002 | #define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4003 | #define DMA_HRS_HRS25_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 4004 | #define DMA_HRS_HRS25_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 4005 | #define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4006 | #define DMA_HRS_HRS26_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 4007 | #define DMA_HRS_HRS26_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 4008 | #define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4009 | #define DMA_HRS_HRS27_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 4010 | #define DMA_HRS_HRS27_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 4011 | #define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4012 | #define DMA_HRS_HRS28_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 4013 | #define DMA_HRS_HRS28_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 4014 | #define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4015 | #define DMA_HRS_HRS29_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 4016 | #define DMA_HRS_HRS29_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 4017 | #define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4018 | #define DMA_HRS_HRS30_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 4019 | #define DMA_HRS_HRS30_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 4020 | #define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4021 | #define DMA_HRS_HRS31_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 4022 | #define DMA_HRS_HRS31_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 4023 | #define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4024 | |
AnnaBridge | 171:3a7713b1edbc | 4025 | /*! @name EARS - Enable Asynchronous Request in Stop Register */ |
AnnaBridge | 171:3a7713b1edbc | 4026 | #define DMA_EARS_EDREQ_0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 4027 | #define DMA_EARS_EDREQ_0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4028 | #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4029 | #define DMA_EARS_EDREQ_1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 4030 | #define DMA_EARS_EDREQ_1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 4031 | #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4032 | #define DMA_EARS_EDREQ_2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 4033 | #define DMA_EARS_EDREQ_2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4034 | #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4035 | #define DMA_EARS_EDREQ_3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 4036 | #define DMA_EARS_EDREQ_3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 4037 | #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4038 | #define DMA_EARS_EDREQ_4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 4039 | #define DMA_EARS_EDREQ_4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4040 | #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4041 | #define DMA_EARS_EDREQ_5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 4042 | #define DMA_EARS_EDREQ_5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 4043 | #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4044 | #define DMA_EARS_EDREQ_6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4045 | #define DMA_EARS_EDREQ_6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4046 | #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4047 | #define DMA_EARS_EDREQ_7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4048 | #define DMA_EARS_EDREQ_7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4049 | #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4050 | #define DMA_EARS_EDREQ_8_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 4051 | #define DMA_EARS_EDREQ_8_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 4052 | #define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4053 | #define DMA_EARS_EDREQ_9_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 4054 | #define DMA_EARS_EDREQ_9_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 4055 | #define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4056 | #define DMA_EARS_EDREQ_10_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 4057 | #define DMA_EARS_EDREQ_10_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 4058 | #define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4059 | #define DMA_EARS_EDREQ_11_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 4060 | #define DMA_EARS_EDREQ_11_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 4061 | #define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4062 | #define DMA_EARS_EDREQ_12_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 4063 | #define DMA_EARS_EDREQ_12_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 4064 | #define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4065 | #define DMA_EARS_EDREQ_13_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 4066 | #define DMA_EARS_EDREQ_13_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 4067 | #define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4068 | #define DMA_EARS_EDREQ_14_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 4069 | #define DMA_EARS_EDREQ_14_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 4070 | #define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4071 | #define DMA_EARS_EDREQ_15_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 4072 | #define DMA_EARS_EDREQ_15_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 4073 | #define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4074 | #define DMA_EARS_EDREQ_16_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 4075 | #define DMA_EARS_EDREQ_16_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 4076 | #define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4077 | #define DMA_EARS_EDREQ_17_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 4078 | #define DMA_EARS_EDREQ_17_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 4079 | #define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4080 | #define DMA_EARS_EDREQ_18_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 4081 | #define DMA_EARS_EDREQ_18_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 4082 | #define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4083 | #define DMA_EARS_EDREQ_19_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 4084 | #define DMA_EARS_EDREQ_19_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 4085 | #define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4086 | #define DMA_EARS_EDREQ_20_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 4087 | #define DMA_EARS_EDREQ_20_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 4088 | #define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4089 | #define DMA_EARS_EDREQ_21_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 4090 | #define DMA_EARS_EDREQ_21_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 4091 | #define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4092 | #define DMA_EARS_EDREQ_22_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 4093 | #define DMA_EARS_EDREQ_22_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 4094 | #define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4095 | #define DMA_EARS_EDREQ_23_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 4096 | #define DMA_EARS_EDREQ_23_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 4097 | #define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4098 | #define DMA_EARS_EDREQ_24_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 4099 | #define DMA_EARS_EDREQ_24_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 4100 | #define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4101 | #define DMA_EARS_EDREQ_25_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 4102 | #define DMA_EARS_EDREQ_25_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 4103 | #define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4104 | #define DMA_EARS_EDREQ_26_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 4105 | #define DMA_EARS_EDREQ_26_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 4106 | #define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4107 | #define DMA_EARS_EDREQ_27_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 4108 | #define DMA_EARS_EDREQ_27_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 4109 | #define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4110 | #define DMA_EARS_EDREQ_28_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 4111 | #define DMA_EARS_EDREQ_28_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 4112 | #define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4113 | #define DMA_EARS_EDREQ_29_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 4114 | #define DMA_EARS_EDREQ_29_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 4115 | #define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4116 | #define DMA_EARS_EDREQ_30_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 4117 | #define DMA_EARS_EDREQ_30_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 4118 | #define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4119 | #define DMA_EARS_EDREQ_31_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 4120 | #define DMA_EARS_EDREQ_31_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 4121 | #define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4122 | |
AnnaBridge | 171:3a7713b1edbc | 4123 | /*! @name DCHPRI3 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4124 | #define DMA_DCHPRI3_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4125 | #define DMA_DCHPRI3_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4126 | #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4127 | #define DMA_DCHPRI3_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4128 | #define DMA_DCHPRI3_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4129 | #define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4130 | #define DMA_DCHPRI3_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4131 | #define DMA_DCHPRI3_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4132 | #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4133 | #define DMA_DCHPRI3_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4134 | #define DMA_DCHPRI3_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4135 | #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4136 | |
AnnaBridge | 171:3a7713b1edbc | 4137 | /*! @name DCHPRI2 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4138 | #define DMA_DCHPRI2_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4139 | #define DMA_DCHPRI2_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4140 | #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4141 | #define DMA_DCHPRI2_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4142 | #define DMA_DCHPRI2_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4143 | #define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4144 | #define DMA_DCHPRI2_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4145 | #define DMA_DCHPRI2_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4146 | #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4147 | #define DMA_DCHPRI2_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4148 | #define DMA_DCHPRI2_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4149 | #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4150 | |
AnnaBridge | 171:3a7713b1edbc | 4151 | /*! @name DCHPRI1 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4152 | #define DMA_DCHPRI1_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4153 | #define DMA_DCHPRI1_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4154 | #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4155 | #define DMA_DCHPRI1_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4156 | #define DMA_DCHPRI1_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4157 | #define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4158 | #define DMA_DCHPRI1_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4159 | #define DMA_DCHPRI1_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4160 | #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4161 | #define DMA_DCHPRI1_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4162 | #define DMA_DCHPRI1_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4163 | #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4164 | |
AnnaBridge | 171:3a7713b1edbc | 4165 | /*! @name DCHPRI0 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4166 | #define DMA_DCHPRI0_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4167 | #define DMA_DCHPRI0_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4168 | #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4169 | #define DMA_DCHPRI0_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4170 | #define DMA_DCHPRI0_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4171 | #define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4172 | #define DMA_DCHPRI0_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4173 | #define DMA_DCHPRI0_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4174 | #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4175 | #define DMA_DCHPRI0_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4176 | #define DMA_DCHPRI0_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4177 | #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4178 | |
AnnaBridge | 171:3a7713b1edbc | 4179 | /*! @name DCHPRI7 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4180 | #define DMA_DCHPRI7_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4181 | #define DMA_DCHPRI7_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4182 | #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4183 | #define DMA_DCHPRI7_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4184 | #define DMA_DCHPRI7_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4185 | #define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4186 | #define DMA_DCHPRI7_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4187 | #define DMA_DCHPRI7_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4188 | #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4189 | #define DMA_DCHPRI7_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4190 | #define DMA_DCHPRI7_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4191 | #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4192 | |
AnnaBridge | 171:3a7713b1edbc | 4193 | /*! @name DCHPRI6 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4194 | #define DMA_DCHPRI6_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4195 | #define DMA_DCHPRI6_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4196 | #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4197 | #define DMA_DCHPRI6_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4198 | #define DMA_DCHPRI6_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4199 | #define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4200 | #define DMA_DCHPRI6_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4201 | #define DMA_DCHPRI6_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4202 | #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4203 | #define DMA_DCHPRI6_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4204 | #define DMA_DCHPRI6_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4205 | #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4206 | |
AnnaBridge | 171:3a7713b1edbc | 4207 | /*! @name DCHPRI5 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4208 | #define DMA_DCHPRI5_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4209 | #define DMA_DCHPRI5_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4210 | #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4211 | #define DMA_DCHPRI5_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4212 | #define DMA_DCHPRI5_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4213 | #define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4214 | #define DMA_DCHPRI5_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4215 | #define DMA_DCHPRI5_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4216 | #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4217 | #define DMA_DCHPRI5_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4218 | #define DMA_DCHPRI5_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4219 | #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4220 | |
AnnaBridge | 171:3a7713b1edbc | 4221 | /*! @name DCHPRI4 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4222 | #define DMA_DCHPRI4_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4223 | #define DMA_DCHPRI4_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4224 | #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4225 | #define DMA_DCHPRI4_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4226 | #define DMA_DCHPRI4_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4227 | #define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4228 | #define DMA_DCHPRI4_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4229 | #define DMA_DCHPRI4_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4230 | #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4231 | #define DMA_DCHPRI4_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4232 | #define DMA_DCHPRI4_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4233 | #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4234 | |
AnnaBridge | 171:3a7713b1edbc | 4235 | /*! @name DCHPRI11 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4236 | #define DMA_DCHPRI11_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4237 | #define DMA_DCHPRI11_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4238 | #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4239 | #define DMA_DCHPRI11_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4240 | #define DMA_DCHPRI11_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4241 | #define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4242 | #define DMA_DCHPRI11_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4243 | #define DMA_DCHPRI11_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4244 | #define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4245 | #define DMA_DCHPRI11_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4246 | #define DMA_DCHPRI11_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4247 | #define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4248 | |
AnnaBridge | 171:3a7713b1edbc | 4249 | /*! @name DCHPRI10 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4250 | #define DMA_DCHPRI10_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4251 | #define DMA_DCHPRI10_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4252 | #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4253 | #define DMA_DCHPRI10_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4254 | #define DMA_DCHPRI10_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4255 | #define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4256 | #define DMA_DCHPRI10_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4257 | #define DMA_DCHPRI10_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4258 | #define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4259 | #define DMA_DCHPRI10_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4260 | #define DMA_DCHPRI10_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4261 | #define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4262 | |
AnnaBridge | 171:3a7713b1edbc | 4263 | /*! @name DCHPRI9 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4264 | #define DMA_DCHPRI9_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4265 | #define DMA_DCHPRI9_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4266 | #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4267 | #define DMA_DCHPRI9_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4268 | #define DMA_DCHPRI9_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4269 | #define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4270 | #define DMA_DCHPRI9_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4271 | #define DMA_DCHPRI9_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4272 | #define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4273 | #define DMA_DCHPRI9_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4274 | #define DMA_DCHPRI9_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4275 | #define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4276 | |
AnnaBridge | 171:3a7713b1edbc | 4277 | /*! @name DCHPRI8 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4278 | #define DMA_DCHPRI8_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4279 | #define DMA_DCHPRI8_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4280 | #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4281 | #define DMA_DCHPRI8_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4282 | #define DMA_DCHPRI8_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4283 | #define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4284 | #define DMA_DCHPRI8_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4285 | #define DMA_DCHPRI8_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4286 | #define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4287 | #define DMA_DCHPRI8_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4288 | #define DMA_DCHPRI8_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4289 | #define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4290 | |
AnnaBridge | 171:3a7713b1edbc | 4291 | /*! @name DCHPRI15 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4292 | #define DMA_DCHPRI15_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4293 | #define DMA_DCHPRI15_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4294 | #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4295 | #define DMA_DCHPRI15_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4296 | #define DMA_DCHPRI15_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4297 | #define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4298 | #define DMA_DCHPRI15_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4299 | #define DMA_DCHPRI15_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4300 | #define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4301 | #define DMA_DCHPRI15_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4302 | #define DMA_DCHPRI15_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4303 | #define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4304 | |
AnnaBridge | 171:3a7713b1edbc | 4305 | /*! @name DCHPRI14 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4306 | #define DMA_DCHPRI14_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4307 | #define DMA_DCHPRI14_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4308 | #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4309 | #define DMA_DCHPRI14_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4310 | #define DMA_DCHPRI14_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4311 | #define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4312 | #define DMA_DCHPRI14_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4313 | #define DMA_DCHPRI14_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4314 | #define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4315 | #define DMA_DCHPRI14_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4316 | #define DMA_DCHPRI14_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4317 | #define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4318 | |
AnnaBridge | 171:3a7713b1edbc | 4319 | /*! @name DCHPRI13 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4320 | #define DMA_DCHPRI13_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4321 | #define DMA_DCHPRI13_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4322 | #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4323 | #define DMA_DCHPRI13_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4324 | #define DMA_DCHPRI13_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4325 | #define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4326 | #define DMA_DCHPRI13_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4327 | #define DMA_DCHPRI13_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4328 | #define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4329 | #define DMA_DCHPRI13_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4330 | #define DMA_DCHPRI13_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4331 | #define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4332 | |
AnnaBridge | 171:3a7713b1edbc | 4333 | /*! @name DCHPRI12 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4334 | #define DMA_DCHPRI12_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4335 | #define DMA_DCHPRI12_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4336 | #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4337 | #define DMA_DCHPRI12_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4338 | #define DMA_DCHPRI12_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4339 | #define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4340 | #define DMA_DCHPRI12_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4341 | #define DMA_DCHPRI12_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4342 | #define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4343 | #define DMA_DCHPRI12_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4344 | #define DMA_DCHPRI12_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4345 | #define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4346 | |
AnnaBridge | 171:3a7713b1edbc | 4347 | /*! @name DCHPRI19 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4348 | #define DMA_DCHPRI19_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4349 | #define DMA_DCHPRI19_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4350 | #define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4351 | #define DMA_DCHPRI19_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4352 | #define DMA_DCHPRI19_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4353 | #define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4354 | #define DMA_DCHPRI19_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4355 | #define DMA_DCHPRI19_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4356 | #define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4357 | #define DMA_DCHPRI19_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4358 | #define DMA_DCHPRI19_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4359 | #define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4360 | |
AnnaBridge | 171:3a7713b1edbc | 4361 | /*! @name DCHPRI18 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4362 | #define DMA_DCHPRI18_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4363 | #define DMA_DCHPRI18_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4364 | #define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4365 | #define DMA_DCHPRI18_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4366 | #define DMA_DCHPRI18_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4367 | #define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4368 | #define DMA_DCHPRI18_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4369 | #define DMA_DCHPRI18_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4370 | #define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4371 | #define DMA_DCHPRI18_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4372 | #define DMA_DCHPRI18_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4373 | #define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4374 | |
AnnaBridge | 171:3a7713b1edbc | 4375 | /*! @name DCHPRI17 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4376 | #define DMA_DCHPRI17_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4377 | #define DMA_DCHPRI17_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4378 | #define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4379 | #define DMA_DCHPRI17_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4380 | #define DMA_DCHPRI17_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4381 | #define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4382 | #define DMA_DCHPRI17_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4383 | #define DMA_DCHPRI17_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4384 | #define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4385 | #define DMA_DCHPRI17_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4386 | #define DMA_DCHPRI17_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4387 | #define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4388 | |
AnnaBridge | 171:3a7713b1edbc | 4389 | /*! @name DCHPRI16 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4390 | #define DMA_DCHPRI16_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4391 | #define DMA_DCHPRI16_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4392 | #define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4393 | #define DMA_DCHPRI16_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4394 | #define DMA_DCHPRI16_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4395 | #define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4396 | #define DMA_DCHPRI16_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4397 | #define DMA_DCHPRI16_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4398 | #define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4399 | #define DMA_DCHPRI16_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4400 | #define DMA_DCHPRI16_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4401 | #define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4402 | |
AnnaBridge | 171:3a7713b1edbc | 4403 | /*! @name DCHPRI23 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4404 | #define DMA_DCHPRI23_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4405 | #define DMA_DCHPRI23_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4406 | #define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4407 | #define DMA_DCHPRI23_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4408 | #define DMA_DCHPRI23_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4409 | #define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4410 | #define DMA_DCHPRI23_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4411 | #define DMA_DCHPRI23_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4412 | #define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4413 | #define DMA_DCHPRI23_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4414 | #define DMA_DCHPRI23_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4415 | #define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4416 | |
AnnaBridge | 171:3a7713b1edbc | 4417 | /*! @name DCHPRI22 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4418 | #define DMA_DCHPRI22_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4419 | #define DMA_DCHPRI22_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4420 | #define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4421 | #define DMA_DCHPRI22_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4422 | #define DMA_DCHPRI22_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4423 | #define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4424 | #define DMA_DCHPRI22_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4425 | #define DMA_DCHPRI22_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4426 | #define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4427 | #define DMA_DCHPRI22_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4428 | #define DMA_DCHPRI22_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4429 | #define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4430 | |
AnnaBridge | 171:3a7713b1edbc | 4431 | /*! @name DCHPRI21 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4432 | #define DMA_DCHPRI21_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4433 | #define DMA_DCHPRI21_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4434 | #define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4435 | #define DMA_DCHPRI21_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4436 | #define DMA_DCHPRI21_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4437 | #define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4438 | #define DMA_DCHPRI21_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4439 | #define DMA_DCHPRI21_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4440 | #define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4441 | #define DMA_DCHPRI21_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4442 | #define DMA_DCHPRI21_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4443 | #define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4444 | |
AnnaBridge | 171:3a7713b1edbc | 4445 | /*! @name DCHPRI20 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4446 | #define DMA_DCHPRI20_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4447 | #define DMA_DCHPRI20_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4448 | #define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4449 | #define DMA_DCHPRI20_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4450 | #define DMA_DCHPRI20_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4451 | #define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4452 | #define DMA_DCHPRI20_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4453 | #define DMA_DCHPRI20_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4454 | #define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4455 | #define DMA_DCHPRI20_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4456 | #define DMA_DCHPRI20_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4457 | #define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4458 | |
AnnaBridge | 171:3a7713b1edbc | 4459 | /*! @name DCHPRI27 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4460 | #define DMA_DCHPRI27_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4461 | #define DMA_DCHPRI27_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4462 | #define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4463 | #define DMA_DCHPRI27_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4464 | #define DMA_DCHPRI27_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4465 | #define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4466 | #define DMA_DCHPRI27_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4467 | #define DMA_DCHPRI27_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4468 | #define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4469 | #define DMA_DCHPRI27_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4470 | #define DMA_DCHPRI27_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4471 | #define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4472 | |
AnnaBridge | 171:3a7713b1edbc | 4473 | /*! @name DCHPRI26 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4474 | #define DMA_DCHPRI26_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4475 | #define DMA_DCHPRI26_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4476 | #define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4477 | #define DMA_DCHPRI26_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4478 | #define DMA_DCHPRI26_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4479 | #define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4480 | #define DMA_DCHPRI26_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4481 | #define DMA_DCHPRI26_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4482 | #define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4483 | #define DMA_DCHPRI26_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4484 | #define DMA_DCHPRI26_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4485 | #define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4486 | |
AnnaBridge | 171:3a7713b1edbc | 4487 | /*! @name DCHPRI25 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4488 | #define DMA_DCHPRI25_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4489 | #define DMA_DCHPRI25_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4490 | #define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4491 | #define DMA_DCHPRI25_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4492 | #define DMA_DCHPRI25_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4493 | #define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4494 | #define DMA_DCHPRI25_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4495 | #define DMA_DCHPRI25_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4496 | #define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4497 | #define DMA_DCHPRI25_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4498 | #define DMA_DCHPRI25_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4499 | #define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4500 | |
AnnaBridge | 171:3a7713b1edbc | 4501 | /*! @name DCHPRI24 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4502 | #define DMA_DCHPRI24_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4503 | #define DMA_DCHPRI24_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4504 | #define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4505 | #define DMA_DCHPRI24_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4506 | #define DMA_DCHPRI24_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4507 | #define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4508 | #define DMA_DCHPRI24_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4509 | #define DMA_DCHPRI24_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4510 | #define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4511 | #define DMA_DCHPRI24_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4512 | #define DMA_DCHPRI24_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4513 | #define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4514 | |
AnnaBridge | 171:3a7713b1edbc | 4515 | /*! @name DCHPRI31 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4516 | #define DMA_DCHPRI31_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4517 | #define DMA_DCHPRI31_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4518 | #define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4519 | #define DMA_DCHPRI31_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4520 | #define DMA_DCHPRI31_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4521 | #define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4522 | #define DMA_DCHPRI31_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4523 | #define DMA_DCHPRI31_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4524 | #define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4525 | #define DMA_DCHPRI31_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4526 | #define DMA_DCHPRI31_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4527 | #define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4528 | |
AnnaBridge | 171:3a7713b1edbc | 4529 | /*! @name DCHPRI30 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4530 | #define DMA_DCHPRI30_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4531 | #define DMA_DCHPRI30_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4532 | #define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4533 | #define DMA_DCHPRI30_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4534 | #define DMA_DCHPRI30_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4535 | #define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4536 | #define DMA_DCHPRI30_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4537 | #define DMA_DCHPRI30_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4538 | #define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4539 | #define DMA_DCHPRI30_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4540 | #define DMA_DCHPRI30_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4541 | #define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4542 | |
AnnaBridge | 171:3a7713b1edbc | 4543 | /*! @name DCHPRI29 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4544 | #define DMA_DCHPRI29_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4545 | #define DMA_DCHPRI29_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4546 | #define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4547 | #define DMA_DCHPRI29_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4548 | #define DMA_DCHPRI29_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4549 | #define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4550 | #define DMA_DCHPRI29_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4551 | #define DMA_DCHPRI29_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4552 | #define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4553 | #define DMA_DCHPRI29_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4554 | #define DMA_DCHPRI29_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4555 | #define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4556 | |
AnnaBridge | 171:3a7713b1edbc | 4557 | /*! @name DCHPRI28 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 4558 | #define DMA_DCHPRI28_CHPRI_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4559 | #define DMA_DCHPRI28_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4560 | #define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4561 | #define DMA_DCHPRI28_GRPPRI_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4562 | #define DMA_DCHPRI28_GRPPRI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4563 | #define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4564 | #define DMA_DCHPRI28_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4565 | #define DMA_DCHPRI28_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4566 | #define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4567 | #define DMA_DCHPRI28_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4568 | #define DMA_DCHPRI28_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4569 | #define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4570 | |
AnnaBridge | 171:3a7713b1edbc | 4571 | /*! @name SADDR - TCD Source Address */ |
AnnaBridge | 171:3a7713b1edbc | 4572 | #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 4573 | #define DMA_SADDR_SADDR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4574 | #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4575 | |
AnnaBridge | 171:3a7713b1edbc | 4576 | /* The count of DMA_SADDR */ |
AnnaBridge | 171:3a7713b1edbc | 4577 | #define DMA_SADDR_COUNT (32U) |
AnnaBridge | 171:3a7713b1edbc | 4578 | |
AnnaBridge | 171:3a7713b1edbc | 4579 | /*! @name SOFF - TCD Signed Source Address Offset */ |
AnnaBridge | 171:3a7713b1edbc | 4580 | #define DMA_SOFF_SOFF_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 4581 | #define DMA_SOFF_SOFF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4582 | #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4583 | |
AnnaBridge | 171:3a7713b1edbc | 4584 | /* The count of DMA_SOFF */ |
AnnaBridge | 171:3a7713b1edbc | 4585 | #define DMA_SOFF_COUNT (32U) |
AnnaBridge | 171:3a7713b1edbc | 4586 | |
AnnaBridge | 171:3a7713b1edbc | 4587 | /*! @name ATTR - TCD Transfer Attributes */ |
AnnaBridge | 171:3a7713b1edbc | 4588 | #define DMA_ATTR_DSIZE_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 4589 | #define DMA_ATTR_DSIZE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4590 | #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4591 | #define DMA_ATTR_DMOD_MASK (0xF8U) |
AnnaBridge | 171:3a7713b1edbc | 4592 | #define DMA_ATTR_DMOD_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 4593 | #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4594 | #define DMA_ATTR_SSIZE_MASK (0x700U) |
AnnaBridge | 171:3a7713b1edbc | 4595 | #define DMA_ATTR_SSIZE_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 4596 | #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4597 | #define DMA_ATTR_SMOD_MASK (0xF800U) |
AnnaBridge | 171:3a7713b1edbc | 4598 | #define DMA_ATTR_SMOD_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 4599 | #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4600 | |
AnnaBridge | 171:3a7713b1edbc | 4601 | /* The count of DMA_ATTR */ |
AnnaBridge | 171:3a7713b1edbc | 4602 | #define DMA_ATTR_COUNT (32U) |
AnnaBridge | 171:3a7713b1edbc | 4603 | |
AnnaBridge | 171:3a7713b1edbc | 4604 | /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */ |
AnnaBridge | 171:3a7713b1edbc | 4605 | #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 4606 | #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4607 | #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4608 | |
AnnaBridge | 171:3a7713b1edbc | 4609 | /* The count of DMA_NBYTES_MLNO */ |
AnnaBridge | 171:3a7713b1edbc | 4610 | #define DMA_NBYTES_MLNO_COUNT (32U) |
AnnaBridge | 171:3a7713b1edbc | 4611 | |
AnnaBridge | 171:3a7713b1edbc | 4612 | /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */ |
AnnaBridge | 171:3a7713b1edbc | 4613 | #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 4614 | #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4615 | #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4616 | #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 4617 | #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 4618 | #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4619 | #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 4620 | #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 4621 | #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4622 | |
AnnaBridge | 171:3a7713b1edbc | 4623 | /* The count of DMA_NBYTES_MLOFFNO */ |
AnnaBridge | 171:3a7713b1edbc | 4624 | #define DMA_NBYTES_MLOFFNO_COUNT (32U) |
AnnaBridge | 171:3a7713b1edbc | 4625 | |
AnnaBridge | 171:3a7713b1edbc | 4626 | /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */ |
AnnaBridge | 171:3a7713b1edbc | 4627 | #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) |
AnnaBridge | 171:3a7713b1edbc | 4628 | #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4629 | #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4630 | #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) |
AnnaBridge | 171:3a7713b1edbc | 4631 | #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 4632 | #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4633 | #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 4634 | #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 4635 | #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4636 | #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 4637 | #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 4638 | #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4639 | |
AnnaBridge | 171:3a7713b1edbc | 4640 | /* The count of DMA_NBYTES_MLOFFYES */ |
AnnaBridge | 171:3a7713b1edbc | 4641 | #define DMA_NBYTES_MLOFFYES_COUNT (32U) |
AnnaBridge | 171:3a7713b1edbc | 4642 | |
AnnaBridge | 171:3a7713b1edbc | 4643 | /*! @name SLAST - TCD Last Source Address Adjustment */ |
AnnaBridge | 171:3a7713b1edbc | 4644 | #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 4645 | #define DMA_SLAST_SLAST_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4646 | #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4647 | |
AnnaBridge | 171:3a7713b1edbc | 4648 | /* The count of DMA_SLAST */ |
AnnaBridge | 171:3a7713b1edbc | 4649 | #define DMA_SLAST_COUNT (32U) |
AnnaBridge | 171:3a7713b1edbc | 4650 | |
AnnaBridge | 171:3a7713b1edbc | 4651 | /*! @name DADDR - TCD Destination Address */ |
AnnaBridge | 171:3a7713b1edbc | 4652 | #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 4653 | #define DMA_DADDR_DADDR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4654 | #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4655 | |
AnnaBridge | 171:3a7713b1edbc | 4656 | /* The count of DMA_DADDR */ |
AnnaBridge | 171:3a7713b1edbc | 4657 | #define DMA_DADDR_COUNT (32U) |
AnnaBridge | 171:3a7713b1edbc | 4658 | |
AnnaBridge | 171:3a7713b1edbc | 4659 | /*! @name DOFF - TCD Signed Destination Address Offset */ |
AnnaBridge | 171:3a7713b1edbc | 4660 | #define DMA_DOFF_DOFF_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 4661 | #define DMA_DOFF_DOFF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4662 | #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4663 | |
AnnaBridge | 171:3a7713b1edbc | 4664 | /* The count of DMA_DOFF */ |
AnnaBridge | 171:3a7713b1edbc | 4665 | #define DMA_DOFF_COUNT (32U) |
AnnaBridge | 171:3a7713b1edbc | 4666 | |
AnnaBridge | 171:3a7713b1edbc | 4667 | /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ |
AnnaBridge | 171:3a7713b1edbc | 4668 | #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) |
AnnaBridge | 171:3a7713b1edbc | 4669 | #define DMA_CITER_ELINKNO_CITER_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4670 | #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4671 | #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 4672 | #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 4673 | #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4674 | |
AnnaBridge | 171:3a7713b1edbc | 4675 | /* The count of DMA_CITER_ELINKNO */ |
AnnaBridge | 171:3a7713b1edbc | 4676 | #define DMA_CITER_ELINKNO_COUNT (32U) |
AnnaBridge | 171:3a7713b1edbc | 4677 | |
AnnaBridge | 171:3a7713b1edbc | 4678 | /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ |
AnnaBridge | 171:3a7713b1edbc | 4679 | #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) |
AnnaBridge | 171:3a7713b1edbc | 4680 | #define DMA_CITER_ELINKYES_CITER_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4681 | #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4682 | #define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U) |
AnnaBridge | 171:3a7713b1edbc | 4683 | #define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 4684 | #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4685 | #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 4686 | #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 4687 | #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4688 | |
AnnaBridge | 171:3a7713b1edbc | 4689 | /* The count of DMA_CITER_ELINKYES */ |
AnnaBridge | 171:3a7713b1edbc | 4690 | #define DMA_CITER_ELINKYES_COUNT (32U) |
AnnaBridge | 171:3a7713b1edbc | 4691 | |
AnnaBridge | 171:3a7713b1edbc | 4692 | /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ |
AnnaBridge | 171:3a7713b1edbc | 4693 | #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 4694 | #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4695 | #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4696 | |
AnnaBridge | 171:3a7713b1edbc | 4697 | /* The count of DMA_DLAST_SGA */ |
AnnaBridge | 171:3a7713b1edbc | 4698 | #define DMA_DLAST_SGA_COUNT (32U) |
AnnaBridge | 171:3a7713b1edbc | 4699 | |
AnnaBridge | 171:3a7713b1edbc | 4700 | /*! @name CSR - TCD Control and Status */ |
AnnaBridge | 171:3a7713b1edbc | 4701 | #define DMA_CSR_START_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 4702 | #define DMA_CSR_START_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4703 | #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4704 | #define DMA_CSR_INTMAJOR_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 4705 | #define DMA_CSR_INTMAJOR_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 4706 | #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4707 | #define DMA_CSR_INTHALF_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 4708 | #define DMA_CSR_INTHALF_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4709 | #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4710 | #define DMA_CSR_DREQ_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 4711 | #define DMA_CSR_DREQ_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 4712 | #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4713 | #define DMA_CSR_ESG_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 4714 | #define DMA_CSR_ESG_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4715 | #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4716 | #define DMA_CSR_MAJORELINK_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 4717 | #define DMA_CSR_MAJORELINK_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 4718 | #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4719 | #define DMA_CSR_ACTIVE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4720 | #define DMA_CSR_ACTIVE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4721 | #define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4722 | #define DMA_CSR_DONE_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4723 | #define DMA_CSR_DONE_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4724 | #define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4725 | #define DMA_CSR_MAJORLINKCH_MASK (0x1F00U) |
AnnaBridge | 171:3a7713b1edbc | 4726 | #define DMA_CSR_MAJORLINKCH_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 4727 | #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4728 | #define DMA_CSR_BWC_MASK (0xC000U) |
AnnaBridge | 171:3a7713b1edbc | 4729 | #define DMA_CSR_BWC_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 4730 | #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4731 | |
AnnaBridge | 171:3a7713b1edbc | 4732 | /* The count of DMA_CSR */ |
AnnaBridge | 171:3a7713b1edbc | 4733 | #define DMA_CSR_COUNT (32U) |
AnnaBridge | 171:3a7713b1edbc | 4734 | |
AnnaBridge | 171:3a7713b1edbc | 4735 | /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ |
AnnaBridge | 171:3a7713b1edbc | 4736 | #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) |
AnnaBridge | 171:3a7713b1edbc | 4737 | #define DMA_BITER_ELINKNO_BITER_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4738 | #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4739 | #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 4740 | #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 4741 | #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4742 | |
AnnaBridge | 171:3a7713b1edbc | 4743 | /* The count of DMA_BITER_ELINKNO */ |
AnnaBridge | 171:3a7713b1edbc | 4744 | #define DMA_BITER_ELINKNO_COUNT (32U) |
AnnaBridge | 171:3a7713b1edbc | 4745 | |
AnnaBridge | 171:3a7713b1edbc | 4746 | /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ |
AnnaBridge | 171:3a7713b1edbc | 4747 | #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) |
AnnaBridge | 171:3a7713b1edbc | 4748 | #define DMA_BITER_ELINKYES_BITER_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4749 | #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4750 | #define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U) |
AnnaBridge | 171:3a7713b1edbc | 4751 | #define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 4752 | #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4753 | #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 4754 | #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 4755 | #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4756 | |
AnnaBridge | 171:3a7713b1edbc | 4757 | /* The count of DMA_BITER_ELINKYES */ |
AnnaBridge | 171:3a7713b1edbc | 4758 | #define DMA_BITER_ELINKYES_COUNT (32U) |
AnnaBridge | 171:3a7713b1edbc | 4759 | |
AnnaBridge | 171:3a7713b1edbc | 4760 | |
AnnaBridge | 171:3a7713b1edbc | 4761 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4762 | * @} |
AnnaBridge | 171:3a7713b1edbc | 4763 | */ /* end of group DMA_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 4764 | |
AnnaBridge | 171:3a7713b1edbc | 4765 | |
AnnaBridge | 171:3a7713b1edbc | 4766 | /* DMA - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 4767 | /** Peripheral DMA base address */ |
AnnaBridge | 171:3a7713b1edbc | 4768 | #define DMA_BASE (0x40008000u) |
AnnaBridge | 171:3a7713b1edbc | 4769 | /** Peripheral DMA base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 4770 | #define DMA0 ((DMA_Type *)DMA_BASE) |
AnnaBridge | 171:3a7713b1edbc | 4771 | /** Array initializer of DMA peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 4772 | #define DMA_BASE_ADDRS { DMA_BASE } |
AnnaBridge | 171:3a7713b1edbc | 4773 | /** Array initializer of DMA peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 4774 | #define DMA_BASE_PTRS { DMA0 } |
AnnaBridge | 171:3a7713b1edbc | 4775 | /** Interrupt vectors for the DMA peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 4776 | #define DMA_CHN_IRQS { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 4777 | #define DMA_ERROR_IRQS { DMA_Error_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 4778 | |
AnnaBridge | 171:3a7713b1edbc | 4779 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4780 | * @} |
AnnaBridge | 171:3a7713b1edbc | 4781 | */ /* end of group DMA_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 4782 | |
AnnaBridge | 171:3a7713b1edbc | 4783 | |
AnnaBridge | 171:3a7713b1edbc | 4784 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 4785 | -- DMAMUX Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 4786 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 4787 | |
AnnaBridge | 171:3a7713b1edbc | 4788 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4789 | * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 4790 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 4791 | */ |
AnnaBridge | 171:3a7713b1edbc | 4792 | |
AnnaBridge | 171:3a7713b1edbc | 4793 | /** DMAMUX - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 4794 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 4795 | __IO uint8_t CHCFG[32]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 4796 | } DMAMUX_Type; |
AnnaBridge | 171:3a7713b1edbc | 4797 | |
AnnaBridge | 171:3a7713b1edbc | 4798 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 4799 | -- DMAMUX Register Masks |
AnnaBridge | 171:3a7713b1edbc | 4800 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 4801 | |
AnnaBridge | 171:3a7713b1edbc | 4802 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4803 | * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks |
AnnaBridge | 171:3a7713b1edbc | 4804 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 4805 | */ |
AnnaBridge | 171:3a7713b1edbc | 4806 | |
AnnaBridge | 171:3a7713b1edbc | 4807 | /*! @name CHCFG - Channel Configuration register */ |
AnnaBridge | 171:3a7713b1edbc | 4808 | #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 4809 | #define DMAMUX_CHCFG_SOURCE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4810 | #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4811 | #define DMAMUX_CHCFG_TRIG_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4812 | #define DMAMUX_CHCFG_TRIG_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4813 | #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4814 | #define DMAMUX_CHCFG_ENBL_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4815 | #define DMAMUX_CHCFG_ENBL_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4816 | #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4817 | |
AnnaBridge | 171:3a7713b1edbc | 4818 | /* The count of DMAMUX_CHCFG */ |
AnnaBridge | 171:3a7713b1edbc | 4819 | #define DMAMUX_CHCFG_COUNT (32U) |
AnnaBridge | 171:3a7713b1edbc | 4820 | |
AnnaBridge | 171:3a7713b1edbc | 4821 | |
AnnaBridge | 171:3a7713b1edbc | 4822 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4823 | * @} |
AnnaBridge | 171:3a7713b1edbc | 4824 | */ /* end of group DMAMUX_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 4825 | |
AnnaBridge | 171:3a7713b1edbc | 4826 | |
AnnaBridge | 171:3a7713b1edbc | 4827 | /* DMAMUX - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 4828 | /** Peripheral DMAMUX base address */ |
AnnaBridge | 171:3a7713b1edbc | 4829 | #define DMAMUX_BASE (0x40021000u) |
AnnaBridge | 171:3a7713b1edbc | 4830 | /** Peripheral DMAMUX base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 4831 | #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) |
AnnaBridge | 171:3a7713b1edbc | 4832 | /** Array initializer of DMAMUX peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 4833 | #define DMAMUX_BASE_ADDRS { DMAMUX_BASE } |
AnnaBridge | 171:3a7713b1edbc | 4834 | /** Array initializer of DMAMUX peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 4835 | #define DMAMUX_BASE_PTRS { DMAMUX } |
AnnaBridge | 171:3a7713b1edbc | 4836 | |
AnnaBridge | 171:3a7713b1edbc | 4837 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4838 | * @} |
AnnaBridge | 171:3a7713b1edbc | 4839 | */ /* end of group DMAMUX_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 4840 | |
AnnaBridge | 171:3a7713b1edbc | 4841 | |
AnnaBridge | 171:3a7713b1edbc | 4842 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 4843 | -- EMVSIM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 4844 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 4845 | |
AnnaBridge | 171:3a7713b1edbc | 4846 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4847 | * @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 4848 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 4849 | */ |
AnnaBridge | 171:3a7713b1edbc | 4850 | |
AnnaBridge | 171:3a7713b1edbc | 4851 | /** EMVSIM - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 4852 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 4853 | __I uint32_t VER_ID; /**< Version ID Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 4854 | __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 4855 | __IO uint32_t CLKCFG; /**< Clock Configuration Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 4856 | __IO uint32_t DIVISOR; /**< Baud Rate Divisor Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 4857 | __IO uint32_t CTRL; /**< Control Register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 4858 | __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 4859 | __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 4860 | __IO uint32_t TX_THD; /**< Transmitter Threshold Register, offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 4861 | __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 4862 | __IO uint32_t TX_STATUS; /**< Transmitter Status Register, offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 4863 | __IO uint32_t PCSR; /**< Port Control and Status Register, offset: 0x28 */ |
AnnaBridge | 171:3a7713b1edbc | 4864 | __I uint32_t RX_BUF; /**< Receive Data Read Buffer, offset: 0x2C */ |
AnnaBridge | 171:3a7713b1edbc | 4865 | __IO uint32_t TX_BUF; /**< Transmit Data Buffer, offset: 0x30 */ |
AnnaBridge | 171:3a7713b1edbc | 4866 | __IO uint32_t TX_GETU; /**< Transmitter Guard ETU Value Register, offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 4867 | __IO uint32_t CWT_VAL; /**< Character Wait Time Value Register, offset: 0x38 */ |
AnnaBridge | 171:3a7713b1edbc | 4868 | __IO uint32_t BWT_VAL; /**< Block Wait Time Value Register, offset: 0x3C */ |
AnnaBridge | 171:3a7713b1edbc | 4869 | __IO uint32_t BGT_VAL; /**< Block Guard Time Value Register, offset: 0x40 */ |
AnnaBridge | 171:3a7713b1edbc | 4870 | __IO uint32_t GPCNT0_VAL; /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */ |
AnnaBridge | 171:3a7713b1edbc | 4871 | __IO uint32_t GPCNT1_VAL; /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */ |
AnnaBridge | 171:3a7713b1edbc | 4872 | } EMVSIM_Type; |
AnnaBridge | 171:3a7713b1edbc | 4873 | |
AnnaBridge | 171:3a7713b1edbc | 4874 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 4875 | -- EMVSIM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 4876 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 4877 | |
AnnaBridge | 171:3a7713b1edbc | 4878 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4879 | * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 4880 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 4881 | */ |
AnnaBridge | 171:3a7713b1edbc | 4882 | |
AnnaBridge | 171:3a7713b1edbc | 4883 | /*! @name VER_ID - Version ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 4884 | #define EMVSIM_VER_ID_VER_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 4885 | #define EMVSIM_VER_ID_VER_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4886 | #define EMVSIM_VER_ID_VER(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4887 | |
AnnaBridge | 171:3a7713b1edbc | 4888 | /*! @name PARAM - Parameter Register */ |
AnnaBridge | 171:3a7713b1edbc | 4889 | #define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4890 | #define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4891 | #define EMVSIM_PARAM_RX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4892 | #define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 4893 | #define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 4894 | #define EMVSIM_PARAM_TX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4895 | |
AnnaBridge | 171:3a7713b1edbc | 4896 | /*! @name CLKCFG - Clock Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 4897 | #define EMVSIM_CLKCFG_CLK_PRSC_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4898 | #define EMVSIM_CLKCFG_CLK_PRSC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4899 | #define EMVSIM_CLKCFG_CLK_PRSC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4900 | #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK (0x300U) |
AnnaBridge | 171:3a7713b1edbc | 4901 | #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 4902 | #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4903 | #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK (0xC00U) |
AnnaBridge | 171:3a7713b1edbc | 4904 | #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 4905 | #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4906 | |
AnnaBridge | 171:3a7713b1edbc | 4907 | /*! @name DIVISOR - Baud Rate Divisor Register */ |
AnnaBridge | 171:3a7713b1edbc | 4908 | #define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK (0x1FFU) |
AnnaBridge | 171:3a7713b1edbc | 4909 | #define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4910 | #define EMVSIM_DIVISOR_DIVISOR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4911 | |
AnnaBridge | 171:3a7713b1edbc | 4912 | /*! @name CTRL - Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 4913 | #define EMVSIM_CTRL_IC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 4914 | #define EMVSIM_CTRL_IC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4915 | #define EMVSIM_CTRL_IC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4916 | #define EMVSIM_CTRL_ICM_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 4917 | #define EMVSIM_CTRL_ICM_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 4918 | #define EMVSIM_CTRL_ICM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4919 | #define EMVSIM_CTRL_ANACK_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 4920 | #define EMVSIM_CTRL_ANACK_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4921 | #define EMVSIM_CTRL_ANACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4922 | #define EMVSIM_CTRL_ONACK_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 4923 | #define EMVSIM_CTRL_ONACK_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 4924 | #define EMVSIM_CTRL_ONACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4925 | #define EMVSIM_CTRL_FLSH_RX_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 4926 | #define EMVSIM_CTRL_FLSH_RX_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 4927 | #define EMVSIM_CTRL_FLSH_RX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4928 | #define EMVSIM_CTRL_FLSH_TX_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 4929 | #define EMVSIM_CTRL_FLSH_TX_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 4930 | #define EMVSIM_CTRL_FLSH_TX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4931 | #define EMVSIM_CTRL_SW_RST_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 4932 | #define EMVSIM_CTRL_SW_RST_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 4933 | #define EMVSIM_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4934 | #define EMVSIM_CTRL_KILL_CLOCKS_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 4935 | #define EMVSIM_CTRL_KILL_CLOCKS_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 4936 | #define EMVSIM_CTRL_KILL_CLOCKS(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4937 | #define EMVSIM_CTRL_DOZE_EN_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 4938 | #define EMVSIM_CTRL_DOZE_EN_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 4939 | #define EMVSIM_CTRL_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4940 | #define EMVSIM_CTRL_STOP_EN_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 4941 | #define EMVSIM_CTRL_STOP_EN_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 4942 | #define EMVSIM_CTRL_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4943 | #define EMVSIM_CTRL_RCV_EN_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 4944 | #define EMVSIM_CTRL_RCV_EN_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 4945 | #define EMVSIM_CTRL_RCV_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4946 | #define EMVSIM_CTRL_XMT_EN_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 4947 | #define EMVSIM_CTRL_XMT_EN_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 4948 | #define EMVSIM_CTRL_XMT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4949 | #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 4950 | #define EMVSIM_CTRL_RCVR_11_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 4951 | #define EMVSIM_CTRL_RCVR_11(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4952 | #define EMVSIM_CTRL_RX_DMA_EN_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 4953 | #define EMVSIM_CTRL_RX_DMA_EN_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 4954 | #define EMVSIM_CTRL_RX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4955 | #define EMVSIM_CTRL_TX_DMA_EN_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 4956 | #define EMVSIM_CTRL_TX_DMA_EN_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 4957 | #define EMVSIM_CTRL_TX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4958 | #define EMVSIM_CTRL_INV_CRC_VAL_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 4959 | #define EMVSIM_CTRL_INV_CRC_VAL_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 4960 | #define EMVSIM_CTRL_INV_CRC_VAL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4961 | #define EMVSIM_CTRL_CRC_OUT_FLIP_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 4962 | #define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 4963 | #define EMVSIM_CTRL_CRC_OUT_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4964 | #define EMVSIM_CTRL_CRC_IN_FLIP_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 4965 | #define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 4966 | #define EMVSIM_CTRL_CRC_IN_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4967 | #define EMVSIM_CTRL_CWT_EN_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 4968 | #define EMVSIM_CTRL_CWT_EN_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 4969 | #define EMVSIM_CTRL_CWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4970 | #define EMVSIM_CTRL_LRC_EN_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 4971 | #define EMVSIM_CTRL_LRC_EN_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 4972 | #define EMVSIM_CTRL_LRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4973 | #define EMVSIM_CTRL_CRC_EN_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 4974 | #define EMVSIM_CTRL_CRC_EN_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 4975 | #define EMVSIM_CTRL_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4976 | #define EMVSIM_CTRL_XMT_CRC_LRC_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 4977 | #define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 4978 | #define EMVSIM_CTRL_XMT_CRC_LRC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4979 | #define EMVSIM_CTRL_BWT_EN_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 4980 | #define EMVSIM_CTRL_BWT_EN_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 4981 | #define EMVSIM_CTRL_BWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4982 | |
AnnaBridge | 171:3a7713b1edbc | 4983 | /*! @name INT_MASK - Interrupt Mask Register */ |
AnnaBridge | 171:3a7713b1edbc | 4984 | #define EMVSIM_INT_MASK_RDT_IM_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 4985 | #define EMVSIM_INT_MASK_RDT_IM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4986 | #define EMVSIM_INT_MASK_RDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4987 | #define EMVSIM_INT_MASK_TC_IM_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 4988 | #define EMVSIM_INT_MASK_TC_IM_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 4989 | #define EMVSIM_INT_MASK_TC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4990 | #define EMVSIM_INT_MASK_RFO_IM_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 4991 | #define EMVSIM_INT_MASK_RFO_IM_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4992 | #define EMVSIM_INT_MASK_RFO_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4993 | #define EMVSIM_INT_MASK_ETC_IM_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 4994 | #define EMVSIM_INT_MASK_ETC_IM_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 4995 | #define EMVSIM_INT_MASK_ETC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4996 | #define EMVSIM_INT_MASK_TFE_IM_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 4997 | #define EMVSIM_INT_MASK_TFE_IM_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4998 | #define EMVSIM_INT_MASK_TFE_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4999 | #define EMVSIM_INT_MASK_TNACK_IM_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 5000 | #define EMVSIM_INT_MASK_TNACK_IM_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 5001 | #define EMVSIM_INT_MASK_TNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5002 | #define EMVSIM_INT_MASK_TFF_IM_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 5003 | #define EMVSIM_INT_MASK_TFF_IM_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 5004 | #define EMVSIM_INT_MASK_TFF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5005 | #define EMVSIM_INT_MASK_TDT_IM_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 5006 | #define EMVSIM_INT_MASK_TDT_IM_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 5007 | #define EMVSIM_INT_MASK_TDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5008 | #define EMVSIM_INT_MASK_GPCNT0_IM_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 5009 | #define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5010 | #define EMVSIM_INT_MASK_GPCNT0_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5011 | #define EMVSIM_INT_MASK_CWT_ERR_IM_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 5012 | #define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 5013 | #define EMVSIM_INT_MASK_CWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5014 | #define EMVSIM_INT_MASK_RNACK_IM_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 5015 | #define EMVSIM_INT_MASK_RNACK_IM_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 5016 | #define EMVSIM_INT_MASK_RNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5017 | #define EMVSIM_INT_MASK_BWT_ERR_IM_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 5018 | #define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 5019 | #define EMVSIM_INT_MASK_BWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5020 | #define EMVSIM_INT_MASK_BGT_ERR_IM_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 5021 | #define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 5022 | #define EMVSIM_INT_MASK_BGT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5023 | #define EMVSIM_INT_MASK_GPCNT1_IM_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 5024 | #define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 5025 | #define EMVSIM_INT_MASK_GPCNT1_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5026 | #define EMVSIM_INT_MASK_RX_DATA_IM_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 5027 | #define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 5028 | #define EMVSIM_INT_MASK_RX_DATA_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5029 | #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 5030 | #define EMVSIM_INT_MASK_PEF_IM_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 5031 | #define EMVSIM_INT_MASK_PEF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5032 | |
AnnaBridge | 171:3a7713b1edbc | 5033 | /*! @name RX_THD - Receiver Threshold Register */ |
AnnaBridge | 171:3a7713b1edbc | 5034 | #define EMVSIM_RX_THD_RDT_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 5035 | #define EMVSIM_RX_THD_RDT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5036 | #define EMVSIM_RX_THD_RDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5037 | #define EMVSIM_RX_THD_RNCK_THD_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 5038 | #define EMVSIM_RX_THD_RNCK_THD_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5039 | #define EMVSIM_RX_THD_RNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5040 | |
AnnaBridge | 171:3a7713b1edbc | 5041 | /*! @name TX_THD - Transmitter Threshold Register */ |
AnnaBridge | 171:3a7713b1edbc | 5042 | #define EMVSIM_TX_THD_TDT_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 5043 | #define EMVSIM_TX_THD_TDT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5044 | #define EMVSIM_TX_THD_TDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5045 | #define EMVSIM_TX_THD_TNCK_THD_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 5046 | #define EMVSIM_TX_THD_TNCK_THD_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5047 | #define EMVSIM_TX_THD_TNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5048 | |
AnnaBridge | 171:3a7713b1edbc | 5049 | /*! @name RX_STATUS - Receive Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 5050 | #define EMVSIM_RX_STATUS_RFO_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 5051 | #define EMVSIM_RX_STATUS_RFO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5052 | #define EMVSIM_RX_STATUS_RFO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5053 | #define EMVSIM_RX_STATUS_RX_DATA_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 5054 | #define EMVSIM_RX_STATUS_RX_DATA_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5055 | #define EMVSIM_RX_STATUS_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5056 | #define EMVSIM_RX_STATUS_RDTF_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 5057 | #define EMVSIM_RX_STATUS_RDTF_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 5058 | #define EMVSIM_RX_STATUS_RDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5059 | #define EMVSIM_RX_STATUS_LRC_OK_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 5060 | #define EMVSIM_RX_STATUS_LRC_OK_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 5061 | #define EMVSIM_RX_STATUS_LRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5062 | #define EMVSIM_RX_STATUS_CRC_OK_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 5063 | #define EMVSIM_RX_STATUS_CRC_OK_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 5064 | #define EMVSIM_RX_STATUS_CRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5065 | #define EMVSIM_RX_STATUS_CWT_ERR_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 5066 | #define EMVSIM_RX_STATUS_CWT_ERR_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5067 | #define EMVSIM_RX_STATUS_CWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5068 | #define EMVSIM_RX_STATUS_RTE_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 5069 | #define EMVSIM_RX_STATUS_RTE_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 5070 | #define EMVSIM_RX_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5071 | #define EMVSIM_RX_STATUS_BWT_ERR_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 5072 | #define EMVSIM_RX_STATUS_BWT_ERR_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 5073 | #define EMVSIM_RX_STATUS_BWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5074 | #define EMVSIM_RX_STATUS_BGT_ERR_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 5075 | #define EMVSIM_RX_STATUS_BGT_ERR_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 5076 | #define EMVSIM_RX_STATUS_BGT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5077 | #define EMVSIM_RX_STATUS_PEF_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 5078 | #define EMVSIM_RX_STATUS_PEF_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 5079 | #define EMVSIM_RX_STATUS_PEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5080 | #define EMVSIM_RX_STATUS_FEF_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 5081 | #define EMVSIM_RX_STATUS_FEF_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 5082 | #define EMVSIM_RX_STATUS_FEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5083 | #define EMVSIM_RX_STATUS_RX_WPTR_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 5084 | #define EMVSIM_RX_STATUS_RX_WPTR_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5085 | #define EMVSIM_RX_STATUS_RX_WPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5086 | #define EMVSIM_RX_STATUS_RX_CNT_MASK (0x1F000000U) |
AnnaBridge | 171:3a7713b1edbc | 5087 | #define EMVSIM_RX_STATUS_RX_CNT_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 5088 | #define EMVSIM_RX_STATUS_RX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5089 | |
AnnaBridge | 171:3a7713b1edbc | 5090 | /*! @name TX_STATUS - Transmitter Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 5091 | #define EMVSIM_TX_STATUS_TNTE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 5092 | #define EMVSIM_TX_STATUS_TNTE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5093 | #define EMVSIM_TX_STATUS_TNTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5094 | #define EMVSIM_TX_STATUS_TFE_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 5095 | #define EMVSIM_TX_STATUS_TFE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 5096 | #define EMVSIM_TX_STATUS_TFE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5097 | #define EMVSIM_TX_STATUS_ETCF_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 5098 | #define EMVSIM_TX_STATUS_ETCF_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5099 | #define EMVSIM_TX_STATUS_ETCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5100 | #define EMVSIM_TX_STATUS_TCF_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 5101 | #define EMVSIM_TX_STATUS_TCF_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 5102 | #define EMVSIM_TX_STATUS_TCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5103 | #define EMVSIM_TX_STATUS_TFF_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 5104 | #define EMVSIM_TX_STATUS_TFF_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 5105 | #define EMVSIM_TX_STATUS_TFF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5106 | #define EMVSIM_TX_STATUS_TDTF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 5107 | #define EMVSIM_TX_STATUS_TDTF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 5108 | #define EMVSIM_TX_STATUS_TDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5109 | #define EMVSIM_TX_STATUS_GPCNT0_TO_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 5110 | #define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5111 | #define EMVSIM_TX_STATUS_GPCNT0_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5112 | #define EMVSIM_TX_STATUS_GPCNT1_TO_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 5113 | #define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 5114 | #define EMVSIM_TX_STATUS_GPCNT1_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5115 | #define EMVSIM_TX_STATUS_TX_RPTR_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 5116 | #define EMVSIM_TX_STATUS_TX_RPTR_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5117 | #define EMVSIM_TX_STATUS_TX_RPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5118 | #define EMVSIM_TX_STATUS_TX_CNT_MASK (0x1F000000U) |
AnnaBridge | 171:3a7713b1edbc | 5119 | #define EMVSIM_TX_STATUS_TX_CNT_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 5120 | #define EMVSIM_TX_STATUS_TX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5121 | |
AnnaBridge | 171:3a7713b1edbc | 5122 | /*! @name PCSR - Port Control and Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 5123 | #define EMVSIM_PCSR_SAPD_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 5124 | #define EMVSIM_PCSR_SAPD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5125 | #define EMVSIM_PCSR_SAPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5126 | #define EMVSIM_PCSR_SVCC_EN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 5127 | #define EMVSIM_PCSR_SVCC_EN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 5128 | #define EMVSIM_PCSR_SVCC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5129 | #define EMVSIM_PCSR_VCCENP_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 5130 | #define EMVSIM_PCSR_VCCENP_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 5131 | #define EMVSIM_PCSR_VCCENP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5132 | #define EMVSIM_PCSR_SRST_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 5133 | #define EMVSIM_PCSR_SRST_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 5134 | #define EMVSIM_PCSR_SRST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5135 | #define EMVSIM_PCSR_SCEN_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 5136 | #define EMVSIM_PCSR_SCEN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5137 | #define EMVSIM_PCSR_SCEN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5138 | #define EMVSIM_PCSR_SCSP_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 5139 | #define EMVSIM_PCSR_SCSP_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 5140 | #define EMVSIM_PCSR_SCSP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5141 | #define EMVSIM_PCSR_SPD_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 5142 | #define EMVSIM_PCSR_SPD_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 5143 | #define EMVSIM_PCSR_SPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5144 | #define EMVSIM_PCSR_SPDIM_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 5145 | #define EMVSIM_PCSR_SPDIM_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 5146 | #define EMVSIM_PCSR_SPDIM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5147 | #define EMVSIM_PCSR_SPDIF_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 5148 | #define EMVSIM_PCSR_SPDIF_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 5149 | #define EMVSIM_PCSR_SPDIF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5150 | #define EMVSIM_PCSR_SPDP_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 5151 | #define EMVSIM_PCSR_SPDP_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 5152 | #define EMVSIM_PCSR_SPDP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5153 | #define EMVSIM_PCSR_SPDES_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 5154 | #define EMVSIM_PCSR_SPDES_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 5155 | #define EMVSIM_PCSR_SPDES(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5156 | |
AnnaBridge | 171:3a7713b1edbc | 5157 | /*! @name RX_BUF - Receive Data Read Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 5158 | #define EMVSIM_RX_BUF_RX_BYTE_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 5159 | #define EMVSIM_RX_BUF_RX_BYTE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5160 | #define EMVSIM_RX_BUF_RX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5161 | |
AnnaBridge | 171:3a7713b1edbc | 5162 | /*! @name TX_BUF - Transmit Data Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 5163 | #define EMVSIM_TX_BUF_TX_BYTE_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 5164 | #define EMVSIM_TX_BUF_TX_BYTE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5165 | #define EMVSIM_TX_BUF_TX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5166 | |
AnnaBridge | 171:3a7713b1edbc | 5167 | /*! @name TX_GETU - Transmitter Guard ETU Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 5168 | #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 5169 | #define EMVSIM_TX_GETU_GETU_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5170 | #define EMVSIM_TX_GETU_GETU(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5171 | |
AnnaBridge | 171:3a7713b1edbc | 5172 | /*! @name CWT_VAL - Character Wait Time Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 5173 | #define EMVSIM_CWT_VAL_CWT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5174 | #define EMVSIM_CWT_VAL_CWT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5175 | #define EMVSIM_CWT_VAL_CWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5176 | |
AnnaBridge | 171:3a7713b1edbc | 5177 | /*! @name BWT_VAL - Block Wait Time Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 5178 | #define EMVSIM_BWT_VAL_BWT_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5179 | #define EMVSIM_BWT_VAL_BWT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5180 | #define EMVSIM_BWT_VAL_BWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5181 | |
AnnaBridge | 171:3a7713b1edbc | 5182 | /*! @name BGT_VAL - Block Guard Time Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 5183 | #define EMVSIM_BGT_VAL_BGT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5184 | #define EMVSIM_BGT_VAL_BGT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5185 | #define EMVSIM_BGT_VAL_BGT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5186 | |
AnnaBridge | 171:3a7713b1edbc | 5187 | /*! @name GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 5188 | #define EMVSIM_GPCNT0_VAL_GPCNT0_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5189 | #define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5190 | #define EMVSIM_GPCNT0_VAL_GPCNT0(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5191 | |
AnnaBridge | 171:3a7713b1edbc | 5192 | /*! @name GPCNT1_VAL - General Purpose Counter 1 Timeout Value */ |
AnnaBridge | 171:3a7713b1edbc | 5193 | #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5194 | #define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5195 | #define EMVSIM_GPCNT1_VAL_GPCNT1(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5196 | |
AnnaBridge | 171:3a7713b1edbc | 5197 | |
AnnaBridge | 171:3a7713b1edbc | 5198 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5199 | * @} |
AnnaBridge | 171:3a7713b1edbc | 5200 | */ /* end of group EMVSIM_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 5201 | |
AnnaBridge | 171:3a7713b1edbc | 5202 | |
AnnaBridge | 171:3a7713b1edbc | 5203 | /* EMVSIM - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 5204 | /** Peripheral EMVSIM0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 5205 | #define EMVSIM0_BASE (0x400D4000u) |
AnnaBridge | 171:3a7713b1edbc | 5206 | /** Peripheral EMVSIM0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 5207 | #define EMVSIM0 ((EMVSIM_Type *)EMVSIM0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 5208 | /** Peripheral EMVSIM1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 5209 | #define EMVSIM1_BASE (0x400D5000u) |
AnnaBridge | 171:3a7713b1edbc | 5210 | /** Peripheral EMVSIM1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 5211 | #define EMVSIM1 ((EMVSIM_Type *)EMVSIM1_BASE) |
AnnaBridge | 171:3a7713b1edbc | 5212 | /** Array initializer of EMVSIM peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 5213 | #define EMVSIM_BASE_ADDRS { EMVSIM0_BASE, EMVSIM1_BASE } |
AnnaBridge | 171:3a7713b1edbc | 5214 | /** Array initializer of EMVSIM peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 5215 | #define EMVSIM_BASE_PTRS { EMVSIM0, EMVSIM1 } |
AnnaBridge | 171:3a7713b1edbc | 5216 | /** Interrupt vectors for the EMVSIM peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 5217 | #define EMVSIM_IRQS { EMVSIM0_IRQn, EMVSIM1_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 5218 | |
AnnaBridge | 171:3a7713b1edbc | 5219 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5220 | * @} |
AnnaBridge | 171:3a7713b1edbc | 5221 | */ /* end of group EMVSIM_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 5222 | |
AnnaBridge | 171:3a7713b1edbc | 5223 | |
AnnaBridge | 171:3a7713b1edbc | 5224 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 5225 | -- EWM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 5226 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 5227 | |
AnnaBridge | 171:3a7713b1edbc | 5228 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5229 | * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 5230 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 5231 | */ |
AnnaBridge | 171:3a7713b1edbc | 5232 | |
AnnaBridge | 171:3a7713b1edbc | 5233 | /** EWM - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 5234 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 5235 | __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 5236 | __O uint8_t SERV; /**< Service Register, offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 5237 | __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 5238 | __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ |
AnnaBridge | 171:3a7713b1edbc | 5239 | __IO uint8_t CLKCTRL; /**< Clock Control Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5240 | __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */ |
AnnaBridge | 171:3a7713b1edbc | 5241 | } EWM_Type; |
AnnaBridge | 171:3a7713b1edbc | 5242 | |
AnnaBridge | 171:3a7713b1edbc | 5243 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 5244 | -- EWM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 5245 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 5246 | |
AnnaBridge | 171:3a7713b1edbc | 5247 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5248 | * @addtogroup EWM_Register_Masks EWM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 5249 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 5250 | */ |
AnnaBridge | 171:3a7713b1edbc | 5251 | |
AnnaBridge | 171:3a7713b1edbc | 5252 | /*! @name CTRL - Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 5253 | #define EWM_CTRL_EWMEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 5254 | #define EWM_CTRL_EWMEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5255 | #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5256 | #define EWM_CTRL_ASSIN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 5257 | #define EWM_CTRL_ASSIN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 5258 | #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5259 | #define EWM_CTRL_INEN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 5260 | #define EWM_CTRL_INEN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 5261 | #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5262 | #define EWM_CTRL_INTEN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 5263 | #define EWM_CTRL_INTEN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 5264 | #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5265 | |
AnnaBridge | 171:3a7713b1edbc | 5266 | /*! @name SERV - Service Register */ |
AnnaBridge | 171:3a7713b1edbc | 5267 | #define EWM_SERV_SERVICE_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 5268 | #define EWM_SERV_SERVICE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5269 | #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5270 | |
AnnaBridge | 171:3a7713b1edbc | 5271 | /*! @name CMPL - Compare Low Register */ |
AnnaBridge | 171:3a7713b1edbc | 5272 | #define EWM_CMPL_COMPAREL_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 5273 | #define EWM_CMPL_COMPAREL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5274 | #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5275 | |
AnnaBridge | 171:3a7713b1edbc | 5276 | /*! @name CMPH - Compare High Register */ |
AnnaBridge | 171:3a7713b1edbc | 5277 | #define EWM_CMPH_COMPAREH_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 5278 | #define EWM_CMPH_COMPAREH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5279 | #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5280 | |
AnnaBridge | 171:3a7713b1edbc | 5281 | /*! @name CLKCTRL - Clock Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 5282 | #define EWM_CLKCTRL_CLKSEL_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 5283 | #define EWM_CLKCTRL_CLKSEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5284 | #define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5285 | |
AnnaBridge | 171:3a7713b1edbc | 5286 | /*! @name CLKPRESCALER - Clock Prescaler Register */ |
AnnaBridge | 171:3a7713b1edbc | 5287 | #define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 5288 | #define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5289 | #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5290 | |
AnnaBridge | 171:3a7713b1edbc | 5291 | |
AnnaBridge | 171:3a7713b1edbc | 5292 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5293 | * @} |
AnnaBridge | 171:3a7713b1edbc | 5294 | */ /* end of group EWM_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 5295 | |
AnnaBridge | 171:3a7713b1edbc | 5296 | |
AnnaBridge | 171:3a7713b1edbc | 5297 | /* EWM - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 5298 | /** Peripheral EWM base address */ |
AnnaBridge | 171:3a7713b1edbc | 5299 | #define EWM_BASE (0x40061000u) |
AnnaBridge | 171:3a7713b1edbc | 5300 | /** Peripheral EWM base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 5301 | #define EWM ((EWM_Type *)EWM_BASE) |
AnnaBridge | 171:3a7713b1edbc | 5302 | /** Array initializer of EWM peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 5303 | #define EWM_BASE_ADDRS { EWM_BASE } |
AnnaBridge | 171:3a7713b1edbc | 5304 | /** Array initializer of EWM peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 5305 | #define EWM_BASE_PTRS { EWM } |
AnnaBridge | 171:3a7713b1edbc | 5306 | /** Interrupt vectors for the EWM peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 5307 | #define EWM_IRQS { WDOG_EWM_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 5308 | |
AnnaBridge | 171:3a7713b1edbc | 5309 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5310 | * @} |
AnnaBridge | 171:3a7713b1edbc | 5311 | */ /* end of group EWM_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 5312 | |
AnnaBridge | 171:3a7713b1edbc | 5313 | |
AnnaBridge | 171:3a7713b1edbc | 5314 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 5315 | -- FB Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 5316 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 5317 | |
AnnaBridge | 171:3a7713b1edbc | 5318 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5319 | * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 5320 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 5321 | */ |
AnnaBridge | 171:3a7713b1edbc | 5322 | |
AnnaBridge | 171:3a7713b1edbc | 5323 | /** FB - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 5324 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 5325 | struct { /* offset: 0x0, array step: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 5326 | __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 5327 | __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 5328 | __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 5329 | } CS[6]; |
AnnaBridge | 171:3a7713b1edbc | 5330 | uint8_t RESERVED_0[24]; |
AnnaBridge | 171:3a7713b1edbc | 5331 | __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */ |
AnnaBridge | 171:3a7713b1edbc | 5332 | } FB_Type; |
AnnaBridge | 171:3a7713b1edbc | 5333 | |
AnnaBridge | 171:3a7713b1edbc | 5334 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 5335 | -- FB Register Masks |
AnnaBridge | 171:3a7713b1edbc | 5336 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 5337 | |
AnnaBridge | 171:3a7713b1edbc | 5338 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5339 | * @addtogroup FB_Register_Masks FB Register Masks |
AnnaBridge | 171:3a7713b1edbc | 5340 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 5341 | */ |
AnnaBridge | 171:3a7713b1edbc | 5342 | |
AnnaBridge | 171:3a7713b1edbc | 5343 | /*! @name CSAR - Chip Select Address Register */ |
AnnaBridge | 171:3a7713b1edbc | 5344 | #define FB_CSAR_BA_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 5345 | #define FB_CSAR_BA_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5346 | #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5347 | |
AnnaBridge | 171:3a7713b1edbc | 5348 | /* The count of FB_CSAR */ |
AnnaBridge | 171:3a7713b1edbc | 5349 | #define FB_CSAR_COUNT (6U) |
AnnaBridge | 171:3a7713b1edbc | 5350 | |
AnnaBridge | 171:3a7713b1edbc | 5351 | /*! @name CSMR - Chip Select Mask Register */ |
AnnaBridge | 171:3a7713b1edbc | 5352 | #define FB_CSMR_V_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 5353 | #define FB_CSMR_V_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5354 | #define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5355 | #define FB_CSMR_WP_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 5356 | #define FB_CSMR_WP_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5357 | #define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5358 | #define FB_CSMR_BAM_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 5359 | #define FB_CSMR_BAM_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5360 | #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5361 | |
AnnaBridge | 171:3a7713b1edbc | 5362 | /* The count of FB_CSMR */ |
AnnaBridge | 171:3a7713b1edbc | 5363 | #define FB_CSMR_COUNT (6U) |
AnnaBridge | 171:3a7713b1edbc | 5364 | |
AnnaBridge | 171:3a7713b1edbc | 5365 | /*! @name CSCR - Chip Select Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 5366 | #define FB_CSCR_BSTW_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 5367 | #define FB_CSCR_BSTW_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 5368 | #define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5369 | #define FB_CSCR_BSTR_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 5370 | #define FB_CSCR_BSTR_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5371 | #define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5372 | #define FB_CSCR_BEM_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 5373 | #define FB_CSCR_BEM_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 5374 | #define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5375 | #define FB_CSCR_PS_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 5376 | #define FB_CSCR_PS_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 5377 | #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5378 | #define FB_CSCR_AA_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 5379 | #define FB_CSCR_AA_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5380 | #define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5381 | #define FB_CSCR_BLS_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 5382 | #define FB_CSCR_BLS_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 5383 | #define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5384 | #define FB_CSCR_WS_MASK (0xFC00U) |
AnnaBridge | 171:3a7713b1edbc | 5385 | #define FB_CSCR_WS_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 5386 | #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5387 | #define FB_CSCR_WRAH_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 5388 | #define FB_CSCR_WRAH_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5389 | #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5390 | #define FB_CSCR_RDAH_MASK (0xC0000U) |
AnnaBridge | 171:3a7713b1edbc | 5391 | #define FB_CSCR_RDAH_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 5392 | #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5393 | #define FB_CSCR_ASET_MASK (0x300000U) |
AnnaBridge | 171:3a7713b1edbc | 5394 | #define FB_CSCR_ASET_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 5395 | #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5396 | #define FB_CSCR_EXTS_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 5397 | #define FB_CSCR_EXTS_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 5398 | #define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5399 | #define FB_CSCR_SWSEN_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 5400 | #define FB_CSCR_SWSEN_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 5401 | #define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5402 | #define FB_CSCR_SWS_MASK (0xFC000000U) |
AnnaBridge | 171:3a7713b1edbc | 5403 | #define FB_CSCR_SWS_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 5404 | #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5405 | |
AnnaBridge | 171:3a7713b1edbc | 5406 | /* The count of FB_CSCR */ |
AnnaBridge | 171:3a7713b1edbc | 5407 | #define FB_CSCR_COUNT (6U) |
AnnaBridge | 171:3a7713b1edbc | 5408 | |
AnnaBridge | 171:3a7713b1edbc | 5409 | /*! @name CSPMCR - Chip Select port Multiplexing Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 5410 | #define FB_CSPMCR_GROUP5_MASK (0xF000U) |
AnnaBridge | 171:3a7713b1edbc | 5411 | #define FB_CSPMCR_GROUP5_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 5412 | #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5413 | #define FB_CSPMCR_GROUP4_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 5414 | #define FB_CSPMCR_GROUP4_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5415 | #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5416 | #define FB_CSPMCR_GROUP3_MASK (0xF00000U) |
AnnaBridge | 171:3a7713b1edbc | 5417 | #define FB_CSPMCR_GROUP3_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 5418 | #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5419 | #define FB_CSPMCR_GROUP2_MASK (0xF000000U) |
AnnaBridge | 171:3a7713b1edbc | 5420 | #define FB_CSPMCR_GROUP2_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 5421 | #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5422 | #define FB_CSPMCR_GROUP1_MASK (0xF0000000U) |
AnnaBridge | 171:3a7713b1edbc | 5423 | #define FB_CSPMCR_GROUP1_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 5424 | #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5425 | |
AnnaBridge | 171:3a7713b1edbc | 5426 | |
AnnaBridge | 171:3a7713b1edbc | 5427 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5428 | * @} |
AnnaBridge | 171:3a7713b1edbc | 5429 | */ /* end of group FB_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 5430 | |
AnnaBridge | 171:3a7713b1edbc | 5431 | |
AnnaBridge | 171:3a7713b1edbc | 5432 | /* FB - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 5433 | /** Peripheral FB base address */ |
AnnaBridge | 171:3a7713b1edbc | 5434 | #define FB_BASE (0x4000C000u) |
AnnaBridge | 171:3a7713b1edbc | 5435 | /** Peripheral FB base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 5436 | #define FB ((FB_Type *)FB_BASE) |
AnnaBridge | 171:3a7713b1edbc | 5437 | /** Array initializer of FB peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 5438 | #define FB_BASE_ADDRS { FB_BASE } |
AnnaBridge | 171:3a7713b1edbc | 5439 | /** Array initializer of FB peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 5440 | #define FB_BASE_PTRS { FB } |
AnnaBridge | 171:3a7713b1edbc | 5441 | |
AnnaBridge | 171:3a7713b1edbc | 5442 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5443 | * @} |
AnnaBridge | 171:3a7713b1edbc | 5444 | */ /* end of group FB_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 5445 | |
AnnaBridge | 171:3a7713b1edbc | 5446 | |
AnnaBridge | 171:3a7713b1edbc | 5447 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 5448 | -- FLEXIO Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 5449 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 5450 | |
AnnaBridge | 171:3a7713b1edbc | 5451 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5452 | * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 5453 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 5454 | */ |
AnnaBridge | 171:3a7713b1edbc | 5455 | |
AnnaBridge | 171:3a7713b1edbc | 5456 | /** FLEXIO - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 5457 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 5458 | __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 5459 | __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5460 | __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 5461 | __I uint32_t PIN; /**< Pin State Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 5462 | __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 5463 | __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 5464 | __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 5465 | uint8_t RESERVED_0[4]; |
AnnaBridge | 171:3a7713b1edbc | 5466 | __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 5467 | __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 5468 | __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */ |
AnnaBridge | 171:3a7713b1edbc | 5469 | uint8_t RESERVED_1[4]; |
AnnaBridge | 171:3a7713b1edbc | 5470 | __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ |
AnnaBridge | 171:3a7713b1edbc | 5471 | uint8_t RESERVED_2[12]; |
AnnaBridge | 171:3a7713b1edbc | 5472 | __IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */ |
AnnaBridge | 171:3a7713b1edbc | 5473 | uint8_t RESERVED_3[60]; |
AnnaBridge | 171:3a7713b1edbc | 5474 | __IO uint32_t SHIFTCTL[8]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5475 | uint8_t RESERVED_4[96]; |
AnnaBridge | 171:3a7713b1edbc | 5476 | __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5477 | uint8_t RESERVED_5[224]; |
AnnaBridge | 171:3a7713b1edbc | 5478 | __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5479 | uint8_t RESERVED_6[96]; |
AnnaBridge | 171:3a7713b1edbc | 5480 | __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5481 | uint8_t RESERVED_7[96]; |
AnnaBridge | 171:3a7713b1edbc | 5482 | __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5483 | uint8_t RESERVED_8[96]; |
AnnaBridge | 171:3a7713b1edbc | 5484 | __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5485 | uint8_t RESERVED_9[96]; |
AnnaBridge | 171:3a7713b1edbc | 5486 | __IO uint32_t TIMCTL[8]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5487 | uint8_t RESERVED_10[96]; |
AnnaBridge | 171:3a7713b1edbc | 5488 | __IO uint32_t TIMCFG[8]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5489 | uint8_t RESERVED_11[96]; |
AnnaBridge | 171:3a7713b1edbc | 5490 | __IO uint32_t TIMCMP[8]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5491 | uint8_t RESERVED_12[352]; |
AnnaBridge | 171:3a7713b1edbc | 5492 | __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5493 | uint8_t RESERVED_13[96]; |
AnnaBridge | 171:3a7713b1edbc | 5494 | __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5495 | uint8_t RESERVED_14[96]; |
AnnaBridge | 171:3a7713b1edbc | 5496 | __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5497 | } FLEXIO_Type; |
AnnaBridge | 171:3a7713b1edbc | 5498 | |
AnnaBridge | 171:3a7713b1edbc | 5499 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 5500 | -- FLEXIO Register Masks |
AnnaBridge | 171:3a7713b1edbc | 5501 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 5502 | |
AnnaBridge | 171:3a7713b1edbc | 5503 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5504 | * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks |
AnnaBridge | 171:3a7713b1edbc | 5505 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 5506 | */ |
AnnaBridge | 171:3a7713b1edbc | 5507 | |
AnnaBridge | 171:3a7713b1edbc | 5508 | /*! @name VERID - Version ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 5509 | #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5510 | #define FLEXIO_VERID_FEATURE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5511 | #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5512 | #define FLEXIO_VERID_MINOR_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 5513 | #define FLEXIO_VERID_MINOR_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5514 | #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5515 | #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 5516 | #define FLEXIO_VERID_MAJOR_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 5517 | #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5518 | |
AnnaBridge | 171:3a7713b1edbc | 5519 | /*! @name PARAM - Parameter Register */ |
AnnaBridge | 171:3a7713b1edbc | 5520 | #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 5521 | #define FLEXIO_PARAM_SHIFTER_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5522 | #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5523 | #define FLEXIO_PARAM_TIMER_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 5524 | #define FLEXIO_PARAM_TIMER_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5525 | #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5526 | #define FLEXIO_PARAM_PIN_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 5527 | #define FLEXIO_PARAM_PIN_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5528 | #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5529 | #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 5530 | #define FLEXIO_PARAM_TRIGGER_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 5531 | #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5532 | |
AnnaBridge | 171:3a7713b1edbc | 5533 | /*! @name CTRL - FlexIO Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 5534 | #define FLEXIO_CTRL_FLEXEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 5535 | #define FLEXIO_CTRL_FLEXEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5536 | #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5537 | #define FLEXIO_CTRL_SWRST_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 5538 | #define FLEXIO_CTRL_SWRST_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 5539 | #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5540 | #define FLEXIO_CTRL_FASTACC_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 5541 | #define FLEXIO_CTRL_FASTACC_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 5542 | #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5543 | #define FLEXIO_CTRL_DBGE_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 5544 | #define FLEXIO_CTRL_DBGE_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 5545 | #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5546 | #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 5547 | #define FLEXIO_CTRL_DOZEN_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 5548 | #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5549 | |
AnnaBridge | 171:3a7713b1edbc | 5550 | /*! @name PIN - Pin State Register */ |
AnnaBridge | 171:3a7713b1edbc | 5551 | #define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5552 | #define FLEXIO_PIN_PDI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5553 | #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5554 | |
AnnaBridge | 171:3a7713b1edbc | 5555 | /*! @name SHIFTSTAT - Shifter Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 5556 | #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 5557 | #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5558 | #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5559 | |
AnnaBridge | 171:3a7713b1edbc | 5560 | /*! @name SHIFTERR - Shifter Error Register */ |
AnnaBridge | 171:3a7713b1edbc | 5561 | #define FLEXIO_SHIFTERR_SEF_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 5562 | #define FLEXIO_SHIFTERR_SEF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5563 | #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5564 | |
AnnaBridge | 171:3a7713b1edbc | 5565 | /*! @name TIMSTAT - Timer Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 5566 | #define FLEXIO_TIMSTAT_TSF_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 5567 | #define FLEXIO_TIMSTAT_TSF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5568 | #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5569 | |
AnnaBridge | 171:3a7713b1edbc | 5570 | /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 5571 | #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 5572 | #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5573 | #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5574 | |
AnnaBridge | 171:3a7713b1edbc | 5575 | /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 5576 | #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 5577 | #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5578 | #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5579 | |
AnnaBridge | 171:3a7713b1edbc | 5580 | /*! @name TIMIEN - Timer Interrupt Enable Register */ |
AnnaBridge | 171:3a7713b1edbc | 5581 | #define FLEXIO_TIMIEN_TEIE_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 5582 | #define FLEXIO_TIMIEN_TEIE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5583 | #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5584 | |
AnnaBridge | 171:3a7713b1edbc | 5585 | /*! @name SHIFTSDEN - Shifter Status DMA Enable */ |
AnnaBridge | 171:3a7713b1edbc | 5586 | #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 5587 | #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5588 | #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5589 | |
AnnaBridge | 171:3a7713b1edbc | 5590 | /*! @name SHIFTSTATE - Shifter State Register */ |
AnnaBridge | 171:3a7713b1edbc | 5591 | #define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 5592 | #define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5593 | #define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5594 | |
AnnaBridge | 171:3a7713b1edbc | 5595 | /*! @name SHIFTCTL - Shifter Control N Register */ |
AnnaBridge | 171:3a7713b1edbc | 5596 | #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 5597 | #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5598 | #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5599 | #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 5600 | #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 5601 | #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5602 | #define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) |
AnnaBridge | 171:3a7713b1edbc | 5603 | #define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5604 | #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5605 | #define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 5606 | #define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5607 | #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5608 | #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 5609 | #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 5610 | #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5611 | #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U) |
AnnaBridge | 171:3a7713b1edbc | 5612 | #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 5613 | #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5614 | |
AnnaBridge | 171:3a7713b1edbc | 5615 | /* The count of FLEXIO_SHIFTCTL */ |
AnnaBridge | 171:3a7713b1edbc | 5616 | #define FLEXIO_SHIFTCTL_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5617 | |
AnnaBridge | 171:3a7713b1edbc | 5618 | /*! @name SHIFTCFG - Shifter Configuration N Register */ |
AnnaBridge | 171:3a7713b1edbc | 5619 | #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 5620 | #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5621 | #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5622 | #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 5623 | #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5624 | #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5625 | #define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 5626 | #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5627 | #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5628 | #define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) |
AnnaBridge | 171:3a7713b1edbc | 5629 | #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5630 | #define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5631 | |
AnnaBridge | 171:3a7713b1edbc | 5632 | /* The count of FLEXIO_SHIFTCFG */ |
AnnaBridge | 171:3a7713b1edbc | 5633 | #define FLEXIO_SHIFTCFG_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5634 | |
AnnaBridge | 171:3a7713b1edbc | 5635 | /*! @name SHIFTBUF - Shifter Buffer N Register */ |
AnnaBridge | 171:3a7713b1edbc | 5636 | #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5637 | #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5638 | #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5639 | |
AnnaBridge | 171:3a7713b1edbc | 5640 | /* The count of FLEXIO_SHIFTBUF */ |
AnnaBridge | 171:3a7713b1edbc | 5641 | #define FLEXIO_SHIFTBUF_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5642 | |
AnnaBridge | 171:3a7713b1edbc | 5643 | /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ |
AnnaBridge | 171:3a7713b1edbc | 5644 | #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5645 | #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5646 | #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5647 | |
AnnaBridge | 171:3a7713b1edbc | 5648 | /* The count of FLEXIO_SHIFTBUFBIS */ |
AnnaBridge | 171:3a7713b1edbc | 5649 | #define FLEXIO_SHIFTBUFBIS_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5650 | |
AnnaBridge | 171:3a7713b1edbc | 5651 | /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ |
AnnaBridge | 171:3a7713b1edbc | 5652 | #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5653 | #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5654 | #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5655 | |
AnnaBridge | 171:3a7713b1edbc | 5656 | /* The count of FLEXIO_SHIFTBUFBYS */ |
AnnaBridge | 171:3a7713b1edbc | 5657 | #define FLEXIO_SHIFTBUFBYS_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5658 | |
AnnaBridge | 171:3a7713b1edbc | 5659 | /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ |
AnnaBridge | 171:3a7713b1edbc | 5660 | #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5661 | #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5662 | #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5663 | |
AnnaBridge | 171:3a7713b1edbc | 5664 | /* The count of FLEXIO_SHIFTBUFBBS */ |
AnnaBridge | 171:3a7713b1edbc | 5665 | #define FLEXIO_SHIFTBUFBBS_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5666 | |
AnnaBridge | 171:3a7713b1edbc | 5667 | /*! @name TIMCTL - Timer Control N Register */ |
AnnaBridge | 171:3a7713b1edbc | 5668 | #define FLEXIO_TIMCTL_TIMOD_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 5669 | #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5670 | #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5671 | #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 5672 | #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 5673 | #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5674 | #define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) |
AnnaBridge | 171:3a7713b1edbc | 5675 | #define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5676 | #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5677 | #define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 5678 | #define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5679 | #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5680 | #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 5681 | #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 5682 | #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5683 | #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 5684 | #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 5685 | #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5686 | #define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) |
AnnaBridge | 171:3a7713b1edbc | 5687 | #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 5688 | #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5689 | |
AnnaBridge | 171:3a7713b1edbc | 5690 | /* The count of FLEXIO_TIMCTL */ |
AnnaBridge | 171:3a7713b1edbc | 5691 | #define FLEXIO_TIMCTL_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5692 | |
AnnaBridge | 171:3a7713b1edbc | 5693 | /*! @name TIMCFG - Timer Configuration N Register */ |
AnnaBridge | 171:3a7713b1edbc | 5694 | #define FLEXIO_TIMCFG_TSTART_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 5695 | #define FLEXIO_TIMCFG_TSTART_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 5696 | #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5697 | #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 5698 | #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5699 | #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5700 | #define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) |
AnnaBridge | 171:3a7713b1edbc | 5701 | #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5702 | #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5703 | #define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) |
AnnaBridge | 171:3a7713b1edbc | 5704 | #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 5705 | #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5706 | #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) |
AnnaBridge | 171:3a7713b1edbc | 5707 | #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5708 | #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5709 | #define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U) |
AnnaBridge | 171:3a7713b1edbc | 5710 | #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 5711 | #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5712 | #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) |
AnnaBridge | 171:3a7713b1edbc | 5713 | #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 5714 | #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5715 | |
AnnaBridge | 171:3a7713b1edbc | 5716 | /* The count of FLEXIO_TIMCFG */ |
AnnaBridge | 171:3a7713b1edbc | 5717 | #define FLEXIO_TIMCFG_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5718 | |
AnnaBridge | 171:3a7713b1edbc | 5719 | /*! @name TIMCMP - Timer Compare N Register */ |
AnnaBridge | 171:3a7713b1edbc | 5720 | #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5721 | #define FLEXIO_TIMCMP_CMP_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5722 | #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5723 | |
AnnaBridge | 171:3a7713b1edbc | 5724 | /* The count of FLEXIO_TIMCMP */ |
AnnaBridge | 171:3a7713b1edbc | 5725 | #define FLEXIO_TIMCMP_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5726 | |
AnnaBridge | 171:3a7713b1edbc | 5727 | /*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */ |
AnnaBridge | 171:3a7713b1edbc | 5728 | #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5729 | #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5730 | #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5731 | |
AnnaBridge | 171:3a7713b1edbc | 5732 | /* The count of FLEXIO_SHIFTBUFNBS */ |
AnnaBridge | 171:3a7713b1edbc | 5733 | #define FLEXIO_SHIFTBUFNBS_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5734 | |
AnnaBridge | 171:3a7713b1edbc | 5735 | /*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */ |
AnnaBridge | 171:3a7713b1edbc | 5736 | #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5737 | #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5738 | #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5739 | |
AnnaBridge | 171:3a7713b1edbc | 5740 | /* The count of FLEXIO_SHIFTBUFHWS */ |
AnnaBridge | 171:3a7713b1edbc | 5741 | #define FLEXIO_SHIFTBUFHWS_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5742 | |
AnnaBridge | 171:3a7713b1edbc | 5743 | /*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */ |
AnnaBridge | 171:3a7713b1edbc | 5744 | #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5745 | #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5746 | #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5747 | |
AnnaBridge | 171:3a7713b1edbc | 5748 | /* The count of FLEXIO_SHIFTBUFNIS */ |
AnnaBridge | 171:3a7713b1edbc | 5749 | #define FLEXIO_SHIFTBUFNIS_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5750 | |
AnnaBridge | 171:3a7713b1edbc | 5751 | |
AnnaBridge | 171:3a7713b1edbc | 5752 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5753 | * @} |
AnnaBridge | 171:3a7713b1edbc | 5754 | */ /* end of group FLEXIO_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 5755 | |
AnnaBridge | 171:3a7713b1edbc | 5756 | |
AnnaBridge | 171:3a7713b1edbc | 5757 | /* FLEXIO - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 5758 | /** Peripheral FLEXIO0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 5759 | #define FLEXIO0_BASE (0x400DF000u) |
AnnaBridge | 171:3a7713b1edbc | 5760 | /** Peripheral FLEXIO0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 5761 | #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 5762 | /** Array initializer of FLEXIO peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 5763 | #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 5764 | /** Array initializer of FLEXIO peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 5765 | #define FLEXIO_BASE_PTRS { FLEXIO0 } |
AnnaBridge | 171:3a7713b1edbc | 5766 | /** Interrupt vectors for the FLEXIO peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 5767 | #define FLEXIO_IRQS { FLEXIO0_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 5768 | |
AnnaBridge | 171:3a7713b1edbc | 5769 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5770 | * @} |
AnnaBridge | 171:3a7713b1edbc | 5771 | */ /* end of group FLEXIO_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 5772 | |
AnnaBridge | 171:3a7713b1edbc | 5773 | |
AnnaBridge | 171:3a7713b1edbc | 5774 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 5775 | -- FMC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 5776 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 5777 | |
AnnaBridge | 171:3a7713b1edbc | 5778 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5779 | * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 5780 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 5781 | */ |
AnnaBridge | 171:3a7713b1edbc | 5782 | |
AnnaBridge | 171:3a7713b1edbc | 5783 | /** FMC - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 5784 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 5785 | __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 5786 | __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5787 | __I uint32_t RESERVED; /**< Reserved, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 5788 | uint8_t RESERVED_0[244]; |
AnnaBridge | 171:3a7713b1edbc | 5789 | __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5790 | __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5791 | __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5792 | __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5793 | uint8_t RESERVED_1[192]; |
AnnaBridge | 171:3a7713b1edbc | 5794 | struct { /* offset: 0x200, array step: index*0x40, index2*0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 5795 | __IO uint32_t DATA_UM; /**< Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 5796 | __IO uint32_t DATA_MU; /**< Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 5797 | __IO uint32_t DATA_ML; /**< Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 5798 | __IO uint32_t DATA_LM; /**< Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 5799 | } SET[4][4]; |
AnnaBridge | 171:3a7713b1edbc | 5800 | } FMC_Type; |
AnnaBridge | 171:3a7713b1edbc | 5801 | |
AnnaBridge | 171:3a7713b1edbc | 5802 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 5803 | -- FMC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 5804 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 5805 | |
AnnaBridge | 171:3a7713b1edbc | 5806 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5807 | * @addtogroup FMC_Register_Masks FMC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 5808 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 5809 | */ |
AnnaBridge | 171:3a7713b1edbc | 5810 | |
AnnaBridge | 171:3a7713b1edbc | 5811 | /*! @name PFAPR - Flash Access Protection Register */ |
AnnaBridge | 171:3a7713b1edbc | 5812 | #define FMC_PFAPR_M0AP_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 5813 | #define FMC_PFAPR_M0AP_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5814 | #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5815 | #define FMC_PFAPR_M1AP_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 5816 | #define FMC_PFAPR_M1AP_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 5817 | #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5818 | #define FMC_PFAPR_M2AP_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 5819 | #define FMC_PFAPR_M2AP_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5820 | #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5821 | #define FMC_PFAPR_M3AP_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 5822 | #define FMC_PFAPR_M3AP_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 5823 | #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5824 | #define FMC_PFAPR_M4AP_MASK (0x300U) |
AnnaBridge | 171:3a7713b1edbc | 5825 | #define FMC_PFAPR_M4AP_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5826 | #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5827 | #define FMC_PFAPR_M0PFD_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 5828 | #define FMC_PFAPR_M0PFD_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5829 | #define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5830 | #define FMC_PFAPR_M1PFD_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 5831 | #define FMC_PFAPR_M1PFD_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 5832 | #define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5833 | #define FMC_PFAPR_M2PFD_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 5834 | #define FMC_PFAPR_M2PFD_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 5835 | #define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5836 | #define FMC_PFAPR_M3PFD_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 5837 | #define FMC_PFAPR_M3PFD_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 5838 | #define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5839 | #define FMC_PFAPR_M4PFD_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 5840 | #define FMC_PFAPR_M4PFD_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 5841 | #define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5842 | |
AnnaBridge | 171:3a7713b1edbc | 5843 | /*! @name PFB0CR - Flash Bank 0 Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 5844 | #define FMC_PFB0CR_B0SEBE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 5845 | #define FMC_PFB0CR_B0SEBE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5846 | #define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5847 | #define FMC_PFB0CR_B0IPE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 5848 | #define FMC_PFB0CR_B0IPE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 5849 | #define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5850 | #define FMC_PFB0CR_B0DPE_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 5851 | #define FMC_PFB0CR_B0DPE_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 5852 | #define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5853 | #define FMC_PFB0CR_B0ICE_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 5854 | #define FMC_PFB0CR_B0ICE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 5855 | #define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5856 | #define FMC_PFB0CR_B0DCE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 5857 | #define FMC_PFB0CR_B0DCE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5858 | #define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5859 | #define FMC_PFB0CR_CRC_MASK (0xE0U) |
AnnaBridge | 171:3a7713b1edbc | 5860 | #define FMC_PFB0CR_CRC_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 5861 | #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5862 | #define FMC_PFB0CR_B0MW_MASK (0x60000U) |
AnnaBridge | 171:3a7713b1edbc | 5863 | #define FMC_PFB0CR_B0MW_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 5864 | #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5865 | #define FMC_PFB0CR_S_B_INV_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 5866 | #define FMC_PFB0CR_S_B_INV_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 5867 | #define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5868 | #define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U) |
AnnaBridge | 171:3a7713b1edbc | 5869 | #define FMC_PFB0CR_CINV_WAY_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 5870 | #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5871 | #define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U) |
AnnaBridge | 171:3a7713b1edbc | 5872 | #define FMC_PFB0CR_CLCK_WAY_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 5873 | #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5874 | #define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U) |
AnnaBridge | 171:3a7713b1edbc | 5875 | #define FMC_PFB0CR_B0RWSC_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 5876 | #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5877 | |
AnnaBridge | 171:3a7713b1edbc | 5878 | /*! @name TAGVDW0S - Cache Tag Storage */ |
AnnaBridge | 171:3a7713b1edbc | 5879 | #define FMC_TAGVDW0S_valid_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 5880 | #define FMC_TAGVDW0S_valid_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5881 | #define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5882 | #define FMC_TAGVDW0S_cache_tag_MASK (0xFFFC0U) |
AnnaBridge | 171:3a7713b1edbc | 5883 | #define FMC_TAGVDW0S_cache_tag_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 5884 | #define FMC_TAGVDW0S_cache_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_cache_tag_SHIFT)) & FMC_TAGVDW0S_cache_tag_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5885 | |
AnnaBridge | 171:3a7713b1edbc | 5886 | /* The count of FMC_TAGVDW0S */ |
AnnaBridge | 171:3a7713b1edbc | 5887 | #define FMC_TAGVDW0S_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5888 | |
AnnaBridge | 171:3a7713b1edbc | 5889 | /*! @name TAGVDW1S - Cache Tag Storage */ |
AnnaBridge | 171:3a7713b1edbc | 5890 | #define FMC_TAGVDW1S_valid_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 5891 | #define FMC_TAGVDW1S_valid_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5892 | #define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5893 | #define FMC_TAGVDW1S_cache_tag_MASK (0xFFFC0U) |
AnnaBridge | 171:3a7713b1edbc | 5894 | #define FMC_TAGVDW1S_cache_tag_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 5895 | #define FMC_TAGVDW1S_cache_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_cache_tag_SHIFT)) & FMC_TAGVDW1S_cache_tag_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5896 | |
AnnaBridge | 171:3a7713b1edbc | 5897 | /* The count of FMC_TAGVDW1S */ |
AnnaBridge | 171:3a7713b1edbc | 5898 | #define FMC_TAGVDW1S_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5899 | |
AnnaBridge | 171:3a7713b1edbc | 5900 | /*! @name TAGVDW2S - Cache Tag Storage */ |
AnnaBridge | 171:3a7713b1edbc | 5901 | #define FMC_TAGVDW2S_valid_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 5902 | #define FMC_TAGVDW2S_valid_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5903 | #define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5904 | #define FMC_TAGVDW2S_cache_tag_MASK (0xFFFC0U) |
AnnaBridge | 171:3a7713b1edbc | 5905 | #define FMC_TAGVDW2S_cache_tag_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 5906 | #define FMC_TAGVDW2S_cache_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_cache_tag_SHIFT)) & FMC_TAGVDW2S_cache_tag_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5907 | |
AnnaBridge | 171:3a7713b1edbc | 5908 | /* The count of FMC_TAGVDW2S */ |
AnnaBridge | 171:3a7713b1edbc | 5909 | #define FMC_TAGVDW2S_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5910 | |
AnnaBridge | 171:3a7713b1edbc | 5911 | /*! @name TAGVDW3S - Cache Tag Storage */ |
AnnaBridge | 171:3a7713b1edbc | 5912 | #define FMC_TAGVDW3S_valid_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 5913 | #define FMC_TAGVDW3S_valid_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5914 | #define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5915 | #define FMC_TAGVDW3S_cache_tag_MASK (0xFFFC0U) |
AnnaBridge | 171:3a7713b1edbc | 5916 | #define FMC_TAGVDW3S_cache_tag_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 5917 | #define FMC_TAGVDW3S_cache_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_cache_tag_SHIFT)) & FMC_TAGVDW3S_cache_tag_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5918 | |
AnnaBridge | 171:3a7713b1edbc | 5919 | /* The count of FMC_TAGVDW3S */ |
AnnaBridge | 171:3a7713b1edbc | 5920 | #define FMC_TAGVDW3S_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5921 | |
AnnaBridge | 171:3a7713b1edbc | 5922 | /*! @name DATA_UM - Cache Data Storage (uppermost word) */ |
AnnaBridge | 171:3a7713b1edbc | 5923 | #define FMC_DATA_UM_data_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5924 | #define FMC_DATA_UM_data_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5925 | #define FMC_DATA_UM_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_UM_data_SHIFT)) & FMC_DATA_UM_data_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5926 | |
AnnaBridge | 171:3a7713b1edbc | 5927 | /* The count of FMC_DATA_UM */ |
AnnaBridge | 171:3a7713b1edbc | 5928 | #define FMC_DATA_UM_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5929 | |
AnnaBridge | 171:3a7713b1edbc | 5930 | /* The count of FMC_DATA_UM */ |
AnnaBridge | 171:3a7713b1edbc | 5931 | #define FMC_DATA_UM_COUNT2 (4U) |
AnnaBridge | 171:3a7713b1edbc | 5932 | |
AnnaBridge | 171:3a7713b1edbc | 5933 | /*! @name DATA_MU - Cache Data Storage (mid-upper word) */ |
AnnaBridge | 171:3a7713b1edbc | 5934 | #define FMC_DATA_MU_data_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5935 | #define FMC_DATA_MU_data_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5936 | #define FMC_DATA_MU_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_MU_data_SHIFT)) & FMC_DATA_MU_data_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5937 | |
AnnaBridge | 171:3a7713b1edbc | 5938 | /* The count of FMC_DATA_MU */ |
AnnaBridge | 171:3a7713b1edbc | 5939 | #define FMC_DATA_MU_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5940 | |
AnnaBridge | 171:3a7713b1edbc | 5941 | /* The count of FMC_DATA_MU */ |
AnnaBridge | 171:3a7713b1edbc | 5942 | #define FMC_DATA_MU_COUNT2 (4U) |
AnnaBridge | 171:3a7713b1edbc | 5943 | |
AnnaBridge | 171:3a7713b1edbc | 5944 | /*! @name DATA_ML - Cache Data Storage (mid-lower word) */ |
AnnaBridge | 171:3a7713b1edbc | 5945 | #define FMC_DATA_ML_data_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5946 | #define FMC_DATA_ML_data_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5947 | #define FMC_DATA_ML_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_ML_data_SHIFT)) & FMC_DATA_ML_data_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5948 | |
AnnaBridge | 171:3a7713b1edbc | 5949 | /* The count of FMC_DATA_ML */ |
AnnaBridge | 171:3a7713b1edbc | 5950 | #define FMC_DATA_ML_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5951 | |
AnnaBridge | 171:3a7713b1edbc | 5952 | /* The count of FMC_DATA_ML */ |
AnnaBridge | 171:3a7713b1edbc | 5953 | #define FMC_DATA_ML_COUNT2 (4U) |
AnnaBridge | 171:3a7713b1edbc | 5954 | |
AnnaBridge | 171:3a7713b1edbc | 5955 | /*! @name DATA_LM - Cache Data Storage (lowermost word) */ |
AnnaBridge | 171:3a7713b1edbc | 5956 | #define FMC_DATA_LM_data_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5957 | #define FMC_DATA_LM_data_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5958 | #define FMC_DATA_LM_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_LM_data_SHIFT)) & FMC_DATA_LM_data_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5959 | |
AnnaBridge | 171:3a7713b1edbc | 5960 | /* The count of FMC_DATA_LM */ |
AnnaBridge | 171:3a7713b1edbc | 5961 | #define FMC_DATA_LM_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5962 | |
AnnaBridge | 171:3a7713b1edbc | 5963 | /* The count of FMC_DATA_LM */ |
AnnaBridge | 171:3a7713b1edbc | 5964 | #define FMC_DATA_LM_COUNT2 (4U) |
AnnaBridge | 171:3a7713b1edbc | 5965 | |
AnnaBridge | 171:3a7713b1edbc | 5966 | |
AnnaBridge | 171:3a7713b1edbc | 5967 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5968 | * @} |
AnnaBridge | 171:3a7713b1edbc | 5969 | */ /* end of group FMC_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 5970 | |
AnnaBridge | 171:3a7713b1edbc | 5971 | |
AnnaBridge | 171:3a7713b1edbc | 5972 | /* FMC - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 5973 | /** Peripheral FMC base address */ |
AnnaBridge | 171:3a7713b1edbc | 5974 | #define FMC_BASE (0x4001F000u) |
AnnaBridge | 171:3a7713b1edbc | 5975 | /** Peripheral FMC base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 5976 | #define FMC ((FMC_Type *)FMC_BASE) |
AnnaBridge | 171:3a7713b1edbc | 5977 | /** Array initializer of FMC peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 5978 | #define FMC_BASE_ADDRS { FMC_BASE } |
AnnaBridge | 171:3a7713b1edbc | 5979 | /** Array initializer of FMC peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 5980 | #define FMC_BASE_PTRS { FMC } |
AnnaBridge | 171:3a7713b1edbc | 5981 | |
AnnaBridge | 171:3a7713b1edbc | 5982 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5983 | * @} |
AnnaBridge | 171:3a7713b1edbc | 5984 | */ /* end of group FMC_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 5985 | |
AnnaBridge | 171:3a7713b1edbc | 5986 | |
AnnaBridge | 171:3a7713b1edbc | 5987 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 5988 | -- FTFA Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 5989 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 5990 | |
AnnaBridge | 171:3a7713b1edbc | 5991 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5992 | * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 5993 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 5994 | */ |
AnnaBridge | 171:3a7713b1edbc | 5995 | |
AnnaBridge | 171:3a7713b1edbc | 5996 | /** FTFA - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 5997 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 5998 | __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 5999 | __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 6000 | __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 6001 | __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ |
AnnaBridge | 171:3a7713b1edbc | 6002 | __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 6003 | __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ |
AnnaBridge | 171:3a7713b1edbc | 6004 | __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ |
AnnaBridge | 171:3a7713b1edbc | 6005 | __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ |
AnnaBridge | 171:3a7713b1edbc | 6006 | __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 6007 | __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ |
AnnaBridge | 171:3a7713b1edbc | 6008 | __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ |
AnnaBridge | 171:3a7713b1edbc | 6009 | __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ |
AnnaBridge | 171:3a7713b1edbc | 6010 | __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 6011 | __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ |
AnnaBridge | 171:3a7713b1edbc | 6012 | __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ |
AnnaBridge | 171:3a7713b1edbc | 6013 | __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ |
AnnaBridge | 171:3a7713b1edbc | 6014 | __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 6015 | __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ |
AnnaBridge | 171:3a7713b1edbc | 6016 | __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ |
AnnaBridge | 171:3a7713b1edbc | 6017 | __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ |
AnnaBridge | 171:3a7713b1edbc | 6018 | uint8_t RESERVED_0[4]; |
AnnaBridge | 171:3a7713b1edbc | 6019 | __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 6020 | __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */ |
AnnaBridge | 171:3a7713b1edbc | 6021 | __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */ |
AnnaBridge | 171:3a7713b1edbc | 6022 | __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */ |
AnnaBridge | 171:3a7713b1edbc | 6023 | __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 6024 | __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */ |
AnnaBridge | 171:3a7713b1edbc | 6025 | __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */ |
AnnaBridge | 171:3a7713b1edbc | 6026 | __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */ |
AnnaBridge | 171:3a7713b1edbc | 6027 | __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 6028 | __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */ |
AnnaBridge | 171:3a7713b1edbc | 6029 | __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */ |
AnnaBridge | 171:3a7713b1edbc | 6030 | __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */ |
AnnaBridge | 171:3a7713b1edbc | 6031 | __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 6032 | __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */ |
AnnaBridge | 171:3a7713b1edbc | 6033 | __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */ |
AnnaBridge | 171:3a7713b1edbc | 6034 | __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */ |
AnnaBridge | 171:3a7713b1edbc | 6035 | __I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */ |
AnnaBridge | 171:3a7713b1edbc | 6036 | uint8_t RESERVED_1[2]; |
AnnaBridge | 171:3a7713b1edbc | 6037 | __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */ |
AnnaBridge | 171:3a7713b1edbc | 6038 | } FTFA_Type; |
AnnaBridge | 171:3a7713b1edbc | 6039 | |
AnnaBridge | 171:3a7713b1edbc | 6040 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 6041 | -- FTFA Register Masks |
AnnaBridge | 171:3a7713b1edbc | 6042 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 6043 | |
AnnaBridge | 171:3a7713b1edbc | 6044 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6045 | * @addtogroup FTFA_Register_Masks FTFA Register Masks |
AnnaBridge | 171:3a7713b1edbc | 6046 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 6047 | */ |
AnnaBridge | 171:3a7713b1edbc | 6048 | |
AnnaBridge | 171:3a7713b1edbc | 6049 | /*! @name FSTAT - Flash Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 6050 | #define FTFA_FSTAT_MGSTAT0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6051 | #define FTFA_FSTAT_MGSTAT0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6052 | #define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6053 | #define FTFA_FSTAT_FPVIOL_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 6054 | #define FTFA_FSTAT_FPVIOL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6055 | #define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6056 | #define FTFA_FSTAT_ACCERR_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6057 | #define FTFA_FSTAT_ACCERR_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6058 | #define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6059 | #define FTFA_FSTAT_RDCOLERR_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6060 | #define FTFA_FSTAT_RDCOLERR_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6061 | #define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6062 | #define FTFA_FSTAT_CCIF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6063 | #define FTFA_FSTAT_CCIF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6064 | #define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6065 | |
AnnaBridge | 171:3a7713b1edbc | 6066 | /*! @name FCNFG - Flash Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 6067 | #define FTFA_FCNFG_ERSSUSP_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 6068 | #define FTFA_FCNFG_ERSSUSP_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6069 | #define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6070 | #define FTFA_FCNFG_ERSAREQ_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6071 | #define FTFA_FCNFG_ERSAREQ_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6072 | #define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6073 | #define FTFA_FCNFG_RDCOLLIE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6074 | #define FTFA_FCNFG_RDCOLLIE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6075 | #define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6076 | #define FTFA_FCNFG_CCIE_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6077 | #define FTFA_FCNFG_CCIE_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6078 | #define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6079 | |
AnnaBridge | 171:3a7713b1edbc | 6080 | /*! @name FSEC - Flash Security Register */ |
AnnaBridge | 171:3a7713b1edbc | 6081 | #define FTFA_FSEC_SEC_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 6082 | #define FTFA_FSEC_SEC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6083 | #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6084 | #define FTFA_FSEC_FSLACC_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 6085 | #define FTFA_FSEC_FSLACC_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6086 | #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6087 | #define FTFA_FSEC_MEEN_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 6088 | #define FTFA_FSEC_MEEN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6089 | #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6090 | #define FTFA_FSEC_KEYEN_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 6091 | #define FTFA_FSEC_KEYEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6092 | #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6093 | |
AnnaBridge | 171:3a7713b1edbc | 6094 | /*! @name FOPT - Flash Option Register */ |
AnnaBridge | 171:3a7713b1edbc | 6095 | #define FTFA_FOPT_OPT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6096 | #define FTFA_FOPT_OPT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6097 | #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6098 | |
AnnaBridge | 171:3a7713b1edbc | 6099 | /*! @name FCCOB3 - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6100 | #define FTFA_FCCOB3_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6101 | #define FTFA_FCCOB3_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6102 | #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6103 | |
AnnaBridge | 171:3a7713b1edbc | 6104 | /*! @name FCCOB2 - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6105 | #define FTFA_FCCOB2_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6106 | #define FTFA_FCCOB2_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6107 | #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6108 | |
AnnaBridge | 171:3a7713b1edbc | 6109 | /*! @name FCCOB1 - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6110 | #define FTFA_FCCOB1_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6111 | #define FTFA_FCCOB1_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6112 | #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6113 | |
AnnaBridge | 171:3a7713b1edbc | 6114 | /*! @name FCCOB0 - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6115 | #define FTFA_FCCOB0_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6116 | #define FTFA_FCCOB0_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6117 | #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6118 | |
AnnaBridge | 171:3a7713b1edbc | 6119 | /*! @name FCCOB7 - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6120 | #define FTFA_FCCOB7_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6121 | #define FTFA_FCCOB7_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6122 | #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6123 | |
AnnaBridge | 171:3a7713b1edbc | 6124 | /*! @name FCCOB6 - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6125 | #define FTFA_FCCOB6_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6126 | #define FTFA_FCCOB6_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6127 | #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6128 | |
AnnaBridge | 171:3a7713b1edbc | 6129 | /*! @name FCCOB5 - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6130 | #define FTFA_FCCOB5_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6131 | #define FTFA_FCCOB5_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6132 | #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6133 | |
AnnaBridge | 171:3a7713b1edbc | 6134 | /*! @name FCCOB4 - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6135 | #define FTFA_FCCOB4_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6136 | #define FTFA_FCCOB4_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6137 | #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6138 | |
AnnaBridge | 171:3a7713b1edbc | 6139 | /*! @name FCCOBB - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6140 | #define FTFA_FCCOBB_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6141 | #define FTFA_FCCOBB_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6142 | #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6143 | |
AnnaBridge | 171:3a7713b1edbc | 6144 | /*! @name FCCOBA - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6145 | #define FTFA_FCCOBA_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6146 | #define FTFA_FCCOBA_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6147 | #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6148 | |
AnnaBridge | 171:3a7713b1edbc | 6149 | /*! @name FCCOB9 - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6150 | #define FTFA_FCCOB9_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6151 | #define FTFA_FCCOB9_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6152 | #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6153 | |
AnnaBridge | 171:3a7713b1edbc | 6154 | /*! @name FCCOB8 - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6155 | #define FTFA_FCCOB8_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6156 | #define FTFA_FCCOB8_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6157 | #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6158 | |
AnnaBridge | 171:3a7713b1edbc | 6159 | /*! @name FPROT3 - Program Flash Protection Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6160 | #define FTFA_FPROT3_PROT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6161 | #define FTFA_FPROT3_PROT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6162 | #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6163 | |
AnnaBridge | 171:3a7713b1edbc | 6164 | /*! @name FPROT2 - Program Flash Protection Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6165 | #define FTFA_FPROT2_PROT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6166 | #define FTFA_FPROT2_PROT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6167 | #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6168 | |
AnnaBridge | 171:3a7713b1edbc | 6169 | /*! @name FPROT1 - Program Flash Protection Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6170 | #define FTFA_FPROT1_PROT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6171 | #define FTFA_FPROT1_PROT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6172 | #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6173 | |
AnnaBridge | 171:3a7713b1edbc | 6174 | /*! @name FPROT0 - Program Flash Protection Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6175 | #define FTFA_FPROT0_PROT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6176 | #define FTFA_FPROT0_PROT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6177 | #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6178 | |
AnnaBridge | 171:3a7713b1edbc | 6179 | /*! @name XACCH3 - Execute-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6180 | #define FTFA_XACCH3_XA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6181 | #define FTFA_XACCH3_XA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6182 | #define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH3_XA_SHIFT)) & FTFA_XACCH3_XA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6183 | |
AnnaBridge | 171:3a7713b1edbc | 6184 | /*! @name XACCH2 - Execute-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6185 | #define FTFA_XACCH2_XA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6186 | #define FTFA_XACCH2_XA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6187 | #define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH2_XA_SHIFT)) & FTFA_XACCH2_XA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6188 | |
AnnaBridge | 171:3a7713b1edbc | 6189 | /*! @name XACCH1 - Execute-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6190 | #define FTFA_XACCH1_XA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6191 | #define FTFA_XACCH1_XA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6192 | #define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH1_XA_SHIFT)) & FTFA_XACCH1_XA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6193 | |
AnnaBridge | 171:3a7713b1edbc | 6194 | /*! @name XACCH0 - Execute-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6195 | #define FTFA_XACCH0_XA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6196 | #define FTFA_XACCH0_XA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6197 | #define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH0_XA_SHIFT)) & FTFA_XACCH0_XA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6198 | |
AnnaBridge | 171:3a7713b1edbc | 6199 | /*! @name XACCL3 - Execute-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6200 | #define FTFA_XACCL3_XA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6201 | #define FTFA_XACCL3_XA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6202 | #define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL3_XA_SHIFT)) & FTFA_XACCL3_XA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6203 | |
AnnaBridge | 171:3a7713b1edbc | 6204 | /*! @name XACCL2 - Execute-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6205 | #define FTFA_XACCL2_XA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6206 | #define FTFA_XACCL2_XA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6207 | #define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL2_XA_SHIFT)) & FTFA_XACCL2_XA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6208 | |
AnnaBridge | 171:3a7713b1edbc | 6209 | /*! @name XACCL1 - Execute-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6210 | #define FTFA_XACCL1_XA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6211 | #define FTFA_XACCL1_XA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6212 | #define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL1_XA_SHIFT)) & FTFA_XACCL1_XA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6213 | |
AnnaBridge | 171:3a7713b1edbc | 6214 | /*! @name XACCL0 - Execute-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6215 | #define FTFA_XACCL0_XA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6216 | #define FTFA_XACCL0_XA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6217 | #define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL0_XA_SHIFT)) & FTFA_XACCL0_XA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6218 | |
AnnaBridge | 171:3a7713b1edbc | 6219 | /*! @name SACCH3 - Supervisor-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6220 | #define FTFA_SACCH3_SA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6221 | #define FTFA_SACCH3_SA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6222 | #define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH3_SA_SHIFT)) & FTFA_SACCH3_SA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6223 | |
AnnaBridge | 171:3a7713b1edbc | 6224 | /*! @name SACCH2 - Supervisor-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6225 | #define FTFA_SACCH2_SA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6226 | #define FTFA_SACCH2_SA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6227 | #define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH2_SA_SHIFT)) & FTFA_SACCH2_SA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6228 | |
AnnaBridge | 171:3a7713b1edbc | 6229 | /*! @name SACCH1 - Supervisor-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6230 | #define FTFA_SACCH1_SA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6231 | #define FTFA_SACCH1_SA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6232 | #define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH1_SA_SHIFT)) & FTFA_SACCH1_SA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6233 | |
AnnaBridge | 171:3a7713b1edbc | 6234 | /*! @name SACCH0 - Supervisor-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6235 | #define FTFA_SACCH0_SA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6236 | #define FTFA_SACCH0_SA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6237 | #define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH0_SA_SHIFT)) & FTFA_SACCH0_SA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6238 | |
AnnaBridge | 171:3a7713b1edbc | 6239 | /*! @name SACCL3 - Supervisor-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6240 | #define FTFA_SACCL3_SA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6241 | #define FTFA_SACCL3_SA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6242 | #define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL3_SA_SHIFT)) & FTFA_SACCL3_SA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6243 | |
AnnaBridge | 171:3a7713b1edbc | 6244 | /*! @name SACCL2 - Supervisor-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6245 | #define FTFA_SACCL2_SA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6246 | #define FTFA_SACCL2_SA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6247 | #define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL2_SA_SHIFT)) & FTFA_SACCL2_SA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6248 | |
AnnaBridge | 171:3a7713b1edbc | 6249 | /*! @name SACCL1 - Supervisor-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6250 | #define FTFA_SACCL1_SA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6251 | #define FTFA_SACCL1_SA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6252 | #define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL1_SA_SHIFT)) & FTFA_SACCL1_SA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6253 | |
AnnaBridge | 171:3a7713b1edbc | 6254 | /*! @name SACCL0 - Supervisor-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 6255 | #define FTFA_SACCL0_SA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6256 | #define FTFA_SACCL0_SA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6257 | #define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL0_SA_SHIFT)) & FTFA_SACCL0_SA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6258 | |
AnnaBridge | 171:3a7713b1edbc | 6259 | /*! @name FACSS - Flash Access Segment Size Register */ |
AnnaBridge | 171:3a7713b1edbc | 6260 | #define FTFA_FACSS_SGSIZE_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6261 | #define FTFA_FACSS_SGSIZE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6262 | #define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSS_SGSIZE_SHIFT)) & FTFA_FACSS_SGSIZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6263 | |
AnnaBridge | 171:3a7713b1edbc | 6264 | /*! @name FACSN - Flash Access Segment Number Register */ |
AnnaBridge | 171:3a7713b1edbc | 6265 | #define FTFA_FACSN_NUMSG_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6266 | #define FTFA_FACSN_NUMSG_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6267 | #define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSN_NUMSG_SHIFT)) & FTFA_FACSN_NUMSG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6268 | |
AnnaBridge | 171:3a7713b1edbc | 6269 | |
AnnaBridge | 171:3a7713b1edbc | 6270 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6271 | * @} |
AnnaBridge | 171:3a7713b1edbc | 6272 | */ /* end of group FTFA_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 6273 | |
AnnaBridge | 171:3a7713b1edbc | 6274 | |
AnnaBridge | 171:3a7713b1edbc | 6275 | /* FTFA - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 6276 | /** Peripheral FTFA base address */ |
AnnaBridge | 171:3a7713b1edbc | 6277 | #define FTFA_BASE (0x40020000u) |
AnnaBridge | 171:3a7713b1edbc | 6278 | /** Peripheral FTFA base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 6279 | #define FTFA ((FTFA_Type *)FTFA_BASE) |
AnnaBridge | 171:3a7713b1edbc | 6280 | /** Array initializer of FTFA peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 6281 | #define FTFA_BASE_ADDRS { FTFA_BASE } |
AnnaBridge | 171:3a7713b1edbc | 6282 | /** Array initializer of FTFA peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 6283 | #define FTFA_BASE_PTRS { FTFA } |
AnnaBridge | 171:3a7713b1edbc | 6284 | /** Interrupt vectors for the FTFA peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 6285 | #define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 6286 | #define FTFA_READ_COLLISION_IRQS { Read_Collision_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 6287 | |
AnnaBridge | 171:3a7713b1edbc | 6288 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6289 | * @} |
AnnaBridge | 171:3a7713b1edbc | 6290 | */ /* end of group FTFA_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 6291 | |
AnnaBridge | 171:3a7713b1edbc | 6292 | |
AnnaBridge | 171:3a7713b1edbc | 6293 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 6294 | -- FTM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 6295 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 6296 | |
AnnaBridge | 171:3a7713b1edbc | 6297 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6298 | * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 6299 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 6300 | */ |
AnnaBridge | 171:3a7713b1edbc | 6301 | |
AnnaBridge | 171:3a7713b1edbc | 6302 | /** FTM - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 6303 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 6304 | __IO uint32_t SC; /**< Status And Control, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 6305 | __IO uint32_t CNT; /**< Counter, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 6306 | __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 6307 | struct { /* offset: 0xC, array step: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 6308 | __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 6309 | __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 6310 | } CONTROLS[8]; |
AnnaBridge | 171:3a7713b1edbc | 6311 | __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ |
AnnaBridge | 171:3a7713b1edbc | 6312 | __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */ |
AnnaBridge | 171:3a7713b1edbc | 6313 | __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ |
AnnaBridge | 171:3a7713b1edbc | 6314 | __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */ |
AnnaBridge | 171:3a7713b1edbc | 6315 | __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */ |
AnnaBridge | 171:3a7713b1edbc | 6316 | __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */ |
AnnaBridge | 171:3a7713b1edbc | 6317 | __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */ |
AnnaBridge | 171:3a7713b1edbc | 6318 | __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */ |
AnnaBridge | 171:3a7713b1edbc | 6319 | __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ |
AnnaBridge | 171:3a7713b1edbc | 6320 | __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ |
AnnaBridge | 171:3a7713b1edbc | 6321 | __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ |
AnnaBridge | 171:3a7713b1edbc | 6322 | __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ |
AnnaBridge | 171:3a7713b1edbc | 6323 | __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ |
AnnaBridge | 171:3a7713b1edbc | 6324 | __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */ |
AnnaBridge | 171:3a7713b1edbc | 6325 | __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ |
AnnaBridge | 171:3a7713b1edbc | 6326 | __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ |
AnnaBridge | 171:3a7713b1edbc | 6327 | __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ |
AnnaBridge | 171:3a7713b1edbc | 6328 | __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ |
AnnaBridge | 171:3a7713b1edbc | 6329 | __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ |
AnnaBridge | 171:3a7713b1edbc | 6330 | __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ |
AnnaBridge | 171:3a7713b1edbc | 6331 | } FTM_Type; |
AnnaBridge | 171:3a7713b1edbc | 6332 | |
AnnaBridge | 171:3a7713b1edbc | 6333 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 6334 | -- FTM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 6335 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 6336 | |
AnnaBridge | 171:3a7713b1edbc | 6337 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6338 | * @addtogroup FTM_Register_Masks FTM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 6339 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 6340 | */ |
AnnaBridge | 171:3a7713b1edbc | 6341 | |
AnnaBridge | 171:3a7713b1edbc | 6342 | /*! @name SC - Status And Control */ |
AnnaBridge | 171:3a7713b1edbc | 6343 | #define FTM_SC_PS_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 6344 | #define FTM_SC_PS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6345 | #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6346 | #define FTM_SC_CLKS_MASK (0x18U) |
AnnaBridge | 171:3a7713b1edbc | 6347 | #define FTM_SC_CLKS_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6348 | #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6349 | #define FTM_SC_CPWMS_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6350 | #define FTM_SC_CPWMS_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6351 | #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6352 | #define FTM_SC_TOIE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6353 | #define FTM_SC_TOIE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6354 | #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6355 | #define FTM_SC_TOF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6356 | #define FTM_SC_TOF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6357 | #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6358 | |
AnnaBridge | 171:3a7713b1edbc | 6359 | /*! @name CNT - Counter */ |
AnnaBridge | 171:3a7713b1edbc | 6360 | #define FTM_CNT_COUNT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6361 | #define FTM_CNT_COUNT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6362 | #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6363 | |
AnnaBridge | 171:3a7713b1edbc | 6364 | /*! @name MOD - Modulo */ |
AnnaBridge | 171:3a7713b1edbc | 6365 | #define FTM_MOD_MOD_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6366 | #define FTM_MOD_MOD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6367 | #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6368 | |
AnnaBridge | 171:3a7713b1edbc | 6369 | /*! @name CnSC - Channel (n) Status And Control */ |
AnnaBridge | 171:3a7713b1edbc | 6370 | #define FTM_CnSC_DMA_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6371 | #define FTM_CnSC_DMA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6372 | #define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6373 | #define FTM_CnSC_ICRST_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 6374 | #define FTM_CnSC_ICRST_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6375 | #define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6376 | #define FTM_CnSC_ELSA_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6377 | #define FTM_CnSC_ELSA_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6378 | #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6379 | #define FTM_CnSC_ELSB_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 6380 | #define FTM_CnSC_ELSB_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6381 | #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6382 | #define FTM_CnSC_MSA_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 6383 | #define FTM_CnSC_MSA_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6384 | #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6385 | #define FTM_CnSC_MSB_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6386 | #define FTM_CnSC_MSB_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6387 | #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6388 | #define FTM_CnSC_CHIE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6389 | #define FTM_CnSC_CHIE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6390 | #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6391 | #define FTM_CnSC_CHF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6392 | #define FTM_CnSC_CHF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6393 | #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6394 | |
AnnaBridge | 171:3a7713b1edbc | 6395 | /* The count of FTM_CnSC */ |
AnnaBridge | 171:3a7713b1edbc | 6396 | #define FTM_CnSC_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 6397 | |
AnnaBridge | 171:3a7713b1edbc | 6398 | /*! @name CnV - Channel (n) Value */ |
AnnaBridge | 171:3a7713b1edbc | 6399 | #define FTM_CnV_VAL_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6400 | #define FTM_CnV_VAL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6401 | #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6402 | |
AnnaBridge | 171:3a7713b1edbc | 6403 | /* The count of FTM_CnV */ |
AnnaBridge | 171:3a7713b1edbc | 6404 | #define FTM_CnV_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 6405 | |
AnnaBridge | 171:3a7713b1edbc | 6406 | /*! @name CNTIN - Counter Initial Value */ |
AnnaBridge | 171:3a7713b1edbc | 6407 | #define FTM_CNTIN_INIT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6408 | #define FTM_CNTIN_INIT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6409 | #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6410 | |
AnnaBridge | 171:3a7713b1edbc | 6411 | /*! @name STATUS - Capture And Compare Status */ |
AnnaBridge | 171:3a7713b1edbc | 6412 | #define FTM_STATUS_CH0F_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6413 | #define FTM_STATUS_CH0F_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6414 | #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6415 | #define FTM_STATUS_CH1F_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 6416 | #define FTM_STATUS_CH1F_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6417 | #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6418 | #define FTM_STATUS_CH2F_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6419 | #define FTM_STATUS_CH2F_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6420 | #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6421 | #define FTM_STATUS_CH3F_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 6422 | #define FTM_STATUS_CH3F_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6423 | #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6424 | #define FTM_STATUS_CH4F_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 6425 | #define FTM_STATUS_CH4F_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6426 | #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6427 | #define FTM_STATUS_CH5F_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6428 | #define FTM_STATUS_CH5F_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6429 | #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6430 | #define FTM_STATUS_CH6F_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6431 | #define FTM_STATUS_CH6F_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6432 | #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6433 | #define FTM_STATUS_CH7F_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6434 | #define FTM_STATUS_CH7F_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6435 | #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6436 | |
AnnaBridge | 171:3a7713b1edbc | 6437 | /*! @name MODE - Features Mode Selection */ |
AnnaBridge | 171:3a7713b1edbc | 6438 | #define FTM_MODE_FTMEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6439 | #define FTM_MODE_FTMEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6440 | #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6441 | #define FTM_MODE_INIT_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 6442 | #define FTM_MODE_INIT_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6443 | #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6444 | #define FTM_MODE_WPDIS_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6445 | #define FTM_MODE_WPDIS_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6446 | #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6447 | #define FTM_MODE_PWMSYNC_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 6448 | #define FTM_MODE_PWMSYNC_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6449 | #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6450 | #define FTM_MODE_CAPTEST_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 6451 | #define FTM_MODE_CAPTEST_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6452 | #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6453 | #define FTM_MODE_FAULTM_MASK (0x60U) |
AnnaBridge | 171:3a7713b1edbc | 6454 | #define FTM_MODE_FAULTM_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6455 | #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6456 | #define FTM_MODE_FAULTIE_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6457 | #define FTM_MODE_FAULTIE_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6458 | #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6459 | |
AnnaBridge | 171:3a7713b1edbc | 6460 | /*! @name SYNC - Synchronization */ |
AnnaBridge | 171:3a7713b1edbc | 6461 | #define FTM_SYNC_CNTMIN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6462 | #define FTM_SYNC_CNTMIN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6463 | #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6464 | #define FTM_SYNC_CNTMAX_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 6465 | #define FTM_SYNC_CNTMAX_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6466 | #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6467 | #define FTM_SYNC_REINIT_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6468 | #define FTM_SYNC_REINIT_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6469 | #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6470 | #define FTM_SYNC_SYNCHOM_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 6471 | #define FTM_SYNC_SYNCHOM_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6472 | #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6473 | #define FTM_SYNC_TRIG0_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 6474 | #define FTM_SYNC_TRIG0_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6475 | #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6476 | #define FTM_SYNC_TRIG1_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6477 | #define FTM_SYNC_TRIG1_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6478 | #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6479 | #define FTM_SYNC_TRIG2_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6480 | #define FTM_SYNC_TRIG2_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6481 | #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6482 | #define FTM_SYNC_SWSYNC_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6483 | #define FTM_SYNC_SWSYNC_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6484 | #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6485 | |
AnnaBridge | 171:3a7713b1edbc | 6486 | /*! @name OUTINIT - Initial State For Channels Output */ |
AnnaBridge | 171:3a7713b1edbc | 6487 | #define FTM_OUTINIT_CH0OI_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6488 | #define FTM_OUTINIT_CH0OI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6489 | #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6490 | #define FTM_OUTINIT_CH1OI_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 6491 | #define FTM_OUTINIT_CH1OI_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6492 | #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6493 | #define FTM_OUTINIT_CH2OI_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6494 | #define FTM_OUTINIT_CH2OI_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6495 | #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6496 | #define FTM_OUTINIT_CH3OI_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 6497 | #define FTM_OUTINIT_CH3OI_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6498 | #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6499 | #define FTM_OUTINIT_CH4OI_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 6500 | #define FTM_OUTINIT_CH4OI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6501 | #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6502 | #define FTM_OUTINIT_CH5OI_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6503 | #define FTM_OUTINIT_CH5OI_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6504 | #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6505 | #define FTM_OUTINIT_CH6OI_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6506 | #define FTM_OUTINIT_CH6OI_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6507 | #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6508 | #define FTM_OUTINIT_CH7OI_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6509 | #define FTM_OUTINIT_CH7OI_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6510 | #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6511 | |
AnnaBridge | 171:3a7713b1edbc | 6512 | /*! @name OUTMASK - Output Mask */ |
AnnaBridge | 171:3a7713b1edbc | 6513 | #define FTM_OUTMASK_CH0OM_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6514 | #define FTM_OUTMASK_CH0OM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6515 | #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6516 | #define FTM_OUTMASK_CH1OM_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 6517 | #define FTM_OUTMASK_CH1OM_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6518 | #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6519 | #define FTM_OUTMASK_CH2OM_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6520 | #define FTM_OUTMASK_CH2OM_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6521 | #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6522 | #define FTM_OUTMASK_CH3OM_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 6523 | #define FTM_OUTMASK_CH3OM_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6524 | #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6525 | #define FTM_OUTMASK_CH4OM_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 6526 | #define FTM_OUTMASK_CH4OM_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6527 | #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6528 | #define FTM_OUTMASK_CH5OM_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6529 | #define FTM_OUTMASK_CH5OM_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6530 | #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6531 | #define FTM_OUTMASK_CH6OM_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6532 | #define FTM_OUTMASK_CH6OM_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6533 | #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6534 | #define FTM_OUTMASK_CH7OM_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6535 | #define FTM_OUTMASK_CH7OM_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6536 | #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6537 | |
AnnaBridge | 171:3a7713b1edbc | 6538 | /*! @name COMBINE - Function For Linked Channels */ |
AnnaBridge | 171:3a7713b1edbc | 6539 | #define FTM_COMBINE_COMBINE0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6540 | #define FTM_COMBINE_COMBINE0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6541 | #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6542 | #define FTM_COMBINE_COMP0_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 6543 | #define FTM_COMBINE_COMP0_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6544 | #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6545 | #define FTM_COMBINE_DECAPEN0_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6546 | #define FTM_COMBINE_DECAPEN0_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6547 | #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6548 | #define FTM_COMBINE_DECAP0_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 6549 | #define FTM_COMBINE_DECAP0_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6550 | #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6551 | #define FTM_COMBINE_DTEN0_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 6552 | #define FTM_COMBINE_DTEN0_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6553 | #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6554 | #define FTM_COMBINE_SYNCEN0_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6555 | #define FTM_COMBINE_SYNCEN0_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6556 | #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6557 | #define FTM_COMBINE_FAULTEN0_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6558 | #define FTM_COMBINE_FAULTEN0_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6559 | #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6560 | #define FTM_COMBINE_COMBINE1_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 6561 | #define FTM_COMBINE_COMBINE1_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 6562 | #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6563 | #define FTM_COMBINE_COMP1_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 6564 | #define FTM_COMBINE_COMP1_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 6565 | #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6566 | #define FTM_COMBINE_DECAPEN1_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 6567 | #define FTM_COMBINE_DECAPEN1_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 6568 | #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6569 | #define FTM_COMBINE_DECAP1_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 6570 | #define FTM_COMBINE_DECAP1_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 6571 | #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6572 | #define FTM_COMBINE_DTEN1_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 6573 | #define FTM_COMBINE_DTEN1_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 6574 | #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6575 | #define FTM_COMBINE_SYNCEN1_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 6576 | #define FTM_COMBINE_SYNCEN1_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 6577 | #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6578 | #define FTM_COMBINE_FAULTEN1_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 6579 | #define FTM_COMBINE_FAULTEN1_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 6580 | #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6581 | #define FTM_COMBINE_COMBINE2_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 6582 | #define FTM_COMBINE_COMBINE2_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 6583 | #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6584 | #define FTM_COMBINE_COMP2_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 6585 | #define FTM_COMBINE_COMP2_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 6586 | #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6587 | #define FTM_COMBINE_DECAPEN2_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 6588 | #define FTM_COMBINE_DECAPEN2_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 6589 | #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6590 | #define FTM_COMBINE_DECAP2_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 6591 | #define FTM_COMBINE_DECAP2_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 6592 | #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6593 | #define FTM_COMBINE_DTEN2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 6594 | #define FTM_COMBINE_DTEN2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 6595 | #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6596 | #define FTM_COMBINE_SYNCEN2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 6597 | #define FTM_COMBINE_SYNCEN2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 6598 | #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6599 | #define FTM_COMBINE_FAULTEN2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 6600 | #define FTM_COMBINE_FAULTEN2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 6601 | #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6602 | #define FTM_COMBINE_COMBINE3_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 6603 | #define FTM_COMBINE_COMBINE3_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 6604 | #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6605 | #define FTM_COMBINE_COMP3_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 6606 | #define FTM_COMBINE_COMP3_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 6607 | #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6608 | #define FTM_COMBINE_DECAPEN3_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 6609 | #define FTM_COMBINE_DECAPEN3_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 6610 | #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6611 | #define FTM_COMBINE_DECAP3_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 6612 | #define FTM_COMBINE_DECAP3_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 6613 | #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6614 | #define FTM_COMBINE_DTEN3_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 6615 | #define FTM_COMBINE_DTEN3_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 6616 | #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6617 | #define FTM_COMBINE_SYNCEN3_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 6618 | #define FTM_COMBINE_SYNCEN3_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 6619 | #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6620 | #define FTM_COMBINE_FAULTEN3_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 6621 | #define FTM_COMBINE_FAULTEN3_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 6622 | #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6623 | |
AnnaBridge | 171:3a7713b1edbc | 6624 | /*! @name DEADTIME - Deadtime Insertion Control */ |
AnnaBridge | 171:3a7713b1edbc | 6625 | #define FTM_DEADTIME_DTVAL_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 6626 | #define FTM_DEADTIME_DTVAL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6627 | #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6628 | #define FTM_DEADTIME_DTPS_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 6629 | #define FTM_DEADTIME_DTPS_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6630 | #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6631 | |
AnnaBridge | 171:3a7713b1edbc | 6632 | /*! @name EXTTRIG - FTM External Trigger */ |
AnnaBridge | 171:3a7713b1edbc | 6633 | #define FTM_EXTTRIG_CH2TRIG_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6634 | #define FTM_EXTTRIG_CH2TRIG_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6635 | #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6636 | #define FTM_EXTTRIG_CH3TRIG_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 6637 | #define FTM_EXTTRIG_CH3TRIG_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6638 | #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6639 | #define FTM_EXTTRIG_CH4TRIG_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6640 | #define FTM_EXTTRIG_CH4TRIG_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6641 | #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6642 | #define FTM_EXTTRIG_CH5TRIG_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 6643 | #define FTM_EXTTRIG_CH5TRIG_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6644 | #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6645 | #define FTM_EXTTRIG_CH0TRIG_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 6646 | #define FTM_EXTTRIG_CH0TRIG_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6647 | #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6648 | #define FTM_EXTTRIG_CH1TRIG_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6649 | #define FTM_EXTTRIG_CH1TRIG_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6650 | #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6651 | #define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6652 | #define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6653 | #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6654 | #define FTM_EXTTRIG_TRIGF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6655 | #define FTM_EXTTRIG_TRIGF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6656 | #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6657 | |
AnnaBridge | 171:3a7713b1edbc | 6658 | /*! @name POL - Channels Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 6659 | #define FTM_POL_POL0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6660 | #define FTM_POL_POL0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6661 | #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6662 | #define FTM_POL_POL1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 6663 | #define FTM_POL_POL1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6664 | #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6665 | #define FTM_POL_POL2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6666 | #define FTM_POL_POL2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6667 | #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6668 | #define FTM_POL_POL3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 6669 | #define FTM_POL_POL3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6670 | #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6671 | #define FTM_POL_POL4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 6672 | #define FTM_POL_POL4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6673 | #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6674 | #define FTM_POL_POL5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6675 | #define FTM_POL_POL5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6676 | #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6677 | #define FTM_POL_POL6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6678 | #define FTM_POL_POL6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6679 | #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6680 | #define FTM_POL_POL7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6681 | #define FTM_POL_POL7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6682 | #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6683 | |
AnnaBridge | 171:3a7713b1edbc | 6684 | /*! @name FMS - Fault Mode Status */ |
AnnaBridge | 171:3a7713b1edbc | 6685 | #define FTM_FMS_FAULTF0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6686 | #define FTM_FMS_FAULTF0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6687 | #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6688 | #define FTM_FMS_FAULTF1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 6689 | #define FTM_FMS_FAULTF1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6690 | #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6691 | #define FTM_FMS_FAULTF2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6692 | #define FTM_FMS_FAULTF2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6693 | #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6694 | #define FTM_FMS_FAULTF3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 6695 | #define FTM_FMS_FAULTF3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6696 | #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6697 | #define FTM_FMS_FAULTIN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6698 | #define FTM_FMS_FAULTIN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6699 | #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6700 | #define FTM_FMS_WPEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6701 | #define FTM_FMS_WPEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6702 | #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6703 | #define FTM_FMS_FAULTF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6704 | #define FTM_FMS_FAULTF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6705 | #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6706 | |
AnnaBridge | 171:3a7713b1edbc | 6707 | /*! @name FILTER - Input Capture Filter Control */ |
AnnaBridge | 171:3a7713b1edbc | 6708 | #define FTM_FILTER_CH0FVAL_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 6709 | #define FTM_FILTER_CH0FVAL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6710 | #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6711 | #define FTM_FILTER_CH1FVAL_MASK (0xF0U) |
AnnaBridge | 171:3a7713b1edbc | 6712 | #define FTM_FILTER_CH1FVAL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6713 | #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6714 | #define FTM_FILTER_CH2FVAL_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 6715 | #define FTM_FILTER_CH2FVAL_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 6716 | #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6717 | #define FTM_FILTER_CH3FVAL_MASK (0xF000U) |
AnnaBridge | 171:3a7713b1edbc | 6718 | #define FTM_FILTER_CH3FVAL_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 6719 | #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6720 | |
AnnaBridge | 171:3a7713b1edbc | 6721 | /*! @name FLTCTRL - Fault Control */ |
AnnaBridge | 171:3a7713b1edbc | 6722 | #define FTM_FLTCTRL_FAULT0EN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6723 | #define FTM_FLTCTRL_FAULT0EN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6724 | #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6725 | #define FTM_FLTCTRL_FAULT1EN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 6726 | #define FTM_FLTCTRL_FAULT1EN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6727 | #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6728 | #define FTM_FLTCTRL_FAULT2EN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6729 | #define FTM_FLTCTRL_FAULT2EN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6730 | #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6731 | #define FTM_FLTCTRL_FAULT3EN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 6732 | #define FTM_FLTCTRL_FAULT3EN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6733 | #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6734 | #define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 6735 | #define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6736 | #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6737 | #define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6738 | #define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6739 | #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6740 | #define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6741 | #define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6742 | #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6743 | #define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6744 | #define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6745 | #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6746 | #define FTM_FLTCTRL_FFVAL_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 6747 | #define FTM_FLTCTRL_FFVAL_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 6748 | #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6749 | |
AnnaBridge | 171:3a7713b1edbc | 6750 | /*! @name QDCTRL - Quadrature Decoder Control And Status */ |
AnnaBridge | 171:3a7713b1edbc | 6751 | #define FTM_QDCTRL_QUADEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6752 | #define FTM_QDCTRL_QUADEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6753 | #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6754 | #define FTM_QDCTRL_TOFDIR_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 6755 | #define FTM_QDCTRL_TOFDIR_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6756 | #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6757 | #define FTM_QDCTRL_QUADIR_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6758 | #define FTM_QDCTRL_QUADIR_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6759 | #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6760 | #define FTM_QDCTRL_QUADMODE_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 6761 | #define FTM_QDCTRL_QUADMODE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6762 | #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6763 | #define FTM_QDCTRL_PHBPOL_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 6764 | #define FTM_QDCTRL_PHBPOL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6765 | #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6766 | #define FTM_QDCTRL_PHAPOL_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6767 | #define FTM_QDCTRL_PHAPOL_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6768 | #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6769 | #define FTM_QDCTRL_PHBFLTREN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6770 | #define FTM_QDCTRL_PHBFLTREN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6771 | #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6772 | #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6773 | #define FTM_QDCTRL_PHAFLTREN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6774 | #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6775 | |
AnnaBridge | 171:3a7713b1edbc | 6776 | /*! @name CONF - Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 6777 | #define FTM_CONF_NUMTOF_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 6778 | #define FTM_CONF_NUMTOF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6779 | #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6780 | #define FTM_CONF_BDMMODE_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 6781 | #define FTM_CONF_BDMMODE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6782 | #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6783 | #define FTM_CONF_GTBEEN_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 6784 | #define FTM_CONF_GTBEEN_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 6785 | #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6786 | #define FTM_CONF_GTBEOUT_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 6787 | #define FTM_CONF_GTBEOUT_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 6788 | #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6789 | |
AnnaBridge | 171:3a7713b1edbc | 6790 | /*! @name FLTPOL - FTM Fault Input Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 6791 | #define FTM_FLTPOL_FLT0POL_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6792 | #define FTM_FLTPOL_FLT0POL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6793 | #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6794 | #define FTM_FLTPOL_FLT1POL_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 6795 | #define FTM_FLTPOL_FLT1POL_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6796 | #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6797 | #define FTM_FLTPOL_FLT2POL_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6798 | #define FTM_FLTPOL_FLT2POL_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6799 | #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6800 | #define FTM_FLTPOL_FLT3POL_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 6801 | #define FTM_FLTPOL_FLT3POL_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6802 | #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6803 | |
AnnaBridge | 171:3a7713b1edbc | 6804 | /*! @name SYNCONF - Synchronization Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 6805 | #define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6806 | #define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6807 | #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6808 | #define FTM_SYNCONF_CNTINC_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6809 | #define FTM_SYNCONF_CNTINC_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6810 | #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6811 | #define FTM_SYNCONF_INVC_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 6812 | #define FTM_SYNCONF_INVC_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6813 | #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6814 | #define FTM_SYNCONF_SWOC_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6815 | #define FTM_SYNCONF_SWOC_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6816 | #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6817 | #define FTM_SYNCONF_SYNCMODE_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6818 | #define FTM_SYNCONF_SYNCMODE_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6819 | #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6820 | #define FTM_SYNCONF_SWRSTCNT_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 6821 | #define FTM_SYNCONF_SWRSTCNT_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 6822 | #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6823 | #define FTM_SYNCONF_SWWRBUF_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 6824 | #define FTM_SYNCONF_SWWRBUF_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 6825 | #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6826 | #define FTM_SYNCONF_SWOM_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 6827 | #define FTM_SYNCONF_SWOM_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 6828 | #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6829 | #define FTM_SYNCONF_SWINVC_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 6830 | #define FTM_SYNCONF_SWINVC_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 6831 | #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6832 | #define FTM_SYNCONF_SWSOC_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 6833 | #define FTM_SYNCONF_SWSOC_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 6834 | #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6835 | #define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 6836 | #define FTM_SYNCONF_HWRSTCNT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 6837 | #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6838 | #define FTM_SYNCONF_HWWRBUF_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 6839 | #define FTM_SYNCONF_HWWRBUF_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 6840 | #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6841 | #define FTM_SYNCONF_HWOM_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 6842 | #define FTM_SYNCONF_HWOM_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 6843 | #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6844 | #define FTM_SYNCONF_HWINVC_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 6845 | #define FTM_SYNCONF_HWINVC_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 6846 | #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6847 | #define FTM_SYNCONF_HWSOC_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 6848 | #define FTM_SYNCONF_HWSOC_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 6849 | #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6850 | |
AnnaBridge | 171:3a7713b1edbc | 6851 | /*! @name INVCTRL - FTM Inverting Control */ |
AnnaBridge | 171:3a7713b1edbc | 6852 | #define FTM_INVCTRL_INV0EN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6853 | #define FTM_INVCTRL_INV0EN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6854 | #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6855 | #define FTM_INVCTRL_INV1EN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 6856 | #define FTM_INVCTRL_INV1EN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6857 | #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6858 | #define FTM_INVCTRL_INV2EN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6859 | #define FTM_INVCTRL_INV2EN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6860 | #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6861 | #define FTM_INVCTRL_INV3EN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 6862 | #define FTM_INVCTRL_INV3EN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6863 | #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6864 | |
AnnaBridge | 171:3a7713b1edbc | 6865 | /*! @name SWOCTRL - FTM Software Output Control */ |
AnnaBridge | 171:3a7713b1edbc | 6866 | #define FTM_SWOCTRL_CH0OC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6867 | #define FTM_SWOCTRL_CH0OC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6868 | #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6869 | #define FTM_SWOCTRL_CH1OC_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 6870 | #define FTM_SWOCTRL_CH1OC_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6871 | #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6872 | #define FTM_SWOCTRL_CH2OC_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6873 | #define FTM_SWOCTRL_CH2OC_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6874 | #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6875 | #define FTM_SWOCTRL_CH3OC_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 6876 | #define FTM_SWOCTRL_CH3OC_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6877 | #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6878 | #define FTM_SWOCTRL_CH4OC_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 6879 | #define FTM_SWOCTRL_CH4OC_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6880 | #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6881 | #define FTM_SWOCTRL_CH5OC_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6882 | #define FTM_SWOCTRL_CH5OC_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6883 | #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6884 | #define FTM_SWOCTRL_CH6OC_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6885 | #define FTM_SWOCTRL_CH6OC_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6886 | #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6887 | #define FTM_SWOCTRL_CH7OC_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6888 | #define FTM_SWOCTRL_CH7OC_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6889 | #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6890 | #define FTM_SWOCTRL_CH0OCV_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 6891 | #define FTM_SWOCTRL_CH0OCV_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 6892 | #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6893 | #define FTM_SWOCTRL_CH1OCV_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 6894 | #define FTM_SWOCTRL_CH1OCV_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 6895 | #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6896 | #define FTM_SWOCTRL_CH2OCV_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 6897 | #define FTM_SWOCTRL_CH2OCV_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 6898 | #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6899 | #define FTM_SWOCTRL_CH3OCV_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 6900 | #define FTM_SWOCTRL_CH3OCV_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 6901 | #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6902 | #define FTM_SWOCTRL_CH4OCV_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 6903 | #define FTM_SWOCTRL_CH4OCV_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 6904 | #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6905 | #define FTM_SWOCTRL_CH5OCV_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 6906 | #define FTM_SWOCTRL_CH5OCV_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 6907 | #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6908 | #define FTM_SWOCTRL_CH6OCV_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 6909 | #define FTM_SWOCTRL_CH6OCV_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 6910 | #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6911 | #define FTM_SWOCTRL_CH7OCV_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 6912 | #define FTM_SWOCTRL_CH7OCV_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 6913 | #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6914 | |
AnnaBridge | 171:3a7713b1edbc | 6915 | /*! @name PWMLOAD - FTM PWM Load */ |
AnnaBridge | 171:3a7713b1edbc | 6916 | #define FTM_PWMLOAD_CH0SEL_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6917 | #define FTM_PWMLOAD_CH0SEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6918 | #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6919 | #define FTM_PWMLOAD_CH1SEL_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 6920 | #define FTM_PWMLOAD_CH1SEL_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6921 | #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6922 | #define FTM_PWMLOAD_CH2SEL_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6923 | #define FTM_PWMLOAD_CH2SEL_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6924 | #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6925 | #define FTM_PWMLOAD_CH3SEL_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 6926 | #define FTM_PWMLOAD_CH3SEL_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6927 | #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6928 | #define FTM_PWMLOAD_CH4SEL_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 6929 | #define FTM_PWMLOAD_CH4SEL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6930 | #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6931 | #define FTM_PWMLOAD_CH5SEL_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6932 | #define FTM_PWMLOAD_CH5SEL_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6933 | #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6934 | #define FTM_PWMLOAD_CH6SEL_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6935 | #define FTM_PWMLOAD_CH6SEL_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6936 | #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6937 | #define FTM_PWMLOAD_CH7SEL_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6938 | #define FTM_PWMLOAD_CH7SEL_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6939 | #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6940 | #define FTM_PWMLOAD_LDOK_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 6941 | #define FTM_PWMLOAD_LDOK_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 6942 | #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6943 | |
AnnaBridge | 171:3a7713b1edbc | 6944 | |
AnnaBridge | 171:3a7713b1edbc | 6945 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6946 | * @} |
AnnaBridge | 171:3a7713b1edbc | 6947 | */ /* end of group FTM_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 6948 | |
AnnaBridge | 171:3a7713b1edbc | 6949 | |
AnnaBridge | 171:3a7713b1edbc | 6950 | /* FTM - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 6951 | /** Peripheral FTM0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 6952 | #define FTM0_BASE (0x40038000u) |
AnnaBridge | 171:3a7713b1edbc | 6953 | /** Peripheral FTM0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 6954 | #define FTM0 ((FTM_Type *)FTM0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 6955 | /** Peripheral FTM1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 6956 | #define FTM1_BASE (0x40039000u) |
AnnaBridge | 171:3a7713b1edbc | 6957 | /** Peripheral FTM1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 6958 | #define FTM1 ((FTM_Type *)FTM1_BASE) |
AnnaBridge | 171:3a7713b1edbc | 6959 | /** Peripheral FTM2 base address */ |
AnnaBridge | 171:3a7713b1edbc | 6960 | #define FTM2_BASE (0x4003A000u) |
AnnaBridge | 171:3a7713b1edbc | 6961 | /** Peripheral FTM2 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 6962 | #define FTM2 ((FTM_Type *)FTM2_BASE) |
AnnaBridge | 171:3a7713b1edbc | 6963 | /** Peripheral FTM3 base address */ |
AnnaBridge | 171:3a7713b1edbc | 6964 | #define FTM3_BASE (0x400B9000u) |
AnnaBridge | 171:3a7713b1edbc | 6965 | /** Peripheral FTM3 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 6966 | #define FTM3 ((FTM_Type *)FTM3_BASE) |
AnnaBridge | 171:3a7713b1edbc | 6967 | /** Array initializer of FTM peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 6968 | #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE } |
AnnaBridge | 171:3a7713b1edbc | 6969 | /** Array initializer of FTM peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 6970 | #define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 } |
AnnaBridge | 171:3a7713b1edbc | 6971 | /** Interrupt vectors for the FTM peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 6972 | #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 6973 | |
AnnaBridge | 171:3a7713b1edbc | 6974 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6975 | * @} |
AnnaBridge | 171:3a7713b1edbc | 6976 | */ /* end of group FTM_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 6977 | |
AnnaBridge | 171:3a7713b1edbc | 6978 | |
AnnaBridge | 171:3a7713b1edbc | 6979 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 6980 | -- GPIO Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 6981 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 6982 | |
AnnaBridge | 171:3a7713b1edbc | 6983 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6984 | * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 6985 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 6986 | */ |
AnnaBridge | 171:3a7713b1edbc | 6987 | |
AnnaBridge | 171:3a7713b1edbc | 6988 | /** GPIO - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 6989 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 6990 | __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 6991 | __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 6992 | __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 6993 | __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 6994 | __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 6995 | __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 6996 | } GPIO_Type; |
AnnaBridge | 171:3a7713b1edbc | 6997 | |
AnnaBridge | 171:3a7713b1edbc | 6998 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 6999 | -- GPIO Register Masks |
AnnaBridge | 171:3a7713b1edbc | 7000 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 7001 | |
AnnaBridge | 171:3a7713b1edbc | 7002 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7003 | * @addtogroup GPIO_Register_Masks GPIO Register Masks |
AnnaBridge | 171:3a7713b1edbc | 7004 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 7005 | */ |
AnnaBridge | 171:3a7713b1edbc | 7006 | |
AnnaBridge | 171:3a7713b1edbc | 7007 | /*! @name PDOR - Port Data Output Register */ |
AnnaBridge | 171:3a7713b1edbc | 7008 | #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7009 | #define GPIO_PDOR_PDO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7010 | #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7011 | |
AnnaBridge | 171:3a7713b1edbc | 7012 | /*! @name PSOR - Port Set Output Register */ |
AnnaBridge | 171:3a7713b1edbc | 7013 | #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7014 | #define GPIO_PSOR_PTSO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7015 | #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7016 | |
AnnaBridge | 171:3a7713b1edbc | 7017 | /*! @name PCOR - Port Clear Output Register */ |
AnnaBridge | 171:3a7713b1edbc | 7018 | #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7019 | #define GPIO_PCOR_PTCO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7020 | #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7021 | |
AnnaBridge | 171:3a7713b1edbc | 7022 | /*! @name PTOR - Port Toggle Output Register */ |
AnnaBridge | 171:3a7713b1edbc | 7023 | #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7024 | #define GPIO_PTOR_PTTO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7025 | #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7026 | |
AnnaBridge | 171:3a7713b1edbc | 7027 | /*! @name PDIR - Port Data Input Register */ |
AnnaBridge | 171:3a7713b1edbc | 7028 | #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7029 | #define GPIO_PDIR_PDI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7030 | #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7031 | |
AnnaBridge | 171:3a7713b1edbc | 7032 | /*! @name PDDR - Port Data Direction Register */ |
AnnaBridge | 171:3a7713b1edbc | 7033 | #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7034 | #define GPIO_PDDR_PDD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7035 | #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7036 | |
AnnaBridge | 171:3a7713b1edbc | 7037 | |
AnnaBridge | 171:3a7713b1edbc | 7038 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7039 | * @} |
AnnaBridge | 171:3a7713b1edbc | 7040 | */ /* end of group GPIO_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 7041 | |
AnnaBridge | 171:3a7713b1edbc | 7042 | |
AnnaBridge | 171:3a7713b1edbc | 7043 | /* GPIO - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 7044 | /** Peripheral GPIOA base address */ |
AnnaBridge | 171:3a7713b1edbc | 7045 | #define GPIOA_BASE (0x400FF000u) |
AnnaBridge | 171:3a7713b1edbc | 7046 | /** Peripheral GPIOA base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 7047 | #define GPIOA ((GPIO_Type *)GPIOA_BASE) |
AnnaBridge | 171:3a7713b1edbc | 7048 | /** Peripheral GPIOB base address */ |
AnnaBridge | 171:3a7713b1edbc | 7049 | #define GPIOB_BASE (0x400FF040u) |
AnnaBridge | 171:3a7713b1edbc | 7050 | /** Peripheral GPIOB base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 7051 | #define GPIOB ((GPIO_Type *)GPIOB_BASE) |
AnnaBridge | 171:3a7713b1edbc | 7052 | /** Peripheral GPIOC base address */ |
AnnaBridge | 171:3a7713b1edbc | 7053 | #define GPIOC_BASE (0x400FF080u) |
AnnaBridge | 171:3a7713b1edbc | 7054 | /** Peripheral GPIOC base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 7055 | #define GPIOC ((GPIO_Type *)GPIOC_BASE) |
AnnaBridge | 171:3a7713b1edbc | 7056 | /** Peripheral GPIOD base address */ |
AnnaBridge | 171:3a7713b1edbc | 7057 | #define GPIOD_BASE (0x400FF0C0u) |
AnnaBridge | 171:3a7713b1edbc | 7058 | /** Peripheral GPIOD base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 7059 | #define GPIOD ((GPIO_Type *)GPIOD_BASE) |
AnnaBridge | 171:3a7713b1edbc | 7060 | /** Peripheral GPIOE base address */ |
AnnaBridge | 171:3a7713b1edbc | 7061 | #define GPIOE_BASE (0x400FF100u) |
AnnaBridge | 171:3a7713b1edbc | 7062 | /** Peripheral GPIOE base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 7063 | #define GPIOE ((GPIO_Type *)GPIOE_BASE) |
AnnaBridge | 171:3a7713b1edbc | 7064 | /** Array initializer of GPIO peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 7065 | #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE } |
AnnaBridge | 171:3a7713b1edbc | 7066 | /** Array initializer of GPIO peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 7067 | #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE } |
AnnaBridge | 171:3a7713b1edbc | 7068 | |
AnnaBridge | 171:3a7713b1edbc | 7069 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7070 | * @} |
AnnaBridge | 171:3a7713b1edbc | 7071 | */ /* end of group GPIO_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 7072 | |
AnnaBridge | 171:3a7713b1edbc | 7073 | |
AnnaBridge | 171:3a7713b1edbc | 7074 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 7075 | -- I2C Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 7076 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 7077 | |
AnnaBridge | 171:3a7713b1edbc | 7078 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7079 | * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 7080 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 7081 | */ |
AnnaBridge | 171:3a7713b1edbc | 7082 | |
AnnaBridge | 171:3a7713b1edbc | 7083 | /** I2C - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 7084 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 7085 | __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 7086 | __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 7087 | __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 7088 | __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ |
AnnaBridge | 171:3a7713b1edbc | 7089 | __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 7090 | __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ |
AnnaBridge | 171:3a7713b1edbc | 7091 | __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */ |
AnnaBridge | 171:3a7713b1edbc | 7092 | __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ |
AnnaBridge | 171:3a7713b1edbc | 7093 | __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 7094 | __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ |
AnnaBridge | 171:3a7713b1edbc | 7095 | __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ |
AnnaBridge | 171:3a7713b1edbc | 7096 | __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ |
AnnaBridge | 171:3a7713b1edbc | 7097 | __IO uint8_t S2; /**< I2C Status register 2, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 7098 | } I2C_Type; |
AnnaBridge | 171:3a7713b1edbc | 7099 | |
AnnaBridge | 171:3a7713b1edbc | 7100 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 7101 | -- I2C Register Masks |
AnnaBridge | 171:3a7713b1edbc | 7102 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 7103 | |
AnnaBridge | 171:3a7713b1edbc | 7104 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7105 | * @addtogroup I2C_Register_Masks I2C Register Masks |
AnnaBridge | 171:3a7713b1edbc | 7106 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 7107 | */ |
AnnaBridge | 171:3a7713b1edbc | 7108 | |
AnnaBridge | 171:3a7713b1edbc | 7109 | /*! @name A1 - I2C Address Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 7110 | #define I2C_A1_AD_MASK (0xFEU) |
AnnaBridge | 171:3a7713b1edbc | 7111 | #define I2C_A1_AD_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7112 | #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7113 | |
AnnaBridge | 171:3a7713b1edbc | 7114 | /*! @name F - I2C Frequency Divider register */ |
AnnaBridge | 171:3a7713b1edbc | 7115 | #define I2C_F_ICR_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 7116 | #define I2C_F_ICR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7117 | #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7118 | #define I2C_F_MULT_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 7119 | #define I2C_F_MULT_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7120 | #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7121 | |
AnnaBridge | 171:3a7713b1edbc | 7122 | /*! @name C1 - I2C Control Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 7123 | #define I2C_C1_DMAEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7124 | #define I2C_C1_DMAEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7125 | #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7126 | #define I2C_C1_WUEN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7127 | #define I2C_C1_WUEN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7128 | #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7129 | #define I2C_C1_RSTA_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 7130 | #define I2C_C1_RSTA_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7131 | #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7132 | #define I2C_C1_TXAK_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 7133 | #define I2C_C1_TXAK_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 7134 | #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7135 | #define I2C_C1_TX_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 7136 | #define I2C_C1_TX_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7137 | #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7138 | #define I2C_C1_MST_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 7139 | #define I2C_C1_MST_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 7140 | #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7141 | #define I2C_C1_IICIE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 7142 | #define I2C_C1_IICIE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7143 | #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7144 | #define I2C_C1_IICEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 7145 | #define I2C_C1_IICEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 7146 | #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7147 | |
AnnaBridge | 171:3a7713b1edbc | 7148 | /*! @name S - I2C Status register */ |
AnnaBridge | 171:3a7713b1edbc | 7149 | #define I2C_S_RXAK_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7150 | #define I2C_S_RXAK_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7151 | #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7152 | #define I2C_S_IICIF_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7153 | #define I2C_S_IICIF_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7154 | #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7155 | #define I2C_S_SRW_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 7156 | #define I2C_S_SRW_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7157 | #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7158 | #define I2C_S_RAM_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 7159 | #define I2C_S_RAM_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 7160 | #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7161 | #define I2C_S_ARBL_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 7162 | #define I2C_S_ARBL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7163 | #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7164 | #define I2C_S_BUSY_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 7165 | #define I2C_S_BUSY_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 7166 | #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7167 | #define I2C_S_IAAS_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 7168 | #define I2C_S_IAAS_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7169 | #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7170 | #define I2C_S_TCF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 7171 | #define I2C_S_TCF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 7172 | #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7173 | |
AnnaBridge | 171:3a7713b1edbc | 7174 | /*! @name D - I2C Data I/O register */ |
AnnaBridge | 171:3a7713b1edbc | 7175 | #define I2C_D_DATA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 7176 | #define I2C_D_DATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7177 | #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7178 | |
AnnaBridge | 171:3a7713b1edbc | 7179 | /*! @name C2 - I2C Control Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 7180 | #define I2C_C2_AD_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 7181 | #define I2C_C2_AD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7182 | #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7183 | #define I2C_C2_RMEN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 7184 | #define I2C_C2_RMEN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 7185 | #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7186 | #define I2C_C2_SBRC_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 7187 | #define I2C_C2_SBRC_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7188 | #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7189 | #define I2C_C2_HDRS_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 7190 | #define I2C_C2_HDRS_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 7191 | #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7192 | #define I2C_C2_ADEXT_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 7193 | #define I2C_C2_ADEXT_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7194 | #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7195 | #define I2C_C2_GCAEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 7196 | #define I2C_C2_GCAEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 7197 | #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7198 | |
AnnaBridge | 171:3a7713b1edbc | 7199 | /*! @name FLT - I2C Programmable Input Glitch Filter Register */ |
AnnaBridge | 171:3a7713b1edbc | 7200 | #define I2C_FLT_FLT_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 7201 | #define I2C_FLT_FLT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7202 | #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7203 | #define I2C_FLT_STARTF_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 7204 | #define I2C_FLT_STARTF_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7205 | #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7206 | #define I2C_FLT_SSIE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 7207 | #define I2C_FLT_SSIE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 7208 | #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7209 | #define I2C_FLT_STOPF_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 7210 | #define I2C_FLT_STOPF_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7211 | #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7212 | #define I2C_FLT_SHEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 7213 | #define I2C_FLT_SHEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 7214 | #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7215 | |
AnnaBridge | 171:3a7713b1edbc | 7216 | /*! @name RA - I2C Range Address register */ |
AnnaBridge | 171:3a7713b1edbc | 7217 | #define I2C_RA_RAD_MASK (0xFEU) |
AnnaBridge | 171:3a7713b1edbc | 7218 | #define I2C_RA_RAD_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7219 | #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7220 | |
AnnaBridge | 171:3a7713b1edbc | 7221 | /*! @name SMB - I2C SMBus Control and Status register */ |
AnnaBridge | 171:3a7713b1edbc | 7222 | #define I2C_SMB_SHTF2IE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7223 | #define I2C_SMB_SHTF2IE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7224 | #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7225 | #define I2C_SMB_SHTF2_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7226 | #define I2C_SMB_SHTF2_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7227 | #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7228 | #define I2C_SMB_SHTF1_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 7229 | #define I2C_SMB_SHTF1_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7230 | #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7231 | #define I2C_SMB_SLTF_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 7232 | #define I2C_SMB_SLTF_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 7233 | #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7234 | #define I2C_SMB_TCKSEL_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 7235 | #define I2C_SMB_TCKSEL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7236 | #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7237 | #define I2C_SMB_SIICAEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 7238 | #define I2C_SMB_SIICAEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 7239 | #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7240 | #define I2C_SMB_ALERTEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 7241 | #define I2C_SMB_ALERTEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7242 | #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7243 | #define I2C_SMB_FACK_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 7244 | #define I2C_SMB_FACK_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 7245 | #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7246 | |
AnnaBridge | 171:3a7713b1edbc | 7247 | /*! @name A2 - I2C Address Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 7248 | #define I2C_A2_SAD_MASK (0xFEU) |
AnnaBridge | 171:3a7713b1edbc | 7249 | #define I2C_A2_SAD_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7250 | #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7251 | |
AnnaBridge | 171:3a7713b1edbc | 7252 | /*! @name SLTH - I2C SCL Low Timeout Register High */ |
AnnaBridge | 171:3a7713b1edbc | 7253 | #define I2C_SLTH_SSLT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 7254 | #define I2C_SLTH_SSLT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7255 | #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7256 | |
AnnaBridge | 171:3a7713b1edbc | 7257 | /*! @name SLTL - I2C SCL Low Timeout Register Low */ |
AnnaBridge | 171:3a7713b1edbc | 7258 | #define I2C_SLTL_SSLT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 7259 | #define I2C_SLTL_SSLT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7260 | #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7261 | |
AnnaBridge | 171:3a7713b1edbc | 7262 | /*! @name S2 - I2C Status register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 7263 | #define I2C_S2_EMPTY_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7264 | #define I2C_S2_EMPTY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7265 | #define I2C_S2_EMPTY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_EMPTY_SHIFT)) & I2C_S2_EMPTY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7266 | #define I2C_S2_ERROR_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7267 | #define I2C_S2_ERROR_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7268 | #define I2C_S2_ERROR(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_ERROR_SHIFT)) & I2C_S2_ERROR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7269 | |
AnnaBridge | 171:3a7713b1edbc | 7270 | |
AnnaBridge | 171:3a7713b1edbc | 7271 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7272 | * @} |
AnnaBridge | 171:3a7713b1edbc | 7273 | */ /* end of group I2C_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 7274 | |
AnnaBridge | 171:3a7713b1edbc | 7275 | |
AnnaBridge | 171:3a7713b1edbc | 7276 | /* I2C - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 7277 | /** Peripheral I2C0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 7278 | #define I2C0_BASE (0x40066000u) |
AnnaBridge | 171:3a7713b1edbc | 7279 | /** Peripheral I2C0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 7280 | #define I2C0 ((I2C_Type *)I2C0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 7281 | /** Peripheral I2C1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 7282 | #define I2C1_BASE (0x40067000u) |
AnnaBridge | 171:3a7713b1edbc | 7283 | /** Peripheral I2C1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 7284 | #define I2C1 ((I2C_Type *)I2C1_BASE) |
AnnaBridge | 171:3a7713b1edbc | 7285 | /** Peripheral I2C2 base address */ |
AnnaBridge | 171:3a7713b1edbc | 7286 | #define I2C2_BASE (0x400E6000u) |
AnnaBridge | 171:3a7713b1edbc | 7287 | /** Peripheral I2C2 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 7288 | #define I2C2 ((I2C_Type *)I2C2_BASE) |
AnnaBridge | 171:3a7713b1edbc | 7289 | /** Peripheral I2C3 base address */ |
AnnaBridge | 171:3a7713b1edbc | 7290 | #define I2C3_BASE (0x400E7000u) |
AnnaBridge | 171:3a7713b1edbc | 7291 | /** Peripheral I2C3 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 7292 | #define I2C3 ((I2C_Type *)I2C3_BASE) |
AnnaBridge | 171:3a7713b1edbc | 7293 | /** Array initializer of I2C peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 7294 | #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE } |
AnnaBridge | 171:3a7713b1edbc | 7295 | /** Array initializer of I2C peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 7296 | #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3 } |
AnnaBridge | 171:3a7713b1edbc | 7297 | /** Interrupt vectors for the I2C peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 7298 | #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 7299 | |
AnnaBridge | 171:3a7713b1edbc | 7300 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7301 | * @} |
AnnaBridge | 171:3a7713b1edbc | 7302 | */ /* end of group I2C_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 7303 | |
AnnaBridge | 171:3a7713b1edbc | 7304 | |
AnnaBridge | 171:3a7713b1edbc | 7305 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 7306 | -- I2S Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 7307 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 7308 | |
AnnaBridge | 171:3a7713b1edbc | 7309 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7310 | * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 7311 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 7312 | */ |
AnnaBridge | 171:3a7713b1edbc | 7313 | |
AnnaBridge | 171:3a7713b1edbc | 7314 | /** I2S - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 7315 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 7316 | __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 7317 | __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 7318 | __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 7319 | __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 7320 | __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 7321 | __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 7322 | uint8_t RESERVED_0[8]; |
AnnaBridge | 171:3a7713b1edbc | 7323 | __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 7324 | uint8_t RESERVED_1[24]; |
AnnaBridge | 171:3a7713b1edbc | 7325 | __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 7326 | uint8_t RESERVED_2[24]; |
AnnaBridge | 171:3a7713b1edbc | 7327 | __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ |
AnnaBridge | 171:3a7713b1edbc | 7328 | uint8_t RESERVED_3[28]; |
AnnaBridge | 171:3a7713b1edbc | 7329 | __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ |
AnnaBridge | 171:3a7713b1edbc | 7330 | __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */ |
AnnaBridge | 171:3a7713b1edbc | 7331 | __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ |
AnnaBridge | 171:3a7713b1edbc | 7332 | __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ |
AnnaBridge | 171:3a7713b1edbc | 7333 | __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ |
AnnaBridge | 171:3a7713b1edbc | 7334 | __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ |
AnnaBridge | 171:3a7713b1edbc | 7335 | uint8_t RESERVED_4[8]; |
AnnaBridge | 171:3a7713b1edbc | 7336 | __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 7337 | uint8_t RESERVED_5[24]; |
AnnaBridge | 171:3a7713b1edbc | 7338 | __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 7339 | uint8_t RESERVED_6[24]; |
AnnaBridge | 171:3a7713b1edbc | 7340 | __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ |
AnnaBridge | 171:3a7713b1edbc | 7341 | uint8_t RESERVED_7[28]; |
AnnaBridge | 171:3a7713b1edbc | 7342 | __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */ |
AnnaBridge | 171:3a7713b1edbc | 7343 | __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */ |
AnnaBridge | 171:3a7713b1edbc | 7344 | } I2S_Type; |
AnnaBridge | 171:3a7713b1edbc | 7345 | |
AnnaBridge | 171:3a7713b1edbc | 7346 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 7347 | -- I2S Register Masks |
AnnaBridge | 171:3a7713b1edbc | 7348 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 7349 | |
AnnaBridge | 171:3a7713b1edbc | 7350 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7351 | * @addtogroup I2S_Register_Masks I2S Register Masks |
AnnaBridge | 171:3a7713b1edbc | 7352 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 7353 | */ |
AnnaBridge | 171:3a7713b1edbc | 7354 | |
AnnaBridge | 171:3a7713b1edbc | 7355 | /*! @name TCSR - SAI Transmit Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 7356 | #define I2S_TCSR_FRDE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7357 | #define I2S_TCSR_FRDE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7358 | #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7359 | #define I2S_TCSR_FWDE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7360 | #define I2S_TCSR_FWDE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7361 | #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7362 | #define I2S_TCSR_FRIE_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 7363 | #define I2S_TCSR_FRIE_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 7364 | #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7365 | #define I2S_TCSR_FWIE_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 7366 | #define I2S_TCSR_FWIE_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 7367 | #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7368 | #define I2S_TCSR_FEIE_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 7369 | #define I2S_TCSR_FEIE_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 7370 | #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7371 | #define I2S_TCSR_SEIE_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 7372 | #define I2S_TCSR_SEIE_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 7373 | #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7374 | #define I2S_TCSR_WSIE_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 7375 | #define I2S_TCSR_WSIE_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 7376 | #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7377 | #define I2S_TCSR_FRF_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 7378 | #define I2S_TCSR_FRF_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7379 | #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7380 | #define I2S_TCSR_FWF_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 7381 | #define I2S_TCSR_FWF_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 7382 | #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7383 | #define I2S_TCSR_FEF_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 7384 | #define I2S_TCSR_FEF_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 7385 | #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7386 | #define I2S_TCSR_SEF_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 7387 | #define I2S_TCSR_SEF_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 7388 | #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7389 | #define I2S_TCSR_WSF_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 7390 | #define I2S_TCSR_WSF_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 7391 | #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7392 | #define I2S_TCSR_SR_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 7393 | #define I2S_TCSR_SR_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 7394 | #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7395 | #define I2S_TCSR_FR_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 7396 | #define I2S_TCSR_FR_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 7397 | #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7398 | #define I2S_TCSR_BCE_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 7399 | #define I2S_TCSR_BCE_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 7400 | #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7401 | #define I2S_TCSR_DBGE_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 7402 | #define I2S_TCSR_DBGE_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 7403 | #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7404 | #define I2S_TCSR_STOPE_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 7405 | #define I2S_TCSR_STOPE_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 7406 | #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7407 | #define I2S_TCSR_TE_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 7408 | #define I2S_TCSR_TE_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 7409 | #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7410 | |
AnnaBridge | 171:3a7713b1edbc | 7411 | /*! @name TCR1 - SAI Transmit Configuration 1 Register */ |
AnnaBridge | 171:3a7713b1edbc | 7412 | #define I2S_TCR1_TFW_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 7413 | #define I2S_TCR1_TFW_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7414 | #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7415 | |
AnnaBridge | 171:3a7713b1edbc | 7416 | /*! @name TCR2 - SAI Transmit Configuration 2 Register */ |
AnnaBridge | 171:3a7713b1edbc | 7417 | #define I2S_TCR2_DIV_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 7418 | #define I2S_TCR2_DIV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7419 | #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7420 | #define I2S_TCR2_BCD_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 7421 | #define I2S_TCR2_BCD_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 7422 | #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7423 | #define I2S_TCR2_BCP_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 7424 | #define I2S_TCR2_BCP_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 7425 | #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7426 | #define I2S_TCR2_MSEL_MASK (0xC000000U) |
AnnaBridge | 171:3a7713b1edbc | 7427 | #define I2S_TCR2_MSEL_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 7428 | #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7429 | #define I2S_TCR2_BCI_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 7430 | #define I2S_TCR2_BCI_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 7431 | #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7432 | #define I2S_TCR2_BCS_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 7433 | #define I2S_TCR2_BCS_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 7434 | #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7435 | #define I2S_TCR2_SYNC_MASK (0xC0000000U) |
AnnaBridge | 171:3a7713b1edbc | 7436 | #define I2S_TCR2_SYNC_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 7437 | #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7438 | |
AnnaBridge | 171:3a7713b1edbc | 7439 | /*! @name TCR3 - SAI Transmit Configuration 3 Register */ |
AnnaBridge | 171:3a7713b1edbc | 7440 | #define I2S_TCR3_WDFL_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 7441 | #define I2S_TCR3_WDFL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7442 | #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7443 | #define I2S_TCR3_TCE_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 7444 | #define I2S_TCR3_TCE_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7445 | #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7446 | #define I2S_TCR3_CFR_MASK (0x3000000U) |
AnnaBridge | 171:3a7713b1edbc | 7447 | #define I2S_TCR3_CFR_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 7448 | #define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7449 | |
AnnaBridge | 171:3a7713b1edbc | 7450 | /*! @name TCR4 - SAI Transmit Configuration 4 Register */ |
AnnaBridge | 171:3a7713b1edbc | 7451 | #define I2S_TCR4_FSD_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7452 | #define I2S_TCR4_FSD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7453 | #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7454 | #define I2S_TCR4_FSP_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7455 | #define I2S_TCR4_FSP_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7456 | #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7457 | #define I2S_TCR4_ONDEM_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 7458 | #define I2S_TCR4_ONDEM_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7459 | #define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7460 | #define I2S_TCR4_FSE_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 7461 | #define I2S_TCR4_FSE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 7462 | #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7463 | #define I2S_TCR4_MF_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 7464 | #define I2S_TCR4_MF_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7465 | #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7466 | #define I2S_TCR4_SYWD_MASK (0x1F00U) |
AnnaBridge | 171:3a7713b1edbc | 7467 | #define I2S_TCR4_SYWD_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 7468 | #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7469 | #define I2S_TCR4_FRSZ_MASK (0x1F0000U) |
AnnaBridge | 171:3a7713b1edbc | 7470 | #define I2S_TCR4_FRSZ_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7471 | #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7472 | #define I2S_TCR4_FPACK_MASK (0x3000000U) |
AnnaBridge | 171:3a7713b1edbc | 7473 | #define I2S_TCR4_FPACK_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 7474 | #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7475 | #define I2S_TCR4_FCOMB_MASK (0xC000000U) |
AnnaBridge | 171:3a7713b1edbc | 7476 | #define I2S_TCR4_FCOMB_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 7477 | #define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7478 | #define I2S_TCR4_FCONT_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 7479 | #define I2S_TCR4_FCONT_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 7480 | #define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7481 | |
AnnaBridge | 171:3a7713b1edbc | 7482 | /*! @name TCR5 - SAI Transmit Configuration 5 Register */ |
AnnaBridge | 171:3a7713b1edbc | 7483 | #define I2S_TCR5_FBT_MASK (0x1F00U) |
AnnaBridge | 171:3a7713b1edbc | 7484 | #define I2S_TCR5_FBT_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 7485 | #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7486 | #define I2S_TCR5_W0W_MASK (0x1F0000U) |
AnnaBridge | 171:3a7713b1edbc | 7487 | #define I2S_TCR5_W0W_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7488 | #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7489 | #define I2S_TCR5_WNW_MASK (0x1F000000U) |
AnnaBridge | 171:3a7713b1edbc | 7490 | #define I2S_TCR5_WNW_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 7491 | #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7492 | |
AnnaBridge | 171:3a7713b1edbc | 7493 | /*! @name TDR - SAI Transmit Data Register */ |
AnnaBridge | 171:3a7713b1edbc | 7494 | #define I2S_TDR_TDR_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7495 | #define I2S_TDR_TDR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7496 | #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7497 | |
AnnaBridge | 171:3a7713b1edbc | 7498 | /* The count of I2S_TDR */ |
AnnaBridge | 171:3a7713b1edbc | 7499 | #define I2S_TDR_COUNT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7500 | |
AnnaBridge | 171:3a7713b1edbc | 7501 | /*! @name TFR - SAI Transmit FIFO Register */ |
AnnaBridge | 171:3a7713b1edbc | 7502 | #define I2S_TFR_RFP_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 7503 | #define I2S_TFR_RFP_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7504 | #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7505 | #define I2S_TFR_WFP_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 7506 | #define I2S_TFR_WFP_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7507 | #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7508 | #define I2S_TFR_WCP_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 7509 | #define I2S_TFR_WCP_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 7510 | #define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7511 | |
AnnaBridge | 171:3a7713b1edbc | 7512 | /* The count of I2S_TFR */ |
AnnaBridge | 171:3a7713b1edbc | 7513 | #define I2S_TFR_COUNT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7514 | |
AnnaBridge | 171:3a7713b1edbc | 7515 | /*! @name TMR - SAI Transmit Mask Register */ |
AnnaBridge | 171:3a7713b1edbc | 7516 | #define I2S_TMR_TWM_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7517 | #define I2S_TMR_TWM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7518 | #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7519 | |
AnnaBridge | 171:3a7713b1edbc | 7520 | /*! @name RCSR - SAI Receive Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 7521 | #define I2S_RCSR_FRDE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7522 | #define I2S_RCSR_FRDE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7523 | #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7524 | #define I2S_RCSR_FWDE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7525 | #define I2S_RCSR_FWDE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7526 | #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7527 | #define I2S_RCSR_FRIE_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 7528 | #define I2S_RCSR_FRIE_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 7529 | #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7530 | #define I2S_RCSR_FWIE_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 7531 | #define I2S_RCSR_FWIE_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 7532 | #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7533 | #define I2S_RCSR_FEIE_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 7534 | #define I2S_RCSR_FEIE_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 7535 | #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7536 | #define I2S_RCSR_SEIE_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 7537 | #define I2S_RCSR_SEIE_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 7538 | #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7539 | #define I2S_RCSR_WSIE_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 7540 | #define I2S_RCSR_WSIE_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 7541 | #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7542 | #define I2S_RCSR_FRF_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 7543 | #define I2S_RCSR_FRF_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7544 | #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7545 | #define I2S_RCSR_FWF_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 7546 | #define I2S_RCSR_FWF_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 7547 | #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7548 | #define I2S_RCSR_FEF_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 7549 | #define I2S_RCSR_FEF_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 7550 | #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7551 | #define I2S_RCSR_SEF_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 7552 | #define I2S_RCSR_SEF_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 7553 | #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7554 | #define I2S_RCSR_WSF_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 7555 | #define I2S_RCSR_WSF_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 7556 | #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7557 | #define I2S_RCSR_SR_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 7558 | #define I2S_RCSR_SR_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 7559 | #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7560 | #define I2S_RCSR_FR_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 7561 | #define I2S_RCSR_FR_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 7562 | #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7563 | #define I2S_RCSR_BCE_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 7564 | #define I2S_RCSR_BCE_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 7565 | #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7566 | #define I2S_RCSR_DBGE_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 7567 | #define I2S_RCSR_DBGE_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 7568 | #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7569 | #define I2S_RCSR_STOPE_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 7570 | #define I2S_RCSR_STOPE_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 7571 | #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7572 | #define I2S_RCSR_RE_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 7573 | #define I2S_RCSR_RE_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 7574 | #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7575 | |
AnnaBridge | 171:3a7713b1edbc | 7576 | /*! @name RCR1 - SAI Receive Configuration 1 Register */ |
AnnaBridge | 171:3a7713b1edbc | 7577 | #define I2S_RCR1_RFW_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 7578 | #define I2S_RCR1_RFW_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7579 | #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7580 | |
AnnaBridge | 171:3a7713b1edbc | 7581 | /*! @name RCR2 - SAI Receive Configuration 2 Register */ |
AnnaBridge | 171:3a7713b1edbc | 7582 | #define I2S_RCR2_DIV_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 7583 | #define I2S_RCR2_DIV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7584 | #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7585 | #define I2S_RCR2_BCD_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 7586 | #define I2S_RCR2_BCD_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 7587 | #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7588 | #define I2S_RCR2_BCP_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 7589 | #define I2S_RCR2_BCP_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 7590 | #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7591 | #define I2S_RCR2_MSEL_MASK (0xC000000U) |
AnnaBridge | 171:3a7713b1edbc | 7592 | #define I2S_RCR2_MSEL_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 7593 | #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7594 | #define I2S_RCR2_BCI_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 7595 | #define I2S_RCR2_BCI_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 7596 | #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7597 | #define I2S_RCR2_BCS_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 7598 | #define I2S_RCR2_BCS_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 7599 | #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7600 | #define I2S_RCR2_SYNC_MASK (0xC0000000U) |
AnnaBridge | 171:3a7713b1edbc | 7601 | #define I2S_RCR2_SYNC_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 7602 | #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7603 | |
AnnaBridge | 171:3a7713b1edbc | 7604 | /*! @name RCR3 - SAI Receive Configuration 3 Register */ |
AnnaBridge | 171:3a7713b1edbc | 7605 | #define I2S_RCR3_WDFL_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 7606 | #define I2S_RCR3_WDFL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7607 | #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7608 | #define I2S_RCR3_RCE_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 7609 | #define I2S_RCR3_RCE_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7610 | #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7611 | #define I2S_RCR3_CFR_MASK (0x3000000U) |
AnnaBridge | 171:3a7713b1edbc | 7612 | #define I2S_RCR3_CFR_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 7613 | #define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7614 | |
AnnaBridge | 171:3a7713b1edbc | 7615 | /*! @name RCR4 - SAI Receive Configuration 4 Register */ |
AnnaBridge | 171:3a7713b1edbc | 7616 | #define I2S_RCR4_FSD_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7617 | #define I2S_RCR4_FSD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7618 | #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7619 | #define I2S_RCR4_FSP_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7620 | #define I2S_RCR4_FSP_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7621 | #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7622 | #define I2S_RCR4_ONDEM_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 7623 | #define I2S_RCR4_ONDEM_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7624 | #define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7625 | #define I2S_RCR4_FSE_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 7626 | #define I2S_RCR4_FSE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 7627 | #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7628 | #define I2S_RCR4_MF_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 7629 | #define I2S_RCR4_MF_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7630 | #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7631 | #define I2S_RCR4_SYWD_MASK (0x1F00U) |
AnnaBridge | 171:3a7713b1edbc | 7632 | #define I2S_RCR4_SYWD_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 7633 | #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7634 | #define I2S_RCR4_FRSZ_MASK (0x1F0000U) |
AnnaBridge | 171:3a7713b1edbc | 7635 | #define I2S_RCR4_FRSZ_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7636 | #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7637 | #define I2S_RCR4_FPACK_MASK (0x3000000U) |
AnnaBridge | 171:3a7713b1edbc | 7638 | #define I2S_RCR4_FPACK_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 7639 | #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7640 | #define I2S_RCR4_FCOMB_MASK (0xC000000U) |
AnnaBridge | 171:3a7713b1edbc | 7641 | #define I2S_RCR4_FCOMB_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 7642 | #define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7643 | #define I2S_RCR4_FCONT_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 7644 | #define I2S_RCR4_FCONT_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 7645 | #define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7646 | |
AnnaBridge | 171:3a7713b1edbc | 7647 | /*! @name RCR5 - SAI Receive Configuration 5 Register */ |
AnnaBridge | 171:3a7713b1edbc | 7648 | #define I2S_RCR5_FBT_MASK (0x1F00U) |
AnnaBridge | 171:3a7713b1edbc | 7649 | #define I2S_RCR5_FBT_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 7650 | #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7651 | #define I2S_RCR5_W0W_MASK (0x1F0000U) |
AnnaBridge | 171:3a7713b1edbc | 7652 | #define I2S_RCR5_W0W_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7653 | #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7654 | #define I2S_RCR5_WNW_MASK (0x1F000000U) |
AnnaBridge | 171:3a7713b1edbc | 7655 | #define I2S_RCR5_WNW_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 7656 | #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7657 | |
AnnaBridge | 171:3a7713b1edbc | 7658 | /*! @name RDR - SAI Receive Data Register */ |
AnnaBridge | 171:3a7713b1edbc | 7659 | #define I2S_RDR_RDR_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7660 | #define I2S_RDR_RDR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7661 | #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7662 | |
AnnaBridge | 171:3a7713b1edbc | 7663 | /* The count of I2S_RDR */ |
AnnaBridge | 171:3a7713b1edbc | 7664 | #define I2S_RDR_COUNT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7665 | |
AnnaBridge | 171:3a7713b1edbc | 7666 | /*! @name RFR - SAI Receive FIFO Register */ |
AnnaBridge | 171:3a7713b1edbc | 7667 | #define I2S_RFR_RFP_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 7668 | #define I2S_RFR_RFP_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7669 | #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7670 | #define I2S_RFR_RCP_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 7671 | #define I2S_RFR_RCP_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 7672 | #define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7673 | #define I2S_RFR_WFP_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 7674 | #define I2S_RFR_WFP_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7675 | #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7676 | |
AnnaBridge | 171:3a7713b1edbc | 7677 | /* The count of I2S_RFR */ |
AnnaBridge | 171:3a7713b1edbc | 7678 | #define I2S_RFR_COUNT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7679 | |
AnnaBridge | 171:3a7713b1edbc | 7680 | /*! @name RMR - SAI Receive Mask Register */ |
AnnaBridge | 171:3a7713b1edbc | 7681 | #define I2S_RMR_RWM_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7682 | #define I2S_RMR_RWM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7683 | #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7684 | |
AnnaBridge | 171:3a7713b1edbc | 7685 | /*! @name MCR - SAI MCLK Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 7686 | #define I2S_MCR_MICS_MASK (0x3000000U) |
AnnaBridge | 171:3a7713b1edbc | 7687 | #define I2S_MCR_MICS_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 7688 | #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7689 | #define I2S_MCR_MOE_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 7690 | #define I2S_MCR_MOE_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 7691 | #define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7692 | #define I2S_MCR_DUF_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 7693 | #define I2S_MCR_DUF_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 7694 | #define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7695 | |
AnnaBridge | 171:3a7713b1edbc | 7696 | /*! @name MDR - SAI MCLK Divide Register */ |
AnnaBridge | 171:3a7713b1edbc | 7697 | #define I2S_MDR_DIVIDE_MASK (0xFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7698 | #define I2S_MDR_DIVIDE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7699 | #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7700 | #define I2S_MDR_FRACT_MASK (0xFF000U) |
AnnaBridge | 171:3a7713b1edbc | 7701 | #define I2S_MDR_FRACT_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 7702 | #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7703 | |
AnnaBridge | 171:3a7713b1edbc | 7704 | |
AnnaBridge | 171:3a7713b1edbc | 7705 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7706 | * @} |
AnnaBridge | 171:3a7713b1edbc | 7707 | */ /* end of group I2S_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 7708 | |
AnnaBridge | 171:3a7713b1edbc | 7709 | |
AnnaBridge | 171:3a7713b1edbc | 7710 | /* I2S - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 7711 | /** Peripheral I2S0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 7712 | #define I2S0_BASE (0x4002F000u) |
AnnaBridge | 171:3a7713b1edbc | 7713 | /** Peripheral I2S0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 7714 | #define I2S0 ((I2S_Type *)I2S0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 7715 | /** Array initializer of I2S peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 7716 | #define I2S_BASE_ADDRS { I2S0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 7717 | /** Array initializer of I2S peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 7718 | #define I2S_BASE_PTRS { I2S0 } |
AnnaBridge | 171:3a7713b1edbc | 7719 | /** Interrupt vectors for the I2S peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 7720 | #define I2S_RX_IRQS { I2S0_Rx_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 7721 | #define I2S_TX_IRQS { I2S0_Tx_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 7722 | |
AnnaBridge | 171:3a7713b1edbc | 7723 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7724 | * @} |
AnnaBridge | 171:3a7713b1edbc | 7725 | */ /* end of group I2S_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 7726 | |
AnnaBridge | 171:3a7713b1edbc | 7727 | |
AnnaBridge | 171:3a7713b1edbc | 7728 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 7729 | -- LLWU Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 7730 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 7731 | |
AnnaBridge | 171:3a7713b1edbc | 7732 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7733 | * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 7734 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 7735 | */ |
AnnaBridge | 171:3a7713b1edbc | 7736 | |
AnnaBridge | 171:3a7713b1edbc | 7737 | /** LLWU - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 7738 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 7739 | __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 7740 | __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 7741 | __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 7742 | __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */ |
AnnaBridge | 171:3a7713b1edbc | 7743 | __IO uint8_t PE5; /**< LLWU Pin Enable 5 register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 7744 | __IO uint8_t PE6; /**< LLWU Pin Enable 6 register, offset: 0x5 */ |
AnnaBridge | 171:3a7713b1edbc | 7745 | __IO uint8_t PE7; /**< LLWU Pin Enable 7 register, offset: 0x6 */ |
AnnaBridge | 171:3a7713b1edbc | 7746 | __IO uint8_t PE8; /**< LLWU Pin Enable 8 register, offset: 0x7 */ |
AnnaBridge | 171:3a7713b1edbc | 7747 | __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 7748 | __IO uint8_t PF1; /**< LLWU Pin Flag 1 register, offset: 0x9 */ |
AnnaBridge | 171:3a7713b1edbc | 7749 | __IO uint8_t PF2; /**< LLWU Pin Flag 2 register, offset: 0xA */ |
AnnaBridge | 171:3a7713b1edbc | 7750 | __IO uint8_t PF3; /**< LLWU Pin Flag 3 register, offset: 0xB */ |
AnnaBridge | 171:3a7713b1edbc | 7751 | __IO uint8_t PF4; /**< LLWU Pin Flag 4 register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 7752 | __I uint8_t MF5; /**< LLWU Module Flag 5 register, offset: 0xD */ |
AnnaBridge | 171:3a7713b1edbc | 7753 | __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0xE */ |
AnnaBridge | 171:3a7713b1edbc | 7754 | __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0xF */ |
AnnaBridge | 171:3a7713b1edbc | 7755 | __IO uint8_t FILT3; /**< LLWU Pin Filter 3 register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 7756 | __IO uint8_t FILT4; /**< LLWU Pin Filter 4 register, offset: 0x11 */ |
AnnaBridge | 171:3a7713b1edbc | 7757 | } LLWU_Type; |
AnnaBridge | 171:3a7713b1edbc | 7758 | |
AnnaBridge | 171:3a7713b1edbc | 7759 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 7760 | -- LLWU Register Masks |
AnnaBridge | 171:3a7713b1edbc | 7761 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 7762 | |
AnnaBridge | 171:3a7713b1edbc | 7763 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7764 | * @addtogroup LLWU_Register_Masks LLWU Register Masks |
AnnaBridge | 171:3a7713b1edbc | 7765 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 7766 | */ |
AnnaBridge | 171:3a7713b1edbc | 7767 | |
AnnaBridge | 171:3a7713b1edbc | 7768 | /*! @name PE1 - LLWU Pin Enable 1 register */ |
AnnaBridge | 171:3a7713b1edbc | 7769 | #define LLWU_PE1_WUPE0_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 7770 | #define LLWU_PE1_WUPE0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7771 | #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7772 | #define LLWU_PE1_WUPE1_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 7773 | #define LLWU_PE1_WUPE1_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7774 | #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7775 | #define LLWU_PE1_WUPE2_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 7776 | #define LLWU_PE1_WUPE2_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7777 | #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7778 | #define LLWU_PE1_WUPE3_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 7779 | #define LLWU_PE1_WUPE3_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7780 | #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7781 | |
AnnaBridge | 171:3a7713b1edbc | 7782 | /*! @name PE2 - LLWU Pin Enable 2 register */ |
AnnaBridge | 171:3a7713b1edbc | 7783 | #define LLWU_PE2_WUPE4_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 7784 | #define LLWU_PE2_WUPE4_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7785 | #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7786 | #define LLWU_PE2_WUPE5_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 7787 | #define LLWU_PE2_WUPE5_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7788 | #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7789 | #define LLWU_PE2_WUPE6_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 7790 | #define LLWU_PE2_WUPE6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7791 | #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7792 | #define LLWU_PE2_WUPE7_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 7793 | #define LLWU_PE2_WUPE7_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7794 | #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7795 | |
AnnaBridge | 171:3a7713b1edbc | 7796 | /*! @name PE3 - LLWU Pin Enable 3 register */ |
AnnaBridge | 171:3a7713b1edbc | 7797 | #define LLWU_PE3_WUPE8_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 7798 | #define LLWU_PE3_WUPE8_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7799 | #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7800 | #define LLWU_PE3_WUPE9_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 7801 | #define LLWU_PE3_WUPE9_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7802 | #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7803 | #define LLWU_PE3_WUPE10_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 7804 | #define LLWU_PE3_WUPE10_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7805 | #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7806 | #define LLWU_PE3_WUPE11_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 7807 | #define LLWU_PE3_WUPE11_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7808 | #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7809 | |
AnnaBridge | 171:3a7713b1edbc | 7810 | /*! @name PE4 - LLWU Pin Enable 4 register */ |
AnnaBridge | 171:3a7713b1edbc | 7811 | #define LLWU_PE4_WUPE12_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 7812 | #define LLWU_PE4_WUPE12_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7813 | #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7814 | #define LLWU_PE4_WUPE13_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 7815 | #define LLWU_PE4_WUPE13_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7816 | #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7817 | #define LLWU_PE4_WUPE14_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 7818 | #define LLWU_PE4_WUPE14_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7819 | #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7820 | #define LLWU_PE4_WUPE15_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 7821 | #define LLWU_PE4_WUPE15_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7822 | #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7823 | |
AnnaBridge | 171:3a7713b1edbc | 7824 | /*! @name PE5 - LLWU Pin Enable 5 register */ |
AnnaBridge | 171:3a7713b1edbc | 7825 | #define LLWU_PE5_WUPE16_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 7826 | #define LLWU_PE5_WUPE16_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7827 | #define LLWU_PE5_WUPE16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE16_SHIFT)) & LLWU_PE5_WUPE16_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7828 | #define LLWU_PE5_WUPE17_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 7829 | #define LLWU_PE5_WUPE17_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7830 | #define LLWU_PE5_WUPE17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE17_SHIFT)) & LLWU_PE5_WUPE17_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7831 | #define LLWU_PE5_WUPE18_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 7832 | #define LLWU_PE5_WUPE18_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7833 | #define LLWU_PE5_WUPE18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE18_SHIFT)) & LLWU_PE5_WUPE18_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7834 | #define LLWU_PE5_WUPE19_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 7835 | #define LLWU_PE5_WUPE19_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7836 | #define LLWU_PE5_WUPE19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE19_SHIFT)) & LLWU_PE5_WUPE19_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7837 | |
AnnaBridge | 171:3a7713b1edbc | 7838 | /*! @name PE6 - LLWU Pin Enable 6 register */ |
AnnaBridge | 171:3a7713b1edbc | 7839 | #define LLWU_PE6_WUPE20_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 7840 | #define LLWU_PE6_WUPE20_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7841 | #define LLWU_PE6_WUPE20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE20_SHIFT)) & LLWU_PE6_WUPE20_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7842 | #define LLWU_PE6_WUPE21_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 7843 | #define LLWU_PE6_WUPE21_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7844 | #define LLWU_PE6_WUPE21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE21_SHIFT)) & LLWU_PE6_WUPE21_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7845 | #define LLWU_PE6_WUPE22_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 7846 | #define LLWU_PE6_WUPE22_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7847 | #define LLWU_PE6_WUPE22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE22_SHIFT)) & LLWU_PE6_WUPE22_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7848 | #define LLWU_PE6_WUPE23_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 7849 | #define LLWU_PE6_WUPE23_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7850 | #define LLWU_PE6_WUPE23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE23_SHIFT)) & LLWU_PE6_WUPE23_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7851 | |
AnnaBridge | 171:3a7713b1edbc | 7852 | /*! @name PE7 - LLWU Pin Enable 7 register */ |
AnnaBridge | 171:3a7713b1edbc | 7853 | #define LLWU_PE7_WUPE24_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 7854 | #define LLWU_PE7_WUPE24_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7855 | #define LLWU_PE7_WUPE24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE24_SHIFT)) & LLWU_PE7_WUPE24_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7856 | #define LLWU_PE7_WUPE25_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 7857 | #define LLWU_PE7_WUPE25_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7858 | #define LLWU_PE7_WUPE25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE25_SHIFT)) & LLWU_PE7_WUPE25_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7859 | #define LLWU_PE7_WUPE26_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 7860 | #define LLWU_PE7_WUPE26_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7861 | #define LLWU_PE7_WUPE26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE26_SHIFT)) & LLWU_PE7_WUPE26_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7862 | #define LLWU_PE7_WUPE27_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 7863 | #define LLWU_PE7_WUPE27_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7864 | #define LLWU_PE7_WUPE27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE27_SHIFT)) & LLWU_PE7_WUPE27_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7865 | |
AnnaBridge | 171:3a7713b1edbc | 7866 | /*! @name PE8 - LLWU Pin Enable 8 register */ |
AnnaBridge | 171:3a7713b1edbc | 7867 | #define LLWU_PE8_WUPE28_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 7868 | #define LLWU_PE8_WUPE28_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7869 | #define LLWU_PE8_WUPE28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE28_SHIFT)) & LLWU_PE8_WUPE28_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7870 | #define LLWU_PE8_WUPE29_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 7871 | #define LLWU_PE8_WUPE29_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7872 | #define LLWU_PE8_WUPE29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE29_SHIFT)) & LLWU_PE8_WUPE29_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7873 | #define LLWU_PE8_WUPE30_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 7874 | #define LLWU_PE8_WUPE30_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7875 | #define LLWU_PE8_WUPE30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE30_SHIFT)) & LLWU_PE8_WUPE30_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7876 | #define LLWU_PE8_WUPE31_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 7877 | #define LLWU_PE8_WUPE31_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7878 | #define LLWU_PE8_WUPE31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE31_SHIFT)) & LLWU_PE8_WUPE31_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7879 | |
AnnaBridge | 171:3a7713b1edbc | 7880 | /*! @name ME - LLWU Module Enable register */ |
AnnaBridge | 171:3a7713b1edbc | 7881 | #define LLWU_ME_WUME0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7882 | #define LLWU_ME_WUME0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7883 | #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7884 | #define LLWU_ME_WUME1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7885 | #define LLWU_ME_WUME1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7886 | #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7887 | #define LLWU_ME_WUME2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 7888 | #define LLWU_ME_WUME2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7889 | #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7890 | #define LLWU_ME_WUME3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 7891 | #define LLWU_ME_WUME3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 7892 | #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7893 | #define LLWU_ME_WUME4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 7894 | #define LLWU_ME_WUME4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7895 | #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7896 | #define LLWU_ME_WUME5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 7897 | #define LLWU_ME_WUME5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 7898 | #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7899 | #define LLWU_ME_WUME6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 7900 | #define LLWU_ME_WUME6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7901 | #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7902 | #define LLWU_ME_WUME7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 7903 | #define LLWU_ME_WUME7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 7904 | #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7905 | |
AnnaBridge | 171:3a7713b1edbc | 7906 | /*! @name PF1 - LLWU Pin Flag 1 register */ |
AnnaBridge | 171:3a7713b1edbc | 7907 | #define LLWU_PF1_WUF0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7908 | #define LLWU_PF1_WUF0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7909 | #define LLWU_PF1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF0_SHIFT)) & LLWU_PF1_WUF0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7910 | #define LLWU_PF1_WUF1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7911 | #define LLWU_PF1_WUF1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7912 | #define LLWU_PF1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF1_SHIFT)) & LLWU_PF1_WUF1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7913 | #define LLWU_PF1_WUF2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 7914 | #define LLWU_PF1_WUF2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7915 | #define LLWU_PF1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF2_SHIFT)) & LLWU_PF1_WUF2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7916 | #define LLWU_PF1_WUF3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 7917 | #define LLWU_PF1_WUF3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 7918 | #define LLWU_PF1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF3_SHIFT)) & LLWU_PF1_WUF3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7919 | #define LLWU_PF1_WUF4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 7920 | #define LLWU_PF1_WUF4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7921 | #define LLWU_PF1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF4_SHIFT)) & LLWU_PF1_WUF4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7922 | #define LLWU_PF1_WUF5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 7923 | #define LLWU_PF1_WUF5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 7924 | #define LLWU_PF1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF5_SHIFT)) & LLWU_PF1_WUF5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7925 | #define LLWU_PF1_WUF6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 7926 | #define LLWU_PF1_WUF6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7927 | #define LLWU_PF1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF6_SHIFT)) & LLWU_PF1_WUF6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7928 | #define LLWU_PF1_WUF7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 7929 | #define LLWU_PF1_WUF7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 7930 | #define LLWU_PF1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF7_SHIFT)) & LLWU_PF1_WUF7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7931 | |
AnnaBridge | 171:3a7713b1edbc | 7932 | /*! @name PF2 - LLWU Pin Flag 2 register */ |
AnnaBridge | 171:3a7713b1edbc | 7933 | #define LLWU_PF2_WUF8_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7934 | #define LLWU_PF2_WUF8_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7935 | #define LLWU_PF2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF8_SHIFT)) & LLWU_PF2_WUF8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7936 | #define LLWU_PF2_WUF9_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7937 | #define LLWU_PF2_WUF9_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7938 | #define LLWU_PF2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF9_SHIFT)) & LLWU_PF2_WUF9_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7939 | #define LLWU_PF2_WUF10_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 7940 | #define LLWU_PF2_WUF10_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7941 | #define LLWU_PF2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF10_SHIFT)) & LLWU_PF2_WUF10_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7942 | #define LLWU_PF2_WUF11_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 7943 | #define LLWU_PF2_WUF11_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 7944 | #define LLWU_PF2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF11_SHIFT)) & LLWU_PF2_WUF11_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7945 | #define LLWU_PF2_WUF12_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 7946 | #define LLWU_PF2_WUF12_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7947 | #define LLWU_PF2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF12_SHIFT)) & LLWU_PF2_WUF12_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7948 | #define LLWU_PF2_WUF13_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 7949 | #define LLWU_PF2_WUF13_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 7950 | #define LLWU_PF2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF13_SHIFT)) & LLWU_PF2_WUF13_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7951 | #define LLWU_PF2_WUF14_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 7952 | #define LLWU_PF2_WUF14_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7953 | #define LLWU_PF2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF14_SHIFT)) & LLWU_PF2_WUF14_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7954 | #define LLWU_PF2_WUF15_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 7955 | #define LLWU_PF2_WUF15_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 7956 | #define LLWU_PF2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF15_SHIFT)) & LLWU_PF2_WUF15_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7957 | |
AnnaBridge | 171:3a7713b1edbc | 7958 | /*! @name PF3 - LLWU Pin Flag 3 register */ |
AnnaBridge | 171:3a7713b1edbc | 7959 | #define LLWU_PF3_WUF16_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7960 | #define LLWU_PF3_WUF16_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7961 | #define LLWU_PF3_WUF16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF16_SHIFT)) & LLWU_PF3_WUF16_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7962 | #define LLWU_PF3_WUF17_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7963 | #define LLWU_PF3_WUF17_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7964 | #define LLWU_PF3_WUF17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF17_SHIFT)) & LLWU_PF3_WUF17_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7965 | #define LLWU_PF3_WUF18_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 7966 | #define LLWU_PF3_WUF18_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7967 | #define LLWU_PF3_WUF18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF18_SHIFT)) & LLWU_PF3_WUF18_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7968 | #define LLWU_PF3_WUF19_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 7969 | #define LLWU_PF3_WUF19_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 7970 | #define LLWU_PF3_WUF19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF19_SHIFT)) & LLWU_PF3_WUF19_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7971 | #define LLWU_PF3_WUF20_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 7972 | #define LLWU_PF3_WUF20_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7973 | #define LLWU_PF3_WUF20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF20_SHIFT)) & LLWU_PF3_WUF20_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7974 | #define LLWU_PF3_WUF21_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 7975 | #define LLWU_PF3_WUF21_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 7976 | #define LLWU_PF3_WUF21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF21_SHIFT)) & LLWU_PF3_WUF21_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7977 | #define LLWU_PF3_WUF22_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 7978 | #define LLWU_PF3_WUF22_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7979 | #define LLWU_PF3_WUF22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF22_SHIFT)) & LLWU_PF3_WUF22_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7980 | #define LLWU_PF3_WUF23_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 7981 | #define LLWU_PF3_WUF23_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 7982 | #define LLWU_PF3_WUF23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF23_SHIFT)) & LLWU_PF3_WUF23_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7983 | |
AnnaBridge | 171:3a7713b1edbc | 7984 | /*! @name PF4 - LLWU Pin Flag 4 register */ |
AnnaBridge | 171:3a7713b1edbc | 7985 | #define LLWU_PF4_WUF24_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7986 | #define LLWU_PF4_WUF24_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7987 | #define LLWU_PF4_WUF24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF24_SHIFT)) & LLWU_PF4_WUF24_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7988 | #define LLWU_PF4_WUF25_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7989 | #define LLWU_PF4_WUF25_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7990 | #define LLWU_PF4_WUF25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF25_SHIFT)) & LLWU_PF4_WUF25_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7991 | #define LLWU_PF4_WUF26_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 7992 | #define LLWU_PF4_WUF26_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7993 | #define LLWU_PF4_WUF26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF26_SHIFT)) & LLWU_PF4_WUF26_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7994 | #define LLWU_PF4_WUF27_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 7995 | #define LLWU_PF4_WUF27_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 7996 | #define LLWU_PF4_WUF27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF27_SHIFT)) & LLWU_PF4_WUF27_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7997 | #define LLWU_PF4_WUF28_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 7998 | #define LLWU_PF4_WUF28_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7999 | #define LLWU_PF4_WUF28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF28_SHIFT)) & LLWU_PF4_WUF28_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8000 | #define LLWU_PF4_WUF29_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 8001 | #define LLWU_PF4_WUF29_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 8002 | #define LLWU_PF4_WUF29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF29_SHIFT)) & LLWU_PF4_WUF29_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8003 | #define LLWU_PF4_WUF30_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 8004 | #define LLWU_PF4_WUF30_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 8005 | #define LLWU_PF4_WUF30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF30_SHIFT)) & LLWU_PF4_WUF30_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8006 | #define LLWU_PF4_WUF31_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 8007 | #define LLWU_PF4_WUF31_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 8008 | #define LLWU_PF4_WUF31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF31_SHIFT)) & LLWU_PF4_WUF31_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8009 | |
AnnaBridge | 171:3a7713b1edbc | 8010 | /*! @name MF5 - LLWU Module Flag 5 register */ |
AnnaBridge | 171:3a7713b1edbc | 8011 | #define LLWU_MF5_MWUF0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8012 | #define LLWU_MF5_MWUF0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8013 | #define LLWU_MF5_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF0_SHIFT)) & LLWU_MF5_MWUF0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8014 | #define LLWU_MF5_MWUF1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 8015 | #define LLWU_MF5_MWUF1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 8016 | #define LLWU_MF5_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF1_SHIFT)) & LLWU_MF5_MWUF1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8017 | #define LLWU_MF5_MWUF2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 8018 | #define LLWU_MF5_MWUF2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8019 | #define LLWU_MF5_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF2_SHIFT)) & LLWU_MF5_MWUF2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8020 | #define LLWU_MF5_MWUF3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 8021 | #define LLWU_MF5_MWUF3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 8022 | #define LLWU_MF5_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF3_SHIFT)) & LLWU_MF5_MWUF3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8023 | #define LLWU_MF5_MWUF4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 8024 | #define LLWU_MF5_MWUF4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 8025 | #define LLWU_MF5_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF4_SHIFT)) & LLWU_MF5_MWUF4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8026 | #define LLWU_MF5_MWUF5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 8027 | #define LLWU_MF5_MWUF5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 8028 | #define LLWU_MF5_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF5_SHIFT)) & LLWU_MF5_MWUF5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8029 | #define LLWU_MF5_MWUF6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 8030 | #define LLWU_MF5_MWUF6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 8031 | #define LLWU_MF5_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF6_SHIFT)) & LLWU_MF5_MWUF6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8032 | #define LLWU_MF5_MWUF7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 8033 | #define LLWU_MF5_MWUF7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 8034 | #define LLWU_MF5_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF7_SHIFT)) & LLWU_MF5_MWUF7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8035 | |
AnnaBridge | 171:3a7713b1edbc | 8036 | /*! @name FILT1 - LLWU Pin Filter 1 register */ |
AnnaBridge | 171:3a7713b1edbc | 8037 | #define LLWU_FILT1_FILTSEL_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 8038 | #define LLWU_FILT1_FILTSEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8039 | #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8040 | #define LLWU_FILT1_FILTE_MASK (0x60U) |
AnnaBridge | 171:3a7713b1edbc | 8041 | #define LLWU_FILT1_FILTE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 8042 | #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8043 | #define LLWU_FILT1_FILTF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 8044 | #define LLWU_FILT1_FILTF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 8045 | #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8046 | |
AnnaBridge | 171:3a7713b1edbc | 8047 | /*! @name FILT2 - LLWU Pin Filter 2 register */ |
AnnaBridge | 171:3a7713b1edbc | 8048 | #define LLWU_FILT2_FILTSEL_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 8049 | #define LLWU_FILT2_FILTSEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8050 | #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8051 | #define LLWU_FILT2_FILTE_MASK (0x60U) |
AnnaBridge | 171:3a7713b1edbc | 8052 | #define LLWU_FILT2_FILTE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 8053 | #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8054 | #define LLWU_FILT2_FILTF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 8055 | #define LLWU_FILT2_FILTF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 8056 | #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8057 | |
AnnaBridge | 171:3a7713b1edbc | 8058 | /*! @name FILT3 - LLWU Pin Filter 3 register */ |
AnnaBridge | 171:3a7713b1edbc | 8059 | #define LLWU_FILT3_FILTSEL_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 8060 | #define LLWU_FILT3_FILTSEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8061 | #define LLWU_FILT3_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTSEL_SHIFT)) & LLWU_FILT3_FILTSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8062 | #define LLWU_FILT3_FILTE_MASK (0x60U) |
AnnaBridge | 171:3a7713b1edbc | 8063 | #define LLWU_FILT3_FILTE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 8064 | #define LLWU_FILT3_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTE_SHIFT)) & LLWU_FILT3_FILTE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8065 | #define LLWU_FILT3_FILTF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 8066 | #define LLWU_FILT3_FILTF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 8067 | #define LLWU_FILT3_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTF_SHIFT)) & LLWU_FILT3_FILTF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8068 | |
AnnaBridge | 171:3a7713b1edbc | 8069 | /*! @name FILT4 - LLWU Pin Filter 4 register */ |
AnnaBridge | 171:3a7713b1edbc | 8070 | #define LLWU_FILT4_FILTSEL_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 8071 | #define LLWU_FILT4_FILTSEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8072 | #define LLWU_FILT4_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTSEL_SHIFT)) & LLWU_FILT4_FILTSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8073 | #define LLWU_FILT4_FILTE_MASK (0x60U) |
AnnaBridge | 171:3a7713b1edbc | 8074 | #define LLWU_FILT4_FILTE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 8075 | #define LLWU_FILT4_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTE_SHIFT)) & LLWU_FILT4_FILTE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8076 | #define LLWU_FILT4_FILTF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 8077 | #define LLWU_FILT4_FILTF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 8078 | #define LLWU_FILT4_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTF_SHIFT)) & LLWU_FILT4_FILTF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8079 | |
AnnaBridge | 171:3a7713b1edbc | 8080 | |
AnnaBridge | 171:3a7713b1edbc | 8081 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8082 | * @} |
AnnaBridge | 171:3a7713b1edbc | 8083 | */ /* end of group LLWU_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 8084 | |
AnnaBridge | 171:3a7713b1edbc | 8085 | |
AnnaBridge | 171:3a7713b1edbc | 8086 | /* LLWU - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 8087 | /** Peripheral LLWU base address */ |
AnnaBridge | 171:3a7713b1edbc | 8088 | #define LLWU_BASE (0x4007C000u) |
AnnaBridge | 171:3a7713b1edbc | 8089 | /** Peripheral LLWU base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 8090 | #define LLWU ((LLWU_Type *)LLWU_BASE) |
AnnaBridge | 171:3a7713b1edbc | 8091 | /** Array initializer of LLWU peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 8092 | #define LLWU_BASE_ADDRS { LLWU_BASE } |
AnnaBridge | 171:3a7713b1edbc | 8093 | /** Array initializer of LLWU peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 8094 | #define LLWU_BASE_PTRS { LLWU } |
AnnaBridge | 171:3a7713b1edbc | 8095 | /** Interrupt vectors for the LLWU peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 8096 | #define LLWU_IRQS { LLWU_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 8097 | |
AnnaBridge | 171:3a7713b1edbc | 8098 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8099 | * @} |
AnnaBridge | 171:3a7713b1edbc | 8100 | */ /* end of group LLWU_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 8101 | |
AnnaBridge | 171:3a7713b1edbc | 8102 | |
AnnaBridge | 171:3a7713b1edbc | 8103 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 8104 | -- LMEM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 8105 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 8106 | |
AnnaBridge | 171:3a7713b1edbc | 8107 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8108 | * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 8109 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 8110 | */ |
AnnaBridge | 171:3a7713b1edbc | 8111 | |
AnnaBridge | 171:3a7713b1edbc | 8112 | /** LMEM - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 8113 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 8114 | __IO uint32_t PCCCR; /**< Cache control register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 8115 | __IO uint32_t PCCLCR; /**< Cache line control register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8116 | __IO uint32_t PCCSAR; /**< Cache search address register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 8117 | __IO uint32_t PCCCVR; /**< Cache read/write value register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 8118 | uint8_t RESERVED_0[16]; |
AnnaBridge | 171:3a7713b1edbc | 8119 | __IO uint32_t PCCRMR; /**< Cache regions mode register, offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 8120 | uint8_t RESERVED_1[2012]; |
AnnaBridge | 171:3a7713b1edbc | 8121 | __IO uint32_t PSCCR; /**< Cache control register, offset: 0x800 */ |
AnnaBridge | 171:3a7713b1edbc | 8122 | __IO uint32_t PSCLCR; /**< Cache line control register, offset: 0x804 */ |
AnnaBridge | 171:3a7713b1edbc | 8123 | __IO uint32_t PSCSAR; /**< Cache search address register, offset: 0x808 */ |
AnnaBridge | 171:3a7713b1edbc | 8124 | __IO uint32_t PSCCVR; /**< Cache read/write value register, offset: 0x80C */ |
AnnaBridge | 171:3a7713b1edbc | 8125 | uint8_t RESERVED_2[16]; |
AnnaBridge | 171:3a7713b1edbc | 8126 | __IO uint32_t PSCRMR; /**< Cache regions mode register, offset: 0x820 */ |
AnnaBridge | 171:3a7713b1edbc | 8127 | } LMEM_Type; |
AnnaBridge | 171:3a7713b1edbc | 8128 | |
AnnaBridge | 171:3a7713b1edbc | 8129 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 8130 | -- LMEM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 8131 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 8132 | |
AnnaBridge | 171:3a7713b1edbc | 8133 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8134 | * @addtogroup LMEM_Register_Masks LMEM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 8135 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 8136 | */ |
AnnaBridge | 171:3a7713b1edbc | 8137 | |
AnnaBridge | 171:3a7713b1edbc | 8138 | /*! @name PCCCR - Cache control register */ |
AnnaBridge | 171:3a7713b1edbc | 8139 | #define LMEM_PCCCR_ENCACHE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8140 | #define LMEM_PCCCR_ENCACHE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8141 | #define LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8142 | #define LMEM_PCCCR_ENWRBUF_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 8143 | #define LMEM_PCCCR_ENWRBUF_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 8144 | #define LMEM_PCCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8145 | #define LMEM_PCCCR_PCCR2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 8146 | #define LMEM_PCCCR_PCCR2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8147 | #define LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8148 | #define LMEM_PCCCR_PCCR3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 8149 | #define LMEM_PCCCR_PCCR3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 8150 | #define LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8151 | #define LMEM_PCCCR_INVW0_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 8152 | #define LMEM_PCCCR_INVW0_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 8153 | #define LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8154 | #define LMEM_PCCCR_PUSHW0_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 8155 | #define LMEM_PCCCR_PUSHW0_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 8156 | #define LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8157 | #define LMEM_PCCCR_INVW1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 8158 | #define LMEM_PCCCR_INVW1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 8159 | #define LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8160 | #define LMEM_PCCCR_PUSHW1_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 8161 | #define LMEM_PCCCR_PUSHW1_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 8162 | #define LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8163 | #define LMEM_PCCCR_GO_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 8164 | #define LMEM_PCCCR_GO_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 8165 | #define LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8166 | |
AnnaBridge | 171:3a7713b1edbc | 8167 | /*! @name PCCLCR - Cache line control register */ |
AnnaBridge | 171:3a7713b1edbc | 8168 | #define LMEM_PCCLCR_LGO_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8169 | #define LMEM_PCCLCR_LGO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8170 | #define LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8171 | #define LMEM_PCCLCR_CACHEADDR_MASK (0xFFCU) |
AnnaBridge | 171:3a7713b1edbc | 8172 | #define LMEM_PCCLCR_CACHEADDR_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8173 | #define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8174 | #define LMEM_PCCLCR_WSEL_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 8175 | #define LMEM_PCCLCR_WSEL_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 8176 | #define LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8177 | #define LMEM_PCCLCR_TDSEL_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 8178 | #define LMEM_PCCLCR_TDSEL_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 8179 | #define LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8180 | #define LMEM_PCCLCR_LCIVB_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 8181 | #define LMEM_PCCLCR_LCIVB_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 8182 | #define LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8183 | #define LMEM_PCCLCR_LCIMB_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 8184 | #define LMEM_PCCLCR_LCIMB_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 8185 | #define LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8186 | #define LMEM_PCCLCR_LCWAY_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 8187 | #define LMEM_PCCLCR_LCWAY_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 8188 | #define LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8189 | #define LMEM_PCCLCR_LCMD_MASK (0x3000000U) |
AnnaBridge | 171:3a7713b1edbc | 8190 | #define LMEM_PCCLCR_LCMD_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 8191 | #define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8192 | #define LMEM_PCCLCR_LADSEL_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 8193 | #define LMEM_PCCLCR_LADSEL_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 8194 | #define LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8195 | #define LMEM_PCCLCR_LACC_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 8196 | #define LMEM_PCCLCR_LACC_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 8197 | #define LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8198 | |
AnnaBridge | 171:3a7713b1edbc | 8199 | /*! @name PCCSAR - Cache search address register */ |
AnnaBridge | 171:3a7713b1edbc | 8200 | #define LMEM_PCCSAR_LGO_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8201 | #define LMEM_PCCSAR_LGO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8202 | #define LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8203 | #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) |
AnnaBridge | 171:3a7713b1edbc | 8204 | #define LMEM_PCCSAR_PHYADDR_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8205 | #define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8206 | |
AnnaBridge | 171:3a7713b1edbc | 8207 | /*! @name PCCCVR - Cache read/write value register */ |
AnnaBridge | 171:3a7713b1edbc | 8208 | #define LMEM_PCCCVR_DATA_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8209 | #define LMEM_PCCCVR_DATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8210 | #define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8211 | |
AnnaBridge | 171:3a7713b1edbc | 8212 | /*! @name PCCRMR - Cache regions mode register */ |
AnnaBridge | 171:3a7713b1edbc | 8213 | #define LMEM_PCCRMR_R15_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 8214 | #define LMEM_PCCRMR_R15_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8215 | #define LMEM_PCCRMR_R15(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R15_SHIFT)) & LMEM_PCCRMR_R15_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8216 | #define LMEM_PCCRMR_R14_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 8217 | #define LMEM_PCCRMR_R14_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8218 | #define LMEM_PCCRMR_R14(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R14_SHIFT)) & LMEM_PCCRMR_R14_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8219 | #define LMEM_PCCRMR_R13_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 8220 | #define LMEM_PCCRMR_R13_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 8221 | #define LMEM_PCCRMR_R13(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R13_SHIFT)) & LMEM_PCCRMR_R13_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8222 | #define LMEM_PCCRMR_R12_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 8223 | #define LMEM_PCCRMR_R12_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 8224 | #define LMEM_PCCRMR_R12(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R12_SHIFT)) & LMEM_PCCRMR_R12_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8225 | #define LMEM_PCCRMR_R11_MASK (0x300U) |
AnnaBridge | 171:3a7713b1edbc | 8226 | #define LMEM_PCCRMR_R11_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 8227 | #define LMEM_PCCRMR_R11(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R11_SHIFT)) & LMEM_PCCRMR_R11_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8228 | #define LMEM_PCCRMR_R10_MASK (0xC00U) |
AnnaBridge | 171:3a7713b1edbc | 8229 | #define LMEM_PCCRMR_R10_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 8230 | #define LMEM_PCCRMR_R10(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R10_SHIFT)) & LMEM_PCCRMR_R10_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8231 | #define LMEM_PCCRMR_R9_MASK (0x3000U) |
AnnaBridge | 171:3a7713b1edbc | 8232 | #define LMEM_PCCRMR_R9_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 8233 | #define LMEM_PCCRMR_R9(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R9_SHIFT)) & LMEM_PCCRMR_R9_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8234 | #define LMEM_PCCRMR_R8_MASK (0xC000U) |
AnnaBridge | 171:3a7713b1edbc | 8235 | #define LMEM_PCCRMR_R8_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 8236 | #define LMEM_PCCRMR_R8(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R8_SHIFT)) & LMEM_PCCRMR_R8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8237 | #define LMEM_PCCRMR_R7_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 8238 | #define LMEM_PCCRMR_R7_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 8239 | #define LMEM_PCCRMR_R7(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R7_SHIFT)) & LMEM_PCCRMR_R7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8240 | #define LMEM_PCCRMR_R6_MASK (0xC0000U) |
AnnaBridge | 171:3a7713b1edbc | 8241 | #define LMEM_PCCRMR_R6_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 8242 | #define LMEM_PCCRMR_R6(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R6_SHIFT)) & LMEM_PCCRMR_R6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8243 | #define LMEM_PCCRMR_R5_MASK (0x300000U) |
AnnaBridge | 171:3a7713b1edbc | 8244 | #define LMEM_PCCRMR_R5_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 8245 | #define LMEM_PCCRMR_R5(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R5_SHIFT)) & LMEM_PCCRMR_R5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8246 | #define LMEM_PCCRMR_R4_MASK (0xC00000U) |
AnnaBridge | 171:3a7713b1edbc | 8247 | #define LMEM_PCCRMR_R4_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 8248 | #define LMEM_PCCRMR_R4(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R4_SHIFT)) & LMEM_PCCRMR_R4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8249 | #define LMEM_PCCRMR_R3_MASK (0x3000000U) |
AnnaBridge | 171:3a7713b1edbc | 8250 | #define LMEM_PCCRMR_R3_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 8251 | #define LMEM_PCCRMR_R3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R3_SHIFT)) & LMEM_PCCRMR_R3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8252 | #define LMEM_PCCRMR_R2_MASK (0xC000000U) |
AnnaBridge | 171:3a7713b1edbc | 8253 | #define LMEM_PCCRMR_R2_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 8254 | #define LMEM_PCCRMR_R2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R2_SHIFT)) & LMEM_PCCRMR_R2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8255 | #define LMEM_PCCRMR_R1_MASK (0x30000000U) |
AnnaBridge | 171:3a7713b1edbc | 8256 | #define LMEM_PCCRMR_R1_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 8257 | #define LMEM_PCCRMR_R1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R1_SHIFT)) & LMEM_PCCRMR_R1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8258 | #define LMEM_PCCRMR_R0_MASK (0xC0000000U) |
AnnaBridge | 171:3a7713b1edbc | 8259 | #define LMEM_PCCRMR_R0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 8260 | #define LMEM_PCCRMR_R0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R0_SHIFT)) & LMEM_PCCRMR_R0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8261 | |
AnnaBridge | 171:3a7713b1edbc | 8262 | /*! @name PSCCR - Cache control register */ |
AnnaBridge | 171:3a7713b1edbc | 8263 | #define LMEM_PSCCR_ENCACHE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8264 | #define LMEM_PSCCR_ENCACHE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8265 | #define LMEM_PSCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENCACHE_SHIFT)) & LMEM_PSCCR_ENCACHE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8266 | #define LMEM_PSCCR_ENWRBUF_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 8267 | #define LMEM_PSCCR_ENWRBUF_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 8268 | #define LMEM_PSCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENWRBUF_SHIFT)) & LMEM_PSCCR_ENWRBUF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8269 | #define LMEM_PSCCR_INVW0_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 8270 | #define LMEM_PSCCR_INVW0_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 8271 | #define LMEM_PSCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW0_SHIFT)) & LMEM_PSCCR_INVW0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8272 | #define LMEM_PSCCR_PUSHW0_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 8273 | #define LMEM_PSCCR_PUSHW0_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 8274 | #define LMEM_PSCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW0_SHIFT)) & LMEM_PSCCR_PUSHW0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8275 | #define LMEM_PSCCR_INVW1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 8276 | #define LMEM_PSCCR_INVW1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 8277 | #define LMEM_PSCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW1_SHIFT)) & LMEM_PSCCR_INVW1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8278 | #define LMEM_PSCCR_PUSHW1_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 8279 | #define LMEM_PSCCR_PUSHW1_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 8280 | #define LMEM_PSCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW1_SHIFT)) & LMEM_PSCCR_PUSHW1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8281 | #define LMEM_PSCCR_GO_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 8282 | #define LMEM_PSCCR_GO_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 8283 | #define LMEM_PSCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_GO_SHIFT)) & LMEM_PSCCR_GO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8284 | |
AnnaBridge | 171:3a7713b1edbc | 8285 | /*! @name PSCLCR - Cache line control register */ |
AnnaBridge | 171:3a7713b1edbc | 8286 | #define LMEM_PSCLCR_LGO_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8287 | #define LMEM_PSCLCR_LGO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8288 | #define LMEM_PSCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LGO_SHIFT)) & LMEM_PSCLCR_LGO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8289 | #define LMEM_PSCLCR_CACHEADDR_MASK (0xFFCU) |
AnnaBridge | 171:3a7713b1edbc | 8290 | #define LMEM_PSCLCR_CACHEADDR_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8291 | #define LMEM_PSCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_CACHEADDR_SHIFT)) & LMEM_PSCLCR_CACHEADDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8292 | #define LMEM_PSCLCR_WSEL_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 8293 | #define LMEM_PSCLCR_WSEL_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 8294 | #define LMEM_PSCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_WSEL_SHIFT)) & LMEM_PSCLCR_WSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8295 | #define LMEM_PSCLCR_TDSEL_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 8296 | #define LMEM_PSCLCR_TDSEL_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 8297 | #define LMEM_PSCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_TDSEL_SHIFT)) & LMEM_PSCLCR_TDSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8298 | #define LMEM_PSCLCR_LCIVB_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 8299 | #define LMEM_PSCLCR_LCIVB_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 8300 | #define LMEM_PSCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIVB_SHIFT)) & LMEM_PSCLCR_LCIVB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8301 | #define LMEM_PSCLCR_LCIMB_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 8302 | #define LMEM_PSCLCR_LCIMB_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 8303 | #define LMEM_PSCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIMB_SHIFT)) & LMEM_PSCLCR_LCIMB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8304 | #define LMEM_PSCLCR_LCWAY_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 8305 | #define LMEM_PSCLCR_LCWAY_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 8306 | #define LMEM_PSCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCWAY_SHIFT)) & LMEM_PSCLCR_LCWAY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8307 | #define LMEM_PSCLCR_LCMD_MASK (0x3000000U) |
AnnaBridge | 171:3a7713b1edbc | 8308 | #define LMEM_PSCLCR_LCMD_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 8309 | #define LMEM_PSCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCMD_SHIFT)) & LMEM_PSCLCR_LCMD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8310 | #define LMEM_PSCLCR_LADSEL_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 8311 | #define LMEM_PSCLCR_LADSEL_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 8312 | #define LMEM_PSCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LADSEL_SHIFT)) & LMEM_PSCLCR_LADSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8313 | #define LMEM_PSCLCR_LACC_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 8314 | #define LMEM_PSCLCR_LACC_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 8315 | #define LMEM_PSCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LACC_SHIFT)) & LMEM_PSCLCR_LACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8316 | |
AnnaBridge | 171:3a7713b1edbc | 8317 | /*! @name PSCSAR - Cache search address register */ |
AnnaBridge | 171:3a7713b1edbc | 8318 | #define LMEM_PSCSAR_LGO_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8319 | #define LMEM_PSCSAR_LGO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8320 | #define LMEM_PSCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_LGO_SHIFT)) & LMEM_PSCSAR_LGO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8321 | #define LMEM_PSCSAR_PHYADDR_MASK (0xFFFFFFFCU) |
AnnaBridge | 171:3a7713b1edbc | 8322 | #define LMEM_PSCSAR_PHYADDR_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8323 | #define LMEM_PSCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_PHYADDR_SHIFT)) & LMEM_PSCSAR_PHYADDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8324 | |
AnnaBridge | 171:3a7713b1edbc | 8325 | /*! @name PSCCVR - Cache read/write value register */ |
AnnaBridge | 171:3a7713b1edbc | 8326 | #define LMEM_PSCCVR_DATA_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8327 | #define LMEM_PSCCVR_DATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8328 | #define LMEM_PSCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCVR_DATA_SHIFT)) & LMEM_PSCCVR_DATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8329 | |
AnnaBridge | 171:3a7713b1edbc | 8330 | /*! @name PSCRMR - Cache regions mode register */ |
AnnaBridge | 171:3a7713b1edbc | 8331 | #define LMEM_PSCRMR_R15_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 8332 | #define LMEM_PSCRMR_R15_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8333 | #define LMEM_PSCRMR_R15(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R15_SHIFT)) & LMEM_PSCRMR_R15_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8334 | #define LMEM_PSCRMR_R14_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 8335 | #define LMEM_PSCRMR_R14_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8336 | #define LMEM_PSCRMR_R14(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R14_SHIFT)) & LMEM_PSCRMR_R14_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8337 | #define LMEM_PSCRMR_R13_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 8338 | #define LMEM_PSCRMR_R13_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 8339 | #define LMEM_PSCRMR_R13(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R13_SHIFT)) & LMEM_PSCRMR_R13_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8340 | #define LMEM_PSCRMR_R12_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 8341 | #define LMEM_PSCRMR_R12_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 8342 | #define LMEM_PSCRMR_R12(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R12_SHIFT)) & LMEM_PSCRMR_R12_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8343 | #define LMEM_PSCRMR_R11_MASK (0x300U) |
AnnaBridge | 171:3a7713b1edbc | 8344 | #define LMEM_PSCRMR_R11_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 8345 | #define LMEM_PSCRMR_R11(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R11_SHIFT)) & LMEM_PSCRMR_R11_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8346 | #define LMEM_PSCRMR_R10_MASK (0xC00U) |
AnnaBridge | 171:3a7713b1edbc | 8347 | #define LMEM_PSCRMR_R10_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 8348 | #define LMEM_PSCRMR_R10(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R10_SHIFT)) & LMEM_PSCRMR_R10_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8349 | #define LMEM_PSCRMR_R9_MASK (0x3000U) |
AnnaBridge | 171:3a7713b1edbc | 8350 | #define LMEM_PSCRMR_R9_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 8351 | #define LMEM_PSCRMR_R9(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R9_SHIFT)) & LMEM_PSCRMR_R9_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8352 | #define LMEM_PSCRMR_R8_MASK (0xC000U) |
AnnaBridge | 171:3a7713b1edbc | 8353 | #define LMEM_PSCRMR_R8_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 8354 | #define LMEM_PSCRMR_R8(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R8_SHIFT)) & LMEM_PSCRMR_R8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8355 | #define LMEM_PSCRMR_R7_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 8356 | #define LMEM_PSCRMR_R7_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 8357 | #define LMEM_PSCRMR_R7(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R7_SHIFT)) & LMEM_PSCRMR_R7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8358 | #define LMEM_PSCRMR_R6_MASK (0xC0000U) |
AnnaBridge | 171:3a7713b1edbc | 8359 | #define LMEM_PSCRMR_R6_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 8360 | #define LMEM_PSCRMR_R6(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R6_SHIFT)) & LMEM_PSCRMR_R6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8361 | #define LMEM_PSCRMR_R5_MASK (0x300000U) |
AnnaBridge | 171:3a7713b1edbc | 8362 | #define LMEM_PSCRMR_R5_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 8363 | #define LMEM_PSCRMR_R5(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R5_SHIFT)) & LMEM_PSCRMR_R5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8364 | #define LMEM_PSCRMR_R4_MASK (0xC00000U) |
AnnaBridge | 171:3a7713b1edbc | 8365 | #define LMEM_PSCRMR_R4_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 8366 | #define LMEM_PSCRMR_R4(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R4_SHIFT)) & LMEM_PSCRMR_R4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8367 | #define LMEM_PSCRMR_R3_MASK (0x3000000U) |
AnnaBridge | 171:3a7713b1edbc | 8368 | #define LMEM_PSCRMR_R3_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 8369 | #define LMEM_PSCRMR_R3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R3_SHIFT)) & LMEM_PSCRMR_R3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8370 | #define LMEM_PSCRMR_R2_MASK (0xC000000U) |
AnnaBridge | 171:3a7713b1edbc | 8371 | #define LMEM_PSCRMR_R2_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 8372 | #define LMEM_PSCRMR_R2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R2_SHIFT)) & LMEM_PSCRMR_R2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8373 | #define LMEM_PSCRMR_R1_MASK (0x30000000U) |
AnnaBridge | 171:3a7713b1edbc | 8374 | #define LMEM_PSCRMR_R1_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 8375 | #define LMEM_PSCRMR_R1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R1_SHIFT)) & LMEM_PSCRMR_R1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8376 | #define LMEM_PSCRMR_R0_MASK (0xC0000000U) |
AnnaBridge | 171:3a7713b1edbc | 8377 | #define LMEM_PSCRMR_R0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 8378 | #define LMEM_PSCRMR_R0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R0_SHIFT)) & LMEM_PSCRMR_R0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8379 | |
AnnaBridge | 171:3a7713b1edbc | 8380 | |
AnnaBridge | 171:3a7713b1edbc | 8381 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8382 | * @} |
AnnaBridge | 171:3a7713b1edbc | 8383 | */ /* end of group LMEM_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 8384 | |
AnnaBridge | 171:3a7713b1edbc | 8385 | |
AnnaBridge | 171:3a7713b1edbc | 8386 | /* LMEM - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 8387 | /** Peripheral LMEM base address */ |
AnnaBridge | 171:3a7713b1edbc | 8388 | #define LMEM_BASE (0xE0082000u) |
AnnaBridge | 171:3a7713b1edbc | 8389 | /** Peripheral LMEM base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 8390 | #define LMEM ((LMEM_Type *)LMEM_BASE) |
AnnaBridge | 171:3a7713b1edbc | 8391 | /** Array initializer of LMEM peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 8392 | #define LMEM_BASE_ADDRS { LMEM_BASE } |
AnnaBridge | 171:3a7713b1edbc | 8393 | /** Array initializer of LMEM peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 8394 | #define LMEM_BASE_PTRS { LMEM } |
AnnaBridge | 171:3a7713b1edbc | 8395 | |
AnnaBridge | 171:3a7713b1edbc | 8396 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8397 | * @} |
AnnaBridge | 171:3a7713b1edbc | 8398 | */ /* end of group LMEM_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 8399 | |
AnnaBridge | 171:3a7713b1edbc | 8400 | |
AnnaBridge | 171:3a7713b1edbc | 8401 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 8402 | -- LPTMR Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 8403 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 8404 | |
AnnaBridge | 171:3a7713b1edbc | 8405 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8406 | * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 8407 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 8408 | */ |
AnnaBridge | 171:3a7713b1edbc | 8409 | |
AnnaBridge | 171:3a7713b1edbc | 8410 | /** LPTMR - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 8411 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 8412 | __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 8413 | __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8414 | __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 8415 | __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 8416 | } LPTMR_Type; |
AnnaBridge | 171:3a7713b1edbc | 8417 | |
AnnaBridge | 171:3a7713b1edbc | 8418 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 8419 | -- LPTMR Register Masks |
AnnaBridge | 171:3a7713b1edbc | 8420 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 8421 | |
AnnaBridge | 171:3a7713b1edbc | 8422 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8423 | * @addtogroup LPTMR_Register_Masks LPTMR Register Masks |
AnnaBridge | 171:3a7713b1edbc | 8424 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 8425 | */ |
AnnaBridge | 171:3a7713b1edbc | 8426 | |
AnnaBridge | 171:3a7713b1edbc | 8427 | /*! @name CSR - Low Power Timer Control Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 8428 | #define LPTMR_CSR_TEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8429 | #define LPTMR_CSR_TEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8430 | #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8431 | #define LPTMR_CSR_TMS_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 8432 | #define LPTMR_CSR_TMS_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 8433 | #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8434 | #define LPTMR_CSR_TFC_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 8435 | #define LPTMR_CSR_TFC_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8436 | #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8437 | #define LPTMR_CSR_TPP_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 8438 | #define LPTMR_CSR_TPP_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 8439 | #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8440 | #define LPTMR_CSR_TPS_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 8441 | #define LPTMR_CSR_TPS_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 8442 | #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8443 | #define LPTMR_CSR_TIE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 8444 | #define LPTMR_CSR_TIE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 8445 | #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8446 | #define LPTMR_CSR_TCF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 8447 | #define LPTMR_CSR_TCF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 8448 | #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8449 | |
AnnaBridge | 171:3a7713b1edbc | 8450 | /*! @name PSR - Low Power Timer Prescale Register */ |
AnnaBridge | 171:3a7713b1edbc | 8451 | #define LPTMR_PSR_PCS_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 8452 | #define LPTMR_PSR_PCS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8453 | #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8454 | #define LPTMR_PSR_PBYP_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 8455 | #define LPTMR_PSR_PBYP_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8456 | #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8457 | #define LPTMR_PSR_PRESCALE_MASK (0x78U) |
AnnaBridge | 171:3a7713b1edbc | 8458 | #define LPTMR_PSR_PRESCALE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 8459 | #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8460 | |
AnnaBridge | 171:3a7713b1edbc | 8461 | /*! @name CMR - Low Power Timer Compare Register */ |
AnnaBridge | 171:3a7713b1edbc | 8462 | #define LPTMR_CMR_COMPARE_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8463 | #define LPTMR_CMR_COMPARE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8464 | #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8465 | |
AnnaBridge | 171:3a7713b1edbc | 8466 | /*! @name CNR - Low Power Timer Counter Register */ |
AnnaBridge | 171:3a7713b1edbc | 8467 | #define LPTMR_CNR_COUNTER_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8468 | #define LPTMR_CNR_COUNTER_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8469 | #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8470 | |
AnnaBridge | 171:3a7713b1edbc | 8471 | |
AnnaBridge | 171:3a7713b1edbc | 8472 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8473 | * @} |
AnnaBridge | 171:3a7713b1edbc | 8474 | */ /* end of group LPTMR_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 8475 | |
AnnaBridge | 171:3a7713b1edbc | 8476 | |
AnnaBridge | 171:3a7713b1edbc | 8477 | /* LPTMR - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 8478 | /** Peripheral LPTMR0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 8479 | #define LPTMR0_BASE (0x40040000u) |
AnnaBridge | 171:3a7713b1edbc | 8480 | /** Peripheral LPTMR0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 8481 | #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 8482 | /** Peripheral LPTMR1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 8483 | #define LPTMR1_BASE (0x40044000u) |
AnnaBridge | 171:3a7713b1edbc | 8484 | /** Peripheral LPTMR1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 8485 | #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) |
AnnaBridge | 171:3a7713b1edbc | 8486 | /** Array initializer of LPTMR peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 8487 | #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } |
AnnaBridge | 171:3a7713b1edbc | 8488 | /** Array initializer of LPTMR peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 8489 | #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } |
AnnaBridge | 171:3a7713b1edbc | 8490 | /** Interrupt vectors for the LPTMR peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 8491 | #define LPTMR_IRQS { LPTMR0_LPTMR1_IRQn, LPTMR0_LPTMR1_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 8492 | |
AnnaBridge | 171:3a7713b1edbc | 8493 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8494 | * @} |
AnnaBridge | 171:3a7713b1edbc | 8495 | */ /* end of group LPTMR_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 8496 | |
AnnaBridge | 171:3a7713b1edbc | 8497 | |
AnnaBridge | 171:3a7713b1edbc | 8498 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 8499 | -- LPUART Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 8500 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 8501 | |
AnnaBridge | 171:3a7713b1edbc | 8502 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8503 | * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 8504 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 8505 | */ |
AnnaBridge | 171:3a7713b1edbc | 8506 | |
AnnaBridge | 171:3a7713b1edbc | 8507 | /** LPUART - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 8508 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 8509 | __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 8510 | __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8511 | __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 8512 | __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 8513 | __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 8514 | __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 8515 | __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 8516 | __IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 8517 | } LPUART_Type; |
AnnaBridge | 171:3a7713b1edbc | 8518 | |
AnnaBridge | 171:3a7713b1edbc | 8519 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 8520 | -- LPUART Register Masks |
AnnaBridge | 171:3a7713b1edbc | 8521 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 8522 | |
AnnaBridge | 171:3a7713b1edbc | 8523 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8524 | * @addtogroup LPUART_Register_Masks LPUART Register Masks |
AnnaBridge | 171:3a7713b1edbc | 8525 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 8526 | */ |
AnnaBridge | 171:3a7713b1edbc | 8527 | |
AnnaBridge | 171:3a7713b1edbc | 8528 | /*! @name BAUD - LPUART Baud Rate Register */ |
AnnaBridge | 171:3a7713b1edbc | 8529 | #define LPUART_BAUD_SBR_MASK (0x1FFFU) |
AnnaBridge | 171:3a7713b1edbc | 8530 | #define LPUART_BAUD_SBR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8531 | #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8532 | #define LPUART_BAUD_SBNS_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 8533 | #define LPUART_BAUD_SBNS_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 8534 | #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8535 | #define LPUART_BAUD_RXEDGIE_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 8536 | #define LPUART_BAUD_RXEDGIE_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 8537 | #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8538 | #define LPUART_BAUD_LBKDIE_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 8539 | #define LPUART_BAUD_LBKDIE_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 8540 | #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8541 | #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 8542 | #define LPUART_BAUD_RESYNCDIS_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 8543 | #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8544 | #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 8545 | #define LPUART_BAUD_BOTHEDGE_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 8546 | #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8547 | #define LPUART_BAUD_MATCFG_MASK (0xC0000U) |
AnnaBridge | 171:3a7713b1edbc | 8548 | #define LPUART_BAUD_MATCFG_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 8549 | #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8550 | #define LPUART_BAUD_RDMAE_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 8551 | #define LPUART_BAUD_RDMAE_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 8552 | #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8553 | #define LPUART_BAUD_TDMAE_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 8554 | #define LPUART_BAUD_TDMAE_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 8555 | #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8556 | #define LPUART_BAUD_OSR_MASK (0x1F000000U) |
AnnaBridge | 171:3a7713b1edbc | 8557 | #define LPUART_BAUD_OSR_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 8558 | #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8559 | #define LPUART_BAUD_M10_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 8560 | #define LPUART_BAUD_M10_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 8561 | #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8562 | #define LPUART_BAUD_MAEN2_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 8563 | #define LPUART_BAUD_MAEN2_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 8564 | #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8565 | #define LPUART_BAUD_MAEN1_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 8566 | #define LPUART_BAUD_MAEN1_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 8567 | #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8568 | |
AnnaBridge | 171:3a7713b1edbc | 8569 | /*! @name STAT - LPUART Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 8570 | #define LPUART_STAT_MA2F_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 8571 | #define LPUART_STAT_MA2F_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 8572 | #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8573 | #define LPUART_STAT_MA1F_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 8574 | #define LPUART_STAT_MA1F_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 8575 | #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8576 | #define LPUART_STAT_PF_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 8577 | #define LPUART_STAT_PF_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 8578 | #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8579 | #define LPUART_STAT_FE_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 8580 | #define LPUART_STAT_FE_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 8581 | #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8582 | #define LPUART_STAT_NF_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 8583 | #define LPUART_STAT_NF_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 8584 | #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8585 | #define LPUART_STAT_OR_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 8586 | #define LPUART_STAT_OR_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 8587 | #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8588 | #define LPUART_STAT_IDLE_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 8589 | #define LPUART_STAT_IDLE_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 8590 | #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8591 | #define LPUART_STAT_RDRF_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 8592 | #define LPUART_STAT_RDRF_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 8593 | #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8594 | #define LPUART_STAT_TC_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 8595 | #define LPUART_STAT_TC_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 8596 | #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8597 | #define LPUART_STAT_TDRE_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 8598 | #define LPUART_STAT_TDRE_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 8599 | #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8600 | #define LPUART_STAT_RAF_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 8601 | #define LPUART_STAT_RAF_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 8602 | #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8603 | #define LPUART_STAT_LBKDE_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 8604 | #define LPUART_STAT_LBKDE_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 8605 | #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8606 | #define LPUART_STAT_BRK13_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 8607 | #define LPUART_STAT_BRK13_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 8608 | #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8609 | #define LPUART_STAT_RWUID_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 8610 | #define LPUART_STAT_RWUID_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 8611 | #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8612 | #define LPUART_STAT_RXINV_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 8613 | #define LPUART_STAT_RXINV_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 8614 | #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8615 | #define LPUART_STAT_MSBF_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 8616 | #define LPUART_STAT_MSBF_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 8617 | #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8618 | #define LPUART_STAT_RXEDGIF_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 8619 | #define LPUART_STAT_RXEDGIF_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 8620 | #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8621 | #define LPUART_STAT_LBKDIF_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 8622 | #define LPUART_STAT_LBKDIF_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 8623 | #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8624 | |
AnnaBridge | 171:3a7713b1edbc | 8625 | /*! @name CTRL - LPUART Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 8626 | #define LPUART_CTRL_PT_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8627 | #define LPUART_CTRL_PT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8628 | #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8629 | #define LPUART_CTRL_PE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 8630 | #define LPUART_CTRL_PE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 8631 | #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8632 | #define LPUART_CTRL_ILT_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 8633 | #define LPUART_CTRL_ILT_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8634 | #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8635 | #define LPUART_CTRL_WAKE_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 8636 | #define LPUART_CTRL_WAKE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 8637 | #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8638 | #define LPUART_CTRL_M_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 8639 | #define LPUART_CTRL_M_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 8640 | #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8641 | #define LPUART_CTRL_RSRC_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 8642 | #define LPUART_CTRL_RSRC_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 8643 | #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8644 | #define LPUART_CTRL_DOZEEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 8645 | #define LPUART_CTRL_DOZEEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 8646 | #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8647 | #define LPUART_CTRL_LOOPS_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 8648 | #define LPUART_CTRL_LOOPS_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 8649 | #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8650 | #define LPUART_CTRL_IDLECFG_MASK (0x700U) |
AnnaBridge | 171:3a7713b1edbc | 8651 | #define LPUART_CTRL_IDLECFG_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 8652 | #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8653 | #define LPUART_CTRL_MA2IE_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 8654 | #define LPUART_CTRL_MA2IE_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 8655 | #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8656 | #define LPUART_CTRL_MA1IE_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 8657 | #define LPUART_CTRL_MA1IE_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 8658 | #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8659 | #define LPUART_CTRL_SBK_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 8660 | #define LPUART_CTRL_SBK_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 8661 | #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8662 | #define LPUART_CTRL_RWU_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 8663 | #define LPUART_CTRL_RWU_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 8664 | #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8665 | #define LPUART_CTRL_RE_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 8666 | #define LPUART_CTRL_RE_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 8667 | #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8668 | #define LPUART_CTRL_TE_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 8669 | #define LPUART_CTRL_TE_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 8670 | #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8671 | #define LPUART_CTRL_ILIE_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 8672 | #define LPUART_CTRL_ILIE_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 8673 | #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8674 | #define LPUART_CTRL_RIE_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 8675 | #define LPUART_CTRL_RIE_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 8676 | #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8677 | #define LPUART_CTRL_TCIE_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 8678 | #define LPUART_CTRL_TCIE_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 8679 | #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8680 | #define LPUART_CTRL_TIE_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 8681 | #define LPUART_CTRL_TIE_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 8682 | #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8683 | #define LPUART_CTRL_PEIE_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 8684 | #define LPUART_CTRL_PEIE_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 8685 | #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8686 | #define LPUART_CTRL_FEIE_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 8687 | #define LPUART_CTRL_FEIE_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 8688 | #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8689 | #define LPUART_CTRL_NEIE_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 8690 | #define LPUART_CTRL_NEIE_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 8691 | #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8692 | #define LPUART_CTRL_ORIE_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 8693 | #define LPUART_CTRL_ORIE_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 8694 | #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8695 | #define LPUART_CTRL_TXINV_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 8696 | #define LPUART_CTRL_TXINV_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 8697 | #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8698 | #define LPUART_CTRL_TXDIR_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 8699 | #define LPUART_CTRL_TXDIR_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 8700 | #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8701 | #define LPUART_CTRL_R9T8_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 8702 | #define LPUART_CTRL_R9T8_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 8703 | #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8704 | #define LPUART_CTRL_R8T9_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 8705 | #define LPUART_CTRL_R8T9_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 8706 | #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8707 | |
AnnaBridge | 171:3a7713b1edbc | 8708 | /*! @name DATA - LPUART Data Register */ |
AnnaBridge | 171:3a7713b1edbc | 8709 | #define LPUART_DATA_R0T0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8710 | #define LPUART_DATA_R0T0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8711 | #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8712 | #define LPUART_DATA_R1T1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 8713 | #define LPUART_DATA_R1T1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 8714 | #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8715 | #define LPUART_DATA_R2T2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 8716 | #define LPUART_DATA_R2T2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8717 | #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8718 | #define LPUART_DATA_R3T3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 8719 | #define LPUART_DATA_R3T3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 8720 | #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8721 | #define LPUART_DATA_R4T4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 8722 | #define LPUART_DATA_R4T4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 8723 | #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8724 | #define LPUART_DATA_R5T5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 8725 | #define LPUART_DATA_R5T5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 8726 | #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8727 | #define LPUART_DATA_R6T6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 8728 | #define LPUART_DATA_R6T6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 8729 | #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8730 | #define LPUART_DATA_R7T7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 8731 | #define LPUART_DATA_R7T7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 8732 | #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8733 | #define LPUART_DATA_R8T8_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 8734 | #define LPUART_DATA_R8T8_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 8735 | #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8736 | #define LPUART_DATA_R9T9_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 8737 | #define LPUART_DATA_R9T9_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 8738 | #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8739 | #define LPUART_DATA_IDLINE_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 8740 | #define LPUART_DATA_IDLINE_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 8741 | #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8742 | #define LPUART_DATA_RXEMPT_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 8743 | #define LPUART_DATA_RXEMPT_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 8744 | #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8745 | #define LPUART_DATA_FRETSC_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 8746 | #define LPUART_DATA_FRETSC_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 8747 | #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8748 | #define LPUART_DATA_PARITYE_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 8749 | #define LPUART_DATA_PARITYE_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 8750 | #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8751 | #define LPUART_DATA_NOISY_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 8752 | #define LPUART_DATA_NOISY_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 8753 | #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8754 | |
AnnaBridge | 171:3a7713b1edbc | 8755 | /*! @name MATCH - LPUART Match Address Register */ |
AnnaBridge | 171:3a7713b1edbc | 8756 | #define LPUART_MATCH_MA1_MASK (0x3FFU) |
AnnaBridge | 171:3a7713b1edbc | 8757 | #define LPUART_MATCH_MA1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8758 | #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8759 | #define LPUART_MATCH_MA2_MASK (0x3FF0000U) |
AnnaBridge | 171:3a7713b1edbc | 8760 | #define LPUART_MATCH_MA2_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 8761 | #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8762 | |
AnnaBridge | 171:3a7713b1edbc | 8763 | /*! @name MODIR - LPUART Modem IrDA Register */ |
AnnaBridge | 171:3a7713b1edbc | 8764 | #define LPUART_MODIR_TXCTSE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8765 | #define LPUART_MODIR_TXCTSE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8766 | #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8767 | #define LPUART_MODIR_TXRTSE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 8768 | #define LPUART_MODIR_TXRTSE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 8769 | #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8770 | #define LPUART_MODIR_TXRTSPOL_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 8771 | #define LPUART_MODIR_TXRTSPOL_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8772 | #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8773 | #define LPUART_MODIR_RXRTSE_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 8774 | #define LPUART_MODIR_RXRTSE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 8775 | #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8776 | #define LPUART_MODIR_TXCTSC_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 8777 | #define LPUART_MODIR_TXCTSC_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 8778 | #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8779 | #define LPUART_MODIR_TXCTSSRC_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 8780 | #define LPUART_MODIR_TXCTSSRC_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 8781 | #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8782 | #define LPUART_MODIR_RTSWATER_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 8783 | #define LPUART_MODIR_RTSWATER_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 8784 | #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8785 | #define LPUART_MODIR_TNP_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 8786 | #define LPUART_MODIR_TNP_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 8787 | #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8788 | #define LPUART_MODIR_IREN_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 8789 | #define LPUART_MODIR_IREN_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 8790 | #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8791 | |
AnnaBridge | 171:3a7713b1edbc | 8792 | /*! @name FIFO - LPUART FIFO Register */ |
AnnaBridge | 171:3a7713b1edbc | 8793 | #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 8794 | #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8795 | #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8796 | #define LPUART_FIFO_RXFE_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 8797 | #define LPUART_FIFO_RXFE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 8798 | #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8799 | #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) |
AnnaBridge | 171:3a7713b1edbc | 8800 | #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 8801 | #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8802 | #define LPUART_FIFO_TXFE_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 8803 | #define LPUART_FIFO_TXFE_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 8804 | #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8805 | #define LPUART_FIFO_RXUFE_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 8806 | #define LPUART_FIFO_RXUFE_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 8807 | #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8808 | #define LPUART_FIFO_TXOFE_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 8809 | #define LPUART_FIFO_TXOFE_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 8810 | #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8811 | #define LPUART_FIFO_RXIDEN_MASK (0x1C00U) |
AnnaBridge | 171:3a7713b1edbc | 8812 | #define LPUART_FIFO_RXIDEN_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 8813 | #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8814 | #define LPUART_FIFO_RXFLUSH_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 8815 | #define LPUART_FIFO_RXFLUSH_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 8816 | #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8817 | #define LPUART_FIFO_TXFLUSH_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 8818 | #define LPUART_FIFO_TXFLUSH_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 8819 | #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8820 | #define LPUART_FIFO_RXUF_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 8821 | #define LPUART_FIFO_RXUF_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 8822 | #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8823 | #define LPUART_FIFO_TXOF_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 8824 | #define LPUART_FIFO_TXOF_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 8825 | #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8826 | #define LPUART_FIFO_RXEMPT_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 8827 | #define LPUART_FIFO_RXEMPT_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 8828 | #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8829 | #define LPUART_FIFO_TXEMPT_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 8830 | #define LPUART_FIFO_TXEMPT_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 8831 | #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8832 | |
AnnaBridge | 171:3a7713b1edbc | 8833 | /*! @name WATER - LPUART Watermark Register */ |
AnnaBridge | 171:3a7713b1edbc | 8834 | #define LPUART_WATER_TXWATER_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 8835 | #define LPUART_WATER_TXWATER_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8836 | #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8837 | #define LPUART_WATER_TXCOUNT_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 8838 | #define LPUART_WATER_TXCOUNT_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 8839 | #define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8840 | #define LPUART_WATER_RXWATER_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 8841 | #define LPUART_WATER_RXWATER_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 8842 | #define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8843 | #define LPUART_WATER_RXCOUNT_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 8844 | #define LPUART_WATER_RXCOUNT_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 8845 | #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8846 | |
AnnaBridge | 171:3a7713b1edbc | 8847 | |
AnnaBridge | 171:3a7713b1edbc | 8848 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8849 | * @} |
AnnaBridge | 171:3a7713b1edbc | 8850 | */ /* end of group LPUART_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 8851 | |
AnnaBridge | 171:3a7713b1edbc | 8852 | |
AnnaBridge | 171:3a7713b1edbc | 8853 | /* LPUART - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 8854 | /** Peripheral LPUART0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 8855 | #define LPUART0_BASE (0x400C4000u) |
AnnaBridge | 171:3a7713b1edbc | 8856 | /** Peripheral LPUART0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 8857 | #define LPUART0 ((LPUART_Type *)LPUART0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 8858 | /** Peripheral LPUART1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 8859 | #define LPUART1_BASE (0x400C5000u) |
AnnaBridge | 171:3a7713b1edbc | 8860 | /** Peripheral LPUART1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 8861 | #define LPUART1 ((LPUART_Type *)LPUART1_BASE) |
AnnaBridge | 171:3a7713b1edbc | 8862 | /** Peripheral LPUART2 base address */ |
AnnaBridge | 171:3a7713b1edbc | 8863 | #define LPUART2_BASE (0x400C6000u) |
AnnaBridge | 171:3a7713b1edbc | 8864 | /** Peripheral LPUART2 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 8865 | #define LPUART2 ((LPUART_Type *)LPUART2_BASE) |
AnnaBridge | 171:3a7713b1edbc | 8866 | /** Peripheral LPUART3 base address */ |
AnnaBridge | 171:3a7713b1edbc | 8867 | #define LPUART3_BASE (0x400C7000u) |
AnnaBridge | 171:3a7713b1edbc | 8868 | /** Peripheral LPUART3 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 8869 | #define LPUART3 ((LPUART_Type *)LPUART3_BASE) |
AnnaBridge | 171:3a7713b1edbc | 8870 | /** Peripheral LPUART4 base address */ |
AnnaBridge | 171:3a7713b1edbc | 8871 | #define LPUART4_BASE (0x400D6000u) |
AnnaBridge | 171:3a7713b1edbc | 8872 | /** Peripheral LPUART4 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 8873 | #define LPUART4 ((LPUART_Type *)LPUART4_BASE) |
AnnaBridge | 171:3a7713b1edbc | 8874 | /** Array initializer of LPUART peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 8875 | #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE } |
AnnaBridge | 171:3a7713b1edbc | 8876 | /** Array initializer of LPUART peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 8877 | #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4 } |
AnnaBridge | 171:3a7713b1edbc | 8878 | /** Interrupt vectors for the LPUART peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 8879 | #define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 8880 | #define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 8881 | |
AnnaBridge | 171:3a7713b1edbc | 8882 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8883 | * @} |
AnnaBridge | 171:3a7713b1edbc | 8884 | */ /* end of group LPUART_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 8885 | |
AnnaBridge | 171:3a7713b1edbc | 8886 | |
AnnaBridge | 171:3a7713b1edbc | 8887 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 8888 | -- LTC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 8889 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 8890 | |
AnnaBridge | 171:3a7713b1edbc | 8891 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8892 | * @addtogroup LTC_Peripheral_Access_Layer LTC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 8893 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 8894 | */ |
AnnaBridge | 171:3a7713b1edbc | 8895 | |
AnnaBridge | 171:3a7713b1edbc | 8896 | /** LTC - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 8897 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 8898 | union { /* offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 8899 | __IO uint32_t MD; /**< LTC Mode Register (non-PKHA/non-RNG use), offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 8900 | __IO uint32_t MDPK; /**< LTC Mode Register (PublicKey), offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 8901 | }; |
AnnaBridge | 171:3a7713b1edbc | 8902 | uint8_t RESERVED_0[4]; |
AnnaBridge | 171:3a7713b1edbc | 8903 | __IO uint32_t KS; /**< LTC Key Size Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 8904 | uint8_t RESERVED_1[4]; |
AnnaBridge | 171:3a7713b1edbc | 8905 | __IO uint32_t DS; /**< LTC Data Size Register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 8906 | uint8_t RESERVED_2[4]; |
AnnaBridge | 171:3a7713b1edbc | 8907 | __IO uint32_t ICVS; /**< LTC ICV Size Register, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 8908 | uint8_t RESERVED_3[20]; |
AnnaBridge | 171:3a7713b1edbc | 8909 | __IO uint32_t COM; /**< LTC Command Register, offset: 0x30 */ |
AnnaBridge | 171:3a7713b1edbc | 8910 | __IO uint32_t CTL; /**< LTC Control Register, offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 8911 | uint8_t RESERVED_4[8]; |
AnnaBridge | 171:3a7713b1edbc | 8912 | __IO uint32_t CW; /**< LTC Clear Written Register, offset: 0x40 */ |
AnnaBridge | 171:3a7713b1edbc | 8913 | uint8_t RESERVED_5[4]; |
AnnaBridge | 171:3a7713b1edbc | 8914 | __IO uint32_t STA; /**< LTC Status Register, offset: 0x48 */ |
AnnaBridge | 171:3a7713b1edbc | 8915 | __I uint32_t ESTA; /**< LTC Error Status Register, offset: 0x4C */ |
AnnaBridge | 171:3a7713b1edbc | 8916 | uint8_t RESERVED_6[8]; |
AnnaBridge | 171:3a7713b1edbc | 8917 | __IO uint32_t AADSZ; /**< LTC AAD Size Register, offset: 0x58 */ |
AnnaBridge | 171:3a7713b1edbc | 8918 | uint8_t RESERVED_7[4]; |
AnnaBridge | 171:3a7713b1edbc | 8919 | __IO uint32_t IVSZ; /**< LTC IV Size Register, offset: 0x60 */ |
AnnaBridge | 171:3a7713b1edbc | 8920 | uint8_t RESERVED_8[4]; |
AnnaBridge | 171:3a7713b1edbc | 8921 | __O uint32_t DPAMS; /**< LTC DPA Mask Seed Register, offset: 0x68 */ |
AnnaBridge | 171:3a7713b1edbc | 8922 | uint8_t RESERVED_9[20]; |
AnnaBridge | 171:3a7713b1edbc | 8923 | __IO uint32_t PKASZ; /**< LTC PKHA A Size Register, offset: 0x80 */ |
AnnaBridge | 171:3a7713b1edbc | 8924 | uint8_t RESERVED_10[4]; |
AnnaBridge | 171:3a7713b1edbc | 8925 | __IO uint32_t PKBSZ; /**< LTC PKHA B Size Register, offset: 0x88 */ |
AnnaBridge | 171:3a7713b1edbc | 8926 | uint8_t RESERVED_11[4]; |
AnnaBridge | 171:3a7713b1edbc | 8927 | __IO uint32_t PKNSZ; /**< LTC PKHA N Size Register, offset: 0x90 */ |
AnnaBridge | 171:3a7713b1edbc | 8928 | uint8_t RESERVED_12[4]; |
AnnaBridge | 171:3a7713b1edbc | 8929 | __IO uint32_t PKESZ; /**< LTC PKHA E Size Register, offset: 0x98 */ |
AnnaBridge | 171:3a7713b1edbc | 8930 | uint8_t RESERVED_13[100]; |
AnnaBridge | 171:3a7713b1edbc | 8931 | __IO uint32_t CTX[16]; /**< LTC Context Register, array offset: 0x100, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8932 | uint8_t RESERVED_14[192]; |
AnnaBridge | 171:3a7713b1edbc | 8933 | __IO uint32_t KEY[8]; /**< LTC Key Registers, array offset: 0x200, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8934 | uint8_t RESERVED_15[720]; |
AnnaBridge | 171:3a7713b1edbc | 8935 | __I uint32_t VID1; /**< LTC Version ID Register, offset: 0x4F0 */ |
AnnaBridge | 171:3a7713b1edbc | 8936 | uint8_t RESERVED_16[4]; |
AnnaBridge | 171:3a7713b1edbc | 8937 | __I uint32_t CHAVID; /**< LTC CHA Version ID Register, offset: 0x4F8 */ |
AnnaBridge | 171:3a7713b1edbc | 8938 | uint8_t RESERVED_17[708]; |
AnnaBridge | 171:3a7713b1edbc | 8939 | __I uint32_t FIFOSTA; /**< LTC FIFO Status Register, offset: 0x7C0 */ |
AnnaBridge | 171:3a7713b1edbc | 8940 | uint8_t RESERVED_18[28]; |
AnnaBridge | 171:3a7713b1edbc | 8941 | __O uint32_t IFIFO; /**< LTC Input Data FIFO, offset: 0x7E0 */ |
AnnaBridge | 171:3a7713b1edbc | 8942 | uint8_t RESERVED_19[12]; |
AnnaBridge | 171:3a7713b1edbc | 8943 | __I uint32_t OFIFO; /**< LTC Output Data FIFO, offset: 0x7F0 */ |
AnnaBridge | 171:3a7713b1edbc | 8944 | uint8_t RESERVED_20[12]; |
AnnaBridge | 171:3a7713b1edbc | 8945 | union { /* offset: 0x800 */ |
AnnaBridge | 171:3a7713b1edbc | 8946 | __IO uint32_t PKA[64]; /**< LTC PKHA A 0 Register..LTC PKHA A 63 Register, array offset: 0x800, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8947 | struct { /* offset: 0x800 */ |
AnnaBridge | 171:3a7713b1edbc | 8948 | __IO uint32_t PKA0[16]; /**< LTC PKHA A0 0 Register..LTC PKHA A0 15 Register, array offset: 0x800, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8949 | __IO uint32_t PKA1[16]; /**< LTC PKHA A1 0 Register..LTC PKHA A1 15 Register, array offset: 0x840, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8950 | __IO uint32_t PKA2[16]; /**< LTC PKHA A2 0 Register..LTC PKHA A2 15 Register, array offset: 0x880, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8951 | __IO uint32_t PKA3[16]; /**< LTC PKHA A3 0 Register..LTC PKHA A3 15 Register, array offset: 0x8C0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8952 | } PKA_SHORT; |
AnnaBridge | 171:3a7713b1edbc | 8953 | }; |
AnnaBridge | 171:3a7713b1edbc | 8954 | uint8_t RESERVED_21[256]; |
AnnaBridge | 171:3a7713b1edbc | 8955 | union { /* offset: 0xA00 */ |
AnnaBridge | 171:3a7713b1edbc | 8956 | __IO uint32_t PKB[64]; /**< LTC PKHA B 0 Register..LTC PKHA B 63 Register, array offset: 0xA00, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8957 | struct { /* offset: 0xA00 */ |
AnnaBridge | 171:3a7713b1edbc | 8958 | __IO uint32_t PKB0[16]; /**< LTC PKHA B0 0 Register..LTC PKHA B0 15 Register, array offset: 0xA00, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8959 | __IO uint32_t PKB1[16]; /**< LTC PKHA B1 0 Register..LTC PKHA B1 15 Register, array offset: 0xA40, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8960 | __IO uint32_t PKB2[16]; /**< LTC PKHA B2 0 Register..LTC PKHA B2 15 Register, array offset: 0xA80, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8961 | __IO uint32_t PKB3[16]; /**< LTC PKHA B3 0 Register..LTC PKHA B3 15 Register, array offset: 0xAC0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8962 | } PKB_SHORT; |
AnnaBridge | 171:3a7713b1edbc | 8963 | }; |
AnnaBridge | 171:3a7713b1edbc | 8964 | uint8_t RESERVED_22[256]; |
AnnaBridge | 171:3a7713b1edbc | 8965 | union { /* offset: 0xC00 */ |
AnnaBridge | 171:3a7713b1edbc | 8966 | __IO uint32_t PKN[64]; /**< LTC PKHA N 0 Register..LTC PKHA N 63 Register, array offset: 0xC00, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8967 | struct { /* offset: 0xC00 */ |
AnnaBridge | 171:3a7713b1edbc | 8968 | __IO uint32_t PKN0[16]; /**< LTC PKHA N0 0 Register..LTC PKHA N0 15 Register, array offset: 0xC00, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8969 | __IO uint32_t PKN1[16]; /**< LTC PKHA N1 0 Register..LTC PKHA N1 15 Register, array offset: 0xC40, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8970 | __IO uint32_t PKN2[16]; /**< LTC PKHA N2 0 Register..LTC PKHA N2 15 Register, array offset: 0xC80, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8971 | __IO uint32_t PKN3[16]; /**< LTC PKHA N3 0 Register..LTC PKHA N3 15 Register, array offset: 0xCC0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8972 | } PKN_SHORT; |
AnnaBridge | 171:3a7713b1edbc | 8973 | }; |
AnnaBridge | 171:3a7713b1edbc | 8974 | uint8_t RESERVED_23[256]; |
AnnaBridge | 171:3a7713b1edbc | 8975 | union { /* offset: 0xE00 */ |
AnnaBridge | 171:3a7713b1edbc | 8976 | __IO uint32_t PKE[64]; /**< LTC PKHA E 0 Register..LTC PKHA E 63 Register, array offset: 0xE00, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8977 | struct { /* offset: 0xE00 */ |
AnnaBridge | 171:3a7713b1edbc | 8978 | __IO uint32_t PKE0[16]; /**< LTC PKHA E0 0 Register..LTC PKHA E0 15 Register, array offset: 0xE00, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8979 | __IO uint32_t PKE1[16]; /**< LTC PKHA E1 0 Register..LTC PKHA E1 15 Register, array offset: 0xE40, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8980 | __IO uint32_t PKE2[16]; /**< LTC PKHA E2 0 Register..LTC PKHA E2 15 Register, array offset: 0xE80, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8981 | __IO uint32_t PKE3[16]; /**< LTC PKHA E3 0 Register..LTC PKHA E3 15 Register, array offset: 0xEC0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8982 | } PKE_SHORT; |
AnnaBridge | 171:3a7713b1edbc | 8983 | }; |
AnnaBridge | 171:3a7713b1edbc | 8984 | } LTC_Type; |
AnnaBridge | 171:3a7713b1edbc | 8985 | |
AnnaBridge | 171:3a7713b1edbc | 8986 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 8987 | -- LTC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 8988 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 8989 | |
AnnaBridge | 171:3a7713b1edbc | 8990 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8991 | * @addtogroup LTC_Register_Masks LTC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 8992 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 8993 | */ |
AnnaBridge | 171:3a7713b1edbc | 8994 | |
AnnaBridge | 171:3a7713b1edbc | 8995 | /*! @name MD - LTC Mode Register (non-PKHA/non-RNG use) */ |
AnnaBridge | 171:3a7713b1edbc | 8996 | #define LTC_MD_ENC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8997 | #define LTC_MD_ENC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8998 | #define LTC_MD_ENC(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_ENC_SHIFT)) & LTC_MD_ENC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8999 | #define LTC_MD_ICV_TEST_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 9000 | #define LTC_MD_ICV_TEST_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9001 | #define LTC_MD_ICV_TEST(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_ICV_TEST_SHIFT)) & LTC_MD_ICV_TEST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9002 | #define LTC_MD_AS_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 9003 | #define LTC_MD_AS_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 9004 | #define LTC_MD_AS(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_AS_SHIFT)) & LTC_MD_AS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9005 | #define LTC_MD_AAI_MASK (0x1FF0U) |
AnnaBridge | 171:3a7713b1edbc | 9006 | #define LTC_MD_AAI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 9007 | #define LTC_MD_AAI(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_AAI_SHIFT)) & LTC_MD_AAI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9008 | #define LTC_MD_ALG_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 9009 | #define LTC_MD_ALG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9010 | #define LTC_MD_ALG(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_ALG_SHIFT)) & LTC_MD_ALG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9011 | |
AnnaBridge | 171:3a7713b1edbc | 9012 | /*! @name MDPK - LTC Mode Register (PublicKey) */ |
AnnaBridge | 171:3a7713b1edbc | 9013 | #define LTC_MDPK_PKHA_MODE_LS_MASK (0xFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9014 | #define LTC_MDPK_PKHA_MODE_LS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9015 | #define LTC_MDPK_PKHA_MODE_LS(x) (((uint32_t)(((uint32_t)(x)) << LTC_MDPK_PKHA_MODE_LS_SHIFT)) & LTC_MDPK_PKHA_MODE_LS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9016 | #define LTC_MDPK_PKHA_MODE_MS_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 9017 | #define LTC_MDPK_PKHA_MODE_MS_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9018 | #define LTC_MDPK_PKHA_MODE_MS(x) (((uint32_t)(((uint32_t)(x)) << LTC_MDPK_PKHA_MODE_MS_SHIFT)) & LTC_MDPK_PKHA_MODE_MS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9019 | #define LTC_MDPK_ALG_MASK (0xF00000U) |
AnnaBridge | 171:3a7713b1edbc | 9020 | #define LTC_MDPK_ALG_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 9021 | #define LTC_MDPK_ALG(x) (((uint32_t)(((uint32_t)(x)) << LTC_MDPK_ALG_SHIFT)) & LTC_MDPK_ALG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9022 | |
AnnaBridge | 171:3a7713b1edbc | 9023 | /*! @name KS - LTC Key Size Register */ |
AnnaBridge | 171:3a7713b1edbc | 9024 | #define LTC_KS_KS_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 9025 | #define LTC_KS_KS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9026 | #define LTC_KS_KS(x) (((uint32_t)(((uint32_t)(x)) << LTC_KS_KS_SHIFT)) & LTC_KS_KS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9027 | |
AnnaBridge | 171:3a7713b1edbc | 9028 | /*! @name DS - LTC Data Size Register */ |
AnnaBridge | 171:3a7713b1edbc | 9029 | #define LTC_DS_DS_MASK (0xFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9030 | #define LTC_DS_DS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9031 | #define LTC_DS_DS(x) (((uint32_t)(((uint32_t)(x)) << LTC_DS_DS_SHIFT)) & LTC_DS_DS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9032 | |
AnnaBridge | 171:3a7713b1edbc | 9033 | /*! @name ICVS - LTC ICV Size Register */ |
AnnaBridge | 171:3a7713b1edbc | 9034 | #define LTC_ICVS_ICVS_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 9035 | #define LTC_ICVS_ICVS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9036 | #define LTC_ICVS_ICVS(x) (((uint32_t)(((uint32_t)(x)) << LTC_ICVS_ICVS_SHIFT)) & LTC_ICVS_ICVS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9037 | |
AnnaBridge | 171:3a7713b1edbc | 9038 | /*! @name COM - LTC Command Register */ |
AnnaBridge | 171:3a7713b1edbc | 9039 | #define LTC_COM_ALL_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9040 | #define LTC_COM_ALL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9041 | #define LTC_COM_ALL(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_ALL_SHIFT)) & LTC_COM_ALL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9042 | #define LTC_COM_AES_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 9043 | #define LTC_COM_AES_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9044 | #define LTC_COM_AES(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_AES_SHIFT)) & LTC_COM_AES_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9045 | #define LTC_COM_DES_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 9046 | #define LTC_COM_DES_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 9047 | #define LTC_COM_DES(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_DES_SHIFT)) & LTC_COM_DES_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9048 | #define LTC_COM_PK_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 9049 | #define LTC_COM_PK_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 9050 | #define LTC_COM_PK(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_PK_SHIFT)) & LTC_COM_PK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9051 | |
AnnaBridge | 171:3a7713b1edbc | 9052 | /*! @name CTL - LTC Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 9053 | #define LTC_CTL_IM_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9054 | #define LTC_CTL_IM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9055 | #define LTC_CTL_IM(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IM_SHIFT)) & LTC_CTL_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9056 | #define LTC_CTL_PDE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 9057 | #define LTC_CTL_PDE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 9058 | #define LTC_CTL_PDE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_PDE_SHIFT)) & LTC_CTL_PDE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9059 | #define LTC_CTL_IFE_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 9060 | #define LTC_CTL_IFE_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 9061 | #define LTC_CTL_IFE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFE_SHIFT)) & LTC_CTL_IFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9062 | #define LTC_CTL_IFR_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 9063 | #define LTC_CTL_IFR_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 9064 | #define LTC_CTL_IFR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFR_SHIFT)) & LTC_CTL_IFR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9065 | #define LTC_CTL_OFE_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 9066 | #define LTC_CTL_OFE_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 9067 | #define LTC_CTL_OFE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFE_SHIFT)) & LTC_CTL_OFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9068 | #define LTC_CTL_OFR_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 9069 | #define LTC_CTL_OFR_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 9070 | #define LTC_CTL_OFR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFR_SHIFT)) & LTC_CTL_OFR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9071 | #define LTC_CTL_IFS_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 9072 | #define LTC_CTL_IFS_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9073 | #define LTC_CTL_IFS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFS_SHIFT)) & LTC_CTL_IFS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9074 | #define LTC_CTL_OFS_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 9075 | #define LTC_CTL_OFS_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 9076 | #define LTC_CTL_OFS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFS_SHIFT)) & LTC_CTL_OFS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9077 | #define LTC_CTL_KIS_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 9078 | #define LTC_CTL_KIS_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 9079 | #define LTC_CTL_KIS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KIS_SHIFT)) & LTC_CTL_KIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9080 | #define LTC_CTL_KOS_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 9081 | #define LTC_CTL_KOS_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 9082 | #define LTC_CTL_KOS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KOS_SHIFT)) & LTC_CTL_KOS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9083 | #define LTC_CTL_CIS_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 9084 | #define LTC_CTL_CIS_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 9085 | #define LTC_CTL_CIS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_CIS_SHIFT)) & LTC_CTL_CIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9086 | #define LTC_CTL_COS_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 9087 | #define LTC_CTL_COS_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 9088 | #define LTC_CTL_COS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_COS_SHIFT)) & LTC_CTL_COS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9089 | #define LTC_CTL_KAL_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 9090 | #define LTC_CTL_KAL_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 9091 | #define LTC_CTL_KAL(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KAL_SHIFT)) & LTC_CTL_KAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9092 | |
AnnaBridge | 171:3a7713b1edbc | 9093 | /*! @name CW - LTC Clear Written Register */ |
AnnaBridge | 171:3a7713b1edbc | 9094 | #define LTC_CW_CM_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9095 | #define LTC_CW_CM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9096 | #define LTC_CW_CM(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CM_SHIFT)) & LTC_CW_CM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9097 | #define LTC_CW_CDS_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 9098 | #define LTC_CW_CDS_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 9099 | #define LTC_CW_CDS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CDS_SHIFT)) & LTC_CW_CDS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9100 | #define LTC_CW_CICV_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 9101 | #define LTC_CW_CICV_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 9102 | #define LTC_CW_CICV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CICV_SHIFT)) & LTC_CW_CICV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9103 | #define LTC_CW_CCR_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 9104 | #define LTC_CW_CCR_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9105 | #define LTC_CW_CCR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CCR_SHIFT)) & LTC_CW_CCR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9106 | #define LTC_CW_CKR_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 9107 | #define LTC_CW_CKR_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 9108 | #define LTC_CW_CKR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CKR_SHIFT)) & LTC_CW_CKR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9109 | #define LTC_CW_CPKA_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 9110 | #define LTC_CW_CPKA_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 9111 | #define LTC_CW_CPKA(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CPKA_SHIFT)) & LTC_CW_CPKA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9112 | #define LTC_CW_CPKB_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 9113 | #define LTC_CW_CPKB_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 9114 | #define LTC_CW_CPKB(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CPKB_SHIFT)) & LTC_CW_CPKB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9115 | #define LTC_CW_CPKN_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 9116 | #define LTC_CW_CPKN_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 9117 | #define LTC_CW_CPKN(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CPKN_SHIFT)) & LTC_CW_CPKN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9118 | #define LTC_CW_CPKE_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 9119 | #define LTC_CW_CPKE_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 9120 | #define LTC_CW_CPKE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CPKE_SHIFT)) & LTC_CW_CPKE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9121 | #define LTC_CW_COF_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 9122 | #define LTC_CW_COF_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 9123 | #define LTC_CW_COF(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_COF_SHIFT)) & LTC_CW_COF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9124 | #define LTC_CW_CIF_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 9125 | #define LTC_CW_CIF_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 9126 | #define LTC_CW_CIF(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CIF_SHIFT)) & LTC_CW_CIF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9127 | |
AnnaBridge | 171:3a7713b1edbc | 9128 | /*! @name STA - LTC Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 9129 | #define LTC_STA_AB_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 9130 | #define LTC_STA_AB_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9131 | #define LTC_STA_AB(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_AB_SHIFT)) & LTC_STA_AB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9132 | #define LTC_STA_DB_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 9133 | #define LTC_STA_DB_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 9134 | #define LTC_STA_DB(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_DB_SHIFT)) & LTC_STA_DB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9135 | #define LTC_STA_PB_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 9136 | #define LTC_STA_PB_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 9137 | #define LTC_STA_PB(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_PB_SHIFT)) & LTC_STA_PB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9138 | #define LTC_STA_DI_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 9139 | #define LTC_STA_DI_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9140 | #define LTC_STA_DI(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_DI_SHIFT)) & LTC_STA_DI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9141 | #define LTC_STA_EI_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 9142 | #define LTC_STA_EI_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 9143 | #define LTC_STA_EI(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_EI_SHIFT)) & LTC_STA_EI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9144 | #define LTC_STA_PKP_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 9145 | #define LTC_STA_PKP_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 9146 | #define LTC_STA_PKP(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_PKP_SHIFT)) & LTC_STA_PKP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9147 | #define LTC_STA_PKO_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 9148 | #define LTC_STA_PKO_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 9149 | #define LTC_STA_PKO(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_PKO_SHIFT)) & LTC_STA_PKO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9150 | #define LTC_STA_PKZ_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 9151 | #define LTC_STA_PKZ_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 9152 | #define LTC_STA_PKZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_PKZ_SHIFT)) & LTC_STA_PKZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9153 | |
AnnaBridge | 171:3a7713b1edbc | 9154 | /*! @name ESTA - LTC Error Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 9155 | #define LTC_ESTA_ERRID1_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 9156 | #define LTC_ESTA_ERRID1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9157 | #define LTC_ESTA_ERRID1(x) (((uint32_t)(((uint32_t)(x)) << LTC_ESTA_ERRID1_SHIFT)) & LTC_ESTA_ERRID1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9158 | #define LTC_ESTA_CL1_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 9159 | #define LTC_ESTA_CL1_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 9160 | #define LTC_ESTA_CL1(x) (((uint32_t)(((uint32_t)(x)) << LTC_ESTA_CL1_SHIFT)) & LTC_ESTA_CL1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9161 | |
AnnaBridge | 171:3a7713b1edbc | 9162 | /*! @name AADSZ - LTC AAD Size Register */ |
AnnaBridge | 171:3a7713b1edbc | 9163 | #define LTC_AADSZ_AADSZ_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 9164 | #define LTC_AADSZ_AADSZ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9165 | #define LTC_AADSZ_AADSZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_AADSZ_AADSZ_SHIFT)) & LTC_AADSZ_AADSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9166 | #define LTC_AADSZ_AL_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 9167 | #define LTC_AADSZ_AL_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 9168 | #define LTC_AADSZ_AL(x) (((uint32_t)(((uint32_t)(x)) << LTC_AADSZ_AL_SHIFT)) & LTC_AADSZ_AL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9169 | |
AnnaBridge | 171:3a7713b1edbc | 9170 | /*! @name IVSZ - LTC IV Size Register */ |
AnnaBridge | 171:3a7713b1edbc | 9171 | #define LTC_IVSZ_IVSZ_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 9172 | #define LTC_IVSZ_IVSZ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9173 | #define LTC_IVSZ_IVSZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_IVSZ_IVSZ_SHIFT)) & LTC_IVSZ_IVSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9174 | #define LTC_IVSZ_IL_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 9175 | #define LTC_IVSZ_IL_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 9176 | #define LTC_IVSZ_IL(x) (((uint32_t)(((uint32_t)(x)) << LTC_IVSZ_IL_SHIFT)) & LTC_IVSZ_IL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9177 | |
AnnaBridge | 171:3a7713b1edbc | 9178 | /*! @name DPAMS - LTC DPA Mask Seed Register */ |
AnnaBridge | 171:3a7713b1edbc | 9179 | #define LTC_DPAMS_DPAMS_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9180 | #define LTC_DPAMS_DPAMS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9181 | #define LTC_DPAMS_DPAMS(x) (((uint32_t)(((uint32_t)(x)) << LTC_DPAMS_DPAMS_SHIFT)) & LTC_DPAMS_DPAMS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9182 | |
AnnaBridge | 171:3a7713b1edbc | 9183 | /*! @name PKASZ - LTC PKHA A Size Register */ |
AnnaBridge | 171:3a7713b1edbc | 9184 | #define LTC_PKASZ_PKASZ_MASK (0x1FFU) |
AnnaBridge | 171:3a7713b1edbc | 9185 | #define LTC_PKASZ_PKASZ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9186 | #define LTC_PKASZ_PKASZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKASZ_PKASZ_SHIFT)) & LTC_PKASZ_PKASZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9187 | |
AnnaBridge | 171:3a7713b1edbc | 9188 | /*! @name PKBSZ - LTC PKHA B Size Register */ |
AnnaBridge | 171:3a7713b1edbc | 9189 | #define LTC_PKBSZ_PKBSZ_MASK (0x1FFU) |
AnnaBridge | 171:3a7713b1edbc | 9190 | #define LTC_PKBSZ_PKBSZ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9191 | #define LTC_PKBSZ_PKBSZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKBSZ_PKBSZ_SHIFT)) & LTC_PKBSZ_PKBSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9192 | |
AnnaBridge | 171:3a7713b1edbc | 9193 | /*! @name PKNSZ - LTC PKHA N Size Register */ |
AnnaBridge | 171:3a7713b1edbc | 9194 | #define LTC_PKNSZ_PKNSZ_MASK (0x1FFU) |
AnnaBridge | 171:3a7713b1edbc | 9195 | #define LTC_PKNSZ_PKNSZ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9196 | #define LTC_PKNSZ_PKNSZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKNSZ_PKNSZ_SHIFT)) & LTC_PKNSZ_PKNSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9197 | |
AnnaBridge | 171:3a7713b1edbc | 9198 | /*! @name PKESZ - LTC PKHA E Size Register */ |
AnnaBridge | 171:3a7713b1edbc | 9199 | #define LTC_PKESZ_PKESZ_MASK (0x1FFU) |
AnnaBridge | 171:3a7713b1edbc | 9200 | #define LTC_PKESZ_PKESZ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9201 | #define LTC_PKESZ_PKESZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKESZ_PKESZ_SHIFT)) & LTC_PKESZ_PKESZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9202 | |
AnnaBridge | 171:3a7713b1edbc | 9203 | /*! @name CTX - LTC Context Register */ |
AnnaBridge | 171:3a7713b1edbc | 9204 | #define LTC_CTX_CTX_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9205 | #define LTC_CTX_CTX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9206 | #define LTC_CTX_CTX(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTX_CTX_SHIFT)) & LTC_CTX_CTX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9207 | |
AnnaBridge | 171:3a7713b1edbc | 9208 | /* The count of LTC_CTX */ |
AnnaBridge | 171:3a7713b1edbc | 9209 | #define LTC_CTX_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9210 | |
AnnaBridge | 171:3a7713b1edbc | 9211 | /*! @name KEY - LTC Key Registers */ |
AnnaBridge | 171:3a7713b1edbc | 9212 | #define LTC_KEY_KEY_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9213 | #define LTC_KEY_KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9214 | #define LTC_KEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << LTC_KEY_KEY_SHIFT)) & LTC_KEY_KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9215 | |
AnnaBridge | 171:3a7713b1edbc | 9216 | /* The count of LTC_KEY */ |
AnnaBridge | 171:3a7713b1edbc | 9217 | #define LTC_KEY_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 9218 | |
AnnaBridge | 171:3a7713b1edbc | 9219 | /*! @name VID1 - LTC Version ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 9220 | #define LTC_VID1_MIN_REV_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 9221 | #define LTC_VID1_MIN_REV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9222 | #define LTC_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID1_MIN_REV_SHIFT)) & LTC_VID1_MIN_REV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9223 | #define LTC_VID1_MAJ_REV_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 9224 | #define LTC_VID1_MAJ_REV_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 9225 | #define LTC_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID1_MAJ_REV_SHIFT)) & LTC_VID1_MAJ_REV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9226 | #define LTC_VID1_IP_ID_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 9227 | #define LTC_VID1_IP_ID_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9228 | #define LTC_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID1_IP_ID_SHIFT)) & LTC_VID1_IP_ID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9229 | |
AnnaBridge | 171:3a7713b1edbc | 9230 | /*! @name CHAVID - LTC CHA Version ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 9231 | #define LTC_CHAVID_AESREV_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 9232 | #define LTC_CHAVID_AESREV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9233 | #define LTC_CHAVID_AESREV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESREV_SHIFT)) & LTC_CHAVID_AESREV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9234 | #define LTC_CHAVID_AESVID_MASK (0xF0U) |
AnnaBridge | 171:3a7713b1edbc | 9235 | #define LTC_CHAVID_AESVID_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 9236 | #define LTC_CHAVID_AESVID(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESVID_SHIFT)) & LTC_CHAVID_AESVID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9237 | #define LTC_CHAVID_DESREV_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 9238 | #define LTC_CHAVID_DESREV_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 9239 | #define LTC_CHAVID_DESREV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_DESREV_SHIFT)) & LTC_CHAVID_DESREV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9240 | #define LTC_CHAVID_DESVID_MASK (0xF000U) |
AnnaBridge | 171:3a7713b1edbc | 9241 | #define LTC_CHAVID_DESVID_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 9242 | #define LTC_CHAVID_DESVID(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_DESVID_SHIFT)) & LTC_CHAVID_DESVID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9243 | #define LTC_CHAVID_PKHAREV_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 9244 | #define LTC_CHAVID_PKHAREV_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9245 | #define LTC_CHAVID_PKHAREV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_PKHAREV_SHIFT)) & LTC_CHAVID_PKHAREV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9246 | #define LTC_CHAVID_PKHAVID_MASK (0xF00000U) |
AnnaBridge | 171:3a7713b1edbc | 9247 | #define LTC_CHAVID_PKHAVID_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 9248 | #define LTC_CHAVID_PKHAVID(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_PKHAVID_SHIFT)) & LTC_CHAVID_PKHAVID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9249 | |
AnnaBridge | 171:3a7713b1edbc | 9250 | /*! @name FIFOSTA - LTC FIFO Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 9251 | #define LTC_FIFOSTA_IFL_MASK (0x7FU) |
AnnaBridge | 171:3a7713b1edbc | 9252 | #define LTC_FIFOSTA_IFL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9253 | #define LTC_FIFOSTA_IFL(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_IFL_SHIFT)) & LTC_FIFOSTA_IFL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9254 | #define LTC_FIFOSTA_IFF_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 9255 | #define LTC_FIFOSTA_IFF_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 9256 | #define LTC_FIFOSTA_IFF(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_IFF_SHIFT)) & LTC_FIFOSTA_IFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9257 | #define LTC_FIFOSTA_OFL_MASK (0x7F0000U) |
AnnaBridge | 171:3a7713b1edbc | 9258 | #define LTC_FIFOSTA_OFL_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9259 | #define LTC_FIFOSTA_OFL(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_OFL_SHIFT)) & LTC_FIFOSTA_OFL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9260 | #define LTC_FIFOSTA_OFF_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 9261 | #define LTC_FIFOSTA_OFF_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 9262 | #define LTC_FIFOSTA_OFF(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_OFF_SHIFT)) & LTC_FIFOSTA_OFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9263 | |
AnnaBridge | 171:3a7713b1edbc | 9264 | /*! @name IFIFO - LTC Input Data FIFO */ |
AnnaBridge | 171:3a7713b1edbc | 9265 | #define LTC_IFIFO_IFIFO_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9266 | #define LTC_IFIFO_IFIFO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9267 | #define LTC_IFIFO_IFIFO(x) (((uint32_t)(((uint32_t)(x)) << LTC_IFIFO_IFIFO_SHIFT)) & LTC_IFIFO_IFIFO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9268 | |
AnnaBridge | 171:3a7713b1edbc | 9269 | /*! @name OFIFO - LTC Output Data FIFO */ |
AnnaBridge | 171:3a7713b1edbc | 9270 | #define LTC_OFIFO_OFIFO_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9271 | #define LTC_OFIFO_OFIFO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9272 | #define LTC_OFIFO_OFIFO(x) (((uint32_t)(((uint32_t)(x)) << LTC_OFIFO_OFIFO_SHIFT)) & LTC_OFIFO_OFIFO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9273 | |
AnnaBridge | 171:3a7713b1edbc | 9274 | /* The count of LTC_PKA */ |
AnnaBridge | 171:3a7713b1edbc | 9275 | #define LTC_PKA_COUNT (64U) |
AnnaBridge | 171:3a7713b1edbc | 9276 | |
AnnaBridge | 171:3a7713b1edbc | 9277 | /*! @name PKA0 - LTC PKHA A0 0 Register..LTC PKHA A0 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9278 | #define LTC_PKA0_PKHA_A0_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9279 | #define LTC_PKA0_PKHA_A0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9280 | #define LTC_PKA0_PKHA_A0(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKA0_PKHA_A0_SHIFT)) & LTC_PKA0_PKHA_A0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9281 | |
AnnaBridge | 171:3a7713b1edbc | 9282 | /* The count of LTC_PKA0 */ |
AnnaBridge | 171:3a7713b1edbc | 9283 | #define LTC_PKA0_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9284 | |
AnnaBridge | 171:3a7713b1edbc | 9285 | /*! @name PKA1 - LTC PKHA A1 0 Register..LTC PKHA A1 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9286 | #define LTC_PKA1_PKHA_A1_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9287 | #define LTC_PKA1_PKHA_A1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9288 | #define LTC_PKA1_PKHA_A1(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKA1_PKHA_A1_SHIFT)) & LTC_PKA1_PKHA_A1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9289 | |
AnnaBridge | 171:3a7713b1edbc | 9290 | /* The count of LTC_PKA1 */ |
AnnaBridge | 171:3a7713b1edbc | 9291 | #define LTC_PKA1_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9292 | |
AnnaBridge | 171:3a7713b1edbc | 9293 | /*! @name PKA2 - LTC PKHA A2 0 Register..LTC PKHA A2 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9294 | #define LTC_PKA2_PKHA_A2_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9295 | #define LTC_PKA2_PKHA_A2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9296 | #define LTC_PKA2_PKHA_A2(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKA2_PKHA_A2_SHIFT)) & LTC_PKA2_PKHA_A2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9297 | |
AnnaBridge | 171:3a7713b1edbc | 9298 | /* The count of LTC_PKA2 */ |
AnnaBridge | 171:3a7713b1edbc | 9299 | #define LTC_PKA2_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9300 | |
AnnaBridge | 171:3a7713b1edbc | 9301 | /*! @name PKA3 - LTC PKHA A3 0 Register..LTC PKHA A3 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9302 | #define LTC_PKA3_PKHA_A3_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9303 | #define LTC_PKA3_PKHA_A3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9304 | #define LTC_PKA3_PKHA_A3(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKA3_PKHA_A3_SHIFT)) & LTC_PKA3_PKHA_A3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9305 | |
AnnaBridge | 171:3a7713b1edbc | 9306 | /* The count of LTC_PKA3 */ |
AnnaBridge | 171:3a7713b1edbc | 9307 | #define LTC_PKA3_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9308 | |
AnnaBridge | 171:3a7713b1edbc | 9309 | /* The count of LTC_PKB */ |
AnnaBridge | 171:3a7713b1edbc | 9310 | #define LTC_PKB_COUNT (64U) |
AnnaBridge | 171:3a7713b1edbc | 9311 | |
AnnaBridge | 171:3a7713b1edbc | 9312 | /*! @name PKB0 - LTC PKHA B0 0 Register..LTC PKHA B0 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9313 | #define LTC_PKB0_PKHA_B0_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9314 | #define LTC_PKB0_PKHA_B0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9315 | #define LTC_PKB0_PKHA_B0(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKB0_PKHA_B0_SHIFT)) & LTC_PKB0_PKHA_B0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9316 | |
AnnaBridge | 171:3a7713b1edbc | 9317 | /* The count of LTC_PKB0 */ |
AnnaBridge | 171:3a7713b1edbc | 9318 | #define LTC_PKB0_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9319 | |
AnnaBridge | 171:3a7713b1edbc | 9320 | /*! @name PKB1 - LTC PKHA B1 0 Register..LTC PKHA B1 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9321 | #define LTC_PKB1_PKHA_B1_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9322 | #define LTC_PKB1_PKHA_B1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9323 | #define LTC_PKB1_PKHA_B1(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKB1_PKHA_B1_SHIFT)) & LTC_PKB1_PKHA_B1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9324 | |
AnnaBridge | 171:3a7713b1edbc | 9325 | /* The count of LTC_PKB1 */ |
AnnaBridge | 171:3a7713b1edbc | 9326 | #define LTC_PKB1_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9327 | |
AnnaBridge | 171:3a7713b1edbc | 9328 | /*! @name PKB2 - LTC PKHA B2 0 Register..LTC PKHA B2 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9329 | #define LTC_PKB2_PKHA_B2_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9330 | #define LTC_PKB2_PKHA_B2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9331 | #define LTC_PKB2_PKHA_B2(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKB2_PKHA_B2_SHIFT)) & LTC_PKB2_PKHA_B2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9332 | |
AnnaBridge | 171:3a7713b1edbc | 9333 | /* The count of LTC_PKB2 */ |
AnnaBridge | 171:3a7713b1edbc | 9334 | #define LTC_PKB2_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9335 | |
AnnaBridge | 171:3a7713b1edbc | 9336 | /*! @name PKB3 - LTC PKHA B3 0 Register..LTC PKHA B3 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9337 | #define LTC_PKB3_PKHA_B3_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9338 | #define LTC_PKB3_PKHA_B3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9339 | #define LTC_PKB3_PKHA_B3(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKB3_PKHA_B3_SHIFT)) & LTC_PKB3_PKHA_B3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9340 | |
AnnaBridge | 171:3a7713b1edbc | 9341 | /* The count of LTC_PKB3 */ |
AnnaBridge | 171:3a7713b1edbc | 9342 | #define LTC_PKB3_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9343 | |
AnnaBridge | 171:3a7713b1edbc | 9344 | /* The count of LTC_PKN */ |
AnnaBridge | 171:3a7713b1edbc | 9345 | #define LTC_PKN_COUNT (64U) |
AnnaBridge | 171:3a7713b1edbc | 9346 | |
AnnaBridge | 171:3a7713b1edbc | 9347 | /*! @name PKN0 - LTC PKHA N0 0 Register..LTC PKHA N0 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9348 | #define LTC_PKN0_PKHA_N0_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9349 | #define LTC_PKN0_PKHA_N0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9350 | #define LTC_PKN0_PKHA_N0(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKN0_PKHA_N0_SHIFT)) & LTC_PKN0_PKHA_N0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9351 | |
AnnaBridge | 171:3a7713b1edbc | 9352 | /* The count of LTC_PKN0 */ |
AnnaBridge | 171:3a7713b1edbc | 9353 | #define LTC_PKN0_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9354 | |
AnnaBridge | 171:3a7713b1edbc | 9355 | /*! @name PKN1 - LTC PKHA N1 0 Register..LTC PKHA N1 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9356 | #define LTC_PKN1_PKHA_N1_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9357 | #define LTC_PKN1_PKHA_N1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9358 | #define LTC_PKN1_PKHA_N1(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKN1_PKHA_N1_SHIFT)) & LTC_PKN1_PKHA_N1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9359 | |
AnnaBridge | 171:3a7713b1edbc | 9360 | /* The count of LTC_PKN1 */ |
AnnaBridge | 171:3a7713b1edbc | 9361 | #define LTC_PKN1_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9362 | |
AnnaBridge | 171:3a7713b1edbc | 9363 | /*! @name PKN2 - LTC PKHA N2 0 Register..LTC PKHA N2 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9364 | #define LTC_PKN2_PKHA_N2_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9365 | #define LTC_PKN2_PKHA_N2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9366 | #define LTC_PKN2_PKHA_N2(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKN2_PKHA_N2_SHIFT)) & LTC_PKN2_PKHA_N2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9367 | |
AnnaBridge | 171:3a7713b1edbc | 9368 | /* The count of LTC_PKN2 */ |
AnnaBridge | 171:3a7713b1edbc | 9369 | #define LTC_PKN2_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9370 | |
AnnaBridge | 171:3a7713b1edbc | 9371 | /*! @name PKN3 - LTC PKHA N3 0 Register..LTC PKHA N3 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9372 | #define LTC_PKN3_PKHA_N3_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9373 | #define LTC_PKN3_PKHA_N3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9374 | #define LTC_PKN3_PKHA_N3(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKN3_PKHA_N3_SHIFT)) & LTC_PKN3_PKHA_N3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9375 | |
AnnaBridge | 171:3a7713b1edbc | 9376 | /* The count of LTC_PKN3 */ |
AnnaBridge | 171:3a7713b1edbc | 9377 | #define LTC_PKN3_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9378 | |
AnnaBridge | 171:3a7713b1edbc | 9379 | /* The count of LTC_PKE */ |
AnnaBridge | 171:3a7713b1edbc | 9380 | #define LTC_PKE_COUNT (64U) |
AnnaBridge | 171:3a7713b1edbc | 9381 | |
AnnaBridge | 171:3a7713b1edbc | 9382 | /*! @name PKE0 - LTC PKHA E0 0 Register..LTC PKHA E0 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9383 | #define LTC_PKE0_PKHA_E0_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9384 | #define LTC_PKE0_PKHA_E0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9385 | #define LTC_PKE0_PKHA_E0(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKE0_PKHA_E0_SHIFT)) & LTC_PKE0_PKHA_E0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9386 | |
AnnaBridge | 171:3a7713b1edbc | 9387 | /* The count of LTC_PKE0 */ |
AnnaBridge | 171:3a7713b1edbc | 9388 | #define LTC_PKE0_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9389 | |
AnnaBridge | 171:3a7713b1edbc | 9390 | /*! @name PKE1 - LTC PKHA E1 0 Register..LTC PKHA E1 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9391 | #define LTC_PKE1_PKHA_E1_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9392 | #define LTC_PKE1_PKHA_E1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9393 | #define LTC_PKE1_PKHA_E1(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKE1_PKHA_E1_SHIFT)) & LTC_PKE1_PKHA_E1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9394 | |
AnnaBridge | 171:3a7713b1edbc | 9395 | /* The count of LTC_PKE1 */ |
AnnaBridge | 171:3a7713b1edbc | 9396 | #define LTC_PKE1_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9397 | |
AnnaBridge | 171:3a7713b1edbc | 9398 | /*! @name PKE2 - LTC PKHA E2 0 Register..LTC PKHA E2 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9399 | #define LTC_PKE2_PKHA_E2_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9400 | #define LTC_PKE2_PKHA_E2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9401 | #define LTC_PKE2_PKHA_E2(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKE2_PKHA_E2_SHIFT)) & LTC_PKE2_PKHA_E2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9402 | |
AnnaBridge | 171:3a7713b1edbc | 9403 | /* The count of LTC_PKE2 */ |
AnnaBridge | 171:3a7713b1edbc | 9404 | #define LTC_PKE2_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9405 | |
AnnaBridge | 171:3a7713b1edbc | 9406 | /*! @name PKE3 - LTC PKHA E3 0 Register..LTC PKHA E3 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9407 | #define LTC_PKE3_PKHA_E3_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9408 | #define LTC_PKE3_PKHA_E3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9409 | #define LTC_PKE3_PKHA_E3(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKE3_PKHA_E3_SHIFT)) & LTC_PKE3_PKHA_E3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9410 | |
AnnaBridge | 171:3a7713b1edbc | 9411 | /* The count of LTC_PKE3 */ |
AnnaBridge | 171:3a7713b1edbc | 9412 | #define LTC_PKE3_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9413 | |
AnnaBridge | 171:3a7713b1edbc | 9414 | |
AnnaBridge | 171:3a7713b1edbc | 9415 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9416 | * @} |
AnnaBridge | 171:3a7713b1edbc | 9417 | */ /* end of group LTC_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 9418 | |
AnnaBridge | 171:3a7713b1edbc | 9419 | |
AnnaBridge | 171:3a7713b1edbc | 9420 | /* LTC - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 9421 | /** Peripheral LTC0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 9422 | #define LTC0_BASE (0x400D1000u) |
AnnaBridge | 171:3a7713b1edbc | 9423 | /** Peripheral LTC0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 9424 | #define LTC0 ((LTC_Type *)LTC0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 9425 | /** Array initializer of LTC peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 9426 | #define LTC_BASE_ADDRS { LTC0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 9427 | /** Array initializer of LTC peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 9428 | #define LTC_BASE_PTRS { LTC0 } |
AnnaBridge | 171:3a7713b1edbc | 9429 | /** Interrupt vectors for the LTC peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 9430 | #define LTC_IRQS { LTC0_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 9431 | |
AnnaBridge | 171:3a7713b1edbc | 9432 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9433 | * @} |
AnnaBridge | 171:3a7713b1edbc | 9434 | */ /* end of group LTC_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 9435 | |
AnnaBridge | 171:3a7713b1edbc | 9436 | |
AnnaBridge | 171:3a7713b1edbc | 9437 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 9438 | -- MCG Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 9439 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 9440 | |
AnnaBridge | 171:3a7713b1edbc | 9441 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9442 | * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 9443 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 9444 | */ |
AnnaBridge | 171:3a7713b1edbc | 9445 | |
AnnaBridge | 171:3a7713b1edbc | 9446 | /** MCG - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 9447 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 9448 | __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 9449 | __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 9450 | __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 9451 | __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */ |
AnnaBridge | 171:3a7713b1edbc | 9452 | __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 9453 | __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */ |
AnnaBridge | 171:3a7713b1edbc | 9454 | __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */ |
AnnaBridge | 171:3a7713b1edbc | 9455 | uint8_t RESERVED_0[1]; |
AnnaBridge | 171:3a7713b1edbc | 9456 | __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 9457 | uint8_t RESERVED_1[1]; |
AnnaBridge | 171:3a7713b1edbc | 9458 | __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */ |
AnnaBridge | 171:3a7713b1edbc | 9459 | __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */ |
AnnaBridge | 171:3a7713b1edbc | 9460 | __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 9461 | __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */ |
AnnaBridge | 171:3a7713b1edbc | 9462 | } MCG_Type; |
AnnaBridge | 171:3a7713b1edbc | 9463 | |
AnnaBridge | 171:3a7713b1edbc | 9464 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 9465 | -- MCG Register Masks |
AnnaBridge | 171:3a7713b1edbc | 9466 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 9467 | |
AnnaBridge | 171:3a7713b1edbc | 9468 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9469 | * @addtogroup MCG_Register_Masks MCG Register Masks |
AnnaBridge | 171:3a7713b1edbc | 9470 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 9471 | */ |
AnnaBridge | 171:3a7713b1edbc | 9472 | |
AnnaBridge | 171:3a7713b1edbc | 9473 | /*! @name C1 - MCG Control 1 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9474 | #define MCG_C1_IREFSTEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9475 | #define MCG_C1_IREFSTEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9476 | #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9477 | #define MCG_C1_IRCLKEN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 9478 | #define MCG_C1_IRCLKEN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9479 | #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9480 | #define MCG_C1_IREFS_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 9481 | #define MCG_C1_IREFS_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 9482 | #define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9483 | #define MCG_C1_FRDIV_MASK (0x38U) |
AnnaBridge | 171:3a7713b1edbc | 9484 | #define MCG_C1_FRDIV_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 9485 | #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9486 | #define MCG_C1_CLKS_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 9487 | #define MCG_C1_CLKS_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 9488 | #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9489 | |
AnnaBridge | 171:3a7713b1edbc | 9490 | /*! @name C2 - MCG Control 2 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9491 | #define MCG_C2_IRCS_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9492 | #define MCG_C2_IRCS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9493 | #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9494 | #define MCG_C2_LP_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 9495 | #define MCG_C2_LP_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9496 | #define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9497 | #define MCG_C2_EREFS_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 9498 | #define MCG_C2_EREFS_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 9499 | #define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9500 | #define MCG_C2_HGO_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 9501 | #define MCG_C2_HGO_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 9502 | #define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9503 | #define MCG_C2_RANGE_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 9504 | #define MCG_C2_RANGE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 9505 | #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9506 | #define MCG_C2_FCFTRIM_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 9507 | #define MCG_C2_FCFTRIM_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 9508 | #define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9509 | #define MCG_C2_LOCRE0_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 9510 | #define MCG_C2_LOCRE0_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 9511 | #define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9512 | |
AnnaBridge | 171:3a7713b1edbc | 9513 | /*! @name C3 - MCG Control 3 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9514 | #define MCG_C3_SCTRIM_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 9515 | #define MCG_C3_SCTRIM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9516 | #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9517 | |
AnnaBridge | 171:3a7713b1edbc | 9518 | /*! @name C4 - MCG Control 4 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9519 | #define MCG_C4_SCFTRIM_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9520 | #define MCG_C4_SCFTRIM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9521 | #define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9522 | #define MCG_C4_FCTRIM_MASK (0x1EU) |
AnnaBridge | 171:3a7713b1edbc | 9523 | #define MCG_C4_FCTRIM_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9524 | #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9525 | #define MCG_C4_DRST_DRS_MASK (0x60U) |
AnnaBridge | 171:3a7713b1edbc | 9526 | #define MCG_C4_DRST_DRS_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9527 | #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9528 | #define MCG_C4_DMX32_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 9529 | #define MCG_C4_DMX32_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 9530 | #define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9531 | |
AnnaBridge | 171:3a7713b1edbc | 9532 | /*! @name C5 - MCG Control 5 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9533 | #define MCG_C5_PRDIV_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 9534 | #define MCG_C5_PRDIV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9535 | #define MCG_C5_PRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV_SHIFT)) & MCG_C5_PRDIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9536 | #define MCG_C5_PLLSTEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 9537 | #define MCG_C5_PLLSTEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9538 | #define MCG_C5_PLLSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN_SHIFT)) & MCG_C5_PLLSTEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9539 | #define MCG_C5_PLLCLKEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 9540 | #define MCG_C5_PLLCLKEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 9541 | #define MCG_C5_PLLCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN_SHIFT)) & MCG_C5_PLLCLKEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9542 | |
AnnaBridge | 171:3a7713b1edbc | 9543 | /*! @name C6 - MCG Control 6 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9544 | #define MCG_C6_VDIV_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 9545 | #define MCG_C6_VDIV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9546 | #define MCG_C6_VDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV_SHIFT)) & MCG_C6_VDIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9547 | #define MCG_C6_CME0_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 9548 | #define MCG_C6_CME0_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9549 | #define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9550 | #define MCG_C6_PLLS_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 9551 | #define MCG_C6_PLLS_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 9552 | #define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9553 | #define MCG_C6_LOLIE0_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 9554 | #define MCG_C6_LOLIE0_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 9555 | #define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9556 | |
AnnaBridge | 171:3a7713b1edbc | 9557 | /*! @name S - MCG Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 9558 | #define MCG_S_IRCST_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9559 | #define MCG_S_IRCST_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9560 | #define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9561 | #define MCG_S_OSCINIT0_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 9562 | #define MCG_S_OSCINIT0_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9563 | #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9564 | #define MCG_S_CLKST_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 9565 | #define MCG_S_CLKST_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 9566 | #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9567 | #define MCG_S_IREFST_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 9568 | #define MCG_S_IREFST_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 9569 | #define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9570 | #define MCG_S_PLLST_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 9571 | #define MCG_S_PLLST_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9572 | #define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9573 | #define MCG_S_LOCK0_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 9574 | #define MCG_S_LOCK0_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 9575 | #define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9576 | #define MCG_S_LOLS0_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 9577 | #define MCG_S_LOLS0_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 9578 | #define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9579 | |
AnnaBridge | 171:3a7713b1edbc | 9580 | /*! @name SC - MCG Status and Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 9581 | #define MCG_SC_LOCS0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9582 | #define MCG_SC_LOCS0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9583 | #define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9584 | #define MCG_SC_FCRDIV_MASK (0xEU) |
AnnaBridge | 171:3a7713b1edbc | 9585 | #define MCG_SC_FCRDIV_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9586 | #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9587 | #define MCG_SC_FLTPRSRV_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 9588 | #define MCG_SC_FLTPRSRV_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 9589 | #define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9590 | #define MCG_SC_ATMF_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 9591 | #define MCG_SC_ATMF_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9592 | #define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9593 | #define MCG_SC_ATMS_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 9594 | #define MCG_SC_ATMS_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 9595 | #define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9596 | #define MCG_SC_ATME_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 9597 | #define MCG_SC_ATME_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 9598 | #define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9599 | |
AnnaBridge | 171:3a7713b1edbc | 9600 | /*! @name ATCVH - MCG Auto Trim Compare Value High Register */ |
AnnaBridge | 171:3a7713b1edbc | 9601 | #define MCG_ATCVH_ATCVH_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 9602 | #define MCG_ATCVH_ATCVH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9603 | #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9604 | |
AnnaBridge | 171:3a7713b1edbc | 9605 | /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */ |
AnnaBridge | 171:3a7713b1edbc | 9606 | #define MCG_ATCVL_ATCVL_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 9607 | #define MCG_ATCVL_ATCVL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9608 | #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9609 | |
AnnaBridge | 171:3a7713b1edbc | 9610 | /*! @name C7 - MCG Control 7 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9611 | #define MCG_C7_OSCSEL_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 9612 | #define MCG_C7_OSCSEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9613 | #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9614 | |
AnnaBridge | 171:3a7713b1edbc | 9615 | /*! @name C8 - MCG Control 8 Register */ |
AnnaBridge | 171:3a7713b1edbc | 9616 | #define MCG_C8_LOCS1_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9617 | #define MCG_C8_LOCS1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9618 | #define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9619 | #define MCG_C8_CME1_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 9620 | #define MCG_C8_CME1_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9621 | #define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9622 | #define MCG_C8_LOLRE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 9623 | #define MCG_C8_LOLRE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 9624 | #define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9625 | #define MCG_C8_LOCRE1_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 9626 | #define MCG_C8_LOCRE1_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 9627 | #define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9628 | |
AnnaBridge | 171:3a7713b1edbc | 9629 | |
AnnaBridge | 171:3a7713b1edbc | 9630 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9631 | * @} |
AnnaBridge | 171:3a7713b1edbc | 9632 | */ /* end of group MCG_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 9633 | |
AnnaBridge | 171:3a7713b1edbc | 9634 | |
AnnaBridge | 171:3a7713b1edbc | 9635 | /* MCG - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 9636 | /** Peripheral MCG base address */ |
AnnaBridge | 171:3a7713b1edbc | 9637 | #define MCG_BASE (0x40064000u) |
AnnaBridge | 171:3a7713b1edbc | 9638 | /** Peripheral MCG base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 9639 | #define MCG ((MCG_Type *)MCG_BASE) |
AnnaBridge | 171:3a7713b1edbc | 9640 | /** Array initializer of MCG peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 9641 | #define MCG_BASE_ADDRS { MCG_BASE } |
AnnaBridge | 171:3a7713b1edbc | 9642 | /** Array initializer of MCG peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 9643 | #define MCG_BASE_PTRS { MCG } |
AnnaBridge | 171:3a7713b1edbc | 9644 | /** Interrupt vectors for the MCG peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 9645 | #define MCG_IRQS { MCG_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 9646 | /* MCG C5[PLLCLKEN0] backward compatibility */ |
AnnaBridge | 171:3a7713b1edbc | 9647 | #define MCG_C5_PLLCLKEN0_MASK (MCG_C5_PLLCLKEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9648 | #define MCG_C5_PLLCLKEN0_SHIFT (MCG_C5_PLLCLKEN_SHIFT) |
AnnaBridge | 171:3a7713b1edbc | 9649 | #define MCG_C5_PLLCLKEN0_WIDTH (MCG_C5_PLLCLKEN_WIDTH) |
AnnaBridge | 171:3a7713b1edbc | 9650 | #define MCG_C5_PLLCLKEN0(x) (MCG_C5_PLLCLKEN(x)) |
AnnaBridge | 171:3a7713b1edbc | 9651 | |
AnnaBridge | 171:3a7713b1edbc | 9652 | /* MCG C5[PLLSTEN0] backward compatibility */ |
AnnaBridge | 171:3a7713b1edbc | 9653 | #define MCG_C5_PLLSTEN0_MASK (MCG_C5_PLLSTEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9654 | #define MCG_C5_PLLSTEN0_SHIFT (MCG_C5_PLLSTEN_SHIFT) |
AnnaBridge | 171:3a7713b1edbc | 9655 | #define MCG_C5_PLLSTEN0_WIDTH (MCG_C5_PLLSTEN_WIDTH) |
AnnaBridge | 171:3a7713b1edbc | 9656 | #define MCG_C5_PLLSTEN0(x) (MCG_C5_PLLSTEN(x)) |
AnnaBridge | 171:3a7713b1edbc | 9657 | |
AnnaBridge | 171:3a7713b1edbc | 9658 | /* MCG C5[PRDIV0] backward compatibility */ |
AnnaBridge | 171:3a7713b1edbc | 9659 | #define MCG_C5_PRDIV0_MASK (MCG_C5_PRDIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9660 | #define MCG_C5_PRDIV0_SHIFT (MCG_C5_PRDIV_SHIFT) |
AnnaBridge | 171:3a7713b1edbc | 9661 | #define MCG_C5_PRDIV0_WIDTH (MCG_C5_PRDIV_WIDTH) |
AnnaBridge | 171:3a7713b1edbc | 9662 | #define MCG_C5_PRDIV0(x) (MCG_C5_PRDIV(x)) |
AnnaBridge | 171:3a7713b1edbc | 9663 | |
AnnaBridge | 171:3a7713b1edbc | 9664 | /* MCG C6[VDIV0] backward compatibility */ |
AnnaBridge | 171:3a7713b1edbc | 9665 | #define MCG_C6_VDIV0_MASK (MCG_C6_VDIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9666 | #define MCG_C6_VDIV0_SHIFT (MCG_C6_VDIV_SHIFT) |
AnnaBridge | 171:3a7713b1edbc | 9667 | #define MCG_C6_VDIV0_WIDTH (MCG_C6_VDIV_WIDTH) |
AnnaBridge | 171:3a7713b1edbc | 9668 | #define MCG_C6_VDIV0(x) (MCG_C6_VDIV(x)) |
AnnaBridge | 171:3a7713b1edbc | 9669 | |
AnnaBridge | 171:3a7713b1edbc | 9670 | |
AnnaBridge | 171:3a7713b1edbc | 9671 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9672 | * @} |
AnnaBridge | 171:3a7713b1edbc | 9673 | */ /* end of group MCG_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 9674 | |
AnnaBridge | 171:3a7713b1edbc | 9675 | |
AnnaBridge | 171:3a7713b1edbc | 9676 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 9677 | -- MCM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 9678 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 9679 | |
AnnaBridge | 171:3a7713b1edbc | 9680 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9681 | * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 9682 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 9683 | */ |
AnnaBridge | 171:3a7713b1edbc | 9684 | |
AnnaBridge | 171:3a7713b1edbc | 9685 | /** MCM - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 9686 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 9687 | uint8_t RESERVED_0[8]; |
AnnaBridge | 171:3a7713b1edbc | 9688 | __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 9689 | __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ |
AnnaBridge | 171:3a7713b1edbc | 9690 | __IO uint32_t CR; /**< Control Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 9691 | __IO uint32_t ISCR; /**< Interrupt Status Register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 9692 | uint8_t RESERVED_1[12]; |
AnnaBridge | 171:3a7713b1edbc | 9693 | __I uint32_t FADR; /**< Fault address register, offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 9694 | __I uint32_t FATR; /**< Fault attributes register, offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 9695 | __I uint32_t FDR; /**< Fault data register, offset: 0x28 */ |
AnnaBridge | 171:3a7713b1edbc | 9696 | uint8_t RESERVED_2[4]; |
AnnaBridge | 171:3a7713b1edbc | 9697 | __IO uint32_t PID; /**< Process ID register, offset: 0x30 */ |
AnnaBridge | 171:3a7713b1edbc | 9698 | uint8_t RESERVED_3[12]; |
AnnaBridge | 171:3a7713b1edbc | 9699 | __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ |
AnnaBridge | 171:3a7713b1edbc | 9700 | } MCM_Type; |
AnnaBridge | 171:3a7713b1edbc | 9701 | |
AnnaBridge | 171:3a7713b1edbc | 9702 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 9703 | -- MCM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 9704 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 9705 | |
AnnaBridge | 171:3a7713b1edbc | 9706 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9707 | * @addtogroup MCM_Register_Masks MCM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 9708 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 9709 | */ |
AnnaBridge | 171:3a7713b1edbc | 9710 | |
AnnaBridge | 171:3a7713b1edbc | 9711 | /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 9712 | #define MCM_PLASC_ASC_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 9713 | #define MCM_PLASC_ASC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9714 | #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9715 | |
AnnaBridge | 171:3a7713b1edbc | 9716 | /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 9717 | #define MCM_PLAMC_AMC_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 9718 | #define MCM_PLAMC_AMC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9719 | #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9720 | |
AnnaBridge | 171:3a7713b1edbc | 9721 | /*! @name CR - Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 9722 | #define MCM_CR_SRAMUAP_MASK (0x3000000U) |
AnnaBridge | 171:3a7713b1edbc | 9723 | #define MCM_CR_SRAMUAP_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 9724 | #define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9725 | #define MCM_CR_SRAMUWP_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 9726 | #define MCM_CR_SRAMUWP_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 9727 | #define MCM_CR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9728 | #define MCM_CR_SRAMLAP_MASK (0x30000000U) |
AnnaBridge | 171:3a7713b1edbc | 9729 | #define MCM_CR_SRAMLAP_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 9730 | #define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9731 | #define MCM_CR_SRAMLWP_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 9732 | #define MCM_CR_SRAMLWP_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 9733 | #define MCM_CR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9734 | |
AnnaBridge | 171:3a7713b1edbc | 9735 | /*! @name ISCR - Interrupt Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 9736 | #define MCM_ISCR_FIOC_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 9737 | #define MCM_ISCR_FIOC_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 9738 | #define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9739 | #define MCM_ISCR_FDZC_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 9740 | #define MCM_ISCR_FDZC_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 9741 | #define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9742 | #define MCM_ISCR_FOFC_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 9743 | #define MCM_ISCR_FOFC_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 9744 | #define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9745 | #define MCM_ISCR_FUFC_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 9746 | #define MCM_ISCR_FUFC_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 9747 | #define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9748 | #define MCM_ISCR_FIXC_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 9749 | #define MCM_ISCR_FIXC_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 9750 | #define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9751 | #define MCM_ISCR_FIDC_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 9752 | #define MCM_ISCR_FIDC_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 9753 | #define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9754 | #define MCM_ISCR_FIOCE_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 9755 | #define MCM_ISCR_FIOCE_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 9756 | #define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9757 | #define MCM_ISCR_FDZCE_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 9758 | #define MCM_ISCR_FDZCE_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 9759 | #define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9760 | #define MCM_ISCR_FOFCE_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 9761 | #define MCM_ISCR_FOFCE_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 9762 | #define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9763 | #define MCM_ISCR_FUFCE_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 9764 | #define MCM_ISCR_FUFCE_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 9765 | #define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9766 | #define MCM_ISCR_FIXCE_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 9767 | #define MCM_ISCR_FIXCE_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 9768 | #define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9769 | #define MCM_ISCR_FIDCE_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 9770 | #define MCM_ISCR_FIDCE_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 9771 | #define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9772 | |
AnnaBridge | 171:3a7713b1edbc | 9773 | /*! @name FADR - Fault address register */ |
AnnaBridge | 171:3a7713b1edbc | 9774 | #define MCM_FADR_ADDRESS_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9775 | #define MCM_FADR_ADDRESS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9776 | #define MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9777 | |
AnnaBridge | 171:3a7713b1edbc | 9778 | /*! @name FATR - Fault attributes register */ |
AnnaBridge | 171:3a7713b1edbc | 9779 | #define MCM_FATR_BEDA_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9780 | #define MCM_FATR_BEDA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9781 | #define MCM_FATR_BEDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9782 | #define MCM_FATR_BEMD_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 9783 | #define MCM_FATR_BEMD_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9784 | #define MCM_FATR_BEMD(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9785 | #define MCM_FATR_BESZ_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 9786 | #define MCM_FATR_BESZ_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 9787 | #define MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9788 | #define MCM_FATR_BEWT_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 9789 | #define MCM_FATR_BEWT_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 9790 | #define MCM_FATR_BEWT(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9791 | #define MCM_FATR_BEMN_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 9792 | #define MCM_FATR_BEMN_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 9793 | #define MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9794 | #define MCM_FATR_BEOVR_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 9795 | #define MCM_FATR_BEOVR_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 9796 | #define MCM_FATR_BEOVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9797 | |
AnnaBridge | 171:3a7713b1edbc | 9798 | /*! @name FDR - Fault data register */ |
AnnaBridge | 171:3a7713b1edbc | 9799 | #define MCM_FDR_DATA_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9800 | #define MCM_FDR_DATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9801 | #define MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9802 | |
AnnaBridge | 171:3a7713b1edbc | 9803 | /*! @name PID - Process ID register */ |
AnnaBridge | 171:3a7713b1edbc | 9804 | #define MCM_PID_PID_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 9805 | #define MCM_PID_PID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9806 | #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9807 | |
AnnaBridge | 171:3a7713b1edbc | 9808 | /*! @name CPO - Compute Operation Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 9809 | #define MCM_CPO_CPOREQ_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9810 | #define MCM_CPO_CPOREQ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9811 | #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9812 | #define MCM_CPO_CPOACK_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 9813 | #define MCM_CPO_CPOACK_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9814 | #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9815 | #define MCM_CPO_CPOWOI_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 9816 | #define MCM_CPO_CPOWOI_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 9817 | #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9818 | |
AnnaBridge | 171:3a7713b1edbc | 9819 | |
AnnaBridge | 171:3a7713b1edbc | 9820 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9821 | * @} |
AnnaBridge | 171:3a7713b1edbc | 9822 | */ /* end of group MCM_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 9823 | |
AnnaBridge | 171:3a7713b1edbc | 9824 | |
AnnaBridge | 171:3a7713b1edbc | 9825 | /* MCM - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 9826 | /** Peripheral MCM base address */ |
AnnaBridge | 171:3a7713b1edbc | 9827 | #define MCM_BASE (0xE0080000u) |
AnnaBridge | 171:3a7713b1edbc | 9828 | /** Peripheral MCM base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 9829 | #define MCM ((MCM_Type *)MCM_BASE) |
AnnaBridge | 171:3a7713b1edbc | 9830 | /** Array initializer of MCM peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 9831 | #define MCM_BASE_ADDRS { MCM_BASE } |
AnnaBridge | 171:3a7713b1edbc | 9832 | /** Array initializer of MCM peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 9833 | #define MCM_BASE_PTRS { MCM } |
AnnaBridge | 171:3a7713b1edbc | 9834 | /** Interrupt vectors for the MCM peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 9835 | #define MCM_IRQS { MCM_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 9836 | |
AnnaBridge | 171:3a7713b1edbc | 9837 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9838 | * @} |
AnnaBridge | 171:3a7713b1edbc | 9839 | */ /* end of group MCM_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 9840 | |
AnnaBridge | 171:3a7713b1edbc | 9841 | |
AnnaBridge | 171:3a7713b1edbc | 9842 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 9843 | -- MPU Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 9844 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 9845 | |
AnnaBridge | 171:3a7713b1edbc | 9846 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9847 | * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 9848 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 9849 | */ |
AnnaBridge | 171:3a7713b1edbc | 9850 | |
AnnaBridge | 171:3a7713b1edbc | 9851 | /** MPU - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 9852 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 9853 | __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 9854 | uint8_t RESERVED_0[12]; |
AnnaBridge | 171:3a7713b1edbc | 9855 | struct { /* offset: 0x10, array step: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 9856 | __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 9857 | __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 9858 | } SP[5]; |
AnnaBridge | 171:3a7713b1edbc | 9859 | uint8_t RESERVED_1[968]; |
AnnaBridge | 171:3a7713b1edbc | 9860 | __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 9861 | uint8_t RESERVED_2[832]; |
AnnaBridge | 171:3a7713b1edbc | 9862 | __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 9863 | } MPU_Type; |
AnnaBridge | 171:3a7713b1edbc | 9864 | |
AnnaBridge | 171:3a7713b1edbc | 9865 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 9866 | -- MPU Register Masks |
AnnaBridge | 171:3a7713b1edbc | 9867 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 9868 | |
AnnaBridge | 171:3a7713b1edbc | 9869 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9870 | * @addtogroup MPU_Register_Masks MPU Register Masks |
AnnaBridge | 171:3a7713b1edbc | 9871 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 9872 | */ |
AnnaBridge | 171:3a7713b1edbc | 9873 | |
AnnaBridge | 171:3a7713b1edbc | 9874 | /*! @name CESR - Control/Error Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 9875 | #define MPU_CESR_VLD_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9876 | #define MPU_CESR_VLD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9877 | #define MPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_VLD_SHIFT)) & MPU_CESR_VLD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9878 | #define MPU_CESR_NRGD_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 9879 | #define MPU_CESR_NRGD_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 9880 | #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NRGD_SHIFT)) & MPU_CESR_NRGD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9881 | #define MPU_CESR_NSP_MASK (0xF000U) |
AnnaBridge | 171:3a7713b1edbc | 9882 | #define MPU_CESR_NSP_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 9883 | #define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NSP_SHIFT)) & MPU_CESR_NSP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9884 | #define MPU_CESR_HRL_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 9885 | #define MPU_CESR_HRL_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9886 | #define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_HRL_SHIFT)) & MPU_CESR_HRL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9887 | #define MPU_CESR_SPERR_MASK (0xF8000000U) |
AnnaBridge | 171:3a7713b1edbc | 9888 | #define MPU_CESR_SPERR_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 9889 | #define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_SPERR_SHIFT)) & MPU_CESR_SPERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9890 | |
AnnaBridge | 171:3a7713b1edbc | 9891 | /*! @name EAR - Error Address Register, slave port n */ |
AnnaBridge | 171:3a7713b1edbc | 9892 | #define MPU_EAR_EADDR_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9893 | #define MPU_EAR_EADDR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9894 | #define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_EAR_EADDR_SHIFT)) & MPU_EAR_EADDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9895 | |
AnnaBridge | 171:3a7713b1edbc | 9896 | /* The count of MPU_EAR */ |
AnnaBridge | 171:3a7713b1edbc | 9897 | #define MPU_EAR_COUNT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9898 | |
AnnaBridge | 171:3a7713b1edbc | 9899 | /*! @name EDR - Error Detail Register, slave port n */ |
AnnaBridge | 171:3a7713b1edbc | 9900 | #define MPU_EDR_ERW_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9901 | #define MPU_EDR_ERW_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9902 | #define MPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_ERW_SHIFT)) & MPU_EDR_ERW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9903 | #define MPU_EDR_EATTR_MASK (0xEU) |
AnnaBridge | 171:3a7713b1edbc | 9904 | #define MPU_EDR_EATTR_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9905 | #define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EATTR_SHIFT)) & MPU_EDR_EATTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9906 | #define MPU_EDR_EMN_MASK (0xF0U) |
AnnaBridge | 171:3a7713b1edbc | 9907 | #define MPU_EDR_EMN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 9908 | #define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EMN_SHIFT)) & MPU_EDR_EMN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9909 | #define MPU_EDR_EPID_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 9910 | #define MPU_EDR_EPID_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 9911 | #define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EPID_SHIFT)) & MPU_EDR_EPID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9912 | #define MPU_EDR_EACD_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 9913 | #define MPU_EDR_EACD_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9914 | #define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EACD_SHIFT)) & MPU_EDR_EACD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9915 | |
AnnaBridge | 171:3a7713b1edbc | 9916 | /* The count of MPU_EDR */ |
AnnaBridge | 171:3a7713b1edbc | 9917 | #define MPU_EDR_COUNT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9918 | |
AnnaBridge | 171:3a7713b1edbc | 9919 | /*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */ |
AnnaBridge | 171:3a7713b1edbc | 9920 | #define MPU_WORD_VLD_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9921 | #define MPU_WORD_VLD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9922 | #define MPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_VLD_SHIFT)) & MPU_WORD_VLD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9923 | #define MPU_WORD_M0UM_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 9924 | #define MPU_WORD_M0UM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9925 | #define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0UM_SHIFT)) & MPU_WORD_M0UM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9926 | #define MPU_WORD_M0SM_MASK (0x18U) |
AnnaBridge | 171:3a7713b1edbc | 9927 | #define MPU_WORD_M0SM_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 9928 | #define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0SM_SHIFT)) & MPU_WORD_M0SM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9929 | #define MPU_WORD_M0PE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 9930 | #define MPU_WORD_M0PE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9931 | #define MPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0PE_SHIFT)) & MPU_WORD_M0PE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9932 | #define MPU_WORD_ENDADDR_MASK (0xFFFFFFE0U) |
AnnaBridge | 171:3a7713b1edbc | 9933 | #define MPU_WORD_ENDADDR_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9934 | #define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_ENDADDR_SHIFT)) & MPU_WORD_ENDADDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9935 | #define MPU_WORD_SRTADDR_MASK (0xFFFFFFE0U) |
AnnaBridge | 171:3a7713b1edbc | 9936 | #define MPU_WORD_SRTADDR_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9937 | #define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_SRTADDR_SHIFT)) & MPU_WORD_SRTADDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9938 | #define MPU_WORD_M1UM_MASK (0x1C0U) |
AnnaBridge | 171:3a7713b1edbc | 9939 | #define MPU_WORD_M1UM_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 9940 | #define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1UM_SHIFT)) & MPU_WORD_M1UM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9941 | #define MPU_WORD_M1SM_MASK (0x600U) |
AnnaBridge | 171:3a7713b1edbc | 9942 | #define MPU_WORD_M1SM_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 9943 | #define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1SM_SHIFT)) & MPU_WORD_M1SM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9944 | #define MPU_WORD_M1PE_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 9945 | #define MPU_WORD_M1PE_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 9946 | #define MPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1PE_SHIFT)) & MPU_WORD_M1PE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9947 | #define MPU_WORD_M2UM_MASK (0x7000U) |
AnnaBridge | 171:3a7713b1edbc | 9948 | #define MPU_WORD_M2UM_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 9949 | #define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2UM_SHIFT)) & MPU_WORD_M2UM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9950 | #define MPU_WORD_M2SM_MASK (0x18000U) |
AnnaBridge | 171:3a7713b1edbc | 9951 | #define MPU_WORD_M2SM_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 9952 | #define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2SM_SHIFT)) & MPU_WORD_M2SM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9953 | #define MPU_WORD_PIDMASK_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 9954 | #define MPU_WORD_PIDMASK_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9955 | #define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PIDMASK_SHIFT)) & MPU_WORD_PIDMASK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9956 | #define MPU_WORD_M2PE_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 9957 | #define MPU_WORD_M2PE_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 9958 | #define MPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2PE_SHIFT)) & MPU_WORD_M2PE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9959 | #define MPU_WORD_M3UM_MASK (0x1C0000U) |
AnnaBridge | 171:3a7713b1edbc | 9960 | #define MPU_WORD_M3UM_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 9961 | #define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3UM_SHIFT)) & MPU_WORD_M3UM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9962 | #define MPU_WORD_M3SM_MASK (0x600000U) |
AnnaBridge | 171:3a7713b1edbc | 9963 | #define MPU_WORD_M3SM_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 9964 | #define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3SM_SHIFT)) & MPU_WORD_M3SM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9965 | #define MPU_WORD_M3PE_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 9966 | #define MPU_WORD_M3PE_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 9967 | #define MPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3PE_SHIFT)) & MPU_WORD_M3PE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9968 | #define MPU_WORD_PID_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 9969 | #define MPU_WORD_PID_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 9970 | #define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PID_SHIFT)) & MPU_WORD_PID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9971 | #define MPU_WORD_M4WE_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 9972 | #define MPU_WORD_M4WE_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 9973 | #define MPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4WE_SHIFT)) & MPU_WORD_M4WE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9974 | #define MPU_WORD_M4RE_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 9975 | #define MPU_WORD_M4RE_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 9976 | #define MPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4RE_SHIFT)) & MPU_WORD_M4RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9977 | #define MPU_WORD_M5WE_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 9978 | #define MPU_WORD_M5WE_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 9979 | #define MPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5WE_SHIFT)) & MPU_WORD_M5WE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9980 | #define MPU_WORD_M5RE_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 9981 | #define MPU_WORD_M5RE_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 9982 | #define MPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5RE_SHIFT)) & MPU_WORD_M5RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9983 | #define MPU_WORD_M6WE_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 9984 | #define MPU_WORD_M6WE_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 9985 | #define MPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6WE_SHIFT)) & MPU_WORD_M6WE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9986 | #define MPU_WORD_M6RE_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 9987 | #define MPU_WORD_M6RE_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 9988 | #define MPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6RE_SHIFT)) & MPU_WORD_M6RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9989 | #define MPU_WORD_M7WE_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 9990 | #define MPU_WORD_M7WE_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 9991 | #define MPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7WE_SHIFT)) & MPU_WORD_M7WE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9992 | #define MPU_WORD_M7RE_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 9993 | #define MPU_WORD_M7RE_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 9994 | #define MPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7RE_SHIFT)) & MPU_WORD_M7RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9995 | |
AnnaBridge | 171:3a7713b1edbc | 9996 | /* The count of MPU_WORD */ |
AnnaBridge | 171:3a7713b1edbc | 9997 | #define MPU_WORD_COUNT (12U) |
AnnaBridge | 171:3a7713b1edbc | 9998 | |
AnnaBridge | 171:3a7713b1edbc | 9999 | /* The count of MPU_WORD */ |
AnnaBridge | 171:3a7713b1edbc | 10000 | #define MPU_WORD_COUNT2 (4U) |
AnnaBridge | 171:3a7713b1edbc | 10001 | |
AnnaBridge | 171:3a7713b1edbc | 10002 | /*! @name RGDAAC - Region Descriptor Alternate Access Control n */ |
AnnaBridge | 171:3a7713b1edbc | 10003 | #define MPU_RGDAAC_M0UM_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 10004 | #define MPU_RGDAAC_M0UM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10005 | #define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0UM_SHIFT)) & MPU_RGDAAC_M0UM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10006 | #define MPU_RGDAAC_M0SM_MASK (0x18U) |
AnnaBridge | 171:3a7713b1edbc | 10007 | #define MPU_RGDAAC_M0SM_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 10008 | #define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0SM_SHIFT)) & MPU_RGDAAC_M0SM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10009 | #define MPU_RGDAAC_M0PE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10010 | #define MPU_RGDAAC_M0PE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10011 | #define MPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0PE_SHIFT)) & MPU_RGDAAC_M0PE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10012 | #define MPU_RGDAAC_M1UM_MASK (0x1C0U) |
AnnaBridge | 171:3a7713b1edbc | 10013 | #define MPU_RGDAAC_M1UM_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10014 | #define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1UM_SHIFT)) & MPU_RGDAAC_M1UM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10015 | #define MPU_RGDAAC_M1SM_MASK (0x600U) |
AnnaBridge | 171:3a7713b1edbc | 10016 | #define MPU_RGDAAC_M1SM_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 10017 | #define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1SM_SHIFT)) & MPU_RGDAAC_M1SM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10018 | #define MPU_RGDAAC_M1PE_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 10019 | #define MPU_RGDAAC_M1PE_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 10020 | #define MPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1PE_SHIFT)) & MPU_RGDAAC_M1PE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10021 | #define MPU_RGDAAC_M2UM_MASK (0x7000U) |
AnnaBridge | 171:3a7713b1edbc | 10022 | #define MPU_RGDAAC_M2UM_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 10023 | #define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2UM_SHIFT)) & MPU_RGDAAC_M2UM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10024 | #define MPU_RGDAAC_M2SM_MASK (0x18000U) |
AnnaBridge | 171:3a7713b1edbc | 10025 | #define MPU_RGDAAC_M2SM_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 10026 | #define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2SM_SHIFT)) & MPU_RGDAAC_M2SM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10027 | #define MPU_RGDAAC_M2PE_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 10028 | #define MPU_RGDAAC_M2PE_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 10029 | #define MPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2PE_SHIFT)) & MPU_RGDAAC_M2PE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10030 | #define MPU_RGDAAC_M3UM_MASK (0x1C0000U) |
AnnaBridge | 171:3a7713b1edbc | 10031 | #define MPU_RGDAAC_M3UM_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 10032 | #define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3UM_SHIFT)) & MPU_RGDAAC_M3UM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10033 | #define MPU_RGDAAC_M3SM_MASK (0x600000U) |
AnnaBridge | 171:3a7713b1edbc | 10034 | #define MPU_RGDAAC_M3SM_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 10035 | #define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3SM_SHIFT)) & MPU_RGDAAC_M3SM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10036 | #define MPU_RGDAAC_M3PE_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 10037 | #define MPU_RGDAAC_M3PE_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 10038 | #define MPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3PE_SHIFT)) & MPU_RGDAAC_M3PE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10039 | #define MPU_RGDAAC_M4WE_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 10040 | #define MPU_RGDAAC_M4WE_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 10041 | #define MPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4WE_SHIFT)) & MPU_RGDAAC_M4WE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10042 | #define MPU_RGDAAC_M4RE_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 10043 | #define MPU_RGDAAC_M4RE_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 10044 | #define MPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4RE_SHIFT)) & MPU_RGDAAC_M4RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10045 | #define MPU_RGDAAC_M5WE_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 10046 | #define MPU_RGDAAC_M5WE_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 10047 | #define MPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5WE_SHIFT)) & MPU_RGDAAC_M5WE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10048 | #define MPU_RGDAAC_M5RE_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 10049 | #define MPU_RGDAAC_M5RE_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 10050 | #define MPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5RE_SHIFT)) & MPU_RGDAAC_M5RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10051 | #define MPU_RGDAAC_M6WE_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 10052 | #define MPU_RGDAAC_M6WE_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 10053 | #define MPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6WE_SHIFT)) & MPU_RGDAAC_M6WE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10054 | #define MPU_RGDAAC_M6RE_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 10055 | #define MPU_RGDAAC_M6RE_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 10056 | #define MPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6RE_SHIFT)) & MPU_RGDAAC_M6RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10057 | #define MPU_RGDAAC_M7WE_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 10058 | #define MPU_RGDAAC_M7WE_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 10059 | #define MPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7WE_SHIFT)) & MPU_RGDAAC_M7WE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10060 | #define MPU_RGDAAC_M7RE_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 10061 | #define MPU_RGDAAC_M7RE_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 10062 | #define MPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7RE_SHIFT)) & MPU_RGDAAC_M7RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10063 | |
AnnaBridge | 171:3a7713b1edbc | 10064 | /* The count of MPU_RGDAAC */ |
AnnaBridge | 171:3a7713b1edbc | 10065 | #define MPU_RGDAAC_COUNT (12U) |
AnnaBridge | 171:3a7713b1edbc | 10066 | |
AnnaBridge | 171:3a7713b1edbc | 10067 | |
AnnaBridge | 171:3a7713b1edbc | 10068 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10069 | * @} |
AnnaBridge | 171:3a7713b1edbc | 10070 | */ /* end of group MPU_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 10071 | |
AnnaBridge | 171:3a7713b1edbc | 10072 | |
AnnaBridge | 171:3a7713b1edbc | 10073 | /* MPU - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 10074 | /** Peripheral MPU base address */ |
AnnaBridge | 171:3a7713b1edbc | 10075 | #define MPU_BASE (0x4000D000u) |
AnnaBridge | 171:3a7713b1edbc | 10076 | /** Peripheral MPU base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 10077 | #define MPU ((MPU_Type *)MPU_BASE) |
AnnaBridge | 171:3a7713b1edbc | 10078 | /** Array initializer of MPU peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 10079 | #define MPU_BASE_ADDRS { MPU_BASE } |
AnnaBridge | 171:3a7713b1edbc | 10080 | /** Array initializer of MPU peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 10081 | #define MPU_BASE_PTRS { MPU } |
AnnaBridge | 171:3a7713b1edbc | 10082 | |
AnnaBridge | 171:3a7713b1edbc | 10083 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10084 | * @} |
AnnaBridge | 171:3a7713b1edbc | 10085 | */ /* end of group MPU_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 10086 | |
AnnaBridge | 171:3a7713b1edbc | 10087 | |
AnnaBridge | 171:3a7713b1edbc | 10088 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 10089 | -- NV Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 10090 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 10091 | |
AnnaBridge | 171:3a7713b1edbc | 10092 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10093 | * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 10094 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 10095 | */ |
AnnaBridge | 171:3a7713b1edbc | 10096 | |
AnnaBridge | 171:3a7713b1edbc | 10097 | /** NV - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 10098 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 10099 | __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 10100 | __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 10101 | __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 10102 | __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ |
AnnaBridge | 171:3a7713b1edbc | 10103 | __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 10104 | __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ |
AnnaBridge | 171:3a7713b1edbc | 10105 | __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ |
AnnaBridge | 171:3a7713b1edbc | 10106 | __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ |
AnnaBridge | 171:3a7713b1edbc | 10107 | __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 10108 | __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ |
AnnaBridge | 171:3a7713b1edbc | 10109 | __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ |
AnnaBridge | 171:3a7713b1edbc | 10110 | __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ |
AnnaBridge | 171:3a7713b1edbc | 10111 | __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 10112 | __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ |
AnnaBridge | 171:3a7713b1edbc | 10113 | } NV_Type; |
AnnaBridge | 171:3a7713b1edbc | 10114 | |
AnnaBridge | 171:3a7713b1edbc | 10115 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 10116 | -- NV Register Masks |
AnnaBridge | 171:3a7713b1edbc | 10117 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 10118 | |
AnnaBridge | 171:3a7713b1edbc | 10119 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10120 | * @addtogroup NV_Register_Masks NV Register Masks |
AnnaBridge | 171:3a7713b1edbc | 10121 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 10122 | */ |
AnnaBridge | 171:3a7713b1edbc | 10123 | |
AnnaBridge | 171:3a7713b1edbc | 10124 | /*! @name BACKKEY3 - Backdoor Comparison Key 3. */ |
AnnaBridge | 171:3a7713b1edbc | 10125 | #define NV_BACKKEY3_KEY_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10126 | #define NV_BACKKEY3_KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10127 | #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10128 | |
AnnaBridge | 171:3a7713b1edbc | 10129 | /*! @name BACKKEY2 - Backdoor Comparison Key 2. */ |
AnnaBridge | 171:3a7713b1edbc | 10130 | #define NV_BACKKEY2_KEY_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10131 | #define NV_BACKKEY2_KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10132 | #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10133 | |
AnnaBridge | 171:3a7713b1edbc | 10134 | /*! @name BACKKEY1 - Backdoor Comparison Key 1. */ |
AnnaBridge | 171:3a7713b1edbc | 10135 | #define NV_BACKKEY1_KEY_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10136 | #define NV_BACKKEY1_KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10137 | #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10138 | |
AnnaBridge | 171:3a7713b1edbc | 10139 | /*! @name BACKKEY0 - Backdoor Comparison Key 0. */ |
AnnaBridge | 171:3a7713b1edbc | 10140 | #define NV_BACKKEY0_KEY_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10141 | #define NV_BACKKEY0_KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10142 | #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10143 | |
AnnaBridge | 171:3a7713b1edbc | 10144 | /*! @name BACKKEY7 - Backdoor Comparison Key 7. */ |
AnnaBridge | 171:3a7713b1edbc | 10145 | #define NV_BACKKEY7_KEY_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10146 | #define NV_BACKKEY7_KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10147 | #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10148 | |
AnnaBridge | 171:3a7713b1edbc | 10149 | /*! @name BACKKEY6 - Backdoor Comparison Key 6. */ |
AnnaBridge | 171:3a7713b1edbc | 10150 | #define NV_BACKKEY6_KEY_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10151 | #define NV_BACKKEY6_KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10152 | #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10153 | |
AnnaBridge | 171:3a7713b1edbc | 10154 | /*! @name BACKKEY5 - Backdoor Comparison Key 5. */ |
AnnaBridge | 171:3a7713b1edbc | 10155 | #define NV_BACKKEY5_KEY_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10156 | #define NV_BACKKEY5_KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10157 | #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10158 | |
AnnaBridge | 171:3a7713b1edbc | 10159 | /*! @name BACKKEY4 - Backdoor Comparison Key 4. */ |
AnnaBridge | 171:3a7713b1edbc | 10160 | #define NV_BACKKEY4_KEY_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10161 | #define NV_BACKKEY4_KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10162 | #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10163 | |
AnnaBridge | 171:3a7713b1edbc | 10164 | /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */ |
AnnaBridge | 171:3a7713b1edbc | 10165 | #define NV_FPROT3_PROT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10166 | #define NV_FPROT3_PROT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10167 | #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10168 | |
AnnaBridge | 171:3a7713b1edbc | 10169 | /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */ |
AnnaBridge | 171:3a7713b1edbc | 10170 | #define NV_FPROT2_PROT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10171 | #define NV_FPROT2_PROT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10172 | #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10173 | |
AnnaBridge | 171:3a7713b1edbc | 10174 | /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */ |
AnnaBridge | 171:3a7713b1edbc | 10175 | #define NV_FPROT1_PROT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10176 | #define NV_FPROT1_PROT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10177 | #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10178 | |
AnnaBridge | 171:3a7713b1edbc | 10179 | /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */ |
AnnaBridge | 171:3a7713b1edbc | 10180 | #define NV_FPROT0_PROT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10181 | #define NV_FPROT0_PROT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10182 | #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10183 | |
AnnaBridge | 171:3a7713b1edbc | 10184 | /*! @name FSEC - Non-volatile Flash Security Register */ |
AnnaBridge | 171:3a7713b1edbc | 10185 | #define NV_FSEC_SEC_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 10186 | #define NV_FSEC_SEC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10187 | #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10188 | #define NV_FSEC_FSLACC_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 10189 | #define NV_FSEC_FSLACC_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10190 | #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10191 | #define NV_FSEC_MEEN_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 10192 | #define NV_FSEC_MEEN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10193 | #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10194 | #define NV_FSEC_KEYEN_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 10195 | #define NV_FSEC_KEYEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10196 | #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10197 | |
AnnaBridge | 171:3a7713b1edbc | 10198 | /*! @name FOPT - Non-volatile Flash Option Register */ |
AnnaBridge | 171:3a7713b1edbc | 10199 | #define NV_FOPT_LPBOOT_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10200 | #define NV_FOPT_LPBOOT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10201 | #define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10202 | #define NV_FOPT_BOOTPIN_OPT_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10203 | #define NV_FOPT_BOOTPIN_OPT_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10204 | #define NV_FOPT_BOOTPIN_OPT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTPIN_OPT_SHIFT)) & NV_FOPT_BOOTPIN_OPT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10205 | #define NV_FOPT_NMI_DIS_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10206 | #define NV_FOPT_NMI_DIS_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10207 | #define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10208 | #define NV_FOPT_FAST_INIT_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10209 | #define NV_FOPT_FAST_INIT_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10210 | #define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10211 | #define NV_FOPT_BOOTSRC_SEL_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 10212 | #define NV_FOPT_BOOTSRC_SEL_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10213 | #define NV_FOPT_BOOTSRC_SEL(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTSRC_SEL_SHIFT)) & NV_FOPT_BOOTSRC_SEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10214 | |
AnnaBridge | 171:3a7713b1edbc | 10215 | |
AnnaBridge | 171:3a7713b1edbc | 10216 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10217 | * @} |
AnnaBridge | 171:3a7713b1edbc | 10218 | */ /* end of group NV_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 10219 | |
AnnaBridge | 171:3a7713b1edbc | 10220 | |
AnnaBridge | 171:3a7713b1edbc | 10221 | /* NV - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 10222 | /** Peripheral FTFA_FlashConfig base address */ |
AnnaBridge | 171:3a7713b1edbc | 10223 | #define FTFA_FlashConfig_BASE (0x400u) |
AnnaBridge | 171:3a7713b1edbc | 10224 | /** Peripheral FTFA_FlashConfig base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 10225 | #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE) |
AnnaBridge | 171:3a7713b1edbc | 10226 | /** Array initializer of NV peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 10227 | #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE } |
AnnaBridge | 171:3a7713b1edbc | 10228 | /** Array initializer of NV peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 10229 | #define NV_BASE_PTRS { FTFA_FlashConfig } |
AnnaBridge | 171:3a7713b1edbc | 10230 | |
AnnaBridge | 171:3a7713b1edbc | 10231 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10232 | * @} |
AnnaBridge | 171:3a7713b1edbc | 10233 | */ /* end of group NV_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 10234 | |
AnnaBridge | 171:3a7713b1edbc | 10235 | |
AnnaBridge | 171:3a7713b1edbc | 10236 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 10237 | -- OSC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 10238 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 10239 | |
AnnaBridge | 171:3a7713b1edbc | 10240 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10241 | * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 10242 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 10243 | */ |
AnnaBridge | 171:3a7713b1edbc | 10244 | |
AnnaBridge | 171:3a7713b1edbc | 10245 | /** OSC - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 10246 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 10247 | __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 10248 | uint8_t RESERVED_0[1]; |
AnnaBridge | 171:3a7713b1edbc | 10249 | __IO uint8_t DIV; /**< OSC_DIV, offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 10250 | } OSC_Type; |
AnnaBridge | 171:3a7713b1edbc | 10251 | |
AnnaBridge | 171:3a7713b1edbc | 10252 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 10253 | -- OSC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 10254 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 10255 | |
AnnaBridge | 171:3a7713b1edbc | 10256 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10257 | * @addtogroup OSC_Register_Masks OSC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 10258 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 10259 | */ |
AnnaBridge | 171:3a7713b1edbc | 10260 | |
AnnaBridge | 171:3a7713b1edbc | 10261 | /*! @name CR - OSC Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 10262 | #define OSC_CR_SC16P_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10263 | #define OSC_CR_SC16P_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10264 | #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10265 | #define OSC_CR_SC8P_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10266 | #define OSC_CR_SC8P_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10267 | #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10268 | #define OSC_CR_SC4P_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10269 | #define OSC_CR_SC4P_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10270 | #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10271 | #define OSC_CR_SC2P_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 10272 | #define OSC_CR_SC2P_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 10273 | #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10274 | #define OSC_CR_EREFSTEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10275 | #define OSC_CR_EREFSTEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10276 | #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10277 | #define OSC_CR_ERCLKEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 10278 | #define OSC_CR_ERCLKEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 10279 | #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10280 | |
AnnaBridge | 171:3a7713b1edbc | 10281 | /*! @name DIV - OSC_DIV */ |
AnnaBridge | 171:3a7713b1edbc | 10282 | #define OSC_DIV_ERPS_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 10283 | #define OSC_DIV_ERPS_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10284 | #define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x)) << OSC_DIV_ERPS_SHIFT)) & OSC_DIV_ERPS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10285 | |
AnnaBridge | 171:3a7713b1edbc | 10286 | |
AnnaBridge | 171:3a7713b1edbc | 10287 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10288 | * @} |
AnnaBridge | 171:3a7713b1edbc | 10289 | */ /* end of group OSC_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 10290 | |
AnnaBridge | 171:3a7713b1edbc | 10291 | |
AnnaBridge | 171:3a7713b1edbc | 10292 | /* OSC - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 10293 | /** Peripheral OSC base address */ |
AnnaBridge | 171:3a7713b1edbc | 10294 | #define OSC_BASE (0x40065000u) |
AnnaBridge | 171:3a7713b1edbc | 10295 | /** Peripheral OSC base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 10296 | #define OSC ((OSC_Type *)OSC_BASE) |
AnnaBridge | 171:3a7713b1edbc | 10297 | /** Array initializer of OSC peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 10298 | #define OSC_BASE_ADDRS { OSC_BASE } |
AnnaBridge | 171:3a7713b1edbc | 10299 | /** Array initializer of OSC peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 10300 | #define OSC_BASE_PTRS { OSC } |
AnnaBridge | 171:3a7713b1edbc | 10301 | |
AnnaBridge | 171:3a7713b1edbc | 10302 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10303 | * @} |
AnnaBridge | 171:3a7713b1edbc | 10304 | */ /* end of group OSC_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 10305 | |
AnnaBridge | 171:3a7713b1edbc | 10306 | |
AnnaBridge | 171:3a7713b1edbc | 10307 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 10308 | -- OTFAD Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 10309 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 10310 | |
AnnaBridge | 171:3a7713b1edbc | 10311 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10312 | * @addtogroup OTFAD_Peripheral_Access_Layer OTFAD Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 10313 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 10314 | */ |
AnnaBridge | 171:3a7713b1edbc | 10315 | |
AnnaBridge | 171:3a7713b1edbc | 10316 | /** OTFAD - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 10317 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 10318 | __IO uint32_t CR; /**< Control Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 10319 | __I uint32_t SR; /**< Status Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 10320 | __IO uint32_t CRC; /**< Cyclic Redundancy Check Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 10321 | uint8_t RESERVED_0[244]; |
AnnaBridge | 171:3a7713b1edbc | 10322 | struct { /* offset: 0x100, array step: 0x40 */ |
AnnaBridge | 171:3a7713b1edbc | 10323 | __IO uint32_t CTX_KEY[4]; /**< AES Key Word0..AES Key Word3, array offset: 0x100, array step: index*0x40, index2*0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 10324 | __IO uint32_t CTX_CTR[2]; /**< AES Counter Word0..AES Counter Word1, array offset: 0x110, array step: index*0x40, index2*0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 10325 | __IO uint32_t CTX_RGD[2]; /**< AES Region Descriptor Word0..AES Region Descriptor Word1, array offset: 0x118, array step: index*0x40, index2*0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 10326 | uint8_t RESERVED_0[32]; |
AnnaBridge | 171:3a7713b1edbc | 10327 | } CTX[4]; |
AnnaBridge | 171:3a7713b1edbc | 10328 | } OTFAD_Type; |
AnnaBridge | 171:3a7713b1edbc | 10329 | |
AnnaBridge | 171:3a7713b1edbc | 10330 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 10331 | -- OTFAD Register Masks |
AnnaBridge | 171:3a7713b1edbc | 10332 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 10333 | |
AnnaBridge | 171:3a7713b1edbc | 10334 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10335 | * @addtogroup OTFAD_Register_Masks OTFAD Register Masks |
AnnaBridge | 171:3a7713b1edbc | 10336 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 10337 | */ |
AnnaBridge | 171:3a7713b1edbc | 10338 | |
AnnaBridge | 171:3a7713b1edbc | 10339 | /*! @name CR - Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 10340 | #define OTFAD_CR_FSVM_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10341 | #define OTFAD_CR_FSVM_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10342 | #define OTFAD_CR_FSVM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FSVM_SHIFT)) & OTFAD_CR_FSVM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10343 | #define OTFAD_CR_FLDM_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 10344 | #define OTFAD_CR_FLDM_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 10345 | #define OTFAD_CR_FLDM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FLDM_SHIFT)) & OTFAD_CR_FLDM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10346 | #define OTFAD_CR_RRAE_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 10347 | #define OTFAD_CR_RRAE_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 10348 | #define OTFAD_CR_RRAE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_RRAE_SHIFT)) & OTFAD_CR_RRAE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10349 | #define OTFAD_CR_CCTX_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 10350 | #define OTFAD_CR_CCTX_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10351 | #define OTFAD_CR_CCTX(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_CCTX_SHIFT)) & OTFAD_CR_CCTX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10352 | #define OTFAD_CR_CRCE_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 10353 | #define OTFAD_CR_CRCE_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 10354 | #define OTFAD_CR_CRCE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_CRCE_SHIFT)) & OTFAD_CR_CRCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10355 | #define OTFAD_CR_CRCI_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 10356 | #define OTFAD_CR_CRCI_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 10357 | #define OTFAD_CR_CRCI(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_CRCI_SHIFT)) & OTFAD_CR_CRCI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10358 | #define OTFAD_CR_GE_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 10359 | #define OTFAD_CR_GE_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 10360 | #define OTFAD_CR_GE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_GE_SHIFT)) & OTFAD_CR_GE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10361 | |
AnnaBridge | 171:3a7713b1edbc | 10362 | /*! @name SR - Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 10363 | #define OTFAD_SR_MDPCP_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10364 | #define OTFAD_SR_MDPCP_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10365 | #define OTFAD_SR_MDPCP(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MDPCP_SHIFT)) & OTFAD_SR_MDPCP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10366 | #define OTFAD_SR_MODE_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 10367 | #define OTFAD_SR_MODE_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10368 | #define OTFAD_SR_MODE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MODE_SHIFT)) & OTFAD_SR_MODE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10369 | #define OTFAD_SR_NCTX_MASK (0xF0U) |
AnnaBridge | 171:3a7713b1edbc | 10370 | #define OTFAD_SR_NCTX_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10371 | #define OTFAD_SR_NCTX(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_NCTX_SHIFT)) & OTFAD_SR_NCTX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10372 | #define OTFAD_SR_HRL_MASK (0xF000000U) |
AnnaBridge | 171:3a7713b1edbc | 10373 | #define OTFAD_SR_HRL_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 10374 | #define OTFAD_SR_HRL(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_HRL_SHIFT)) & OTFAD_SR_HRL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10375 | #define OTFAD_SR_RRAM_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 10376 | #define OTFAD_SR_RRAM_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 10377 | #define OTFAD_SR_RRAM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10378 | #define OTFAD_SR_GEM_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 10379 | #define OTFAD_SR_GEM_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 10380 | #define OTFAD_SR_GEM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_GEM_SHIFT)) & OTFAD_SR_GEM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10381 | |
AnnaBridge | 171:3a7713b1edbc | 10382 | /*! @name CRC - Cyclic Redundancy Check Register */ |
AnnaBridge | 171:3a7713b1edbc | 10383 | #define OTFAD_CRC_CRCD_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10384 | #define OTFAD_CRC_CRCD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10385 | #define OTFAD_CRC_CRCD(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CRC_CRCD_SHIFT)) & OTFAD_CRC_CRCD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10386 | |
AnnaBridge | 171:3a7713b1edbc | 10387 | /*! @name CTX_KEY - AES Key Word0..AES Key Word3 */ |
AnnaBridge | 171:3a7713b1edbc | 10388 | #define OTFAD_CTX_KEY_W0KEY_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10389 | #define OTFAD_CTX_KEY_W0KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10390 | #define OTFAD_CTX_KEY_W0KEY(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_KEY_W0KEY_SHIFT)) & OTFAD_CTX_KEY_W0KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10391 | #define OTFAD_CTX_KEY_W1KEY_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10392 | #define OTFAD_CTX_KEY_W1KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10393 | #define OTFAD_CTX_KEY_W1KEY(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_KEY_W1KEY_SHIFT)) & OTFAD_CTX_KEY_W1KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10394 | #define OTFAD_CTX_KEY_W2KEY_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10395 | #define OTFAD_CTX_KEY_W2KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10396 | #define OTFAD_CTX_KEY_W2KEY(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_KEY_W2KEY_SHIFT)) & OTFAD_CTX_KEY_W2KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10397 | #define OTFAD_CTX_KEY_W3KEY_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10398 | #define OTFAD_CTX_KEY_W3KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10399 | #define OTFAD_CTX_KEY_W3KEY(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_KEY_W3KEY_SHIFT)) & OTFAD_CTX_KEY_W3KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10400 | |
AnnaBridge | 171:3a7713b1edbc | 10401 | /* The count of OTFAD_CTX_KEY */ |
AnnaBridge | 171:3a7713b1edbc | 10402 | #define OTFAD_CTX_KEY_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10403 | |
AnnaBridge | 171:3a7713b1edbc | 10404 | /* The count of OTFAD_CTX_KEY */ |
AnnaBridge | 171:3a7713b1edbc | 10405 | #define OTFAD_CTX_KEY_COUNT2 (4U) |
AnnaBridge | 171:3a7713b1edbc | 10406 | |
AnnaBridge | 171:3a7713b1edbc | 10407 | /*! @name CTX_CTR - AES Counter Word0..AES Counter Word1 */ |
AnnaBridge | 171:3a7713b1edbc | 10408 | #define OTFAD_CTX_CTR_W0CTR_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10409 | #define OTFAD_CTX_CTR_W0CTR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10410 | #define OTFAD_CTX_CTR_W0CTR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_CTR_W0CTR_SHIFT)) & OTFAD_CTX_CTR_W0CTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10411 | #define OTFAD_CTX_CTR_W1CTR_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10412 | #define OTFAD_CTX_CTR_W1CTR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10413 | #define OTFAD_CTX_CTR_W1CTR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_CTR_W1CTR_SHIFT)) & OTFAD_CTX_CTR_W1CTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10414 | |
AnnaBridge | 171:3a7713b1edbc | 10415 | /* The count of OTFAD_CTX_CTR */ |
AnnaBridge | 171:3a7713b1edbc | 10416 | #define OTFAD_CTX_CTR_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10417 | |
AnnaBridge | 171:3a7713b1edbc | 10418 | /* The count of OTFAD_CTX_CTR */ |
AnnaBridge | 171:3a7713b1edbc | 10419 | #define OTFAD_CTX_CTR_COUNT2 (2U) |
AnnaBridge | 171:3a7713b1edbc | 10420 | |
AnnaBridge | 171:3a7713b1edbc | 10421 | /*! @name CTX_RGD - AES Region Descriptor Word0..AES Region Descriptor Word1 */ |
AnnaBridge | 171:3a7713b1edbc | 10422 | #define OTFAD_CTX_RGD_VLD_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10423 | #define OTFAD_CTX_RGD_VLD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10424 | #define OTFAD_CTX_RGD_VLD(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_RGD_VLD_SHIFT)) & OTFAD_CTX_RGD_VLD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10425 | #define OTFAD_CTX_RGD_ADE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10426 | #define OTFAD_CTX_RGD_ADE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10427 | #define OTFAD_CTX_RGD_ADE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_RGD_ADE_SHIFT)) & OTFAD_CTX_RGD_ADE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10428 | #define OTFAD_CTX_RGD_RO_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10429 | #define OTFAD_CTX_RGD_RO_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10430 | #define OTFAD_CTX_RGD_RO(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_RGD_RO_SHIFT)) & OTFAD_CTX_RGD_RO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10431 | #define OTFAD_CTX_RGD_ENDADDR_MASK (0xFFFFFC00U) |
AnnaBridge | 171:3a7713b1edbc | 10432 | #define OTFAD_CTX_RGD_ENDADDR_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 10433 | #define OTFAD_CTX_RGD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_RGD_ENDADDR_SHIFT)) & OTFAD_CTX_RGD_ENDADDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10434 | #define OTFAD_CTX_RGD_SRTADDR_MASK (0xFFFFFC00U) |
AnnaBridge | 171:3a7713b1edbc | 10435 | #define OTFAD_CTX_RGD_SRTADDR_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 10436 | #define OTFAD_CTX_RGD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_RGD_SRTADDR_SHIFT)) & OTFAD_CTX_RGD_SRTADDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10437 | |
AnnaBridge | 171:3a7713b1edbc | 10438 | /* The count of OTFAD_CTX_RGD */ |
AnnaBridge | 171:3a7713b1edbc | 10439 | #define OTFAD_CTX_RGD_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10440 | |
AnnaBridge | 171:3a7713b1edbc | 10441 | /* The count of OTFAD_CTX_RGD */ |
AnnaBridge | 171:3a7713b1edbc | 10442 | #define OTFAD_CTX_RGD_COUNT2 (2U) |
AnnaBridge | 171:3a7713b1edbc | 10443 | |
AnnaBridge | 171:3a7713b1edbc | 10444 | |
AnnaBridge | 171:3a7713b1edbc | 10445 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10446 | * @} |
AnnaBridge | 171:3a7713b1edbc | 10447 | */ /* end of group OTFAD_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 10448 | |
AnnaBridge | 171:3a7713b1edbc | 10449 | |
AnnaBridge | 171:3a7713b1edbc | 10450 | /* OTFAD - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 10451 | /** Peripheral OTFAD base address */ |
AnnaBridge | 171:3a7713b1edbc | 10452 | #define OTFAD_BASE (0x400DAC00u) |
AnnaBridge | 171:3a7713b1edbc | 10453 | /** Peripheral OTFAD base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 10454 | #define OTFAD ((OTFAD_Type *)OTFAD_BASE) |
AnnaBridge | 171:3a7713b1edbc | 10455 | /** Array initializer of OTFAD peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 10456 | #define OTFAD_BASE_ADDRS { OTFAD_BASE } |
AnnaBridge | 171:3a7713b1edbc | 10457 | /** Array initializer of OTFAD peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 10458 | #define OTFAD_BASE_PTRS { OTFAD } |
AnnaBridge | 171:3a7713b1edbc | 10459 | |
AnnaBridge | 171:3a7713b1edbc | 10460 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10461 | * @} |
AnnaBridge | 171:3a7713b1edbc | 10462 | */ /* end of group OTFAD_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 10463 | |
AnnaBridge | 171:3a7713b1edbc | 10464 | |
AnnaBridge | 171:3a7713b1edbc | 10465 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 10466 | -- PDB Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 10467 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 10468 | |
AnnaBridge | 171:3a7713b1edbc | 10469 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10470 | * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 10471 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 10472 | */ |
AnnaBridge | 171:3a7713b1edbc | 10473 | |
AnnaBridge | 171:3a7713b1edbc | 10474 | /** PDB - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 10475 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 10476 | __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 10477 | __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 10478 | __I uint32_t CNT; /**< Counter register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 10479 | __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 10480 | struct { /* offset: 0x10, array step: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 10481 | __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 10482 | __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 10483 | __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x10, index2*0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 10484 | } CH[1]; |
AnnaBridge | 171:3a7713b1edbc | 10485 | uint8_t RESERVED_0[304]; |
AnnaBridge | 171:3a7713b1edbc | 10486 | struct { /* offset: 0x150, array step: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 10487 | __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 10488 | __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 10489 | } DAC[1]; |
AnnaBridge | 171:3a7713b1edbc | 10490 | uint8_t RESERVED_1[56]; |
AnnaBridge | 171:3a7713b1edbc | 10491 | __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */ |
AnnaBridge | 171:3a7713b1edbc | 10492 | __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 10493 | } PDB_Type; |
AnnaBridge | 171:3a7713b1edbc | 10494 | |
AnnaBridge | 171:3a7713b1edbc | 10495 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 10496 | -- PDB Register Masks |
AnnaBridge | 171:3a7713b1edbc | 10497 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 10498 | |
AnnaBridge | 171:3a7713b1edbc | 10499 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10500 | * @addtogroup PDB_Register_Masks PDB Register Masks |
AnnaBridge | 171:3a7713b1edbc | 10501 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 10502 | */ |
AnnaBridge | 171:3a7713b1edbc | 10503 | |
AnnaBridge | 171:3a7713b1edbc | 10504 | /*! @name SC - Status and Control register */ |
AnnaBridge | 171:3a7713b1edbc | 10505 | #define PDB_SC_LDOK_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10506 | #define PDB_SC_LDOK_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10507 | #define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10508 | #define PDB_SC_CONT_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10509 | #define PDB_SC_CONT_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10510 | #define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10511 | #define PDB_SC_MULT_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 10512 | #define PDB_SC_MULT_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10513 | #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10514 | #define PDB_SC_PDBIE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10515 | #define PDB_SC_PDBIE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10516 | #define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10517 | #define PDB_SC_PDBIF_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 10518 | #define PDB_SC_PDBIF_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10519 | #define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10520 | #define PDB_SC_PDBEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 10521 | #define PDB_SC_PDBEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 10522 | #define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10523 | #define PDB_SC_TRGSEL_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 10524 | #define PDB_SC_TRGSEL_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 10525 | #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10526 | #define PDB_SC_PRESCALER_MASK (0x7000U) |
AnnaBridge | 171:3a7713b1edbc | 10527 | #define PDB_SC_PRESCALER_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 10528 | #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10529 | #define PDB_SC_DMAEN_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 10530 | #define PDB_SC_DMAEN_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 10531 | #define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10532 | #define PDB_SC_SWTRIG_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 10533 | #define PDB_SC_SWTRIG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10534 | #define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10535 | #define PDB_SC_PDBEIE_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 10536 | #define PDB_SC_PDBEIE_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 10537 | #define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10538 | #define PDB_SC_LDMOD_MASK (0xC0000U) |
AnnaBridge | 171:3a7713b1edbc | 10539 | #define PDB_SC_LDMOD_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 10540 | #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10541 | |
AnnaBridge | 171:3a7713b1edbc | 10542 | /*! @name MOD - Modulus register */ |
AnnaBridge | 171:3a7713b1edbc | 10543 | #define PDB_MOD_MOD_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10544 | #define PDB_MOD_MOD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10545 | #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10546 | |
AnnaBridge | 171:3a7713b1edbc | 10547 | /*! @name CNT - Counter register */ |
AnnaBridge | 171:3a7713b1edbc | 10548 | #define PDB_CNT_CNT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10549 | #define PDB_CNT_CNT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10550 | #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10551 | |
AnnaBridge | 171:3a7713b1edbc | 10552 | /*! @name IDLY - Interrupt Delay register */ |
AnnaBridge | 171:3a7713b1edbc | 10553 | #define PDB_IDLY_IDLY_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10554 | #define PDB_IDLY_IDLY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10555 | #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10556 | |
AnnaBridge | 171:3a7713b1edbc | 10557 | /*! @name C1 - Channel n Control register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 10558 | #define PDB_C1_EN_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10559 | #define PDB_C1_EN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10560 | #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10561 | #define PDB_C1_TOS_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 10562 | #define PDB_C1_TOS_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 10563 | #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10564 | #define PDB_C1_BB_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10565 | #define PDB_C1_BB_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10566 | #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10567 | |
AnnaBridge | 171:3a7713b1edbc | 10568 | /* The count of PDB_C1 */ |
AnnaBridge | 171:3a7713b1edbc | 10569 | #define PDB_C1_COUNT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10570 | |
AnnaBridge | 171:3a7713b1edbc | 10571 | /*! @name S - Channel n Status register */ |
AnnaBridge | 171:3a7713b1edbc | 10572 | #define PDB_S_ERR_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10573 | #define PDB_S_ERR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10574 | #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10575 | #define PDB_S_CF_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10576 | #define PDB_S_CF_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10577 | #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10578 | |
AnnaBridge | 171:3a7713b1edbc | 10579 | /* The count of PDB_S */ |
AnnaBridge | 171:3a7713b1edbc | 10580 | #define PDB_S_COUNT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10581 | |
AnnaBridge | 171:3a7713b1edbc | 10582 | /*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */ |
AnnaBridge | 171:3a7713b1edbc | 10583 | #define PDB_DLY_DLY_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10584 | #define PDB_DLY_DLY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10585 | #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10586 | |
AnnaBridge | 171:3a7713b1edbc | 10587 | /* The count of PDB_DLY */ |
AnnaBridge | 171:3a7713b1edbc | 10588 | #define PDB_DLY_COUNT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10589 | |
AnnaBridge | 171:3a7713b1edbc | 10590 | /* The count of PDB_DLY */ |
AnnaBridge | 171:3a7713b1edbc | 10591 | #define PDB_DLY_COUNT2 (2U) |
AnnaBridge | 171:3a7713b1edbc | 10592 | |
AnnaBridge | 171:3a7713b1edbc | 10593 | /*! @name INTC - DAC Interval Trigger n Control register */ |
AnnaBridge | 171:3a7713b1edbc | 10594 | #define PDB_INTC_TOE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10595 | #define PDB_INTC_TOE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10596 | #define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10597 | #define PDB_INTC_EXT_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10598 | #define PDB_INTC_EXT_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10599 | #define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10600 | |
AnnaBridge | 171:3a7713b1edbc | 10601 | /* The count of PDB_INTC */ |
AnnaBridge | 171:3a7713b1edbc | 10602 | #define PDB_INTC_COUNT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10603 | |
AnnaBridge | 171:3a7713b1edbc | 10604 | /*! @name INT - DAC Interval n register */ |
AnnaBridge | 171:3a7713b1edbc | 10605 | #define PDB_INT_INT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10606 | #define PDB_INT_INT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10607 | #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10608 | |
AnnaBridge | 171:3a7713b1edbc | 10609 | /* The count of PDB_INT */ |
AnnaBridge | 171:3a7713b1edbc | 10610 | #define PDB_INT_COUNT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10611 | |
AnnaBridge | 171:3a7713b1edbc | 10612 | /*! @name POEN - Pulse-Out n Enable register */ |
AnnaBridge | 171:3a7713b1edbc | 10613 | #define PDB_POEN_POEN_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10614 | #define PDB_POEN_POEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10615 | #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10616 | |
AnnaBridge | 171:3a7713b1edbc | 10617 | /*! @name PODLY - Pulse-Out n Delay register */ |
AnnaBridge | 171:3a7713b1edbc | 10618 | #define PDB_PODLY_DLY2_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10619 | #define PDB_PODLY_DLY2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10620 | #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10621 | #define PDB_PODLY_DLY1_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10622 | #define PDB_PODLY_DLY1_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10623 | #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10624 | |
AnnaBridge | 171:3a7713b1edbc | 10625 | /* The count of PDB_PODLY */ |
AnnaBridge | 171:3a7713b1edbc | 10626 | #define PDB_PODLY_COUNT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10627 | |
AnnaBridge | 171:3a7713b1edbc | 10628 | |
AnnaBridge | 171:3a7713b1edbc | 10629 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10630 | * @} |
AnnaBridge | 171:3a7713b1edbc | 10631 | */ /* end of group PDB_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 10632 | |
AnnaBridge | 171:3a7713b1edbc | 10633 | |
AnnaBridge | 171:3a7713b1edbc | 10634 | /* PDB - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 10635 | /** Peripheral PDB0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 10636 | #define PDB0_BASE (0x40036000u) |
AnnaBridge | 171:3a7713b1edbc | 10637 | /** Peripheral PDB0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 10638 | #define PDB0 ((PDB_Type *)PDB0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 10639 | /** Array initializer of PDB peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 10640 | #define PDB_BASE_ADDRS { PDB0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 10641 | /** Array initializer of PDB peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 10642 | #define PDB_BASE_PTRS { PDB0 } |
AnnaBridge | 171:3a7713b1edbc | 10643 | /** Interrupt vectors for the PDB peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 10644 | #define PDB_IRQS { PDB0_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 10645 | |
AnnaBridge | 171:3a7713b1edbc | 10646 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10647 | * @} |
AnnaBridge | 171:3a7713b1edbc | 10648 | */ /* end of group PDB_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 10649 | |
AnnaBridge | 171:3a7713b1edbc | 10650 | |
AnnaBridge | 171:3a7713b1edbc | 10651 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 10652 | -- PIT Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 10653 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 10654 | |
AnnaBridge | 171:3a7713b1edbc | 10655 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10656 | * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 10657 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 10658 | */ |
AnnaBridge | 171:3a7713b1edbc | 10659 | |
AnnaBridge | 171:3a7713b1edbc | 10660 | /** PIT - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 10661 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 10662 | __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 10663 | uint8_t RESERVED_0[252]; |
AnnaBridge | 171:3a7713b1edbc | 10664 | struct { /* offset: 0x100, array step: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 10665 | __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 10666 | __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 10667 | __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 10668 | __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 10669 | } CHANNEL[4]; |
AnnaBridge | 171:3a7713b1edbc | 10670 | } PIT_Type; |
AnnaBridge | 171:3a7713b1edbc | 10671 | |
AnnaBridge | 171:3a7713b1edbc | 10672 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 10673 | -- PIT Register Masks |
AnnaBridge | 171:3a7713b1edbc | 10674 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 10675 | |
AnnaBridge | 171:3a7713b1edbc | 10676 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10677 | * @addtogroup PIT_Register_Masks PIT Register Masks |
AnnaBridge | 171:3a7713b1edbc | 10678 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 10679 | */ |
AnnaBridge | 171:3a7713b1edbc | 10680 | |
AnnaBridge | 171:3a7713b1edbc | 10681 | /*! @name MCR - PIT Module Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 10682 | #define PIT_MCR_FRZ_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10683 | #define PIT_MCR_FRZ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10684 | #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10685 | #define PIT_MCR_MDIS_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10686 | #define PIT_MCR_MDIS_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10687 | #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10688 | |
AnnaBridge | 171:3a7713b1edbc | 10689 | /*! @name LDVAL - Timer Load Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 10690 | #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10691 | #define PIT_LDVAL_TSV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10692 | #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10693 | |
AnnaBridge | 171:3a7713b1edbc | 10694 | /* The count of PIT_LDVAL */ |
AnnaBridge | 171:3a7713b1edbc | 10695 | #define PIT_LDVAL_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10696 | |
AnnaBridge | 171:3a7713b1edbc | 10697 | /*! @name CVAL - Current Timer Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 10698 | #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10699 | #define PIT_CVAL_TVL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10700 | #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10701 | |
AnnaBridge | 171:3a7713b1edbc | 10702 | /* The count of PIT_CVAL */ |
AnnaBridge | 171:3a7713b1edbc | 10703 | #define PIT_CVAL_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10704 | |
AnnaBridge | 171:3a7713b1edbc | 10705 | /*! @name TCTRL - Timer Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 10706 | #define PIT_TCTRL_TEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10707 | #define PIT_TCTRL_TEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10708 | #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10709 | #define PIT_TCTRL_TIE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10710 | #define PIT_TCTRL_TIE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10711 | #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10712 | #define PIT_TCTRL_CHN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10713 | #define PIT_TCTRL_CHN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10714 | #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10715 | |
AnnaBridge | 171:3a7713b1edbc | 10716 | /* The count of PIT_TCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 10717 | #define PIT_TCTRL_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10718 | |
AnnaBridge | 171:3a7713b1edbc | 10719 | /*! @name TFLG - Timer Flag Register */ |
AnnaBridge | 171:3a7713b1edbc | 10720 | #define PIT_TFLG_TIF_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10721 | #define PIT_TFLG_TIF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10722 | #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10723 | |
AnnaBridge | 171:3a7713b1edbc | 10724 | /* The count of PIT_TFLG */ |
AnnaBridge | 171:3a7713b1edbc | 10725 | #define PIT_TFLG_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10726 | |
AnnaBridge | 171:3a7713b1edbc | 10727 | |
AnnaBridge | 171:3a7713b1edbc | 10728 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10729 | * @} |
AnnaBridge | 171:3a7713b1edbc | 10730 | */ /* end of group PIT_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 10731 | |
AnnaBridge | 171:3a7713b1edbc | 10732 | |
AnnaBridge | 171:3a7713b1edbc | 10733 | /* PIT - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 10734 | /** Peripheral PIT0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 10735 | #define PIT0_BASE (0x40037000u) |
AnnaBridge | 171:3a7713b1edbc | 10736 | /** Peripheral PIT0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 10737 | #define PIT0 ((PIT_Type *)PIT0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 10738 | /** Array initializer of PIT peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 10739 | #define PIT_BASE_ADDRS { PIT0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 10740 | /** Array initializer of PIT peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 10741 | #define PIT_BASE_PTRS { PIT0 } |
AnnaBridge | 171:3a7713b1edbc | 10742 | /** Interrupt vectors for the PIT peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 10743 | #define PIT_IRQS { PIT0CH0_IRQn, PIT0CH1_IRQn, PIT0CH2_IRQn, PIT0CH3_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 10744 | |
AnnaBridge | 171:3a7713b1edbc | 10745 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10746 | * @} |
AnnaBridge | 171:3a7713b1edbc | 10747 | */ /* end of group PIT_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 10748 | |
AnnaBridge | 171:3a7713b1edbc | 10749 | |
AnnaBridge | 171:3a7713b1edbc | 10750 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 10751 | -- PMC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 10752 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 10753 | |
AnnaBridge | 171:3a7713b1edbc | 10754 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10755 | * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 10756 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 10757 | */ |
AnnaBridge | 171:3a7713b1edbc | 10758 | |
AnnaBridge | 171:3a7713b1edbc | 10759 | /** PMC - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 10760 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 10761 | __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 10762 | __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 10763 | __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 10764 | uint8_t RESERVED_0[8]; |
AnnaBridge | 171:3a7713b1edbc | 10765 | __IO uint8_t HVDSC1; /**< High Voltage Detect Status And Control 1 register, offset: 0xB */ |
AnnaBridge | 171:3a7713b1edbc | 10766 | } PMC_Type; |
AnnaBridge | 171:3a7713b1edbc | 10767 | |
AnnaBridge | 171:3a7713b1edbc | 10768 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 10769 | -- PMC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 10770 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 10771 | |
AnnaBridge | 171:3a7713b1edbc | 10772 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10773 | * @addtogroup PMC_Register_Masks PMC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 10774 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 10775 | */ |
AnnaBridge | 171:3a7713b1edbc | 10776 | |
AnnaBridge | 171:3a7713b1edbc | 10777 | /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */ |
AnnaBridge | 171:3a7713b1edbc | 10778 | #define PMC_LVDSC1_LVDV_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 10779 | #define PMC_LVDSC1_LVDV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10780 | #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10781 | #define PMC_LVDSC1_LVDRE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 10782 | #define PMC_LVDSC1_LVDRE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10783 | #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10784 | #define PMC_LVDSC1_LVDIE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10785 | #define PMC_LVDSC1_LVDIE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10786 | #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10787 | #define PMC_LVDSC1_LVDACK_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 10788 | #define PMC_LVDSC1_LVDACK_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10789 | #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10790 | #define PMC_LVDSC1_LVDF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 10791 | #define PMC_LVDSC1_LVDF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 10792 | #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10793 | |
AnnaBridge | 171:3a7713b1edbc | 10794 | /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */ |
AnnaBridge | 171:3a7713b1edbc | 10795 | #define PMC_LVDSC2_LVWV_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 10796 | #define PMC_LVDSC2_LVWV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10797 | #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10798 | #define PMC_LVDSC2_LVWIE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10799 | #define PMC_LVDSC2_LVWIE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10800 | #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10801 | #define PMC_LVDSC2_LVWACK_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 10802 | #define PMC_LVDSC2_LVWACK_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10803 | #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10804 | #define PMC_LVDSC2_LVWF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 10805 | #define PMC_LVDSC2_LVWF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 10806 | #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10807 | |
AnnaBridge | 171:3a7713b1edbc | 10808 | /*! @name REGSC - Regulator Status And Control register */ |
AnnaBridge | 171:3a7713b1edbc | 10809 | #define PMC_REGSC_BGBE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10810 | #define PMC_REGSC_BGBE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10811 | #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10812 | #define PMC_REGSC_REGONS_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10813 | #define PMC_REGSC_REGONS_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10814 | #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10815 | #define PMC_REGSC_ACKISO_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 10816 | #define PMC_REGSC_ACKISO_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 10817 | #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10818 | #define PMC_REGSC_BGEN_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 10819 | #define PMC_REGSC_BGEN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10820 | #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10821 | |
AnnaBridge | 171:3a7713b1edbc | 10822 | /*! @name HVDSC1 - High Voltage Detect Status And Control 1 register */ |
AnnaBridge | 171:3a7713b1edbc | 10823 | #define PMC_HVDSC1_HVDV_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10824 | #define PMC_HVDSC1_HVDV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10825 | #define PMC_HVDSC1_HVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDV_SHIFT)) & PMC_HVDSC1_HVDV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10826 | #define PMC_HVDSC1_HVDRE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 10827 | #define PMC_HVDSC1_HVDRE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10828 | #define PMC_HVDSC1_HVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDRE_SHIFT)) & PMC_HVDSC1_HVDRE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10829 | #define PMC_HVDSC1_HVDIE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10830 | #define PMC_HVDSC1_HVDIE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10831 | #define PMC_HVDSC1_HVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDIE_SHIFT)) & PMC_HVDSC1_HVDIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10832 | #define PMC_HVDSC1_HVDACK_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 10833 | #define PMC_HVDSC1_HVDACK_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10834 | #define PMC_HVDSC1_HVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDACK_SHIFT)) & PMC_HVDSC1_HVDACK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10835 | #define PMC_HVDSC1_HVDF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 10836 | #define PMC_HVDSC1_HVDF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 10837 | #define PMC_HVDSC1_HVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDF_SHIFT)) & PMC_HVDSC1_HVDF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10838 | |
AnnaBridge | 171:3a7713b1edbc | 10839 | |
AnnaBridge | 171:3a7713b1edbc | 10840 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10841 | * @} |
AnnaBridge | 171:3a7713b1edbc | 10842 | */ /* end of group PMC_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 10843 | |
AnnaBridge | 171:3a7713b1edbc | 10844 | |
AnnaBridge | 171:3a7713b1edbc | 10845 | /* PMC - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 10846 | /** Peripheral PMC base address */ |
AnnaBridge | 171:3a7713b1edbc | 10847 | #define PMC_BASE (0x4007D000u) |
AnnaBridge | 171:3a7713b1edbc | 10848 | /** Peripheral PMC base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 10849 | #define PMC ((PMC_Type *)PMC_BASE) |
AnnaBridge | 171:3a7713b1edbc | 10850 | /** Array initializer of PMC peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 10851 | #define PMC_BASE_ADDRS { PMC_BASE } |
AnnaBridge | 171:3a7713b1edbc | 10852 | /** Array initializer of PMC peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 10853 | #define PMC_BASE_PTRS { PMC } |
AnnaBridge | 171:3a7713b1edbc | 10854 | /** Interrupt vectors for the PMC peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 10855 | #define PMC_IRQS { LVD_LVW_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 10856 | |
AnnaBridge | 171:3a7713b1edbc | 10857 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10858 | * @} |
AnnaBridge | 171:3a7713b1edbc | 10859 | */ /* end of group PMC_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 10860 | |
AnnaBridge | 171:3a7713b1edbc | 10861 | |
AnnaBridge | 171:3a7713b1edbc | 10862 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 10863 | -- PORT Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 10864 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 10865 | |
AnnaBridge | 171:3a7713b1edbc | 10866 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10867 | * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 10868 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 10869 | */ |
AnnaBridge | 171:3a7713b1edbc | 10870 | |
AnnaBridge | 171:3a7713b1edbc | 10871 | /** PORT - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 10872 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 10873 | __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 10874 | __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ |
AnnaBridge | 171:3a7713b1edbc | 10875 | __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ |
AnnaBridge | 171:3a7713b1edbc | 10876 | uint8_t RESERVED_0[24]; |
AnnaBridge | 171:3a7713b1edbc | 10877 | __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ |
AnnaBridge | 171:3a7713b1edbc | 10878 | uint8_t RESERVED_1[28]; |
AnnaBridge | 171:3a7713b1edbc | 10879 | __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */ |
AnnaBridge | 171:3a7713b1edbc | 10880 | __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */ |
AnnaBridge | 171:3a7713b1edbc | 10881 | __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */ |
AnnaBridge | 171:3a7713b1edbc | 10882 | } PORT_Type; |
AnnaBridge | 171:3a7713b1edbc | 10883 | |
AnnaBridge | 171:3a7713b1edbc | 10884 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 10885 | -- PORT Register Masks |
AnnaBridge | 171:3a7713b1edbc | 10886 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 10887 | |
AnnaBridge | 171:3a7713b1edbc | 10888 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10889 | * @addtogroup PORT_Register_Masks PORT Register Masks |
AnnaBridge | 171:3a7713b1edbc | 10890 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 10891 | */ |
AnnaBridge | 171:3a7713b1edbc | 10892 | |
AnnaBridge | 171:3a7713b1edbc | 10893 | /*! @name PCR - Pin Control Register n */ |
AnnaBridge | 171:3a7713b1edbc | 10894 | #define PORT_PCR_PS_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10895 | #define PORT_PCR_PS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10896 | #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10897 | #define PORT_PCR_PE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10898 | #define PORT_PCR_PE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10899 | #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10900 | #define PORT_PCR_SRE_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10901 | #define PORT_PCR_SRE_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10902 | #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10903 | #define PORT_PCR_PFE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 10904 | #define PORT_PCR_PFE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10905 | #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10906 | #define PORT_PCR_ODE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10907 | #define PORT_PCR_ODE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10908 | #define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10909 | #define PORT_PCR_DSE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 10910 | #define PORT_PCR_DSE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10911 | #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10912 | #define PORT_PCR_MUX_MASK (0x700U) |
AnnaBridge | 171:3a7713b1edbc | 10913 | #define PORT_PCR_MUX_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 10914 | #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10915 | #define PORT_PCR_LK_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 10916 | #define PORT_PCR_LK_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 10917 | #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10918 | #define PORT_PCR_IRQC_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10919 | #define PORT_PCR_IRQC_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10920 | #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10921 | #define PORT_PCR_ISF_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 10922 | #define PORT_PCR_ISF_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 10923 | #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10924 | |
AnnaBridge | 171:3a7713b1edbc | 10925 | /* The count of PORT_PCR */ |
AnnaBridge | 171:3a7713b1edbc | 10926 | #define PORT_PCR_COUNT (32U) |
AnnaBridge | 171:3a7713b1edbc | 10927 | |
AnnaBridge | 171:3a7713b1edbc | 10928 | /*! @name GPCLR - Global Pin Control Low Register */ |
AnnaBridge | 171:3a7713b1edbc | 10929 | #define PORT_GPCLR_GPWD_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10930 | #define PORT_GPCLR_GPWD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10931 | #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10932 | #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10933 | #define PORT_GPCLR_GPWE_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10934 | #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10935 | |
AnnaBridge | 171:3a7713b1edbc | 10936 | /*! @name GPCHR - Global Pin Control High Register */ |
AnnaBridge | 171:3a7713b1edbc | 10937 | #define PORT_GPCHR_GPWD_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10938 | #define PORT_GPCHR_GPWD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10939 | #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10940 | #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10941 | #define PORT_GPCHR_GPWE_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10942 | #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10943 | |
AnnaBridge | 171:3a7713b1edbc | 10944 | /*! @name ISFR - Interrupt Status Flag Register */ |
AnnaBridge | 171:3a7713b1edbc | 10945 | #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10946 | #define PORT_ISFR_ISF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10947 | #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10948 | |
AnnaBridge | 171:3a7713b1edbc | 10949 | /*! @name DFER - Digital Filter Enable Register */ |
AnnaBridge | 171:3a7713b1edbc | 10950 | #define PORT_DFER_DFE_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10951 | #define PORT_DFER_DFE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10952 | #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10953 | |
AnnaBridge | 171:3a7713b1edbc | 10954 | /*! @name DFCR - Digital Filter Clock Register */ |
AnnaBridge | 171:3a7713b1edbc | 10955 | #define PORT_DFCR_CS_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10956 | #define PORT_DFCR_CS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10957 | #define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10958 | |
AnnaBridge | 171:3a7713b1edbc | 10959 | /*! @name DFWR - Digital Filter Width Register */ |
AnnaBridge | 171:3a7713b1edbc | 10960 | #define PORT_DFWR_FILT_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 10961 | #define PORT_DFWR_FILT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10962 | #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10963 | |
AnnaBridge | 171:3a7713b1edbc | 10964 | |
AnnaBridge | 171:3a7713b1edbc | 10965 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10966 | * @} |
AnnaBridge | 171:3a7713b1edbc | 10967 | */ /* end of group PORT_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 10968 | |
AnnaBridge | 171:3a7713b1edbc | 10969 | |
AnnaBridge | 171:3a7713b1edbc | 10970 | /* PORT - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 10971 | /** Peripheral PORTA base address */ |
AnnaBridge | 171:3a7713b1edbc | 10972 | #define PORTA_BASE (0x40049000u) |
AnnaBridge | 171:3a7713b1edbc | 10973 | /** Peripheral PORTA base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 10974 | #define PORTA ((PORT_Type *)PORTA_BASE) |
AnnaBridge | 171:3a7713b1edbc | 10975 | /** Peripheral PORTB base address */ |
AnnaBridge | 171:3a7713b1edbc | 10976 | #define PORTB_BASE (0x4004A000u) |
AnnaBridge | 171:3a7713b1edbc | 10977 | /** Peripheral PORTB base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 10978 | #define PORTB ((PORT_Type *)PORTB_BASE) |
AnnaBridge | 171:3a7713b1edbc | 10979 | /** Peripheral PORTC base address */ |
AnnaBridge | 171:3a7713b1edbc | 10980 | #define PORTC_BASE (0x4004B000u) |
AnnaBridge | 171:3a7713b1edbc | 10981 | /** Peripheral PORTC base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 10982 | #define PORTC ((PORT_Type *)PORTC_BASE) |
AnnaBridge | 171:3a7713b1edbc | 10983 | /** Peripheral PORTD base address */ |
AnnaBridge | 171:3a7713b1edbc | 10984 | #define PORTD_BASE (0x4004C000u) |
AnnaBridge | 171:3a7713b1edbc | 10985 | /** Peripheral PORTD base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 10986 | #define PORTD ((PORT_Type *)PORTD_BASE) |
AnnaBridge | 171:3a7713b1edbc | 10987 | /** Peripheral PORTE base address */ |
AnnaBridge | 171:3a7713b1edbc | 10988 | #define PORTE_BASE (0x4004D000u) |
AnnaBridge | 171:3a7713b1edbc | 10989 | /** Peripheral PORTE base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 10990 | #define PORTE ((PORT_Type *)PORTE_BASE) |
AnnaBridge | 171:3a7713b1edbc | 10991 | /** Array initializer of PORT peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 10992 | #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE } |
AnnaBridge | 171:3a7713b1edbc | 10993 | /** Array initializer of PORT peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 10994 | #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE } |
AnnaBridge | 171:3a7713b1edbc | 10995 | /** Interrupt vectors for the PORT peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 10996 | #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 10997 | |
AnnaBridge | 171:3a7713b1edbc | 10998 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10999 | * @} |
AnnaBridge | 171:3a7713b1edbc | 11000 | */ /* end of group PORT_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 11001 | |
AnnaBridge | 171:3a7713b1edbc | 11002 | |
AnnaBridge | 171:3a7713b1edbc | 11003 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 11004 | -- QuadSPI Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 11005 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 11006 | |
AnnaBridge | 171:3a7713b1edbc | 11007 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11008 | * @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 11009 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 11010 | */ |
AnnaBridge | 171:3a7713b1edbc | 11011 | |
AnnaBridge | 171:3a7713b1edbc | 11012 | /** QuadSPI - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 11013 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 11014 | __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 11015 | uint8_t RESERVED_0[4]; |
AnnaBridge | 171:3a7713b1edbc | 11016 | union { /* offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 11017 | __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 11018 | struct { |
AnnaBridge | 171:3a7713b1edbc | 11019 | __IO uint16_t IDATZ; /**< IP data transfer size, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 11020 | __IO uint8_t PAR_EN; /**< IP data transfer size, offset: 0xA */ |
AnnaBridge | 171:3a7713b1edbc | 11021 | __IO uint8_t SEQID; /**< IP data transfer size, offset: 0xB */ |
AnnaBridge | 171:3a7713b1edbc | 11022 | } IPCR_ACCESSBIT; |
AnnaBridge | 171:3a7713b1edbc | 11023 | }; |
AnnaBridge | 171:3a7713b1edbc | 11024 | __IO uint32_t FLSHCR; /**< Flash Configuration Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 11025 | __IO uint32_t BUF0CR; /**< Buffer0 Configuration Register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 11026 | __IO uint32_t BUF1CR; /**< Buffer1 Configuration Register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 11027 | __IO uint32_t BUF2CR; /**< Buffer2 Configuration Register, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 11028 | __IO uint32_t BUF3CR; /**< Buffer3 Configuration Register, offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 11029 | __IO uint32_t BFGENCR; /**< Buffer Generic Configuration Register, offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 11030 | __IO uint32_t SOCCR; /**< SOC Configuration Register, offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 11031 | uint8_t RESERVED_1[8]; |
AnnaBridge | 171:3a7713b1edbc | 11032 | __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ |
AnnaBridge | 171:3a7713b1edbc | 11033 | __IO uint32_t BUF1IND; /**< Buffer1 Top Index Register, offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 11034 | __IO uint32_t BUF2IND; /**< Buffer2 Top Index Register, offset: 0x38 */ |
AnnaBridge | 171:3a7713b1edbc | 11035 | uint8_t RESERVED_2[196]; |
AnnaBridge | 171:3a7713b1edbc | 11036 | __IO uint32_t SFAR; /**< Serial Flash Address Register, offset: 0x100 */ |
AnnaBridge | 171:3a7713b1edbc | 11037 | __IO uint32_t SFACR; /**< Serial Flash Address Configuration Register, offset: 0x104 */ |
AnnaBridge | 171:3a7713b1edbc | 11038 | __IO uint32_t SMPR; /**< Sampling Register, offset: 0x108 */ |
AnnaBridge | 171:3a7713b1edbc | 11039 | __I uint32_t RBSR; /**< RX Buffer Status Register, offset: 0x10C */ |
AnnaBridge | 171:3a7713b1edbc | 11040 | __IO uint32_t RBCT; /**< RX Buffer Control Register, offset: 0x110 */ |
AnnaBridge | 171:3a7713b1edbc | 11041 | uint8_t RESERVED_3[60]; |
AnnaBridge | 171:3a7713b1edbc | 11042 | __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ |
AnnaBridge | 171:3a7713b1edbc | 11043 | __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ |
AnnaBridge | 171:3a7713b1edbc | 11044 | __IO uint32_t TBCT; /**< Tx Buffer Control Register, offset: 0x158 */ |
AnnaBridge | 171:3a7713b1edbc | 11045 | __I uint32_t SR; /**< Status Register, offset: 0x15C */ |
AnnaBridge | 171:3a7713b1edbc | 11046 | __IO uint32_t FR; /**< Flag Register, offset: 0x160 */ |
AnnaBridge | 171:3a7713b1edbc | 11047 | __IO uint32_t RSER; /**< Interrupt and DMA Request Select and Enable Register, offset: 0x164 */ |
AnnaBridge | 171:3a7713b1edbc | 11048 | __I uint32_t SPNDST; /**< Sequence Suspend Status Register, offset: 0x168 */ |
AnnaBridge | 171:3a7713b1edbc | 11049 | __IO uint32_t SPTRCLR; /**< Sequence Pointer Clear Register, offset: 0x16C */ |
AnnaBridge | 171:3a7713b1edbc | 11050 | uint8_t RESERVED_4[16]; |
AnnaBridge | 171:3a7713b1edbc | 11051 | __IO uint32_t SFA1AD; /**< Serial Flash A1 Top Address, offset: 0x180 */ |
AnnaBridge | 171:3a7713b1edbc | 11052 | __IO uint32_t SFA2AD; /**< Serial Flash A2 Top Address, offset: 0x184 */ |
AnnaBridge | 171:3a7713b1edbc | 11053 | __IO uint32_t SFB1AD; /**< Serial Flash B1Top Address, offset: 0x188 */ |
AnnaBridge | 171:3a7713b1edbc | 11054 | __IO uint32_t SFB2AD; /**< Serial Flash B2Top Address, offset: 0x18C */ |
AnnaBridge | 171:3a7713b1edbc | 11055 | __IO uint32_t DLPR; /**< Data Learn Pattern Register, offset: 0x190 */ |
AnnaBridge | 171:3a7713b1edbc | 11056 | uint8_t RESERVED_5[108]; |
AnnaBridge | 171:3a7713b1edbc | 11057 | __I uint32_t RBDR[16]; /**< RX Buffer Data Register, array offset: 0x200, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 11058 | uint8_t RESERVED_6[192]; |
AnnaBridge | 171:3a7713b1edbc | 11059 | __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x300 */ |
AnnaBridge | 171:3a7713b1edbc | 11060 | __IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x304 */ |
AnnaBridge | 171:3a7713b1edbc | 11061 | uint8_t RESERVED_7[8]; |
AnnaBridge | 171:3a7713b1edbc | 11062 | __IO uint32_t LUT[64]; /**< Look-up Table register, array offset: 0x310, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 11063 | } QuadSPI_Type; |
AnnaBridge | 171:3a7713b1edbc | 11064 | |
AnnaBridge | 171:3a7713b1edbc | 11065 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 11066 | -- QuadSPI Register Masks |
AnnaBridge | 171:3a7713b1edbc | 11067 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 11068 | |
AnnaBridge | 171:3a7713b1edbc | 11069 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11070 | * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks |
AnnaBridge | 171:3a7713b1edbc | 11071 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 11072 | */ |
AnnaBridge | 171:3a7713b1edbc | 11073 | |
AnnaBridge | 171:3a7713b1edbc | 11074 | /*! @name MCR - Module Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 11075 | #define QuadSPI_MCR_SWRSTSD_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11076 | #define QuadSPI_MCR_SWRSTSD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11077 | #define QuadSPI_MCR_SWRSTSD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTSD_SHIFT)) & QuadSPI_MCR_SWRSTSD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11078 | #define QuadSPI_MCR_SWRSTHD_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 11079 | #define QuadSPI_MCR_SWRSTHD_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 11080 | #define QuadSPI_MCR_SWRSTHD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11081 | #define QuadSPI_MCR_END_CFG_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 11082 | #define QuadSPI_MCR_END_CFG_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 11083 | #define QuadSPI_MCR_END_CFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_END_CFG_SHIFT)) & QuadSPI_MCR_END_CFG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11084 | #define QuadSPI_MCR_DQS_LAT_EN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 11085 | #define QuadSPI_MCR_DQS_LAT_EN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 11086 | #define QuadSPI_MCR_DQS_LAT_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_LAT_EN_SHIFT)) & QuadSPI_MCR_DQS_LAT_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11087 | #define QuadSPI_MCR_DQS_EN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 11088 | #define QuadSPI_MCR_DQS_EN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 11089 | #define QuadSPI_MCR_DQS_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_EN_SHIFT)) & QuadSPI_MCR_DQS_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11090 | #define QuadSPI_MCR_DDR_EN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 11091 | #define QuadSPI_MCR_DDR_EN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 11092 | #define QuadSPI_MCR_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DDR_EN_SHIFT)) & QuadSPI_MCR_DDR_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11093 | #define QuadSPI_MCR_CLR_RXF_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 11094 | #define QuadSPI_MCR_CLR_RXF_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 11095 | #define QuadSPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_RXF_SHIFT)) & QuadSPI_MCR_CLR_RXF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11096 | #define QuadSPI_MCR_CLR_TXF_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 11097 | #define QuadSPI_MCR_CLR_TXF_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 11098 | #define QuadSPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_TXF_SHIFT)) & QuadSPI_MCR_CLR_TXF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11099 | #define QuadSPI_MCR_MDIS_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 11100 | #define QuadSPI_MCR_MDIS_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 11101 | #define QuadSPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_MDIS_SHIFT)) & QuadSPI_MCR_MDIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11102 | #define QuadSPI_MCR_SCLKCFG_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 11103 | #define QuadSPI_MCR_SCLKCFG_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 11104 | #define QuadSPI_MCR_SCLKCFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SCLKCFG_SHIFT)) & QuadSPI_MCR_SCLKCFG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11105 | |
AnnaBridge | 171:3a7713b1edbc | 11106 | /*! @name IPCR - IP Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 11107 | #define QuadSPI_IPCR_IDATSZ_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 11108 | #define QuadSPI_IPCR_IDATSZ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11109 | #define QuadSPI_IPCR_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_IDATSZ_SHIFT)) & QuadSPI_IPCR_IDATSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11110 | #define QuadSPI_IPCR_PAR_EN_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 11111 | #define QuadSPI_IPCR_PAR_EN_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 11112 | #define QuadSPI_IPCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_PAR_EN_SHIFT)) & QuadSPI_IPCR_PAR_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11113 | #define QuadSPI_IPCR_SEQID_MASK (0xF000000U) |
AnnaBridge | 171:3a7713b1edbc | 11114 | #define QuadSPI_IPCR_SEQID_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 11115 | #define QuadSPI_IPCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11116 | |
AnnaBridge | 171:3a7713b1edbc | 11117 | /*! @name FLSHCR - Flash Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 11118 | #define QuadSPI_FLSHCR_TCSS_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 11119 | #define QuadSPI_FLSHCR_TCSS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11120 | #define QuadSPI_FLSHCR_TCSS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSS_SHIFT)) & QuadSPI_FLSHCR_TCSS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11121 | #define QuadSPI_FLSHCR_TCSH_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 11122 | #define QuadSPI_FLSHCR_TCSH_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 11123 | #define QuadSPI_FLSHCR_TCSH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSH_SHIFT)) & QuadSPI_FLSHCR_TCSH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11124 | #define QuadSPI_FLSHCR_TDH_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 11125 | #define QuadSPI_FLSHCR_TDH_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 11126 | #define QuadSPI_FLSHCR_TDH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11127 | |
AnnaBridge | 171:3a7713b1edbc | 11128 | /*! @name BUF0CR - Buffer0 Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 11129 | #define QuadSPI_BUF0CR_MSTRID_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 11130 | #define QuadSPI_BUF0CR_MSTRID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11131 | #define QuadSPI_BUF0CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_MSTRID_SHIFT)) & QuadSPI_BUF0CR_MSTRID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11132 | #define QuadSPI_BUF0CR_ADATSZ_MASK (0x7F00U) |
AnnaBridge | 171:3a7713b1edbc | 11133 | #define QuadSPI_BUF0CR_ADATSZ_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 11134 | #define QuadSPI_BUF0CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_ADATSZ_SHIFT)) & QuadSPI_BUF0CR_ADATSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11135 | #define QuadSPI_BUF0CR_HP_EN_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 11136 | #define QuadSPI_BUF0CR_HP_EN_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 11137 | #define QuadSPI_BUF0CR_HP_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_HP_EN_SHIFT)) & QuadSPI_BUF0CR_HP_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11138 | |
AnnaBridge | 171:3a7713b1edbc | 11139 | /*! @name BUF1CR - Buffer1 Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 11140 | #define QuadSPI_BUF1CR_MSTRID_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 11141 | #define QuadSPI_BUF1CR_MSTRID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11142 | #define QuadSPI_BUF1CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_MSTRID_SHIFT)) & QuadSPI_BUF1CR_MSTRID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11143 | #define QuadSPI_BUF1CR_ADATSZ_MASK (0x7F00U) |
AnnaBridge | 171:3a7713b1edbc | 11144 | #define QuadSPI_BUF1CR_ADATSZ_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 11145 | #define QuadSPI_BUF1CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_ADATSZ_SHIFT)) & QuadSPI_BUF1CR_ADATSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11146 | |
AnnaBridge | 171:3a7713b1edbc | 11147 | /*! @name BUF2CR - Buffer2 Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 11148 | #define QuadSPI_BUF2CR_MSTRID_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 11149 | #define QuadSPI_BUF2CR_MSTRID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11150 | #define QuadSPI_BUF2CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_MSTRID_SHIFT)) & QuadSPI_BUF2CR_MSTRID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11151 | #define QuadSPI_BUF2CR_ADATSZ_MASK (0x7F00U) |
AnnaBridge | 171:3a7713b1edbc | 11152 | #define QuadSPI_BUF2CR_ADATSZ_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 11153 | #define QuadSPI_BUF2CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_ADATSZ_SHIFT)) & QuadSPI_BUF2CR_ADATSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11154 | |
AnnaBridge | 171:3a7713b1edbc | 11155 | /*! @name BUF3CR - Buffer3 Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 11156 | #define QuadSPI_BUF3CR_MSTRID_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 11157 | #define QuadSPI_BUF3CR_MSTRID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11158 | #define QuadSPI_BUF3CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_MSTRID_SHIFT)) & QuadSPI_BUF3CR_MSTRID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11159 | #define QuadSPI_BUF3CR_ADATSZ_MASK (0x7F00U) |
AnnaBridge | 171:3a7713b1edbc | 11160 | #define QuadSPI_BUF3CR_ADATSZ_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 11161 | #define QuadSPI_BUF3CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ADATSZ_SHIFT)) & QuadSPI_BUF3CR_ADATSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11162 | #define QuadSPI_BUF3CR_ALLMST_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 11163 | #define QuadSPI_BUF3CR_ALLMST_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 11164 | #define QuadSPI_BUF3CR_ALLMST(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ALLMST_SHIFT)) & QuadSPI_BUF3CR_ALLMST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11165 | |
AnnaBridge | 171:3a7713b1edbc | 11166 | /*! @name BFGENCR - Buffer Generic Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 11167 | #define QuadSPI_BFGENCR_SEQID_MASK (0xF000U) |
AnnaBridge | 171:3a7713b1edbc | 11168 | #define QuadSPI_BFGENCR_SEQID_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 11169 | #define QuadSPI_BFGENCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_SEQID_SHIFT)) & QuadSPI_BFGENCR_SEQID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11170 | #define QuadSPI_BFGENCR_PAR_EN_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 11171 | #define QuadSPI_BFGENCR_PAR_EN_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 11172 | #define QuadSPI_BFGENCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_PAR_EN_SHIFT)) & QuadSPI_BFGENCR_PAR_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11173 | |
AnnaBridge | 171:3a7713b1edbc | 11174 | /*! @name SOCCR - SOC Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 11175 | #define QuadSPI_SOCCR_QSPISRC_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 11176 | #define QuadSPI_SOCCR_QSPISRC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11177 | #define QuadSPI_SOCCR_QSPISRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_QSPISRC_SHIFT)) & QuadSPI_SOCCR_QSPISRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11178 | #define QuadSPI_SOCCR_DQSLPEN_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 11179 | #define QuadSPI_SOCCR_DQSLPEN_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 11180 | #define QuadSPI_SOCCR_DQSLPEN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQSLPEN_SHIFT)) & QuadSPI_SOCCR_DQSLPEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11181 | #define QuadSPI_SOCCR_DQSPADLPEN_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 11182 | #define QuadSPI_SOCCR_DQSPADLPEN_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 11183 | #define QuadSPI_SOCCR_DQSPADLPEN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQSPADLPEN_SHIFT)) & QuadSPI_SOCCR_DQSPADLPEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11184 | #define QuadSPI_SOCCR_DQSPHASEL_MASK (0xC00U) |
AnnaBridge | 171:3a7713b1edbc | 11185 | #define QuadSPI_SOCCR_DQSPHASEL_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 11186 | #define QuadSPI_SOCCR_DQSPHASEL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQSPHASEL_SHIFT)) & QuadSPI_SOCCR_DQSPHASEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11187 | #define QuadSPI_SOCCR_DQSINVSEL_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 11188 | #define QuadSPI_SOCCR_DQSINVSEL_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 11189 | #define QuadSPI_SOCCR_DQSINVSEL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQSINVSEL_SHIFT)) & QuadSPI_SOCCR_DQSINVSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11190 | #define QuadSPI_SOCCR_CK2EN_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 11191 | #define QuadSPI_SOCCR_CK2EN_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 11192 | #define QuadSPI_SOCCR_CK2EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_CK2EN_SHIFT)) & QuadSPI_SOCCR_CK2EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11193 | #define QuadSPI_SOCCR_DIFFCKEN_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 11194 | #define QuadSPI_SOCCR_DIFFCKEN_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 11195 | #define QuadSPI_SOCCR_DIFFCKEN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DIFFCKEN_SHIFT)) & QuadSPI_SOCCR_DIFFCKEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11196 | #define QuadSPI_SOCCR_OCTEN_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 11197 | #define QuadSPI_SOCCR_OCTEN_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 11198 | #define QuadSPI_SOCCR_OCTEN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_OCTEN_SHIFT)) & QuadSPI_SOCCR_OCTEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11199 | #define QuadSPI_SOCCR_DLYTAPSELA_MASK (0x3F0000U) |
AnnaBridge | 171:3a7713b1edbc | 11200 | #define QuadSPI_SOCCR_DLYTAPSELA_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 11201 | #define QuadSPI_SOCCR_DLYTAPSELA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DLYTAPSELA_SHIFT)) & QuadSPI_SOCCR_DLYTAPSELA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11202 | #define QuadSPI_SOCCR_DLYTAPSELB_MASK (0x3F000000U) |
AnnaBridge | 171:3a7713b1edbc | 11203 | #define QuadSPI_SOCCR_DLYTAPSELB_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 11204 | #define QuadSPI_SOCCR_DLYTAPSELB(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DLYTAPSELB_SHIFT)) & QuadSPI_SOCCR_DLYTAPSELB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11205 | |
AnnaBridge | 171:3a7713b1edbc | 11206 | /*! @name BUF0IND - Buffer0 Top Index Register */ |
AnnaBridge | 171:3a7713b1edbc | 11207 | #define QuadSPI_BUF0IND_TPINDX0_MASK (0xFFFFFFF8U) |
AnnaBridge | 171:3a7713b1edbc | 11208 | #define QuadSPI_BUF0IND_TPINDX0_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 11209 | #define QuadSPI_BUF0IND_TPINDX0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0IND_TPINDX0_SHIFT)) & QuadSPI_BUF0IND_TPINDX0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11210 | |
AnnaBridge | 171:3a7713b1edbc | 11211 | /*! @name BUF1IND - Buffer1 Top Index Register */ |
AnnaBridge | 171:3a7713b1edbc | 11212 | #define QuadSPI_BUF1IND_TPINDX1_MASK (0xFFFFFFF8U) |
AnnaBridge | 171:3a7713b1edbc | 11213 | #define QuadSPI_BUF1IND_TPINDX1_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 11214 | #define QuadSPI_BUF1IND_TPINDX1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1IND_TPINDX1_SHIFT)) & QuadSPI_BUF1IND_TPINDX1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11215 | |
AnnaBridge | 171:3a7713b1edbc | 11216 | /*! @name BUF2IND - Buffer2 Top Index Register */ |
AnnaBridge | 171:3a7713b1edbc | 11217 | #define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) |
AnnaBridge | 171:3a7713b1edbc | 11218 | #define QuadSPI_BUF2IND_TPINDX2_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 11219 | #define QuadSPI_BUF2IND_TPINDX2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11220 | |
AnnaBridge | 171:3a7713b1edbc | 11221 | /*! @name SFAR - Serial Flash Address Register */ |
AnnaBridge | 171:3a7713b1edbc | 11222 | #define QuadSPI_SFAR_SFADR_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 11223 | #define QuadSPI_SFAR_SFADR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11224 | #define QuadSPI_SFAR_SFADR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFAR_SFADR_SHIFT)) & QuadSPI_SFAR_SFADR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11225 | |
AnnaBridge | 171:3a7713b1edbc | 11226 | /*! @name SFACR - Serial Flash Address Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 11227 | #define QuadSPI_SFACR_CAS_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 11228 | #define QuadSPI_SFACR_CAS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11229 | #define QuadSPI_SFACR_CAS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFACR_CAS_SHIFT)) & QuadSPI_SFACR_CAS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11230 | #define QuadSPI_SFACR_WA_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 11231 | #define QuadSPI_SFACR_WA_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 11232 | #define QuadSPI_SFACR_WA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFACR_WA_SHIFT)) & QuadSPI_SFACR_WA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11233 | |
AnnaBridge | 171:3a7713b1edbc | 11234 | /*! @name SMPR - Sampling Register */ |
AnnaBridge | 171:3a7713b1edbc | 11235 | #define QuadSPI_SMPR_HSENA_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11236 | #define QuadSPI_SMPR_HSENA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11237 | #define QuadSPI_SMPR_HSENA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSENA_SHIFT)) & QuadSPI_SMPR_HSENA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11238 | #define QuadSPI_SMPR_HSPHS_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 11239 | #define QuadSPI_SMPR_HSPHS_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 11240 | #define QuadSPI_SMPR_HSPHS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSPHS_SHIFT)) & QuadSPI_SMPR_HSPHS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11241 | #define QuadSPI_SMPR_HSDLY_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 11242 | #define QuadSPI_SMPR_HSDLY_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 11243 | #define QuadSPI_SMPR_HSDLY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSDLY_SHIFT)) & QuadSPI_SMPR_HSDLY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11244 | #define QuadSPI_SMPR_FSPHS_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 11245 | #define QuadSPI_SMPR_FSPHS_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 11246 | #define QuadSPI_SMPR_FSPHS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_FSPHS_SHIFT)) & QuadSPI_SMPR_FSPHS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11247 | #define QuadSPI_SMPR_FSDLY_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 11248 | #define QuadSPI_SMPR_FSDLY_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 11249 | #define QuadSPI_SMPR_FSDLY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_FSDLY_SHIFT)) & QuadSPI_SMPR_FSDLY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11250 | #define QuadSPI_SMPR_DDRSMP_MASK (0x70000U) |
AnnaBridge | 171:3a7713b1edbc | 11251 | #define QuadSPI_SMPR_DDRSMP_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 11252 | #define QuadSPI_SMPR_DDRSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_DDRSMP_SHIFT)) & QuadSPI_SMPR_DDRSMP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11253 | |
AnnaBridge | 171:3a7713b1edbc | 11254 | /*! @name RBSR - RX Buffer Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 11255 | #define QuadSPI_RBSR_RDBFL_MASK (0x1F00U) |
AnnaBridge | 171:3a7713b1edbc | 11256 | #define QuadSPI_RBSR_RDBFL_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 11257 | #define QuadSPI_RBSR_RDBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDBFL_SHIFT)) & QuadSPI_RBSR_RDBFL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11258 | #define QuadSPI_RBSR_RDCTR_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 11259 | #define QuadSPI_RBSR_RDCTR_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 11260 | #define QuadSPI_RBSR_RDCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDCTR_SHIFT)) & QuadSPI_RBSR_RDCTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11261 | |
AnnaBridge | 171:3a7713b1edbc | 11262 | /*! @name RBCT - RX Buffer Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 11263 | #define QuadSPI_RBCT_WMRK_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 11264 | #define QuadSPI_RBCT_WMRK_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11265 | #define QuadSPI_RBCT_WMRK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_WMRK_SHIFT)) & QuadSPI_RBCT_WMRK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11266 | #define QuadSPI_RBCT_RXBRD_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 11267 | #define QuadSPI_RBCT_RXBRD_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 11268 | #define QuadSPI_RBCT_RXBRD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_RXBRD_SHIFT)) & QuadSPI_RBCT_RXBRD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11269 | |
AnnaBridge | 171:3a7713b1edbc | 11270 | /*! @name TBSR - TX Buffer Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 11271 | #define QuadSPI_TBSR_TRBFL_MASK (0x1F00U) |
AnnaBridge | 171:3a7713b1edbc | 11272 | #define QuadSPI_TBSR_TRBFL_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 11273 | #define QuadSPI_TBSR_TRBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRBFL_SHIFT)) & QuadSPI_TBSR_TRBFL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11274 | #define QuadSPI_TBSR_TRCTR_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 11275 | #define QuadSPI_TBSR_TRCTR_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 11276 | #define QuadSPI_TBSR_TRCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRCTR_SHIFT)) & QuadSPI_TBSR_TRCTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11277 | |
AnnaBridge | 171:3a7713b1edbc | 11278 | /*! @name TBDR - TX Buffer Data Register */ |
AnnaBridge | 171:3a7713b1edbc | 11279 | #define QuadSPI_TBDR_TXDATA_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 11280 | #define QuadSPI_TBDR_TXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11281 | #define QuadSPI_TBDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBDR_TXDATA_SHIFT)) & QuadSPI_TBDR_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11282 | |
AnnaBridge | 171:3a7713b1edbc | 11283 | /*! @name TBCT - Tx Buffer Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 11284 | #define QuadSPI_TBCT_WMRK_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 11285 | #define QuadSPI_TBCT_WMRK_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11286 | #define QuadSPI_TBCT_WMRK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBCT_WMRK_SHIFT)) & QuadSPI_TBCT_WMRK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11287 | |
AnnaBridge | 171:3a7713b1edbc | 11288 | /*! @name SR - Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 11289 | #define QuadSPI_SR_BUSY_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11290 | #define QuadSPI_SR_BUSY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11291 | #define QuadSPI_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_BUSY_SHIFT)) & QuadSPI_SR_BUSY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11292 | #define QuadSPI_SR_IP_ACC_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 11293 | #define QuadSPI_SR_IP_ACC_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 11294 | #define QuadSPI_SR_IP_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_IP_ACC_SHIFT)) & QuadSPI_SR_IP_ACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11295 | #define QuadSPI_SR_AHB_ACC_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 11296 | #define QuadSPI_SR_AHB_ACC_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 11297 | #define QuadSPI_SR_AHB_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB_ACC_SHIFT)) & QuadSPI_SR_AHB_ACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11298 | #define QuadSPI_SR_AHBGNT_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 11299 | #define QuadSPI_SR_AHBGNT_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 11300 | #define QuadSPI_SR_AHBGNT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBGNT_SHIFT)) & QuadSPI_SR_AHBGNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11301 | #define QuadSPI_SR_AHBTRN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 11302 | #define QuadSPI_SR_AHBTRN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 11303 | #define QuadSPI_SR_AHBTRN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBTRN_SHIFT)) & QuadSPI_SR_AHBTRN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11304 | #define QuadSPI_SR_AHB0NE_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 11305 | #define QuadSPI_SR_AHB0NE_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 11306 | #define QuadSPI_SR_AHB0NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11307 | #define QuadSPI_SR_AHB1NE_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 11308 | #define QuadSPI_SR_AHB1NE_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 11309 | #define QuadSPI_SR_AHB1NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1NE_SHIFT)) & QuadSPI_SR_AHB1NE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11310 | #define QuadSPI_SR_AHB2NE_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 11311 | #define QuadSPI_SR_AHB2NE_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 11312 | #define QuadSPI_SR_AHB2NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2NE_SHIFT)) & QuadSPI_SR_AHB2NE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11313 | #define QuadSPI_SR_AHB3NE_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 11314 | #define QuadSPI_SR_AHB3NE_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 11315 | #define QuadSPI_SR_AHB3NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3NE_SHIFT)) & QuadSPI_SR_AHB3NE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11316 | #define QuadSPI_SR_AHB0FUL_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 11317 | #define QuadSPI_SR_AHB0FUL_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 11318 | #define QuadSPI_SR_AHB0FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11319 | #define QuadSPI_SR_AHB1FUL_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 11320 | #define QuadSPI_SR_AHB1FUL_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 11321 | #define QuadSPI_SR_AHB1FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1FUL_SHIFT)) & QuadSPI_SR_AHB1FUL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11322 | #define QuadSPI_SR_AHB2FUL_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 11323 | #define QuadSPI_SR_AHB2FUL_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 11324 | #define QuadSPI_SR_AHB2FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2FUL_SHIFT)) & QuadSPI_SR_AHB2FUL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11325 | #define QuadSPI_SR_AHB3FUL_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 11326 | #define QuadSPI_SR_AHB3FUL_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 11327 | #define QuadSPI_SR_AHB3FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3FUL_SHIFT)) & QuadSPI_SR_AHB3FUL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11328 | #define QuadSPI_SR_RXWE_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 11329 | #define QuadSPI_SR_RXWE_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 11330 | #define QuadSPI_SR_RXWE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11331 | #define QuadSPI_SR_RXFULL_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 11332 | #define QuadSPI_SR_RXFULL_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 11333 | #define QuadSPI_SR_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11334 | #define QuadSPI_SR_RXDMA_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 11335 | #define QuadSPI_SR_RXDMA_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 11336 | #define QuadSPI_SR_RXDMA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXDMA_SHIFT)) & QuadSPI_SR_RXDMA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11337 | #define QuadSPI_SR_TXEDA_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 11338 | #define QuadSPI_SR_TXEDA_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 11339 | #define QuadSPI_SR_TXEDA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXEDA_SHIFT)) & QuadSPI_SR_TXEDA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11340 | #define QuadSPI_SR_TXWA_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 11341 | #define QuadSPI_SR_TXWA_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 11342 | #define QuadSPI_SR_TXWA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXWA_SHIFT)) & QuadSPI_SR_TXWA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11343 | #define QuadSPI_SR_TXDMA_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 11344 | #define QuadSPI_SR_TXDMA_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 11345 | #define QuadSPI_SR_TXDMA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXDMA_SHIFT)) & QuadSPI_SR_TXDMA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11346 | #define QuadSPI_SR_TXFULL_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 11347 | #define QuadSPI_SR_TXFULL_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 11348 | #define QuadSPI_SR_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11349 | #define QuadSPI_SR_DLPSMP_MASK (0xE0000000U) |
AnnaBridge | 171:3a7713b1edbc | 11350 | #define QuadSPI_SR_DLPSMP_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 11351 | #define QuadSPI_SR_DLPSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11352 | |
AnnaBridge | 171:3a7713b1edbc | 11353 | /*! @name FR - Flag Register */ |
AnnaBridge | 171:3a7713b1edbc | 11354 | #define QuadSPI_FR_TFF_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11355 | #define QuadSPI_FR_TFF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11356 | #define QuadSPI_FR_TFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TFF_SHIFT)) & QuadSPI_FR_TFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11357 | #define QuadSPI_FR_IPGEF_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 11358 | #define QuadSPI_FR_IPGEF_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 11359 | #define QuadSPI_FR_IPGEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPGEF_SHIFT)) & QuadSPI_FR_IPGEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11360 | #define QuadSPI_FR_IPIEF_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 11361 | #define QuadSPI_FR_IPIEF_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 11362 | #define QuadSPI_FR_IPIEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPIEF_SHIFT)) & QuadSPI_FR_IPIEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11363 | #define QuadSPI_FR_IPAEF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 11364 | #define QuadSPI_FR_IPAEF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 11365 | #define QuadSPI_FR_IPAEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPAEF_SHIFT)) & QuadSPI_FR_IPAEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11366 | #define QuadSPI_FR_IUEF_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 11367 | #define QuadSPI_FR_IUEF_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 11368 | #define QuadSPI_FR_IUEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IUEF_SHIFT)) & QuadSPI_FR_IUEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11369 | #define QuadSPI_FR_ABOF_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 11370 | #define QuadSPI_FR_ABOF_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 11371 | #define QuadSPI_FR_ABOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABOF_SHIFT)) & QuadSPI_FR_ABOF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11372 | #define QuadSPI_FR_AIBSEF_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 11373 | #define QuadSPI_FR_AIBSEF_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 11374 | #define QuadSPI_FR_AIBSEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AIBSEF_SHIFT)) & QuadSPI_FR_AIBSEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11375 | #define QuadSPI_FR_AITEF_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 11376 | #define QuadSPI_FR_AITEF_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 11377 | #define QuadSPI_FR_AITEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AITEF_SHIFT)) & QuadSPI_FR_AITEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11378 | #define QuadSPI_FR_ABSEF_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 11379 | #define QuadSPI_FR_ABSEF_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 11380 | #define QuadSPI_FR_ABSEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11381 | #define QuadSPI_FR_RBDF_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 11382 | #define QuadSPI_FR_RBDF_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 11383 | #define QuadSPI_FR_RBDF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBDF_SHIFT)) & QuadSPI_FR_RBDF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11384 | #define QuadSPI_FR_RBOF_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 11385 | #define QuadSPI_FR_RBOF_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 11386 | #define QuadSPI_FR_RBOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBOF_SHIFT)) & QuadSPI_FR_RBOF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11387 | #define QuadSPI_FR_ILLINE_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 11388 | #define QuadSPI_FR_ILLINE_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 11389 | #define QuadSPI_FR_ILLINE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11390 | #define QuadSPI_FR_TBUF_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 11391 | #define QuadSPI_FR_TBUF_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 11392 | #define QuadSPI_FR_TBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBUF_SHIFT)) & QuadSPI_FR_TBUF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11393 | #define QuadSPI_FR_TBFF_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 11394 | #define QuadSPI_FR_TBFF_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 11395 | #define QuadSPI_FR_TBFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBFF_SHIFT)) & QuadSPI_FR_TBFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11396 | #define QuadSPI_FR_DLPFF_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 11397 | #define QuadSPI_FR_DLPFF_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 11398 | #define QuadSPI_FR_DLPFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_DLPFF_SHIFT)) & QuadSPI_FR_DLPFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11399 | |
AnnaBridge | 171:3a7713b1edbc | 11400 | /*! @name RSER - Interrupt and DMA Request Select and Enable Register */ |
AnnaBridge | 171:3a7713b1edbc | 11401 | #define QuadSPI_RSER_TFIE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11402 | #define QuadSPI_RSER_TFIE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11403 | #define QuadSPI_RSER_TFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TFIE_SHIFT)) & QuadSPI_RSER_TFIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11404 | #define QuadSPI_RSER_IPGEIE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 11405 | #define QuadSPI_RSER_IPGEIE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 11406 | #define QuadSPI_RSER_IPGEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPGEIE_SHIFT)) & QuadSPI_RSER_IPGEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11407 | #define QuadSPI_RSER_IPIEIE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 11408 | #define QuadSPI_RSER_IPIEIE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 11409 | #define QuadSPI_RSER_IPIEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPIEIE_SHIFT)) & QuadSPI_RSER_IPIEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11410 | #define QuadSPI_RSER_IPAEIE_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 11411 | #define QuadSPI_RSER_IPAEIE_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 11412 | #define QuadSPI_RSER_IPAEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPAEIE_SHIFT)) & QuadSPI_RSER_IPAEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11413 | #define QuadSPI_RSER_IUEIE_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 11414 | #define QuadSPI_RSER_IUEIE_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 11415 | #define QuadSPI_RSER_IUEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IUEIE_SHIFT)) & QuadSPI_RSER_IUEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11416 | #define QuadSPI_RSER_ABOIE_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 11417 | #define QuadSPI_RSER_ABOIE_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 11418 | #define QuadSPI_RSER_ABOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABOIE_SHIFT)) & QuadSPI_RSER_ABOIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11419 | #define QuadSPI_RSER_AIBSIE_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 11420 | #define QuadSPI_RSER_AIBSIE_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 11421 | #define QuadSPI_RSER_AIBSIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_AIBSIE_SHIFT)) & QuadSPI_RSER_AIBSIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11422 | #define QuadSPI_RSER_AITIE_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 11423 | #define QuadSPI_RSER_AITIE_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 11424 | #define QuadSPI_RSER_AITIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_AITIE_SHIFT)) & QuadSPI_RSER_AITIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11425 | #define QuadSPI_RSER_ABSEIE_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 11426 | #define QuadSPI_RSER_ABSEIE_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 11427 | #define QuadSPI_RSER_ABSEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABSEIE_SHIFT)) & QuadSPI_RSER_ABSEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11428 | #define QuadSPI_RSER_RBDIE_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 11429 | #define QuadSPI_RSER_RBDIE_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 11430 | #define QuadSPI_RSER_RBDIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDIE_SHIFT)) & QuadSPI_RSER_RBDIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11431 | #define QuadSPI_RSER_RBOIE_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 11432 | #define QuadSPI_RSER_RBOIE_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 11433 | #define QuadSPI_RSER_RBOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBOIE_SHIFT)) & QuadSPI_RSER_RBOIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11434 | #define QuadSPI_RSER_RBDDE_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 11435 | #define QuadSPI_RSER_RBDDE_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 11436 | #define QuadSPI_RSER_RBDDE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDDE_SHIFT)) & QuadSPI_RSER_RBDDE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11437 | #define QuadSPI_RSER_ILLINIE_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 11438 | #define QuadSPI_RSER_ILLINIE_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 11439 | #define QuadSPI_RSER_ILLINIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ILLINIE_SHIFT)) & QuadSPI_RSER_ILLINIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11440 | #define QuadSPI_RSER_TBFDE_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 11441 | #define QuadSPI_RSER_TBFDE_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 11442 | #define QuadSPI_RSER_TBFDE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFDE_SHIFT)) & QuadSPI_RSER_TBFDE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11443 | #define QuadSPI_RSER_TBUIE_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 11444 | #define QuadSPI_RSER_TBUIE_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 11445 | #define QuadSPI_RSER_TBUIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBUIE_SHIFT)) & QuadSPI_RSER_TBUIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11446 | #define QuadSPI_RSER_TBFIE_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 11447 | #define QuadSPI_RSER_TBFIE_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 11448 | #define QuadSPI_RSER_TBFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFIE_SHIFT)) & QuadSPI_RSER_TBFIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11449 | #define QuadSPI_RSER_DLPFIE_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 11450 | #define QuadSPI_RSER_DLPFIE_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 11451 | #define QuadSPI_RSER_DLPFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_DLPFIE_SHIFT)) & QuadSPI_RSER_DLPFIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11452 | |
AnnaBridge | 171:3a7713b1edbc | 11453 | /*! @name SPNDST - Sequence Suspend Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 11454 | #define QuadSPI_SPNDST_SUSPND_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11455 | #define QuadSPI_SPNDST_SUSPND_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11456 | #define QuadSPI_SPNDST_SUSPND(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SUSPND_SHIFT)) & QuadSPI_SPNDST_SUSPND_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11457 | #define QuadSPI_SPNDST_SPDBUF_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 11458 | #define QuadSPI_SPNDST_SPDBUF_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 11459 | #define QuadSPI_SPNDST_SPDBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SPDBUF_SHIFT)) & QuadSPI_SPNDST_SPDBUF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11460 | #define QuadSPI_SPNDST_DATLFT_MASK (0x7E00U) |
AnnaBridge | 171:3a7713b1edbc | 11461 | #define QuadSPI_SPNDST_DATLFT_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 11462 | #define QuadSPI_SPNDST_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_DATLFT_SHIFT)) & QuadSPI_SPNDST_DATLFT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11463 | |
AnnaBridge | 171:3a7713b1edbc | 11464 | /*! @name SPTRCLR - Sequence Pointer Clear Register */ |
AnnaBridge | 171:3a7713b1edbc | 11465 | #define QuadSPI_SPTRCLR_BFPTRC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11466 | #define QuadSPI_SPTRCLR_BFPTRC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11467 | #define QuadSPI_SPTRCLR_BFPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_BFPTRC_SHIFT)) & QuadSPI_SPTRCLR_BFPTRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11468 | #define QuadSPI_SPTRCLR_IPPTRC_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 11469 | #define QuadSPI_SPTRCLR_IPPTRC_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 11470 | #define QuadSPI_SPTRCLR_IPPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_IPPTRC_SHIFT)) & QuadSPI_SPTRCLR_IPPTRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11471 | |
AnnaBridge | 171:3a7713b1edbc | 11472 | /*! @name SFA1AD - Serial Flash A1 Top Address */ |
AnnaBridge | 171:3a7713b1edbc | 11473 | #define QuadSPI_SFA1AD_TPADA1_MASK (0xFFFFFC00U) |
AnnaBridge | 171:3a7713b1edbc | 11474 | #define QuadSPI_SFA1AD_TPADA1_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 11475 | #define QuadSPI_SFA1AD_TPADA1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA1AD_TPADA1_SHIFT)) & QuadSPI_SFA1AD_TPADA1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11476 | |
AnnaBridge | 171:3a7713b1edbc | 11477 | /*! @name SFA2AD - Serial Flash A2 Top Address */ |
AnnaBridge | 171:3a7713b1edbc | 11478 | #define QuadSPI_SFA2AD_TPADA2_MASK (0xFFFFFC00U) |
AnnaBridge | 171:3a7713b1edbc | 11479 | #define QuadSPI_SFA2AD_TPADA2_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 11480 | #define QuadSPI_SFA2AD_TPADA2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA2AD_TPADA2_SHIFT)) & QuadSPI_SFA2AD_TPADA2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11481 | |
AnnaBridge | 171:3a7713b1edbc | 11482 | /*! @name SFB1AD - Serial Flash B1Top Address */ |
AnnaBridge | 171:3a7713b1edbc | 11483 | #define QuadSPI_SFB1AD_TPADB1_MASK (0xFFFFFC00U) |
AnnaBridge | 171:3a7713b1edbc | 11484 | #define QuadSPI_SFB1AD_TPADB1_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 11485 | #define QuadSPI_SFB1AD_TPADB1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB1AD_TPADB1_SHIFT)) & QuadSPI_SFB1AD_TPADB1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11486 | |
AnnaBridge | 171:3a7713b1edbc | 11487 | /*! @name SFB2AD - Serial Flash B2Top Address */ |
AnnaBridge | 171:3a7713b1edbc | 11488 | #define QuadSPI_SFB2AD_TPADB2_MASK (0xFFFFFC00U) |
AnnaBridge | 171:3a7713b1edbc | 11489 | #define QuadSPI_SFB2AD_TPADB2_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 11490 | #define QuadSPI_SFB2AD_TPADB2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB2AD_TPADB2_SHIFT)) & QuadSPI_SFB2AD_TPADB2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11491 | |
AnnaBridge | 171:3a7713b1edbc | 11492 | /*! @name DLPR - Data Learn Pattern Register */ |
AnnaBridge | 171:3a7713b1edbc | 11493 | #define QuadSPI_DLPR_DLPV_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 11494 | #define QuadSPI_DLPR_DLPV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11495 | #define QuadSPI_DLPR_DLPV(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLPR_DLPV_SHIFT)) & QuadSPI_DLPR_DLPV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11496 | |
AnnaBridge | 171:3a7713b1edbc | 11497 | /*! @name RBDR - RX Buffer Data Register */ |
AnnaBridge | 171:3a7713b1edbc | 11498 | #define QuadSPI_RBDR_RXDATA_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 11499 | #define QuadSPI_RBDR_RXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11500 | #define QuadSPI_RBDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBDR_RXDATA_SHIFT)) & QuadSPI_RBDR_RXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11501 | |
AnnaBridge | 171:3a7713b1edbc | 11502 | /* The count of QuadSPI_RBDR */ |
AnnaBridge | 171:3a7713b1edbc | 11503 | #define QuadSPI_RBDR_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 11504 | |
AnnaBridge | 171:3a7713b1edbc | 11505 | /*! @name LUTKEY - LUT Key Register */ |
AnnaBridge | 171:3a7713b1edbc | 11506 | #define QuadSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 11507 | #define QuadSPI_LUTKEY_KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11508 | #define QuadSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUTKEY_KEY_SHIFT)) & QuadSPI_LUTKEY_KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11509 | |
AnnaBridge | 171:3a7713b1edbc | 11510 | /*! @name LCKCR - LUT Lock Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 11511 | #define QuadSPI_LCKCR_LOCK_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11512 | #define QuadSPI_LCKCR_LOCK_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11513 | #define QuadSPI_LCKCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11514 | #define QuadSPI_LCKCR_UNLOCK_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 11515 | #define QuadSPI_LCKCR_UNLOCK_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 11516 | #define QuadSPI_LCKCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_UNLOCK_SHIFT)) & QuadSPI_LCKCR_UNLOCK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11517 | |
AnnaBridge | 171:3a7713b1edbc | 11518 | /*! @name LUT - Look-up Table register */ |
AnnaBridge | 171:3a7713b1edbc | 11519 | #define QuadSPI_LUT_OPRND0_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 11520 | #define QuadSPI_LUT_OPRND0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11521 | #define QuadSPI_LUT_OPRND0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND0_SHIFT)) & QuadSPI_LUT_OPRND0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11522 | #define QuadSPI_LUT_PAD0_MASK (0x300U) |
AnnaBridge | 171:3a7713b1edbc | 11523 | #define QuadSPI_LUT_PAD0_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 11524 | #define QuadSPI_LUT_PAD0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD0_SHIFT)) & QuadSPI_LUT_PAD0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11525 | #define QuadSPI_LUT_INSTR0_MASK (0xFC00U) |
AnnaBridge | 171:3a7713b1edbc | 11526 | #define QuadSPI_LUT_INSTR0_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 11527 | #define QuadSPI_LUT_INSTR0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR0_SHIFT)) & QuadSPI_LUT_INSTR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11528 | #define QuadSPI_LUT_OPRND1_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 11529 | #define QuadSPI_LUT_OPRND1_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 11530 | #define QuadSPI_LUT_OPRND1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND1_SHIFT)) & QuadSPI_LUT_OPRND1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11531 | #define QuadSPI_LUT_PAD1_MASK (0x3000000U) |
AnnaBridge | 171:3a7713b1edbc | 11532 | #define QuadSPI_LUT_PAD1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 11533 | #define QuadSPI_LUT_PAD1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD1_SHIFT)) & QuadSPI_LUT_PAD1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11534 | #define QuadSPI_LUT_INSTR1_MASK (0xFC000000U) |
AnnaBridge | 171:3a7713b1edbc | 11535 | #define QuadSPI_LUT_INSTR1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 11536 | #define QuadSPI_LUT_INSTR1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR1_SHIFT)) & QuadSPI_LUT_INSTR1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11537 | |
AnnaBridge | 171:3a7713b1edbc | 11538 | /* The count of QuadSPI_LUT */ |
AnnaBridge | 171:3a7713b1edbc | 11539 | #define QuadSPI_LUT_COUNT (64U) |
AnnaBridge | 171:3a7713b1edbc | 11540 | |
AnnaBridge | 171:3a7713b1edbc | 11541 | |
AnnaBridge | 171:3a7713b1edbc | 11542 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11543 | * @} |
AnnaBridge | 171:3a7713b1edbc | 11544 | */ /* end of group QuadSPI_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 11545 | |
AnnaBridge | 171:3a7713b1edbc | 11546 | |
AnnaBridge | 171:3a7713b1edbc | 11547 | /* QuadSPI - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 11548 | /** Peripheral QuadSPI0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 11549 | #define QuadSPI0_BASE (0x400DA000u) |
AnnaBridge | 171:3a7713b1edbc | 11550 | /** Peripheral QuadSPI0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 11551 | #define QuadSPI0 ((QuadSPI_Type *)QuadSPI0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 11552 | /** Array initializer of QuadSPI peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 11553 | #define QuadSPI_BASE_ADDRS { QuadSPI0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 11554 | /** Array initializer of QuadSPI peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 11555 | #define QuadSPI_BASE_PTRS { QuadSPI0 } |
AnnaBridge | 171:3a7713b1edbc | 11556 | /** Interrupt vectors for the QuadSPI peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 11557 | #define QuadSPI_IRQS { QuadSPI0_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 11558 | |
AnnaBridge | 171:3a7713b1edbc | 11559 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11560 | * @} |
AnnaBridge | 171:3a7713b1edbc | 11561 | */ /* end of group QuadSPI_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 11562 | |
AnnaBridge | 171:3a7713b1edbc | 11563 | |
AnnaBridge | 171:3a7713b1edbc | 11564 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 11565 | -- RCM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 11566 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 11567 | |
AnnaBridge | 171:3a7713b1edbc | 11568 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11569 | * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 11570 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 11571 | */ |
AnnaBridge | 171:3a7713b1edbc | 11572 | |
AnnaBridge | 171:3a7713b1edbc | 11573 | /** RCM - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 11574 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 11575 | __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 11576 | __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 11577 | uint8_t RESERVED_0[2]; |
AnnaBridge | 171:3a7713b1edbc | 11578 | __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 11579 | __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */ |
AnnaBridge | 171:3a7713b1edbc | 11580 | __IO uint8_t FM; /**< Force Mode Register, offset: 0x6 */ |
AnnaBridge | 171:3a7713b1edbc | 11581 | __IO uint8_t MR; /**< Mode Register, offset: 0x7 */ |
AnnaBridge | 171:3a7713b1edbc | 11582 | __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 11583 | __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */ |
AnnaBridge | 171:3a7713b1edbc | 11584 | } RCM_Type; |
AnnaBridge | 171:3a7713b1edbc | 11585 | |
AnnaBridge | 171:3a7713b1edbc | 11586 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 11587 | -- RCM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 11588 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 11589 | |
AnnaBridge | 171:3a7713b1edbc | 11590 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11591 | * @addtogroup RCM_Register_Masks RCM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 11592 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 11593 | */ |
AnnaBridge | 171:3a7713b1edbc | 11594 | |
AnnaBridge | 171:3a7713b1edbc | 11595 | /*! @name SRS0 - System Reset Status Register 0 */ |
AnnaBridge | 171:3a7713b1edbc | 11596 | #define RCM_SRS0_WAKEUP_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11597 | #define RCM_SRS0_WAKEUP_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11598 | #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11599 | #define RCM_SRS0_LVD_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 11600 | #define RCM_SRS0_LVD_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 11601 | #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11602 | #define RCM_SRS0_LOC_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 11603 | #define RCM_SRS0_LOC_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 11604 | #define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11605 | #define RCM_SRS0_LOL_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 11606 | #define RCM_SRS0_LOL_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 11607 | #define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11608 | #define RCM_SRS0_WDOG_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 11609 | #define RCM_SRS0_WDOG_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 11610 | #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11611 | #define RCM_SRS0_PIN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 11612 | #define RCM_SRS0_PIN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 11613 | #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11614 | #define RCM_SRS0_POR_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 11615 | #define RCM_SRS0_POR_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 11616 | #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11617 | |
AnnaBridge | 171:3a7713b1edbc | 11618 | /*! @name SRS1 - System Reset Status Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 11619 | #define RCM_SRS1_JTAG_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11620 | #define RCM_SRS1_JTAG_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11621 | #define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11622 | #define RCM_SRS1_LOCKUP_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 11623 | #define RCM_SRS1_LOCKUP_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 11624 | #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11625 | #define RCM_SRS1_SW_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 11626 | #define RCM_SRS1_SW_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 11627 | #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11628 | #define RCM_SRS1_MDM_AP_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 11629 | #define RCM_SRS1_MDM_AP_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 11630 | #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11631 | #define RCM_SRS1_SACKERR_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 11632 | #define RCM_SRS1_SACKERR_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 11633 | #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11634 | |
AnnaBridge | 171:3a7713b1edbc | 11635 | /*! @name RPFC - Reset Pin Filter Control register */ |
AnnaBridge | 171:3a7713b1edbc | 11636 | #define RCM_RPFC_RSTFLTSRW_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 11637 | #define RCM_RPFC_RSTFLTSRW_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11638 | #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11639 | #define RCM_RPFC_RSTFLTSS_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 11640 | #define RCM_RPFC_RSTFLTSS_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 11641 | #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11642 | |
AnnaBridge | 171:3a7713b1edbc | 11643 | /*! @name RPFW - Reset Pin Filter Width register */ |
AnnaBridge | 171:3a7713b1edbc | 11644 | #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 11645 | #define RCM_RPFW_RSTFLTSEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11646 | #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11647 | |
AnnaBridge | 171:3a7713b1edbc | 11648 | /*! @name FM - Force Mode Register */ |
AnnaBridge | 171:3a7713b1edbc | 11649 | #define RCM_FM_FORCEROM_MASK (0x6U) |
AnnaBridge | 171:3a7713b1edbc | 11650 | #define RCM_FM_FORCEROM_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 11651 | #define RCM_FM_FORCEROM(x) (((uint8_t)(((uint8_t)(x)) << RCM_FM_FORCEROM_SHIFT)) & RCM_FM_FORCEROM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11652 | |
AnnaBridge | 171:3a7713b1edbc | 11653 | /*! @name MR - Mode Register */ |
AnnaBridge | 171:3a7713b1edbc | 11654 | #define RCM_MR_BOOTROM_MASK (0x6U) |
AnnaBridge | 171:3a7713b1edbc | 11655 | #define RCM_MR_BOOTROM_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 11656 | #define RCM_MR_BOOTROM(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_BOOTROM_SHIFT)) & RCM_MR_BOOTROM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11657 | |
AnnaBridge | 171:3a7713b1edbc | 11658 | /*! @name SSRS0 - Sticky System Reset Status Register 0 */ |
AnnaBridge | 171:3a7713b1edbc | 11659 | #define RCM_SSRS0_SWAKEUP_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11660 | #define RCM_SSRS0_SWAKEUP_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11661 | #define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11662 | #define RCM_SSRS0_SLVD_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 11663 | #define RCM_SSRS0_SLVD_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 11664 | #define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11665 | #define RCM_SSRS0_SLOC_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 11666 | #define RCM_SSRS0_SLOC_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 11667 | #define RCM_SSRS0_SLOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOC_SHIFT)) & RCM_SSRS0_SLOC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11668 | #define RCM_SSRS0_SLOL_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 11669 | #define RCM_SSRS0_SLOL_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 11670 | #define RCM_SSRS0_SLOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOL_SHIFT)) & RCM_SSRS0_SLOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11671 | #define RCM_SSRS0_SWDOG_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 11672 | #define RCM_SSRS0_SWDOG_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 11673 | #define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11674 | #define RCM_SSRS0_SPIN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 11675 | #define RCM_SSRS0_SPIN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 11676 | #define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11677 | #define RCM_SSRS0_SPOR_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 11678 | #define RCM_SSRS0_SPOR_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 11679 | #define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11680 | |
AnnaBridge | 171:3a7713b1edbc | 11681 | /*! @name SSRS1 - Sticky System Reset Status Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 11682 | #define RCM_SSRS1_SJTAG_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11683 | #define RCM_SSRS1_SJTAG_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11684 | #define RCM_SSRS1_SJTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SJTAG_SHIFT)) & RCM_SSRS1_SJTAG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11685 | #define RCM_SSRS1_SLOCKUP_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 11686 | #define RCM_SSRS1_SLOCKUP_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 11687 | #define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11688 | #define RCM_SSRS1_SSW_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 11689 | #define RCM_SSRS1_SSW_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 11690 | #define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11691 | #define RCM_SSRS1_SMDM_AP_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 11692 | #define RCM_SSRS1_SMDM_AP_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 11693 | #define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11694 | #define RCM_SSRS1_SSACKERR_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 11695 | #define RCM_SSRS1_SSACKERR_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 11696 | #define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11697 | |
AnnaBridge | 171:3a7713b1edbc | 11698 | |
AnnaBridge | 171:3a7713b1edbc | 11699 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11700 | * @} |
AnnaBridge | 171:3a7713b1edbc | 11701 | */ /* end of group RCM_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 11702 | |
AnnaBridge | 171:3a7713b1edbc | 11703 | |
AnnaBridge | 171:3a7713b1edbc | 11704 | /* RCM - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 11705 | /** Peripheral RCM base address */ |
AnnaBridge | 171:3a7713b1edbc | 11706 | #define RCM_BASE (0x4007F000u) |
AnnaBridge | 171:3a7713b1edbc | 11707 | /** Peripheral RCM base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 11708 | #define RCM ((RCM_Type *)RCM_BASE) |
AnnaBridge | 171:3a7713b1edbc | 11709 | /** Array initializer of RCM peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 11710 | #define RCM_BASE_ADDRS { RCM_BASE } |
AnnaBridge | 171:3a7713b1edbc | 11711 | /** Array initializer of RCM peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 11712 | #define RCM_BASE_PTRS { RCM } |
AnnaBridge | 171:3a7713b1edbc | 11713 | |
AnnaBridge | 171:3a7713b1edbc | 11714 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11715 | * @} |
AnnaBridge | 171:3a7713b1edbc | 11716 | */ /* end of group RCM_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 11717 | |
AnnaBridge | 171:3a7713b1edbc | 11718 | |
AnnaBridge | 171:3a7713b1edbc | 11719 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 11720 | -- RFSYS Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 11721 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 11722 | |
AnnaBridge | 171:3a7713b1edbc | 11723 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11724 | * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 11725 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 11726 | */ |
AnnaBridge | 171:3a7713b1edbc | 11727 | |
AnnaBridge | 171:3a7713b1edbc | 11728 | /** RFSYS - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 11729 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 11730 | __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 11731 | } RFSYS_Type; |
AnnaBridge | 171:3a7713b1edbc | 11732 | |
AnnaBridge | 171:3a7713b1edbc | 11733 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 11734 | -- RFSYS Register Masks |
AnnaBridge | 171:3a7713b1edbc | 11735 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 11736 | |
AnnaBridge | 171:3a7713b1edbc | 11737 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11738 | * @addtogroup RFSYS_Register_Masks RFSYS Register Masks |
AnnaBridge | 171:3a7713b1edbc | 11739 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 11740 | */ |
AnnaBridge | 171:3a7713b1edbc | 11741 | |
AnnaBridge | 171:3a7713b1edbc | 11742 | /*! @name REG - Register file register */ |
AnnaBridge | 171:3a7713b1edbc | 11743 | #define RFSYS_REG_LL_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 11744 | #define RFSYS_REG_LL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11745 | #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11746 | #define RFSYS_REG_LH_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 11747 | #define RFSYS_REG_LH_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 11748 | #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11749 | #define RFSYS_REG_HL_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 11750 | #define RFSYS_REG_HL_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 11751 | #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11752 | #define RFSYS_REG_HH_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 11753 | #define RFSYS_REG_HH_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 11754 | #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11755 | |
AnnaBridge | 171:3a7713b1edbc | 11756 | /* The count of RFSYS_REG */ |
AnnaBridge | 171:3a7713b1edbc | 11757 | #define RFSYS_REG_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 11758 | |
AnnaBridge | 171:3a7713b1edbc | 11759 | |
AnnaBridge | 171:3a7713b1edbc | 11760 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11761 | * @} |
AnnaBridge | 171:3a7713b1edbc | 11762 | */ /* end of group RFSYS_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 11763 | |
AnnaBridge | 171:3a7713b1edbc | 11764 | |
AnnaBridge | 171:3a7713b1edbc | 11765 | /* RFSYS - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 11766 | /** Peripheral RFSYS base address */ |
AnnaBridge | 171:3a7713b1edbc | 11767 | #define RFSYS_BASE (0x40041000u) |
AnnaBridge | 171:3a7713b1edbc | 11768 | /** Peripheral RFSYS base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 11769 | #define RFSYS ((RFSYS_Type *)RFSYS_BASE) |
AnnaBridge | 171:3a7713b1edbc | 11770 | /** Array initializer of RFSYS peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 11771 | #define RFSYS_BASE_ADDRS { RFSYS_BASE } |
AnnaBridge | 171:3a7713b1edbc | 11772 | /** Array initializer of RFSYS peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 11773 | #define RFSYS_BASE_PTRS { RFSYS } |
AnnaBridge | 171:3a7713b1edbc | 11774 | |
AnnaBridge | 171:3a7713b1edbc | 11775 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11776 | * @} |
AnnaBridge | 171:3a7713b1edbc | 11777 | */ /* end of group RFSYS_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 11778 | |
AnnaBridge | 171:3a7713b1edbc | 11779 | |
AnnaBridge | 171:3a7713b1edbc | 11780 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 11781 | -- RFVBAT Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 11782 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 11783 | |
AnnaBridge | 171:3a7713b1edbc | 11784 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11785 | * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 11786 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 11787 | */ |
AnnaBridge | 171:3a7713b1edbc | 11788 | |
AnnaBridge | 171:3a7713b1edbc | 11789 | /** RFVBAT - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 11790 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 11791 | __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 11792 | } RFVBAT_Type; |
AnnaBridge | 171:3a7713b1edbc | 11793 | |
AnnaBridge | 171:3a7713b1edbc | 11794 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 11795 | -- RFVBAT Register Masks |
AnnaBridge | 171:3a7713b1edbc | 11796 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 11797 | |
AnnaBridge | 171:3a7713b1edbc | 11798 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11799 | * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks |
AnnaBridge | 171:3a7713b1edbc | 11800 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 11801 | */ |
AnnaBridge | 171:3a7713b1edbc | 11802 | |
AnnaBridge | 171:3a7713b1edbc | 11803 | /*! @name REG - VBAT register file register */ |
AnnaBridge | 171:3a7713b1edbc | 11804 | #define RFVBAT_REG_LL_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 11805 | #define RFVBAT_REG_LL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11806 | #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11807 | #define RFVBAT_REG_LH_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 11808 | #define RFVBAT_REG_LH_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 11809 | #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11810 | #define RFVBAT_REG_HL_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 11811 | #define RFVBAT_REG_HL_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 11812 | #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11813 | #define RFVBAT_REG_HH_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 11814 | #define RFVBAT_REG_HH_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 11815 | #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11816 | |
AnnaBridge | 171:3a7713b1edbc | 11817 | /* The count of RFVBAT_REG */ |
AnnaBridge | 171:3a7713b1edbc | 11818 | #define RFVBAT_REG_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 11819 | |
AnnaBridge | 171:3a7713b1edbc | 11820 | |
AnnaBridge | 171:3a7713b1edbc | 11821 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11822 | * @} |
AnnaBridge | 171:3a7713b1edbc | 11823 | */ /* end of group RFVBAT_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 11824 | |
AnnaBridge | 171:3a7713b1edbc | 11825 | |
AnnaBridge | 171:3a7713b1edbc | 11826 | /* RFVBAT - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 11827 | /** Peripheral RFVBAT base address */ |
AnnaBridge | 171:3a7713b1edbc | 11828 | #define RFVBAT_BASE (0x4003E000u) |
AnnaBridge | 171:3a7713b1edbc | 11829 | /** Peripheral RFVBAT base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 11830 | #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE) |
AnnaBridge | 171:3a7713b1edbc | 11831 | /** Array initializer of RFVBAT peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 11832 | #define RFVBAT_BASE_ADDRS { RFVBAT_BASE } |
AnnaBridge | 171:3a7713b1edbc | 11833 | /** Array initializer of RFVBAT peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 11834 | #define RFVBAT_BASE_PTRS { RFVBAT } |
AnnaBridge | 171:3a7713b1edbc | 11835 | |
AnnaBridge | 171:3a7713b1edbc | 11836 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11837 | * @} |
AnnaBridge | 171:3a7713b1edbc | 11838 | */ /* end of group RFVBAT_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 11839 | |
AnnaBridge | 171:3a7713b1edbc | 11840 | |
AnnaBridge | 171:3a7713b1edbc | 11841 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 11842 | -- RTC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 11843 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 11844 | |
AnnaBridge | 171:3a7713b1edbc | 11845 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11846 | * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 11847 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 11848 | */ |
AnnaBridge | 171:3a7713b1edbc | 11849 | |
AnnaBridge | 171:3a7713b1edbc | 11850 | /** RTC - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 11851 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 11852 | __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 11853 | __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 11854 | __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 11855 | __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 11856 | __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 11857 | __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 11858 | __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 11859 | __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 11860 | uint8_t RESERVED_0[2016]; |
AnnaBridge | 171:3a7713b1edbc | 11861 | __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */ |
AnnaBridge | 171:3a7713b1edbc | 11862 | __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */ |
AnnaBridge | 171:3a7713b1edbc | 11863 | } RTC_Type; |
AnnaBridge | 171:3a7713b1edbc | 11864 | |
AnnaBridge | 171:3a7713b1edbc | 11865 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 11866 | -- RTC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 11867 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 11868 | |
AnnaBridge | 171:3a7713b1edbc | 11869 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11870 | * @addtogroup RTC_Register_Masks RTC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 11871 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 11872 | */ |
AnnaBridge | 171:3a7713b1edbc | 11873 | |
AnnaBridge | 171:3a7713b1edbc | 11874 | /*! @name TSR - RTC Time Seconds Register */ |
AnnaBridge | 171:3a7713b1edbc | 11875 | #define RTC_TSR_TSR_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 11876 | #define RTC_TSR_TSR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11877 | #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11878 | |
AnnaBridge | 171:3a7713b1edbc | 11879 | /*! @name TPR - RTC Time Prescaler Register */ |
AnnaBridge | 171:3a7713b1edbc | 11880 | #define RTC_TPR_TPR_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 11881 | #define RTC_TPR_TPR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11882 | #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11883 | |
AnnaBridge | 171:3a7713b1edbc | 11884 | /*! @name TAR - RTC Time Alarm Register */ |
AnnaBridge | 171:3a7713b1edbc | 11885 | #define RTC_TAR_TAR_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 11886 | #define RTC_TAR_TAR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11887 | #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11888 | |
AnnaBridge | 171:3a7713b1edbc | 11889 | /*! @name TCR - RTC Time Compensation Register */ |
AnnaBridge | 171:3a7713b1edbc | 11890 | #define RTC_TCR_TCR_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 11891 | #define RTC_TCR_TCR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11892 | #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11893 | #define RTC_TCR_CIR_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 11894 | #define RTC_TCR_CIR_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 11895 | #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11896 | #define RTC_TCR_TCV_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 11897 | #define RTC_TCR_TCV_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 11898 | #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11899 | #define RTC_TCR_CIC_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 11900 | #define RTC_TCR_CIC_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 11901 | #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11902 | |
AnnaBridge | 171:3a7713b1edbc | 11903 | /*! @name CR - RTC Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 11904 | #define RTC_CR_SWR_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11905 | #define RTC_CR_SWR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11906 | #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11907 | #define RTC_CR_WPE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 11908 | #define RTC_CR_WPE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 11909 | #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11910 | #define RTC_CR_SUP_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 11911 | #define RTC_CR_SUP_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 11912 | #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11913 | #define RTC_CR_UM_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 11914 | #define RTC_CR_UM_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 11915 | #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11916 | #define RTC_CR_WPS_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 11917 | #define RTC_CR_WPS_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 11918 | #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11919 | #define RTC_CR_OSCE_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 11920 | #define RTC_CR_OSCE_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 11921 | #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11922 | #define RTC_CR_CLKO_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 11923 | #define RTC_CR_CLKO_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 11924 | #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11925 | #define RTC_CR_SC16P_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 11926 | #define RTC_CR_SC16P_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 11927 | #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11928 | #define RTC_CR_SC8P_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 11929 | #define RTC_CR_SC8P_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 11930 | #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11931 | #define RTC_CR_SC4P_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 11932 | #define RTC_CR_SC4P_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 11933 | #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11934 | #define RTC_CR_SC2P_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 11935 | #define RTC_CR_SC2P_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 11936 | #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11937 | |
AnnaBridge | 171:3a7713b1edbc | 11938 | /*! @name SR - RTC Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 11939 | #define RTC_SR_TIF_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11940 | #define RTC_SR_TIF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11941 | #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11942 | #define RTC_SR_TOF_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 11943 | #define RTC_SR_TOF_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 11944 | #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11945 | #define RTC_SR_TAF_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 11946 | #define RTC_SR_TAF_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 11947 | #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11948 | #define RTC_SR_TCE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 11949 | #define RTC_SR_TCE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 11950 | #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11951 | |
AnnaBridge | 171:3a7713b1edbc | 11952 | /*! @name LR - RTC Lock Register */ |
AnnaBridge | 171:3a7713b1edbc | 11953 | #define RTC_LR_TCL_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 11954 | #define RTC_LR_TCL_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 11955 | #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11956 | #define RTC_LR_CRL_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 11957 | #define RTC_LR_CRL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 11958 | #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11959 | #define RTC_LR_SRL_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 11960 | #define RTC_LR_SRL_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 11961 | #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11962 | #define RTC_LR_LRL_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 11963 | #define RTC_LR_LRL_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 11964 | #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11965 | |
AnnaBridge | 171:3a7713b1edbc | 11966 | /*! @name IER - RTC Interrupt Enable Register */ |
AnnaBridge | 171:3a7713b1edbc | 11967 | #define RTC_IER_TIIE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11968 | #define RTC_IER_TIIE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11969 | #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11970 | #define RTC_IER_TOIE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 11971 | #define RTC_IER_TOIE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 11972 | #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11973 | #define RTC_IER_TAIE_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 11974 | #define RTC_IER_TAIE_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 11975 | #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11976 | #define RTC_IER_TSIE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 11977 | #define RTC_IER_TSIE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 11978 | #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11979 | #define RTC_IER_WPON_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 11980 | #define RTC_IER_WPON_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 11981 | #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11982 | |
AnnaBridge | 171:3a7713b1edbc | 11983 | /*! @name WAR - RTC Write Access Register */ |
AnnaBridge | 171:3a7713b1edbc | 11984 | #define RTC_WAR_TSRW_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11985 | #define RTC_WAR_TSRW_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11986 | #define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11987 | #define RTC_WAR_TPRW_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 11988 | #define RTC_WAR_TPRW_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 11989 | #define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11990 | #define RTC_WAR_TARW_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 11991 | #define RTC_WAR_TARW_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 11992 | #define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11993 | #define RTC_WAR_TCRW_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 11994 | #define RTC_WAR_TCRW_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 11995 | #define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11996 | #define RTC_WAR_CRW_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 11997 | #define RTC_WAR_CRW_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 11998 | #define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11999 | #define RTC_WAR_SRW_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 12000 | #define RTC_WAR_SRW_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 12001 | #define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12002 | #define RTC_WAR_LRW_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 12003 | #define RTC_WAR_LRW_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 12004 | #define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12005 | #define RTC_WAR_IERW_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 12006 | #define RTC_WAR_IERW_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 12007 | #define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12008 | |
AnnaBridge | 171:3a7713b1edbc | 12009 | /*! @name RAR - RTC Read Access Register */ |
AnnaBridge | 171:3a7713b1edbc | 12010 | #define RTC_RAR_TSRR_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 12011 | #define RTC_RAR_TSRR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12012 | #define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12013 | #define RTC_RAR_TPRR_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 12014 | #define RTC_RAR_TPRR_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 12015 | #define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12016 | #define RTC_RAR_TARR_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 12017 | #define RTC_RAR_TARR_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 12018 | #define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12019 | #define RTC_RAR_TCRR_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 12020 | #define RTC_RAR_TCRR_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 12021 | #define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12022 | #define RTC_RAR_CRR_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 12023 | #define RTC_RAR_CRR_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 12024 | #define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12025 | #define RTC_RAR_SRR_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 12026 | #define RTC_RAR_SRR_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 12027 | #define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12028 | #define RTC_RAR_LRR_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 12029 | #define RTC_RAR_LRR_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 12030 | #define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12031 | #define RTC_RAR_IERR_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 12032 | #define RTC_RAR_IERR_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 12033 | #define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12034 | |
AnnaBridge | 171:3a7713b1edbc | 12035 | |
AnnaBridge | 171:3a7713b1edbc | 12036 | /*! |
AnnaBridge | 171:3a7713b1edbc | 12037 | * @} |
AnnaBridge | 171:3a7713b1edbc | 12038 | */ /* end of group RTC_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 12039 | |
AnnaBridge | 171:3a7713b1edbc | 12040 | |
AnnaBridge | 171:3a7713b1edbc | 12041 | /* RTC - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 12042 | /** Peripheral RTC base address */ |
AnnaBridge | 171:3a7713b1edbc | 12043 | #define RTC_BASE (0x4003D000u) |
AnnaBridge | 171:3a7713b1edbc | 12044 | /** Peripheral RTC base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 12045 | #define RTC ((RTC_Type *)RTC_BASE) |
AnnaBridge | 171:3a7713b1edbc | 12046 | /** Array initializer of RTC peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 12047 | #define RTC_BASE_ADDRS { RTC_BASE } |
AnnaBridge | 171:3a7713b1edbc | 12048 | /** Array initializer of RTC peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 12049 | #define RTC_BASE_PTRS { RTC } |
AnnaBridge | 171:3a7713b1edbc | 12050 | /** Interrupt vectors for the RTC peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 12051 | #define RTC_IRQS { RTC_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 12052 | #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 12053 | |
AnnaBridge | 171:3a7713b1edbc | 12054 | /*! |
AnnaBridge | 171:3a7713b1edbc | 12055 | * @} |
AnnaBridge | 171:3a7713b1edbc | 12056 | */ /* end of group RTC_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 12057 | |
AnnaBridge | 171:3a7713b1edbc | 12058 | |
AnnaBridge | 171:3a7713b1edbc | 12059 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 12060 | -- SDHC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 12061 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 12062 | |
AnnaBridge | 171:3a7713b1edbc | 12063 | /*! |
AnnaBridge | 171:3a7713b1edbc | 12064 | * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 12065 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 12066 | */ |
AnnaBridge | 171:3a7713b1edbc | 12067 | |
AnnaBridge | 171:3a7713b1edbc | 12068 | /** SDHC - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 12069 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 12070 | __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 12071 | __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 12072 | __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 12073 | __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 12074 | __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 12075 | __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 12076 | __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 12077 | __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */ |
AnnaBridge | 171:3a7713b1edbc | 12078 | __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */ |
AnnaBridge | 171:3a7713b1edbc | 12079 | __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */ |
AnnaBridge | 171:3a7713b1edbc | 12080 | __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 12081 | __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */ |
AnnaBridge | 171:3a7713b1edbc | 12082 | __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */ |
AnnaBridge | 171:3a7713b1edbc | 12083 | __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */ |
AnnaBridge | 171:3a7713b1edbc | 12084 | __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */ |
AnnaBridge | 171:3a7713b1edbc | 12085 | uint8_t RESERVED_0[8]; |
AnnaBridge | 171:3a7713b1edbc | 12086 | __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */ |
AnnaBridge | 171:3a7713b1edbc | 12087 | __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */ |
AnnaBridge | 171:3a7713b1edbc | 12088 | __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */ |
AnnaBridge | 171:3a7713b1edbc | 12089 | uint8_t RESERVED_1[100]; |
AnnaBridge | 171:3a7713b1edbc | 12090 | __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */ |
AnnaBridge | 171:3a7713b1edbc | 12091 | __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */ |
AnnaBridge | 171:3a7713b1edbc | 12092 | uint8_t RESERVED_2[52]; |
AnnaBridge | 171:3a7713b1edbc | 12093 | __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */ |
AnnaBridge | 171:3a7713b1edbc | 12094 | } SDHC_Type; |
AnnaBridge | 171:3a7713b1edbc | 12095 | |
AnnaBridge | 171:3a7713b1edbc | 12096 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 12097 | -- SDHC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 12098 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 12099 | |
AnnaBridge | 171:3a7713b1edbc | 12100 | /*! |
AnnaBridge | 171:3a7713b1edbc | 12101 | * @addtogroup SDHC_Register_Masks SDHC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 12102 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 12103 | */ |
AnnaBridge | 171:3a7713b1edbc | 12104 | |
AnnaBridge | 171:3a7713b1edbc | 12105 | /*! @name DSADDR - DMA System Address register */ |
AnnaBridge | 171:3a7713b1edbc | 12106 | #define SDHC_DSADDR_DSADDR_MASK (0xFFFFFFFCU) |
AnnaBridge | 171:3a7713b1edbc | 12107 | #define SDHC_DSADDR_DSADDR_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 12108 | #define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12109 | |
AnnaBridge | 171:3a7713b1edbc | 12110 | /*! @name BLKATTR - Block Attributes register */ |
AnnaBridge | 171:3a7713b1edbc | 12111 | #define SDHC_BLKATTR_BLKSIZE_MASK (0x1FFFU) |
AnnaBridge | 171:3a7713b1edbc | 12112 | #define SDHC_BLKATTR_BLKSIZE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12113 | #define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12114 | #define SDHC_BLKATTR_BLKCNT_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 12115 | #define SDHC_BLKATTR_BLKCNT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 12116 | #define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12117 | |
AnnaBridge | 171:3a7713b1edbc | 12118 | /*! @name CMDARG - Command Argument register */ |
AnnaBridge | 171:3a7713b1edbc | 12119 | #define SDHC_CMDARG_CMDARG_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 12120 | #define SDHC_CMDARG_CMDARG_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12121 | #define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12122 | |
AnnaBridge | 171:3a7713b1edbc | 12123 | /*! @name XFERTYP - Transfer Type register */ |
AnnaBridge | 171:3a7713b1edbc | 12124 | #define SDHC_XFERTYP_DMAEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 12125 | #define SDHC_XFERTYP_DMAEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12126 | #define SDHC_XFERTYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12127 | #define SDHC_XFERTYP_BCEN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 12128 | #define SDHC_XFERTYP_BCEN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 12129 | #define SDHC_XFERTYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12130 | #define SDHC_XFERTYP_AC12EN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 12131 | #define SDHC_XFERTYP_AC12EN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 12132 | #define SDHC_XFERTYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12133 | #define SDHC_XFERTYP_DTDSEL_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 12134 | #define SDHC_XFERTYP_DTDSEL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 12135 | #define SDHC_XFERTYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12136 | #define SDHC_XFERTYP_MSBSEL_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 12137 | #define SDHC_XFERTYP_MSBSEL_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 12138 | #define SDHC_XFERTYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12139 | #define SDHC_XFERTYP_RSPTYP_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 12140 | #define SDHC_XFERTYP_RSPTYP_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 12141 | #define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12142 | #define SDHC_XFERTYP_CCCEN_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 12143 | #define SDHC_XFERTYP_CCCEN_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 12144 | #define SDHC_XFERTYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12145 | #define SDHC_XFERTYP_CICEN_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 12146 | #define SDHC_XFERTYP_CICEN_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 12147 | #define SDHC_XFERTYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12148 | #define SDHC_XFERTYP_DPSEL_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 12149 | #define SDHC_XFERTYP_DPSEL_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 12150 | #define SDHC_XFERTYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12151 | #define SDHC_XFERTYP_CMDTYP_MASK (0xC00000U) |
AnnaBridge | 171:3a7713b1edbc | 12152 | #define SDHC_XFERTYP_CMDTYP_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 12153 | #define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12154 | #define SDHC_XFERTYP_CMDINX_MASK (0x3F000000U) |
AnnaBridge | 171:3a7713b1edbc | 12155 | #define SDHC_XFERTYP_CMDINX_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 12156 | #define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12157 | |
AnnaBridge | 171:3a7713b1edbc | 12158 | /*! @name CMDRSP - Command Response 0..Command Response 3 */ |
AnnaBridge | 171:3a7713b1edbc | 12159 | #define SDHC_CMDRSP_CMDRSP0_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 12160 | #define SDHC_CMDRSP_CMDRSP0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12161 | #define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12162 | #define SDHC_CMDRSP_CMDRSP1_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 12163 | #define SDHC_CMDRSP_CMDRSP1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12164 | #define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12165 | #define SDHC_CMDRSP_CMDRSP2_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 12166 | #define SDHC_CMDRSP_CMDRSP2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12167 | #define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12168 | #define SDHC_CMDRSP_CMDRSP3_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 12169 | #define SDHC_CMDRSP_CMDRSP3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12170 | #define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12171 | |
AnnaBridge | 171:3a7713b1edbc | 12172 | /* The count of SDHC_CMDRSP */ |
AnnaBridge | 171:3a7713b1edbc | 12173 | #define SDHC_CMDRSP_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 12174 | |
AnnaBridge | 171:3a7713b1edbc | 12175 | /*! @name DATPORT - Buffer Data Port register */ |
AnnaBridge | 171:3a7713b1edbc | 12176 | #define SDHC_DATPORT_DATCONT_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 12177 | #define SDHC_DATPORT_DATCONT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12178 | #define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12179 | |
AnnaBridge | 171:3a7713b1edbc | 12180 | /*! @name PRSSTAT - Present State register */ |
AnnaBridge | 171:3a7713b1edbc | 12181 | #define SDHC_PRSSTAT_CIHB_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 12182 | #define SDHC_PRSSTAT_CIHB_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12183 | #define SDHC_PRSSTAT_CIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12184 | #define SDHC_PRSSTAT_CDIHB_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 12185 | #define SDHC_PRSSTAT_CDIHB_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 12186 | #define SDHC_PRSSTAT_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12187 | #define SDHC_PRSSTAT_DLA_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 12188 | #define SDHC_PRSSTAT_DLA_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 12189 | #define SDHC_PRSSTAT_DLA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12190 | #define SDHC_PRSSTAT_SDSTB_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 12191 | #define SDHC_PRSSTAT_SDSTB_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 12192 | #define SDHC_PRSSTAT_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12193 | #define SDHC_PRSSTAT_IPGOFF_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 12194 | #define SDHC_PRSSTAT_IPGOFF_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 12195 | #define SDHC_PRSSTAT_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12196 | #define SDHC_PRSSTAT_HCKOFF_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 12197 | #define SDHC_PRSSTAT_HCKOFF_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 12198 | #define SDHC_PRSSTAT_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12199 | #define SDHC_PRSSTAT_PEROFF_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 12200 | #define SDHC_PRSSTAT_PEROFF_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 12201 | #define SDHC_PRSSTAT_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12202 | #define SDHC_PRSSTAT_SDOFF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 12203 | #define SDHC_PRSSTAT_SDOFF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 12204 | #define SDHC_PRSSTAT_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12205 | #define SDHC_PRSSTAT_WTA_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 12206 | #define SDHC_PRSSTAT_WTA_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 12207 | #define SDHC_PRSSTAT_WTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12208 | #define SDHC_PRSSTAT_RTA_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 12209 | #define SDHC_PRSSTAT_RTA_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 12210 | #define SDHC_PRSSTAT_RTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12211 | #define SDHC_PRSSTAT_BWEN_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 12212 | #define SDHC_PRSSTAT_BWEN_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 12213 | #define SDHC_PRSSTAT_BWEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12214 | #define SDHC_PRSSTAT_BREN_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 12215 | #define SDHC_PRSSTAT_BREN_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 12216 | #define SDHC_PRSSTAT_BREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12217 | #define SDHC_PRSSTAT_CINS_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 12218 | #define SDHC_PRSSTAT_CINS_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 12219 | #define SDHC_PRSSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12220 | #define SDHC_PRSSTAT_CLSL_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 12221 | #define SDHC_PRSSTAT_CLSL_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 12222 | #define SDHC_PRSSTAT_CLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12223 | #define SDHC_PRSSTAT_DLSL_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 12224 | #define SDHC_PRSSTAT_DLSL_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 12225 | #define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12226 | |
AnnaBridge | 171:3a7713b1edbc | 12227 | /*! @name PROCTL - Protocol Control register */ |
AnnaBridge | 171:3a7713b1edbc | 12228 | #define SDHC_PROCTL_LCTL_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 12229 | #define SDHC_PROCTL_LCTL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12230 | #define SDHC_PROCTL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12231 | #define SDHC_PROCTL_DTW_MASK (0x6U) |
AnnaBridge | 171:3a7713b1edbc | 12232 | #define SDHC_PROCTL_DTW_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 12233 | #define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12234 | #define SDHC_PROCTL_D3CD_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 12235 | #define SDHC_PROCTL_D3CD_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 12236 | #define SDHC_PROCTL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12237 | #define SDHC_PROCTL_EMODE_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 12238 | #define SDHC_PROCTL_EMODE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 12239 | #define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12240 | #define SDHC_PROCTL_CDTL_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 12241 | #define SDHC_PROCTL_CDTL_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 12242 | #define SDHC_PROCTL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12243 | #define SDHC_PROCTL_CDSS_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 12244 | #define SDHC_PROCTL_CDSS_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 12245 | #define SDHC_PROCTL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12246 | #define SDHC_PROCTL_DMAS_MASK (0x300U) |
AnnaBridge | 171:3a7713b1edbc | 12247 | #define SDHC_PROCTL_DMAS_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 12248 | #define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12249 | #define SDHC_PROCTL_SABGREQ_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 12250 | #define SDHC_PROCTL_SABGREQ_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 12251 | #define SDHC_PROCTL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12252 | #define SDHC_PROCTL_CREQ_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 12253 | #define SDHC_PROCTL_CREQ_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 12254 | #define SDHC_PROCTL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12255 | #define SDHC_PROCTL_RWCTL_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 12256 | #define SDHC_PROCTL_RWCTL_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 12257 | #define SDHC_PROCTL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12258 | #define SDHC_PROCTL_IABG_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 12259 | #define SDHC_PROCTL_IABG_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 12260 | #define SDHC_PROCTL_IABG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12261 | #define SDHC_PROCTL_WECINT_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 12262 | #define SDHC_PROCTL_WECINT_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 12263 | #define SDHC_PROCTL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12264 | #define SDHC_PROCTL_WECINS_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 12265 | #define SDHC_PROCTL_WECINS_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 12266 | #define SDHC_PROCTL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12267 | #define SDHC_PROCTL_WECRM_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 12268 | #define SDHC_PROCTL_WECRM_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 12269 | #define SDHC_PROCTL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12270 | |
AnnaBridge | 171:3a7713b1edbc | 12271 | /*! @name SYSCTL - System Control register */ |
AnnaBridge | 171:3a7713b1edbc | 12272 | #define SDHC_SYSCTL_IPGEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 12273 | #define SDHC_SYSCTL_IPGEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12274 | #define SDHC_SYSCTL_IPGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12275 | #define SDHC_SYSCTL_HCKEN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 12276 | #define SDHC_SYSCTL_HCKEN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 12277 | #define SDHC_SYSCTL_HCKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12278 | #define SDHC_SYSCTL_PEREN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 12279 | #define SDHC_SYSCTL_PEREN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 12280 | #define SDHC_SYSCTL_PEREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12281 | #define SDHC_SYSCTL_SDCLKEN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 12282 | #define SDHC_SYSCTL_SDCLKEN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 12283 | #define SDHC_SYSCTL_SDCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12284 | #define SDHC_SYSCTL_DVS_MASK (0xF0U) |
AnnaBridge | 171:3a7713b1edbc | 12285 | #define SDHC_SYSCTL_DVS_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 12286 | #define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12287 | #define SDHC_SYSCTL_SDCLKFS_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 12288 | #define SDHC_SYSCTL_SDCLKFS_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 12289 | #define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12290 | #define SDHC_SYSCTL_DTOCV_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 12291 | #define SDHC_SYSCTL_DTOCV_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 12292 | #define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12293 | #define SDHC_SYSCTL_RSTA_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 12294 | #define SDHC_SYSCTL_RSTA_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 12295 | #define SDHC_SYSCTL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12296 | #define SDHC_SYSCTL_RSTC_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 12297 | #define SDHC_SYSCTL_RSTC_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 12298 | #define SDHC_SYSCTL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12299 | #define SDHC_SYSCTL_RSTD_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 12300 | #define SDHC_SYSCTL_RSTD_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 12301 | #define SDHC_SYSCTL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12302 | #define SDHC_SYSCTL_INITA_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 12303 | #define SDHC_SYSCTL_INITA_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 12304 | #define SDHC_SYSCTL_INITA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12305 | |
AnnaBridge | 171:3a7713b1edbc | 12306 | /*! @name IRQSTAT - Interrupt Status register */ |
AnnaBridge | 171:3a7713b1edbc | 12307 | #define SDHC_IRQSTAT_CC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 12308 | #define SDHC_IRQSTAT_CC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12309 | #define SDHC_IRQSTAT_CC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12310 | #define SDHC_IRQSTAT_TC_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 12311 | #define SDHC_IRQSTAT_TC_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 12312 | #define SDHC_IRQSTAT_TC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12313 | #define SDHC_IRQSTAT_BGE_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 12314 | #define SDHC_IRQSTAT_BGE_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 12315 | #define SDHC_IRQSTAT_BGE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12316 | #define SDHC_IRQSTAT_DINT_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 12317 | #define SDHC_IRQSTAT_DINT_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 12318 | #define SDHC_IRQSTAT_DINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12319 | #define SDHC_IRQSTAT_BWR_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 12320 | #define SDHC_IRQSTAT_BWR_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 12321 | #define SDHC_IRQSTAT_BWR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12322 | #define SDHC_IRQSTAT_BRR_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 12323 | #define SDHC_IRQSTAT_BRR_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 12324 | #define SDHC_IRQSTAT_BRR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12325 | #define SDHC_IRQSTAT_CINS_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 12326 | #define SDHC_IRQSTAT_CINS_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 12327 | #define SDHC_IRQSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12328 | #define SDHC_IRQSTAT_CRM_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 12329 | #define SDHC_IRQSTAT_CRM_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 12330 | #define SDHC_IRQSTAT_CRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12331 | #define SDHC_IRQSTAT_CINT_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 12332 | #define SDHC_IRQSTAT_CINT_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 12333 | #define SDHC_IRQSTAT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12334 | #define SDHC_IRQSTAT_CTOE_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 12335 | #define SDHC_IRQSTAT_CTOE_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 12336 | #define SDHC_IRQSTAT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12337 | #define SDHC_IRQSTAT_CCE_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 12338 | #define SDHC_IRQSTAT_CCE_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 12339 | #define SDHC_IRQSTAT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12340 | #define SDHC_IRQSTAT_CEBE_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 12341 | #define SDHC_IRQSTAT_CEBE_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 12342 | #define SDHC_IRQSTAT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12343 | #define SDHC_IRQSTAT_CIE_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 12344 | #define SDHC_IRQSTAT_CIE_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 12345 | #define SDHC_IRQSTAT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12346 | #define SDHC_IRQSTAT_DTOE_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 12347 | #define SDHC_IRQSTAT_DTOE_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 12348 | #define SDHC_IRQSTAT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12349 | #define SDHC_IRQSTAT_DCE_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 12350 | #define SDHC_IRQSTAT_DCE_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 12351 | #define SDHC_IRQSTAT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12352 | #define SDHC_IRQSTAT_DEBE_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 12353 | #define SDHC_IRQSTAT_DEBE_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 12354 | #define SDHC_IRQSTAT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12355 | #define SDHC_IRQSTAT_AC12E_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 12356 | #define SDHC_IRQSTAT_AC12E_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 12357 | #define SDHC_IRQSTAT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12358 | #define SDHC_IRQSTAT_DMAE_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 12359 | #define SDHC_IRQSTAT_DMAE_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 12360 | #define SDHC_IRQSTAT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12361 | |
AnnaBridge | 171:3a7713b1edbc | 12362 | /*! @name IRQSTATEN - Interrupt Status Enable register */ |
AnnaBridge | 171:3a7713b1edbc | 12363 | #define SDHC_IRQSTATEN_CCSEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 12364 | #define SDHC_IRQSTATEN_CCSEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12365 | #define SDHC_IRQSTATEN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12366 | #define SDHC_IRQSTATEN_TCSEN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 12367 | #define SDHC_IRQSTATEN_TCSEN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 12368 | #define SDHC_IRQSTATEN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12369 | #define SDHC_IRQSTATEN_BGESEN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 12370 | #define SDHC_IRQSTATEN_BGESEN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 12371 | #define SDHC_IRQSTATEN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12372 | #define SDHC_IRQSTATEN_DINTSEN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 12373 | #define SDHC_IRQSTATEN_DINTSEN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 12374 | #define SDHC_IRQSTATEN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12375 | #define SDHC_IRQSTATEN_BWRSEN_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 12376 | #define SDHC_IRQSTATEN_BWRSEN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 12377 | #define SDHC_IRQSTATEN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12378 | #define SDHC_IRQSTATEN_BRRSEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 12379 | #define SDHC_IRQSTATEN_BRRSEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 12380 | #define SDHC_IRQSTATEN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12381 | #define SDHC_IRQSTATEN_CINSEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 12382 | #define SDHC_IRQSTATEN_CINSEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 12383 | #define SDHC_IRQSTATEN_CINSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12384 | #define SDHC_IRQSTATEN_CRMSEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 12385 | #define SDHC_IRQSTATEN_CRMSEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 12386 | #define SDHC_IRQSTATEN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12387 | #define SDHC_IRQSTATEN_CINTSEN_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 12388 | #define SDHC_IRQSTATEN_CINTSEN_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 12389 | #define SDHC_IRQSTATEN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12390 | #define SDHC_IRQSTATEN_CTOESEN_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 12391 | #define SDHC_IRQSTATEN_CTOESEN_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 12392 | #define SDHC_IRQSTATEN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12393 | #define SDHC_IRQSTATEN_CCESEN_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 12394 | #define SDHC_IRQSTATEN_CCESEN_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 12395 | #define SDHC_IRQSTATEN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12396 | #define SDHC_IRQSTATEN_CEBESEN_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 12397 | #define SDHC_IRQSTATEN_CEBESEN_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 12398 | #define SDHC_IRQSTATEN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12399 | #define SDHC_IRQSTATEN_CIESEN_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 12400 | #define SDHC_IRQSTATEN_CIESEN_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 12401 | #define SDHC_IRQSTATEN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12402 | #define SDHC_IRQSTATEN_DTOESEN_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 12403 | #define SDHC_IRQSTATEN_DTOESEN_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 12404 | #define SDHC_IRQSTATEN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12405 | #define SDHC_IRQSTATEN_DCESEN_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 12406 | #define SDHC_IRQSTATEN_DCESEN_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 12407 | #define SDHC_IRQSTATEN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12408 | #define SDHC_IRQSTATEN_DEBESEN_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 12409 | #define SDHC_IRQSTATEN_DEBESEN_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 12410 | #define SDHC_IRQSTATEN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12411 | #define SDHC_IRQSTATEN_AC12ESEN_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 12412 | #define SDHC_IRQSTATEN_AC12ESEN_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 12413 | #define SDHC_IRQSTATEN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12414 | #define SDHC_IRQSTATEN_DMAESEN_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 12415 | #define SDHC_IRQSTATEN_DMAESEN_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 12416 | #define SDHC_IRQSTATEN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12417 | |
AnnaBridge | 171:3a7713b1edbc | 12418 | /*! @name IRQSIGEN - Interrupt Signal Enable register */ |
AnnaBridge | 171:3a7713b1edbc | 12419 | #define SDHC_IRQSIGEN_CCIEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 12420 | #define SDHC_IRQSIGEN_CCIEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12421 | #define SDHC_IRQSIGEN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12422 | #define SDHC_IRQSIGEN_TCIEN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 12423 | #define SDHC_IRQSIGEN_TCIEN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 12424 | #define SDHC_IRQSIGEN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12425 | #define SDHC_IRQSIGEN_BGEIEN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 12426 | #define SDHC_IRQSIGEN_BGEIEN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 12427 | #define SDHC_IRQSIGEN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12428 | #define SDHC_IRQSIGEN_DINTIEN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 12429 | #define SDHC_IRQSIGEN_DINTIEN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 12430 | #define SDHC_IRQSIGEN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12431 | #define SDHC_IRQSIGEN_BWRIEN_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 12432 | #define SDHC_IRQSIGEN_BWRIEN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 12433 | #define SDHC_IRQSIGEN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12434 | #define SDHC_IRQSIGEN_BRRIEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 12435 | #define SDHC_IRQSIGEN_BRRIEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 12436 | #define SDHC_IRQSIGEN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12437 | #define SDHC_IRQSIGEN_CINSIEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 12438 | #define SDHC_IRQSIGEN_CINSIEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 12439 | #define SDHC_IRQSIGEN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12440 | #define SDHC_IRQSIGEN_CRMIEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 12441 | #define SDHC_IRQSIGEN_CRMIEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 12442 | #define SDHC_IRQSIGEN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12443 | #define SDHC_IRQSIGEN_CINTIEN_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 12444 | #define SDHC_IRQSIGEN_CINTIEN_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 12445 | #define SDHC_IRQSIGEN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12446 | #define SDHC_IRQSIGEN_CTOEIEN_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 12447 | #define SDHC_IRQSIGEN_CTOEIEN_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 12448 | #define SDHC_IRQSIGEN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12449 | #define SDHC_IRQSIGEN_CCEIEN_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 12450 | #define SDHC_IRQSIGEN_CCEIEN_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 12451 | #define SDHC_IRQSIGEN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12452 | #define SDHC_IRQSIGEN_CEBEIEN_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 12453 | #define SDHC_IRQSIGEN_CEBEIEN_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 12454 | #define SDHC_IRQSIGEN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12455 | #define SDHC_IRQSIGEN_CIEIEN_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 12456 | #define SDHC_IRQSIGEN_CIEIEN_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 12457 | #define SDHC_IRQSIGEN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12458 | #define SDHC_IRQSIGEN_DTOEIEN_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 12459 | #define SDHC_IRQSIGEN_DTOEIEN_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 12460 | #define SDHC_IRQSIGEN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12461 | #define SDHC_IRQSIGEN_DCEIEN_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 12462 | #define SDHC_IRQSIGEN_DCEIEN_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 12463 | #define SDHC_IRQSIGEN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12464 | #define SDHC_IRQSIGEN_DEBEIEN_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 12465 | #define SDHC_IRQSIGEN_DEBEIEN_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 12466 | #define SDHC_IRQSIGEN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12467 | #define SDHC_IRQSIGEN_AC12EIEN_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 12468 | #define SDHC_IRQSIGEN_AC12EIEN_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 12469 | #define SDHC_IRQSIGEN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12470 | #define SDHC_IRQSIGEN_DMAEIEN_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 12471 | #define SDHC_IRQSIGEN_DMAEIEN_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 12472 | #define SDHC_IRQSIGEN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12473 | |
AnnaBridge | 171:3a7713b1edbc | 12474 | /*! @name AC12ERR - Auto CMD12 Error Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 12475 | #define SDHC_AC12ERR_AC12NE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 12476 | #define SDHC_AC12ERR_AC12NE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12477 | #define SDHC_AC12ERR_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12478 | #define SDHC_AC12ERR_AC12TOE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 12479 | #define SDHC_AC12ERR_AC12TOE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 12480 | #define SDHC_AC12ERR_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12481 | #define SDHC_AC12ERR_AC12EBE_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 12482 | #define SDHC_AC12ERR_AC12EBE_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 12483 | #define SDHC_AC12ERR_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12484 | #define SDHC_AC12ERR_AC12CE_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 12485 | #define SDHC_AC12ERR_AC12CE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 12486 | #define SDHC_AC12ERR_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12487 | #define SDHC_AC12ERR_AC12IE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 12488 | #define SDHC_AC12ERR_AC12IE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 12489 | #define SDHC_AC12ERR_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12490 | #define SDHC_AC12ERR_CNIBAC12E_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 12491 | #define SDHC_AC12ERR_CNIBAC12E_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 12492 | #define SDHC_AC12ERR_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12493 | |
AnnaBridge | 171:3a7713b1edbc | 12494 | /*! @name HTCAPBLT - Host Controller Capabilities */ |
AnnaBridge | 171:3a7713b1edbc | 12495 | #define SDHC_HTCAPBLT_MBL_MASK (0x70000U) |
AnnaBridge | 171:3a7713b1edbc | 12496 | #define SDHC_HTCAPBLT_MBL_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 12497 | #define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12498 | #define SDHC_HTCAPBLT_ADMAS_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 12499 | #define SDHC_HTCAPBLT_ADMAS_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 12500 | #define SDHC_HTCAPBLT_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12501 | #define SDHC_HTCAPBLT_HSS_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 12502 | #define SDHC_HTCAPBLT_HSS_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 12503 | #define SDHC_HTCAPBLT_HSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12504 | #define SDHC_HTCAPBLT_DMAS_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 12505 | #define SDHC_HTCAPBLT_DMAS_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 12506 | #define SDHC_HTCAPBLT_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12507 | #define SDHC_HTCAPBLT_SRS_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 12508 | #define SDHC_HTCAPBLT_SRS_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 12509 | #define SDHC_HTCAPBLT_SRS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12510 | #define SDHC_HTCAPBLT_VS33_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 12511 | #define SDHC_HTCAPBLT_VS33_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 12512 | #define SDHC_HTCAPBLT_VS33(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12513 | |
AnnaBridge | 171:3a7713b1edbc | 12514 | /*! @name WML - Watermark Level Register */ |
AnnaBridge | 171:3a7713b1edbc | 12515 | #define SDHC_WML_RDWML_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 12516 | #define SDHC_WML_RDWML_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12517 | #define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12518 | #define SDHC_WML_WRWML_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 12519 | #define SDHC_WML_WRWML_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 12520 | #define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12521 | |
AnnaBridge | 171:3a7713b1edbc | 12522 | /*! @name FEVT - Force Event register */ |
AnnaBridge | 171:3a7713b1edbc | 12523 | #define SDHC_FEVT_AC12NE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 12524 | #define SDHC_FEVT_AC12NE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12525 | #define SDHC_FEVT_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12526 | #define SDHC_FEVT_AC12TOE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 12527 | #define SDHC_FEVT_AC12TOE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 12528 | #define SDHC_FEVT_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12529 | #define SDHC_FEVT_AC12CE_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 12530 | #define SDHC_FEVT_AC12CE_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 12531 | #define SDHC_FEVT_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12532 | #define SDHC_FEVT_AC12EBE_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 12533 | #define SDHC_FEVT_AC12EBE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 12534 | #define SDHC_FEVT_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12535 | #define SDHC_FEVT_AC12IE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 12536 | #define SDHC_FEVT_AC12IE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 12537 | #define SDHC_FEVT_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12538 | #define SDHC_FEVT_CNIBAC12E_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 12539 | #define SDHC_FEVT_CNIBAC12E_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 12540 | #define SDHC_FEVT_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12541 | #define SDHC_FEVT_CTOE_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 12542 | #define SDHC_FEVT_CTOE_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 12543 | #define SDHC_FEVT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12544 | #define SDHC_FEVT_CCE_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 12545 | #define SDHC_FEVT_CCE_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 12546 | #define SDHC_FEVT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12547 | #define SDHC_FEVT_CEBE_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 12548 | #define SDHC_FEVT_CEBE_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 12549 | #define SDHC_FEVT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12550 | #define SDHC_FEVT_CIE_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 12551 | #define SDHC_FEVT_CIE_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 12552 | #define SDHC_FEVT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12553 | #define SDHC_FEVT_DTOE_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 12554 | #define SDHC_FEVT_DTOE_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 12555 | #define SDHC_FEVT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12556 | #define SDHC_FEVT_DCE_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 12557 | #define SDHC_FEVT_DCE_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 12558 | #define SDHC_FEVT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12559 | #define SDHC_FEVT_DEBE_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 12560 | #define SDHC_FEVT_DEBE_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 12561 | #define SDHC_FEVT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12562 | #define SDHC_FEVT_AC12E_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 12563 | #define SDHC_FEVT_AC12E_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 12564 | #define SDHC_FEVT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12565 | #define SDHC_FEVT_DMAE_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 12566 | #define SDHC_FEVT_DMAE_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 12567 | #define SDHC_FEVT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12568 | #define SDHC_FEVT_CINT_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 12569 | #define SDHC_FEVT_CINT_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 12570 | #define SDHC_FEVT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12571 | |
AnnaBridge | 171:3a7713b1edbc | 12572 | /*! @name ADMAES - ADMA Error Status register */ |
AnnaBridge | 171:3a7713b1edbc | 12573 | #define SDHC_ADMAES_ADMAES_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 12574 | #define SDHC_ADMAES_ADMAES_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12575 | #define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12576 | #define SDHC_ADMAES_ADMALME_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 12577 | #define SDHC_ADMAES_ADMALME_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 12578 | #define SDHC_ADMAES_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12579 | #define SDHC_ADMAES_ADMADCE_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 12580 | #define SDHC_ADMAES_ADMADCE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 12581 | #define SDHC_ADMAES_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12582 | |
AnnaBridge | 171:3a7713b1edbc | 12583 | /*! @name ADSADDR - ADMA System Addressregister */ |
AnnaBridge | 171:3a7713b1edbc | 12584 | #define SDHC_ADSADDR_ADSADDR_MASK (0xFFFFFFFCU) |
AnnaBridge | 171:3a7713b1edbc | 12585 | #define SDHC_ADSADDR_ADSADDR_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 12586 | #define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12587 | |
AnnaBridge | 171:3a7713b1edbc | 12588 | /*! @name VENDOR - Vendor Specific register */ |
AnnaBridge | 171:3a7713b1edbc | 12589 | #define SDHC_VENDOR_EXBLKNU_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 12590 | #define SDHC_VENDOR_EXBLKNU_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 12591 | #define SDHC_VENDOR_EXBLKNU(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12592 | #define SDHC_VENDOR_INTSTVAL_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 12593 | #define SDHC_VENDOR_INTSTVAL_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 12594 | #define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12595 | |
AnnaBridge | 171:3a7713b1edbc | 12596 | /*! @name MMCBOOT - MMC Boot register */ |
AnnaBridge | 171:3a7713b1edbc | 12597 | #define SDHC_MMCBOOT_DTOCVACK_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 12598 | #define SDHC_MMCBOOT_DTOCVACK_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12599 | #define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12600 | #define SDHC_MMCBOOT_BOOTACK_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 12601 | #define SDHC_MMCBOOT_BOOTACK_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 12602 | #define SDHC_MMCBOOT_BOOTACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12603 | #define SDHC_MMCBOOT_BOOTMODE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 12604 | #define SDHC_MMCBOOT_BOOTMODE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 12605 | #define SDHC_MMCBOOT_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12606 | #define SDHC_MMCBOOT_BOOTEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 12607 | #define SDHC_MMCBOOT_BOOTEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 12608 | #define SDHC_MMCBOOT_BOOTEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12609 | #define SDHC_MMCBOOT_AUTOSABGEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 12610 | #define SDHC_MMCBOOT_AUTOSABGEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 12611 | #define SDHC_MMCBOOT_AUTOSABGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12612 | #define SDHC_MMCBOOT_BOOTBLKCNT_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 12613 | #define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 12614 | #define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12615 | |
AnnaBridge | 171:3a7713b1edbc | 12616 | /*! @name HOSTVER - Host Controller Version */ |
AnnaBridge | 171:3a7713b1edbc | 12617 | #define SDHC_HOSTVER_SVN_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 12618 | #define SDHC_HOSTVER_SVN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12619 | #define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12620 | #define SDHC_HOSTVER_VVN_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 12621 | #define SDHC_HOSTVER_VVN_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 12622 | #define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12623 | |
AnnaBridge | 171:3a7713b1edbc | 12624 | |
AnnaBridge | 171:3a7713b1edbc | 12625 | /*! |
AnnaBridge | 171:3a7713b1edbc | 12626 | * @} |
AnnaBridge | 171:3a7713b1edbc | 12627 | */ /* end of group SDHC_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 12628 | |
AnnaBridge | 171:3a7713b1edbc | 12629 | |
AnnaBridge | 171:3a7713b1edbc | 12630 | /* SDHC - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 12631 | /** Peripheral SDHC base address */ |
AnnaBridge | 171:3a7713b1edbc | 12632 | #define SDHC_BASE (0x400B1000u) |
AnnaBridge | 171:3a7713b1edbc | 12633 | /** Peripheral SDHC base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 12634 | #define SDHC ((SDHC_Type *)SDHC_BASE) |
AnnaBridge | 171:3a7713b1edbc | 12635 | /** Array initializer of SDHC peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 12636 | #define SDHC_BASE_ADDRS { SDHC_BASE } |
AnnaBridge | 171:3a7713b1edbc | 12637 | /** Array initializer of SDHC peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 12638 | #define SDHC_BASE_PTRS { SDHC } |
AnnaBridge | 171:3a7713b1edbc | 12639 | /** Interrupt vectors for the SDHC peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 12640 | #define SDHC_IRQS { SDHC_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 12641 | |
AnnaBridge | 171:3a7713b1edbc | 12642 | /*! |
AnnaBridge | 171:3a7713b1edbc | 12643 | * @} |
AnnaBridge | 171:3a7713b1edbc | 12644 | */ /* end of group SDHC_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 12645 | |
AnnaBridge | 171:3a7713b1edbc | 12646 | |
AnnaBridge | 171:3a7713b1edbc | 12647 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 12648 | -- SDRAM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 12649 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 12650 | |
AnnaBridge | 171:3a7713b1edbc | 12651 | /*! |
AnnaBridge | 171:3a7713b1edbc | 12652 | * @addtogroup SDRAM_Peripheral_Access_Layer SDRAM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 12653 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 12654 | */ |
AnnaBridge | 171:3a7713b1edbc | 12655 | |
AnnaBridge | 171:3a7713b1edbc | 12656 | /** SDRAM - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 12657 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 12658 | uint8_t RESERVED_0[66]; |
AnnaBridge | 171:3a7713b1edbc | 12659 | __IO uint16_t CTRL; /**< Control Register, offset: 0x42 */ |
AnnaBridge | 171:3a7713b1edbc | 12660 | uint8_t RESERVED_1[4]; |
AnnaBridge | 171:3a7713b1edbc | 12661 | struct { /* offset: 0x48, array step: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 12662 | __IO uint32_t AC; /**< Address and Control Register, array offset: 0x48, array step: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 12663 | __IO uint32_t CM; /**< Control Mask, array offset: 0x4C, array step: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 12664 | } BLOCK[2]; |
AnnaBridge | 171:3a7713b1edbc | 12665 | } SDRAM_Type; |
AnnaBridge | 171:3a7713b1edbc | 12666 | |
AnnaBridge | 171:3a7713b1edbc | 12667 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 12668 | -- SDRAM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 12669 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 12670 | |
AnnaBridge | 171:3a7713b1edbc | 12671 | /*! |
AnnaBridge | 171:3a7713b1edbc | 12672 | * @addtogroup SDRAM_Register_Masks SDRAM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 12673 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 12674 | */ |
AnnaBridge | 171:3a7713b1edbc | 12675 | |
AnnaBridge | 171:3a7713b1edbc | 12676 | /*! @name CTRL - Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 12677 | #define SDRAM_CTRL_RC_MASK (0x1FFU) |
AnnaBridge | 171:3a7713b1edbc | 12678 | #define SDRAM_CTRL_RC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12679 | #define SDRAM_CTRL_RC(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RC_SHIFT)) & SDRAM_CTRL_RC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12680 | #define SDRAM_CTRL_RTIM_MASK (0x600U) |
AnnaBridge | 171:3a7713b1edbc | 12681 | #define SDRAM_CTRL_RTIM_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 12682 | #define SDRAM_CTRL_RTIM(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RTIM_SHIFT)) & SDRAM_CTRL_RTIM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12683 | #define SDRAM_CTRL_IS_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 12684 | #define SDRAM_CTRL_IS_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 12685 | #define SDRAM_CTRL_IS(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_IS_SHIFT)) & SDRAM_CTRL_IS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12686 | |
AnnaBridge | 171:3a7713b1edbc | 12687 | /*! @name AC - Address and Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 12688 | #define SDRAM_AC_IP_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 12689 | #define SDRAM_AC_IP_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 12690 | #define SDRAM_AC_IP(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IP_SHIFT)) & SDRAM_AC_IP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12691 | #define SDRAM_AC_PS_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 12692 | #define SDRAM_AC_PS_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 12693 | #define SDRAM_AC_PS(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_PS_SHIFT)) & SDRAM_AC_PS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12694 | #define SDRAM_AC_IMRS_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 12695 | #define SDRAM_AC_IMRS_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 12696 | #define SDRAM_AC_IMRS(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IMRS_SHIFT)) & SDRAM_AC_IMRS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12697 | #define SDRAM_AC_CBM_MASK (0x700U) |
AnnaBridge | 171:3a7713b1edbc | 12698 | #define SDRAM_AC_CBM_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 12699 | #define SDRAM_AC_CBM(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CBM_SHIFT)) & SDRAM_AC_CBM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12700 | #define SDRAM_AC_CASL_MASK (0x3000U) |
AnnaBridge | 171:3a7713b1edbc | 12701 | #define SDRAM_AC_CASL_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 12702 | #define SDRAM_AC_CASL(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CASL_SHIFT)) & SDRAM_AC_CASL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12703 | #define SDRAM_AC_RE_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 12704 | #define SDRAM_AC_RE_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 12705 | #define SDRAM_AC_RE(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_RE_SHIFT)) & SDRAM_AC_RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12706 | #define SDRAM_AC_BA_MASK (0xFFFC0000U) |
AnnaBridge | 171:3a7713b1edbc | 12707 | #define SDRAM_AC_BA_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 12708 | #define SDRAM_AC_BA(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_BA_SHIFT)) & SDRAM_AC_BA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12709 | |
AnnaBridge | 171:3a7713b1edbc | 12710 | /* The count of SDRAM_AC */ |
AnnaBridge | 171:3a7713b1edbc | 12711 | #define SDRAM_AC_COUNT (2U) |
AnnaBridge | 171:3a7713b1edbc | 12712 | |
AnnaBridge | 171:3a7713b1edbc | 12713 | /*! @name CM - Control Mask */ |
AnnaBridge | 171:3a7713b1edbc | 12714 | #define SDRAM_CM_V_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 12715 | #define SDRAM_CM_V_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12716 | #define SDRAM_CM_V(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_V_SHIFT)) & SDRAM_CM_V_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12717 | #define SDRAM_CM_WP_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 12718 | #define SDRAM_CM_WP_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 12719 | #define SDRAM_CM_WP(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_WP_SHIFT)) & SDRAM_CM_WP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12720 | #define SDRAM_CM_BAM_MASK (0xFFFC0000U) |
AnnaBridge | 171:3a7713b1edbc | 12721 | #define SDRAM_CM_BAM_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 12722 | #define SDRAM_CM_BAM(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_BAM_SHIFT)) & SDRAM_CM_BAM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12723 | |
AnnaBridge | 171:3a7713b1edbc | 12724 | /* The count of SDRAM_CM */ |
AnnaBridge | 171:3a7713b1edbc | 12725 | #define SDRAM_CM_COUNT (2U) |
AnnaBridge | 171:3a7713b1edbc | 12726 | |
AnnaBridge | 171:3a7713b1edbc | 12727 | |
AnnaBridge | 171:3a7713b1edbc | 12728 | /*! |
AnnaBridge | 171:3a7713b1edbc | 12729 | * @} |
AnnaBridge | 171:3a7713b1edbc | 12730 | */ /* end of group SDRAM_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 12731 | |
AnnaBridge | 171:3a7713b1edbc | 12732 | |
AnnaBridge | 171:3a7713b1edbc | 12733 | /* SDRAM - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 12734 | /** Peripheral SDRAM base address */ |
AnnaBridge | 171:3a7713b1edbc | 12735 | #define SDRAM_BASE (0x4000F000u) |
AnnaBridge | 171:3a7713b1edbc | 12736 | /** Peripheral SDRAM base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 12737 | #define SDRAM ((SDRAM_Type *)SDRAM_BASE) |
AnnaBridge | 171:3a7713b1edbc | 12738 | /** Array initializer of SDRAM peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 12739 | #define SDRAM_BASE_ADDRS { SDRAM_BASE } |
AnnaBridge | 171:3a7713b1edbc | 12740 | /** Array initializer of SDRAM peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 12741 | #define SDRAM_BASE_PTRS { SDRAM } |
AnnaBridge | 171:3a7713b1edbc | 12742 | |
AnnaBridge | 171:3a7713b1edbc | 12743 | /*! |
AnnaBridge | 171:3a7713b1edbc | 12744 | * @} |
AnnaBridge | 171:3a7713b1edbc | 12745 | */ /* end of group SDRAM_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 12746 | |
AnnaBridge | 171:3a7713b1edbc | 12747 | |
AnnaBridge | 171:3a7713b1edbc | 12748 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 12749 | -- SIM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 12750 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 12751 | |
AnnaBridge | 171:3a7713b1edbc | 12752 | /*! |
AnnaBridge | 171:3a7713b1edbc | 12753 | * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 12754 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 12755 | */ |
AnnaBridge | 171:3a7713b1edbc | 12756 | |
AnnaBridge | 171:3a7713b1edbc | 12757 | /** SIM - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 12758 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 12759 | __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 12760 | __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 12761 | uint8_t RESERVED_0[4092]; |
AnnaBridge | 171:3a7713b1edbc | 12762 | __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ |
AnnaBridge | 171:3a7713b1edbc | 12763 | uint8_t RESERVED_1[4]; |
AnnaBridge | 171:3a7713b1edbc | 12764 | __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ |
AnnaBridge | 171:3a7713b1edbc | 12765 | __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ |
AnnaBridge | 171:3a7713b1edbc | 12766 | uint8_t RESERVED_2[4]; |
AnnaBridge | 171:3a7713b1edbc | 12767 | __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ |
AnnaBridge | 171:3a7713b1edbc | 12768 | __IO uint32_t SOPT8; /**< System Options Register 8, offset: 0x101C */ |
AnnaBridge | 171:3a7713b1edbc | 12769 | __IO uint32_t SOPT9; /**< System Options Register 9, offset: 0x1020 */ |
AnnaBridge | 171:3a7713b1edbc | 12770 | __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ |
AnnaBridge | 171:3a7713b1edbc | 12771 | __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */ |
AnnaBridge | 171:3a7713b1edbc | 12772 | __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */ |
AnnaBridge | 171:3a7713b1edbc | 12773 | __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */ |
AnnaBridge | 171:3a7713b1edbc | 12774 | __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ |
AnnaBridge | 171:3a7713b1edbc | 12775 | __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ |
AnnaBridge | 171:3a7713b1edbc | 12776 | __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ |
AnnaBridge | 171:3a7713b1edbc | 12777 | __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ |
AnnaBridge | 171:3a7713b1edbc | 12778 | __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ |
AnnaBridge | 171:3a7713b1edbc | 12779 | __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */ |
AnnaBridge | 171:3a7713b1edbc | 12780 | __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ |
AnnaBridge | 171:3a7713b1edbc | 12781 | __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ |
AnnaBridge | 171:3a7713b1edbc | 12782 | __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */ |
AnnaBridge | 171:3a7713b1edbc | 12783 | __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ |
AnnaBridge | 171:3a7713b1edbc | 12784 | __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ |
AnnaBridge | 171:3a7713b1edbc | 12785 | __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ |
AnnaBridge | 171:3a7713b1edbc | 12786 | __IO uint32_t CLKDIV3; /**< System Clock Divider Register 3, offset: 0x1064 */ |
AnnaBridge | 171:3a7713b1edbc | 12787 | __IO uint32_t CLKDIV4; /**< System Clock Divider Register 4, offset: 0x1068 */ |
AnnaBridge | 171:3a7713b1edbc | 12788 | } SIM_Type; |
AnnaBridge | 171:3a7713b1edbc | 12789 | |
AnnaBridge | 171:3a7713b1edbc | 12790 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 12791 | -- SIM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 12792 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 12793 | |
AnnaBridge | 171:3a7713b1edbc | 12794 | /*! |
AnnaBridge | 171:3a7713b1edbc | 12795 | * @addtogroup SIM_Register_Masks SIM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 12796 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 12797 | */ |
AnnaBridge | 171:3a7713b1edbc | 12798 | |
AnnaBridge | 171:3a7713b1edbc | 12799 | /*! @name SOPT1 - System Options Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 12800 | #define SIM_SOPT1_RAMSIZE_MASK (0xF000U) |
AnnaBridge | 171:3a7713b1edbc | 12801 | #define SIM_SOPT1_RAMSIZE_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 12802 | #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12803 | #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U) |
AnnaBridge | 171:3a7713b1edbc | 12804 | #define SIM_SOPT1_OSC32KSEL_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 12805 | #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12806 | #define SIM_SOPT1_USBVSTBY_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 12807 | #define SIM_SOPT1_USBVSTBY_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 12808 | #define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12809 | #define SIM_SOPT1_USBSSTBY_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 12810 | #define SIM_SOPT1_USBSSTBY_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 12811 | #define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12812 | #define SIM_SOPT1_USBREGEN_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 12813 | #define SIM_SOPT1_USBREGEN_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 12814 | #define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12815 | |
AnnaBridge | 171:3a7713b1edbc | 12816 | /*! @name SOPT1CFG - SOPT1 Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 12817 | #define SIM_SOPT1CFG_URWE_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 12818 | #define SIM_SOPT1CFG_URWE_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 12819 | #define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12820 | #define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 12821 | #define SIM_SOPT1CFG_UVSWE_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 12822 | #define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12823 | #define SIM_SOPT1CFG_USSWE_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 12824 | #define SIM_SOPT1CFG_USSWE_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 12825 | #define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12826 | |
AnnaBridge | 171:3a7713b1edbc | 12827 | /*! @name SOPT2 - System Options Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 12828 | #define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 12829 | #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 12830 | #define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12831 | #define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U) |
AnnaBridge | 171:3a7713b1edbc | 12832 | #define SIM_SOPT2_CLKOUTSEL_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 12833 | #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12834 | #define SIM_SOPT2_FBSL_MASK (0x300U) |
AnnaBridge | 171:3a7713b1edbc | 12835 | #define SIM_SOPT2_FBSL_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 12836 | #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12837 | #define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 12838 | #define SIM_SOPT2_TRACECLKSEL_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 12839 | #define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12840 | #define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 12841 | #define SIM_SOPT2_PLLFLLSEL_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 12842 | #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12843 | #define SIM_SOPT2_USBSRC_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 12844 | #define SIM_SOPT2_USBSRC_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 12845 | #define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12846 | #define SIM_SOPT2_FLEXIOSRC_MASK (0xC00000U) |
AnnaBridge | 171:3a7713b1edbc | 12847 | #define SIM_SOPT2_FLEXIOSRC_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 12848 | #define SIM_SOPT2_FLEXIOSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FLEXIOSRC_SHIFT)) & SIM_SOPT2_FLEXIOSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12849 | #define SIM_SOPT2_TPMSRC_MASK (0x3000000U) |
AnnaBridge | 171:3a7713b1edbc | 12850 | #define SIM_SOPT2_TPMSRC_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 12851 | #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12852 | #define SIM_SOPT2_LPUARTSRC_MASK (0xC000000U) |
AnnaBridge | 171:3a7713b1edbc | 12853 | #define SIM_SOPT2_LPUARTSRC_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 12854 | #define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12855 | #define SIM_SOPT2_SDHCSRC_MASK (0x30000000U) |
AnnaBridge | 171:3a7713b1edbc | 12856 | #define SIM_SOPT2_SDHCSRC_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 12857 | #define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12858 | #define SIM_SOPT2_EMVSIMSRC_MASK (0xC0000000U) |
AnnaBridge | 171:3a7713b1edbc | 12859 | #define SIM_SOPT2_EMVSIMSRC_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 12860 | #define SIM_SOPT2_EMVSIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_EMVSIMSRC_SHIFT)) & SIM_SOPT2_EMVSIMSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12861 | |
AnnaBridge | 171:3a7713b1edbc | 12862 | /*! @name SOPT4 - System Options Register 4 */ |
AnnaBridge | 171:3a7713b1edbc | 12863 | #define SIM_SOPT4_FTM0FLT0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 12864 | #define SIM_SOPT4_FTM0FLT0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12865 | #define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12866 | #define SIM_SOPT4_FTM0FLT1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 12867 | #define SIM_SOPT4_FTM0FLT1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 12868 | #define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12869 | #define SIM_SOPT4_FTM1FLT0_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 12870 | #define SIM_SOPT4_FTM1FLT0_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 12871 | #define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12872 | #define SIM_SOPT4_FTM2FLT0_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 12873 | #define SIM_SOPT4_FTM2FLT0_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 12874 | #define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12875 | #define SIM_SOPT4_FTM3FLT0_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 12876 | #define SIM_SOPT4_FTM3FLT0_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 12877 | #define SIM_SOPT4_FTM3FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12878 | #define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U) |
AnnaBridge | 171:3a7713b1edbc | 12879 | #define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 12880 | #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12881 | #define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U) |
AnnaBridge | 171:3a7713b1edbc | 12882 | #define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 12883 | #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12884 | #define SIM_SOPT4_FTM2CH1SRC_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 12885 | #define SIM_SOPT4_FTM2CH1SRC_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 12886 | #define SIM_SOPT4_FTM2CH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12887 | #define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 12888 | #define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 12889 | #define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12890 | #define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 12891 | #define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 12892 | #define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12893 | #define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 12894 | #define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 12895 | #define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12896 | #define SIM_SOPT4_FTM3CLKSEL_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 12897 | #define SIM_SOPT4_FTM3CLKSEL_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 12898 | #define SIM_SOPT4_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12899 | #define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 12900 | #define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 12901 | #define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12902 | #define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 12903 | #define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 12904 | #define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12905 | #define SIM_SOPT4_FTM3TRG0SRC_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 12906 | #define SIM_SOPT4_FTM3TRG0SRC_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 12907 | #define SIM_SOPT4_FTM3TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12908 | #define SIM_SOPT4_FTM3TRG1SRC_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 12909 | #define SIM_SOPT4_FTM3TRG1SRC_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 12910 | #define SIM_SOPT4_FTM3TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12911 | |
AnnaBridge | 171:3a7713b1edbc | 12912 | /*! @name SOPT5 - System Options Register 5 */ |
AnnaBridge | 171:3a7713b1edbc | 12913 | #define SIM_SOPT5_LPUART0TXSRC_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 12914 | #define SIM_SOPT5_LPUART0TXSRC_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 12915 | #define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12916 | #define SIM_SOPT5_LPUART0RXSRC_MASK (0xC0000U) |
AnnaBridge | 171:3a7713b1edbc | 12917 | #define SIM_SOPT5_LPUART0RXSRC_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 12918 | #define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12919 | #define SIM_SOPT5_LPUART1TXSRC_MASK (0x300000U) |
AnnaBridge | 171:3a7713b1edbc | 12920 | #define SIM_SOPT5_LPUART1TXSRC_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 12921 | #define SIM_SOPT5_LPUART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1TXSRC_SHIFT)) & SIM_SOPT5_LPUART1TXSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12922 | #define SIM_SOPT5_LPUART1RXSRC_MASK (0xC00000U) |
AnnaBridge | 171:3a7713b1edbc | 12923 | #define SIM_SOPT5_LPUART1RXSRC_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 12924 | #define SIM_SOPT5_LPUART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1RXSRC_SHIFT)) & SIM_SOPT5_LPUART1RXSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12925 | |
AnnaBridge | 171:3a7713b1edbc | 12926 | /*! @name SOPT7 - System Options Register 7 */ |
AnnaBridge | 171:3a7713b1edbc | 12927 | #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 12928 | #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12929 | #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12930 | #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 12931 | #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 12932 | #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12933 | #define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 12934 | #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 12935 | #define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12936 | |
AnnaBridge | 171:3a7713b1edbc | 12937 | /*! @name SOPT8 - System Options Register 8 */ |
AnnaBridge | 171:3a7713b1edbc | 12938 | #define SIM_SOPT8_FTM0SYNCBIT_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 12939 | #define SIM_SOPT8_FTM0SYNCBIT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 12940 | #define SIM_SOPT8_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12941 | #define SIM_SOPT8_FTM1SYNCBIT_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 12942 | #define SIM_SOPT8_FTM1SYNCBIT_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 12943 | #define SIM_SOPT8_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12944 | #define SIM_SOPT8_FTM2SYNCBIT_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 12945 | #define SIM_SOPT8_FTM2SYNCBIT_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 12946 | #define SIM_SOPT8_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12947 | #define SIM_SOPT8_FTM3SYNCBIT_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 12948 | #define SIM_SOPT8_FTM3SYNCBIT_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 12949 | #define SIM_SOPT8_FTM3SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3SYNCBIT_SHIFT)) & SIM_SOPT8_FTM3SYNCBIT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12950 | #define SIM_SOPT8_FTM0OCH0SRC_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 12951 | #define SIM_SOPT8_FTM0OCH0SRC_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 12952 | #define SIM_SOPT8_FTM0OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12953 | #define SIM_SOPT8_FTM0OCH1SRC_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 12954 | #define SIM_SOPT8_FTM0OCH1SRC_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 12955 | #define SIM_SOPT8_FTM0OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12956 | #define SIM_SOPT8_FTM0OCH2SRC_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 12957 | #define SIM_SOPT8_FTM0OCH2SRC_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 12958 | #define SIM_SOPT8_FTM0OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12959 | #define SIM_SOPT8_FTM0OCH3SRC_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 12960 | #define SIM_SOPT8_FTM0OCH3SRC_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 12961 | #define SIM_SOPT8_FTM0OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12962 | #define SIM_SOPT8_FTM0OCH4SRC_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 12963 | #define SIM_SOPT8_FTM0OCH4SRC_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 12964 | #define SIM_SOPT8_FTM0OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12965 | #define SIM_SOPT8_FTM0OCH5SRC_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 12966 | #define SIM_SOPT8_FTM0OCH5SRC_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 12967 | #define SIM_SOPT8_FTM0OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12968 | #define SIM_SOPT8_FTM0OCH6SRC_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 12969 | #define SIM_SOPT8_FTM0OCH6SRC_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 12970 | #define SIM_SOPT8_FTM0OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12971 | #define SIM_SOPT8_FTM0OCH7SRC_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 12972 | #define SIM_SOPT8_FTM0OCH7SRC_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 12973 | #define SIM_SOPT8_FTM0OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12974 | #define SIM_SOPT8_FTM3OCH0SRC_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 12975 | #define SIM_SOPT8_FTM3OCH0SRC_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 12976 | #define SIM_SOPT8_FTM3OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH0SRC_SHIFT)) & SIM_SOPT8_FTM3OCH0SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12977 | #define SIM_SOPT8_FTM3OCH1SRC_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 12978 | #define SIM_SOPT8_FTM3OCH1SRC_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 12979 | #define SIM_SOPT8_FTM3OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH1SRC_SHIFT)) & SIM_SOPT8_FTM3OCH1SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12980 | #define SIM_SOPT8_FTM3OCH2SRC_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 12981 | #define SIM_SOPT8_FTM3OCH2SRC_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 12982 | #define SIM_SOPT8_FTM3OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH2SRC_SHIFT)) & SIM_SOPT8_FTM3OCH2SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12983 | #define SIM_SOPT8_FTM3OCH3SRC_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 12984 | #define SIM_SOPT8_FTM3OCH3SRC_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 12985 | #define SIM_SOPT8_FTM3OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH3SRC_SHIFT)) & SIM_SOPT8_FTM3OCH3SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12986 | #define SIM_SOPT8_FTM3OCH4SRC_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 12987 | #define SIM_SOPT8_FTM3OCH4SRC_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 12988 | #define SIM_SOPT8_FTM3OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH4SRC_SHIFT)) & SIM_SOPT8_FTM3OCH4SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12989 | #define SIM_SOPT8_FTM3OCH5SRC_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 12990 | #define SIM_SOPT8_FTM3OCH5SRC_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 12991 | #define SIM_SOPT8_FTM3OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH5SRC_SHIFT)) & SIM_SOPT8_FTM3OCH5SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12992 | #define SIM_SOPT8_FTM3OCH6SRC_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 12993 | #define SIM_SOPT8_FTM3OCH6SRC_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 12994 | #define SIM_SOPT8_FTM3OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH6SRC_SHIFT)) & SIM_SOPT8_FTM3OCH6SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12995 | #define SIM_SOPT8_FTM3OCH7SRC_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 12996 | #define SIM_SOPT8_FTM3OCH7SRC_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 12997 | #define SIM_SOPT8_FTM3OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH7SRC_SHIFT)) & SIM_SOPT8_FTM3OCH7SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 12998 | |
AnnaBridge | 171:3a7713b1edbc | 12999 | /*! @name SOPT9 - System Options Register 9 */ |
AnnaBridge | 171:3a7713b1edbc | 13000 | #define SIM_SOPT9_TPM1CH0SRC_MASK (0xC0000U) |
AnnaBridge | 171:3a7713b1edbc | 13001 | #define SIM_SOPT9_TPM1CH0SRC_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 13002 | #define SIM_SOPT9_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CH0SRC_SHIFT)) & SIM_SOPT9_TPM1CH0SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13003 | #define SIM_SOPT9_TPM2CH0SRC_MASK (0x300000U) |
AnnaBridge | 171:3a7713b1edbc | 13004 | #define SIM_SOPT9_TPM2CH0SRC_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 13005 | #define SIM_SOPT9_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CH0SRC_SHIFT)) & SIM_SOPT9_TPM2CH0SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13006 | #define SIM_SOPT9_TPM1CLKSEL_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 13007 | #define SIM_SOPT9_TPM1CLKSEL_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 13008 | #define SIM_SOPT9_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CLKSEL_SHIFT)) & SIM_SOPT9_TPM1CLKSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13009 | #define SIM_SOPT9_TPM2CLKSEL_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 13010 | #define SIM_SOPT9_TPM2CLKSEL_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 13011 | #define SIM_SOPT9_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CLKSEL_SHIFT)) & SIM_SOPT9_TPM2CLKSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13012 | |
AnnaBridge | 171:3a7713b1edbc | 13013 | /*! @name SDID - System Device Identification Register */ |
AnnaBridge | 171:3a7713b1edbc | 13014 | #define SIM_SDID_PINID_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 13015 | #define SIM_SDID_PINID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13016 | #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13017 | #define SIM_SDID_FAMID_MASK (0x70U) |
AnnaBridge | 171:3a7713b1edbc | 13018 | #define SIM_SDID_FAMID_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 13019 | #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13020 | #define SIM_SDID_DIEID_MASK (0xF80U) |
AnnaBridge | 171:3a7713b1edbc | 13021 | #define SIM_SDID_DIEID_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 13022 | #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13023 | #define SIM_SDID_REVID_MASK (0xF000U) |
AnnaBridge | 171:3a7713b1edbc | 13024 | #define SIM_SDID_REVID_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 13025 | #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13026 | #define SIM_SDID_SERIESID_MASK (0xF00000U) |
AnnaBridge | 171:3a7713b1edbc | 13027 | #define SIM_SDID_SERIESID_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 13028 | #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13029 | #define SIM_SDID_SUBFAMID_MASK (0xF000000U) |
AnnaBridge | 171:3a7713b1edbc | 13030 | #define SIM_SDID_SUBFAMID_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 13031 | #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13032 | #define SIM_SDID_FAMILYID_MASK (0xF0000000U) |
AnnaBridge | 171:3a7713b1edbc | 13033 | #define SIM_SDID_FAMILYID_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 13034 | #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13035 | |
AnnaBridge | 171:3a7713b1edbc | 13036 | /*! @name SCGC1 - System Clock Gating Control Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 13037 | #define SIM_SCGC1_I2C2_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 13038 | #define SIM_SCGC1_I2C2_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 13039 | #define SIM_SCGC1_I2C2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13040 | #define SIM_SCGC1_I2C3_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 13041 | #define SIM_SCGC1_I2C3_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 13042 | #define SIM_SCGC1_I2C3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C3_SHIFT)) & SIM_SCGC1_I2C3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13043 | |
AnnaBridge | 171:3a7713b1edbc | 13044 | /*! @name SCGC2 - System Clock Gating Control Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 13045 | #define SIM_SCGC2_LPUART0_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 13046 | #define SIM_SCGC2_LPUART0_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 13047 | #define SIM_SCGC2_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART0_SHIFT)) & SIM_SCGC2_LPUART0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13048 | #define SIM_SCGC2_LPUART1_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 13049 | #define SIM_SCGC2_LPUART1_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 13050 | #define SIM_SCGC2_LPUART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART1_SHIFT)) & SIM_SCGC2_LPUART1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13051 | #define SIM_SCGC2_LPUART2_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 13052 | #define SIM_SCGC2_LPUART2_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 13053 | #define SIM_SCGC2_LPUART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART2_SHIFT)) & SIM_SCGC2_LPUART2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13054 | #define SIM_SCGC2_LPUART3_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 13055 | #define SIM_SCGC2_LPUART3_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 13056 | #define SIM_SCGC2_LPUART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART3_SHIFT)) & SIM_SCGC2_LPUART3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13057 | #define SIM_SCGC2_TPM1_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 13058 | #define SIM_SCGC2_TPM1_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 13059 | #define SIM_SCGC2_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM1_SHIFT)) & SIM_SCGC2_TPM1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13060 | #define SIM_SCGC2_TPM2_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 13061 | #define SIM_SCGC2_TPM2_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 13062 | #define SIM_SCGC2_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM2_SHIFT)) & SIM_SCGC2_TPM2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13063 | #define SIM_SCGC2_DAC0_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 13064 | #define SIM_SCGC2_DAC0_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 13065 | #define SIM_SCGC2_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13066 | #define SIM_SCGC2_LTC_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 13067 | #define SIM_SCGC2_LTC_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 13068 | #define SIM_SCGC2_LTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LTC_SHIFT)) & SIM_SCGC2_LTC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13069 | #define SIM_SCGC2_EMVSIM0_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 13070 | #define SIM_SCGC2_EMVSIM0_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 13071 | #define SIM_SCGC2_EMVSIM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_EMVSIM0_SHIFT)) & SIM_SCGC2_EMVSIM0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13072 | #define SIM_SCGC2_EMVSIM1_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 13073 | #define SIM_SCGC2_EMVSIM1_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 13074 | #define SIM_SCGC2_EMVSIM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_EMVSIM1_SHIFT)) & SIM_SCGC2_EMVSIM1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13075 | #define SIM_SCGC2_LPUART4_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 13076 | #define SIM_SCGC2_LPUART4_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 13077 | #define SIM_SCGC2_LPUART4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART4_SHIFT)) & SIM_SCGC2_LPUART4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13078 | #define SIM_SCGC2_QSPI_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 13079 | #define SIM_SCGC2_QSPI_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 13080 | #define SIM_SCGC2_QSPI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_QSPI_SHIFT)) & SIM_SCGC2_QSPI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13081 | #define SIM_SCGC2_FLEXIO_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 13082 | #define SIM_SCGC2_FLEXIO_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 13083 | #define SIM_SCGC2_FLEXIO(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_FLEXIO_SHIFT)) & SIM_SCGC2_FLEXIO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13084 | |
AnnaBridge | 171:3a7713b1edbc | 13085 | /*! @name SCGC3 - System Clock Gating Control Register 3 */ |
AnnaBridge | 171:3a7713b1edbc | 13086 | #define SIM_SCGC3_TRNG_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 13087 | #define SIM_SCGC3_TRNG_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13088 | #define SIM_SCGC3_TRNG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_TRNG_SHIFT)) & SIM_SCGC3_TRNG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13089 | #define SIM_SCGC3_SPI2_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 13090 | #define SIM_SCGC3_SPI2_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 13091 | #define SIM_SCGC3_SPI2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13092 | #define SIM_SCGC3_SDHC_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 13093 | #define SIM_SCGC3_SDHC_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 13094 | #define SIM_SCGC3_SDHC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13095 | #define SIM_SCGC3_FTM2_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 13096 | #define SIM_SCGC3_FTM2_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 13097 | #define SIM_SCGC3_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13098 | #define SIM_SCGC3_FTM3_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 13099 | #define SIM_SCGC3_FTM3_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 13100 | #define SIM_SCGC3_FTM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13101 | |
AnnaBridge | 171:3a7713b1edbc | 13102 | /*! @name SCGC4 - System Clock Gating Control Register 4 */ |
AnnaBridge | 171:3a7713b1edbc | 13103 | #define SIM_SCGC4_EWM_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 13104 | #define SIM_SCGC4_EWM_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 13105 | #define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13106 | #define SIM_SCGC4_CMT_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 13107 | #define SIM_SCGC4_CMT_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 13108 | #define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13109 | #define SIM_SCGC4_I2C0_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 13110 | #define SIM_SCGC4_I2C0_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 13111 | #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13112 | #define SIM_SCGC4_I2C1_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 13113 | #define SIM_SCGC4_I2C1_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 13114 | #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13115 | #define SIM_SCGC4_USBOTG_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 13116 | #define SIM_SCGC4_USBOTG_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 13117 | #define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13118 | #define SIM_SCGC4_CMP_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 13119 | #define SIM_SCGC4_CMP_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 13120 | #define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13121 | #define SIM_SCGC4_VREF_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 13122 | #define SIM_SCGC4_VREF_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 13123 | #define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13124 | |
AnnaBridge | 171:3a7713b1edbc | 13125 | /*! @name SCGC5 - System Clock Gating Control Register 5 */ |
AnnaBridge | 171:3a7713b1edbc | 13126 | #define SIM_SCGC5_LPTMR_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 13127 | #define SIM_SCGC5_LPTMR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13128 | #define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13129 | #define SIM_SCGC5_LPTMR1_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 13130 | #define SIM_SCGC5_LPTMR1_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 13131 | #define SIM_SCGC5_LPTMR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR1_SHIFT)) & SIM_SCGC5_LPTMR1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13132 | #define SIM_SCGC5_TSI_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 13133 | #define SIM_SCGC5_TSI_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 13134 | #define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13135 | #define SIM_SCGC5_PORTA_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 13136 | #define SIM_SCGC5_PORTA_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 13137 | #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13138 | #define SIM_SCGC5_PORTB_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 13139 | #define SIM_SCGC5_PORTB_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 13140 | #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13141 | #define SIM_SCGC5_PORTC_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 13142 | #define SIM_SCGC5_PORTC_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 13143 | #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13144 | #define SIM_SCGC5_PORTD_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 13145 | #define SIM_SCGC5_PORTD_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 13146 | #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13147 | #define SIM_SCGC5_PORTE_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 13148 | #define SIM_SCGC5_PORTE_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 13149 | #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13150 | |
AnnaBridge | 171:3a7713b1edbc | 13151 | /*! @name SCGC6 - System Clock Gating Control Register 6 */ |
AnnaBridge | 171:3a7713b1edbc | 13152 | #define SIM_SCGC6_FTF_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 13153 | #define SIM_SCGC6_FTF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13154 | #define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13155 | #define SIM_SCGC6_DMAMUX_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 13156 | #define SIM_SCGC6_DMAMUX_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 13157 | #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13158 | #define SIM_SCGC6_SPI0_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 13159 | #define SIM_SCGC6_SPI0_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 13160 | #define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13161 | #define SIM_SCGC6_SPI1_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 13162 | #define SIM_SCGC6_SPI1_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 13163 | #define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13164 | #define SIM_SCGC6_I2S_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 13165 | #define SIM_SCGC6_I2S_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 13166 | #define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13167 | #define SIM_SCGC6_CRC_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 13168 | #define SIM_SCGC6_CRC_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 13169 | #define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13170 | #define SIM_SCGC6_USBDCD_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 13171 | #define SIM_SCGC6_USBDCD_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 13172 | #define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13173 | #define SIM_SCGC6_PDB_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 13174 | #define SIM_SCGC6_PDB_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 13175 | #define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13176 | #define SIM_SCGC6_PIT_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 13177 | #define SIM_SCGC6_PIT_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 13178 | #define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13179 | #define SIM_SCGC6_FTM0_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 13180 | #define SIM_SCGC6_FTM0_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 13181 | #define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13182 | #define SIM_SCGC6_FTM1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 13183 | #define SIM_SCGC6_FTM1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 13184 | #define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13185 | #define SIM_SCGC6_FTM2_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 13186 | #define SIM_SCGC6_FTM2_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 13187 | #define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13188 | #define SIM_SCGC6_ADC0_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 13189 | #define SIM_SCGC6_ADC0_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 13190 | #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13191 | #define SIM_SCGC6_RTC_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 13192 | #define SIM_SCGC6_RTC_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 13193 | #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13194 | #define SIM_SCGC6_DAC0_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 13195 | #define SIM_SCGC6_DAC0_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 13196 | #define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13197 | |
AnnaBridge | 171:3a7713b1edbc | 13198 | /*! @name SCGC7 - System Clock Gating Control Register 7 */ |
AnnaBridge | 171:3a7713b1edbc | 13199 | #define SIM_SCGC7_FLEXBUS_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 13200 | #define SIM_SCGC7_FLEXBUS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13201 | #define SIM_SCGC7_FLEXBUS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13202 | #define SIM_SCGC7_DMA_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 13203 | #define SIM_SCGC7_DMA_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 13204 | #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13205 | #define SIM_SCGC7_MPU_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 13206 | #define SIM_SCGC7_MPU_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 13207 | #define SIM_SCGC7_MPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13208 | #define SIM_SCGC7_SDRAMC_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 13209 | #define SIM_SCGC7_SDRAMC_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 13210 | #define SIM_SCGC7_SDRAMC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_SDRAMC_SHIFT)) & SIM_SCGC7_SDRAMC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13211 | |
AnnaBridge | 171:3a7713b1edbc | 13212 | /*! @name CLKDIV1 - System Clock Divider Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 13213 | #define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 13214 | #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 13215 | #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13216 | #define SIM_CLKDIV1_OUTDIV3_MASK (0xF00000U) |
AnnaBridge | 171:3a7713b1edbc | 13217 | #define SIM_CLKDIV1_OUTDIV3_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 13218 | #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13219 | #define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U) |
AnnaBridge | 171:3a7713b1edbc | 13220 | #define SIM_CLKDIV1_OUTDIV2_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 13221 | #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13222 | #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U) |
AnnaBridge | 171:3a7713b1edbc | 13223 | #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 13224 | #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13225 | |
AnnaBridge | 171:3a7713b1edbc | 13226 | /*! @name CLKDIV2 - System Clock Divider Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 13227 | #define SIM_CLKDIV2_USBFRAC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 13228 | #define SIM_CLKDIV2_USBFRAC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13229 | #define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13230 | #define SIM_CLKDIV2_USBDIV_MASK (0xEU) |
AnnaBridge | 171:3a7713b1edbc | 13231 | #define SIM_CLKDIV2_USBDIV_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 13232 | #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13233 | |
AnnaBridge | 171:3a7713b1edbc | 13234 | /*! @name FCFG1 - Flash Configuration Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 13235 | #define SIM_FCFG1_FLASHDIS_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 13236 | #define SIM_FCFG1_FLASHDIS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13237 | #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13238 | #define SIM_FCFG1_FLASHDOZE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 13239 | #define SIM_FCFG1_FLASHDOZE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 13240 | #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13241 | #define SIM_FCFG1_PFSIZE_MASK (0xF000000U) |
AnnaBridge | 171:3a7713b1edbc | 13242 | #define SIM_FCFG1_PFSIZE_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 13243 | #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13244 | |
AnnaBridge | 171:3a7713b1edbc | 13245 | /*! @name FCFG2 - Flash Configuration Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 13246 | #define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U) |
AnnaBridge | 171:3a7713b1edbc | 13247 | #define SIM_FCFG2_MAXADDR1_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 13248 | #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13249 | #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U) |
AnnaBridge | 171:3a7713b1edbc | 13250 | #define SIM_FCFG2_MAXADDR0_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 13251 | #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13252 | |
AnnaBridge | 171:3a7713b1edbc | 13253 | /*! @name UIDH - Unique Identification Register High */ |
AnnaBridge | 171:3a7713b1edbc | 13254 | #define SIM_UIDH_UID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 13255 | #define SIM_UIDH_UID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13256 | #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13257 | |
AnnaBridge | 171:3a7713b1edbc | 13258 | /*! @name UIDMH - Unique Identification Register Mid-High */ |
AnnaBridge | 171:3a7713b1edbc | 13259 | #define SIM_UIDMH_UID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 13260 | #define SIM_UIDMH_UID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13261 | #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13262 | |
AnnaBridge | 171:3a7713b1edbc | 13263 | /*! @name UIDML - Unique Identification Register Mid Low */ |
AnnaBridge | 171:3a7713b1edbc | 13264 | #define SIM_UIDML_UID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 13265 | #define SIM_UIDML_UID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13266 | #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13267 | |
AnnaBridge | 171:3a7713b1edbc | 13268 | /*! @name UIDL - Unique Identification Register Low */ |
AnnaBridge | 171:3a7713b1edbc | 13269 | #define SIM_UIDL_UID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 13270 | #define SIM_UIDL_UID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13271 | #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13272 | |
AnnaBridge | 171:3a7713b1edbc | 13273 | /*! @name CLKDIV3 - System Clock Divider Register 3 */ |
AnnaBridge | 171:3a7713b1edbc | 13274 | #define SIM_CLKDIV3_PLLFLLFRAC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 13275 | #define SIM_CLKDIV3_PLLFLLFRAC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13276 | #define SIM_CLKDIV3_PLLFLLFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLFRAC_SHIFT)) & SIM_CLKDIV3_PLLFLLFRAC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13277 | #define SIM_CLKDIV3_PLLFLLDIV_MASK (0xEU) |
AnnaBridge | 171:3a7713b1edbc | 13278 | #define SIM_CLKDIV3_PLLFLLDIV_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 13279 | #define SIM_CLKDIV3_PLLFLLDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLDIV_SHIFT)) & SIM_CLKDIV3_PLLFLLDIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13280 | |
AnnaBridge | 171:3a7713b1edbc | 13281 | /*! @name CLKDIV4 - System Clock Divider Register 4 */ |
AnnaBridge | 171:3a7713b1edbc | 13282 | #define SIM_CLKDIV4_TRACEFRAC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 13283 | #define SIM_CLKDIV4_TRACEFRAC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13284 | #define SIM_CLKDIV4_TRACEFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEFRAC_SHIFT)) & SIM_CLKDIV4_TRACEFRAC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13285 | #define SIM_CLKDIV4_TRACEDIV_MASK (0xEU) |
AnnaBridge | 171:3a7713b1edbc | 13286 | #define SIM_CLKDIV4_TRACEDIV_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 13287 | #define SIM_CLKDIV4_TRACEDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEDIV_SHIFT)) & SIM_CLKDIV4_TRACEDIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13288 | |
AnnaBridge | 171:3a7713b1edbc | 13289 | |
AnnaBridge | 171:3a7713b1edbc | 13290 | /*! |
AnnaBridge | 171:3a7713b1edbc | 13291 | * @} |
AnnaBridge | 171:3a7713b1edbc | 13292 | */ /* end of group SIM_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 13293 | |
AnnaBridge | 171:3a7713b1edbc | 13294 | |
AnnaBridge | 171:3a7713b1edbc | 13295 | /* SIM - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 13296 | /** Peripheral SIM base address */ |
AnnaBridge | 171:3a7713b1edbc | 13297 | #define SIM_BASE (0x40047000u) |
AnnaBridge | 171:3a7713b1edbc | 13298 | /** Peripheral SIM base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 13299 | #define SIM ((SIM_Type *)SIM_BASE) |
AnnaBridge | 171:3a7713b1edbc | 13300 | /** Array initializer of SIM peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 13301 | #define SIM_BASE_ADDRS { SIM_BASE } |
AnnaBridge | 171:3a7713b1edbc | 13302 | /** Array initializer of SIM peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 13303 | #define SIM_BASE_PTRS { SIM } |
AnnaBridge | 171:3a7713b1edbc | 13304 | |
AnnaBridge | 171:3a7713b1edbc | 13305 | /*! |
AnnaBridge | 171:3a7713b1edbc | 13306 | * @} |
AnnaBridge | 171:3a7713b1edbc | 13307 | */ /* end of group SIM_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 13308 | |
AnnaBridge | 171:3a7713b1edbc | 13309 | |
AnnaBridge | 171:3a7713b1edbc | 13310 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 13311 | -- SMC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 13312 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 13313 | |
AnnaBridge | 171:3a7713b1edbc | 13314 | /*! |
AnnaBridge | 171:3a7713b1edbc | 13315 | * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 13316 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 13317 | */ |
AnnaBridge | 171:3a7713b1edbc | 13318 | |
AnnaBridge | 171:3a7713b1edbc | 13319 | /** SMC - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 13320 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 13321 | __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 13322 | __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 13323 | __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 13324 | __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */ |
AnnaBridge | 171:3a7713b1edbc | 13325 | } SMC_Type; |
AnnaBridge | 171:3a7713b1edbc | 13326 | |
AnnaBridge | 171:3a7713b1edbc | 13327 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 13328 | -- SMC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 13329 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 13330 | |
AnnaBridge | 171:3a7713b1edbc | 13331 | /*! |
AnnaBridge | 171:3a7713b1edbc | 13332 | * @addtogroup SMC_Register_Masks SMC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 13333 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 13334 | */ |
AnnaBridge | 171:3a7713b1edbc | 13335 | |
AnnaBridge | 171:3a7713b1edbc | 13336 | /*! @name PMPROT - Power Mode Protection register */ |
AnnaBridge | 171:3a7713b1edbc | 13337 | #define SMC_PMPROT_AVLLS_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 13338 | #define SMC_PMPROT_AVLLS_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 13339 | #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13340 | #define SMC_PMPROT_ALLS_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 13341 | #define SMC_PMPROT_ALLS_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 13342 | #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13343 | #define SMC_PMPROT_AVLP_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 13344 | #define SMC_PMPROT_AVLP_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 13345 | #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13346 | #define SMC_PMPROT_AHSRUN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 13347 | #define SMC_PMPROT_AHSRUN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 13348 | #define SMC_PMPROT_AHSRUN(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13349 | |
AnnaBridge | 171:3a7713b1edbc | 13350 | /*! @name PMCTRL - Power Mode Control register */ |
AnnaBridge | 171:3a7713b1edbc | 13351 | #define SMC_PMCTRL_STOPM_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 13352 | #define SMC_PMCTRL_STOPM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13353 | #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13354 | #define SMC_PMCTRL_STOPA_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 13355 | #define SMC_PMCTRL_STOPA_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 13356 | #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13357 | #define SMC_PMCTRL_RUNM_MASK (0x60U) |
AnnaBridge | 171:3a7713b1edbc | 13358 | #define SMC_PMCTRL_RUNM_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 13359 | #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13360 | |
AnnaBridge | 171:3a7713b1edbc | 13361 | /*! @name STOPCTRL - Stop Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 13362 | #define SMC_STOPCTRL_LLSM_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 13363 | #define SMC_STOPCTRL_LLSM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13364 | #define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13365 | #define SMC_STOPCTRL_LPOPO_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 13366 | #define SMC_STOPCTRL_LPOPO_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 13367 | #define SMC_STOPCTRL_LPOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LPOPO_SHIFT)) & SMC_STOPCTRL_LPOPO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13368 | #define SMC_STOPCTRL_RAM2PO_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 13369 | #define SMC_STOPCTRL_RAM2PO_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 13370 | #define SMC_STOPCTRL_RAM2PO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_RAM2PO_SHIFT)) & SMC_STOPCTRL_RAM2PO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13371 | #define SMC_STOPCTRL_PORPO_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 13372 | #define SMC_STOPCTRL_PORPO_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 13373 | #define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13374 | #define SMC_STOPCTRL_PSTOPO_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 13375 | #define SMC_STOPCTRL_PSTOPO_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 13376 | #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13377 | |
AnnaBridge | 171:3a7713b1edbc | 13378 | /*! @name PMSTAT - Power Mode Status register */ |
AnnaBridge | 171:3a7713b1edbc | 13379 | #define SMC_PMSTAT_PMSTAT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 13380 | #define SMC_PMSTAT_PMSTAT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13381 | #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13382 | |
AnnaBridge | 171:3a7713b1edbc | 13383 | |
AnnaBridge | 171:3a7713b1edbc | 13384 | /*! |
AnnaBridge | 171:3a7713b1edbc | 13385 | * @} |
AnnaBridge | 171:3a7713b1edbc | 13386 | */ /* end of group SMC_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 13387 | |
AnnaBridge | 171:3a7713b1edbc | 13388 | |
AnnaBridge | 171:3a7713b1edbc | 13389 | /* SMC - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 13390 | /** Peripheral SMC base address */ |
AnnaBridge | 171:3a7713b1edbc | 13391 | #define SMC_BASE (0x4007E000u) |
AnnaBridge | 171:3a7713b1edbc | 13392 | /** Peripheral SMC base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 13393 | #define SMC ((SMC_Type *)SMC_BASE) |
AnnaBridge | 171:3a7713b1edbc | 13394 | /** Array initializer of SMC peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 13395 | #define SMC_BASE_ADDRS { SMC_BASE } |
AnnaBridge | 171:3a7713b1edbc | 13396 | /** Array initializer of SMC peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 13397 | #define SMC_BASE_PTRS { SMC } |
AnnaBridge | 171:3a7713b1edbc | 13398 | |
AnnaBridge | 171:3a7713b1edbc | 13399 | /*! |
AnnaBridge | 171:3a7713b1edbc | 13400 | * @} |
AnnaBridge | 171:3a7713b1edbc | 13401 | */ /* end of group SMC_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 13402 | |
AnnaBridge | 171:3a7713b1edbc | 13403 | |
AnnaBridge | 171:3a7713b1edbc | 13404 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 13405 | -- SPI Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 13406 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 13407 | |
AnnaBridge | 171:3a7713b1edbc | 13408 | /*! |
AnnaBridge | 171:3a7713b1edbc | 13409 | * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 13410 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 13411 | */ |
AnnaBridge | 171:3a7713b1edbc | 13412 | |
AnnaBridge | 171:3a7713b1edbc | 13413 | /** SPI - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 13414 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 13415 | __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 13416 | uint8_t RESERVED_0[4]; |
AnnaBridge | 171:3a7713b1edbc | 13417 | __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 13418 | union { /* offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 13419 | __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 13420 | __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 13421 | }; |
AnnaBridge | 171:3a7713b1edbc | 13422 | uint8_t RESERVED_1[24]; |
AnnaBridge | 171:3a7713b1edbc | 13423 | __IO uint32_t SR; /**< Status Register, offset: 0x2C */ |
AnnaBridge | 171:3a7713b1edbc | 13424 | __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ |
AnnaBridge | 171:3a7713b1edbc | 13425 | union { /* offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 13426 | __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 13427 | __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 13428 | }; |
AnnaBridge | 171:3a7713b1edbc | 13429 | __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */ |
AnnaBridge | 171:3a7713b1edbc | 13430 | __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */ |
AnnaBridge | 171:3a7713b1edbc | 13431 | __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */ |
AnnaBridge | 171:3a7713b1edbc | 13432 | __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */ |
AnnaBridge | 171:3a7713b1edbc | 13433 | __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */ |
AnnaBridge | 171:3a7713b1edbc | 13434 | uint8_t RESERVED_2[48]; |
AnnaBridge | 171:3a7713b1edbc | 13435 | __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */ |
AnnaBridge | 171:3a7713b1edbc | 13436 | __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */ |
AnnaBridge | 171:3a7713b1edbc | 13437 | __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */ |
AnnaBridge | 171:3a7713b1edbc | 13438 | __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ |
AnnaBridge | 171:3a7713b1edbc | 13439 | } SPI_Type; |
AnnaBridge | 171:3a7713b1edbc | 13440 | |
AnnaBridge | 171:3a7713b1edbc | 13441 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 13442 | -- SPI Register Masks |
AnnaBridge | 171:3a7713b1edbc | 13443 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 13444 | |
AnnaBridge | 171:3a7713b1edbc | 13445 | /*! |
AnnaBridge | 171:3a7713b1edbc | 13446 | * @addtogroup SPI_Register_Masks SPI Register Masks |
AnnaBridge | 171:3a7713b1edbc | 13447 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 13448 | */ |
AnnaBridge | 171:3a7713b1edbc | 13449 | |
AnnaBridge | 171:3a7713b1edbc | 13450 | /*! @name MCR - Module Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 13451 | #define SPI_MCR_HALT_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 13452 | #define SPI_MCR_HALT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13453 | #define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13454 | #define SPI_MCR_SMPL_PT_MASK (0x300U) |
AnnaBridge | 171:3a7713b1edbc | 13455 | #define SPI_MCR_SMPL_PT_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 13456 | #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13457 | #define SPI_MCR_CLR_RXF_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 13458 | #define SPI_MCR_CLR_RXF_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 13459 | #define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13460 | #define SPI_MCR_CLR_TXF_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 13461 | #define SPI_MCR_CLR_TXF_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 13462 | #define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13463 | #define SPI_MCR_DIS_RXF_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 13464 | #define SPI_MCR_DIS_RXF_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 13465 | #define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13466 | #define SPI_MCR_DIS_TXF_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 13467 | #define SPI_MCR_DIS_TXF_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 13468 | #define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13469 | #define SPI_MCR_MDIS_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 13470 | #define SPI_MCR_MDIS_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 13471 | #define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13472 | #define SPI_MCR_DOZE_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 13473 | #define SPI_MCR_DOZE_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 13474 | #define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13475 | #define SPI_MCR_PCSIS_MASK (0x3F0000U) |
AnnaBridge | 171:3a7713b1edbc | 13476 | #define SPI_MCR_PCSIS_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 13477 | #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13478 | #define SPI_MCR_ROOE_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 13479 | #define SPI_MCR_ROOE_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 13480 | #define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13481 | #define SPI_MCR_PCSSE_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 13482 | #define SPI_MCR_PCSSE_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 13483 | #define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13484 | #define SPI_MCR_MTFE_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 13485 | #define SPI_MCR_MTFE_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 13486 | #define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13487 | #define SPI_MCR_FRZ_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 13488 | #define SPI_MCR_FRZ_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 13489 | #define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13490 | #define SPI_MCR_DCONF_MASK (0x30000000U) |
AnnaBridge | 171:3a7713b1edbc | 13491 | #define SPI_MCR_DCONF_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 13492 | #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13493 | #define SPI_MCR_CONT_SCKE_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 13494 | #define SPI_MCR_CONT_SCKE_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 13495 | #define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13496 | #define SPI_MCR_MSTR_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 13497 | #define SPI_MCR_MSTR_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 13498 | #define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13499 | |
AnnaBridge | 171:3a7713b1edbc | 13500 | /*! @name TCR - Transfer Count Register */ |
AnnaBridge | 171:3a7713b1edbc | 13501 | #define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 13502 | #define SPI_TCR_SPI_TCNT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 13503 | #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13504 | |
AnnaBridge | 171:3a7713b1edbc | 13505 | /*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */ |
AnnaBridge | 171:3a7713b1edbc | 13506 | #define SPI_CTAR_BR_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 13507 | #define SPI_CTAR_BR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13508 | #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13509 | #define SPI_CTAR_DT_MASK (0xF0U) |
AnnaBridge | 171:3a7713b1edbc | 13510 | #define SPI_CTAR_DT_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 13511 | #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13512 | #define SPI_CTAR_ASC_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 13513 | #define SPI_CTAR_ASC_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 13514 | #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13515 | #define SPI_CTAR_CSSCK_MASK (0xF000U) |
AnnaBridge | 171:3a7713b1edbc | 13516 | #define SPI_CTAR_CSSCK_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 13517 | #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13518 | #define SPI_CTAR_PBR_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 13519 | #define SPI_CTAR_PBR_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 13520 | #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13521 | #define SPI_CTAR_PDT_MASK (0xC0000U) |
AnnaBridge | 171:3a7713b1edbc | 13522 | #define SPI_CTAR_PDT_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 13523 | #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13524 | #define SPI_CTAR_PASC_MASK (0x300000U) |
AnnaBridge | 171:3a7713b1edbc | 13525 | #define SPI_CTAR_PASC_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 13526 | #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13527 | #define SPI_CTAR_PCSSCK_MASK (0xC00000U) |
AnnaBridge | 171:3a7713b1edbc | 13528 | #define SPI_CTAR_PCSSCK_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 13529 | #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13530 | #define SPI_CTAR_LSBFE_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 13531 | #define SPI_CTAR_LSBFE_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 13532 | #define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13533 | #define SPI_CTAR_CPHA_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 13534 | #define SPI_CTAR_CPHA_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 13535 | #define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13536 | #define SPI_CTAR_CPOL_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 13537 | #define SPI_CTAR_CPOL_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 13538 | #define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13539 | #define SPI_CTAR_FMSZ_MASK (0x78000000U) |
AnnaBridge | 171:3a7713b1edbc | 13540 | #define SPI_CTAR_FMSZ_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 13541 | #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13542 | #define SPI_CTAR_DBR_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 13543 | #define SPI_CTAR_DBR_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 13544 | #define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13545 | |
AnnaBridge | 171:3a7713b1edbc | 13546 | /* The count of SPI_CTAR */ |
AnnaBridge | 171:3a7713b1edbc | 13547 | #define SPI_CTAR_COUNT (2U) |
AnnaBridge | 171:3a7713b1edbc | 13548 | |
AnnaBridge | 171:3a7713b1edbc | 13549 | /*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */ |
AnnaBridge | 171:3a7713b1edbc | 13550 | #define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 13551 | #define SPI_CTAR_SLAVE_CPHA_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 13552 | #define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13553 | #define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 13554 | #define SPI_CTAR_SLAVE_CPOL_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 13555 | #define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13556 | #define SPI_CTAR_SLAVE_FMSZ_MASK (0x78000000U) |
AnnaBridge | 171:3a7713b1edbc | 13557 | #define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 13558 | #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13559 | |
AnnaBridge | 171:3a7713b1edbc | 13560 | /* The count of SPI_CTAR_SLAVE */ |
AnnaBridge | 171:3a7713b1edbc | 13561 | #define SPI_CTAR_SLAVE_COUNT (1U) |
AnnaBridge | 171:3a7713b1edbc | 13562 | |
AnnaBridge | 171:3a7713b1edbc | 13563 | /*! @name SR - Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 13564 | #define SPI_SR_POPNXTPTR_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 13565 | #define SPI_SR_POPNXTPTR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13566 | #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13567 | #define SPI_SR_RXCTR_MASK (0xF0U) |
AnnaBridge | 171:3a7713b1edbc | 13568 | #define SPI_SR_RXCTR_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 13569 | #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13570 | #define SPI_SR_TXNXTPTR_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 13571 | #define SPI_SR_TXNXTPTR_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 13572 | #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13573 | #define SPI_SR_TXCTR_MASK (0xF000U) |
AnnaBridge | 171:3a7713b1edbc | 13574 | #define SPI_SR_TXCTR_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 13575 | #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13576 | #define SPI_SR_RFDF_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 13577 | #define SPI_SR_RFDF_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 13578 | #define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13579 | #define SPI_SR_RFOF_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 13580 | #define SPI_SR_RFOF_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 13581 | #define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13582 | #define SPI_SR_TFFF_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 13583 | #define SPI_SR_TFFF_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 13584 | #define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13585 | #define SPI_SR_TFUF_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 13586 | #define SPI_SR_TFUF_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 13587 | #define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13588 | #define SPI_SR_EOQF_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 13589 | #define SPI_SR_EOQF_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 13590 | #define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13591 | #define SPI_SR_TXRXS_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 13592 | #define SPI_SR_TXRXS_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 13593 | #define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13594 | #define SPI_SR_TCF_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 13595 | #define SPI_SR_TCF_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 13596 | #define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13597 | |
AnnaBridge | 171:3a7713b1edbc | 13598 | /*! @name RSER - DMA/Interrupt Request Select and Enable Register */ |
AnnaBridge | 171:3a7713b1edbc | 13599 | #define SPI_RSER_RFDF_DIRS_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 13600 | #define SPI_RSER_RFDF_DIRS_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 13601 | #define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13602 | #define SPI_RSER_RFDF_RE_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 13603 | #define SPI_RSER_RFDF_RE_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 13604 | #define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13605 | #define SPI_RSER_RFOF_RE_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 13606 | #define SPI_RSER_RFOF_RE_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 13607 | #define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13608 | #define SPI_RSER_TFFF_DIRS_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 13609 | #define SPI_RSER_TFFF_DIRS_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 13610 | #define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13611 | #define SPI_RSER_TFFF_RE_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 13612 | #define SPI_RSER_TFFF_RE_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 13613 | #define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13614 | #define SPI_RSER_TFUF_RE_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 13615 | #define SPI_RSER_TFUF_RE_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 13616 | #define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13617 | #define SPI_RSER_EOQF_RE_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 13618 | #define SPI_RSER_EOQF_RE_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 13619 | #define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13620 | #define SPI_RSER_TCF_RE_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 13621 | #define SPI_RSER_TCF_RE_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 13622 | #define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13623 | |
AnnaBridge | 171:3a7713b1edbc | 13624 | /*! @name PUSHR - PUSH TX FIFO Register In Master Mode */ |
AnnaBridge | 171:3a7713b1edbc | 13625 | #define SPI_PUSHR_TXDATA_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 13626 | #define SPI_PUSHR_TXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13627 | #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13628 | #define SPI_PUSHR_PCS_MASK (0x3F0000U) |
AnnaBridge | 171:3a7713b1edbc | 13629 | #define SPI_PUSHR_PCS_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 13630 | #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13631 | #define SPI_PUSHR_CTCNT_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 13632 | #define SPI_PUSHR_CTCNT_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 13633 | #define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13634 | #define SPI_PUSHR_EOQ_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 13635 | #define SPI_PUSHR_EOQ_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 13636 | #define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13637 | #define SPI_PUSHR_CTAS_MASK (0x70000000U) |
AnnaBridge | 171:3a7713b1edbc | 13638 | #define SPI_PUSHR_CTAS_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 13639 | #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13640 | #define SPI_PUSHR_CONT_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 13641 | #define SPI_PUSHR_CONT_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 13642 | #define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13643 | |
AnnaBridge | 171:3a7713b1edbc | 13644 | /*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */ |
AnnaBridge | 171:3a7713b1edbc | 13645 | #define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 13646 | #define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13647 | #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13648 | |
AnnaBridge | 171:3a7713b1edbc | 13649 | /*! @name POPR - POP RX FIFO Register */ |
AnnaBridge | 171:3a7713b1edbc | 13650 | #define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 13651 | #define SPI_POPR_RXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13652 | #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13653 | |
AnnaBridge | 171:3a7713b1edbc | 13654 | /*! @name TXFR0 - Transmit FIFO Registers */ |
AnnaBridge | 171:3a7713b1edbc | 13655 | #define SPI_TXFR0_TXDATA_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 13656 | #define SPI_TXFR0_TXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13657 | #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13658 | #define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 13659 | #define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 13660 | #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13661 | |
AnnaBridge | 171:3a7713b1edbc | 13662 | /*! @name TXFR1 - Transmit FIFO Registers */ |
AnnaBridge | 171:3a7713b1edbc | 13663 | #define SPI_TXFR1_TXDATA_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 13664 | #define SPI_TXFR1_TXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13665 | #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13666 | #define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 13667 | #define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 13668 | #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13669 | |
AnnaBridge | 171:3a7713b1edbc | 13670 | /*! @name TXFR2 - Transmit FIFO Registers */ |
AnnaBridge | 171:3a7713b1edbc | 13671 | #define SPI_TXFR2_TXDATA_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 13672 | #define SPI_TXFR2_TXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13673 | #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13674 | #define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 13675 | #define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 13676 | #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13677 | |
AnnaBridge | 171:3a7713b1edbc | 13678 | /*! @name TXFR3 - Transmit FIFO Registers */ |
AnnaBridge | 171:3a7713b1edbc | 13679 | #define SPI_TXFR3_TXDATA_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 13680 | #define SPI_TXFR3_TXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13681 | #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13682 | #define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 13683 | #define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 13684 | #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13685 | |
AnnaBridge | 171:3a7713b1edbc | 13686 | /*! @name RXFR0 - Receive FIFO Registers */ |
AnnaBridge | 171:3a7713b1edbc | 13687 | #define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 13688 | #define SPI_RXFR0_RXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13689 | #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13690 | |
AnnaBridge | 171:3a7713b1edbc | 13691 | /*! @name RXFR1 - Receive FIFO Registers */ |
AnnaBridge | 171:3a7713b1edbc | 13692 | #define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 13693 | #define SPI_RXFR1_RXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13694 | #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13695 | |
AnnaBridge | 171:3a7713b1edbc | 13696 | /*! @name RXFR2 - Receive FIFO Registers */ |
AnnaBridge | 171:3a7713b1edbc | 13697 | #define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 13698 | #define SPI_RXFR2_RXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13699 | #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13700 | |
AnnaBridge | 171:3a7713b1edbc | 13701 | /*! @name RXFR3 - Receive FIFO Registers */ |
AnnaBridge | 171:3a7713b1edbc | 13702 | #define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 13703 | #define SPI_RXFR3_RXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13704 | #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13705 | |
AnnaBridge | 171:3a7713b1edbc | 13706 | |
AnnaBridge | 171:3a7713b1edbc | 13707 | /*! |
AnnaBridge | 171:3a7713b1edbc | 13708 | * @} |
AnnaBridge | 171:3a7713b1edbc | 13709 | */ /* end of group SPI_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 13710 | |
AnnaBridge | 171:3a7713b1edbc | 13711 | |
AnnaBridge | 171:3a7713b1edbc | 13712 | /* SPI - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 13713 | /** Peripheral SPI0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 13714 | #define SPI0_BASE (0x4002C000u) |
AnnaBridge | 171:3a7713b1edbc | 13715 | /** Peripheral SPI0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 13716 | #define SPI0 ((SPI_Type *)SPI0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 13717 | /** Peripheral SPI1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 13718 | #define SPI1_BASE (0x4002D000u) |
AnnaBridge | 171:3a7713b1edbc | 13719 | /** Peripheral SPI1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 13720 | #define SPI1 ((SPI_Type *)SPI1_BASE) |
AnnaBridge | 171:3a7713b1edbc | 13721 | /** Peripheral SPI2 base address */ |
AnnaBridge | 171:3a7713b1edbc | 13722 | #define SPI2_BASE (0x400AC000u) |
AnnaBridge | 171:3a7713b1edbc | 13723 | /** Peripheral SPI2 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 13724 | #define SPI2 ((SPI_Type *)SPI2_BASE) |
AnnaBridge | 171:3a7713b1edbc | 13725 | /** Array initializer of SPI peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 13726 | #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE } |
AnnaBridge | 171:3a7713b1edbc | 13727 | /** Array initializer of SPI peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 13728 | #define SPI_BASE_PTRS { SPI0, SPI1, SPI2 } |
AnnaBridge | 171:3a7713b1edbc | 13729 | /** Interrupt vectors for the SPI peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 13730 | #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 13731 | |
AnnaBridge | 171:3a7713b1edbc | 13732 | /*! |
AnnaBridge | 171:3a7713b1edbc | 13733 | * @} |
AnnaBridge | 171:3a7713b1edbc | 13734 | */ /* end of group SPI_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 13735 | |
AnnaBridge | 171:3a7713b1edbc | 13736 | |
AnnaBridge | 171:3a7713b1edbc | 13737 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 13738 | -- TPM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 13739 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 13740 | |
AnnaBridge | 171:3a7713b1edbc | 13741 | /*! |
AnnaBridge | 171:3a7713b1edbc | 13742 | * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 13743 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 13744 | */ |
AnnaBridge | 171:3a7713b1edbc | 13745 | |
AnnaBridge | 171:3a7713b1edbc | 13746 | /** TPM - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 13747 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 13748 | __IO uint32_t SC; /**< Status and Control, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 13749 | __IO uint32_t CNT; /**< Counter, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 13750 | __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 13751 | struct { /* offset: 0xC, array step: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 13752 | __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 13753 | __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 13754 | } CONTROLS[2]; |
AnnaBridge | 171:3a7713b1edbc | 13755 | uint8_t RESERVED_0[52]; |
AnnaBridge | 171:3a7713b1edbc | 13756 | __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */ |
AnnaBridge | 171:3a7713b1edbc | 13757 | uint8_t RESERVED_1[16]; |
AnnaBridge | 171:3a7713b1edbc | 13758 | __IO uint32_t COMBINE; /**< Combine Channel Register, offset: 0x64 */ |
AnnaBridge | 171:3a7713b1edbc | 13759 | uint8_t RESERVED_2[8]; |
AnnaBridge | 171:3a7713b1edbc | 13760 | __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */ |
AnnaBridge | 171:3a7713b1edbc | 13761 | uint8_t RESERVED_3[4]; |
AnnaBridge | 171:3a7713b1edbc | 13762 | __IO uint32_t FILTER; /**< Filter Control, offset: 0x78 */ |
AnnaBridge | 171:3a7713b1edbc | 13763 | uint8_t RESERVED_4[4]; |
AnnaBridge | 171:3a7713b1edbc | 13764 | __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */ |
AnnaBridge | 171:3a7713b1edbc | 13765 | __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ |
AnnaBridge | 171:3a7713b1edbc | 13766 | } TPM_Type; |
AnnaBridge | 171:3a7713b1edbc | 13767 | |
AnnaBridge | 171:3a7713b1edbc | 13768 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 13769 | -- TPM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 13770 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 13771 | |
AnnaBridge | 171:3a7713b1edbc | 13772 | /*! |
AnnaBridge | 171:3a7713b1edbc | 13773 | * @addtogroup TPM_Register_Masks TPM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 13774 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 13775 | */ |
AnnaBridge | 171:3a7713b1edbc | 13776 | |
AnnaBridge | 171:3a7713b1edbc | 13777 | /*! @name SC - Status and Control */ |
AnnaBridge | 171:3a7713b1edbc | 13778 | #define TPM_SC_PS_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 13779 | #define TPM_SC_PS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13780 | #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13781 | #define TPM_SC_CMOD_MASK (0x18U) |
AnnaBridge | 171:3a7713b1edbc | 13782 | #define TPM_SC_CMOD_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 13783 | #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13784 | #define TPM_SC_CPWMS_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 13785 | #define TPM_SC_CPWMS_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 13786 | #define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13787 | #define TPM_SC_TOIE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 13788 | #define TPM_SC_TOIE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 13789 | #define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13790 | #define TPM_SC_TOF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 13791 | #define TPM_SC_TOF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 13792 | #define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13793 | #define TPM_SC_DMA_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 13794 | #define TPM_SC_DMA_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 13795 | #define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13796 | |
AnnaBridge | 171:3a7713b1edbc | 13797 | /*! @name CNT - Counter */ |
AnnaBridge | 171:3a7713b1edbc | 13798 | #define TPM_CNT_COUNT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 13799 | #define TPM_CNT_COUNT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13800 | #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13801 | |
AnnaBridge | 171:3a7713b1edbc | 13802 | /*! @name MOD - Modulo */ |
AnnaBridge | 171:3a7713b1edbc | 13803 | #define TPM_MOD_MOD_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 13804 | #define TPM_MOD_MOD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13805 | #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13806 | |
AnnaBridge | 171:3a7713b1edbc | 13807 | /*! @name CnSC - Channel (n) Status and Control */ |
AnnaBridge | 171:3a7713b1edbc | 13808 | #define TPM_CnSC_DMA_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 13809 | #define TPM_CnSC_DMA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13810 | #define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13811 | #define TPM_CnSC_ELSA_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 13812 | #define TPM_CnSC_ELSA_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 13813 | #define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13814 | #define TPM_CnSC_ELSB_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 13815 | #define TPM_CnSC_ELSB_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 13816 | #define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13817 | #define TPM_CnSC_MSA_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 13818 | #define TPM_CnSC_MSA_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 13819 | #define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13820 | #define TPM_CnSC_MSB_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 13821 | #define TPM_CnSC_MSB_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 13822 | #define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13823 | #define TPM_CnSC_CHIE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 13824 | #define TPM_CnSC_CHIE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 13825 | #define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13826 | #define TPM_CnSC_CHF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 13827 | #define TPM_CnSC_CHF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 13828 | #define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13829 | |
AnnaBridge | 171:3a7713b1edbc | 13830 | /* The count of TPM_CnSC */ |
AnnaBridge | 171:3a7713b1edbc | 13831 | #define TPM_CnSC_COUNT (2U) |
AnnaBridge | 171:3a7713b1edbc | 13832 | |
AnnaBridge | 171:3a7713b1edbc | 13833 | /*! @name CnV - Channel (n) Value */ |
AnnaBridge | 171:3a7713b1edbc | 13834 | #define TPM_CnV_VAL_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 13835 | #define TPM_CnV_VAL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13836 | #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13837 | |
AnnaBridge | 171:3a7713b1edbc | 13838 | /* The count of TPM_CnV */ |
AnnaBridge | 171:3a7713b1edbc | 13839 | #define TPM_CnV_COUNT (2U) |
AnnaBridge | 171:3a7713b1edbc | 13840 | |
AnnaBridge | 171:3a7713b1edbc | 13841 | /*! @name STATUS - Capture and Compare Status */ |
AnnaBridge | 171:3a7713b1edbc | 13842 | #define TPM_STATUS_CH0F_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 13843 | #define TPM_STATUS_CH0F_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13844 | #define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13845 | #define TPM_STATUS_CH1F_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 13846 | #define TPM_STATUS_CH1F_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 13847 | #define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13848 | #define TPM_STATUS_TOF_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 13849 | #define TPM_STATUS_TOF_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 13850 | #define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13851 | |
AnnaBridge | 171:3a7713b1edbc | 13852 | /*! @name COMBINE - Combine Channel Register */ |
AnnaBridge | 171:3a7713b1edbc | 13853 | #define TPM_COMBINE_COMBINE0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 13854 | #define TPM_COMBINE_COMBINE0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13855 | #define TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13856 | #define TPM_COMBINE_COMSWAP0_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 13857 | #define TPM_COMBINE_COMSWAP0_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 13858 | #define TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13859 | |
AnnaBridge | 171:3a7713b1edbc | 13860 | /*! @name POL - Channel Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 13861 | #define TPM_POL_POL0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 13862 | #define TPM_POL_POL0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13863 | #define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13864 | #define TPM_POL_POL1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 13865 | #define TPM_POL_POL1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 13866 | #define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13867 | |
AnnaBridge | 171:3a7713b1edbc | 13868 | /*! @name FILTER - Filter Control */ |
AnnaBridge | 171:3a7713b1edbc | 13869 | #define TPM_FILTER_CH0FVAL_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 13870 | #define TPM_FILTER_CH0FVAL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13871 | #define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13872 | #define TPM_FILTER_CH1FVAL_MASK (0xF0U) |
AnnaBridge | 171:3a7713b1edbc | 13873 | #define TPM_FILTER_CH1FVAL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 13874 | #define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13875 | |
AnnaBridge | 171:3a7713b1edbc | 13876 | /*! @name QDCTRL - Quadrature Decoder Control and Status */ |
AnnaBridge | 171:3a7713b1edbc | 13877 | #define TPM_QDCTRL_QUADEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 13878 | #define TPM_QDCTRL_QUADEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 13879 | #define TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13880 | #define TPM_QDCTRL_TOFDIR_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 13881 | #define TPM_QDCTRL_TOFDIR_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 13882 | #define TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13883 | #define TPM_QDCTRL_QUADIR_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 13884 | #define TPM_QDCTRL_QUADIR_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 13885 | #define TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13886 | #define TPM_QDCTRL_QUADMODE_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 13887 | #define TPM_QDCTRL_QUADMODE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 13888 | #define TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13889 | |
AnnaBridge | 171:3a7713b1edbc | 13890 | /*! @name CONF - Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 13891 | #define TPM_CONF_DOZEEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 13892 | #define TPM_CONF_DOZEEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 13893 | #define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13894 | #define TPM_CONF_DBGMODE_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 13895 | #define TPM_CONF_DBGMODE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 13896 | #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13897 | #define TPM_CONF_GTBSYNC_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 13898 | #define TPM_CONF_GTBSYNC_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 13899 | #define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13900 | #define TPM_CONF_GTBEEN_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 13901 | #define TPM_CONF_GTBEEN_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 13902 | #define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13903 | #define TPM_CONF_CSOT_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 13904 | #define TPM_CONF_CSOT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 13905 | #define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13906 | #define TPM_CONF_CSOO_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 13907 | #define TPM_CONF_CSOO_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 13908 | #define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13909 | #define TPM_CONF_CROT_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 13910 | #define TPM_CONF_CROT_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 13911 | #define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13912 | #define TPM_CONF_CPOT_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 13913 | #define TPM_CONF_CPOT_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 13914 | #define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13915 | #define TPM_CONF_TRGPOL_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 13916 | #define TPM_CONF_TRGPOL_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 13917 | #define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13918 | #define TPM_CONF_TRGSRC_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 13919 | #define TPM_CONF_TRGSRC_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 13920 | #define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13921 | #define TPM_CONF_TRGSEL_MASK (0xF000000U) |
AnnaBridge | 171:3a7713b1edbc | 13922 | #define TPM_CONF_TRGSEL_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 13923 | #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 13924 | |
AnnaBridge | 171:3a7713b1edbc | 13925 | |
AnnaBridge | 171:3a7713b1edbc | 13926 | /*! |
AnnaBridge | 171:3a7713b1edbc | 13927 | * @} |
AnnaBridge | 171:3a7713b1edbc | 13928 | */ /* end of group TPM_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 13929 | |
AnnaBridge | 171:3a7713b1edbc | 13930 | |
AnnaBridge | 171:3a7713b1edbc | 13931 | /* TPM - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 13932 | /** Peripheral TPM1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 13933 | #define TPM1_BASE (0x400C9000u) |
AnnaBridge | 171:3a7713b1edbc | 13934 | /** Peripheral TPM1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 13935 | #define TPM1 ((TPM_Type *)TPM1_BASE) |
AnnaBridge | 171:3a7713b1edbc | 13936 | /** Peripheral TPM2 base address */ |
AnnaBridge | 171:3a7713b1edbc | 13937 | #define TPM2_BASE (0x400CA000u) |
AnnaBridge | 171:3a7713b1edbc | 13938 | /** Peripheral TPM2 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 13939 | #define TPM2 ((TPM_Type *)TPM2_BASE) |
AnnaBridge | 171:3a7713b1edbc | 13940 | /** Array initializer of TPM peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 13941 | #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE } |
AnnaBridge | 171:3a7713b1edbc | 13942 | /** Array initializer of TPM peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 13943 | #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2 } |
AnnaBridge | 171:3a7713b1edbc | 13944 | /** Interrupt vectors for the TPM peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 13945 | #define TPM_IRQS { NotAvail_IRQn, TPM1_IRQn, TPM2_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 13946 | |
AnnaBridge | 171:3a7713b1edbc | 13947 | /*! |
AnnaBridge | 171:3a7713b1edbc | 13948 | * @} |
AnnaBridge | 171:3a7713b1edbc | 13949 | */ /* end of group TPM_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 13950 | |
AnnaBridge | 171:3a7713b1edbc | 13951 | |
AnnaBridge | 171:3a7713b1edbc | 13952 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 13953 | -- TRNG Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 13954 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 13955 | |
AnnaBridge | 171:3a7713b1edbc | 13956 | /*! |
AnnaBridge | 171:3a7713b1edbc | 13957 | * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 13958 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 13959 | */ |
AnnaBridge | 171:3a7713b1edbc | 13960 | |
AnnaBridge | 171:3a7713b1edbc | 13961 | /** TRNG - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 13962 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 13963 | __IO uint32_t MCTL; /**< RNG Miscellaneous Control Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 13964 | __IO uint32_t SCMISC; /**< RNG Statistical Check Miscellaneous Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 13965 | __IO uint32_t PKRRNG; /**< RNG Poker Range Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 13966 | union { /* offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 13967 | __IO uint32_t PKRMAX; /**< RNG Poker Maximum Limit Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 13968 | __I uint32_t PKRSQ; /**< RNG Poker Square Calculation Result Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 13969 | }; |
AnnaBridge | 171:3a7713b1edbc | 13970 | __IO uint32_t SDCTL; /**< RNG Seed Control Register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 13971 | union { /* offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 13972 | __IO uint32_t SBLIM; /**< RNG Sparse Bit Limit Register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 13973 | __I uint32_t TOTSAM; /**< RNG Total Samples Register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 13974 | }; |
AnnaBridge | 171:3a7713b1edbc | 13975 | __IO uint32_t FRQMIN; /**< RNG Frequency Count Minimum Limit Register, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 13976 | union { /* offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 13977 | __I uint32_t FRQCNT; /**< RNG Frequency Count Register, offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 13978 | __IO uint32_t FRQMAX; /**< RNG Frequency Count Maximum Limit Register, offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 13979 | }; |
AnnaBridge | 171:3a7713b1edbc | 13980 | union { /* offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 13981 | __I uint32_t SCMC; /**< RNG Statistical Check Monobit Count Register, offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 13982 | __IO uint32_t SCML; /**< RNG Statistical Check Monobit Limit Register, offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 13983 | }; |
AnnaBridge | 171:3a7713b1edbc | 13984 | union { /* offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 13985 | __I uint32_t SCR1C; /**< RNG Statistical Check Run Length 1 Count Register, offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 13986 | __IO uint32_t SCR1L; /**< RNG Statistical Check Run Length 1 Limit Register, offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 13987 | }; |
AnnaBridge | 171:3a7713b1edbc | 13988 | union { /* offset: 0x28 */ |
AnnaBridge | 171:3a7713b1edbc | 13989 | __I uint32_t SCR2C; /**< RNG Statistical Check Run Length 2 Count Register, offset: 0x28 */ |
AnnaBridge | 171:3a7713b1edbc | 13990 | __IO uint32_t SCR2L; /**< RNG Statistical Check Run Length 2 Limit Register, offset: 0x28 */ |
AnnaBridge | 171:3a7713b1edbc | 13991 | }; |
AnnaBridge | 171:3a7713b1edbc | 13992 | union { /* offset: 0x2C */ |
AnnaBridge | 171:3a7713b1edbc | 13993 | __I uint32_t SCR3C; /**< RNG Statistical Check Run Length 3 Count Register, offset: 0x2C */ |
AnnaBridge | 171:3a7713b1edbc | 13994 | __IO uint32_t SCR3L; /**< RNG Statistical Check Run Length 3 Limit Register, offset: 0x2C */ |
AnnaBridge | 171:3a7713b1edbc | 13995 | }; |
AnnaBridge | 171:3a7713b1edbc | 13996 | union { /* offset: 0x30 */ |
AnnaBridge | 171:3a7713b1edbc | 13997 | __I uint32_t SCR4C; /**< RNG Statistical Check Run Length 4 Count Register, offset: 0x30 */ |
AnnaBridge | 171:3a7713b1edbc | 13998 | __IO uint32_t SCR4L; /**< RNG Statistical Check Run Length 4 Limit Register, offset: 0x30 */ |
AnnaBridge | 171:3a7713b1edbc | 13999 | }; |
AnnaBridge | 171:3a7713b1edbc | 14000 | union { /* offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 14001 | __I uint32_t SCR5C; /**< RNG Statistical Check Run Length 5 Count Register, offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 14002 | __IO uint32_t SCR5L; /**< RNG Statistical Check Run Length 5 Limit Register, offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 14003 | }; |
AnnaBridge | 171:3a7713b1edbc | 14004 | union { /* offset: 0x38 */ |
AnnaBridge | 171:3a7713b1edbc | 14005 | __I uint32_t SCR6PC; /**< RNG Statistical Check Run Length 6+ Count Register, offset: 0x38 */ |
AnnaBridge | 171:3a7713b1edbc | 14006 | __IO uint32_t SCR6PL; /**< RNG Statistical Check Run Length 6+ Limit Register, offset: 0x38 */ |
AnnaBridge | 171:3a7713b1edbc | 14007 | }; |
AnnaBridge | 171:3a7713b1edbc | 14008 | __I uint32_t STATUS; /**< RNG Status Register, offset: 0x3C */ |
AnnaBridge | 171:3a7713b1edbc | 14009 | __I uint32_t ENT[16]; /**< RNG TRNG Entropy Read Register, array offset: 0x40, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 14010 | __I uint32_t PKRCNT10; /**< RNG Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */ |
AnnaBridge | 171:3a7713b1edbc | 14011 | __I uint32_t PKRCNT32; /**< RNG Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */ |
AnnaBridge | 171:3a7713b1edbc | 14012 | __I uint32_t PKRCNT54; /**< RNG Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */ |
AnnaBridge | 171:3a7713b1edbc | 14013 | __I uint32_t PKRCNT76; /**< RNG Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */ |
AnnaBridge | 171:3a7713b1edbc | 14014 | __I uint32_t PKRCNT98; /**< RNG Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */ |
AnnaBridge | 171:3a7713b1edbc | 14015 | __I uint32_t PKRCNTBA; /**< RNG Statistical Check Poker Count B and A Register, offset: 0x94 */ |
AnnaBridge | 171:3a7713b1edbc | 14016 | __I uint32_t PKRCNTDC; /**< RNG Statistical Check Poker Count D and C Register, offset: 0x98 */ |
AnnaBridge | 171:3a7713b1edbc | 14017 | __I uint32_t PKRCNTFE; /**< RNG Statistical Check Poker Count F and E Register, offset: 0x9C */ |
AnnaBridge | 171:3a7713b1edbc | 14018 | uint8_t RESERVED_0[16]; |
AnnaBridge | 171:3a7713b1edbc | 14019 | __IO uint32_t SEC_CFG; /**< RNG Security Configuration Register, offset: 0xB0 */ |
AnnaBridge | 171:3a7713b1edbc | 14020 | __IO uint32_t INT_CTRL; /**< RNG Interrupt Control Register, offset: 0xB4 */ |
AnnaBridge | 171:3a7713b1edbc | 14021 | __IO uint32_t INT_MASK; /**< RNG Mask Register, offset: 0xB8 */ |
AnnaBridge | 171:3a7713b1edbc | 14022 | __IO uint32_t INT_STATUS; /**< RNG Interrupt Status Register, offset: 0xBC */ |
AnnaBridge | 171:3a7713b1edbc | 14023 | uint8_t RESERVED_1[48]; |
AnnaBridge | 171:3a7713b1edbc | 14024 | __I uint32_t VID1; /**< RNG Version ID Register (MS), offset: 0xF0 */ |
AnnaBridge | 171:3a7713b1edbc | 14025 | __I uint32_t VID2; /**< RNG Version ID Register (LS), offset: 0xF4 */ |
AnnaBridge | 171:3a7713b1edbc | 14026 | } TRNG_Type; |
AnnaBridge | 171:3a7713b1edbc | 14027 | |
AnnaBridge | 171:3a7713b1edbc | 14028 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 14029 | -- TRNG Register Masks |
AnnaBridge | 171:3a7713b1edbc | 14030 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 14031 | |
AnnaBridge | 171:3a7713b1edbc | 14032 | /*! |
AnnaBridge | 171:3a7713b1edbc | 14033 | * @addtogroup TRNG_Register_Masks TRNG Register Masks |
AnnaBridge | 171:3a7713b1edbc | 14034 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 14035 | */ |
AnnaBridge | 171:3a7713b1edbc | 14036 | |
AnnaBridge | 171:3a7713b1edbc | 14037 | /*! @name MCTL - RNG Miscellaneous Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 14038 | #define TRNG_MCTL_SAMP_MODE_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 14039 | #define TRNG_MCTL_SAMP_MODE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14040 | #define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14041 | #define TRNG_MCTL_OSC_DIV_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 14042 | #define TRNG_MCTL_OSC_DIV_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 14043 | #define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14044 | #define TRNG_MCTL_UNUSED_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 14045 | #define TRNG_MCTL_UNUSED_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 14046 | #define TRNG_MCTL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED_SHIFT)) & TRNG_MCTL_UNUSED_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14047 | #define TRNG_MCTL_TRNG_ACC_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 14048 | #define TRNG_MCTL_TRNG_ACC_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 14049 | #define TRNG_MCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14050 | #define TRNG_MCTL_RST_DEF_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 14051 | #define TRNG_MCTL_RST_DEF_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 14052 | #define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14053 | #define TRNG_MCTL_FOR_SCLK_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 14054 | #define TRNG_MCTL_FOR_SCLK_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 14055 | #define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14056 | #define TRNG_MCTL_FCT_FAIL_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 14057 | #define TRNG_MCTL_FCT_FAIL_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 14058 | #define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14059 | #define TRNG_MCTL_FCT_VAL_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 14060 | #define TRNG_MCTL_FCT_VAL_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 14061 | #define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14062 | #define TRNG_MCTL_ENT_VAL_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 14063 | #define TRNG_MCTL_ENT_VAL_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 14064 | #define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14065 | #define TRNG_MCTL_TST_OUT_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 14066 | #define TRNG_MCTL_TST_OUT_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 14067 | #define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14068 | #define TRNG_MCTL_ERR_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 14069 | #define TRNG_MCTL_ERR_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 14070 | #define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14071 | #define TRNG_MCTL_TSTOP_OK_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 14072 | #define TRNG_MCTL_TSTOP_OK_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 14073 | #define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14074 | #define TRNG_MCTL_PRGM_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 14075 | #define TRNG_MCTL_PRGM_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14076 | #define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14077 | |
AnnaBridge | 171:3a7713b1edbc | 14078 | /*! @name SCMISC - RNG Statistical Check Miscellaneous Register */ |
AnnaBridge | 171:3a7713b1edbc | 14079 | #define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 14080 | #define TRNG_SCMISC_LRUN_MAX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14081 | #define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14082 | #define TRNG_SCMISC_RTY_CT_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14083 | #define TRNG_SCMISC_RTY_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14084 | #define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14085 | |
AnnaBridge | 171:3a7713b1edbc | 14086 | /*! @name PKRRNG - RNG Poker Range Register */ |
AnnaBridge | 171:3a7713b1edbc | 14087 | #define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14088 | #define TRNG_PKRRNG_PKR_RNG_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14089 | #define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14090 | |
AnnaBridge | 171:3a7713b1edbc | 14091 | /*! @name PKRMAX - RNG Poker Maximum Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 14092 | #define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14093 | #define TRNG_PKRMAX_PKR_MAX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14094 | #define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14095 | |
AnnaBridge | 171:3a7713b1edbc | 14096 | /*! @name PKRSQ - RNG Poker Square Calculation Result Register */ |
AnnaBridge | 171:3a7713b1edbc | 14097 | #define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14098 | #define TRNG_PKRSQ_PKR_SQ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14099 | #define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14100 | |
AnnaBridge | 171:3a7713b1edbc | 14101 | /*! @name SDCTL - RNG Seed Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 14102 | #define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14103 | #define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14104 | #define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14105 | #define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14106 | #define TRNG_SDCTL_ENT_DLY_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14107 | #define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14108 | |
AnnaBridge | 171:3a7713b1edbc | 14109 | /*! @name SBLIM - RNG Sparse Bit Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 14110 | #define TRNG_SBLIM_SB_LIM_MASK (0x3FFU) |
AnnaBridge | 171:3a7713b1edbc | 14111 | #define TRNG_SBLIM_SB_LIM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14112 | #define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14113 | |
AnnaBridge | 171:3a7713b1edbc | 14114 | /*! @name TOTSAM - RNG Total Samples Register */ |
AnnaBridge | 171:3a7713b1edbc | 14115 | #define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14116 | #define TRNG_TOTSAM_TOT_SAM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14117 | #define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14118 | |
AnnaBridge | 171:3a7713b1edbc | 14119 | /*! @name FRQMIN - RNG Frequency Count Minimum Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 14120 | #define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14121 | #define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14122 | #define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14123 | |
AnnaBridge | 171:3a7713b1edbc | 14124 | /*! @name FRQCNT - RNG Frequency Count Register */ |
AnnaBridge | 171:3a7713b1edbc | 14125 | #define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14126 | #define TRNG_FRQCNT_FRQ_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14127 | #define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14128 | |
AnnaBridge | 171:3a7713b1edbc | 14129 | /*! @name FRQMAX - RNG Frequency Count Maximum Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 14130 | #define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14131 | #define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14132 | #define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14133 | |
AnnaBridge | 171:3a7713b1edbc | 14134 | /*! @name SCMC - RNG Statistical Check Monobit Count Register */ |
AnnaBridge | 171:3a7713b1edbc | 14135 | #define TRNG_SCMC_MONO_CT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14136 | #define TRNG_SCMC_MONO_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14137 | #define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14138 | |
AnnaBridge | 171:3a7713b1edbc | 14139 | /*! @name SCML - RNG Statistical Check Monobit Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 14140 | #define TRNG_SCML_MONO_MAX_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14141 | #define TRNG_SCML_MONO_MAX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14142 | #define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14143 | #define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14144 | #define TRNG_SCML_MONO_RNG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14145 | #define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14146 | |
AnnaBridge | 171:3a7713b1edbc | 14147 | /*! @name SCR1C - RNG Statistical Check Run Length 1 Count Register */ |
AnnaBridge | 171:3a7713b1edbc | 14148 | #define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU) |
AnnaBridge | 171:3a7713b1edbc | 14149 | #define TRNG_SCR1C_R1_0_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14150 | #define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14151 | #define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14152 | #define TRNG_SCR1C_R1_1_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14153 | #define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14154 | |
AnnaBridge | 171:3a7713b1edbc | 14155 | /*! @name SCR1L - RNG Statistical Check Run Length 1 Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 14156 | #define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU) |
AnnaBridge | 171:3a7713b1edbc | 14157 | #define TRNG_SCR1L_RUN1_MAX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14158 | #define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14159 | #define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14160 | #define TRNG_SCR1L_RUN1_RNG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14161 | #define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14162 | |
AnnaBridge | 171:3a7713b1edbc | 14163 | /*! @name SCR2C - RNG Statistical Check Run Length 2 Count Register */ |
AnnaBridge | 171:3a7713b1edbc | 14164 | #define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU) |
AnnaBridge | 171:3a7713b1edbc | 14165 | #define TRNG_SCR2C_R2_0_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14166 | #define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14167 | #define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14168 | #define TRNG_SCR2C_R2_1_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14169 | #define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14170 | |
AnnaBridge | 171:3a7713b1edbc | 14171 | /*! @name SCR2L - RNG Statistical Check Run Length 2 Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 14172 | #define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU) |
AnnaBridge | 171:3a7713b1edbc | 14173 | #define TRNG_SCR2L_RUN2_MAX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14174 | #define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14175 | #define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14176 | #define TRNG_SCR2L_RUN2_RNG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14177 | #define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14178 | |
AnnaBridge | 171:3a7713b1edbc | 14179 | /*! @name SCR3C - RNG Statistical Check Run Length 3 Count Register */ |
AnnaBridge | 171:3a7713b1edbc | 14180 | #define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU) |
AnnaBridge | 171:3a7713b1edbc | 14181 | #define TRNG_SCR3C_R3_0_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14182 | #define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14183 | #define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14184 | #define TRNG_SCR3C_R3_1_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14185 | #define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14186 | |
AnnaBridge | 171:3a7713b1edbc | 14187 | /*! @name SCR3L - RNG Statistical Check Run Length 3 Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 14188 | #define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU) |
AnnaBridge | 171:3a7713b1edbc | 14189 | #define TRNG_SCR3L_RUN3_MAX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14190 | #define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14191 | #define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14192 | #define TRNG_SCR3L_RUN3_RNG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14193 | #define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14194 | |
AnnaBridge | 171:3a7713b1edbc | 14195 | /*! @name SCR4C - RNG Statistical Check Run Length 4 Count Register */ |
AnnaBridge | 171:3a7713b1edbc | 14196 | #define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14197 | #define TRNG_SCR4C_R4_0_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14198 | #define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14199 | #define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14200 | #define TRNG_SCR4C_R4_1_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14201 | #define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14202 | |
AnnaBridge | 171:3a7713b1edbc | 14203 | /*! @name SCR4L - RNG Statistical Check Run Length 4 Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 14204 | #define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14205 | #define TRNG_SCR4L_RUN4_MAX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14206 | #define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14207 | #define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14208 | #define TRNG_SCR4L_RUN4_RNG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14209 | #define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14210 | |
AnnaBridge | 171:3a7713b1edbc | 14211 | /*! @name SCR5C - RNG Statistical Check Run Length 5 Count Register */ |
AnnaBridge | 171:3a7713b1edbc | 14212 | #define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU) |
AnnaBridge | 171:3a7713b1edbc | 14213 | #define TRNG_SCR5C_R5_0_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14214 | #define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14215 | #define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14216 | #define TRNG_SCR5C_R5_1_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14217 | #define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14218 | |
AnnaBridge | 171:3a7713b1edbc | 14219 | /*! @name SCR5L - RNG Statistical Check Run Length 5 Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 14220 | #define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU) |
AnnaBridge | 171:3a7713b1edbc | 14221 | #define TRNG_SCR5L_RUN5_MAX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14222 | #define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14223 | #define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14224 | #define TRNG_SCR5L_RUN5_RNG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14225 | #define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14226 | |
AnnaBridge | 171:3a7713b1edbc | 14227 | /*! @name SCR6PC - RNG Statistical Check Run Length 6+ Count Register */ |
AnnaBridge | 171:3a7713b1edbc | 14228 | #define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU) |
AnnaBridge | 171:3a7713b1edbc | 14229 | #define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14230 | #define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14231 | #define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14232 | #define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14233 | #define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14234 | |
AnnaBridge | 171:3a7713b1edbc | 14235 | /*! @name SCR6PL - RNG Statistical Check Run Length 6+ Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 14236 | #define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU) |
AnnaBridge | 171:3a7713b1edbc | 14237 | #define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14238 | #define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14239 | #define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14240 | #define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14241 | #define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14242 | |
AnnaBridge | 171:3a7713b1edbc | 14243 | /*! @name STATUS - RNG Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 14244 | #define TRNG_STATUS_TF1BR0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 14245 | #define TRNG_STATUS_TF1BR0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14246 | #define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14247 | #define TRNG_STATUS_TF1BR1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 14248 | #define TRNG_STATUS_TF1BR1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 14249 | #define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14250 | #define TRNG_STATUS_TF2BR0_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 14251 | #define TRNG_STATUS_TF2BR0_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 14252 | #define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14253 | #define TRNG_STATUS_TF2BR1_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 14254 | #define TRNG_STATUS_TF2BR1_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 14255 | #define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14256 | #define TRNG_STATUS_TF3BR0_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 14257 | #define TRNG_STATUS_TF3BR0_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 14258 | #define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14259 | #define TRNG_STATUS_TF3BR1_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 14260 | #define TRNG_STATUS_TF3BR1_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 14261 | #define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14262 | #define TRNG_STATUS_TF4BR0_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 14263 | #define TRNG_STATUS_TF4BR0_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 14264 | #define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14265 | #define TRNG_STATUS_TF4BR1_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 14266 | #define TRNG_STATUS_TF4BR1_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 14267 | #define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14268 | #define TRNG_STATUS_TF5BR0_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 14269 | #define TRNG_STATUS_TF5BR0_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 14270 | #define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14271 | #define TRNG_STATUS_TF5BR1_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 14272 | #define TRNG_STATUS_TF5BR1_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 14273 | #define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14274 | #define TRNG_STATUS_TF6PBR0_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 14275 | #define TRNG_STATUS_TF6PBR0_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 14276 | #define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14277 | #define TRNG_STATUS_TF6PBR1_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 14278 | #define TRNG_STATUS_TF6PBR1_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 14279 | #define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14280 | #define TRNG_STATUS_TFSB_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 14281 | #define TRNG_STATUS_TFSB_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 14282 | #define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14283 | #define TRNG_STATUS_TFLR_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 14284 | #define TRNG_STATUS_TFLR_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 14285 | #define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14286 | #define TRNG_STATUS_TFP_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 14287 | #define TRNG_STATUS_TFP_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 14288 | #define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14289 | #define TRNG_STATUS_TFMB_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 14290 | #define TRNG_STATUS_TFMB_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 14291 | #define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14292 | #define TRNG_STATUS_RETRY_CT_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14293 | #define TRNG_STATUS_RETRY_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14294 | #define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14295 | |
AnnaBridge | 171:3a7713b1edbc | 14296 | /*! @name ENT - RNG TRNG Entropy Read Register */ |
AnnaBridge | 171:3a7713b1edbc | 14297 | #define TRNG_ENT_ENT_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14298 | #define TRNG_ENT_ENT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14299 | #define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14300 | |
AnnaBridge | 171:3a7713b1edbc | 14301 | /* The count of TRNG_ENT */ |
AnnaBridge | 171:3a7713b1edbc | 14302 | #define TRNG_ENT_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14303 | |
AnnaBridge | 171:3a7713b1edbc | 14304 | /*! @name PKRCNT10 - RNG Statistical Check Poker Count 1 and 0 Register */ |
AnnaBridge | 171:3a7713b1edbc | 14305 | #define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14306 | #define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14307 | #define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14308 | #define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14309 | #define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14310 | #define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14311 | |
AnnaBridge | 171:3a7713b1edbc | 14312 | /*! @name PKRCNT32 - RNG Statistical Check Poker Count 3 and 2 Register */ |
AnnaBridge | 171:3a7713b1edbc | 14313 | #define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14314 | #define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14315 | #define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14316 | #define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14317 | #define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14318 | #define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14319 | |
AnnaBridge | 171:3a7713b1edbc | 14320 | /*! @name PKRCNT54 - RNG Statistical Check Poker Count 5 and 4 Register */ |
AnnaBridge | 171:3a7713b1edbc | 14321 | #define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14322 | #define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14323 | #define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14324 | #define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14325 | #define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14326 | #define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14327 | |
AnnaBridge | 171:3a7713b1edbc | 14328 | /*! @name PKRCNT76 - RNG Statistical Check Poker Count 7 and 6 Register */ |
AnnaBridge | 171:3a7713b1edbc | 14329 | #define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14330 | #define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14331 | #define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14332 | #define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14333 | #define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14334 | #define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14335 | |
AnnaBridge | 171:3a7713b1edbc | 14336 | /*! @name PKRCNT98 - RNG Statistical Check Poker Count 9 and 8 Register */ |
AnnaBridge | 171:3a7713b1edbc | 14337 | #define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14338 | #define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14339 | #define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14340 | #define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14341 | #define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14342 | #define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14343 | |
AnnaBridge | 171:3a7713b1edbc | 14344 | /*! @name PKRCNTBA - RNG Statistical Check Poker Count B and A Register */ |
AnnaBridge | 171:3a7713b1edbc | 14345 | #define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14346 | #define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14347 | #define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14348 | #define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14349 | #define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14350 | #define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14351 | |
AnnaBridge | 171:3a7713b1edbc | 14352 | /*! @name PKRCNTDC - RNG Statistical Check Poker Count D and C Register */ |
AnnaBridge | 171:3a7713b1edbc | 14353 | #define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14354 | #define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14355 | #define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14356 | #define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14357 | #define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14358 | #define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14359 | |
AnnaBridge | 171:3a7713b1edbc | 14360 | /*! @name PKRCNTFE - RNG Statistical Check Poker Count F and E Register */ |
AnnaBridge | 171:3a7713b1edbc | 14361 | #define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14362 | #define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14363 | #define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14364 | #define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14365 | #define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14366 | #define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14367 | |
AnnaBridge | 171:3a7713b1edbc | 14368 | /*! @name SEC_CFG - RNG Security Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 14369 | #define TRNG_SEC_CFG_SH0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 14370 | #define TRNG_SEC_CFG_SH0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14371 | #define TRNG_SEC_CFG_SH0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SH0_SHIFT)) & TRNG_SEC_CFG_SH0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14372 | #define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 14373 | #define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 14374 | #define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14375 | #define TRNG_SEC_CFG_SK_VAL_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 14376 | #define TRNG_SEC_CFG_SK_VAL_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 14377 | #define TRNG_SEC_CFG_SK_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SK_VAL_SHIFT)) & TRNG_SEC_CFG_SK_VAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14378 | |
AnnaBridge | 171:3a7713b1edbc | 14379 | /*! @name INT_CTRL - RNG Interrupt Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 14380 | #define TRNG_INT_CTRL_HW_ERR_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 14381 | #define TRNG_INT_CTRL_HW_ERR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14382 | #define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14383 | #define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 14384 | #define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 14385 | #define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14386 | #define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 14387 | #define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 14388 | #define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14389 | #define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U) |
AnnaBridge | 171:3a7713b1edbc | 14390 | #define TRNG_INT_CTRL_UNUSED_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 14391 | #define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14392 | |
AnnaBridge | 171:3a7713b1edbc | 14393 | /*! @name INT_MASK - RNG Mask Register */ |
AnnaBridge | 171:3a7713b1edbc | 14394 | #define TRNG_INT_MASK_HW_ERR_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 14395 | #define TRNG_INT_MASK_HW_ERR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14396 | #define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14397 | #define TRNG_INT_MASK_ENT_VAL_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 14398 | #define TRNG_INT_MASK_ENT_VAL_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 14399 | #define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14400 | #define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 14401 | #define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 14402 | #define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14403 | |
AnnaBridge | 171:3a7713b1edbc | 14404 | /*! @name INT_STATUS - RNG Interrupt Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 14405 | #define TRNG_INT_STATUS_HW_ERR_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 14406 | #define TRNG_INT_STATUS_HW_ERR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14407 | #define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14408 | #define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 14409 | #define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 14410 | #define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14411 | #define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 14412 | #define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 14413 | #define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14414 | |
AnnaBridge | 171:3a7713b1edbc | 14415 | /*! @name VID1 - RNG Version ID Register (MS) */ |
AnnaBridge | 171:3a7713b1edbc | 14416 | #define TRNG_VID1_RNG_MIN_REV_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 14417 | #define TRNG_VID1_RNG_MIN_REV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14418 | #define TRNG_VID1_RNG_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_RNG_MIN_REV_SHIFT)) & TRNG_VID1_RNG_MIN_REV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14419 | #define TRNG_VID1_RNG_MAJ_REV_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 14420 | #define TRNG_VID1_RNG_MAJ_REV_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 14421 | #define TRNG_VID1_RNG_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_RNG_MAJ_REV_SHIFT)) & TRNG_VID1_RNG_MAJ_REV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14422 | #define TRNG_VID1_RNG_IP_ID_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14423 | #define TRNG_VID1_RNG_IP_ID_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14424 | #define TRNG_VID1_RNG_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_RNG_IP_ID_SHIFT)) & TRNG_VID1_RNG_IP_ID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14425 | |
AnnaBridge | 171:3a7713b1edbc | 14426 | /*! @name VID2 - RNG Version ID Register (LS) */ |
AnnaBridge | 171:3a7713b1edbc | 14427 | #define TRNG_VID2_RNG_CONFIG_OPT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 14428 | #define TRNG_VID2_RNG_CONFIG_OPT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14429 | #define TRNG_VID2_RNG_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_RNG_CONFIG_OPT_SHIFT)) & TRNG_VID2_RNG_CONFIG_OPT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14430 | #define TRNG_VID2_RNG_ECO_REV_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 14431 | #define TRNG_VID2_RNG_ECO_REV_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 14432 | #define TRNG_VID2_RNG_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_RNG_ECO_REV_SHIFT)) & TRNG_VID2_RNG_ECO_REV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14433 | #define TRNG_VID2_RNG_INTG_OPT_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14434 | #define TRNG_VID2_RNG_INTG_OPT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14435 | #define TRNG_VID2_RNG_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_RNG_INTG_OPT_SHIFT)) & TRNG_VID2_RNG_INTG_OPT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14436 | #define TRNG_VID2_RNG_ERA_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 14437 | #define TRNG_VID2_RNG_ERA_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 14438 | #define TRNG_VID2_RNG_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_RNG_ERA_SHIFT)) & TRNG_VID2_RNG_ERA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14439 | |
AnnaBridge | 171:3a7713b1edbc | 14440 | |
AnnaBridge | 171:3a7713b1edbc | 14441 | /*! |
AnnaBridge | 171:3a7713b1edbc | 14442 | * @} |
AnnaBridge | 171:3a7713b1edbc | 14443 | */ /* end of group TRNG_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 14444 | |
AnnaBridge | 171:3a7713b1edbc | 14445 | |
AnnaBridge | 171:3a7713b1edbc | 14446 | /* TRNG - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 14447 | /** Peripheral TRNG0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 14448 | #define TRNG0_BASE (0x400A0000u) |
AnnaBridge | 171:3a7713b1edbc | 14449 | /** Peripheral TRNG0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 14450 | #define TRNG0 ((TRNG_Type *)TRNG0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 14451 | /** Array initializer of TRNG peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 14452 | #define TRNG_BASE_ADDRS { TRNG0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 14453 | /** Array initializer of TRNG peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 14454 | #define TRNG_BASE_PTRS { TRNG0 } |
AnnaBridge | 171:3a7713b1edbc | 14455 | /** Interrupt vectors for the TRNG peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 14456 | #define TRNG_IRQS { TRNG0_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 14457 | |
AnnaBridge | 171:3a7713b1edbc | 14458 | /*! |
AnnaBridge | 171:3a7713b1edbc | 14459 | * @} |
AnnaBridge | 171:3a7713b1edbc | 14460 | */ /* end of group TRNG_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 14461 | |
AnnaBridge | 171:3a7713b1edbc | 14462 | |
AnnaBridge | 171:3a7713b1edbc | 14463 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 14464 | -- TSI Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 14465 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 14466 | |
AnnaBridge | 171:3a7713b1edbc | 14467 | /*! |
AnnaBridge | 171:3a7713b1edbc | 14468 | * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 14469 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 14470 | */ |
AnnaBridge | 171:3a7713b1edbc | 14471 | |
AnnaBridge | 171:3a7713b1edbc | 14472 | /** TSI - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 14473 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 14474 | __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 14475 | __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 14476 | __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 14477 | } TSI_Type; |
AnnaBridge | 171:3a7713b1edbc | 14478 | |
AnnaBridge | 171:3a7713b1edbc | 14479 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 14480 | -- TSI Register Masks |
AnnaBridge | 171:3a7713b1edbc | 14481 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 14482 | |
AnnaBridge | 171:3a7713b1edbc | 14483 | /*! |
AnnaBridge | 171:3a7713b1edbc | 14484 | * @addtogroup TSI_Register_Masks TSI Register Masks |
AnnaBridge | 171:3a7713b1edbc | 14485 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 14486 | */ |
AnnaBridge | 171:3a7713b1edbc | 14487 | |
AnnaBridge | 171:3a7713b1edbc | 14488 | /*! @name GENCS - TSI General Control and Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 14489 | #define TSI_GENCS_EOSDMEO_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 14490 | #define TSI_GENCS_EOSDMEO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14491 | #define TSI_GENCS_EOSDMEO(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSDMEO_SHIFT)) & TSI_GENCS_EOSDMEO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14492 | #define TSI_GENCS_CURSW_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 14493 | #define TSI_GENCS_CURSW_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 14494 | #define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14495 | #define TSI_GENCS_EOSF_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 14496 | #define TSI_GENCS_EOSF_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 14497 | #define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14498 | #define TSI_GENCS_SCNIP_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 14499 | #define TSI_GENCS_SCNIP_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 14500 | #define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14501 | #define TSI_GENCS_STM_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 14502 | #define TSI_GENCS_STM_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 14503 | #define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14504 | #define TSI_GENCS_STPE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 14505 | #define TSI_GENCS_STPE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 14506 | #define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14507 | #define TSI_GENCS_TSIIEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 14508 | #define TSI_GENCS_TSIIEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 14509 | #define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14510 | #define TSI_GENCS_TSIEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 14511 | #define TSI_GENCS_TSIEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 14512 | #define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14513 | #define TSI_GENCS_NSCN_MASK (0x1F00U) |
AnnaBridge | 171:3a7713b1edbc | 14514 | #define TSI_GENCS_NSCN_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 14515 | #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14516 | #define TSI_GENCS_PS_MASK (0xE000U) |
AnnaBridge | 171:3a7713b1edbc | 14517 | #define TSI_GENCS_PS_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 14518 | #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14519 | #define TSI_GENCS_EXTCHRG_MASK (0x70000U) |
AnnaBridge | 171:3a7713b1edbc | 14520 | #define TSI_GENCS_EXTCHRG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14521 | #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14522 | #define TSI_GENCS_DVOLT_MASK (0x180000U) |
AnnaBridge | 171:3a7713b1edbc | 14523 | #define TSI_GENCS_DVOLT_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 14524 | #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14525 | #define TSI_GENCS_REFCHRG_MASK (0xE00000U) |
AnnaBridge | 171:3a7713b1edbc | 14526 | #define TSI_GENCS_REFCHRG_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 14527 | #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14528 | #define TSI_GENCS_MODE_MASK (0xF000000U) |
AnnaBridge | 171:3a7713b1edbc | 14529 | #define TSI_GENCS_MODE_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 14530 | #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14531 | #define TSI_GENCS_ESOR_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 14532 | #define TSI_GENCS_ESOR_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 14533 | #define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14534 | #define TSI_GENCS_OUTRGF_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 14535 | #define TSI_GENCS_OUTRGF_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 14536 | #define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14537 | |
AnnaBridge | 171:3a7713b1edbc | 14538 | /*! @name DATA - TSI DATA Register */ |
AnnaBridge | 171:3a7713b1edbc | 14539 | #define TSI_DATA_TSICNT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14540 | #define TSI_DATA_TSICNT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14541 | #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14542 | #define TSI_DATA_SWTS_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 14543 | #define TSI_DATA_SWTS_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 14544 | #define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14545 | #define TSI_DATA_DMAEN_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 14546 | #define TSI_DATA_DMAEN_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 14547 | #define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14548 | #define TSI_DATA_TSICH_MASK (0xF0000000U) |
AnnaBridge | 171:3a7713b1edbc | 14549 | #define TSI_DATA_TSICH_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 14550 | #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14551 | |
AnnaBridge | 171:3a7713b1edbc | 14552 | /*! @name TSHD - TSI Threshold Register */ |
AnnaBridge | 171:3a7713b1edbc | 14553 | #define TSI_TSHD_THRESL_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 14554 | #define TSI_TSHD_THRESL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14555 | #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14556 | #define TSI_TSHD_THRESH_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 14557 | #define TSI_TSHD_THRESH_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14558 | #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14559 | |
AnnaBridge | 171:3a7713b1edbc | 14560 | |
AnnaBridge | 171:3a7713b1edbc | 14561 | /*! |
AnnaBridge | 171:3a7713b1edbc | 14562 | * @} |
AnnaBridge | 171:3a7713b1edbc | 14563 | */ /* end of group TSI_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 14564 | |
AnnaBridge | 171:3a7713b1edbc | 14565 | |
AnnaBridge | 171:3a7713b1edbc | 14566 | /* TSI - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 14567 | /** Peripheral TSI0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 14568 | #define TSI0_BASE (0x40045000u) |
AnnaBridge | 171:3a7713b1edbc | 14569 | /** Peripheral TSI0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 14570 | #define TSI0 ((TSI_Type *)TSI0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 14571 | /** Array initializer of TSI peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 14572 | #define TSI_BASE_ADDRS { TSI0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 14573 | /** Array initializer of TSI peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 14574 | #define TSI_BASE_PTRS { TSI0 } |
AnnaBridge | 171:3a7713b1edbc | 14575 | /** Interrupt vectors for the TSI peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 14576 | #define TSI_IRQS { TSI0_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 14577 | |
AnnaBridge | 171:3a7713b1edbc | 14578 | /*! |
AnnaBridge | 171:3a7713b1edbc | 14579 | * @} |
AnnaBridge | 171:3a7713b1edbc | 14580 | */ /* end of group TSI_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 14581 | |
AnnaBridge | 171:3a7713b1edbc | 14582 | |
AnnaBridge | 171:3a7713b1edbc | 14583 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 14584 | -- USB Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 14585 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 14586 | |
AnnaBridge | 171:3a7713b1edbc | 14587 | /*! |
AnnaBridge | 171:3a7713b1edbc | 14588 | * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 14589 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 14590 | */ |
AnnaBridge | 171:3a7713b1edbc | 14591 | |
AnnaBridge | 171:3a7713b1edbc | 14592 | /** USB - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 14593 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 14594 | __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 14595 | uint8_t RESERVED_0[3]; |
AnnaBridge | 171:3a7713b1edbc | 14596 | __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 14597 | uint8_t RESERVED_1[3]; |
AnnaBridge | 171:3a7713b1edbc | 14598 | __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 14599 | uint8_t RESERVED_2[3]; |
AnnaBridge | 171:3a7713b1edbc | 14600 | __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 14601 | uint8_t RESERVED_3[3]; |
AnnaBridge | 171:3a7713b1edbc | 14602 | __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 14603 | uint8_t RESERVED_4[3]; |
AnnaBridge | 171:3a7713b1edbc | 14604 | __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 14605 | uint8_t RESERVED_5[3]; |
AnnaBridge | 171:3a7713b1edbc | 14606 | __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 14607 | uint8_t RESERVED_6[3]; |
AnnaBridge | 171:3a7713b1edbc | 14608 | __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 14609 | uint8_t RESERVED_7[99]; |
AnnaBridge | 171:3a7713b1edbc | 14610 | __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */ |
AnnaBridge | 171:3a7713b1edbc | 14611 | uint8_t RESERVED_8[3]; |
AnnaBridge | 171:3a7713b1edbc | 14612 | __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */ |
AnnaBridge | 171:3a7713b1edbc | 14613 | uint8_t RESERVED_9[3]; |
AnnaBridge | 171:3a7713b1edbc | 14614 | __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */ |
AnnaBridge | 171:3a7713b1edbc | 14615 | uint8_t RESERVED_10[3]; |
AnnaBridge | 171:3a7713b1edbc | 14616 | __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */ |
AnnaBridge | 171:3a7713b1edbc | 14617 | uint8_t RESERVED_11[3]; |
AnnaBridge | 171:3a7713b1edbc | 14618 | __I uint8_t STAT; /**< Status register, offset: 0x90 */ |
AnnaBridge | 171:3a7713b1edbc | 14619 | uint8_t RESERVED_12[3]; |
AnnaBridge | 171:3a7713b1edbc | 14620 | __IO uint8_t CTL; /**< Control register, offset: 0x94 */ |
AnnaBridge | 171:3a7713b1edbc | 14621 | uint8_t RESERVED_13[3]; |
AnnaBridge | 171:3a7713b1edbc | 14622 | __IO uint8_t ADDR; /**< Address register, offset: 0x98 */ |
AnnaBridge | 171:3a7713b1edbc | 14623 | uint8_t RESERVED_14[3]; |
AnnaBridge | 171:3a7713b1edbc | 14624 | __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */ |
AnnaBridge | 171:3a7713b1edbc | 14625 | uint8_t RESERVED_15[3]; |
AnnaBridge | 171:3a7713b1edbc | 14626 | __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */ |
AnnaBridge | 171:3a7713b1edbc | 14627 | uint8_t RESERVED_16[3]; |
AnnaBridge | 171:3a7713b1edbc | 14628 | __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */ |
AnnaBridge | 171:3a7713b1edbc | 14629 | uint8_t RESERVED_17[3]; |
AnnaBridge | 171:3a7713b1edbc | 14630 | __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */ |
AnnaBridge | 171:3a7713b1edbc | 14631 | uint8_t RESERVED_18[3]; |
AnnaBridge | 171:3a7713b1edbc | 14632 | __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */ |
AnnaBridge | 171:3a7713b1edbc | 14633 | uint8_t RESERVED_19[3]; |
AnnaBridge | 171:3a7713b1edbc | 14634 | __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ |
AnnaBridge | 171:3a7713b1edbc | 14635 | uint8_t RESERVED_20[3]; |
AnnaBridge | 171:3a7713b1edbc | 14636 | __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ |
AnnaBridge | 171:3a7713b1edbc | 14637 | uint8_t RESERVED_21[11]; |
AnnaBridge | 171:3a7713b1edbc | 14638 | struct { /* offset: 0xC0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 14639 | __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 14640 | uint8_t RESERVED_0[3]; |
AnnaBridge | 171:3a7713b1edbc | 14641 | } ENDPOINT[16]; |
AnnaBridge | 171:3a7713b1edbc | 14642 | __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */ |
AnnaBridge | 171:3a7713b1edbc | 14643 | uint8_t RESERVED_22[3]; |
AnnaBridge | 171:3a7713b1edbc | 14644 | __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */ |
AnnaBridge | 171:3a7713b1edbc | 14645 | uint8_t RESERVED_23[3]; |
AnnaBridge | 171:3a7713b1edbc | 14646 | __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */ |
AnnaBridge | 171:3a7713b1edbc | 14647 | uint8_t RESERVED_24[3]; |
AnnaBridge | 171:3a7713b1edbc | 14648 | __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */ |
AnnaBridge | 171:3a7713b1edbc | 14649 | uint8_t RESERVED_25[7]; |
AnnaBridge | 171:3a7713b1edbc | 14650 | __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */ |
AnnaBridge | 171:3a7713b1edbc | 14651 | uint8_t RESERVED_26[23]; |
AnnaBridge | 171:3a7713b1edbc | 14652 | __IO uint8_t MISCCTRL; /**< Miscellaneous Control register, offset: 0x12C */ |
AnnaBridge | 171:3a7713b1edbc | 14653 | uint8_t RESERVED_27[19]; |
AnnaBridge | 171:3a7713b1edbc | 14654 | __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */ |
AnnaBridge | 171:3a7713b1edbc | 14655 | uint8_t RESERVED_28[3]; |
AnnaBridge | 171:3a7713b1edbc | 14656 | __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */ |
AnnaBridge | 171:3a7713b1edbc | 14657 | uint8_t RESERVED_29[15]; |
AnnaBridge | 171:3a7713b1edbc | 14658 | __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */ |
AnnaBridge | 171:3a7713b1edbc | 14659 | uint8_t RESERVED_30[7]; |
AnnaBridge | 171:3a7713b1edbc | 14660 | __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */ |
AnnaBridge | 171:3a7713b1edbc | 14661 | } USB_Type; |
AnnaBridge | 171:3a7713b1edbc | 14662 | |
AnnaBridge | 171:3a7713b1edbc | 14663 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 14664 | -- USB Register Masks |
AnnaBridge | 171:3a7713b1edbc | 14665 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 14666 | |
AnnaBridge | 171:3a7713b1edbc | 14667 | /*! |
AnnaBridge | 171:3a7713b1edbc | 14668 | * @addtogroup USB_Register_Masks USB Register Masks |
AnnaBridge | 171:3a7713b1edbc | 14669 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 14670 | */ |
AnnaBridge | 171:3a7713b1edbc | 14671 | |
AnnaBridge | 171:3a7713b1edbc | 14672 | /*! @name PERID - Peripheral ID register */ |
AnnaBridge | 171:3a7713b1edbc | 14673 | #define USB_PERID_ID_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 14674 | #define USB_PERID_ID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14675 | #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14676 | |
AnnaBridge | 171:3a7713b1edbc | 14677 | /*! @name IDCOMP - Peripheral ID Complement register */ |
AnnaBridge | 171:3a7713b1edbc | 14678 | #define USB_IDCOMP_NID_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 14679 | #define USB_IDCOMP_NID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14680 | #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14681 | |
AnnaBridge | 171:3a7713b1edbc | 14682 | /*! @name REV - Peripheral Revision register */ |
AnnaBridge | 171:3a7713b1edbc | 14683 | #define USB_REV_REV_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 14684 | #define USB_REV_REV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14685 | #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14686 | |
AnnaBridge | 171:3a7713b1edbc | 14687 | /*! @name ADDINFO - Peripheral Additional Info register */ |
AnnaBridge | 171:3a7713b1edbc | 14688 | #define USB_ADDINFO_IEHOST_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 14689 | #define USB_ADDINFO_IEHOST_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14690 | #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14691 | |
AnnaBridge | 171:3a7713b1edbc | 14692 | /*! @name OTGISTAT - OTG Interrupt Status register */ |
AnnaBridge | 171:3a7713b1edbc | 14693 | #define USB_OTGISTAT_AVBUSCHG_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 14694 | #define USB_OTGISTAT_AVBUSCHG_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14695 | #define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14696 | #define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 14697 | #define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 14698 | #define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14699 | #define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 14700 | #define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 14701 | #define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14702 | #define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 14703 | #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 14704 | #define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14705 | #define USB_OTGISTAT_ONEMSEC_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 14706 | #define USB_OTGISTAT_ONEMSEC_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 14707 | #define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14708 | #define USB_OTGISTAT_IDCHG_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 14709 | #define USB_OTGISTAT_IDCHG_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 14710 | #define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14711 | |
AnnaBridge | 171:3a7713b1edbc | 14712 | /*! @name OTGICR - OTG Interrupt Control register */ |
AnnaBridge | 171:3a7713b1edbc | 14713 | #define USB_OTGICR_AVBUSEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 14714 | #define USB_OTGICR_AVBUSEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14715 | #define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14716 | #define USB_OTGICR_BSESSEN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 14717 | #define USB_OTGICR_BSESSEN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 14718 | #define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14719 | #define USB_OTGICR_SESSVLDEN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 14720 | #define USB_OTGICR_SESSVLDEN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 14721 | #define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14722 | #define USB_OTGICR_LINESTATEEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 14723 | #define USB_OTGICR_LINESTATEEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 14724 | #define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14725 | #define USB_OTGICR_ONEMSECEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 14726 | #define USB_OTGICR_ONEMSECEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 14727 | #define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14728 | #define USB_OTGICR_IDEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 14729 | #define USB_OTGICR_IDEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 14730 | #define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14731 | |
AnnaBridge | 171:3a7713b1edbc | 14732 | /*! @name OTGSTAT - OTG Status register */ |
AnnaBridge | 171:3a7713b1edbc | 14733 | #define USB_OTGSTAT_AVBUSVLD_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 14734 | #define USB_OTGSTAT_AVBUSVLD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14735 | #define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14736 | #define USB_OTGSTAT_BSESSEND_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 14737 | #define USB_OTGSTAT_BSESSEND_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 14738 | #define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14739 | #define USB_OTGSTAT_SESS_VLD_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 14740 | #define USB_OTGSTAT_SESS_VLD_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 14741 | #define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14742 | #define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 14743 | #define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 14744 | #define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14745 | #define USB_OTGSTAT_ONEMSECEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 14746 | #define USB_OTGSTAT_ONEMSECEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 14747 | #define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14748 | #define USB_OTGSTAT_ID_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 14749 | #define USB_OTGSTAT_ID_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 14750 | #define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14751 | |
AnnaBridge | 171:3a7713b1edbc | 14752 | /*! @name OTGCTL - OTG Control register */ |
AnnaBridge | 171:3a7713b1edbc | 14753 | #define USB_OTGCTL_OTGEN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 14754 | #define USB_OTGCTL_OTGEN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 14755 | #define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14756 | #define USB_OTGCTL_DMLOW_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 14757 | #define USB_OTGCTL_DMLOW_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 14758 | #define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14759 | #define USB_OTGCTL_DPLOW_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 14760 | #define USB_OTGCTL_DPLOW_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 14761 | #define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14762 | #define USB_OTGCTL_DPHIGH_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 14763 | #define USB_OTGCTL_DPHIGH_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 14764 | #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14765 | |
AnnaBridge | 171:3a7713b1edbc | 14766 | /*! @name ISTAT - Interrupt Status register */ |
AnnaBridge | 171:3a7713b1edbc | 14767 | #define USB_ISTAT_USBRST_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 14768 | #define USB_ISTAT_USBRST_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14769 | #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14770 | #define USB_ISTAT_ERROR_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 14771 | #define USB_ISTAT_ERROR_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 14772 | #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14773 | #define USB_ISTAT_SOFTOK_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 14774 | #define USB_ISTAT_SOFTOK_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 14775 | #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14776 | #define USB_ISTAT_TOKDNE_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 14777 | #define USB_ISTAT_TOKDNE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 14778 | #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14779 | #define USB_ISTAT_SLEEP_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 14780 | #define USB_ISTAT_SLEEP_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 14781 | #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14782 | #define USB_ISTAT_RESUME_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 14783 | #define USB_ISTAT_RESUME_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 14784 | #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14785 | #define USB_ISTAT_ATTACH_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 14786 | #define USB_ISTAT_ATTACH_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 14787 | #define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14788 | #define USB_ISTAT_STALL_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 14789 | #define USB_ISTAT_STALL_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 14790 | #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14791 | |
AnnaBridge | 171:3a7713b1edbc | 14792 | /*! @name INTEN - Interrupt Enable register */ |
AnnaBridge | 171:3a7713b1edbc | 14793 | #define USB_INTEN_USBRSTEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 14794 | #define USB_INTEN_USBRSTEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14795 | #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14796 | #define USB_INTEN_ERROREN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 14797 | #define USB_INTEN_ERROREN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 14798 | #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14799 | #define USB_INTEN_SOFTOKEN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 14800 | #define USB_INTEN_SOFTOKEN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 14801 | #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14802 | #define USB_INTEN_TOKDNEEN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 14803 | #define USB_INTEN_TOKDNEEN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 14804 | #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14805 | #define USB_INTEN_SLEEPEN_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 14806 | #define USB_INTEN_SLEEPEN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 14807 | #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14808 | #define USB_INTEN_RESUMEEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 14809 | #define USB_INTEN_RESUMEEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 14810 | #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14811 | #define USB_INTEN_ATTACHEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 14812 | #define USB_INTEN_ATTACHEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 14813 | #define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14814 | #define USB_INTEN_STALLEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 14815 | #define USB_INTEN_STALLEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 14816 | #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14817 | |
AnnaBridge | 171:3a7713b1edbc | 14818 | /*! @name ERRSTAT - Error Interrupt Status register */ |
AnnaBridge | 171:3a7713b1edbc | 14819 | #define USB_ERRSTAT_PIDERR_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 14820 | #define USB_ERRSTAT_PIDERR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14821 | #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14822 | #define USB_ERRSTAT_CRC5EOF_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 14823 | #define USB_ERRSTAT_CRC5EOF_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 14824 | #define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14825 | #define USB_ERRSTAT_CRC16_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 14826 | #define USB_ERRSTAT_CRC16_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 14827 | #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14828 | #define USB_ERRSTAT_DFN8_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 14829 | #define USB_ERRSTAT_DFN8_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 14830 | #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14831 | #define USB_ERRSTAT_BTOERR_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 14832 | #define USB_ERRSTAT_BTOERR_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 14833 | #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14834 | #define USB_ERRSTAT_DMAERR_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 14835 | #define USB_ERRSTAT_DMAERR_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 14836 | #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14837 | #define USB_ERRSTAT_OWNERR_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 14838 | #define USB_ERRSTAT_OWNERR_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 14839 | #define USB_ERRSTAT_OWNERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14840 | #define USB_ERRSTAT_BTSERR_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 14841 | #define USB_ERRSTAT_BTSERR_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 14842 | #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14843 | |
AnnaBridge | 171:3a7713b1edbc | 14844 | /*! @name ERREN - Error Interrupt Enable register */ |
AnnaBridge | 171:3a7713b1edbc | 14845 | #define USB_ERREN_PIDERREN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 14846 | #define USB_ERREN_PIDERREN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14847 | #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14848 | #define USB_ERREN_CRC5EOFEN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 14849 | #define USB_ERREN_CRC5EOFEN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 14850 | #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14851 | #define USB_ERREN_CRC16EN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 14852 | #define USB_ERREN_CRC16EN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 14853 | #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14854 | #define USB_ERREN_DFN8EN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 14855 | #define USB_ERREN_DFN8EN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 14856 | #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14857 | #define USB_ERREN_BTOERREN_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 14858 | #define USB_ERREN_BTOERREN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 14859 | #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14860 | #define USB_ERREN_DMAERREN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 14861 | #define USB_ERREN_DMAERREN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 14862 | #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14863 | #define USB_ERREN_OWNERREN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 14864 | #define USB_ERREN_OWNERREN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 14865 | #define USB_ERREN_OWNERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14866 | #define USB_ERREN_BTSERREN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 14867 | #define USB_ERREN_BTSERREN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 14868 | #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14869 | |
AnnaBridge | 171:3a7713b1edbc | 14870 | /*! @name STAT - Status register */ |
AnnaBridge | 171:3a7713b1edbc | 14871 | #define USB_STAT_ODD_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 14872 | #define USB_STAT_ODD_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 14873 | #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14874 | #define USB_STAT_TX_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 14875 | #define USB_STAT_TX_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 14876 | #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14877 | #define USB_STAT_ENDP_MASK (0xF0U) |
AnnaBridge | 171:3a7713b1edbc | 14878 | #define USB_STAT_ENDP_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 14879 | #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14880 | |
AnnaBridge | 171:3a7713b1edbc | 14881 | /*! @name CTL - Control register */ |
AnnaBridge | 171:3a7713b1edbc | 14882 | #define USB_CTL_USBENSOFEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 14883 | #define USB_CTL_USBENSOFEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14884 | #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14885 | #define USB_CTL_ODDRST_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 14886 | #define USB_CTL_ODDRST_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 14887 | #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14888 | #define USB_CTL_RESUME_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 14889 | #define USB_CTL_RESUME_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 14890 | #define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14891 | #define USB_CTL_HOSTMODEEN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 14892 | #define USB_CTL_HOSTMODEEN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 14893 | #define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14894 | #define USB_CTL_RESET_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 14895 | #define USB_CTL_RESET_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 14896 | #define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14897 | #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 14898 | #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 14899 | #define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14900 | #define USB_CTL_SE0_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 14901 | #define USB_CTL_SE0_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 14902 | #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14903 | #define USB_CTL_JSTATE_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 14904 | #define USB_CTL_JSTATE_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 14905 | #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14906 | |
AnnaBridge | 171:3a7713b1edbc | 14907 | /*! @name ADDR - Address register */ |
AnnaBridge | 171:3a7713b1edbc | 14908 | #define USB_ADDR_ADDR_MASK (0x7FU) |
AnnaBridge | 171:3a7713b1edbc | 14909 | #define USB_ADDR_ADDR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14910 | #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14911 | #define USB_ADDR_LSEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 14912 | #define USB_ADDR_LSEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 14913 | #define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14914 | |
AnnaBridge | 171:3a7713b1edbc | 14915 | /*! @name BDTPAGE1 - BDT Page register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 14916 | #define USB_BDTPAGE1_BDTBA_MASK (0xFEU) |
AnnaBridge | 171:3a7713b1edbc | 14917 | #define USB_BDTPAGE1_BDTBA_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 14918 | #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14919 | |
AnnaBridge | 171:3a7713b1edbc | 14920 | /*! @name FRMNUML - Frame Number register Low */ |
AnnaBridge | 171:3a7713b1edbc | 14921 | #define USB_FRMNUML_FRM_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 14922 | #define USB_FRMNUML_FRM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14923 | #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14924 | |
AnnaBridge | 171:3a7713b1edbc | 14925 | /*! @name FRMNUMH - Frame Number register High */ |
AnnaBridge | 171:3a7713b1edbc | 14926 | #define USB_FRMNUMH_FRM_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 14927 | #define USB_FRMNUMH_FRM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14928 | #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14929 | |
AnnaBridge | 171:3a7713b1edbc | 14930 | /*! @name TOKEN - Token register */ |
AnnaBridge | 171:3a7713b1edbc | 14931 | #define USB_TOKEN_TOKENENDPT_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 14932 | #define USB_TOKEN_TOKENENDPT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14933 | #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14934 | #define USB_TOKEN_TOKENPID_MASK (0xF0U) |
AnnaBridge | 171:3a7713b1edbc | 14935 | #define USB_TOKEN_TOKENPID_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 14936 | #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14937 | |
AnnaBridge | 171:3a7713b1edbc | 14938 | /*! @name SOFTHLD - SOF Threshold register */ |
AnnaBridge | 171:3a7713b1edbc | 14939 | #define USB_SOFTHLD_CNT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 14940 | #define USB_SOFTHLD_CNT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14941 | #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14942 | |
AnnaBridge | 171:3a7713b1edbc | 14943 | /*! @name BDTPAGE2 - BDT Page Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 14944 | #define USB_BDTPAGE2_BDTBA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 14945 | #define USB_BDTPAGE2_BDTBA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14946 | #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14947 | |
AnnaBridge | 171:3a7713b1edbc | 14948 | /*! @name BDTPAGE3 - BDT Page Register 3 */ |
AnnaBridge | 171:3a7713b1edbc | 14949 | #define USB_BDTPAGE3_BDTBA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 14950 | #define USB_BDTPAGE3_BDTBA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14951 | #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14952 | |
AnnaBridge | 171:3a7713b1edbc | 14953 | /*! @name ENDPT - Endpoint Control register */ |
AnnaBridge | 171:3a7713b1edbc | 14954 | #define USB_ENDPT_EPHSHK_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 14955 | #define USB_ENDPT_EPHSHK_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 14956 | #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14957 | #define USB_ENDPT_EPSTALL_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 14958 | #define USB_ENDPT_EPSTALL_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 14959 | #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14960 | #define USB_ENDPT_EPTXEN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 14961 | #define USB_ENDPT_EPTXEN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 14962 | #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14963 | #define USB_ENDPT_EPRXEN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 14964 | #define USB_ENDPT_EPRXEN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 14965 | #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14966 | #define USB_ENDPT_EPCTLDIS_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 14967 | #define USB_ENDPT_EPCTLDIS_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 14968 | #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14969 | #define USB_ENDPT_RETRYDIS_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 14970 | #define USB_ENDPT_RETRYDIS_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 14971 | #define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14972 | #define USB_ENDPT_HOSTWOHUB_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 14973 | #define USB_ENDPT_HOSTWOHUB_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 14974 | #define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14975 | |
AnnaBridge | 171:3a7713b1edbc | 14976 | /* The count of USB_ENDPT */ |
AnnaBridge | 171:3a7713b1edbc | 14977 | #define USB_ENDPT_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 14978 | |
AnnaBridge | 171:3a7713b1edbc | 14979 | /*! @name USBCTRL - USB Control register */ |
AnnaBridge | 171:3a7713b1edbc | 14980 | #define USB_USBCTRL_UARTSEL_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 14981 | #define USB_USBCTRL_UARTSEL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 14982 | #define USB_USBCTRL_UARTSEL(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14983 | #define USB_USBCTRL_UARTCHLS_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 14984 | #define USB_USBCTRL_UARTCHLS_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 14985 | #define USB_USBCTRL_UARTCHLS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14986 | #define USB_USBCTRL_PDE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 14987 | #define USB_USBCTRL_PDE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 14988 | #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14989 | #define USB_USBCTRL_SUSP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 14990 | #define USB_USBCTRL_SUSP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 14991 | #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14992 | |
AnnaBridge | 171:3a7713b1edbc | 14993 | /*! @name OBSERVE - USB OTG Observe register */ |
AnnaBridge | 171:3a7713b1edbc | 14994 | #define USB_OBSERVE_DMPD_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 14995 | #define USB_OBSERVE_DMPD_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 14996 | #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 14997 | #define USB_OBSERVE_DPPD_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 14998 | #define USB_OBSERVE_DPPD_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 14999 | #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15000 | #define USB_OBSERVE_DPPU_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 15001 | #define USB_OBSERVE_DPPU_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 15002 | #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15003 | |
AnnaBridge | 171:3a7713b1edbc | 15004 | /*! @name CONTROL - USB OTG Control register */ |
AnnaBridge | 171:3a7713b1edbc | 15005 | #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 15006 | #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 15007 | #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15008 | |
AnnaBridge | 171:3a7713b1edbc | 15009 | /*! @name USBTRC0 - USB Transceiver Control register 0 */ |
AnnaBridge | 171:3a7713b1edbc | 15010 | #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 15011 | #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15012 | #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15013 | #define USB_USBTRC0_SYNC_DET_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 15014 | #define USB_USBTRC0_SYNC_DET_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 15015 | #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15016 | #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 15017 | #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 15018 | #define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15019 | #define USB_USBTRC0_VREDG_DET_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 15020 | #define USB_USBTRC0_VREDG_DET_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 15021 | #define USB_USBTRC0_VREDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15022 | #define USB_USBTRC0_VFEDG_DET_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 15023 | #define USB_USBTRC0_VFEDG_DET_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 15024 | #define USB_USBTRC0_VFEDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15025 | #define USB_USBTRC0_USBRESMEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 15026 | #define USB_USBTRC0_USBRESMEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 15027 | #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15028 | #define USB_USBTRC0_USBRESET_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 15029 | #define USB_USBTRC0_USBRESET_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 15030 | #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15031 | |
AnnaBridge | 171:3a7713b1edbc | 15032 | /*! @name USBFRMADJUST - Frame Adjust Register */ |
AnnaBridge | 171:3a7713b1edbc | 15033 | #define USB_USBFRMADJUST_ADJ_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 15034 | #define USB_USBFRMADJUST_ADJ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15035 | #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15036 | |
AnnaBridge | 171:3a7713b1edbc | 15037 | /*! @name MISCCTRL - Miscellaneous Control register */ |
AnnaBridge | 171:3a7713b1edbc | 15038 | #define USB_MISCCTRL_SOFDYNTHLD_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 15039 | #define USB_MISCCTRL_SOFDYNTHLD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15040 | #define USB_MISCCTRL_SOFDYNTHLD(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15041 | #define USB_MISCCTRL_SOFBUSSET_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 15042 | #define USB_MISCCTRL_SOFBUSSET_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 15043 | #define USB_MISCCTRL_SOFBUSSET(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15044 | #define USB_MISCCTRL_OWNERRISODIS_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 15045 | #define USB_MISCCTRL_OWNERRISODIS_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 15046 | #define USB_MISCCTRL_OWNERRISODIS(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15047 | #define USB_MISCCTRL_VREDG_EN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 15048 | #define USB_MISCCTRL_VREDG_EN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 15049 | #define USB_MISCCTRL_VREDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15050 | #define USB_MISCCTRL_VFEDG_EN_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 15051 | #define USB_MISCCTRL_VFEDG_EN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 15052 | #define USB_MISCCTRL_VFEDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15053 | |
AnnaBridge | 171:3a7713b1edbc | 15054 | /*! @name CLK_RECOVER_CTRL - USB Clock recovery control */ |
AnnaBridge | 171:3a7713b1edbc | 15055 | #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 15056 | #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 15057 | #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15058 | #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 15059 | #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 15060 | #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15061 | #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 15062 | #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 15063 | #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15064 | |
AnnaBridge | 171:3a7713b1edbc | 15065 | /*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */ |
AnnaBridge | 171:3a7713b1edbc | 15066 | #define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 15067 | #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15068 | #define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15069 | #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 15070 | #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 15071 | #define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15072 | |
AnnaBridge | 171:3a7713b1edbc | 15073 | /*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 15074 | #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 15075 | #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 15076 | #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15077 | |
AnnaBridge | 171:3a7713b1edbc | 15078 | /*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */ |
AnnaBridge | 171:3a7713b1edbc | 15079 | #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 15080 | #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 15081 | #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15082 | |
AnnaBridge | 171:3a7713b1edbc | 15083 | |
AnnaBridge | 171:3a7713b1edbc | 15084 | /*! |
AnnaBridge | 171:3a7713b1edbc | 15085 | * @} |
AnnaBridge | 171:3a7713b1edbc | 15086 | */ /* end of group USB_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 15087 | |
AnnaBridge | 171:3a7713b1edbc | 15088 | |
AnnaBridge | 171:3a7713b1edbc | 15089 | /* USB - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 15090 | /** Peripheral USB0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 15091 | #define USB0_BASE (0x40072000u) |
AnnaBridge | 171:3a7713b1edbc | 15092 | /** Peripheral USB0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 15093 | #define USB0 ((USB_Type *)USB0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 15094 | /** Array initializer of USB peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 15095 | #define USB_BASE_ADDRS { USB0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 15096 | /** Array initializer of USB peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 15097 | #define USB_BASE_PTRS { USB0 } |
AnnaBridge | 171:3a7713b1edbc | 15098 | /** Interrupt vectors for the USB peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 15099 | #define USB_IRQS { USB0_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 15100 | |
AnnaBridge | 171:3a7713b1edbc | 15101 | /*! |
AnnaBridge | 171:3a7713b1edbc | 15102 | * @} |
AnnaBridge | 171:3a7713b1edbc | 15103 | */ /* end of group USB_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 15104 | |
AnnaBridge | 171:3a7713b1edbc | 15105 | |
AnnaBridge | 171:3a7713b1edbc | 15106 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 15107 | -- USBDCD Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 15108 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 15109 | |
AnnaBridge | 171:3a7713b1edbc | 15110 | /*! |
AnnaBridge | 171:3a7713b1edbc | 15111 | * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 15112 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 15113 | */ |
AnnaBridge | 171:3a7713b1edbc | 15114 | |
AnnaBridge | 171:3a7713b1edbc | 15115 | /** USBDCD - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 15116 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 15117 | __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 15118 | __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 15119 | __I uint32_t STATUS; /**< Status register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 15120 | __IO uint32_t SIGNAL_OVERRIDE; /**< Signal Override Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 15121 | __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 15122 | __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 15123 | union { /* offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 15124 | __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 15125 | __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 15126 | }; |
AnnaBridge | 171:3a7713b1edbc | 15127 | } USBDCD_Type; |
AnnaBridge | 171:3a7713b1edbc | 15128 | |
AnnaBridge | 171:3a7713b1edbc | 15129 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 15130 | -- USBDCD Register Masks |
AnnaBridge | 171:3a7713b1edbc | 15131 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 15132 | |
AnnaBridge | 171:3a7713b1edbc | 15133 | /*! |
AnnaBridge | 171:3a7713b1edbc | 15134 | * @addtogroup USBDCD_Register_Masks USBDCD Register Masks |
AnnaBridge | 171:3a7713b1edbc | 15135 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 15136 | */ |
AnnaBridge | 171:3a7713b1edbc | 15137 | |
AnnaBridge | 171:3a7713b1edbc | 15138 | /*! @name CONTROL - Control register */ |
AnnaBridge | 171:3a7713b1edbc | 15139 | #define USBDCD_CONTROL_IACK_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 15140 | #define USBDCD_CONTROL_IACK_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15141 | #define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15142 | #define USBDCD_CONTROL_IF_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 15143 | #define USBDCD_CONTROL_IF_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 15144 | #define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15145 | #define USBDCD_CONTROL_IE_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 15146 | #define USBDCD_CONTROL_IE_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 15147 | #define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15148 | #define USBDCD_CONTROL_BC12_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 15149 | #define USBDCD_CONTROL_BC12_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 15150 | #define USBDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15151 | #define USBDCD_CONTROL_START_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 15152 | #define USBDCD_CONTROL_START_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 15153 | #define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15154 | #define USBDCD_CONTROL_SR_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 15155 | #define USBDCD_CONTROL_SR_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 15156 | #define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15157 | |
AnnaBridge | 171:3a7713b1edbc | 15158 | /*! @name CLOCK - Clock register */ |
AnnaBridge | 171:3a7713b1edbc | 15159 | #define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 15160 | #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15161 | #define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15162 | #define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU) |
AnnaBridge | 171:3a7713b1edbc | 15163 | #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 15164 | #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15165 | |
AnnaBridge | 171:3a7713b1edbc | 15166 | /*! @name STATUS - Status register */ |
AnnaBridge | 171:3a7713b1edbc | 15167 | #define USBDCD_STATUS_SEQ_RES_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 15168 | #define USBDCD_STATUS_SEQ_RES_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 15169 | #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15170 | #define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U) |
AnnaBridge | 171:3a7713b1edbc | 15171 | #define USBDCD_STATUS_SEQ_STAT_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 15172 | #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15173 | #define USBDCD_STATUS_ERR_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 15174 | #define USBDCD_STATUS_ERR_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 15175 | #define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15176 | #define USBDCD_STATUS_TO_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 15177 | #define USBDCD_STATUS_TO_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 15178 | #define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15179 | #define USBDCD_STATUS_ACTIVE_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 15180 | #define USBDCD_STATUS_ACTIVE_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 15181 | #define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15182 | |
AnnaBridge | 171:3a7713b1edbc | 15183 | /*! @name SIGNAL_OVERRIDE - Signal Override Register */ |
AnnaBridge | 171:3a7713b1edbc | 15184 | #define USBDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 15185 | #define USBDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15186 | #define USBDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBDCD_SIGNAL_OVERRIDE_PS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15187 | |
AnnaBridge | 171:3a7713b1edbc | 15188 | /*! @name TIMER0 - TIMER0 register */ |
AnnaBridge | 171:3a7713b1edbc | 15189 | #define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU) |
AnnaBridge | 171:3a7713b1edbc | 15190 | #define USBDCD_TIMER0_TUNITCON_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15191 | #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15192 | #define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U) |
AnnaBridge | 171:3a7713b1edbc | 15193 | #define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 15194 | #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15195 | |
AnnaBridge | 171:3a7713b1edbc | 15196 | /*! @name TIMER1 - TIMER1 register */ |
AnnaBridge | 171:3a7713b1edbc | 15197 | #define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU) |
AnnaBridge | 171:3a7713b1edbc | 15198 | #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15199 | #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15200 | #define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U) |
AnnaBridge | 171:3a7713b1edbc | 15201 | #define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 15202 | #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15203 | |
AnnaBridge | 171:3a7713b1edbc | 15204 | /*! @name TIMER2_BC11 - TIMER2_BC11 register */ |
AnnaBridge | 171:3a7713b1edbc | 15205 | #define USBDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 15206 | #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15207 | #define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15208 | #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U) |
AnnaBridge | 171:3a7713b1edbc | 15209 | #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 15210 | #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15211 | |
AnnaBridge | 171:3a7713b1edbc | 15212 | /*! @name TIMER2_BC12 - TIMER2_BC12 register */ |
AnnaBridge | 171:3a7713b1edbc | 15213 | #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU) |
AnnaBridge | 171:3a7713b1edbc | 15214 | #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15215 | #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15216 | #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U) |
AnnaBridge | 171:3a7713b1edbc | 15217 | #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 15218 | #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15219 | |
AnnaBridge | 171:3a7713b1edbc | 15220 | |
AnnaBridge | 171:3a7713b1edbc | 15221 | /*! |
AnnaBridge | 171:3a7713b1edbc | 15222 | * @} |
AnnaBridge | 171:3a7713b1edbc | 15223 | */ /* end of group USBDCD_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 15224 | |
AnnaBridge | 171:3a7713b1edbc | 15225 | |
AnnaBridge | 171:3a7713b1edbc | 15226 | /* USBDCD - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 15227 | /** Peripheral USBDCD base address */ |
AnnaBridge | 171:3a7713b1edbc | 15228 | #define USBDCD_BASE (0x40035000u) |
AnnaBridge | 171:3a7713b1edbc | 15229 | /** Peripheral USBDCD base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 15230 | #define USBDCD ((USBDCD_Type *)USBDCD_BASE) |
AnnaBridge | 171:3a7713b1edbc | 15231 | /** Array initializer of USBDCD peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 15232 | #define USBDCD_BASE_ADDRS { USBDCD_BASE } |
AnnaBridge | 171:3a7713b1edbc | 15233 | /** Array initializer of USBDCD peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 15234 | #define USBDCD_BASE_PTRS { USBDCD } |
AnnaBridge | 171:3a7713b1edbc | 15235 | /** Interrupt vectors for the USBDCD peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 15236 | #define USBDCD_IRQS { USBDCD_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 15237 | |
AnnaBridge | 171:3a7713b1edbc | 15238 | /*! |
AnnaBridge | 171:3a7713b1edbc | 15239 | * @} |
AnnaBridge | 171:3a7713b1edbc | 15240 | */ /* end of group USBDCD_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 15241 | |
AnnaBridge | 171:3a7713b1edbc | 15242 | |
AnnaBridge | 171:3a7713b1edbc | 15243 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 15244 | -- VREF Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 15245 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 15246 | |
AnnaBridge | 171:3a7713b1edbc | 15247 | /*! |
AnnaBridge | 171:3a7713b1edbc | 15248 | * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 15249 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 15250 | */ |
AnnaBridge | 171:3a7713b1edbc | 15251 | |
AnnaBridge | 171:3a7713b1edbc | 15252 | /** VREF - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 15253 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 15254 | __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 15255 | __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 15256 | } VREF_Type; |
AnnaBridge | 171:3a7713b1edbc | 15257 | |
AnnaBridge | 171:3a7713b1edbc | 15258 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 15259 | -- VREF Register Masks |
AnnaBridge | 171:3a7713b1edbc | 15260 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 15261 | |
AnnaBridge | 171:3a7713b1edbc | 15262 | /*! |
AnnaBridge | 171:3a7713b1edbc | 15263 | * @addtogroup VREF_Register_Masks VREF Register Masks |
AnnaBridge | 171:3a7713b1edbc | 15264 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 15265 | */ |
AnnaBridge | 171:3a7713b1edbc | 15266 | |
AnnaBridge | 171:3a7713b1edbc | 15267 | /*! @name TRM - VREF Trim Register */ |
AnnaBridge | 171:3a7713b1edbc | 15268 | #define VREF_TRM_TRIM_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 15269 | #define VREF_TRM_TRIM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15270 | #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15271 | #define VREF_TRM_CHOPEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 15272 | #define VREF_TRM_CHOPEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 15273 | #define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15274 | |
AnnaBridge | 171:3a7713b1edbc | 15275 | /*! @name SC - VREF Status and Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 15276 | #define VREF_SC_MODE_LV_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 15277 | #define VREF_SC_MODE_LV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15278 | #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15279 | #define VREF_SC_VREFST_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 15280 | #define VREF_SC_VREFST_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 15281 | #define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15282 | #define VREF_SC_ICOMPEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 15283 | #define VREF_SC_ICOMPEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 15284 | #define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15285 | #define VREF_SC_REGEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 15286 | #define VREF_SC_REGEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 15287 | #define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15288 | #define VREF_SC_VREFEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 15289 | #define VREF_SC_VREFEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 15290 | #define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15291 | |
AnnaBridge | 171:3a7713b1edbc | 15292 | |
AnnaBridge | 171:3a7713b1edbc | 15293 | /*! |
AnnaBridge | 171:3a7713b1edbc | 15294 | * @} |
AnnaBridge | 171:3a7713b1edbc | 15295 | */ /* end of group VREF_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 15296 | |
AnnaBridge | 171:3a7713b1edbc | 15297 | |
AnnaBridge | 171:3a7713b1edbc | 15298 | /* VREF - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 15299 | /** Peripheral VREF base address */ |
AnnaBridge | 171:3a7713b1edbc | 15300 | #define VREF_BASE (0x40074000u) |
AnnaBridge | 171:3a7713b1edbc | 15301 | /** Peripheral VREF base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 15302 | #define VREF ((VREF_Type *)VREF_BASE) |
AnnaBridge | 171:3a7713b1edbc | 15303 | /** Array initializer of VREF peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 15304 | #define VREF_BASE_ADDRS { VREF_BASE } |
AnnaBridge | 171:3a7713b1edbc | 15305 | /** Array initializer of VREF peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 15306 | #define VREF_BASE_PTRS { VREF } |
AnnaBridge | 171:3a7713b1edbc | 15307 | |
AnnaBridge | 171:3a7713b1edbc | 15308 | /*! |
AnnaBridge | 171:3a7713b1edbc | 15309 | * @} |
AnnaBridge | 171:3a7713b1edbc | 15310 | */ /* end of group VREF_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 15311 | |
AnnaBridge | 171:3a7713b1edbc | 15312 | |
AnnaBridge | 171:3a7713b1edbc | 15313 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 15314 | -- WDOG Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 15315 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 15316 | |
AnnaBridge | 171:3a7713b1edbc | 15317 | /*! |
AnnaBridge | 171:3a7713b1edbc | 15318 | * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 15319 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 15320 | */ |
AnnaBridge | 171:3a7713b1edbc | 15321 | |
AnnaBridge | 171:3a7713b1edbc | 15322 | /** WDOG - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 15323 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 15324 | __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 15325 | __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 15326 | __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 15327 | __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */ |
AnnaBridge | 171:3a7713b1edbc | 15328 | __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 15329 | __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */ |
AnnaBridge | 171:3a7713b1edbc | 15330 | __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 15331 | __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */ |
AnnaBridge | 171:3a7713b1edbc | 15332 | __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 15333 | __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */ |
AnnaBridge | 171:3a7713b1edbc | 15334 | __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 15335 | __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */ |
AnnaBridge | 171:3a7713b1edbc | 15336 | } WDOG_Type; |
AnnaBridge | 171:3a7713b1edbc | 15337 | |
AnnaBridge | 171:3a7713b1edbc | 15338 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 15339 | -- WDOG Register Masks |
AnnaBridge | 171:3a7713b1edbc | 15340 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 15341 | |
AnnaBridge | 171:3a7713b1edbc | 15342 | /*! |
AnnaBridge | 171:3a7713b1edbc | 15343 | * @addtogroup WDOG_Register_Masks WDOG Register Masks |
AnnaBridge | 171:3a7713b1edbc | 15344 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 15345 | */ |
AnnaBridge | 171:3a7713b1edbc | 15346 | |
AnnaBridge | 171:3a7713b1edbc | 15347 | /*! @name STCTRLH - Watchdog Status and Control Register High */ |
AnnaBridge | 171:3a7713b1edbc | 15348 | #define WDOG_STCTRLH_WDOGEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 15349 | #define WDOG_STCTRLH_WDOGEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15350 | #define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15351 | #define WDOG_STCTRLH_CLKSRC_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 15352 | #define WDOG_STCTRLH_CLKSRC_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 15353 | #define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15354 | #define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 15355 | #define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 15356 | #define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15357 | #define WDOG_STCTRLH_WINEN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 15358 | #define WDOG_STCTRLH_WINEN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 15359 | #define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15360 | #define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 15361 | #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 15362 | #define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15363 | #define WDOG_STCTRLH_DBGEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 15364 | #define WDOG_STCTRLH_DBGEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 15365 | #define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15366 | #define WDOG_STCTRLH_STOPEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 15367 | #define WDOG_STCTRLH_STOPEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 15368 | #define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15369 | #define WDOG_STCTRLH_WAITEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 15370 | #define WDOG_STCTRLH_WAITEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 15371 | #define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15372 | #define WDOG_STCTRLH_TESTWDOG_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 15373 | #define WDOG_STCTRLH_TESTWDOG_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 15374 | #define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15375 | #define WDOG_STCTRLH_TESTSEL_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 15376 | #define WDOG_STCTRLH_TESTSEL_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 15377 | #define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15378 | #define WDOG_STCTRLH_BYTESEL_MASK (0x3000U) |
AnnaBridge | 171:3a7713b1edbc | 15379 | #define WDOG_STCTRLH_BYTESEL_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 15380 | #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15381 | #define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 15382 | #define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 15383 | #define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15384 | |
AnnaBridge | 171:3a7713b1edbc | 15385 | /*! @name STCTRLL - Watchdog Status and Control Register Low */ |
AnnaBridge | 171:3a7713b1edbc | 15386 | #define WDOG_STCTRLL_INTFLG_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 15387 | #define WDOG_STCTRLL_INTFLG_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 15388 | #define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15389 | |
AnnaBridge | 171:3a7713b1edbc | 15390 | /*! @name TOVALH - Watchdog Time-out Value Register High */ |
AnnaBridge | 171:3a7713b1edbc | 15391 | #define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 15392 | #define WDOG_TOVALH_TOVALHIGH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15393 | #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15394 | |
AnnaBridge | 171:3a7713b1edbc | 15395 | /*! @name TOVALL - Watchdog Time-out Value Register Low */ |
AnnaBridge | 171:3a7713b1edbc | 15396 | #define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 15397 | #define WDOG_TOVALL_TOVALLOW_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15398 | #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15399 | |
AnnaBridge | 171:3a7713b1edbc | 15400 | /*! @name WINH - Watchdog Window Register High */ |
AnnaBridge | 171:3a7713b1edbc | 15401 | #define WDOG_WINH_WINHIGH_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 15402 | #define WDOG_WINH_WINHIGH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15403 | #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15404 | |
AnnaBridge | 171:3a7713b1edbc | 15405 | /*! @name WINL - Watchdog Window Register Low */ |
AnnaBridge | 171:3a7713b1edbc | 15406 | #define WDOG_WINL_WINLOW_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 15407 | #define WDOG_WINL_WINLOW_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15408 | #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15409 | |
AnnaBridge | 171:3a7713b1edbc | 15410 | /*! @name REFRESH - Watchdog Refresh register */ |
AnnaBridge | 171:3a7713b1edbc | 15411 | #define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 15412 | #define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15413 | #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15414 | |
AnnaBridge | 171:3a7713b1edbc | 15415 | /*! @name UNLOCK - Watchdog Unlock register */ |
AnnaBridge | 171:3a7713b1edbc | 15416 | #define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 15417 | #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15418 | #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15419 | |
AnnaBridge | 171:3a7713b1edbc | 15420 | /*! @name TMROUTH - Watchdog Timer Output Register High */ |
AnnaBridge | 171:3a7713b1edbc | 15421 | #define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 15422 | #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15423 | #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15424 | |
AnnaBridge | 171:3a7713b1edbc | 15425 | /*! @name TMROUTL - Watchdog Timer Output Register Low */ |
AnnaBridge | 171:3a7713b1edbc | 15426 | #define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 15427 | #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15428 | #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15429 | |
AnnaBridge | 171:3a7713b1edbc | 15430 | /*! @name RSTCNT - Watchdog Reset Count register */ |
AnnaBridge | 171:3a7713b1edbc | 15431 | #define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 15432 | #define WDOG_RSTCNT_RSTCNT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 15433 | #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15434 | |
AnnaBridge | 171:3a7713b1edbc | 15435 | /*! @name PRESC - Watchdog Prescaler register */ |
AnnaBridge | 171:3a7713b1edbc | 15436 | #define WDOG_PRESC_PRESCVAL_MASK (0x700U) |
AnnaBridge | 171:3a7713b1edbc | 15437 | #define WDOG_PRESC_PRESCVAL_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 15438 | #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 15439 | |
AnnaBridge | 171:3a7713b1edbc | 15440 | |
AnnaBridge | 171:3a7713b1edbc | 15441 | /*! |
AnnaBridge | 171:3a7713b1edbc | 15442 | * @} |
AnnaBridge | 171:3a7713b1edbc | 15443 | */ /* end of group WDOG_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 15444 | |
AnnaBridge | 171:3a7713b1edbc | 15445 | |
AnnaBridge | 171:3a7713b1edbc | 15446 | /* WDOG - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 15447 | /** Peripheral WDOG base address */ |
AnnaBridge | 171:3a7713b1edbc | 15448 | #define WDOG_BASE (0x40052000u) |
AnnaBridge | 171:3a7713b1edbc | 15449 | /** Peripheral WDOG base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 15450 | #define WDOG ((WDOG_Type *)WDOG_BASE) |
AnnaBridge | 171:3a7713b1edbc | 15451 | /** Array initializer of WDOG peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 15452 | #define WDOG_BASE_ADDRS { WDOG_BASE } |
AnnaBridge | 171:3a7713b1edbc | 15453 | /** Array initializer of WDOG peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 15454 | #define WDOG_BASE_PTRS { WDOG } |
AnnaBridge | 171:3a7713b1edbc | 15455 | /** Interrupt vectors for the WDOG peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 15456 | #define WDOG_IRQS { WDOG_EWM_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 15457 | |
AnnaBridge | 171:3a7713b1edbc | 15458 | /*! |
AnnaBridge | 171:3a7713b1edbc | 15459 | * @} |
AnnaBridge | 171:3a7713b1edbc | 15460 | */ /* end of group WDOG_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 15461 | |
AnnaBridge | 171:3a7713b1edbc | 15462 | |
AnnaBridge | 171:3a7713b1edbc | 15463 | /* |
AnnaBridge | 171:3a7713b1edbc | 15464 | ** End of section using anonymous unions |
AnnaBridge | 171:3a7713b1edbc | 15465 | */ |
AnnaBridge | 171:3a7713b1edbc | 15466 | |
AnnaBridge | 171:3a7713b1edbc | 15467 | #if defined(__ARMCC_VERSION) |
AnnaBridge | 171:3a7713b1edbc | 15468 | #pragma pop |
AnnaBridge | 171:3a7713b1edbc | 15469 | #elif defined(__CWCC__) |
AnnaBridge | 171:3a7713b1edbc | 15470 | #pragma pop |
AnnaBridge | 171:3a7713b1edbc | 15471 | #elif defined(__GNUC__) |
AnnaBridge | 171:3a7713b1edbc | 15472 | /* leave anonymous unions enabled */ |
AnnaBridge | 171:3a7713b1edbc | 15473 | #elif defined(__IAR_SYSTEMS_ICC__) |
AnnaBridge | 171:3a7713b1edbc | 15474 | #pragma language=default |
AnnaBridge | 171:3a7713b1edbc | 15475 | #else |
AnnaBridge | 171:3a7713b1edbc | 15476 | #error Not supported compiler type |
AnnaBridge | 171:3a7713b1edbc | 15477 | #endif |
AnnaBridge | 171:3a7713b1edbc | 15478 | |
AnnaBridge | 171:3a7713b1edbc | 15479 | /*! |
AnnaBridge | 171:3a7713b1edbc | 15480 | * @} |
AnnaBridge | 171:3a7713b1edbc | 15481 | */ /* end of group Peripheral_access_layer */ |
AnnaBridge | 171:3a7713b1edbc | 15482 | |
AnnaBridge | 171:3a7713b1edbc | 15483 | |
AnnaBridge | 171:3a7713b1edbc | 15484 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 15485 | -- SDK Compatibility |
AnnaBridge | 171:3a7713b1edbc | 15486 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 15487 | |
AnnaBridge | 171:3a7713b1edbc | 15488 | /*! |
AnnaBridge | 171:3a7713b1edbc | 15489 | * @addtogroup SDK_Compatibility_Symbols SDK Compatibility |
AnnaBridge | 171:3a7713b1edbc | 15490 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 15491 | */ |
AnnaBridge | 171:3a7713b1edbc | 15492 | |
AnnaBridge | 171:3a7713b1edbc | 15493 | #define PIT0_IRQn PIT0CH0_IRQn |
AnnaBridge | 171:3a7713b1edbc | 15494 | #define PIT1_IRQn PIT0CH1_IRQn |
AnnaBridge | 171:3a7713b1edbc | 15495 | #define PIT2_IRQn PIT0CH2_IRQn |
AnnaBridge | 171:3a7713b1edbc | 15496 | #define PIT3_IRQn PIT0CH3_IRQn |
AnnaBridge | 171:3a7713b1edbc | 15497 | #define PIT_BASE PIT0_BASE |
AnnaBridge | 171:3a7713b1edbc | 15498 | #define PIT PIT0 |
AnnaBridge | 171:3a7713b1edbc | 15499 | #define PIT_MCR PIT0_MCR |
AnnaBridge | 171:3a7713b1edbc | 15500 | #define PIT_LDVAL0 PIT0_LDVAL0 |
AnnaBridge | 171:3a7713b1edbc | 15501 | #define PIT_CVAL0 PIT0_CVAL0 |
AnnaBridge | 171:3a7713b1edbc | 15502 | #define PIT_TCTRL0 PIT0_TCTRL0 |
AnnaBridge | 171:3a7713b1edbc | 15503 | #define PIT_TFLG0 PIT0_TFLG0 |
AnnaBridge | 171:3a7713b1edbc | 15504 | #define PIT_LDVAL1 PIT0_LDVAL1 |
AnnaBridge | 171:3a7713b1edbc | 15505 | #define PIT_CVAL1 PIT0_CVAL1 |
AnnaBridge | 171:3a7713b1edbc | 15506 | #define PIT_TCTRL1 PIT0_TCTRL1 |
AnnaBridge | 171:3a7713b1edbc | 15507 | #define PIT_TFLG1 PIT0_TFLG1 |
AnnaBridge | 171:3a7713b1edbc | 15508 | #define PIT_LDVAL2 PIT0_LDVAL2 |
AnnaBridge | 171:3a7713b1edbc | 15509 | #define PIT_CVAL2 PIT0_CVAL2 |
AnnaBridge | 171:3a7713b1edbc | 15510 | #define PIT_TCTRL2 PIT0_TCTRL2 |
AnnaBridge | 171:3a7713b1edbc | 15511 | #define PIT_TFLG2 PIT0_TFLG2 |
AnnaBridge | 171:3a7713b1edbc | 15512 | #define PIT_LDVAL3 PIT0_LDVAL3 |
AnnaBridge | 171:3a7713b1edbc | 15513 | #define PIT_CVAL3 PIT0_CVAL3 |
AnnaBridge | 171:3a7713b1edbc | 15514 | #define PIT_TCTRL3 PIT0_TCTRL3 |
AnnaBridge | 171:3a7713b1edbc | 15515 | #define PIT_TFLG3 PIT0_TFLG3 |
AnnaBridge | 171:3a7713b1edbc | 15516 | #define PIT_LDVAL(index) PIT0_LDVAL(index) |
AnnaBridge | 171:3a7713b1edbc | 15517 | #define PIT_CVAL(index) PIT0_CVAL(index) |
AnnaBridge | 171:3a7713b1edbc | 15518 | #define PIT_TCTRL(index) PIT0_TCTRL(index) |
AnnaBridge | 171:3a7713b1edbc | 15519 | #define PIT_TFLG(index) PIT0_TFLG(index) |
AnnaBridge | 171:3a7713b1edbc | 15520 | #define PIT0_IRQHandler PIT0CH0_IRQHandler |
AnnaBridge | 171:3a7713b1edbc | 15521 | #define PIT1_IRQHandler PIT0CH1_IRQHandler |
AnnaBridge | 171:3a7713b1edbc | 15522 | #define PIT2_IRQHandler PIT0CH2_IRQHandler |
AnnaBridge | 171:3a7713b1edbc | 15523 | #define PIT3_IRQHandler PIT0CH3_IRQHandler |
AnnaBridge | 171:3a7713b1edbc | 15524 | #define DSPI0 SPI0 |
AnnaBridge | 171:3a7713b1edbc | 15525 | #define DSPI1 SPI1 |
AnnaBridge | 171:3a7713b1edbc | 15526 | #define DSPI2 SPI2 |
AnnaBridge | 171:3a7713b1edbc | 15527 | #define DMAMUX0 DMAMUX |
AnnaBridge | 171:3a7713b1edbc | 15528 | |
AnnaBridge | 171:3a7713b1edbc | 15529 | /*! |
AnnaBridge | 171:3a7713b1edbc | 15530 | * @} |
AnnaBridge | 171:3a7713b1edbc | 15531 | */ /* end of group SDK_Compatibility_Symbols */ |
AnnaBridge | 171:3a7713b1edbc | 15532 | |
AnnaBridge | 171:3a7713b1edbc | 15533 | |
AnnaBridge | 171:3a7713b1edbc | 15534 | #endif /* _MK82F25615_H_ */ |
AnnaBridge | 171:3a7713b1edbc | 15535 |