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TARGET_EFM32ZG_STK3200/TOOLCHAIN_IAR/efm32zg222f32.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file efm32zg222f32.h
AnnaBridge 171:3a7713b1edbc 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
AnnaBridge 171:3a7713b1edbc 4 * for EFM32ZG222F32
AnnaBridge 171:3a7713b1edbc 5 * @version 5.1.2
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @section License
AnnaBridge 171:3a7713b1edbc 8 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 171:3a7713b1edbc 9 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 171:3a7713b1edbc 12 * including commercial applications, and to alter it and redistribute it
AnnaBridge 171:3a7713b1edbc 13 * freely, subject to the following restrictions:
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 171:3a7713b1edbc 16 * claim that you wrote the original software.@n
AnnaBridge 171:3a7713b1edbc 17 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 171:3a7713b1edbc 18 * misrepresented as being the original software.@n
AnnaBridge 171:3a7713b1edbc 19 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 171:3a7713b1edbc 20 *
AnnaBridge 171:3a7713b1edbc 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 171:3a7713b1edbc 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 171:3a7713b1edbc 23 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 171:3a7713b1edbc 24 * kind, including, but not limited to, any implied warranties of
AnnaBridge 171:3a7713b1edbc 25 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 171:3a7713b1edbc 26 * infringement of any proprietary rights of a third party.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 171:3a7713b1edbc 29 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 171:3a7713b1edbc 30 * any third party, arising from your use of this Software.
AnnaBridge 171:3a7713b1edbc 31 *
AnnaBridge 171:3a7713b1edbc 32 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #ifndef EFM32ZG222F32_H
AnnaBridge 171:3a7713b1edbc 35 #define EFM32ZG222F32_H
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 38 extern "C" {
AnnaBridge 171:3a7713b1edbc 39 #endif
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 42 * @addtogroup Parts
AnnaBridge 171:3a7713b1edbc 43 * @{
AnnaBridge 171:3a7713b1edbc 44 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 47 * @defgroup EFM32ZG222F32 EFM32ZG222F32
AnnaBridge 171:3a7713b1edbc 48 * @{
AnnaBridge 171:3a7713b1edbc 49 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 /** Interrupt Number Definition */
AnnaBridge 171:3a7713b1edbc 52 typedef enum IRQn
AnnaBridge 171:3a7713b1edbc 53 {
AnnaBridge 171:3a7713b1edbc 54 /****** Cortex-M0+ Processor Exceptions Numbers *****************************************/
AnnaBridge 171:3a7713b1edbc 55 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M0+ Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 56 HardFault_IRQn = -13, /*!< -13 Cortex-M0+ Hard Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 57 SVCall_IRQn = -5, /*!< -5 Cortex-M0+ SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 58 PendSV_IRQn = -2, /*!< -2 Cortex-M0+ Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 59 SysTick_IRQn = -1, /*!< -1 Cortex-M0+ System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 60
AnnaBridge 171:3a7713b1edbc 61 /****** EFM32ZG Peripheral Interrupt Numbers ********************************************/
AnnaBridge 171:3a7713b1edbc 62 DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
AnnaBridge 171:3a7713b1edbc 63 GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
AnnaBridge 171:3a7713b1edbc 64 TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
AnnaBridge 171:3a7713b1edbc 65 ACMP0_IRQn = 3, /*!< 3 EFM32 ACMP0 Interrupt */
AnnaBridge 171:3a7713b1edbc 66 ADC0_IRQn = 4, /*!< 4 EFM32 ADC0 Interrupt */
AnnaBridge 171:3a7713b1edbc 67 I2C0_IRQn = 5, /*!< 5 EFM32 I2C0 Interrupt */
AnnaBridge 171:3a7713b1edbc 68 GPIO_ODD_IRQn = 6, /*!< 6 EFM32 GPIO_ODD Interrupt */
AnnaBridge 171:3a7713b1edbc 69 TIMER1_IRQn = 7, /*!< 7 EFM32 TIMER1 Interrupt */
AnnaBridge 171:3a7713b1edbc 70 USART1_RX_IRQn = 8, /*!< 8 EFM32 USART1_RX Interrupt */
AnnaBridge 171:3a7713b1edbc 71 USART1_TX_IRQn = 9, /*!< 9 EFM32 USART1_TX Interrupt */
AnnaBridge 171:3a7713b1edbc 72 LEUART0_IRQn = 10, /*!< 10 EFM32 LEUART0 Interrupt */
AnnaBridge 171:3a7713b1edbc 73 PCNT0_IRQn = 11, /*!< 11 EFM32 PCNT0 Interrupt */
AnnaBridge 171:3a7713b1edbc 74 RTC_IRQn = 12, /*!< 12 EFM32 RTC Interrupt */
AnnaBridge 171:3a7713b1edbc 75 CMU_IRQn = 13, /*!< 13 EFM32 CMU Interrupt */
AnnaBridge 171:3a7713b1edbc 76 VCMP_IRQn = 14, /*!< 14 EFM32 VCMP Interrupt */
AnnaBridge 171:3a7713b1edbc 77 MSC_IRQn = 15, /*!< 15 EFM32 MSC Interrupt */
AnnaBridge 171:3a7713b1edbc 78 AES_IRQn = 16, /*!< 16 EFM32 AES Interrupt */
AnnaBridge 171:3a7713b1edbc 79 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 80
AnnaBridge 171:3a7713b1edbc 81 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 82 * @defgroup EFM32ZG222F32_Core EFM32ZG222F32 Core
AnnaBridge 171:3a7713b1edbc 83 * @{
AnnaBridge 171:3a7713b1edbc 84 * @brief Processor and Core Peripheral Section
AnnaBridge 171:3a7713b1edbc 85 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 86 #define __MPU_PRESENT 0 /**< MPU not present */
AnnaBridge 171:3a7713b1edbc 87 #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
AnnaBridge 171:3a7713b1edbc 88 #define __NVIC_PRIO_BITS 2 /**< NVIC interrupt priority bits */
AnnaBridge 171:3a7713b1edbc 89 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
AnnaBridge 171:3a7713b1edbc 90
AnnaBridge 171:3a7713b1edbc 91 /** @} End of group EFM32ZG222F32_Core */
AnnaBridge 171:3a7713b1edbc 92
AnnaBridge 171:3a7713b1edbc 93 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 94 * @defgroup EFM32ZG222F32_Part EFM32ZG222F32 Part
AnnaBridge 171:3a7713b1edbc 95 * @{
AnnaBridge 171:3a7713b1edbc 96 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 97
AnnaBridge 171:3a7713b1edbc 98 /** Part family */
AnnaBridge 171:3a7713b1edbc 99 #define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */
AnnaBridge 171:3a7713b1edbc 100 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
AnnaBridge 171:3a7713b1edbc 101 #define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
AnnaBridge 171:3a7713b1edbc 102 #define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
AnnaBridge 171:3a7713b1edbc 103 #define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */
AnnaBridge 171:3a7713b1edbc 104 #define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */
AnnaBridge 171:3a7713b1edbc 105 #define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */
AnnaBridge 171:3a7713b1edbc 106 #define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */
AnnaBridge 171:3a7713b1edbc 107
AnnaBridge 171:3a7713b1edbc 108 /* If part number is not defined as compiler option, define it */
AnnaBridge 171:3a7713b1edbc 109 #if !defined(EFM32ZG222F32)
AnnaBridge 171:3a7713b1edbc 110 #define EFM32ZG222F32 1 /**< Zero Gecko Part */
AnnaBridge 171:3a7713b1edbc 111 #endif
AnnaBridge 171:3a7713b1edbc 112
AnnaBridge 171:3a7713b1edbc 113 /** Configure part number */
AnnaBridge 171:3a7713b1edbc 114 #define PART_NUMBER "EFM32ZG222F32" /**< Part Number */
AnnaBridge 171:3a7713b1edbc 115
AnnaBridge 171:3a7713b1edbc 116 /** Memory Base addresses and limits */
AnnaBridge 171:3a7713b1edbc 117 #define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
AnnaBridge 171:3a7713b1edbc 118 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
AnnaBridge 171:3a7713b1edbc 119 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
AnnaBridge 171:3a7713b1edbc 120 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
AnnaBridge 171:3a7713b1edbc 121 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
AnnaBridge 171:3a7713b1edbc 122 #define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
AnnaBridge 171:3a7713b1edbc 123 #define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
AnnaBridge 171:3a7713b1edbc 124 #define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
AnnaBridge 171:3a7713b1edbc 125 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
AnnaBridge 171:3a7713b1edbc 126 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
AnnaBridge 171:3a7713b1edbc 127 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
AnnaBridge 171:3a7713b1edbc 128 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
AnnaBridge 171:3a7713b1edbc 129 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
AnnaBridge 171:3a7713b1edbc 130 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
AnnaBridge 171:3a7713b1edbc 131 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
AnnaBridge 171:3a7713b1edbc 132 #define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
AnnaBridge 171:3a7713b1edbc 133 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
AnnaBridge 171:3a7713b1edbc 134 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
AnnaBridge 171:3a7713b1edbc 135 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
AnnaBridge 171:3a7713b1edbc 136 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
AnnaBridge 171:3a7713b1edbc 137
AnnaBridge 171:3a7713b1edbc 138 /** Flash and SRAM limits for EFM32ZG222F32 */
AnnaBridge 171:3a7713b1edbc 139 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
AnnaBridge 171:3a7713b1edbc 140 #define FLASH_SIZE (0x00008000UL) /**< Available Flash Memory */
AnnaBridge 171:3a7713b1edbc 141 #define FLASH_PAGE_SIZE 1024 /**< Flash Memory page size */
AnnaBridge 171:3a7713b1edbc 142 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
AnnaBridge 171:3a7713b1edbc 143 #define SRAM_SIZE (0x00001000UL) /**< Available SRAM Memory */
AnnaBridge 171:3a7713b1edbc 144 #define __CM0PLUS_REV 0x001 /**< Cortex-M0+ Core revision r0p1 */
AnnaBridge 171:3a7713b1edbc 145 #define PRS_CHAN_COUNT 4 /**< Number of PRS channels */
AnnaBridge 171:3a7713b1edbc 146 #define DMA_CHAN_COUNT 4 /**< Number of DMA channels */
AnnaBridge 171:3a7713b1edbc 147 #define EXT_IRQ_COUNT 19 /**< Number of External (NVIC) interrupts */
AnnaBridge 171:3a7713b1edbc 148
AnnaBridge 171:3a7713b1edbc 149 /** AF channels connect the different on-chip peripherals with the af-mux */
AnnaBridge 171:3a7713b1edbc 150 #define AFCHAN_MAX 33
AnnaBridge 171:3a7713b1edbc 151 #define AFCHANLOC_MAX 7
AnnaBridge 171:3a7713b1edbc 152 /** Analog AF channels */
AnnaBridge 171:3a7713b1edbc 153 #define AFACHAN_MAX 25
AnnaBridge 171:3a7713b1edbc 154
AnnaBridge 171:3a7713b1edbc 155 /* Part number capabilities */
AnnaBridge 171:3a7713b1edbc 156
AnnaBridge 171:3a7713b1edbc 157 #define TIMER_PRESENT /**< TIMER is available in this part */
AnnaBridge 171:3a7713b1edbc 158 #define TIMER_COUNT 2 /**< 2 TIMERs available */
AnnaBridge 171:3a7713b1edbc 159 #define ACMP_PRESENT /**< ACMP is available in this part */
AnnaBridge 171:3a7713b1edbc 160 #define ACMP_COUNT 1 /**< 1 ACMPs available */
AnnaBridge 171:3a7713b1edbc 161 #define USART_PRESENT /**< USART is available in this part */
AnnaBridge 171:3a7713b1edbc 162 #define USART_COUNT 1 /**< 1 USARTs available */
AnnaBridge 171:3a7713b1edbc 163 #define IDAC_PRESENT /**< IDAC is available in this part */
AnnaBridge 171:3a7713b1edbc 164 #define IDAC_COUNT 1 /**< 1 IDACs available */
AnnaBridge 171:3a7713b1edbc 165 #define ADC_PRESENT /**< ADC is available in this part */
AnnaBridge 171:3a7713b1edbc 166 #define ADC_COUNT 1 /**< 1 ADCs available */
AnnaBridge 171:3a7713b1edbc 167 #define LEUART_PRESENT /**< LEUART is available in this part */
AnnaBridge 171:3a7713b1edbc 168 #define LEUART_COUNT 1 /**< 1 LEUARTs available */
AnnaBridge 171:3a7713b1edbc 169 #define PCNT_PRESENT /**< PCNT is available in this part */
AnnaBridge 171:3a7713b1edbc 170 #define PCNT_COUNT 1 /**< 1 PCNTs available */
AnnaBridge 171:3a7713b1edbc 171 #define I2C_PRESENT /**< I2C is available in this part */
AnnaBridge 171:3a7713b1edbc 172 #define I2C_COUNT 1 /**< 1 I2Cs available */
AnnaBridge 171:3a7713b1edbc 173 #define AES_PRESENT
AnnaBridge 171:3a7713b1edbc 174 #define AES_COUNT 1
AnnaBridge 171:3a7713b1edbc 175 #define DMA_PRESENT
AnnaBridge 171:3a7713b1edbc 176 #define DMA_COUNT 1
AnnaBridge 171:3a7713b1edbc 177 #define LE_PRESENT
AnnaBridge 171:3a7713b1edbc 178 #define LE_COUNT 1
AnnaBridge 171:3a7713b1edbc 179 #define MSC_PRESENT
AnnaBridge 171:3a7713b1edbc 180 #define MSC_COUNT 1
AnnaBridge 171:3a7713b1edbc 181 #define EMU_PRESENT
AnnaBridge 171:3a7713b1edbc 182 #define EMU_COUNT 1
AnnaBridge 171:3a7713b1edbc 183 #define RMU_PRESENT
AnnaBridge 171:3a7713b1edbc 184 #define RMU_COUNT 1
AnnaBridge 171:3a7713b1edbc 185 #define CMU_PRESENT
AnnaBridge 171:3a7713b1edbc 186 #define CMU_COUNT 1
AnnaBridge 171:3a7713b1edbc 187 #define PRS_PRESENT
AnnaBridge 171:3a7713b1edbc 188 #define PRS_COUNT 1
AnnaBridge 171:3a7713b1edbc 189 #define GPIO_PRESENT
AnnaBridge 171:3a7713b1edbc 190 #define GPIO_COUNT 1
AnnaBridge 171:3a7713b1edbc 191 #define VCMP_PRESENT
AnnaBridge 171:3a7713b1edbc 192 #define VCMP_COUNT 1
AnnaBridge 171:3a7713b1edbc 193 #define RTC_PRESENT
AnnaBridge 171:3a7713b1edbc 194 #define RTC_COUNT 1
AnnaBridge 171:3a7713b1edbc 195 #define HFXTAL_PRESENT
AnnaBridge 171:3a7713b1edbc 196 #define HFXTAL_COUNT 1
AnnaBridge 171:3a7713b1edbc 197 #define LFXTAL_PRESENT
AnnaBridge 171:3a7713b1edbc 198 #define LFXTAL_COUNT 1
AnnaBridge 171:3a7713b1edbc 199 #define WDOG_PRESENT
AnnaBridge 171:3a7713b1edbc 200 #define WDOG_COUNT 1
AnnaBridge 171:3a7713b1edbc 201 #define DBG_PRESENT
AnnaBridge 171:3a7713b1edbc 202 #define DBG_COUNT 1
AnnaBridge 171:3a7713b1edbc 203 #define BOOTLOADER_PRESENT
AnnaBridge 171:3a7713b1edbc 204 #define BOOTLOADER_COUNT 1
AnnaBridge 171:3a7713b1edbc 205 #define ANALOG_PRESENT
AnnaBridge 171:3a7713b1edbc 206 #define ANALOG_COUNT 1
AnnaBridge 171:3a7713b1edbc 207
AnnaBridge 171:3a7713b1edbc 208 /** @} End of group EFM32ZG222F32_Part */
AnnaBridge 171:3a7713b1edbc 209
AnnaBridge 171:3a7713b1edbc 210 #define ARM_MATH_CM0PLUS
AnnaBridge 171:3a7713b1edbc 211 #include "arm_math.h" /* To get __CLZ definitions etc. */
AnnaBridge 171:3a7713b1edbc 212 #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
AnnaBridge 171:3a7713b1edbc 213 #include "system_efm32zg.h" /* System Header */
AnnaBridge 171:3a7713b1edbc 214
AnnaBridge 171:3a7713b1edbc 215 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 216 * @defgroup EFM32ZG222F32_Peripheral_TypeDefs EFM32ZG222F32 Peripheral TypeDefs
AnnaBridge 171:3a7713b1edbc 217 * @{
AnnaBridge 171:3a7713b1edbc 218 * @brief Device Specific Peripheral Register Structures
AnnaBridge 171:3a7713b1edbc 219 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 220
AnnaBridge 171:3a7713b1edbc 221 #include "efm32zg_aes.h"
AnnaBridge 171:3a7713b1edbc 222 #include "efm32zg_dma_ch.h"
AnnaBridge 171:3a7713b1edbc 223 #include "efm32zg_dma.h"
AnnaBridge 171:3a7713b1edbc 224 #include "efm32zg_msc.h"
AnnaBridge 171:3a7713b1edbc 225 #include "efm32zg_emu.h"
AnnaBridge 171:3a7713b1edbc 226 #include "efm32zg_rmu.h"
AnnaBridge 171:3a7713b1edbc 227 #include "efm32zg_cmu.h"
AnnaBridge 171:3a7713b1edbc 228 #include "efm32zg_timer_cc.h"
AnnaBridge 171:3a7713b1edbc 229 #include "efm32zg_timer.h"
AnnaBridge 171:3a7713b1edbc 230 #include "efm32zg_acmp.h"
AnnaBridge 171:3a7713b1edbc 231 #include "efm32zg_usart.h"
AnnaBridge 171:3a7713b1edbc 232 #include "efm32zg_prs_ch.h"
AnnaBridge 171:3a7713b1edbc 233 #include "efm32zg_prs.h"
AnnaBridge 171:3a7713b1edbc 234 #include "efm32zg_idac.h"
AnnaBridge 171:3a7713b1edbc 235 #include "efm32zg_gpio_p.h"
AnnaBridge 171:3a7713b1edbc 236 #include "efm32zg_gpio.h"
AnnaBridge 171:3a7713b1edbc 237 #include "efm32zg_vcmp.h"
AnnaBridge 171:3a7713b1edbc 238 #include "efm32zg_adc.h"
AnnaBridge 171:3a7713b1edbc 239 #include "efm32zg_leuart.h"
AnnaBridge 171:3a7713b1edbc 240 #include "efm32zg_pcnt.h"
AnnaBridge 171:3a7713b1edbc 241 #include "efm32zg_i2c.h"
AnnaBridge 171:3a7713b1edbc 242 #include "efm32zg_rtc.h"
AnnaBridge 171:3a7713b1edbc 243 #include "efm32zg_wdog.h"
AnnaBridge 171:3a7713b1edbc 244 #include "efm32zg_dma_descriptor.h"
AnnaBridge 171:3a7713b1edbc 245 #include "efm32zg_devinfo.h"
AnnaBridge 171:3a7713b1edbc 246 #include "efm32zg_romtable.h"
AnnaBridge 171:3a7713b1edbc 247 #include "efm32zg_calibrate.h"
AnnaBridge 171:3a7713b1edbc 248
AnnaBridge 171:3a7713b1edbc 249 /** @} End of group EFM32ZG222F32_Peripheral_TypeDefs */
AnnaBridge 171:3a7713b1edbc 250
AnnaBridge 171:3a7713b1edbc 251 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 252 * @defgroup EFM32ZG222F32_Peripheral_Base EFM32ZG222F32 Peripheral Memory Map
AnnaBridge 171:3a7713b1edbc 253 * @{
AnnaBridge 171:3a7713b1edbc 254 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 255
AnnaBridge 171:3a7713b1edbc 256 #define AES_BASE (0x400E0000UL) /**< AES base address */
AnnaBridge 171:3a7713b1edbc 257 #define DMA_BASE (0x400C2000UL) /**< DMA base address */
AnnaBridge 171:3a7713b1edbc 258 #define MSC_BASE (0x400C0000UL) /**< MSC base address */
AnnaBridge 171:3a7713b1edbc 259 #define EMU_BASE (0x400C6000UL) /**< EMU base address */
AnnaBridge 171:3a7713b1edbc 260 #define RMU_BASE (0x400CA000UL) /**< RMU base address */
AnnaBridge 171:3a7713b1edbc 261 #define CMU_BASE (0x400C8000UL) /**< CMU base address */
AnnaBridge 171:3a7713b1edbc 262 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
AnnaBridge 171:3a7713b1edbc 263 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
AnnaBridge 171:3a7713b1edbc 264 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
AnnaBridge 171:3a7713b1edbc 265 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */
AnnaBridge 171:3a7713b1edbc 266 #define PRS_BASE (0x400CC000UL) /**< PRS base address */
AnnaBridge 171:3a7713b1edbc 267 #define IDAC0_BASE (0x40004000UL) /**< IDAC0 base address */
AnnaBridge 171:3a7713b1edbc 268 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */
AnnaBridge 171:3a7713b1edbc 269 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */
AnnaBridge 171:3a7713b1edbc 270 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
AnnaBridge 171:3a7713b1edbc 271 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
AnnaBridge 171:3a7713b1edbc 272 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
AnnaBridge 171:3a7713b1edbc 273 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
AnnaBridge 171:3a7713b1edbc 274 #define RTC_BASE (0x40080000UL) /**< RTC base address */
AnnaBridge 171:3a7713b1edbc 275 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */
AnnaBridge 171:3a7713b1edbc 276 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
AnnaBridge 171:3a7713b1edbc 277 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
AnnaBridge 171:3a7713b1edbc 278 #define ROMTABLE_BASE (0xF00FFFD0UL) /**< ROMTABLE base address */
AnnaBridge 171:3a7713b1edbc 279 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
AnnaBridge 171:3a7713b1edbc 280 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
AnnaBridge 171:3a7713b1edbc 281
AnnaBridge 171:3a7713b1edbc 282 /** @} End of group EFM32ZG222F32_Peripheral_Base */
AnnaBridge 171:3a7713b1edbc 283
AnnaBridge 171:3a7713b1edbc 284 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 285 * @defgroup EFM32ZG222F32_Peripheral_Declaration EFM32ZG222F32 Peripheral Declarations
AnnaBridge 171:3a7713b1edbc 286 * @{
AnnaBridge 171:3a7713b1edbc 287 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 288
AnnaBridge 171:3a7713b1edbc 289 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
AnnaBridge 171:3a7713b1edbc 290 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
AnnaBridge 171:3a7713b1edbc 291 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
AnnaBridge 171:3a7713b1edbc 292 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
AnnaBridge 171:3a7713b1edbc 293 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
AnnaBridge 171:3a7713b1edbc 294 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
AnnaBridge 171:3a7713b1edbc 295 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
AnnaBridge 171:3a7713b1edbc 296 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
AnnaBridge 171:3a7713b1edbc 297 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
AnnaBridge 171:3a7713b1edbc 298 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
AnnaBridge 171:3a7713b1edbc 299 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
AnnaBridge 171:3a7713b1edbc 300 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
AnnaBridge 171:3a7713b1edbc 301 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
AnnaBridge 171:3a7713b1edbc 302 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
AnnaBridge 171:3a7713b1edbc 303 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
AnnaBridge 171:3a7713b1edbc 304 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
AnnaBridge 171:3a7713b1edbc 305 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
AnnaBridge 171:3a7713b1edbc 306 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
AnnaBridge 171:3a7713b1edbc 307 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
AnnaBridge 171:3a7713b1edbc 308 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
AnnaBridge 171:3a7713b1edbc 309 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
AnnaBridge 171:3a7713b1edbc 310 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
AnnaBridge 171:3a7713b1edbc 311 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
AnnaBridge 171:3a7713b1edbc 312
AnnaBridge 171:3a7713b1edbc 313 /** @} End of group EFM32ZG222F32_Peripheral_Declaration */
AnnaBridge 171:3a7713b1edbc 314
AnnaBridge 171:3a7713b1edbc 315 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 316 * @defgroup EFM32ZG222F32_BitFields EFM32ZG222F32 Bit Fields
AnnaBridge 171:3a7713b1edbc 317 * @{
AnnaBridge 171:3a7713b1edbc 318 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 319
AnnaBridge 171:3a7713b1edbc 320 #include "efm32zg_prs_signals.h"
AnnaBridge 171:3a7713b1edbc 321 #include "efm32zg_dmareq.h"
AnnaBridge 171:3a7713b1edbc 322 #include "efm32zg_dmactrl.h"
AnnaBridge 171:3a7713b1edbc 323
AnnaBridge 171:3a7713b1edbc 324 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 325 * @defgroup EFM32ZG222F32_UNLOCK EFM32ZG222F32 Unlock Codes
AnnaBridge 171:3a7713b1edbc 326 * @{
AnnaBridge 171:3a7713b1edbc 327 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 328 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
AnnaBridge 171:3a7713b1edbc 329 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
AnnaBridge 171:3a7713b1edbc 330 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
AnnaBridge 171:3a7713b1edbc 331 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
AnnaBridge 171:3a7713b1edbc 332 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
AnnaBridge 171:3a7713b1edbc 333
AnnaBridge 171:3a7713b1edbc 334 /** @} End of group EFM32ZG222F32_UNLOCK */
AnnaBridge 171:3a7713b1edbc 335
AnnaBridge 171:3a7713b1edbc 336 /** @} End of group EFM32ZG222F32_BitFields */
AnnaBridge 171:3a7713b1edbc 337
AnnaBridge 171:3a7713b1edbc 338 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 339 * @defgroup EFM32ZG222F32_Alternate_Function EFM32ZG222F32 Alternate Function
AnnaBridge 171:3a7713b1edbc 340 * @{
AnnaBridge 171:3a7713b1edbc 341 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 342
AnnaBridge 171:3a7713b1edbc 343 #include "efm32zg_af_ports.h"
AnnaBridge 171:3a7713b1edbc 344 #include "efm32zg_af_pins.h"
AnnaBridge 171:3a7713b1edbc 345
AnnaBridge 171:3a7713b1edbc 346 /** @} End of group EFM32ZG222F32_Alternate_Function */
AnnaBridge 171:3a7713b1edbc 347
AnnaBridge 171:3a7713b1edbc 348 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 349 * @brief Set the value of a bit field within a register.
AnnaBridge 171:3a7713b1edbc 350 *
AnnaBridge 171:3a7713b1edbc 351 * @param REG
AnnaBridge 171:3a7713b1edbc 352 * The register to update
AnnaBridge 171:3a7713b1edbc 353 * @param MASK
AnnaBridge 171:3a7713b1edbc 354 * The mask for the bit field to update
AnnaBridge 171:3a7713b1edbc 355 * @param VALUE
AnnaBridge 171:3a7713b1edbc 356 * The value to write to the bit field
AnnaBridge 171:3a7713b1edbc 357 * @param OFFSET
AnnaBridge 171:3a7713b1edbc 358 * The number of bits that the field is offset within the register.
AnnaBridge 171:3a7713b1edbc 359 * 0 (zero) means LSB.
AnnaBridge 171:3a7713b1edbc 360 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 361 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
AnnaBridge 171:3a7713b1edbc 362 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
AnnaBridge 171:3a7713b1edbc 363
AnnaBridge 171:3a7713b1edbc 364 /** @} End of group EFM32ZG222F32 */
AnnaBridge 171:3a7713b1edbc 365
AnnaBridge 171:3a7713b1edbc 366 /** @} End of group Parts */
AnnaBridge 171:3a7713b1edbc 367
AnnaBridge 171:3a7713b1edbc 368 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 369 }
AnnaBridge 171:3a7713b1edbc 370 #endif
AnnaBridge 171:3a7713b1edbc 371 #endif /* EFM32ZG222F32_H */