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TARGET_EFM32HG_STK3400/TOOLCHAIN_GCC_ARM/efm32hg_devinfo.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 2 | * @file efm32hg_devinfo.h |
AnnaBridge | 171:3a7713b1edbc | 3 | * @brief EFM32HG_DEVINFO register and bit field definitions |
AnnaBridge | 171:3a7713b1edbc | 4 | * @version 5.1.2 |
AnnaBridge | 171:3a7713b1edbc | 5 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 6 | * @section License |
AnnaBridge | 171:3a7713b1edbc | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
AnnaBridge | 171:3a7713b1edbc | 8 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 9 | * |
AnnaBridge | 171:3a7713b1edbc | 10 | * Permission is granted to anyone to use this software for any purpose, |
AnnaBridge | 171:3a7713b1edbc | 11 | * including commercial applications, and to alter it and redistribute it |
AnnaBridge | 171:3a7713b1edbc | 12 | * freely, subject to the following restrictions: |
AnnaBridge | 171:3a7713b1edbc | 13 | * |
AnnaBridge | 171:3a7713b1edbc | 14 | * 1. The origin of this software must not be misrepresented; you must not |
AnnaBridge | 171:3a7713b1edbc | 15 | * claim that you wrote the original software.@n |
AnnaBridge | 171:3a7713b1edbc | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
AnnaBridge | 171:3a7713b1edbc | 17 | * misrepresented as being the original software.@n |
AnnaBridge | 171:3a7713b1edbc | 18 | * 3. This notice may not be removed or altered from any source distribution. |
AnnaBridge | 171:3a7713b1edbc | 19 | * |
AnnaBridge | 171:3a7713b1edbc | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
AnnaBridge | 171:3a7713b1edbc | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
AnnaBridge | 171:3a7713b1edbc | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
AnnaBridge | 171:3a7713b1edbc | 23 | * kind, including, but not limited to, any implied warranties of |
AnnaBridge | 171:3a7713b1edbc | 24 | * merchantability or fitness for any particular purpose or warranties against |
AnnaBridge | 171:3a7713b1edbc | 25 | * infringement of any proprietary rights of a third party. |
AnnaBridge | 171:3a7713b1edbc | 26 | * |
AnnaBridge | 171:3a7713b1edbc | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
AnnaBridge | 171:3a7713b1edbc | 28 | * incidental, or special damages, or any other relief, or for any claim by |
AnnaBridge | 171:3a7713b1edbc | 29 | * any third party, arising from your use of this Software. |
AnnaBridge | 171:3a7713b1edbc | 30 | * |
AnnaBridge | 171:3a7713b1edbc | 31 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 32 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 33 | * @addtogroup Parts |
AnnaBridge | 171:3a7713b1edbc | 34 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 35 | ******************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 36 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 37 | * @defgroup EFM32HG_DEVINFO |
AnnaBridge | 171:3a7713b1edbc | 38 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 39 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 40 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 41 | { |
AnnaBridge | 171:3a7713b1edbc | 42 | __IM uint32_t CAL; /**< Calibration temperature and checksum */ |
AnnaBridge | 171:3a7713b1edbc | 43 | __IM uint32_t ADC0CAL0; /**< ADC0 Calibration register 0 */ |
AnnaBridge | 171:3a7713b1edbc | 44 | __IM uint32_t ADC0CAL1; /**< ADC0 Calibration register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 45 | __IM uint32_t ADC0CAL2; /**< ADC0 Calibration register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 46 | uint32_t RESERVED0[2]; /**< Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 47 | __IM uint32_t IDAC0CAL0; /**< IDAC0 calibration register */ |
AnnaBridge | 171:3a7713b1edbc | 48 | __IM uint32_t USHFRCOCAL0; /**< USHFRCO calibration register */ |
AnnaBridge | 171:3a7713b1edbc | 49 | uint32_t RESERVED1[1]; /**< Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 50 | __IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO calibration register 0 */ |
AnnaBridge | 171:3a7713b1edbc | 51 | __IM uint32_t AUXHFRCOCAL1; /**< AUXHFRCO calibration register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 52 | __IM uint32_t HFRCOCAL0; /**< HFRCO calibration register 0 */ |
AnnaBridge | 171:3a7713b1edbc | 53 | __IM uint32_t HFRCOCAL1; /**< HFRCO calibration register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 54 | __IM uint32_t MEMINFO; /**< Memory information */ |
AnnaBridge | 171:3a7713b1edbc | 55 | uint32_t RESERVED2[2]; /**< Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 56 | __IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */ |
AnnaBridge | 171:3a7713b1edbc | 57 | __IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */ |
AnnaBridge | 171:3a7713b1edbc | 58 | __IM uint32_t MSIZE; /**< Flash and SRAM Memory size in KiloBytes */ |
AnnaBridge | 171:3a7713b1edbc | 59 | __IM uint32_t PART; /**< Part description */ |
AnnaBridge | 171:3a7713b1edbc | 60 | } DEVINFO_TypeDef; /** @} */ |
AnnaBridge | 171:3a7713b1edbc | 61 | |
AnnaBridge | 171:3a7713b1edbc | 62 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 63 | * @defgroup EFM32HG_DEVINFO_BitFields |
AnnaBridge | 171:3a7713b1edbc | 64 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 65 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 66 | /* Bit fields for EFM32HG_DEVINFO */ |
AnnaBridge | 171:3a7713b1edbc | 67 | #define _DEVINFO_CAL_CRC_MASK 0x0000FFFFUL /**< Integrity CRC checksum mask */ |
AnnaBridge | 171:3a7713b1edbc | 68 | #define _DEVINFO_CAL_CRC_SHIFT 0 /**< Integrity CRC checksum shift */ |
AnnaBridge | 171:3a7713b1edbc | 69 | #define _DEVINFO_CAL_TEMP_MASK 0x00FF0000UL /**< Calibration temperature, DegC, mask */ |
AnnaBridge | 171:3a7713b1edbc | 70 | #define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Calibration temperature shift */ |
AnnaBridge | 171:3a7713b1edbc | 71 | #define _DEVINFO_ADC0CAL0_1V25_GAIN_MASK 0x00007F00UL /**< Gain for 1V25 reference, mask */ |
AnnaBridge | 171:3a7713b1edbc | 72 | #define _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT 8 /**< Gain for 1V25 reference, shift */ |
AnnaBridge | 171:3a7713b1edbc | 73 | #define _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK 0x0000007FUL /**< Offset for 1V25 reference, mask */ |
AnnaBridge | 171:3a7713b1edbc | 74 | #define _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT 0 /**< Offset for 1V25 reference, shift */ |
AnnaBridge | 171:3a7713b1edbc | 75 | #define _DEVINFO_ADC0CAL0_2V5_GAIN_MASK 0x7F000000UL /**< Gain for 2V5 reference, mask */ |
AnnaBridge | 171:3a7713b1edbc | 76 | #define _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT 24 /**< Gain for 2V5 reference, shift */ |
AnnaBridge | 171:3a7713b1edbc | 77 | #define _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK 0x007F0000UL /**< Offset for 2V5 reference, mask */ |
AnnaBridge | 171:3a7713b1edbc | 78 | #define _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT 16 /**< Offset for 2V5 reference, shift */ |
AnnaBridge | 171:3a7713b1edbc | 79 | #define _DEVINFO_ADC0CAL1_VDD_GAIN_MASK 0x00007F00UL /**< Gain for VDD reference, mask */ |
AnnaBridge | 171:3a7713b1edbc | 80 | #define _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT 8 /**< Gain for VDD reference, shift */ |
AnnaBridge | 171:3a7713b1edbc | 81 | #define _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK 0x0000007FUL /**< Offset for VDD reference, mask */ |
AnnaBridge | 171:3a7713b1edbc | 82 | #define _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT 0 /**< Offset for VDD reference, shift */ |
AnnaBridge | 171:3a7713b1edbc | 83 | #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK 0x7F000000UL /**< Gain 5VDIFF for 5VDIFF reference, mask */ |
AnnaBridge | 171:3a7713b1edbc | 84 | #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT 24 /**< Gain for 5VDIFF reference, mask */ |
AnnaBridge | 171:3a7713b1edbc | 85 | #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK 0x007F0000UL /**< Offset for 5VDIFF reference, mask */ |
AnnaBridge | 171:3a7713b1edbc | 86 | #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT 16 /**< Offset for 5VDIFF reference, shift */ |
AnnaBridge | 171:3a7713b1edbc | 87 | #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK 0x0000007FUL /**< Offset for 2XVDDVSS reference, mask */ |
AnnaBridge | 171:3a7713b1edbc | 88 | #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT 0 /**< Offset for 2XVDDVSS reference, shift */ |
AnnaBridge | 171:3a7713b1edbc | 89 | #define _DEVINFO_ADC0CAL2_TEMP1V25_MASK 0xFFF00000UL /**< Temperature reading at 1V25 reference, mask */ |
AnnaBridge | 171:3a7713b1edbc | 90 | #define _DEVINFO_ADC0CAL2_TEMP1V25_SHIFT 20 /**< Temperature reading at 1V25 reference, DegC */ |
AnnaBridge | 171:3a7713b1edbc | 91 | #define _DEVINFO_IDAC0CAL0_RANGE0_MASK 0x000000FFUL /**< Current range 0 tuning value for IDAC0 mask */ |
AnnaBridge | 171:3a7713b1edbc | 92 | #define _DEVINFO_IDAC0CAL0_RANGE0_SHIFT 0 /**< Current range 0 tuning value for IDAC0 shift */ |
AnnaBridge | 171:3a7713b1edbc | 93 | #define _DEVINFO_IDAC0CAL0_RANGE1_MASK 0x0000FF00UL /**< Current range 1 tuning value for IDAC0 mask */ |
AnnaBridge | 171:3a7713b1edbc | 94 | #define _DEVINFO_IDAC0CAL0_RANGE1_SHIFT 8 /**< Current range 1 tuning value for IDAC0 shift */ |
AnnaBridge | 171:3a7713b1edbc | 95 | #define _DEVINFO_IDAC0CAL0_RANGE2_MASK 0x00FF0000UL /**< Current range 2 tuning value for IDAC0 mask */ |
AnnaBridge | 171:3a7713b1edbc | 96 | #define _DEVINFO_IDAC0CAL0_RANGE2_SHIFT 16 /**< Current range 2 tuning value for IDAC0 shift */ |
AnnaBridge | 171:3a7713b1edbc | 97 | #define _DEVINFO_IDAC0CAL0_RANGE3_MASK 0xFF000000UL /**< Current range 3 tuning value for IDAC0 mask */ |
AnnaBridge | 171:3a7713b1edbc | 98 | #define _DEVINFO_IDAC0CAL0_RANGE3_SHIFT 24 /**< Current range 3 tuning value for IDAC0 shift */ |
AnnaBridge | 171:3a7713b1edbc | 99 | #define _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK 0x0000007FUL /**< 24 MHz TUNING value for USFRCO mask */ |
AnnaBridge | 171:3a7713b1edbc | 100 | #define _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT 0 /**< 24 MHz TUNING value for USFRCO shift */ |
AnnaBridge | 171:3a7713b1edbc | 101 | #define _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK 0x00003F00UL /**< 24 MHz FINETUNING value for USFRCO mask */ |
AnnaBridge | 171:3a7713b1edbc | 102 | #define _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT 8 /**< 24 MHz FINETUNING value for USFRCO shift */ |
AnnaBridge | 171:3a7713b1edbc | 103 | #define _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK 0x007F0000UL /**< 24 MHz TUNING value for USFRCO mask */ |
AnnaBridge | 171:3a7713b1edbc | 104 | #define _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT 16 /**< 24 MHz TUNING value for USFRCO shift */ |
AnnaBridge | 171:3a7713b1edbc | 105 | #define _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK 0x3F000000UL /**< 24 MHz FINETUNING value for USFRCO mask */ |
AnnaBridge | 171:3a7713b1edbc | 106 | #define _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT 24 /**< 24 MHz FINETUNING value for USFRCO shift */ |
AnnaBridge | 171:3a7713b1edbc | 107 | #define _DEVINFO_AUXHFRCOCAL0_BAND1_MASK 0x000000FFUL /**< 1MHz tuning value for AUXHFRCO, mask */ |
AnnaBridge | 171:3a7713b1edbc | 108 | #define _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT 0 /**< 1MHz tuning value for AUXHFRCO, shift */ |
AnnaBridge | 171:3a7713b1edbc | 109 | #define _DEVINFO_AUXHFRCOCAL0_BAND7_MASK 0x0000FF00UL /**< 7MHz tuning value for AUXHFRCO, mask */ |
AnnaBridge | 171:3a7713b1edbc | 110 | #define _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT 8 /**< 7MHz tuning value for AUXHFRCO, shift */ |
AnnaBridge | 171:3a7713b1edbc | 111 | #define _DEVINFO_AUXHFRCOCAL0_BAND11_MASK 0x00FF0000UL /**< 11MHz tuning value for AUXHFRCO, mask */ |
AnnaBridge | 171:3a7713b1edbc | 112 | #define _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT 16 /**< 11MHz tuning value for AUXHFRCO, shift */ |
AnnaBridge | 171:3a7713b1edbc | 113 | #define _DEVINFO_AUXHFRCOCAL0_BAND14_MASK 0xFF000000UL /**< 14MHz tuning value for AUXHFRCO, mask */ |
AnnaBridge | 171:3a7713b1edbc | 114 | #define _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT 24 /**< 14MHz tuning value for AUXHFRCO, shift */ |
AnnaBridge | 171:3a7713b1edbc | 115 | #define _DEVINFO_AUXHFRCOCAL1_BAND21_MASK 0x000000FFUL /**< 21MHz tuning value for AUXHFRCO, mask */ |
AnnaBridge | 171:3a7713b1edbc | 116 | #define _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT 0 /**< 21MHz tuning value for AUXHFRCO, shift */ |
AnnaBridge | 171:3a7713b1edbc | 117 | #define _DEVINFO_HFRCOCAL0_BAND1_MASK 0x000000FFUL /**< 1MHz tuning value for HFRCO, mask */ |
AnnaBridge | 171:3a7713b1edbc | 118 | #define _DEVINFO_HFRCOCAL0_BAND1_SHIFT 0 /**< 1MHz tuning value for HFRCO, shift */ |
AnnaBridge | 171:3a7713b1edbc | 119 | #define _DEVINFO_HFRCOCAL0_BAND7_MASK 0x0000FF00UL /**< 7MHz tuning value for HFRCO, mask */ |
AnnaBridge | 171:3a7713b1edbc | 120 | #define _DEVINFO_HFRCOCAL0_BAND7_SHIFT 8 /**< 7MHz tuning value for HFRCO, shift */ |
AnnaBridge | 171:3a7713b1edbc | 121 | #define _DEVINFO_HFRCOCAL0_BAND11_MASK 0x00FF0000UL /**< 11MHz tuning value for HFRCO, mask */ |
AnnaBridge | 171:3a7713b1edbc | 122 | #define _DEVINFO_HFRCOCAL0_BAND11_SHIFT 16 /**< 11MHz tuning value for HFRCO, shift */ |
AnnaBridge | 171:3a7713b1edbc | 123 | #define _DEVINFO_HFRCOCAL0_BAND14_MASK 0xFF000000UL /**< 14MHz tuning value for HFRCO, mask */ |
AnnaBridge | 171:3a7713b1edbc | 124 | #define _DEVINFO_HFRCOCAL0_BAND14_SHIFT 24 /**< 14MHz tuning value for HFRCO, shift */ |
AnnaBridge | 171:3a7713b1edbc | 125 | #define _DEVINFO_HFRCOCAL1_BAND21_MASK 0x000000FFUL /**< 21MHz tuning value for HFRCO, mask */ |
AnnaBridge | 171:3a7713b1edbc | 126 | #define _DEVINFO_HFRCOCAL1_BAND21_SHIFT 0 /**< 21MHz tuning value for HFRCO, shift */ |
AnnaBridge | 171:3a7713b1edbc | 127 | #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Flash page size (refer to ref.man for encoding) mask */ |
AnnaBridge | 171:3a7713b1edbc | 128 | #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Flash page size shift */ |
AnnaBridge | 171:3a7713b1edbc | 129 | #define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Lower part of 64-bit device unique number */ |
AnnaBridge | 171:3a7713b1edbc | 130 | #define _DEVINFO_UNIQUEL_SHIFT 0 /**< Unique Low 32-bit shift */ |
AnnaBridge | 171:3a7713b1edbc | 131 | #define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< High part of 64-bit device unique number */ |
AnnaBridge | 171:3a7713b1edbc | 132 | #define _DEVINFO_UNIQUEH_SHIFT 0 /**< Unique High 32-bit shift */ |
AnnaBridge | 171:3a7713b1edbc | 133 | #define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Flash size in kilobytes */ |
AnnaBridge | 171:3a7713b1edbc | 134 | #define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Bit position for flash size */ |
AnnaBridge | 171:3a7713b1edbc | 135 | #define _DEVINFO_MSIZE_FLASH_MASK 0x0000FFFFUL /**< SRAM size in kilobytes */ |
AnnaBridge | 171:3a7713b1edbc | 136 | #define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Bit position for SRAM size */ |
AnnaBridge | 171:3a7713b1edbc | 137 | #define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Production revision */ |
AnnaBridge | 171:3a7713b1edbc | 138 | #define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Bit position for production revision */ |
AnnaBridge | 171:3a7713b1edbc | 139 | #define _DEVINFO_PART_DEVICE_FAMILY_MASK 0x00FF0000UL /**< Device Family, 0x47 for Gecko */ |
AnnaBridge | 171:3a7713b1edbc | 140 | #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Bit position for device family */ |
AnnaBridge | 171:3a7713b1edbc | 141 | /* Legacy family #defines */ |
AnnaBridge | 171:3a7713b1edbc | 142 | #define _DEVINFO_PART_DEVICE_FAMILY_G 71 /**< Gecko Device Family */ |
AnnaBridge | 171:3a7713b1edbc | 143 | #define _DEVINFO_PART_DEVICE_FAMILY_GG 72 /**< Giant Gecko Device Family */ |
AnnaBridge | 171:3a7713b1edbc | 144 | #define _DEVINFO_PART_DEVICE_FAMILY_TG 73 /**< Tiny Gecko Device Family */ |
AnnaBridge | 171:3a7713b1edbc | 145 | #define _DEVINFO_PART_DEVICE_FAMILY_LG 74 /**< Leopard Gecko Device Family */ |
AnnaBridge | 171:3a7713b1edbc | 146 | #define _DEVINFO_PART_DEVICE_FAMILY_WG 75 /**< Wonder Gecko Device Family */ |
AnnaBridge | 171:3a7713b1edbc | 147 | #define _DEVINFO_PART_DEVICE_FAMILY_ZG 76 /**< Zero Gecko Device Family */ |
AnnaBridge | 171:3a7713b1edbc | 148 | #define _DEVINFO_PART_DEVICE_FAMILY_HG 77 /**< Happy Gecko Device Family */ |
AnnaBridge | 171:3a7713b1edbc | 149 | /* New style family #defines */ |
AnnaBridge | 171:3a7713b1edbc | 150 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 71 /**< Gecko Device Family */ |
AnnaBridge | 171:3a7713b1edbc | 151 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 72 /**< Giant Gecko Device Family */ |
AnnaBridge | 171:3a7713b1edbc | 152 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 73 /**< Tiny Gecko Device Family */ |
AnnaBridge | 171:3a7713b1edbc | 153 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 74 /**< Leopard Gecko Device Family */ |
AnnaBridge | 171:3a7713b1edbc | 154 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 75 /**< Wonder Gecko Device Family */ |
AnnaBridge | 171:3a7713b1edbc | 155 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 76 /**< Zero Gecko Device Family */ |
AnnaBridge | 171:3a7713b1edbc | 156 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 77 /**< Happy Gecko Device Family */ |
AnnaBridge | 171:3a7713b1edbc | 157 | #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 120 /**< EZR Wonder Gecko Device Family */ |
AnnaBridge | 171:3a7713b1edbc | 158 | #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 121 /**< EZR Leopard Gecko Device Family */ |
AnnaBridge | 171:3a7713b1edbc | 159 | #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 122 /**< EZR Happy Gecko Device Family */ |
AnnaBridge | 171:3a7713b1edbc | 160 | #define _DEVINFO_PART_DEVICE_NUMBER_MASK 0x0000FFFFUL /**< Device number */ |
AnnaBridge | 171:3a7713b1edbc | 161 | #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Bit position for device number */ |
AnnaBridge | 171:3a7713b1edbc | 162 | |
AnnaBridge | 171:3a7713b1edbc | 163 | /** @} End of group EFM32HG_DEVINFO */ |
AnnaBridge | 171:3a7713b1edbc | 164 | /** @} End of group Parts */ |
AnnaBridge | 171:3a7713b1edbc | 165 |