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TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_MICRO/em_opamp.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_TB_SENSE_12/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_opamp.h@160:5571c4ff569f
mbed library. Release version 164
Who changed what in which revision?
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Anna Bridge |
142:4eea097334d6 | 1 | /**************************************************************************//** |
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160:5571c4ff569f | 2 | * @file em_opamp.h |
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160:5571c4ff569f | 3 | * @brief Operational Amplifier (OPAMP) peripheral API |
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160:5571c4ff569f | 4 | * @version 5.3.3 |
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160:5571c4ff569f | 5 | ****************************************************************************** |
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160:5571c4ff569f | 6 | * # License |
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160:5571c4ff569f | 7 | * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b> |
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160:5571c4ff569f | 8 | ******************************************************************************* |
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160:5571c4ff569f | 9 | * |
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160:5571c4ff569f | 10 | * Permission is granted to anyone to use this software for any purpose, |
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160:5571c4ff569f | 11 | * including commercial applications, and to alter it and redistribute it |
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160:5571c4ff569f | 12 | * freely, subject to the following restrictions: |
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160:5571c4ff569f | 13 | * |
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160:5571c4ff569f | 14 | * 1. The origin of this software must not be misrepresented; you must not |
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160:5571c4ff569f | 15 | * claim that you wrote the original software. |
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160:5571c4ff569f | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
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160:5571c4ff569f | 17 | * misrepresented as being the original software. |
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160:5571c4ff569f | 18 | * 3. This notice may not be removed or altered from any source distribution. |
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160:5571c4ff569f | 19 | * |
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160:5571c4ff569f | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no |
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160:5571c4ff569f | 21 | * obligation to support this Software. Silicon Labs is providing the |
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160:5571c4ff569f | 22 | * Software "AS IS", with no express or implied warranties of any kind, |
Anna Bridge |
160:5571c4ff569f | 23 | * including, but not limited to, any implied warranties of merchantability |
Anna Bridge |
160:5571c4ff569f | 24 | * or fitness for any particular purpose or warranties against infringement |
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160:5571c4ff569f | 25 | * of any proprietary rights of a third party. |
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160:5571c4ff569f | 26 | * |
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160:5571c4ff569f | 27 | * Silicon Labs will not be liable for any consequential, incidental, or |
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160:5571c4ff569f | 28 | * special damages, or any other relief, or for any claim by any third party, |
Anna Bridge |
160:5571c4ff569f | 29 | * arising from your use of this Software. |
Anna Bridge |
160:5571c4ff569f | 30 | * |
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160:5571c4ff569f | 31 | ******************************************************************************/ |
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142:4eea097334d6 | 32 | |
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142:4eea097334d6 | 33 | #ifndef EM_OPAMP_H |
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142:4eea097334d6 | 34 | #define EM_OPAMP_H |
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142:4eea097334d6 | 35 | |
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142:4eea097334d6 | 36 | #include "em_device.h" |
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142:4eea097334d6 | 37 | #if ((defined(_SILICON_LABS_32B_SERIES_0) && defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) \ |
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160:5571c4ff569f | 38 | || (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0))) |
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142:4eea097334d6 | 39 | |
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142:4eea097334d6 | 40 | #ifdef __cplusplus |
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142:4eea097334d6 | 41 | extern "C" { |
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142:4eea097334d6 | 42 | #endif |
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142:4eea097334d6 | 43 | |
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142:4eea097334d6 | 44 | #include <stdint.h> |
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142:4eea097334d6 | 45 | #include <stdbool.h> |
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142:4eea097334d6 | 46 | |
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142:4eea097334d6 | 47 | #if defined(_SILICON_LABS_32B_SERIES_0) |
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142:4eea097334d6 | 48 | #include "em_dac.h" |
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142:4eea097334d6 | 49 | #elif defined (_SILICON_LABS_32B_SERIES_1) |
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142:4eea097334d6 | 50 | #include "em_vdac.h" |
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142:4eea097334d6 | 51 | #endif |
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142:4eea097334d6 | 52 | |
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142:4eea097334d6 | 53 | /***************************************************************************//** |
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142:4eea097334d6 | 54 | * @addtogroup emlib |
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142:4eea097334d6 | 55 | * @{ |
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142:4eea097334d6 | 56 | ******************************************************************************/ |
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142:4eea097334d6 | 57 | |
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142:4eea097334d6 | 58 | /***************************************************************************//** |
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142:4eea097334d6 | 59 | * @addtogroup OPAMP |
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142:4eea097334d6 | 60 | * @{ |
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142:4eea097334d6 | 61 | ******************************************************************************/ |
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142:4eea097334d6 | 62 | |
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142:4eea097334d6 | 63 | /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ |
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142:4eea097334d6 | 64 | |
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142:4eea097334d6 | 65 | /** Validation of DAC OPA number for assert statements. */ |
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142:4eea097334d6 | 66 | #if defined(_SILICON_LABS_32B_SERIES_0) |
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142:4eea097334d6 | 67 | #define DAC_OPA_VALID(opa) ((opa) <= OPA2) |
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142:4eea097334d6 | 68 | #elif defined(_SILICON_LABS_32B_SERIES_1) |
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160:5571c4ff569f | 69 | #if defined(VDAC_STATUS_OPA2ENS) |
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142:4eea097334d6 | 70 | #define VDAC_OPA_VALID(opa) ((opa) <= OPA2) |
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160:5571c4ff569f | 71 | #elif defined(VDAC_STATUS_OPA1ENS) |
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160:5571c4ff569f | 72 | #define VDAC_OPA_VALID(opa) ((opa) <= OPA1) |
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160:5571c4ff569f | 73 | #else |
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160:5571c4ff569f | 74 | #define VDAC_OPA_VALID(opa) ((opa) = OPA0) |
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160:5571c4ff569f | 75 | #endif |
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142:4eea097334d6 | 76 | #endif |
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142:4eea097334d6 | 77 | |
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142:4eea097334d6 | 78 | /** @endcond */ |
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142:4eea097334d6 | 79 | |
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142:4eea097334d6 | 80 | /******************************************************************************* |
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142:4eea097334d6 | 81 | ******************************** ENUMS ************************************ |
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142:4eea097334d6 | 82 | ******************************************************************************/ |
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142:4eea097334d6 | 83 | |
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142:4eea097334d6 | 84 | /** OPAMP selector values. */ |
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160:5571c4ff569f | 85 | typedef enum { |
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160:5571c4ff569f | 86 | #if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA0ENS) |
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142:4eea097334d6 | 87 | OPA0 = 0, /**< Select OPA0. */ |
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160:5571c4ff569f | 88 | #endif |
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160:5571c4ff569f | 89 | #if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA1ENS) |
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142:4eea097334d6 | 90 | OPA1 = 1, /**< Select OPA1. */ |
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160:5571c4ff569f | 91 | #endif |
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160:5571c4ff569f | 92 | #if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA2ENS) |
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142:4eea097334d6 | 93 | OPA2 = 2 /**< Select OPA2. */ |
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160:5571c4ff569f | 94 | #endif |
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142:4eea097334d6 | 95 | } OPAMP_TypeDef; |
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142:4eea097334d6 | 96 | |
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142:4eea097334d6 | 97 | /** OPAMP negative terminal input selection values. */ |
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160:5571c4ff569f | 98 | typedef enum { |
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142:4eea097334d6 | 99 | #if defined(_SILICON_LABS_32B_SERIES_0) |
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142:4eea097334d6 | 100 | opaNegSelDisable = DAC_OPA0MUX_NEGSEL_DISABLE, /**< Input disabled. */ |
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142:4eea097334d6 | 101 | opaNegSelUnityGain = DAC_OPA0MUX_NEGSEL_UG, /**< Unity gain feedback path. */ |
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142:4eea097334d6 | 102 | opaNegSelResTap = DAC_OPA0MUX_NEGSEL_OPATAP, /**< Feedback resistor ladder tap. */ |
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142:4eea097334d6 | 103 | opaNegSelNegPad = DAC_OPA0MUX_NEGSEL_NEGPAD /**< Negative pad as input. */ |
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142:4eea097334d6 | 104 | #elif defined(_SILICON_LABS_32B_SERIES_1) |
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142:4eea097334d6 | 105 | opaNegSelAPORT1YCH1 = VDAC_OPA_MUX_NEGSEL_APORT1YCH1, /**< APORT1YCH1 */ |
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142:4eea097334d6 | 106 | opaNegSelAPORT1YCH3 = VDAC_OPA_MUX_NEGSEL_APORT1YCH3, /**< APORT1YCH3 */ |
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142:4eea097334d6 | 107 | opaNegSelAPORT1YCH5 = VDAC_OPA_MUX_NEGSEL_APORT1YCH5, /**< APORT1YCH5 */ |
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142:4eea097334d6 | 108 | opaNegSelAPORT1YCH7 = VDAC_OPA_MUX_NEGSEL_APORT1YCH7, /**< APORT1YCH7 */ |
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142:4eea097334d6 | 109 | opaNegSelAPORT1YCH9 = VDAC_OPA_MUX_NEGSEL_APORT1YCH9, /**< APORT1YCH9 */ |
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142:4eea097334d6 | 110 | opaNegSelAPORT1YCH11 = VDAC_OPA_MUX_NEGSEL_APORT1YCH11, /**< APORT1YCH11 */ |
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142:4eea097334d6 | 111 | opaNegSelAPORT1YCH13 = VDAC_OPA_MUX_NEGSEL_APORT1YCH13, /**< APORT1YCH13 */ |
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142:4eea097334d6 | 112 | opaNegSelAPORT1YCH15 = VDAC_OPA_MUX_NEGSEL_APORT1YCH15, /**< APORT1YCH15 */ |
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142:4eea097334d6 | 113 | opaNegSelAPORT1YCH17 = VDAC_OPA_MUX_NEGSEL_APORT1YCH17, /**< APORT1YCH17 */ |
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142:4eea097334d6 | 114 | opaNegSelAPORT1YCH19 = VDAC_OPA_MUX_NEGSEL_APORT1YCH19, /**< APORT1YCH19 */ |
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142:4eea097334d6 | 115 | opaNegSelAPORT1YCH21 = VDAC_OPA_MUX_NEGSEL_APORT1YCH21, /**< APORT1YCH21 */ |
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142:4eea097334d6 | 116 | opaNegSelAPORT1YCH23 = VDAC_OPA_MUX_NEGSEL_APORT1YCH23, /**< APORT1YCH23 */ |
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142:4eea097334d6 | 117 | opaNegSelAPORT1YCH25 = VDAC_OPA_MUX_NEGSEL_APORT1YCH25, /**< APORT1YCH25 */ |
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142:4eea097334d6 | 118 | opaNegSelAPORT1YCH27 = VDAC_OPA_MUX_NEGSEL_APORT1YCH27, /**< APORT1YCH27 */ |
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142:4eea097334d6 | 119 | opaNegSelAPORT1YCH29 = VDAC_OPA_MUX_NEGSEL_APORT1YCH29, /**< APORT1YCH29 */ |
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142:4eea097334d6 | 120 | opaNegSelAPORT1YCH31 = VDAC_OPA_MUX_NEGSEL_APORT1YCH31, /**< APORT1YCH31 */ |
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142:4eea097334d6 | 121 | opaNegSelAPORT2YCH0 = VDAC_OPA_MUX_NEGSEL_APORT2YCH0, /**< APORT2YCH0 */ |
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142:4eea097334d6 | 122 | opaNegSelAPORT2YCH2 = VDAC_OPA_MUX_NEGSEL_APORT2YCH2, /**< APORT2YCH2 */ |
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142:4eea097334d6 | 123 | opaNegSelAPORT2YCH4 = VDAC_OPA_MUX_NEGSEL_APORT2YCH4, /**< APORT2YCH4 */ |
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142:4eea097334d6 | 124 | opaNegSelAPORT2YCH6 = VDAC_OPA_MUX_NEGSEL_APORT2YCH6, /**< APORT2YCH6 */ |
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142:4eea097334d6 | 125 | opaNegSelAPORT2YCH8 = VDAC_OPA_MUX_NEGSEL_APORT2YCH8, /**< APORT2YCH8 */ |
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142:4eea097334d6 | 126 | opaNegSelAPORT2YCH10 = VDAC_OPA_MUX_NEGSEL_APORT2YCH10, /**< APORT2YCH10 */ |
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142:4eea097334d6 | 127 | opaNegSelAPORT2YCH12 = VDAC_OPA_MUX_NEGSEL_APORT2YCH12, /**< APORT2YCH12 */ |
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142:4eea097334d6 | 128 | opaNegSelAPORT2YCH14 = VDAC_OPA_MUX_NEGSEL_APORT2YCH14, /**< APORT2YCH14 */ |
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142:4eea097334d6 | 129 | opaNegSelAPORT2YCH16 = VDAC_OPA_MUX_NEGSEL_APORT2YCH16, /**< APORT2YCH16 */ |
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142:4eea097334d6 | 130 | opaNegSelAPORT2YCH18 = VDAC_OPA_MUX_NEGSEL_APORT2YCH18, /**< APORT2YCH18 */ |
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142:4eea097334d6 | 131 | opaNegSelAPORT2YCH20 = VDAC_OPA_MUX_NEGSEL_APORT2YCH20, /**< APORT2YCH20 */ |
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142:4eea097334d6 | 132 | opaNegSelAPORT2YCH22 = VDAC_OPA_MUX_NEGSEL_APORT2YCH22, /**< APORT2YCH22 */ |
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142:4eea097334d6 | 133 | opaNegSelAPORT2YCH24 = VDAC_OPA_MUX_NEGSEL_APORT2YCH24, /**< APORT2YCH24 */ |
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142:4eea097334d6 | 134 | opaNegSelAPORT2YCH26 = VDAC_OPA_MUX_NEGSEL_APORT2YCH26, /**< APORT2YCH26 */ |
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142:4eea097334d6 | 135 | opaNegSelAPORT2YCH28 = VDAC_OPA_MUX_NEGSEL_APORT2YCH28, /**< APORT2YCH28 */ |
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142:4eea097334d6 | 136 | opaNegSelAPORT2YCH30 = VDAC_OPA_MUX_NEGSEL_APORT2YCH30, /**< APORT2YCH30 */ |
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142:4eea097334d6 | 137 | opaNegSelAPORT3YCH1 = VDAC_OPA_MUX_NEGSEL_APORT3YCH1, /**< APORT3YCH1 */ |
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142:4eea097334d6 | 138 | opaNegSelAPORT3YCH3 = VDAC_OPA_MUX_NEGSEL_APORT3YCH3, /**< APORT3YCH3 */ |
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142:4eea097334d6 | 139 | opaNegSelAPORT3YCH5 = VDAC_OPA_MUX_NEGSEL_APORT3YCH5, /**< APORT3YCH5 */ |
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142:4eea097334d6 | 140 | opaNegSelAPORT3YCH7 = VDAC_OPA_MUX_NEGSEL_APORT3YCH7, /**< APORT3YCH7 */ |
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142:4eea097334d6 | 141 | opaNegSelAPORT3YCH9 = VDAC_OPA_MUX_NEGSEL_APORT3YCH9, /**< APORT3YCH9 */ |
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142:4eea097334d6 | 142 | opaNegSelAPORT3YCH11 = VDAC_OPA_MUX_NEGSEL_APORT3YCH11, /**< APORT3YCH11 */ |
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142:4eea097334d6 | 143 | opaNegSelAPORT3YCH13 = VDAC_OPA_MUX_NEGSEL_APORT3YCH13, /**< APORT3YCH13 */ |
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142:4eea097334d6 | 144 | opaNegSelAPORT3YCH15 = VDAC_OPA_MUX_NEGSEL_APORT3YCH15, /**< APORT3YCH15 */ |
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142:4eea097334d6 | 145 | opaNegSelAPORT3YCH17 = VDAC_OPA_MUX_NEGSEL_APORT3YCH17, /**< APORT3YCH17 */ |
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142:4eea097334d6 | 146 | opaNegSelAPORT3YCH19 = VDAC_OPA_MUX_NEGSEL_APORT3YCH19, /**< APORT3YCH19 */ |
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142:4eea097334d6 | 147 | opaNegSelAPORT3YCH21 = VDAC_OPA_MUX_NEGSEL_APORT3YCH21, /**< APORT3YCH21 */ |
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142:4eea097334d6 | 148 | opaNegSelAPORT3YCH23 = VDAC_OPA_MUX_NEGSEL_APORT3YCH23, /**< APORT3YCH23 */ |
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142:4eea097334d6 | 149 | opaNegSelAPORT3YCH25 = VDAC_OPA_MUX_NEGSEL_APORT3YCH25, /**< APORT3YCH25 */ |
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142:4eea097334d6 | 150 | opaNegSelAPORT3YCH27 = VDAC_OPA_MUX_NEGSEL_APORT3YCH27, /**< APORT3YCH27 */ |
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142:4eea097334d6 | 151 | opaNegSelAPORT3YCH29 = VDAC_OPA_MUX_NEGSEL_APORT3YCH29, /**< APORT3YCH29 */ |
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142:4eea097334d6 | 152 | opaNegSelAPORT3YCH31 = VDAC_OPA_MUX_NEGSEL_APORT3YCH31, /**< APORT3YCH31 */ |
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142:4eea097334d6 | 153 | opaNegSelAPORT4YCH0 = VDAC_OPA_MUX_NEGSEL_APORT4YCH0, /**< APORT4YCH0 */ |
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142:4eea097334d6 | 154 | opaNegSelAPORT4YCH2 = VDAC_OPA_MUX_NEGSEL_APORT4YCH2, /**< APORT4YCH2 */ |
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142:4eea097334d6 | 155 | opaNegSelAPORT4YCH4 = VDAC_OPA_MUX_NEGSEL_APORT4YCH4, /**< APORT4YCH4 */ |
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142:4eea097334d6 | 156 | opaNegSelAPORT4YCH6 = VDAC_OPA_MUX_NEGSEL_APORT4YCH6, /**< APORT4YCH6 */ |
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142:4eea097334d6 | 157 | opaNegSelAPORT4YCH8 = VDAC_OPA_MUX_NEGSEL_APORT4YCH8, /**< APORT4YCH8 */ |
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142:4eea097334d6 | 158 | opaNegSelAPORT4YCH10 = VDAC_OPA_MUX_NEGSEL_APORT4YCH10, /**< APORT4YCH10 */ |
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142:4eea097334d6 | 159 | opaNegSelAPORT4YCH12 = VDAC_OPA_MUX_NEGSEL_APORT4YCH12, /**< APORT4YCH12 */ |
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142:4eea097334d6 | 160 | opaNegSelAPORT4YCH14 = VDAC_OPA_MUX_NEGSEL_APORT4YCH14, /**< APORT4YCH14 */ |
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142:4eea097334d6 | 161 | opaNegSelAPORT4YCH16 = VDAC_OPA_MUX_NEGSEL_APORT4YCH16, /**< APORT4YCH16 */ |
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142:4eea097334d6 | 162 | opaNegSelAPORT4YCH18 = VDAC_OPA_MUX_NEGSEL_APORT4YCH18, /**< APORT4YCH18 */ |
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142:4eea097334d6 | 163 | opaNegSelAPORT4YCH20 = VDAC_OPA_MUX_NEGSEL_APORT4YCH20, /**< APORT4YCH20 */ |
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142:4eea097334d6 | 164 | opaNegSelAPORT4YCH22 = VDAC_OPA_MUX_NEGSEL_APORT4YCH22, /**< APORT4YCH22 */ |
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142:4eea097334d6 | 165 | opaNegSelAPORT4YCH24 = VDAC_OPA_MUX_NEGSEL_APORT4YCH24, /**< APORT4YCH24 */ |
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142:4eea097334d6 | 166 | opaNegSelAPORT4YCH26 = VDAC_OPA_MUX_NEGSEL_APORT4YCH26, /**< APORT4YCH26 */ |
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142:4eea097334d6 | 167 | opaNegSelAPORT4YCH28 = VDAC_OPA_MUX_NEGSEL_APORT4YCH28, /**< APORT4YCH28 */ |
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142:4eea097334d6 | 168 | opaNegSelAPORT4YCH30 = VDAC_OPA_MUX_NEGSEL_APORT4YCH30, /**< APORT4YCH30 */ |
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142:4eea097334d6 | 169 | opaNegSelDisable = VDAC_OPA_MUX_NEGSEL_DISABLE, /**< Input disabled. */ |
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142:4eea097334d6 | 170 | opaNegSelUnityGain = VDAC_OPA_MUX_NEGSEL_UG, /**< Unity gain feedback path. */ |
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142:4eea097334d6 | 171 | opaNegSelResTap = VDAC_OPA_MUX_NEGSEL_OPATAP, /**< Feedback resistor ladder tap. */ |
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142:4eea097334d6 | 172 | opaNegSelNegPad = VDAC_OPA_MUX_NEGSEL_NEGPAD /**< Negative pad as input. */ |
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142:4eea097334d6 | 173 | #endif /* defined(_SILICON_LABS_32B_SERIES_0) */ |
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142:4eea097334d6 | 174 | } OPAMP_NegSel_TypeDef; |
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142:4eea097334d6 | 175 | |
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142:4eea097334d6 | 176 | /** OPAMP positive terminal input selection values. */ |
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160:5571c4ff569f | 177 | typedef enum { |
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142:4eea097334d6 | 178 | #if defined(_SILICON_LABS_32B_SERIES_0) |
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142:4eea097334d6 | 179 | opaPosSelDisable = DAC_OPA0MUX_POSSEL_DISABLE, /**< Input disabled. */ |
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142:4eea097334d6 | 180 | opaPosSelDac = DAC_OPA0MUX_POSSEL_DAC, /**< DAC as input (not OPA2). */ |
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142:4eea097334d6 | 181 | opaPosSelPosPad = DAC_OPA0MUX_POSSEL_POSPAD, /**< Positive pad as input. */ |
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142:4eea097334d6 | 182 | opaPosSelOpaIn = DAC_OPA0MUX_POSSEL_OPA0INP, /**< Input from OPAx. */ |
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142:4eea097334d6 | 183 | opaPosSelResTapOpa0 = DAC_OPA0MUX_POSSEL_OPATAP /**< Feedback resistor ladder tap from OPA0. */ |
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142:4eea097334d6 | 184 | #elif defined(_SILICON_LABS_32B_SERIES_1) |
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142:4eea097334d6 | 185 | opaPosSelAPORT1XCH0 = VDAC_OPA_MUX_POSSEL_APORT1XCH0, /**< APORT1XCH0 */ |
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142:4eea097334d6 | 186 | opaPosSelAPORT1XCH2 = VDAC_OPA_MUX_POSSEL_APORT1XCH2, /**< APORT1XCH2 */ |
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142:4eea097334d6 | 187 | opaPosSelAPORT1XCH4 = VDAC_OPA_MUX_POSSEL_APORT1XCH4, /**< APORT1XCH4 */ |
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142:4eea097334d6 | 188 | opaPosSelAPORT1XCH6 = VDAC_OPA_MUX_POSSEL_APORT1XCH6, /**< APORT1XCH6 */ |
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142:4eea097334d6 | 189 | opaPosSelAPORT1XCH8 = VDAC_OPA_MUX_POSSEL_APORT1XCH8, /**< APORT1XCH8 */ |
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142:4eea097334d6 | 190 | opaPosSelAPORT1XCH10 = VDAC_OPA_MUX_POSSEL_APORT1XCH10, /**< APORT1XCH10 */ |
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142:4eea097334d6 | 191 | opaPosSelAPORT1XCH12 = VDAC_OPA_MUX_POSSEL_APORT1XCH12, /**< APORT1XCH12 */ |
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142:4eea097334d6 | 192 | opaPosSelAPORT1XCH14 = VDAC_OPA_MUX_POSSEL_APORT1XCH14, /**< APORT1XCH14 */ |
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142:4eea097334d6 | 193 | opaPosSelAPORT1XCH16 = VDAC_OPA_MUX_POSSEL_APORT1XCH16, /**< APORT1XCH16 */ |
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142:4eea097334d6 | 194 | opaPosSelAPORT1XCH18 = VDAC_OPA_MUX_POSSEL_APORT1XCH18, /**< APORT1XCH18 */ |
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142:4eea097334d6 | 195 | opaPosSelAPORT1XCH20 = VDAC_OPA_MUX_POSSEL_APORT1XCH20, /**< APORT1XCH20 */ |
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142:4eea097334d6 | 196 | opaPosSelAPORT1XCH22 = VDAC_OPA_MUX_POSSEL_APORT1XCH22, /**< APORT1XCH22 */ |
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142:4eea097334d6 | 197 | opaPosSelAPORT1XCH24 = VDAC_OPA_MUX_POSSEL_APORT1XCH24, /**< APORT1XCH24 */ |
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142:4eea097334d6 | 198 | opaPosSelAPORT1XCH26 = VDAC_OPA_MUX_POSSEL_APORT1XCH26, /**< APORT1XCH26 */ |
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142:4eea097334d6 | 199 | opaPosSelAPORT1XCH28 = VDAC_OPA_MUX_POSSEL_APORT1XCH28, /**< APORT1XCH28 */ |
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142:4eea097334d6 | 200 | opaPosSelAPORT1XCH30 = VDAC_OPA_MUX_POSSEL_APORT1XCH30, /**< APORT1XCH30 */ |
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142:4eea097334d6 | 201 | opaPosSelAPORT2XCH1 = VDAC_OPA_MUX_POSSEL_APORT2XCH1, /**< APORT2XCH1 */ |
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142:4eea097334d6 | 202 | opaPosSelAPORT2XCH3 = VDAC_OPA_MUX_POSSEL_APORT2XCH3, /**< APORT2XCH3 */ |
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142:4eea097334d6 | 203 | opaPosSelAPORT2XCH5 = VDAC_OPA_MUX_POSSEL_APORT2XCH5, /**< APORT2XCH5 */ |
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142:4eea097334d6 | 204 | opaPosSelAPORT2XCH7 = VDAC_OPA_MUX_POSSEL_APORT2XCH7, /**< APORT2XCH7 */ |
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142:4eea097334d6 | 205 | opaPosSelAPORT2XCH9 = VDAC_OPA_MUX_POSSEL_APORT2XCH9, /**< APORT2XCH9 */ |
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142:4eea097334d6 | 206 | opaPosSelAPORT2XCH11 = VDAC_OPA_MUX_POSSEL_APORT2XCH11, /**< APORT2XCH11 */ |
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142:4eea097334d6 | 207 | opaPosSelAPORT2XCH13 = VDAC_OPA_MUX_POSSEL_APORT2XCH13, /**< APORT2XCH13 */ |
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142:4eea097334d6 | 208 | opaPosSelAPORT2XCH15 = VDAC_OPA_MUX_POSSEL_APORT2XCH15, /**< APORT2XCH15 */ |
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142:4eea097334d6 | 209 | opaPosSelAPORT2XCH17 = VDAC_OPA_MUX_POSSEL_APORT2XCH17, /**< APORT2XCH17 */ |
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142:4eea097334d6 | 210 | opaPosSelAPORT2XCH19 = VDAC_OPA_MUX_POSSEL_APORT2XCH19, /**< APORT2XCH19 */ |
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142:4eea097334d6 | 211 | opaPosSelAPORT2XCH21 = VDAC_OPA_MUX_POSSEL_APORT2XCH21, /**< APORT2XCH21 */ |
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142:4eea097334d6 | 212 | opaPosSelAPORT2XCH23 = VDAC_OPA_MUX_POSSEL_APORT2XCH23, /**< APORT2XCH23 */ |
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142:4eea097334d6 | 213 | opaPosSelAPORT2XCH25 = VDAC_OPA_MUX_POSSEL_APORT2XCH25, /**< APORT2XCH25 */ |
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142:4eea097334d6 | 214 | opaPosSelAPORT2XCH27 = VDAC_OPA_MUX_POSSEL_APORT2XCH27, /**< APORT2XCH27 */ |
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142:4eea097334d6 | 215 | opaPosSelAPORT2XCH29 = VDAC_OPA_MUX_POSSEL_APORT2XCH29, /**< APORT2XCH29 */ |
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142:4eea097334d6 | 216 | opaPosSelAPORT2XCH31 = VDAC_OPA_MUX_POSSEL_APORT2XCH31, /**< APORT2XCH31 */ |
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142:4eea097334d6 | 217 | opaPosSelAPORT3XCH0 = VDAC_OPA_MUX_POSSEL_APORT3XCH0, /**< APORT3XCH0 */ |
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142:4eea097334d6 | 218 | opaPosSelAPORT3XCH2 = VDAC_OPA_MUX_POSSEL_APORT3XCH2, /**< APORT3XCH2 */ |
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142:4eea097334d6 | 219 | opaPosSelAPORT3XCH4 = VDAC_OPA_MUX_POSSEL_APORT3XCH4, /**< APORT3XCH4 */ |
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142:4eea097334d6 | 220 | opaPosSelAPORT3XCH6 = VDAC_OPA_MUX_POSSEL_APORT3XCH6, /**< APORT3XCH6 */ |
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142:4eea097334d6 | 221 | opaPosSelAPORT3XCH8 = VDAC_OPA_MUX_POSSEL_APORT3XCH8, /**< APORT3XCH8 */ |
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142:4eea097334d6 | 222 | opaPosSelAPORT3XCH10 = VDAC_OPA_MUX_POSSEL_APORT3XCH10, /**< APORT3XCH10 */ |
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142:4eea097334d6 | 223 | opaPosSelAPORT3XCH12 = VDAC_OPA_MUX_POSSEL_APORT3XCH12, /**< APORT3XCH12 */ |
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142:4eea097334d6 | 224 | opaPosSelAPORT3XCH14 = VDAC_OPA_MUX_POSSEL_APORT3XCH14, /**< APORT3XCH14 */ |
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142:4eea097334d6 | 225 | opaPosSelAPORT3XCH16 = VDAC_OPA_MUX_POSSEL_APORT3XCH16, /**< APORT3XCH16 */ |
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142:4eea097334d6 | 226 | opaPosSelAPORT3XCH18 = VDAC_OPA_MUX_POSSEL_APORT3XCH18, /**< APORT3XCH18 */ |
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142:4eea097334d6 | 227 | opaPosSelAPORT3XCH20 = VDAC_OPA_MUX_POSSEL_APORT3XCH20, /**< APORT3XCH20 */ |
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142:4eea097334d6 | 228 | opaPosSelAPORT3XCH22 = VDAC_OPA_MUX_POSSEL_APORT3XCH22, /**< APORT3XCH22 */ |
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142:4eea097334d6 | 229 | opaPosSelAPORT3XCH24 = VDAC_OPA_MUX_POSSEL_APORT3XCH24, /**< APORT3XCH24 */ |
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142:4eea097334d6 | 230 | opaPosSelAPORT3XCH26 = VDAC_OPA_MUX_POSSEL_APORT3XCH26, /**< APORT3XCH26 */ |
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142:4eea097334d6 | 231 | opaPosSelAPORT3XCH28 = VDAC_OPA_MUX_POSSEL_APORT3XCH28, /**< APORT3XCH28 */ |
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142:4eea097334d6 | 232 | opaPosSelAPORT3XCH30 = VDAC_OPA_MUX_POSSEL_APORT3XCH30, /**< APORT3XCH30 */ |
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142:4eea097334d6 | 233 | opaPosSelAPORT4XCH1 = VDAC_OPA_MUX_POSSEL_APORT4XCH1, /**< APORT4XCH1 */ |
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142:4eea097334d6 | 234 | opaPosSelAPORT4XCH3 = VDAC_OPA_MUX_POSSEL_APORT4XCH3, /**< APORT4XCH3 */ |
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142:4eea097334d6 | 235 | opaPosSelAPORT4XCH5 = VDAC_OPA_MUX_POSSEL_APORT4XCH5, /**< APORT4XCH5 */ |
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142:4eea097334d6 | 236 | opaPosSelAPORT4XCH7 = VDAC_OPA_MUX_POSSEL_APORT4XCH7, /**< APORT4XCH7 */ |
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142:4eea097334d6 | 237 | opaPosSelAPORT4XCH9 = VDAC_OPA_MUX_POSSEL_APORT4XCH9, /**< APORT4XCH9 */ |
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142:4eea097334d6 | 238 | opaPosSelAPORT4XCH11 = VDAC_OPA_MUX_POSSEL_APORT4XCH11, /**< APORT4XCH11 */ |
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142:4eea097334d6 | 239 | opaPosSelAPORT4XCH13 = VDAC_OPA_MUX_POSSEL_APORT4XCH13, /**< APORT4XCH13 */ |
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142:4eea097334d6 | 240 | opaPosSelAPORT4XCH15 = VDAC_OPA_MUX_POSSEL_APORT4XCH15, /**< APORT4XCH15 */ |
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142:4eea097334d6 | 241 | opaPosSelAPORT4XCH17 = VDAC_OPA_MUX_POSSEL_APORT4XCH17, /**< APORT4XCH17 */ |
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142:4eea097334d6 | 242 | opaPosSelAPORT4XCH19 = VDAC_OPA_MUX_POSSEL_APORT4XCH19, /**< APORT4XCH19 */ |
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142:4eea097334d6 | 243 | opaPosSelAPORT4XCH21 = VDAC_OPA_MUX_POSSEL_APORT4XCH21, /**< APORT4XCH21 */ |
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142:4eea097334d6 | 244 | opaPosSelAPORT4XCH23 = VDAC_OPA_MUX_POSSEL_APORT4XCH23, /**< APORT4XCH23 */ |
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142:4eea097334d6 | 245 | opaPosSelAPORT4XCH25 = VDAC_OPA_MUX_POSSEL_APORT4XCH25, /**< APORT4XCH25 */ |
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142:4eea097334d6 | 246 | opaPosSelAPORT4XCH27 = VDAC_OPA_MUX_POSSEL_APORT4XCH27, /**< APORT4XCH27 */ |
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142:4eea097334d6 | 247 | opaPosSelAPORT4XCH29 = VDAC_OPA_MUX_POSSEL_APORT4XCH29, /**< APORT4XCH29 */ |
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142:4eea097334d6 | 248 | opaPosSelAPORT4XCH31 = VDAC_OPA_MUX_POSSEL_APORT4XCH31, /**< APORT4XCH31 */ |
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142:4eea097334d6 | 249 | opaPosSelDisable = VDAC_OPA_MUX_POSSEL_DISABLE, /**< Input disabled. */ |
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142:4eea097334d6 | 250 | opaPosSelDac = VDAC_OPA_MUX_POSSEL_DAC, /**< DAC as input (not OPA2). */ |
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142:4eea097334d6 | 251 | opaPosSelPosPad = VDAC_OPA_MUX_POSSEL_POSPAD, /**< Positive pad as input. */ |
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142:4eea097334d6 | 252 | opaPosSelOpaIn = VDAC_OPA_MUX_POSSEL_OPANEXT, /**< Input from OPAx. */ |
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142:4eea097334d6 | 253 | opaPosSelResTap = VDAC_OPA_MUX_POSSEL_OPATAP /**< Feedback resistor ladder tap. */ |
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142:4eea097334d6 | 254 | #endif /* defined(_SILICON_LABS_32B_SERIES_0) */ |
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142:4eea097334d6 | 255 | } OPAMP_PosSel_TypeDef; |
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142:4eea097334d6 | 256 | |
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142:4eea097334d6 | 257 | /** OPAMP output terminal selection values. */ |
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160:5571c4ff569f | 258 | typedef enum { |
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142:4eea097334d6 | 259 | #if defined(_SILICON_LABS_32B_SERIES_0) |
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142:4eea097334d6 | 260 | opaOutModeDisable = DAC_OPA0MUX_OUTMODE_DISABLE, /**< OPA output disabled. */ |
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142:4eea097334d6 | 261 | opaOutModeMain = DAC_OPA0MUX_OUTMODE_MAIN, /**< Main output to pin enabled. */ |
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142:4eea097334d6 | 262 | opaOutModeAlt = DAC_OPA0MUX_OUTMODE_ALT, /**< Alternate output(s) enabled (not OPA2). */ |
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142:4eea097334d6 | 263 | opaOutModeAll = DAC_OPA0MUX_OUTMODE_ALL /**< Both main and alternate enabled (not OPA2). */ |
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142:4eea097334d6 | 264 | #elif defined(_SILICON_LABS_32B_SERIES_1) |
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142:4eea097334d6 | 265 | opaOutModeDisable = 0, /**< OPA output disabled. */ |
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142:4eea097334d6 | 266 | opaOutModeMain = VDAC_OPA_OUT_MAINOUTEN, /**< Main output to pin enabled. */ |
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142:4eea097334d6 | 267 | opaOutModeAlt = VDAC_OPA_OUT_ALTOUTEN, /**< Alternate output(s) enabled (not OPA2). */ |
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142:4eea097334d6 | 268 | opaOutModeAll = VDAC_OPA_OUT_SHORT, /**< Both main and alternate enabled (not OPA2). */ |
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142:4eea097334d6 | 269 | opaOutModeAPORT1YCH1 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1), /**< APORT output to APORT1YCH1 pin enabled. */ |
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142:4eea097334d6 | 270 | opaOutModeAPORT1YCH3 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3), /**< APORT output to APORT1YCH3 pin enabled. */ |
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142:4eea097334d6 | 271 | opaOutModeAPORT1YCH5 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5), /**< APORT output to APORT1YCH5 pin enabled. */ |
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142:4eea097334d6 | 272 | opaOutModeAPORT1YCH7 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7), /**< APORT output to APORT1YCH7 pin enabled. */ |
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142:4eea097334d6 | 273 | opaOutModeAPORT1YCH9 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9), /**< APORT output to APORT1YCH9 pin enabled. */ |
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142:4eea097334d6 | 274 | opaOutModeAPORT1YCH11 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11), /**< APORT output to APORT1YCH11 pin enabled. */ |
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142:4eea097334d6 | 275 | opaOutModeAPORT1YCH13 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13), /**< APORT output to APORT1YCH13 pin enabled. */ |
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142:4eea097334d6 | 276 | opaOutModeAPORT1YCH15 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15), /**< APORT output to APORT1YCH15 pin enabled. */ |
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142:4eea097334d6 | 277 | opaOutModeAPORT1YCH17 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17), /**< APORT output to APORT1YCH17 pin enabled. */ |
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142:4eea097334d6 | 278 | opaOutModeAPORT1YCH19 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19), /**< APORT output to APORT1YCH19 pin enabled. */ |
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142:4eea097334d6 | 279 | opaOutModeAPORT1YCH21 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21), /**< APORT output to APORT1YCH21 pin enabled. */ |
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142:4eea097334d6 | 280 | opaOutModeAPORT1YCH23 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23), /**< APORT output to APORT1YCH23 pin enabled. */ |
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142:4eea097334d6 | 281 | opaOutModeAPORT1YCH25 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25), /**< APORT output to APORT1YCH25 pin enabled. */ |
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142:4eea097334d6 | 282 | opaOutModeAPORT1YCH27 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27), /**< APORT output to APORT1YCH27 pin enabled. */ |
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142:4eea097334d6 | 283 | opaOutModeAPORT1YCH29 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29), /**< APORT output to APORT1YCH29 pin enabled. */ |
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142:4eea097334d6 | 284 | opaOutModeAPORT1YCH31 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31), /**< APORT output to APORT1YCH31 pin enabled. */ |
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142:4eea097334d6 | 285 | opaOutModeAPORT2YCH0 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0), /**< APORT output to APORT2YCH0 pin enabled. */ |
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142:4eea097334d6 | 286 | opaOutModeAPORT2YCH2 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2), /**< APORT output to APORT2YCH2 pin enabled. */ |
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142:4eea097334d6 | 287 | opaOutModeAPORT2YCH4 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4), /**< APORT output to APORT2YCH4 pin enabled. */ |
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142:4eea097334d6 | 288 | opaOutModeAPORT2YCH6 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6), /**< APORT output to APORT2YCH6 pin enabled. */ |
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142:4eea097334d6 | 289 | opaOutModeAPORT2YCH8 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8), /**< APORT output to APORT2YCH8 pin enabled. */ |
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142:4eea097334d6 | 290 | opaOutModeAPORT2YCH10 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10), /**< APORT output to APORT2YCH10 pin enabled. */ |
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142:4eea097334d6 | 291 | opaOutModeAPORT2YCH12 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12), /**< APORT output to APORT2YCH12 pin enabled. */ |
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142:4eea097334d6 | 292 | opaOutModeAPORT2YCH14 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14), /**< APORT output to APORT2YCH14 pin enabled. */ |
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142:4eea097334d6 | 293 | opaOutModeAPORT2YCH16 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16), /**< APORT output to APORT2YCH16 pin enabled. */ |
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142:4eea097334d6 | 294 | opaOutModeAPORT2YCH18 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18), /**< APORT output to APORT2YCH18 pin enabled. */ |
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142:4eea097334d6 | 295 | opaOutModeAPORT2YCH20 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20), /**< APORT output to APORT2YCH20 pin enabled. */ |
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142:4eea097334d6 | 296 | opaOutModeAPORT2YCH22 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22), /**< APORT output to APORT2YCH22 pin enabled. */ |
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142:4eea097334d6 | 297 | opaOutModeAPORT2YCH24 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24), /**< APORT output to APORT2YCH24 pin enabled. */ |
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142:4eea097334d6 | 298 | opaOutModeAPORT2YCH26 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26), /**< APORT output to APORT2YCH26 pin enabled. */ |
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142:4eea097334d6 | 299 | opaOutModeAPORT2YCH28 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28), /**< APORT output to APORT2YCH28 pin enabled. */ |
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142:4eea097334d6 | 300 | opaOutModeAPORT2YCH30 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30), /**< APORT output to APORT2YCH30 pin enabled. */ |
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142:4eea097334d6 | 301 | opaOutModeAPORT3YCH1 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1), /**< APORT output to APORT3YCH1 pin enabled. */ |
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142:4eea097334d6 | 302 | opaOutModeAPORT3YCH3 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3), /**< APORT output to APORT3YCH3 pin enabled. */ |
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142:4eea097334d6 | 303 | opaOutModeAPORT3YCH5 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5), /**< APORT output to APORT3YCH5 pin enabled. */ |
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142:4eea097334d6 | 304 | opaOutModeAPORT3YCH7 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7), /**< APORT output to APORT3YCH7 pin enabled. */ |
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142:4eea097334d6 | 305 | opaOutModeAPORT3YCH9 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9), /**< APORT output to APORT3YCH9 pin enabled. */ |
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142:4eea097334d6 | 306 | opaOutModeAPORT3YCH11 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11), /**< APORT output to APORT3YCH11 pin enabled. */ |
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142:4eea097334d6 | 307 | opaOutModeAPORT3YCH13 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13), /**< APORT output to APORT3YCH13 pin enabled. */ |
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142:4eea097334d6 | 308 | opaOutModeAPORT3YCH15 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15), /**< APORT output to APORT3YCH15 pin enabled. */ |
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142:4eea097334d6 | 309 | opaOutModeAPORT3YCH17 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17), /**< APORT output to APORT3YCH17 pin enabled. */ |
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142:4eea097334d6 | 310 | opaOutModeAPORT3YCH19 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19), /**< APORT output to APORT3YCH19 pin enabled. */ |
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142:4eea097334d6 | 311 | opaOutModeAPORT3YCH21 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21), /**< APORT output to APORT3YCH21 pin enabled. */ |
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142:4eea097334d6 | 312 | opaOutModeAPORT3YCH23 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23), /**< APORT output to APORT3YCH23 pin enabled. */ |
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142:4eea097334d6 | 313 | opaOutModeAPORT3YCH25 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25), /**< APORT output to APORT3YCH25 pin enabled. */ |
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142:4eea097334d6 | 314 | opaOutModeAPORT3YCH27 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27), /**< APORT output to APORT3YCH27 pin enabled. */ |
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142:4eea097334d6 | 315 | opaOutModeAPORT3YCH29 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29), /**< APORT output to APORT3YCH29 pin enabled. */ |
Anna Bridge |
142:4eea097334d6 | 316 | opaOutModeAPORT3YCH31 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31), /**< APORT output to APORT3YCH31 pin enabled. */ |
Anna Bridge |
142:4eea097334d6 | 317 | opaOutModeAPORT4YCH0 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0), /**< APORT output to APORT4YCH0 pin enabled. */ |
Anna Bridge |
142:4eea097334d6 | 318 | opaOutModeAPORT4YCH2 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2), /**< APORT output to APORT4YCH2 pin enabled. */ |
Anna Bridge |
142:4eea097334d6 | 319 | opaOutModeAPORT4YCH4 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4), /**< APORT output to APORT4YCH4 pin enabled. */ |
Anna Bridge |
142:4eea097334d6 | 320 | opaOutModeAPORT4YCH6 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6), /**< APORT output to APORT4YCH6 pin enabled. */ |
Anna Bridge |
142:4eea097334d6 | 321 | opaOutModeAPORT4YCH8 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8), /**< APORT output to APORT4YCH8 pin enabled. */ |
Anna Bridge |
142:4eea097334d6 | 322 | opaOutModeAPORT4YCH10 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10), /**< APORT output to APORT4YCH10 pin enabled. */ |
Anna Bridge |
142:4eea097334d6 | 323 | opaOutModeAPORT4YCH12 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12), /**< APORT output to APORT4YCH12 pin enabled. */ |
Anna Bridge |
142:4eea097334d6 | 324 | opaOutModeAPORT4YCH14 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14), /**< APORT output to APORT4YCH14 pin enabled. */ |
Anna Bridge |
142:4eea097334d6 | 325 | opaOutModeAPORT4YCH16 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16), /**< APORT output to APORT4YCH16 pin enabled. */ |
Anna Bridge |
142:4eea097334d6 | 326 | opaOutModeAPORT4YCH18 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18), /**< APORT output to APORT4YCH18 pin enabled. */ |
Anna Bridge |
142:4eea097334d6 | 327 | opaOutModeAPORT4YCH20 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20), /**< APORT output to APORT4YCH20 pin enabled. */ |
Anna Bridge |
142:4eea097334d6 | 328 | opaOutModeAPORT4YCH22 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22), /**< APORT output to APORT4YCH22 pin enabled. */ |
Anna Bridge |
142:4eea097334d6 | 329 | opaOutModeAPORT4YCH24 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24), /**< APORT output to APORT4YCH24 pin enabled. */ |
Anna Bridge |
142:4eea097334d6 | 330 | opaOutModeAPORT4YCH26 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26), /**< APORT output to APORT4YCH26 pin enabled. */ |
Anna Bridge |
142:4eea097334d6 | 331 | opaOutModeAPORT4YCH28 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28), /**< APORT output to APORT4YCH28 pin enabled. */ |
Anna Bridge |
142:4eea097334d6 | 332 | opaOutModeAPORT4YCH30 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30), /**< APORT output to APORT4YCH30 pin enabled. */ |
Anna Bridge |
142:4eea097334d6 | 333 | #endif /* defined(_SILICON_LABS_32B_SERIES_0) */ |
Anna Bridge |
142:4eea097334d6 | 334 | } OPAMP_OutMode_TypeDef; |
Anna Bridge |
142:4eea097334d6 | 335 | |
Anna Bridge |
142:4eea097334d6 | 336 | /** OPAMP gain values. */ |
Anna Bridge |
160:5571c4ff569f | 337 | typedef enum { |
Anna Bridge |
142:4eea097334d6 | 338 | #if defined(_SILICON_LABS_32B_SERIES_0) |
Anna Bridge |
142:4eea097334d6 | 339 | opaResSelDefault = DAC_OPA0MUX_RESSEL_DEFAULT, /**< Default value when resistor ladder is unused. */ |
Anna Bridge |
142:4eea097334d6 | 340 | opaResSelR2eq0_33R1 = DAC_OPA0MUX_RESSEL_RES0, /**< R2 = 0.33 * R1 */ |
Anna Bridge |
142:4eea097334d6 | 341 | opaResSelR2eqR1 = DAC_OPA0MUX_RESSEL_RES1, /**< R2 = R1 */ |
Anna Bridge |
142:4eea097334d6 | 342 | opaResSelR1eq1_67R1 = DAC_OPA0MUX_RESSEL_RES2, /**< R2 = 1.67 R1 */ |
Anna Bridge |
142:4eea097334d6 | 343 | opaResSelR2eq2R1 = DAC_OPA0MUX_RESSEL_RES3, /**< R2 = 2 * R1 */ |
Anna Bridge |
142:4eea097334d6 | 344 | opaResSelR2eq3R1 = DAC_OPA0MUX_RESSEL_RES4, /**< R2 = 3 * R1 */ |
Anna Bridge |
142:4eea097334d6 | 345 | opaResSelR2eq4_33R1 = DAC_OPA0MUX_RESSEL_RES5, /**< R2 = 4.33 * R1 */ |
Anna Bridge |
142:4eea097334d6 | 346 | opaResSelR2eq7R1 = DAC_OPA0MUX_RESSEL_RES6, /**< R2 = 7 * R1 */ |
Anna Bridge |
142:4eea097334d6 | 347 | opaResSelR2eq15R1 = DAC_OPA0MUX_RESSEL_RES7 /**< R2 = 15 * R1 */ |
Anna Bridge |
142:4eea097334d6 | 348 | #elif defined(_SILICON_LABS_32B_SERIES_1) |
Anna Bridge |
142:4eea097334d6 | 349 | opaResSelDefault = VDAC_OPA_MUX_RESSEL_DEFAULT, /**< Default value when resistor ladder is unused. */ |
Anna Bridge |
142:4eea097334d6 | 350 | opaResSelR2eq0_33R1 = VDAC_OPA_MUX_RESSEL_RES0, /**< R2 = 0.33 * R1 */ |
Anna Bridge |
142:4eea097334d6 | 351 | opaResSelR2eqR1 = VDAC_OPA_MUX_RESSEL_RES1, /**< R2 = R1 */ |
Anna Bridge |
142:4eea097334d6 | 352 | opaResSelR1eq1_67R1 = VDAC_OPA_MUX_RESSEL_RES2, /**< R2 = 1.67 R1 */ |
Anna Bridge |
142:4eea097334d6 | 353 | opaResSelR2eq2_2R1 = VDAC_OPA_MUX_RESSEL_RES3, /**< R2 = 2.2 * R1 */ |
Anna Bridge |
142:4eea097334d6 | 354 | opaResSelR2eq3R1 = VDAC_OPA_MUX_RESSEL_RES4, /**< R2 = 3 * R1 */ |
Anna Bridge |
142:4eea097334d6 | 355 | opaResSelR2eq4_33R1 = VDAC_OPA_MUX_RESSEL_RES5, /**< R2 = 4.33 * R1 */ |
Anna Bridge |
142:4eea097334d6 | 356 | opaResSelR2eq7R1 = VDAC_OPA_MUX_RESSEL_RES6, /**< R2 = 7 * R1 */ |
Anna Bridge |
142:4eea097334d6 | 357 | opaResSelR2eq15R1 = VDAC_OPA_MUX_RESSEL_RES7 /**< R2 = 15 * R1 */ |
Anna Bridge |
142:4eea097334d6 | 358 | #endif /* defined(_SILICON_LABS_32B_SERIES_0) */ |
Anna Bridge |
142:4eea097334d6 | 359 | } OPAMP_ResSel_TypeDef; |
Anna Bridge |
142:4eea097334d6 | 360 | |
Anna Bridge |
142:4eea097334d6 | 361 | /** OPAMP resistor ladder input selector values. */ |
Anna Bridge |
160:5571c4ff569f | 362 | typedef enum { |
Anna Bridge |
142:4eea097334d6 | 363 | #if defined(_SILICON_LABS_32B_SERIES_0) |
Anna Bridge |
142:4eea097334d6 | 364 | opaResInMuxDisable = DAC_OPA0MUX_RESINMUX_DISABLE, /**< Resistor ladder disabled. */ |
Anna Bridge |
142:4eea097334d6 | 365 | opaResInMuxOpaIn = DAC_OPA0MUX_RESINMUX_OPA0INP, /**< Input from OPAx. */ |
Anna Bridge |
142:4eea097334d6 | 366 | opaResInMuxNegPad = DAC_OPA0MUX_RESINMUX_NEGPAD, /**< Input from negative pad. */ |
Anna Bridge |
142:4eea097334d6 | 367 | opaResInMuxPosPad = DAC_OPA0MUX_RESINMUX_POSPAD, /**< Input from positive pad. */ |
Anna Bridge |
142:4eea097334d6 | 368 | opaResInMuxVss = DAC_OPA0MUX_RESINMUX_VSS /**< Input connected to Vss. */ |
Anna Bridge |
142:4eea097334d6 | 369 | #elif defined(_SILICON_LABS_32B_SERIES_1) |
Anna Bridge |
142:4eea097334d6 | 370 | opaResInMuxDisable = VDAC_OPA_MUX_RESINMUX_DISABLE, /**< Resistor ladder disabled. */ |
Anna Bridge |
142:4eea097334d6 | 371 | opaResInMuxOpaIn = VDAC_OPA_MUX_RESINMUX_OPANEXT, /**< Input from OPAx. */ |
Anna Bridge |
142:4eea097334d6 | 372 | opaResInMuxNegPad = VDAC_OPA_MUX_RESINMUX_NEGPAD, /**< Input from negative pad. */ |
Anna Bridge |
142:4eea097334d6 | 373 | opaResInMuxPosPad = VDAC_OPA_MUX_RESINMUX_POSPAD, /**< Input from positive pad. */ |
Anna Bridge |
142:4eea097334d6 | 374 | opaResInMuxComPad = VDAC_OPA_MUX_RESINMUX_COMPAD, /**< Input from negative pad of OPA0. |
Anna Bridge |
142:4eea097334d6 | 375 | Direct input to support common reference. */ |
Anna Bridge |
142:4eea097334d6 | 376 | opaResInMuxCenter = VDAC_OPA_MUX_RESINMUX_CENTER, /**< OPA0 and OPA1 Resmux connected to form fully |
Anna Bridge |
142:4eea097334d6 | 377 | differential instrumentation amplifier. */ |
Anna Bridge |
142:4eea097334d6 | 378 | opaResInMuxVss = VDAC_OPA_MUX_RESINMUX_VSS, /**< Input connected to Vss. */ |
Anna Bridge |
142:4eea097334d6 | 379 | #endif /* defined(_SILICON_LABS_32B_SERIES_0) */ |
Anna Bridge |
142:4eea097334d6 | 380 | } OPAMP_ResInMux_TypeDef; |
Anna Bridge |
142:4eea097334d6 | 381 | |
Anna Bridge |
142:4eea097334d6 | 382 | #if defined(_SILICON_LABS_32B_SERIES_1) |
Anna Bridge |
160:5571c4ff569f | 383 | typedef enum { |
Anna Bridge |
142:4eea097334d6 | 384 | opaPrsModeDefault = VDAC_OPA_CTRL_PRSMODE_DEFAULT, /**< Default value when PRS is not the trigger. */ |
Anna Bridge |
142:4eea097334d6 | 385 | opaPrsModePulsed = VDAC_OPA_CTRL_PRSMODE_PULSED, /**< PRS trigger is a pulse that starts the OPAMP |
Anna Bridge |
142:4eea097334d6 | 386 | warmup sequence. The end of the warmup sequence |
Anna Bridge |
142:4eea097334d6 | 387 | is controlled by timeout settings in OPAxTIMER. */ |
Anna Bridge |
142:4eea097334d6 | 388 | opaPrsModeTimed = VDAC_OPA_CTRL_PRSMODE_TIMED, /**< PRS trigger is a pulse long enough to provide the |
Anna Bridge |
142:4eea097334d6 | 389 | OPAMP warmup sequence. The end of the warmup |
Anna Bridge |
142:4eea097334d6 | 390 | sequence is controlled by the edge of the pulse. */ |
Anna Bridge |
142:4eea097334d6 | 391 | } OPAMP_PrsMode_TypeDef; |
Anna Bridge |
142:4eea097334d6 | 392 | |
Anna Bridge |
160:5571c4ff569f | 393 | typedef enum { |
Anna Bridge |
142:4eea097334d6 | 394 | opaPrsSelDefault = VDAC_OPA_CTRL_PRSSEL_DEFAULT, /**< Default value when PRS is not the trigger. */ |
Anna Bridge |
142:4eea097334d6 | 395 | opaPrsSelCh0 = VDAC_OPA_CTRL_PRSSEL_PRSCH0, /**< PRS channel 0 triggers OPAMP. */ |
Anna Bridge |
142:4eea097334d6 | 396 | opaPrsSelCh1 = VDAC_OPA_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1 triggers OPAMP. */ |
Anna Bridge |
142:4eea097334d6 | 397 | opaPrsSelCh2 = VDAC_OPA_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2 triggers OPAMP. */ |
Anna Bridge |
142:4eea097334d6 | 398 | opaPrsSelCh3 = VDAC_OPA_CTRL_PRSSEL_PRSCH3, /**< PRS channel 3 triggers OPAMP. */ |
Anna Bridge |
142:4eea097334d6 | 399 | opaPrsSelCh4 = VDAC_OPA_CTRL_PRSSEL_PRSCH4, /**< PRS channel 4 triggers OPAMP. */ |
Anna Bridge |
142:4eea097334d6 | 400 | opaPrsSelCh5 = VDAC_OPA_CTRL_PRSSEL_PRSCH5, /**< PRS channel 5 triggers OPAMP. */ |
Anna Bridge |
142:4eea097334d6 | 401 | opaPrsSelCh6 = VDAC_OPA_CTRL_PRSSEL_PRSCH6, /**< PRS channel 6 triggers OPAMP. */ |
Anna Bridge |
142:4eea097334d6 | 402 | opaPrsSelCh7 = VDAC_OPA_CTRL_PRSSEL_PRSCH7, /**< PRS channel 7 triggers OPAMP. */ |
Anna Bridge |
160:5571c4ff569f | 403 | #if defined(VDAC_OPA_CTRL_PRSSEL_PRSCH8) |
Anna Bridge |
142:4eea097334d6 | 404 | opaPrsSelCh8 = VDAC_OPA_CTRL_PRSSEL_PRSCH8, /**< PRS channel 8 triggers OPAMP. */ |
Anna Bridge |
142:4eea097334d6 | 405 | opaPrsSelCh9 = VDAC_OPA_CTRL_PRSSEL_PRSCH9, /**< PRS channel 9 triggers OPAMP. */ |
Anna Bridge |
142:4eea097334d6 | 406 | opaPrsSelCh10 = VDAC_OPA_CTRL_PRSSEL_PRSCH10, /**< PRS channel 10 triggers OPAMP. */ |
Anna Bridge |
142:4eea097334d6 | 407 | opaPrsSelCh11 = VDAC_OPA_CTRL_PRSSEL_PRSCH11, /**< PRS channel 11 triggers OPAMP. */ |
Anna Bridge |
160:5571c4ff569f | 408 | #endif |
Anna Bridge |
142:4eea097334d6 | 409 | } OPAMP_PrsSel_TypeDef; |
Anna Bridge |
142:4eea097334d6 | 410 | |
Anna Bridge |
160:5571c4ff569f | 411 | typedef enum { |
Anna Bridge |
142:4eea097334d6 | 412 | opaPrsOutDefault = VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT, /**< Default value. */ |
Anna Bridge |
142:4eea097334d6 | 413 | opaPrsOutWarm = VDAC_OPA_CTRL_PRSOUTMODE_WARM, /**< Warm status available on PRS. */ |
Anna Bridge |
142:4eea097334d6 | 414 | opaPrsOutOutValid = VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID, /**< Outvalid status available on PRS. */ |
Anna Bridge |
142:4eea097334d6 | 415 | } OPAMP_PrsOut_TypeDef; |
Anna Bridge |
142:4eea097334d6 | 416 | |
Anna Bridge |
160:5571c4ff569f | 417 | typedef enum { |
Anna Bridge |
142:4eea097334d6 | 418 | opaOutScaleDefault = VDAC_OPA_CTRL_OUTSCALE_DEFAULT, /**< Default OPAM output drive strength. */ |
Anna Bridge |
142:4eea097334d6 | 419 | opaOutScaleFull = VDAC_OPA_CTRL_OUTSCALE_FULL, /**< OPAMP uses full output drive strength. */ |
Anna Bridge |
142:4eea097334d6 | 420 | opaOutSacleHalf = VDAC_OPA_CTRL_OUTSCALE_HALF, /**< OPAMP uses half output drive strength. */ |
Anna Bridge |
142:4eea097334d6 | 421 | } OPAMP_OutScale_Typedef; |
Anna Bridge |
142:4eea097334d6 | 422 | |
Anna Bridge |
160:5571c4ff569f | 423 | typedef enum { |
Anna Bridge |
142:4eea097334d6 | 424 | opaDrvStrDefault = VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT, /**< Default value. */ |
Anna Bridge |
142:4eea097334d6 | 425 | opaDrvStrLowerAccLowStr = (0 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Lower accuracy with low drive stregth. */ |
Anna Bridge |
142:4eea097334d6 | 426 | opaDrvStrLowAccLowStr = (1 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Low accuracy with low drive stregth. */ |
Anna Bridge |
142:4eea097334d6 | 427 | opaDrvStrHighAccHighStr = (2 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< High accuracy with high drive stregth. */ |
Anna Bridge |
142:4eea097334d6 | 428 | opaDrvStrHigherAccHighStr = (3 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Higher accuracy with high drive stregth. */ |
Anna Bridge |
142:4eea097334d6 | 429 | } OPAMP_DrvStr_Typedef; |
Anna Bridge |
142:4eea097334d6 | 430 | #endif /* defined(_SILICON_LABS_32B_SERIES_0) */ |
Anna Bridge |
142:4eea097334d6 | 431 | |
Anna Bridge |
142:4eea097334d6 | 432 | /******************************************************************************* |
Anna Bridge |
142:4eea097334d6 | 433 | ******************************* STRUCTS *********************************** |
Anna Bridge |
142:4eea097334d6 | 434 | ******************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 435 | |
Anna Bridge |
142:4eea097334d6 | 436 | /** OPAMP init structure. */ |
Anna Bridge |
160:5571c4ff569f | 437 | typedef struct { |
Anna Bridge |
142:4eea097334d6 | 438 | OPAMP_NegSel_TypeDef negSel; /**< Select input source for negative terminal. */ |
Anna Bridge |
142:4eea097334d6 | 439 | OPAMP_PosSel_TypeDef posSel; /**< Select input source for positive terminal. */ |
Anna Bridge |
142:4eea097334d6 | 440 | OPAMP_OutMode_TypeDef outMode; /**< Output terminal connection. */ |
Anna Bridge |
142:4eea097334d6 | 441 | OPAMP_ResSel_TypeDef resSel; /**< Select R2/R1 resistor ratio. */ |
Anna Bridge |
142:4eea097334d6 | 442 | OPAMP_ResInMux_TypeDef resInMux; /**< Select input source for resistor ladder. */ |
Anna Bridge |
142:4eea097334d6 | 443 | uint32_t outPen; /**< Alternate output enable bit mask. This value |
Anna Bridge |
142:4eea097334d6 | 444 | should consist of one or more of the |
Anna Bridge |
142:4eea097334d6 | 445 | @if DOXYDOC_P1_DEVICE |
Anna Bridge |
142:4eea097334d6 | 446 | DAC_OPA[opa#]MUX_OUTPEN_OUT[output#] flags |
Anna Bridge |
142:4eea097334d6 | 447 | (defined in \<part_name\>_dac.h) OR'ed together. |
Anna Bridge |
142:4eea097334d6 | 448 | @n @n |
Anna Bridge |
142:4eea097334d6 | 449 | For OPA0: |
Anna Bridge |
142:4eea097334d6 | 450 | @li DAC_OPA0MUX_OUTPEN_OUT0 |
Anna Bridge |
142:4eea097334d6 | 451 | @li DAC_OPA0MUX_OUTPEN_OUT1 |
Anna Bridge |
142:4eea097334d6 | 452 | @li DAC_OPA0MUX_OUTPEN_OUT2 |
Anna Bridge |
142:4eea097334d6 | 453 | @li DAC_OPA0MUX_OUTPEN_OUT3 |
Anna Bridge |
142:4eea097334d6 | 454 | @li DAC_OPA0MUX_OUTPEN_OUT4 |
Anna Bridge |
142:4eea097334d6 | 455 | |
Anna Bridge |
142:4eea097334d6 | 456 | For OPA1: |
Anna Bridge |
142:4eea097334d6 | 457 | @li DAC_OPA1MUX_OUTPEN_OUT0 |
Anna Bridge |
142:4eea097334d6 | 458 | @li DAC_OPA1MUX_OUTPEN_OUT1 |
Anna Bridge |
142:4eea097334d6 | 459 | @li DAC_OPA1MUX_OUTPEN_OUT2 |
Anna Bridge |
142:4eea097334d6 | 460 | @li DAC_OPA1MUX_OUTPEN_OUT3 |
Anna Bridge |
142:4eea097334d6 | 461 | @li DAC_OPA1MUX_OUTPEN_OUT4 |
Anna Bridge |
142:4eea097334d6 | 462 | |
Anna Bridge |
142:4eea097334d6 | 463 | For OPA2: |
Anna Bridge |
142:4eea097334d6 | 464 | @li DAC_OPA2MUX_OUTPEN_OUT0 |
Anna Bridge |
142:4eea097334d6 | 465 | @li DAC_OPA2MUX_OUTPEN_OUT1 |
Anna Bridge |
142:4eea097334d6 | 466 | |
Anna Bridge |
142:4eea097334d6 | 467 | E.g: @n |
Anna Bridge |
142:4eea097334d6 | 468 | init.outPen = DAC_OPA0MUX_OUTPEN_OUT0 | |
Anna Bridge |
142:4eea097334d6 | 469 | DAC_OPA0MUX_OUTPEN_OUT2 | |
Anna Bridge |
142:4eea097334d6 | 470 | DAC_OPA0MUX_OUTPEN_OUT4; |
Anna Bridge |
142:4eea097334d6 | 471 | |
Anna Bridge |
142:4eea097334d6 | 472 | @elseif DOXYDOC_P2_DEVICE |
Anna Bridge |
142:4eea097334d6 | 473 | VDAC_OPA_OUT_ALTOUTPADEN_OUT[output#] flags |
Anna Bridge |
142:4eea097334d6 | 474 | (defined in \<part_name\>_vdac.h) OR'ed together. |
Anna Bridge |
142:4eea097334d6 | 475 | @n @n |
Anna Bridge |
142:4eea097334d6 | 476 | @li VDAC_OPA_OUT_ALTOUTPADEN_OUT0 |
Anna Bridge |
142:4eea097334d6 | 477 | @li VDAC_OPA_OUT_ALTOUTPADEN_OUT1 |
Anna Bridge |
142:4eea097334d6 | 478 | @li VDAC_OPA_OUT_ALTOUTPADEN_OUT2 |
Anna Bridge |
142:4eea097334d6 | 479 | @li VDAC_OPA_OUT_ALTOUTPADEN_OUT3 |
Anna Bridge |
142:4eea097334d6 | 480 | @li VDAC_OPA_OUT_ALTOUTPADEN_OUT4 |
Anna Bridge |
142:4eea097334d6 | 481 | |
Anna Bridge |
142:4eea097334d6 | 482 | E.g: @n |
Anna Bridge |
142:4eea097334d6 | 483 | init.outPen = VDAC_OPA_OUT_ALTOUTPADEN_OUT0 | |
Anna Bridge |
142:4eea097334d6 | 484 | VDAC_OPA_OUT_ALTOUTPADEN_OUT2 | |
Anna Bridge |
142:4eea097334d6 | 485 | VDAC_OPA_OUT_ALTOUTPADEN_OUT4; |
Anna Bridge |
142:4eea097334d6 | 486 | @endif */ |
Anna Bridge |
142:4eea097334d6 | 487 | #if defined(_SILICON_LABS_32B_SERIES_0) |
Anna Bridge |
142:4eea097334d6 | 488 | uint32_t bias; /**< Set OPAMP bias current. */ |
Anna Bridge |
142:4eea097334d6 | 489 | bool halfBias; /**< Divide OPAMP bias current by 2. */ |
Anna Bridge |
142:4eea097334d6 | 490 | bool lpfPosPadDisable; /**< Disable low pass filter on positive pad. */ |
Anna Bridge |
142:4eea097334d6 | 491 | bool lpfNegPadDisable; /**< Disable low pass filter on negative pad. */ |
Anna Bridge |
142:4eea097334d6 | 492 | bool nextOut; /**< Enable NEXTOUT signal source. */ |
Anna Bridge |
142:4eea097334d6 | 493 | bool npEn; /**< Enable positive pad. */ |
Anna Bridge |
142:4eea097334d6 | 494 | bool ppEn; /**< Enable negative pad. */ |
Anna Bridge |
142:4eea097334d6 | 495 | bool shortInputs; /**< Short OPAMP input terminals. */ |
Anna Bridge |
142:4eea097334d6 | 496 | bool hcmDisable; /**< Disable input rail-to-rail capability. */ |
Anna Bridge |
142:4eea097334d6 | 497 | bool defaultOffset; /**< Use factory calibrated opamp offset value. */ |
Anna Bridge |
142:4eea097334d6 | 498 | uint32_t offset; /**< Opamp offset value when @ref defaultOffset is |
Anna Bridge |
142:4eea097334d6 | 499 | false. */ |
Anna Bridge |
142:4eea097334d6 | 500 | #elif defined(_SILICON_LABS_32B_SERIES_1) |
Anna Bridge |
142:4eea097334d6 | 501 | OPAMP_DrvStr_Typedef drvStr; /**< OPAx operation mode. */ |
Anna Bridge |
142:4eea097334d6 | 502 | bool gain3xEn; /**< Enable 3x gain resistor ladder. */ |
Anna Bridge |
142:4eea097334d6 | 503 | bool halfDrvStr; /**< Half or full output drive strength. */ |
Anna Bridge |
142:4eea097334d6 | 504 | bool ugBwScale; /**< Unity gain bandwidth scaled by factor of 2.5. */ |
Anna Bridge |
142:4eea097334d6 | 505 | bool prsEn; /**< Enable PRS as OPAMP trigger. */ |
Anna Bridge |
142:4eea097334d6 | 506 | OPAMP_PrsMode_TypeDef prsMode; /**< Selects PRS trigger mode. */ |
Anna Bridge |
142:4eea097334d6 | 507 | OPAMP_PrsSel_TypeDef prsSel; /**< PRS channel trigger select. */ |
Anna Bridge |
142:4eea097334d6 | 508 | OPAMP_PrsOut_TypeDef prsOutSel; /**< PRS output select. */ |
Anna Bridge |
142:4eea097334d6 | 509 | bool aportYMasterDisable; /**< Disable bus master request on APORT Y. */ |
Anna Bridge |
142:4eea097334d6 | 510 | bool aportXMasterDisable; /**< Disable bus master request on APORT X. */ |
Anna Bridge |
142:4eea097334d6 | 511 | uint32_t settleTime; /**< Number of clock cycles to drive the output. */ |
Anna Bridge |
142:4eea097334d6 | 512 | uint32_t startupDly; /**< OPAx startup delay in us. */ |
Anna Bridge |
142:4eea097334d6 | 513 | bool hcmDisable; /**< Disable input rail-to-rail capability. */ |
Anna Bridge |
142:4eea097334d6 | 514 | bool defaultOffsetN; /**< Use factory calibrated opamp inverting input |
Anna Bridge |
142:4eea097334d6 | 515 | offset value. */ |
Anna Bridge |
142:4eea097334d6 | 516 | uint32_t offsetN; /**< Opamp inverting input offset value when |
Anna Bridge |
142:4eea097334d6 | 517 | @ref defaultOffsetInv is false. */ |
Anna Bridge |
142:4eea097334d6 | 518 | bool defaultOffsetP; /**< Use factory calibrated opamp non-inverting |
Anna Bridge |
142:4eea097334d6 | 519 | input offset value. */ |
Anna Bridge |
142:4eea097334d6 | 520 | uint32_t offsetP; /**< Opamp non-inverting input offset value when |
Anna Bridge |
142:4eea097334d6 | 521 | @ref defaultOffsetNon is false. */ |
Anna Bridge |
142:4eea097334d6 | 522 | #endif /* defined(_SILICON_LABS_32B_SERIES_1) */ |
Anna Bridge |
142:4eea097334d6 | 523 | } OPAMP_Init_TypeDef; |
Anna Bridge |
142:4eea097334d6 | 524 | |
Anna Bridge |
142:4eea097334d6 | 525 | #if defined(_SILICON_LABS_32B_SERIES_0) |
Anna Bridge |
142:4eea097334d6 | 526 | /** Configuration of OPA0/1 in unity gain voltage follower mode. */ |
Anna Bridge |
142:4eea097334d6 | 527 | #define OPA_INIT_UNITY_GAIN \ |
Anna Bridge |
160:5571c4ff569f | 528 | { \ |
Anna Bridge |
160:5571c4ff569f | 529 | opaNegSelUnityGain, /* Unity gain. */ \ |
Anna Bridge |
160:5571c4ff569f | 530 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 531 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 532 | opaResSelDefault, /* Resistor ladder is not used. */ \ |
Anna Bridge |
160:5571c4ff569f | 533 | opaResInMuxDisable, /* Resistor ladder disabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 534 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 535 | _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 536 | _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 537 | false, /* No low pass filter on pos pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 538 | false, /* No low pass filter on neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 539 | false, /* No nextout output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 540 | false, /* Neg pad disabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 541 | true, /* Pos pad enabled, used as signal input. */ \ |
Anna Bridge |
160:5571c4ff569f | 542 | false, /* No shorting of inputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 543 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 544 | true, /* Use factory calibrated opamp offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 545 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 546 | } |
Anna Bridge |
142:4eea097334d6 | 547 | |
Anna Bridge |
142:4eea097334d6 | 548 | /** Configuration of OPA2 in unity gain voltage follower mode. */ |
Anna Bridge |
142:4eea097334d6 | 549 | #define OPA_INIT_UNITY_GAIN_OPA2 \ |
Anna Bridge |
160:5571c4ff569f | 550 | { \ |
Anna Bridge |
160:5571c4ff569f | 551 | opaNegSelUnityGain, /* Unity gain. */ \ |
Anna Bridge |
160:5571c4ff569f | 552 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 553 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 554 | opaResSelDefault, /* Resistor ladder is not used. */ \ |
Anna Bridge |
160:5571c4ff569f | 555 | opaResInMuxDisable, /* Resistor ladder disabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 556 | DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 557 | _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 558 | _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 559 | false, /* No low pass filter on pos pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 560 | false, /* No low pass filter on neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 561 | false, /* No nextout output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 562 | false, /* Neg pad disabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 563 | true, /* Pos pad enabled, used as signal input. */ \ |
Anna Bridge |
160:5571c4ff569f | 564 | false, /* No shorting of inputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 565 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 566 | true, /* Use factory calibrated opamp offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 567 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 568 | } |
Anna Bridge |
142:4eea097334d6 | 569 | |
Anna Bridge |
142:4eea097334d6 | 570 | /** Configuration of OPA0/1 in non-inverting amplifier mode. */ |
Anna Bridge |
142:4eea097334d6 | 571 | #define OPA_INIT_NON_INVERTING \ |
Anna Bridge |
160:5571c4ff569f | 572 | { \ |
Anna Bridge |
160:5571c4ff569f | 573 | opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 574 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 575 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 576 | opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 577 | opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 578 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 579 | _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 580 | _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 581 | false, /* No low pass filter on pos pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 582 | false, /* No low pass filter on neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 583 | false, /* No nextout output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 584 | true, /* Neg pad enabled, used as signal ground. */ \ |
Anna Bridge |
160:5571c4ff569f | 585 | true, /* Pos pad enabled, used as signal input. */ \ |
Anna Bridge |
160:5571c4ff569f | 586 | false, /* No shorting of inputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 587 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 588 | true, /* Use factory calibrated opamp offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 589 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 590 | } |
Anna Bridge |
142:4eea097334d6 | 591 | |
Anna Bridge |
142:4eea097334d6 | 592 | /** Configuration of OPA2 in non-inverting amplifier mode. */ |
Anna Bridge |
142:4eea097334d6 | 593 | #define OPA_INIT_NON_INVERTING_OPA2 \ |
Anna Bridge |
160:5571c4ff569f | 594 | { \ |
Anna Bridge |
160:5571c4ff569f | 595 | opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 596 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 597 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 598 | opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 599 | opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 600 | DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 601 | _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 602 | _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 603 | false, /* No low pass filter on pos pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 604 | false, /* No low pass filter on neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 605 | false, /* No nextout output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 606 | true, /* Neg pad enabled, used as signal ground. */ \ |
Anna Bridge |
160:5571c4ff569f | 607 | true, /* Pos pad enabled, used as signal input. */ \ |
Anna Bridge |
160:5571c4ff569f | 608 | false, /* No shorting of inputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 609 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 610 | true, /* Use factory calibrated opamp offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 611 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 612 | } |
Anna Bridge |
142:4eea097334d6 | 613 | |
Anna Bridge |
142:4eea097334d6 | 614 | /** Configuration of OPA0/1 in inverting amplifier mode. */ |
Anna Bridge |
142:4eea097334d6 | 615 | #define OPA_INIT_INVERTING \ |
Anna Bridge |
160:5571c4ff569f | 616 | { \ |
Anna Bridge |
160:5571c4ff569f | 617 | opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 618 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 619 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 620 | opaResSelR2eqR1, /* R2 = R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 621 | opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 622 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 623 | _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 624 | _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 625 | false, /* No low pass filter on pos pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 626 | false, /* No low pass filter on neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 627 | false, /* No nextout output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 628 | true, /* Neg pad enabled, used as signal input. */ \ |
Anna Bridge |
160:5571c4ff569f | 629 | true, /* Pos pad enabled, used as signal ground. */ \ |
Anna Bridge |
160:5571c4ff569f | 630 | false, /* No shorting of inputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 631 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 632 | true, /* Use factory calibrated opamp offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 633 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 634 | } |
Anna Bridge |
142:4eea097334d6 | 635 | |
Anna Bridge |
142:4eea097334d6 | 636 | /** Configuration of OPA2 in inverting amplifier mode. */ |
Anna Bridge |
142:4eea097334d6 | 637 | #define OPA_INIT_INVERTING_OPA2 \ |
Anna Bridge |
160:5571c4ff569f | 638 | { \ |
Anna Bridge |
160:5571c4ff569f | 639 | opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 640 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 641 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 642 | opaResSelR2eqR1, /* R2 = R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 643 | opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 644 | DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 645 | _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 646 | _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 647 | false, /* No low pass filter on pos pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 648 | false, /* No low pass filter on neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 649 | false, /* No nextout output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 650 | true, /* Neg pad enabled, used as signal input. */ \ |
Anna Bridge |
160:5571c4ff569f | 651 | true, /* Pos pad enabled, used as signal ground. */ \ |
Anna Bridge |
160:5571c4ff569f | 652 | false, /* No shorting of inputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 653 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 654 | true, /* Use factory calibrated opamp offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 655 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 656 | } |
Anna Bridge |
142:4eea097334d6 | 657 | |
Anna Bridge |
142:4eea097334d6 | 658 | /** Configuration of OPA0 in cascaded non-inverting amplifier mode. */ |
Anna Bridge |
142:4eea097334d6 | 659 | #define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \ |
Anna Bridge |
160:5571c4ff569f | 660 | { \ |
Anna Bridge |
160:5571c4ff569f | 661 | opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 662 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 663 | opaOutModeAll, /* Both main and alternate outputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 664 | opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 665 | opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 666 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 667 | _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 668 | _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 669 | false, /* No low pass filter on pos pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 670 | false, /* No low pass filter on neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 671 | true, /* Pass output to next stage (OPA1). */ \ |
Anna Bridge |
160:5571c4ff569f | 672 | true, /* Neg pad enabled, used as signal ground. */ \ |
Anna Bridge |
160:5571c4ff569f | 673 | true, /* Pos pad enabled, used as signal input. */ \ |
Anna Bridge |
160:5571c4ff569f | 674 | false, /* No shorting of inputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 675 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 676 | true, /* Use factory calibrated opamp offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 677 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 678 | } |
Anna Bridge |
142:4eea097334d6 | 679 | |
Anna Bridge |
142:4eea097334d6 | 680 | /** Configuration of OPA1 in cascaded non-inverting amplifier mode. */ |
Anna Bridge |
142:4eea097334d6 | 681 | #define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \ |
Anna Bridge |
160:5571c4ff569f | 682 | { \ |
Anna Bridge |
160:5571c4ff569f | 683 | opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 684 | opaPosSelOpaIn, /* Pos input from OPA0 output. */ \ |
Anna Bridge |
160:5571c4ff569f | 685 | opaOutModeAll, /* Both main and alternate outputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 686 | opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 687 | opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 688 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 689 | _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 690 | _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 691 | false, /* No low pass filter on pos pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 692 | false, /* No low pass filter on neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 693 | true, /* Pass output to next stage (OPA2). */ \ |
Anna Bridge |
160:5571c4ff569f | 694 | true, /* Neg pad enabled, used as signal ground. */ \ |
Anna Bridge |
160:5571c4ff569f | 695 | false, /* Pos pad disabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 696 | false, /* No shorting of inputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 697 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 698 | true, /* Use factory calibrated opamp offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 699 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 700 | } |
Anna Bridge |
142:4eea097334d6 | 701 | |
Anna Bridge |
142:4eea097334d6 | 702 | /** Configuration of OPA2 in cascaded non-inverting amplifier mode. */ |
Anna Bridge |
142:4eea097334d6 | 703 | #define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \ |
Anna Bridge |
160:5571c4ff569f | 704 | { \ |
Anna Bridge |
160:5571c4ff569f | 705 | opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 706 | opaPosSelOpaIn, /* Pos input from OPA1 output. */ \ |
Anna Bridge |
160:5571c4ff569f | 707 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 708 | opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 709 | opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 710 | DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 711 | _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 712 | _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 713 | false, /* No low pass filter on pos pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 714 | false, /* No low pass filter on neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 715 | false, /* No nextout output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 716 | true, /* Neg pad enabled, used as signal ground. */ \ |
Anna Bridge |
160:5571c4ff569f | 717 | false, /* Pos pad disabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 718 | false, /* No shorting of inputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 719 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 720 | true, /* Use factory calibrated opamp offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 721 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 722 | } |
Anna Bridge |
142:4eea097334d6 | 723 | |
Anna Bridge |
142:4eea097334d6 | 724 | /** Configuration of OPA0 in cascaded inverting amplifier mode. */ |
Anna Bridge |
142:4eea097334d6 | 725 | #define OPA_INIT_CASCADED_INVERTING_OPA0 \ |
Anna Bridge |
160:5571c4ff569f | 726 | { \ |
Anna Bridge |
160:5571c4ff569f | 727 | opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 728 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 729 | opaOutModeAll, /* Both main and alternate outputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 730 | opaResSelR2eqR1, /* R2 = R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 731 | opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 732 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 733 | _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 734 | _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 735 | false, /* No low pass filter on pos pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 736 | false, /* No low pass filter on neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 737 | true, /* Pass output to next stage (OPA1). */ \ |
Anna Bridge |
160:5571c4ff569f | 738 | true, /* Neg pad enabled, used as signal input. */ \ |
Anna Bridge |
160:5571c4ff569f | 739 | true, /* Pos pad enabled, used as signal ground. */ \ |
Anna Bridge |
160:5571c4ff569f | 740 | false, /* No shorting of inputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 741 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 742 | true, /* Use factory calibrated opamp offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 743 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 744 | } |
Anna Bridge |
142:4eea097334d6 | 745 | |
Anna Bridge |
142:4eea097334d6 | 746 | /** Configuration of OPA1 in cascaded inverting amplifier mode. */ |
Anna Bridge |
142:4eea097334d6 | 747 | #define OPA_INIT_CASCADED_INVERTING_OPA1 \ |
Anna Bridge |
160:5571c4ff569f | 748 | { \ |
Anna Bridge |
160:5571c4ff569f | 749 | opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 750 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 751 | opaOutModeAll, /* Both main and alternate outputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 752 | opaResSelR2eqR1, /* R2 = R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 753 | opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ |
Anna Bridge |
160:5571c4ff569f | 754 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 755 | _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 756 | _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 757 | false, /* No low pass filter on pos pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 758 | false, /* No low pass filter on neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 759 | true, /* Pass output to next stage (OPA2). */ \ |
Anna Bridge |
160:5571c4ff569f | 760 | false, /* Neg pad disabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 761 | true, /* Pos pad enabled, used as signal ground. */ \ |
Anna Bridge |
160:5571c4ff569f | 762 | false, /* No shorting of inputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 763 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 764 | true, /* Use factory calibrated opamp offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 765 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 766 | } |
Anna Bridge |
142:4eea097334d6 | 767 | |
Anna Bridge |
142:4eea097334d6 | 768 | /** Configuration of OPA2 in cascaded inverting amplifier mode. */ |
Anna Bridge |
142:4eea097334d6 | 769 | #define OPA_INIT_CASCADED_INVERTING_OPA2 \ |
Anna Bridge |
160:5571c4ff569f | 770 | { \ |
Anna Bridge |
160:5571c4ff569f | 771 | opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 772 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 773 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 774 | opaResSelR2eqR1, /* R2 = R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 775 | opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ |
Anna Bridge |
160:5571c4ff569f | 776 | DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 777 | _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 778 | _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 779 | false, /* No low pass filter on pos pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 780 | false, /* No low pass filter on neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 781 | false, /* No nextout output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 782 | false, /* Neg pad disabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 783 | true, /* Pos pad enabled, used as signal ground. */ \ |
Anna Bridge |
160:5571c4ff569f | 784 | false, /* No shorting of inputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 785 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 786 | true, /* Use factory calibrated opamp offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 787 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 788 | } |
Anna Bridge |
142:4eea097334d6 | 789 | |
Anna Bridge |
142:4eea097334d6 | 790 | /** Configuration of OPA0 in two-opamp differential driver mode. */ |
Anna Bridge |
142:4eea097334d6 | 791 | #define OPA_INIT_DIFF_DRIVER_OPA0 \ |
Anna Bridge |
160:5571c4ff569f | 792 | { \ |
Anna Bridge |
160:5571c4ff569f | 793 | opaNegSelUnityGain, /* Unity gain. */ \ |
Anna Bridge |
160:5571c4ff569f | 794 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 795 | opaOutModeAll, /* Both main and alternate outputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 796 | opaResSelDefault, /* Resistor ladder is not used. */ \ |
Anna Bridge |
160:5571c4ff569f | 797 | opaResInMuxDisable, /* Resistor ladder disabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 798 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 799 | _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 800 | _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 801 | false, /* No low pass filter on pos pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 802 | false, /* No low pass filter on neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 803 | true, /* Pass output to next stage (OPA1). */ \ |
Anna Bridge |
160:5571c4ff569f | 804 | false, /* Neg pad disabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 805 | true, /* Pos pad enabled, used as signal input. */ \ |
Anna Bridge |
160:5571c4ff569f | 806 | false, /* No shorting of inputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 807 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 808 | true, /* Use factory calibrated opamp offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 809 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 810 | } |
Anna Bridge |
142:4eea097334d6 | 811 | |
Anna Bridge |
142:4eea097334d6 | 812 | /** Configuration of OPA1 in two-opamp differential driver mode. */ |
Anna Bridge |
142:4eea097334d6 | 813 | #define OPA_INIT_DIFF_DRIVER_OPA1 \ |
Anna Bridge |
160:5571c4ff569f | 814 | { \ |
Anna Bridge |
160:5571c4ff569f | 815 | opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 816 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 817 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 818 | opaResSelR2eqR1, /* R2 = R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 819 | opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ |
Anna Bridge |
160:5571c4ff569f | 820 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 821 | _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 822 | _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 823 | false, /* No low pass filter on pos pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 824 | false, /* No low pass filter on neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 825 | false, /* No nextout output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 826 | false, /* Neg pad disabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 827 | true, /* Pos pad enabled, used as signal ground. */ \ |
Anna Bridge |
160:5571c4ff569f | 828 | false, /* No shorting of inputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 829 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 830 | true, /* Use factory calibrated opamp offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 831 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 832 | } |
Anna Bridge |
142:4eea097334d6 | 833 | |
Anna Bridge |
142:4eea097334d6 | 834 | /** Configuration of OPA0 in three-opamp differential receiver mode. */ |
Anna Bridge |
142:4eea097334d6 | 835 | #define OPA_INIT_DIFF_RECEIVER_OPA0 \ |
Anna Bridge |
160:5571c4ff569f | 836 | { \ |
Anna Bridge |
160:5571c4ff569f | 837 | opaNegSelUnityGain, /* Unity gain. */ \ |
Anna Bridge |
160:5571c4ff569f | 838 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 839 | opaOutModeAll, /* Both main and alternate outputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 840 | opaResSelR2eqR1, /* R2 = R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 841 | opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 842 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 843 | _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 844 | _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 845 | false, /* No low pass filter on pos pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 846 | false, /* No low pass filter on neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 847 | true, /* Pass output to next stage (OPA2). */ \ |
Anna Bridge |
160:5571c4ff569f | 848 | true, /* Neg pad enabled, used as signal ground. */ \ |
Anna Bridge |
160:5571c4ff569f | 849 | true, /* Pos pad enabled, used as signal input. */ \ |
Anna Bridge |
160:5571c4ff569f | 850 | false, /* No shorting of inputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 851 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 852 | true, /* Use factory calibrated opamp offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 853 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 854 | } |
Anna Bridge |
142:4eea097334d6 | 855 | |
Anna Bridge |
142:4eea097334d6 | 856 | /** Configuration of OPA1 in three-opamp differential receiver mode. */ |
Anna Bridge |
142:4eea097334d6 | 857 | #define OPA_INIT_DIFF_RECEIVER_OPA1 \ |
Anna Bridge |
160:5571c4ff569f | 858 | { \ |
Anna Bridge |
160:5571c4ff569f | 859 | opaNegSelUnityGain, /* Unity gain. */ \ |
Anna Bridge |
160:5571c4ff569f | 860 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 861 | opaOutModeAll, /* Both main and alternate outputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 862 | opaResSelDefault, /* Resistor ladder is not used. */ \ |
Anna Bridge |
160:5571c4ff569f | 863 | opaResInMuxDisable, /* Disable resistor ladder. */ \ |
Anna Bridge |
160:5571c4ff569f | 864 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 865 | _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 866 | _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 867 | false, /* No low pass filter on pos pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 868 | false, /* No low pass filter on neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 869 | true, /* Pass output to next stage (OPA2). */ \ |
Anna Bridge |
160:5571c4ff569f | 870 | false, /* Neg pad disabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 871 | true, /* Pos pad enabled, used as signal input. */ \ |
Anna Bridge |
160:5571c4ff569f | 872 | false, /* No shorting of inputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 873 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 874 | true, /* Use factory calibrated opamp offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 875 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 876 | } |
Anna Bridge |
142:4eea097334d6 | 877 | |
Anna Bridge |
142:4eea097334d6 | 878 | /** Configuration of OPA2 in three-opamp differential receiver mode. */ |
Anna Bridge |
142:4eea097334d6 | 879 | #define OPA_INIT_DIFF_RECEIVER_OPA2 \ |
Anna Bridge |
160:5571c4ff569f | 880 | { \ |
Anna Bridge |
160:5571c4ff569f | 881 | opaNegSelResTap, /* Input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 882 | opaPosSelResTapOpa0, /* Input from OPA0 resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 883 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 884 | opaResSelR2eqR1, /* R2 = R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 885 | opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ |
Anna Bridge |
160:5571c4ff569f | 886 | DAC_OPA0MUX_OUTPEN_OUT0, /* Enable alternate output 0. */ \ |
Anna Bridge |
160:5571c4ff569f | 887 | _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 888 | _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 889 | false, /* No low pass filter on pos pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 890 | false, /* No low pass filter on neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 891 | false, /* No nextout output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 892 | false, /* Neg pad disabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 893 | false, /* Pos pad disabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 894 | false, /* No shorting of inputs. */ \ |
Anna Bridge |
160:5571c4ff569f | 895 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 896 | true, /* Use factory calibrated opamp offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 897 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 898 | } |
Anna Bridge |
142:4eea097334d6 | 899 | |
Anna Bridge |
142:4eea097334d6 | 900 | #elif defined(_SILICON_LABS_32B_SERIES_1) |
Anna Bridge |
142:4eea097334d6 | 901 | /** Configuration of OPA in unity gain voltage follower mode. */ |
Anna Bridge |
142:4eea097334d6 | 902 | #define OPA_INIT_UNITY_GAIN \ |
Anna Bridge |
160:5571c4ff569f | 903 | { \ |
Anna Bridge |
160:5571c4ff569f | 904 | opaNegSelUnityGain, /* Unity gain. */ \ |
Anna Bridge |
160:5571c4ff569f | 905 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 906 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 907 | opaResSelDefault, /* Resistor ladder is not used. */ \ |
Anna Bridge |
160:5571c4ff569f | 908 | opaResInMuxDisable, /* Resistor ladder disabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 909 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 910 | opaDrvStrDefault, /* Default opamp operation mode. */ \ |
Anna Bridge |
160:5571c4ff569f | 911 | false, /* Disable 3x gain setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 912 | false, /* Use full output drive strength. */ \ |
Anna Bridge |
160:5571c4ff569f | 913 | false, /* Disable unity-gain bandwidth scaling. */ \ |
Anna Bridge |
160:5571c4ff569f | 914 | false, /* Opamp triggered by OPAxEN. */ \ |
Anna Bridge |
160:5571c4ff569f | 915 | opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 916 | opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 917 | opaPrsOutDefault, /* Default PRS output setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 918 | false, /* Bus mastering enabled on APORTX. */ \ |
Anna Bridge |
160:5571c4ff569f | 919 | false, /* Bus mastering enabled on APORTY. */ \ |
Anna Bridge |
160:5571c4ff569f | 920 | 3, /* 3us settle time with default DrvStr. */ \ |
Anna Bridge |
160:5571c4ff569f | 921 | 0, /* No startup delay. */ \ |
Anna Bridge |
160:5571c4ff569f | 922 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 923 | true, /* Use calibrated inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 924 | 0, /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 925 | true, /* Use calibrated non-inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 926 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 927 | } |
Anna Bridge |
142:4eea097334d6 | 928 | |
Anna Bridge |
142:4eea097334d6 | 929 | /** Configuration of OPA in non-inverting amplifier mode. */ |
Anna Bridge |
142:4eea097334d6 | 930 | #define OPA_INIT_NON_INVERTING \ |
Anna Bridge |
160:5571c4ff569f | 931 | { \ |
Anna Bridge |
160:5571c4ff569f | 932 | opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 933 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 934 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 935 | opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 936 | opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 937 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 938 | opaDrvStrDefault, /* Default opamp operation mode. */ \ |
Anna Bridge |
160:5571c4ff569f | 939 | false, /* Disable 3x gain setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 940 | false, /* Use full output drive strength. */ \ |
Anna Bridge |
160:5571c4ff569f | 941 | false, /* Disable unity-gain bandwidth scaling. */ \ |
Anna Bridge |
160:5571c4ff569f | 942 | false, /* Opamp triggered by OPAxEN. */ \ |
Anna Bridge |
160:5571c4ff569f | 943 | opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 944 | opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 945 | opaPrsOutDefault, /* Default PRS output setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 946 | false, /* Bus mastering enabled on APORTX. */ \ |
Anna Bridge |
160:5571c4ff569f | 947 | false, /* Bus mastering enabled on APORTY. */ \ |
Anna Bridge |
160:5571c4ff569f | 948 | 3, /* 3us settle time with default DrvStr. */ \ |
Anna Bridge |
160:5571c4ff569f | 949 | 0, /* No startup delay. */ \ |
Anna Bridge |
160:5571c4ff569f | 950 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 951 | true, /* Use calibrated inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 952 | 0, /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 953 | true, /* Use calibrated non-inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 954 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 955 | } |
Anna Bridge |
142:4eea097334d6 | 956 | |
Anna Bridge |
142:4eea097334d6 | 957 | /** Configuration of OPA in inverting amplifier mode. */ |
Anna Bridge |
142:4eea097334d6 | 958 | #define OPA_INIT_INVERTING \ |
Anna Bridge |
160:5571c4ff569f | 959 | { \ |
Anna Bridge |
160:5571c4ff569f | 960 | opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 961 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 962 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 963 | opaResSelR2eqR1, /* R2 = R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 964 | opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 965 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 966 | opaDrvStrDefault, /* Default opamp operation mode. */ \ |
Anna Bridge |
160:5571c4ff569f | 967 | false, /* Disable 3x gain setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 968 | false, /* Use full output drive strength. */ \ |
Anna Bridge |
160:5571c4ff569f | 969 | false, /* Disable unity-gain bandwidth scaling. */ \ |
Anna Bridge |
160:5571c4ff569f | 970 | false, /* Opamp triggered by OPAxEN. */ \ |
Anna Bridge |
160:5571c4ff569f | 971 | opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 972 | opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 973 | opaPrsOutDefault, /* Default PRS output setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 974 | false, /* Bus mastering enabled on APORTX. */ \ |
Anna Bridge |
160:5571c4ff569f | 975 | false, /* Bus mastering enabled on APORTY. */ \ |
Anna Bridge |
160:5571c4ff569f | 976 | 3, /* 3us settle time with default DrvStr. */ \ |
Anna Bridge |
160:5571c4ff569f | 977 | 0, /* No startup delay. */ \ |
Anna Bridge |
160:5571c4ff569f | 978 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 979 | true, /* Use calibrated inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 980 | 0, /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 981 | true, /* Use calibrated non-inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 982 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 983 | } |
Anna Bridge |
142:4eea097334d6 | 984 | |
Anna Bridge |
142:4eea097334d6 | 985 | /** Configuration of OPA0 in cascaded non-inverting amplifier mode. */ |
Anna Bridge |
142:4eea097334d6 | 986 | #define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \ |
Anna Bridge |
160:5571c4ff569f | 987 | { \ |
Anna Bridge |
160:5571c4ff569f | 988 | opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 989 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 990 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 991 | opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 992 | opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 993 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 994 | opaDrvStrDefault, /* Default opamp operation mode. */ \ |
Anna Bridge |
160:5571c4ff569f | 995 | false, /* Disable 3x gain setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 996 | false, /* Use full output drive strength. */ \ |
Anna Bridge |
160:5571c4ff569f | 997 | false, /* Disable unity-gain bandwidth scaling. */ \ |
Anna Bridge |
160:5571c4ff569f | 998 | false, /* Opamp triggered by OPAxEN. */ \ |
Anna Bridge |
160:5571c4ff569f | 999 | opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1000 | opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1001 | opaPrsOutDefault, /* Default PRS output setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1002 | false, /* Bus mastering enabled on APORTX. */ \ |
Anna Bridge |
160:5571c4ff569f | 1003 | false, /* Bus mastering enabled on APORTY. */ \ |
Anna Bridge |
160:5571c4ff569f | 1004 | 3, /* 3us settle time with default DrvStr. */ \ |
Anna Bridge |
160:5571c4ff569f | 1005 | 0, /* No startup delay. */ \ |
Anna Bridge |
160:5571c4ff569f | 1006 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1007 | true, /* Use calibrated inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1008 | 0, /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1009 | true, /* Use calibrated non-inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1010 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1011 | } |
Anna Bridge |
142:4eea097334d6 | 1012 | |
Anna Bridge |
142:4eea097334d6 | 1013 | /** Configuration of OPA1 in cascaded non-inverting amplifier mode. */ |
Anna Bridge |
142:4eea097334d6 | 1014 | #define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \ |
Anna Bridge |
160:5571c4ff569f | 1015 | { \ |
Anna Bridge |
160:5571c4ff569f | 1016 | opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 1017 | opaPosSelOpaIn, /* Pos input from OPA0 output. */ \ |
Anna Bridge |
160:5571c4ff569f | 1018 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1019 | opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 1020 | opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 1021 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1022 | opaDrvStrDefault, /* Default opamp operation mode. */ \ |
Anna Bridge |
160:5571c4ff569f | 1023 | false, /* Disable 3x gain setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1024 | false, /* Use full output drive strength. */ \ |
Anna Bridge |
160:5571c4ff569f | 1025 | false, /* Disable unity-gain bandwidth scaling. */ \ |
Anna Bridge |
160:5571c4ff569f | 1026 | false, /* Opamp triggered by OPAxEN. */ \ |
Anna Bridge |
160:5571c4ff569f | 1027 | opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1028 | opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1029 | opaPrsOutDefault, /* Default PRS output setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1030 | false, /* Bus mastering enabled on APORTX. */ \ |
Anna Bridge |
160:5571c4ff569f | 1031 | false, /* Bus mastering enabled on APORTY. */ \ |
Anna Bridge |
160:5571c4ff569f | 1032 | 3, /* 3us settle time with default DrvStr. */ \ |
Anna Bridge |
160:5571c4ff569f | 1033 | 0, /* No startup delay. */ \ |
Anna Bridge |
160:5571c4ff569f | 1034 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1035 | true, /* Use calibrated inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1036 | 0, /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1037 | true, /* Use calibrated non-inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1038 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1039 | } |
Anna Bridge |
142:4eea097334d6 | 1040 | |
Anna Bridge |
142:4eea097334d6 | 1041 | /** Configuration of OPA2 in cascaded non-inverting amplifier mode. */ |
Anna Bridge |
142:4eea097334d6 | 1042 | #define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \ |
Anna Bridge |
160:5571c4ff569f | 1043 | { \ |
Anna Bridge |
160:5571c4ff569f | 1044 | opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 1045 | opaPosSelOpaIn, /* Pos input from OPA1 output. */ \ |
Anna Bridge |
160:5571c4ff569f | 1046 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1047 | opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 1048 | opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 1049 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1050 | opaDrvStrDefault, /* Default opamp operation mode. */ \ |
Anna Bridge |
160:5571c4ff569f | 1051 | false, /* Disable 3x gain setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1052 | false, /* Use full output drive strength. */ \ |
Anna Bridge |
160:5571c4ff569f | 1053 | false, /* Disable unity-gain bandwidth scaling. */ \ |
Anna Bridge |
160:5571c4ff569f | 1054 | false, /* Opamp triggered by OPAxEN. */ \ |
Anna Bridge |
160:5571c4ff569f | 1055 | opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1056 | opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1057 | opaPrsOutDefault, /* Default PRS output setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1058 | false, /* Bus mastering enabled on APORTX. */ \ |
Anna Bridge |
160:5571c4ff569f | 1059 | false, /* Bus mastering enabled on APORTY. */ \ |
Anna Bridge |
160:5571c4ff569f | 1060 | 3, /* 3us settle time with default DrvStr. */ \ |
Anna Bridge |
160:5571c4ff569f | 1061 | 0, /* No startup delay. */ \ |
Anna Bridge |
160:5571c4ff569f | 1062 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1063 | true, /* Use calibrated inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1064 | 0, /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1065 | true, /* Use calibrated non-inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1066 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1067 | } |
Anna Bridge |
142:4eea097334d6 | 1068 | |
Anna Bridge |
142:4eea097334d6 | 1069 | /** Configuration of OPA0 in cascaded inverting amplifier mode. */ |
Anna Bridge |
142:4eea097334d6 | 1070 | #define OPA_INIT_CASCADED_INVERTING_OPA0 \ |
Anna Bridge |
160:5571c4ff569f | 1071 | { \ |
Anna Bridge |
160:5571c4ff569f | 1072 | opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 1073 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 1074 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1075 | opaResSelR2eqR1, /* R2 = R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 1076 | opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 1077 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1078 | opaDrvStrDefault, /* Default opamp operation mode. */ \ |
Anna Bridge |
160:5571c4ff569f | 1079 | false, /* Disable 3x gain setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1080 | false, /* Use full output drive strength. */ \ |
Anna Bridge |
160:5571c4ff569f | 1081 | false, /* Disable unity-gain bandwidth scaling. */ \ |
Anna Bridge |
160:5571c4ff569f | 1082 | false, /* Opamp triggered by OPAxEN. */ \ |
Anna Bridge |
160:5571c4ff569f | 1083 | opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1084 | opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1085 | opaPrsOutDefault, /* Default PRS output setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1086 | false, /* Bus mastering enabled on APORTX. */ \ |
Anna Bridge |
160:5571c4ff569f | 1087 | false, /* Bus mastering enabled on APORTY. */ \ |
Anna Bridge |
160:5571c4ff569f | 1088 | 3, /* 3us settle time with default DrvStr. */ \ |
Anna Bridge |
160:5571c4ff569f | 1089 | 0, /* No startup delay. */ \ |
Anna Bridge |
160:5571c4ff569f | 1090 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1091 | true, /* Use calibrated inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1092 | 0, /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1093 | true, /* Use calibrated non-inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1094 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1095 | } |
Anna Bridge |
142:4eea097334d6 | 1096 | |
Anna Bridge |
142:4eea097334d6 | 1097 | /** Configuration of OPA1 in cascaded inverting amplifier mode. */ |
Anna Bridge |
142:4eea097334d6 | 1098 | #define OPA_INIT_CASCADED_INVERTING_OPA1 \ |
Anna Bridge |
160:5571c4ff569f | 1099 | { \ |
Anna Bridge |
160:5571c4ff569f | 1100 | opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 1101 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 1102 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1103 | opaResSelR2eqR1, /* R2 = R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 1104 | opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ |
Anna Bridge |
160:5571c4ff569f | 1105 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1106 | opaDrvStrDefault, /* Default opamp operation mode. */ \ |
Anna Bridge |
160:5571c4ff569f | 1107 | false, /* Disable 3x gain setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1108 | false, /* Use full output drive strength. */ \ |
Anna Bridge |
160:5571c4ff569f | 1109 | false, /* Disable unity-gain bandwidth scaling. */ \ |
Anna Bridge |
160:5571c4ff569f | 1110 | false, /* Opamp triggered by OPAxEN. */ \ |
Anna Bridge |
160:5571c4ff569f | 1111 | opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1112 | opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1113 | opaPrsOutDefault, /* Default PRS output setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1114 | false, /* Bus mastering enabled on APORTX. */ \ |
Anna Bridge |
160:5571c4ff569f | 1115 | false, /* Bus mastering enabled on APORTY. */ \ |
Anna Bridge |
160:5571c4ff569f | 1116 | 3, /* 3us settle time with default DrvStr. */ \ |
Anna Bridge |
160:5571c4ff569f | 1117 | 0, /* No startup delay. */ \ |
Anna Bridge |
160:5571c4ff569f | 1118 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1119 | true, /* Use calibrated inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1120 | 0, /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1121 | true, /* Use calibrated non-inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1122 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1123 | } |
Anna Bridge |
142:4eea097334d6 | 1124 | |
Anna Bridge |
142:4eea097334d6 | 1125 | /** Configuration of OPA2 in cascaded inverting amplifier mode. */ |
Anna Bridge |
142:4eea097334d6 | 1126 | #define OPA_INIT_CASCADED_INVERTING_OPA2 \ |
Anna Bridge |
160:5571c4ff569f | 1127 | { \ |
Anna Bridge |
160:5571c4ff569f | 1128 | opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 1129 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 1130 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1131 | opaResSelR2eqR1, /* R2 = R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 1132 | opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ |
Anna Bridge |
160:5571c4ff569f | 1133 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1134 | opaDrvStrDefault, /* Default opamp operation mode. */ \ |
Anna Bridge |
160:5571c4ff569f | 1135 | false, /* Disable 3x gain setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1136 | false, /* Use full output drive strength. */ \ |
Anna Bridge |
160:5571c4ff569f | 1137 | false, /* Disable unity-gain bandwidth scaling. */ \ |
Anna Bridge |
160:5571c4ff569f | 1138 | false, /* Opamp triggered by OPAxEN. */ \ |
Anna Bridge |
160:5571c4ff569f | 1139 | opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1140 | opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1141 | opaPrsOutDefault, /* Default PRS output setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1142 | false, /* Bus mastering enabled on APORTX. */ \ |
Anna Bridge |
160:5571c4ff569f | 1143 | false, /* Bus mastering enabled on APORTY. */ \ |
Anna Bridge |
160:5571c4ff569f | 1144 | 3, /* 3us settle time with default DrvStr. */ \ |
Anna Bridge |
160:5571c4ff569f | 1145 | 0, /* No startup delay. */ \ |
Anna Bridge |
160:5571c4ff569f | 1146 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1147 | true, /* Use calibrated inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1148 | 0, /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1149 | true, /* Use calibrated non-inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1150 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1151 | } |
Anna Bridge |
142:4eea097334d6 | 1152 | |
Anna Bridge |
142:4eea097334d6 | 1153 | /** Configuration of OPA0 in two-opamp differential driver mode. */ |
Anna Bridge |
142:4eea097334d6 | 1154 | #define OPA_INIT_DIFF_DRIVER_OPA0 \ |
Anna Bridge |
160:5571c4ff569f | 1155 | { \ |
Anna Bridge |
160:5571c4ff569f | 1156 | opaNegSelUnityGain, /* Unity gain. */ \ |
Anna Bridge |
160:5571c4ff569f | 1157 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 1158 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1159 | opaResSelDefault, /* Resistor ladder is not used. */ \ |
Anna Bridge |
160:5571c4ff569f | 1160 | opaResInMuxDisable, /* Resistor ladder disabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1161 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1162 | opaDrvStrDefault, /* Default opamp operation mode. */ \ |
Anna Bridge |
160:5571c4ff569f | 1163 | false, /* Disable 3x gain setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1164 | false, /* Use full output drive strength. */ \ |
Anna Bridge |
160:5571c4ff569f | 1165 | false, /* Disable unity-gain bandwidth scaling. */ \ |
Anna Bridge |
160:5571c4ff569f | 1166 | false, /* Opamp triggered by OPAxEN. */ \ |
Anna Bridge |
160:5571c4ff569f | 1167 | opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1168 | opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1169 | opaPrsOutDefault, /* Default PRS output setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1170 | false, /* Bus mastering enabled on APORTX. */ \ |
Anna Bridge |
160:5571c4ff569f | 1171 | false, /* Bus mastering enabled on APORTY. */ \ |
Anna Bridge |
160:5571c4ff569f | 1172 | 3, /* 3us settle time with default DrvStr. */ \ |
Anna Bridge |
160:5571c4ff569f | 1173 | 0, /* No startup delay. */ \ |
Anna Bridge |
160:5571c4ff569f | 1174 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1175 | true, /* Use calibrated inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1176 | 0, /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1177 | true, /* Use calibrated non-inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1178 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1179 | } |
Anna Bridge |
142:4eea097334d6 | 1180 | |
Anna Bridge |
142:4eea097334d6 | 1181 | /** Configuration of OPA1 in two-opamp differential driver mode. */ |
Anna Bridge |
142:4eea097334d6 | 1182 | #define OPA_INIT_DIFF_DRIVER_OPA1 \ |
Anna Bridge |
160:5571c4ff569f | 1183 | { \ |
Anna Bridge |
160:5571c4ff569f | 1184 | opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 1185 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 1186 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1187 | opaResSelR2eqR1, /* R2 = R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 1188 | opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ |
Anna Bridge |
160:5571c4ff569f | 1189 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1190 | opaDrvStrDefault, /* Default opamp operation mode. */ \ |
Anna Bridge |
160:5571c4ff569f | 1191 | false, /* Disable 3x gain setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1192 | false, /* Use full output drive strength. */ \ |
Anna Bridge |
160:5571c4ff569f | 1193 | false, /* Disable unity-gain bandwidth scaling. */ \ |
Anna Bridge |
160:5571c4ff569f | 1194 | false, /* Opamp triggered by OPAxEN. */ \ |
Anna Bridge |
160:5571c4ff569f | 1195 | opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1196 | opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1197 | opaPrsOutDefault, /* Default PRS output setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1198 | false, /* Bus mastering enabled on APORTX. */ \ |
Anna Bridge |
160:5571c4ff569f | 1199 | false, /* Bus mastering enabled on APORTY. */ \ |
Anna Bridge |
160:5571c4ff569f | 1200 | 3, /* 3us settle time with default DrvStr. */ \ |
Anna Bridge |
160:5571c4ff569f | 1201 | 0, /* No startup delay. */ \ |
Anna Bridge |
160:5571c4ff569f | 1202 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1203 | true, /* Use calibrated inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1204 | 0, /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1205 | true, /* Use calibrated non-inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1206 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1207 | } |
Anna Bridge |
142:4eea097334d6 | 1208 | |
Anna Bridge |
142:4eea097334d6 | 1209 | /** Configuration of OPA0 in three-opamp differential receiver mode. */ |
Anna Bridge |
142:4eea097334d6 | 1210 | #define OPA_INIT_DIFF_RECEIVER_OPA0 \ |
Anna Bridge |
160:5571c4ff569f | 1211 | { \ |
Anna Bridge |
160:5571c4ff569f | 1212 | opaNegSelUnityGain, /* Unity gain. */ \ |
Anna Bridge |
160:5571c4ff569f | 1213 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 1214 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1215 | opaResSelR2eqR1, /* R2 = R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 1216 | opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 1217 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1218 | opaDrvStrDefault, /* Default opamp operation mode. */ \ |
Anna Bridge |
160:5571c4ff569f | 1219 | false, /* Disable 3x gain setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1220 | false, /* Use full output drive strength. */ \ |
Anna Bridge |
160:5571c4ff569f | 1221 | false, /* Disable unity-gain bandwidth scaling. */ \ |
Anna Bridge |
160:5571c4ff569f | 1222 | false, /* Opamp triggered by OPAxEN. */ \ |
Anna Bridge |
160:5571c4ff569f | 1223 | opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1224 | opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1225 | opaPrsOutDefault, /* Default PRS output setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1226 | false, /* Bus mastering enabled on APORTX. */ \ |
Anna Bridge |
160:5571c4ff569f | 1227 | false, /* Bus mastering enabled on APORTY. */ \ |
Anna Bridge |
160:5571c4ff569f | 1228 | 3, /* 3us settle time with default DrvStr. */ \ |
Anna Bridge |
160:5571c4ff569f | 1229 | 0, /* No startup delay. */ \ |
Anna Bridge |
160:5571c4ff569f | 1230 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1231 | true, /* Use calibrated inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1232 | 0, /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1233 | true, /* Use calibrated non-inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1234 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1235 | } |
Anna Bridge |
142:4eea097334d6 | 1236 | |
Anna Bridge |
142:4eea097334d6 | 1237 | /** Configuration of OPA1 in three-opamp differential receiver mode. */ |
Anna Bridge |
142:4eea097334d6 | 1238 | #define OPA_INIT_DIFF_RECEIVER_OPA1 \ |
Anna Bridge |
160:5571c4ff569f | 1239 | { \ |
Anna Bridge |
160:5571c4ff569f | 1240 | opaNegSelUnityGain, /* Unity gain. */ \ |
Anna Bridge |
160:5571c4ff569f | 1241 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 1242 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1243 | opaResSelDefault, /* Resistor ladder is not used. */ \ |
Anna Bridge |
160:5571c4ff569f | 1244 | opaResInMuxDisable, /* Disable resistor ladder. */ \ |
Anna Bridge |
160:5571c4ff569f | 1245 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1246 | opaDrvStrDefault, /* Default opamp operation mode. */ \ |
Anna Bridge |
160:5571c4ff569f | 1247 | false, /* Disable 3x gain setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1248 | false, /* Use full output drive strength. */ \ |
Anna Bridge |
160:5571c4ff569f | 1249 | false, /* Disable unity-gain bandwidth scaling. */ \ |
Anna Bridge |
160:5571c4ff569f | 1250 | false, /* Opamp triggered by OPAxEN. */ \ |
Anna Bridge |
160:5571c4ff569f | 1251 | opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1252 | opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1253 | opaPrsOutDefault, /* Default PRS output setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1254 | false, /* Bus mastering enabled on APORTX. */ \ |
Anna Bridge |
160:5571c4ff569f | 1255 | false, /* Bus mastering enabled on APORTY. */ \ |
Anna Bridge |
160:5571c4ff569f | 1256 | 3, /* 3us settle time with default DrvStr. */ \ |
Anna Bridge |
160:5571c4ff569f | 1257 | 0, /* No startup delay. */ \ |
Anna Bridge |
160:5571c4ff569f | 1258 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1259 | true, /* Use calibrated inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1260 | 0, /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1261 | true, /* Use calibrated non-inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1262 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1263 | } |
Anna Bridge |
142:4eea097334d6 | 1264 | |
Anna Bridge |
142:4eea097334d6 | 1265 | /** Configuration of OPA2 in three-opamp differential receiver mode. */ |
Anna Bridge |
142:4eea097334d6 | 1266 | #define OPA_INIT_DIFF_RECEIVER_OPA2 \ |
Anna Bridge |
160:5571c4ff569f | 1267 | { \ |
Anna Bridge |
160:5571c4ff569f | 1268 | opaNegSelResTap, /* Input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 1269 | opaPosSelResTap, /* Input from OPA0 resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 1270 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1271 | opaResSelR2eqR1, /* R2 = R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 1272 | opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ |
Anna Bridge |
160:5571c4ff569f | 1273 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1274 | opaDrvStrDefault, /* Default opamp operation mode. */ \ |
Anna Bridge |
160:5571c4ff569f | 1275 | false, /* Disable 3x gain setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1276 | false, /* Use full output drive strength. */ \ |
Anna Bridge |
160:5571c4ff569f | 1277 | false, /* Disable unity-gain bandwidth scaling. */ \ |
Anna Bridge |
160:5571c4ff569f | 1278 | false, /* Opamp triggered by OPAxEN. */ \ |
Anna Bridge |
160:5571c4ff569f | 1279 | opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1280 | opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1281 | opaPrsOutDefault, /* Default PRS output setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1282 | false, /* Bus mastering enabled on APORTX. */ \ |
Anna Bridge |
160:5571c4ff569f | 1283 | false, /* Bus mastering enabled on APORTY. */ \ |
Anna Bridge |
160:5571c4ff569f | 1284 | 3, /* 3us settle time with default DrvStr. */ \ |
Anna Bridge |
160:5571c4ff569f | 1285 | 0, /* No startup delay. */ \ |
Anna Bridge |
160:5571c4ff569f | 1286 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1287 | true, /* Use calibrated inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1288 | 0, /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1289 | true, /* Use calibrated non-inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1290 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1291 | } |
Anna Bridge |
142:4eea097334d6 | 1292 | |
Anna Bridge |
142:4eea097334d6 | 1293 | /** Configuration of OPA0 in two-opamp instrumentation amplifier mode. */ |
Anna Bridge |
142:4eea097334d6 | 1294 | #define OPA_INIT_INSTR_AMP_OPA0 \ |
Anna Bridge |
160:5571c4ff569f | 1295 | { \ |
Anna Bridge |
160:5571c4ff569f | 1296 | opaNegSelResTap, /* Input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 1297 | opaPosSelPosPad, /* Pos input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 1298 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1299 | opaResSelR2eqR1, /* R2 = R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 1300 | opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \ |
Anna Bridge |
160:5571c4ff569f | 1301 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1302 | opaDrvStrDefault, /* Default opamp operation mode. */ \ |
Anna Bridge |
160:5571c4ff569f | 1303 | false, /* Disable 3x gain setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1304 | false, /* Use full output drive strength. */ \ |
Anna Bridge |
160:5571c4ff569f | 1305 | false, /* Disable unity-gain bandwidth scaling. */ \ |
Anna Bridge |
160:5571c4ff569f | 1306 | false, /* Opamp triggered by OPAxEN. */ \ |
Anna Bridge |
160:5571c4ff569f | 1307 | opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1308 | opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1309 | opaPrsOutDefault, /* Default PRS output setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1310 | false, /* Bus mastering enabled on APORTX. */ \ |
Anna Bridge |
160:5571c4ff569f | 1311 | false, /* Bus mastering enabled on APORTY. */ \ |
Anna Bridge |
160:5571c4ff569f | 1312 | 3, /* 3us settle time with default DrvStr. */ \ |
Anna Bridge |
160:5571c4ff569f | 1313 | 0, /* No startup delay. */ \ |
Anna Bridge |
160:5571c4ff569f | 1314 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1315 | true, /* Use calibrated inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1316 | 0, /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1317 | true, /* Use calibrated non-inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1318 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1319 | } |
Anna Bridge |
142:4eea097334d6 | 1320 | |
Anna Bridge |
142:4eea097334d6 | 1321 | /** Configuration of OPA1 in two-opamp instrumentation amplifier mode. */ |
Anna Bridge |
142:4eea097334d6 | 1322 | #define OPA_INIT_INSTR_AMP_OPA1 \ |
Anna Bridge |
160:5571c4ff569f | 1323 | { \ |
Anna Bridge |
160:5571c4ff569f | 1324 | opaNegSelNegPad, /* Neg input from pad. */ \ |
Anna Bridge |
160:5571c4ff569f | 1325 | opaPosSelResTap, /* Input from resistor ladder tap. */ \ |
Anna Bridge |
160:5571c4ff569f | 1326 | opaOutModeMain, /* Main output enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1327 | opaResSelR2eqR1, /* R2 = R1 */ \ |
Anna Bridge |
160:5571c4ff569f | 1328 | opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \ |
Anna Bridge |
160:5571c4ff569f | 1329 | 0, /* No alternate outputs enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1330 | opaDrvStrDefault, /* Default opamp operation mode. */ \ |
Anna Bridge |
160:5571c4ff569f | 1331 | false, /* Disable 3x gain setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1332 | false, /* Use full output drive strength. */ \ |
Anna Bridge |
160:5571c4ff569f | 1333 | false, /* Disable unity-gain bandwidth scaling. */ \ |
Anna Bridge |
160:5571c4ff569f | 1334 | false, /* Opamp triggered by OPAxEN. */ \ |
Anna Bridge |
160:5571c4ff569f | 1335 | opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1336 | opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ |
Anna Bridge |
160:5571c4ff569f | 1337 | opaPrsOutDefault, /* Default PRS output setting. */ \ |
Anna Bridge |
160:5571c4ff569f | 1338 | false, /* Bus mastering enabled on APORTX. */ \ |
Anna Bridge |
160:5571c4ff569f | 1339 | false, /* Bus mastering enabled on APORTY. */ \ |
Anna Bridge |
160:5571c4ff569f | 1340 | 3, /* 3us settle time with default DrvStr. */ \ |
Anna Bridge |
160:5571c4ff569f | 1341 | 0, /* No startup delay. */ \ |
Anna Bridge |
160:5571c4ff569f | 1342 | false, /* Rail-to-rail input enabled. */ \ |
Anna Bridge |
160:5571c4ff569f | 1343 | true, /* Use calibrated inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1344 | 0, /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1345 | true, /* Use calibrated non-inverting offset. */ \ |
Anna Bridge |
160:5571c4ff569f | 1346 | 0 /* Opamp offset value (not used). */ \ |
Anna Bridge |
160:5571c4ff569f | 1347 | } |
Anna Bridge |
142:4eea097334d6 | 1348 | |
Anna Bridge |
142:4eea097334d6 | 1349 | #endif /* defined(_SILICON_LABS_32B_SERIES_0) */ |
Anna Bridge |
142:4eea097334d6 | 1350 | |
Anna Bridge |
142:4eea097334d6 | 1351 | /******************************************************************************* |
Anna Bridge |
142:4eea097334d6 | 1352 | ***************************** PROTOTYPES ********************************** |
Anna Bridge |
142:4eea097334d6 | 1353 | ******************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 1354 | |
Anna Bridge |
142:4eea097334d6 | 1355 | #if defined(_SILICON_LABS_32B_SERIES_0) |
Anna Bridge |
142:4eea097334d6 | 1356 | void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa); |
Anna Bridge |
142:4eea097334d6 | 1357 | void OPAMP_Enable(DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init); |
Anna Bridge |
142:4eea097334d6 | 1358 | #elif defined(_SILICON_LABS_32B_SERIES_1) |
Anna Bridge |
142:4eea097334d6 | 1359 | void OPAMP_Disable(VDAC_TypeDef *dac, OPAMP_TypeDef opa); |
Anna Bridge |
142:4eea097334d6 | 1360 | void OPAMP_Enable(VDAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init); |
Anna Bridge |
142:4eea097334d6 | 1361 | #endif /* defined(_SILICON_LABS_32B_SERIES_0) */ |
Anna Bridge |
142:4eea097334d6 | 1362 | |
Anna Bridge |
142:4eea097334d6 | 1363 | /** @} (end addtogroup OPAMP) */ |
Anna Bridge |
142:4eea097334d6 | 1364 | /** @} (end addtogroup emlib) */ |
Anna Bridge |
142:4eea097334d6 | 1365 | |
Anna Bridge |
142:4eea097334d6 | 1366 | #ifdef __cplusplus |
Anna Bridge |
142:4eea097334d6 | 1367 | } |
Anna Bridge |
142:4eea097334d6 | 1368 | #endif |
Anna Bridge |
142:4eea097334d6 | 1369 | |
Anna Bridge |
142:4eea097334d6 | 1370 | #endif /* (defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) |
Anna Bridge |
160:5571c4ff569f | 1371 | || defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */ |
Anna Bridge |
142:4eea097334d6 | 1372 | #endif /* EM_OPAMP_H */ |