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TARGET_EFM32GG_STK3700/TOOLCHAIN_IAR/efm32gg290f512.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 171:3a7713b1edbc | 1 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 2 | * @file efm32gg290f512.h |
AnnaBridge | 171:3a7713b1edbc | 3 | * @brief CMSIS Cortex-M Peripheral Access Layer Header File |
AnnaBridge | 171:3a7713b1edbc | 4 | * for EFM32GG290F512 |
AnnaBridge | 171:3a7713b1edbc | 5 | * @version 5.1.2 |
AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 7 | * @section License |
AnnaBridge | 171:3a7713b1edbc | 8 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
AnnaBridge | 171:3a7713b1edbc | 9 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 10 | * |
AnnaBridge | 171:3a7713b1edbc | 11 | * Permission is granted to anyone to use this software for any purpose, |
AnnaBridge | 171:3a7713b1edbc | 12 | * including commercial applications, and to alter it and redistribute it |
AnnaBridge | 171:3a7713b1edbc | 13 | * freely, subject to the following restrictions: |
AnnaBridge | 171:3a7713b1edbc | 14 | * |
AnnaBridge | 171:3a7713b1edbc | 15 | * 1. The origin of this software must not be misrepresented; you must not |
AnnaBridge | 171:3a7713b1edbc | 16 | * claim that you wrote the original software.@n |
AnnaBridge | 171:3a7713b1edbc | 17 | * 2. Altered source versions must be plainly marked as such, and must not be |
AnnaBridge | 171:3a7713b1edbc | 18 | * misrepresented as being the original software.@n |
AnnaBridge | 171:3a7713b1edbc | 19 | * 3. This notice may not be removed or altered from any source distribution. |
AnnaBridge | 171:3a7713b1edbc | 20 | * |
AnnaBridge | 171:3a7713b1edbc | 21 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
AnnaBridge | 171:3a7713b1edbc | 22 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
AnnaBridge | 171:3a7713b1edbc | 23 | * providing the Software "AS IS", with no express or implied warranties of any |
AnnaBridge | 171:3a7713b1edbc | 24 | * kind, including, but not limited to, any implied warranties of |
AnnaBridge | 171:3a7713b1edbc | 25 | * merchantability or fitness for any particular purpose or warranties against |
AnnaBridge | 171:3a7713b1edbc | 26 | * infringement of any proprietary rights of a third party. |
AnnaBridge | 171:3a7713b1edbc | 27 | * |
AnnaBridge | 171:3a7713b1edbc | 28 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
AnnaBridge | 171:3a7713b1edbc | 29 | * incidental, or special damages, or any other relief, or for any claim by |
AnnaBridge | 171:3a7713b1edbc | 30 | * any third party, arising from your use of this Software. |
AnnaBridge | 171:3a7713b1edbc | 31 | * |
AnnaBridge | 171:3a7713b1edbc | 32 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 33 | |
AnnaBridge | 171:3a7713b1edbc | 34 | #ifndef EFM32GG290F512_H |
AnnaBridge | 171:3a7713b1edbc | 35 | #define EFM32GG290F512_H |
AnnaBridge | 171:3a7713b1edbc | 36 | |
AnnaBridge | 171:3a7713b1edbc | 37 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 38 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 39 | #endif |
AnnaBridge | 171:3a7713b1edbc | 40 | |
AnnaBridge | 171:3a7713b1edbc | 41 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 42 | * @addtogroup Parts |
AnnaBridge | 171:3a7713b1edbc | 43 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 44 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 45 | |
AnnaBridge | 171:3a7713b1edbc | 46 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 47 | * @defgroup EFM32GG290F512 EFM32GG290F512 |
AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 49 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 50 | |
AnnaBridge | 171:3a7713b1edbc | 51 | /** Interrupt Number Definition */ |
AnnaBridge | 171:3a7713b1edbc | 52 | typedef enum IRQn |
AnnaBridge | 171:3a7713b1edbc | 53 | { |
AnnaBridge | 171:3a7713b1edbc | 54 | /****** Cortex-M3 Processor Exceptions Numbers ********************************************/ |
AnnaBridge | 171:3a7713b1edbc | 55 | NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M3 Non Maskable Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 56 | HardFault_IRQn = -13, /*!< -13 Cortex-M3 Hard Fault Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 57 | MemoryManagement_IRQn = -12, /*!< -12 Cortex-M3 Memory Management Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 58 | BusFault_IRQn = -11, /*!< -11 Cortex-M3 Bus Fault Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 59 | UsageFault_IRQn = -10, /*!< -10 Cortex-M3 Usage Fault Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 60 | SVCall_IRQn = -5, /*!< -5 Cortex-M3 SV Call Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 61 | DebugMonitor_IRQn = -4, /*!< -4 Cortex-M3 Debug Monitor Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 62 | PendSV_IRQn = -2, /*!< -2 Cortex-M3 Pend SV Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 63 | SysTick_IRQn = -1, /*!< -1 Cortex-M3 System Tick Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 64 | |
AnnaBridge | 171:3a7713b1edbc | 65 | /****** EFM32G Peripheral Interrupt Numbers ***********************************************/ |
AnnaBridge | 171:3a7713b1edbc | 66 | DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 67 | GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 68 | TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 69 | USART0_RX_IRQn = 3, /*!< 3 EFM32 USART0_RX Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 70 | USART0_TX_IRQn = 4, /*!< 4 EFM32 USART0_TX Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 71 | ACMP0_IRQn = 6, /*!< 6 EFM32 ACMP0 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 72 | ADC0_IRQn = 7, /*!< 7 EFM32 ADC0 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 73 | DAC0_IRQn = 8, /*!< 8 EFM32 DAC0 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 74 | I2C0_IRQn = 9, /*!< 9 EFM32 I2C0 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 75 | I2C1_IRQn = 10, /*!< 10 EFM32 I2C1 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 76 | GPIO_ODD_IRQn = 11, /*!< 11 EFM32 GPIO_ODD Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 77 | TIMER1_IRQn = 12, /*!< 12 EFM32 TIMER1 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 78 | TIMER2_IRQn = 13, /*!< 13 EFM32 TIMER2 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 79 | TIMER3_IRQn = 14, /*!< 14 EFM32 TIMER3 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 80 | USART1_RX_IRQn = 15, /*!< 15 EFM32 USART1_RX Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 81 | USART1_TX_IRQn = 16, /*!< 16 EFM32 USART1_TX Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 82 | LESENSE_IRQn = 17, /*!< 17 EFM32 LESENSE Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 83 | USART2_RX_IRQn = 18, /*!< 18 EFM32 USART2_RX Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 84 | USART2_TX_IRQn = 19, /*!< 19 EFM32 USART2_TX Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 85 | UART0_RX_IRQn = 20, /*!< 20 EFM32 UART0_RX Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 86 | UART0_TX_IRQn = 21, /*!< 21 EFM32 UART0_TX Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 87 | UART1_RX_IRQn = 22, /*!< 22 EFM32 UART1_RX Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 88 | UART1_TX_IRQn = 23, /*!< 23 EFM32 UART1_TX Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 89 | LEUART0_IRQn = 24, /*!< 24 EFM32 LEUART0 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 90 | LEUART1_IRQn = 25, /*!< 25 EFM32 LEUART1 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 91 | LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 92 | PCNT0_IRQn = 27, /*!< 27 EFM32 PCNT0 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 93 | PCNT1_IRQn = 28, /*!< 28 EFM32 PCNT1 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 94 | PCNT2_IRQn = 29, /*!< 29 EFM32 PCNT2 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 95 | RTC_IRQn = 30, /*!< 30 EFM32 RTC Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 96 | BURTC_IRQn = 31, /*!< 31 EFM32 BURTC Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 97 | CMU_IRQn = 32, /*!< 32 EFM32 CMU Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 98 | VCMP_IRQn = 33, /*!< 33 EFM32 VCMP Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 99 | MSC_IRQn = 35, /*!< 35 EFM32 MSC Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 100 | AES_IRQn = 36, /*!< 36 EFM32 AES Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 101 | EBI_IRQn = 37, /*!< 37 EFM32 EBI Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 102 | EMU_IRQn = 38, /*!< 38 EFM32 EMU Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 103 | } IRQn_Type; |
AnnaBridge | 171:3a7713b1edbc | 104 | |
AnnaBridge | 171:3a7713b1edbc | 105 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 106 | * @defgroup EFM32GG290F512_Core EFM32GG290F512 Core |
AnnaBridge | 171:3a7713b1edbc | 107 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 108 | * @brief Processor and Core Peripheral Section |
AnnaBridge | 171:3a7713b1edbc | 109 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 110 | #define __MPU_PRESENT 1 /**< Presence of MPU */ |
AnnaBridge | 171:3a7713b1edbc | 111 | #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ |
AnnaBridge | 171:3a7713b1edbc | 112 | #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ |
AnnaBridge | 171:3a7713b1edbc | 113 | #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ |
AnnaBridge | 171:3a7713b1edbc | 114 | |
AnnaBridge | 171:3a7713b1edbc | 115 | /** @} End of group EFM32GG290F512_Core */ |
AnnaBridge | 171:3a7713b1edbc | 116 | |
AnnaBridge | 171:3a7713b1edbc | 117 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 118 | * @defgroup EFM32GG290F512_Part EFM32GG290F512 Part |
AnnaBridge | 171:3a7713b1edbc | 119 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 120 | ******************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 121 | |
AnnaBridge | 171:3a7713b1edbc | 122 | /** Part family */ |
AnnaBridge | 171:3a7713b1edbc | 123 | #define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ |
AnnaBridge | 171:3a7713b1edbc | 124 | #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ |
AnnaBridge | 171:3a7713b1edbc | 125 | #define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ |
AnnaBridge | 171:3a7713b1edbc | 126 | #define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ |
AnnaBridge | 171:3a7713b1edbc | 127 | #define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ |
AnnaBridge | 171:3a7713b1edbc | 128 | #define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ |
AnnaBridge | 171:3a7713b1edbc | 129 | #define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ |
AnnaBridge | 171:3a7713b1edbc | 130 | #define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ |
AnnaBridge | 171:3a7713b1edbc | 131 | |
AnnaBridge | 171:3a7713b1edbc | 132 | /* If part number is not defined as compiler option, define it */ |
AnnaBridge | 171:3a7713b1edbc | 133 | #if !defined(EFM32GG290F512) |
AnnaBridge | 171:3a7713b1edbc | 134 | #define EFM32GG290F512 1 /**< Giant/Leopard Gecko Part */ |
AnnaBridge | 171:3a7713b1edbc | 135 | #endif |
AnnaBridge | 171:3a7713b1edbc | 136 | |
AnnaBridge | 171:3a7713b1edbc | 137 | /** Configure part number */ |
AnnaBridge | 171:3a7713b1edbc | 138 | #define PART_NUMBER "EFM32GG290F512" /**< Part Number */ |
AnnaBridge | 171:3a7713b1edbc | 139 | |
AnnaBridge | 171:3a7713b1edbc | 140 | /** Memory Base addresses and limits */ |
AnnaBridge | 171:3a7713b1edbc | 141 | #define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */ |
AnnaBridge | 171:3a7713b1edbc | 142 | #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ |
AnnaBridge | 171:3a7713b1edbc | 143 | #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */ |
AnnaBridge | 171:3a7713b1edbc | 144 | #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ |
AnnaBridge | 171:3a7713b1edbc | 145 | #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */ |
AnnaBridge | 171:3a7713b1edbc | 146 | #define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */ |
AnnaBridge | 171:3a7713b1edbc | 147 | #define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */ |
AnnaBridge | 171:3a7713b1edbc | 148 | #define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */ |
AnnaBridge | 171:3a7713b1edbc | 149 | #define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */ |
AnnaBridge | 171:3a7713b1edbc | 150 | #define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */ |
AnnaBridge | 171:3a7713b1edbc | 151 | #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */ |
AnnaBridge | 171:3a7713b1edbc | 152 | #define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */ |
AnnaBridge | 171:3a7713b1edbc | 153 | #define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */ |
AnnaBridge | 171:3a7713b1edbc | 154 | #define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */ |
AnnaBridge | 171:3a7713b1edbc | 155 | #define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */ |
AnnaBridge | 171:3a7713b1edbc | 156 | #define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */ |
AnnaBridge | 171:3a7713b1edbc | 157 | #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ |
AnnaBridge | 171:3a7713b1edbc | 158 | #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */ |
AnnaBridge | 171:3a7713b1edbc | 159 | #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */ |
AnnaBridge | 171:3a7713b1edbc | 160 | #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ |
AnnaBridge | 171:3a7713b1edbc | 161 | #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ |
AnnaBridge | 171:3a7713b1edbc | 162 | #define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */ |
AnnaBridge | 171:3a7713b1edbc | 163 | #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */ |
AnnaBridge | 171:3a7713b1edbc | 164 | #define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */ |
AnnaBridge | 171:3a7713b1edbc | 165 | #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ |
AnnaBridge | 171:3a7713b1edbc | 166 | #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */ |
AnnaBridge | 171:3a7713b1edbc | 167 | #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */ |
AnnaBridge | 171:3a7713b1edbc | 168 | #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */ |
AnnaBridge | 171:3a7713b1edbc | 169 | #define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */ |
AnnaBridge | 171:3a7713b1edbc | 170 | #define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */ |
AnnaBridge | 171:3a7713b1edbc | 171 | #define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */ |
AnnaBridge | 171:3a7713b1edbc | 172 | #define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */ |
AnnaBridge | 171:3a7713b1edbc | 173 | |
AnnaBridge | 171:3a7713b1edbc | 174 | /** Bit banding area */ |
AnnaBridge | 171:3a7713b1edbc | 175 | #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ |
AnnaBridge | 171:3a7713b1edbc | 176 | #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ |
AnnaBridge | 171:3a7713b1edbc | 177 | |
AnnaBridge | 171:3a7713b1edbc | 178 | /** Flash and SRAM limits for EFM32GG290F512 */ |
AnnaBridge | 171:3a7713b1edbc | 179 | #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 180 | #define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ |
AnnaBridge | 171:3a7713b1edbc | 181 | #define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */ |
AnnaBridge | 171:3a7713b1edbc | 182 | #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 183 | #define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ |
AnnaBridge | 171:3a7713b1edbc | 184 | #define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */ |
AnnaBridge | 171:3a7713b1edbc | 185 | #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ |
AnnaBridge | 171:3a7713b1edbc | 186 | #define DMA_CHAN_COUNT 12 /**< Number of DMA channels */ |
AnnaBridge | 171:3a7713b1edbc | 187 | #define EXT_IRQ_COUNT 39 /**< Number of External (NVIC) interrupts */ |
AnnaBridge | 171:3a7713b1edbc | 188 | |
AnnaBridge | 171:3a7713b1edbc | 189 | /** AF channels connect the different on-chip peripherals with the af-mux */ |
AnnaBridge | 171:3a7713b1edbc | 190 | #define AFCHAN_MAX 163 |
AnnaBridge | 171:3a7713b1edbc | 191 | #define AFCHANLOC_MAX 7 |
AnnaBridge | 171:3a7713b1edbc | 192 | /** Analog AF channels */ |
AnnaBridge | 171:3a7713b1edbc | 193 | #define AFACHAN_MAX 53 |
AnnaBridge | 171:3a7713b1edbc | 194 | |
AnnaBridge | 171:3a7713b1edbc | 195 | /* Part number capabilities */ |
AnnaBridge | 171:3a7713b1edbc | 196 | |
AnnaBridge | 171:3a7713b1edbc | 197 | #define LETIMER_PRESENT /**< LETIMER is available in this part */ |
AnnaBridge | 171:3a7713b1edbc | 198 | #define LETIMER_COUNT 1 /**< 1 LETIMERs available */ |
AnnaBridge | 171:3a7713b1edbc | 199 | #define USART_PRESENT /**< USART is available in this part */ |
AnnaBridge | 171:3a7713b1edbc | 200 | #define USART_COUNT 3 /**< 3 USARTs available */ |
AnnaBridge | 171:3a7713b1edbc | 201 | #define UART_PRESENT /**< UART is available in this part */ |
AnnaBridge | 171:3a7713b1edbc | 202 | #define UART_COUNT 2 /**< 2 UARTs available */ |
AnnaBridge | 171:3a7713b1edbc | 203 | #define TIMER_PRESENT /**< TIMER is available in this part */ |
AnnaBridge | 171:3a7713b1edbc | 204 | #define TIMER_COUNT 4 /**< 4 TIMERs available */ |
AnnaBridge | 171:3a7713b1edbc | 205 | #define ACMP_PRESENT /**< ACMP is available in this part */ |
AnnaBridge | 171:3a7713b1edbc | 206 | #define ACMP_COUNT 2 /**< 2 ACMPs available */ |
AnnaBridge | 171:3a7713b1edbc | 207 | #define I2C_PRESENT /**< I2C is available in this part */ |
AnnaBridge | 171:3a7713b1edbc | 208 | #define I2C_COUNT 2 /**< 2 I2Cs available */ |
AnnaBridge | 171:3a7713b1edbc | 209 | #define LEUART_PRESENT /**< LEUART is available in this part */ |
AnnaBridge | 171:3a7713b1edbc | 210 | #define LEUART_COUNT 2 /**< 2 LEUARTs available */ |
AnnaBridge | 171:3a7713b1edbc | 211 | #define PCNT_PRESENT /**< PCNT is available in this part */ |
AnnaBridge | 171:3a7713b1edbc | 212 | #define PCNT_COUNT 3 /**< 3 PCNTs available */ |
AnnaBridge | 171:3a7713b1edbc | 213 | #define ADC_PRESENT /**< ADC is available in this part */ |
AnnaBridge | 171:3a7713b1edbc | 214 | #define ADC_COUNT 1 /**< 1 ADCs available */ |
AnnaBridge | 171:3a7713b1edbc | 215 | #define DAC_PRESENT /**< DAC is available in this part */ |
AnnaBridge | 171:3a7713b1edbc | 216 | #define DAC_COUNT 1 /**< 1 DACs available */ |
AnnaBridge | 171:3a7713b1edbc | 217 | #define DMA_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 218 | #define DMA_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 219 | #define AES_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 220 | #define AES_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 221 | #define LE_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 222 | #define LE_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 223 | #define MSC_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 224 | #define MSC_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 225 | #define EMU_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 226 | #define EMU_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 227 | #define RMU_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 228 | #define RMU_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 229 | #define CMU_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 230 | #define CMU_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 231 | #define LESENSE_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 232 | #define LESENSE_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 233 | #define RTC_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 234 | #define RTC_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 235 | #define EBI_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 236 | #define EBI_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 237 | #define GPIO_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 238 | #define GPIO_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 239 | #define VCMP_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 240 | #define VCMP_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 241 | #define PRS_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 242 | #define PRS_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 243 | #define OPAMP_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 244 | #define OPAMP_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 245 | #define BU_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 246 | #define BU_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 247 | #define BURTC_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 248 | #define BURTC_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 249 | #define HFXTAL_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 250 | #define HFXTAL_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 251 | #define LFXTAL_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 252 | #define LFXTAL_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 253 | #define WDOG_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 254 | #define WDOG_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 255 | #define DBG_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 256 | #define DBG_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 257 | #define ETM_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 258 | #define ETM_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 259 | #define BOOTLOADER_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 260 | #define BOOTLOADER_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 261 | #define ANALOG_PRESENT |
AnnaBridge | 171:3a7713b1edbc | 262 | #define ANALOG_COUNT 1 |
AnnaBridge | 171:3a7713b1edbc | 263 | |
AnnaBridge | 171:3a7713b1edbc | 264 | #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ |
AnnaBridge | 171:3a7713b1edbc | 265 | #include "system_efm32gg.h" /* System Header */ |
AnnaBridge | 171:3a7713b1edbc | 266 | |
AnnaBridge | 171:3a7713b1edbc | 267 | /** @} End of group EFM32GG290F512_Part */ |
AnnaBridge | 171:3a7713b1edbc | 268 | |
AnnaBridge | 171:3a7713b1edbc | 269 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 270 | * @defgroup EFM32GG290F512_Peripheral_TypeDefs EFM32GG290F512 Peripheral TypeDefs |
AnnaBridge | 171:3a7713b1edbc | 271 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 272 | * @brief Device Specific Peripheral Register Structures |
AnnaBridge | 171:3a7713b1edbc | 273 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 274 | |
AnnaBridge | 171:3a7713b1edbc | 275 | #include "efm32gg_dma_ch.h" |
AnnaBridge | 171:3a7713b1edbc | 276 | #include "efm32gg_dma.h" |
AnnaBridge | 171:3a7713b1edbc | 277 | #include "efm32gg_aes.h" |
AnnaBridge | 171:3a7713b1edbc | 278 | #include "efm32gg_msc.h" |
AnnaBridge | 171:3a7713b1edbc | 279 | #include "efm32gg_emu.h" |
AnnaBridge | 171:3a7713b1edbc | 280 | #include "efm32gg_rmu.h" |
AnnaBridge | 171:3a7713b1edbc | 281 | |
AnnaBridge | 171:3a7713b1edbc | 282 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 283 | * @defgroup EFM32GG290F512_CMU EFM32GG290F512 CMU |
AnnaBridge | 171:3a7713b1edbc | 284 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 285 | * @brief EFM32GG290F512_CMU Register Declaration |
AnnaBridge | 171:3a7713b1edbc | 286 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 287 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 288 | { |
AnnaBridge | 171:3a7713b1edbc | 289 | __IOM uint32_t CTRL; /**< CMU Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 290 | __IOM uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */ |
AnnaBridge | 171:3a7713b1edbc | 291 | __IOM uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */ |
AnnaBridge | 171:3a7713b1edbc | 292 | __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 293 | __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 294 | __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 295 | __IOM uint32_t CALCTRL; /**< Calibration Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 296 | __IOM uint32_t CALCNT; /**< Calibration Counter Register */ |
AnnaBridge | 171:3a7713b1edbc | 297 | __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ |
AnnaBridge | 171:3a7713b1edbc | 298 | __IOM uint32_t CMD; /**< Command Register */ |
AnnaBridge | 171:3a7713b1edbc | 299 | __IOM uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */ |
AnnaBridge | 171:3a7713b1edbc | 300 | __IM uint32_t STATUS; /**< Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 301 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
AnnaBridge | 171:3a7713b1edbc | 302 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
AnnaBridge | 171:3a7713b1edbc | 303 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
AnnaBridge | 171:3a7713b1edbc | 304 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
AnnaBridge | 171:3a7713b1edbc | 305 | __IOM uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */ |
AnnaBridge | 171:3a7713b1edbc | 306 | __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ |
AnnaBridge | 171:3a7713b1edbc | 307 | uint32_t RESERVED0[2]; /**< Reserved for future use **/ |
AnnaBridge | 171:3a7713b1edbc | 308 | __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ |
AnnaBridge | 171:3a7713b1edbc | 309 | __IOM uint32_t FREEZE; /**< Freeze Register */ |
AnnaBridge | 171:3a7713b1edbc | 310 | __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ |
AnnaBridge | 171:3a7713b1edbc | 311 | uint32_t RESERVED1[1]; /**< Reserved for future use **/ |
AnnaBridge | 171:3a7713b1edbc | 312 | __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ |
AnnaBridge | 171:3a7713b1edbc | 313 | |
AnnaBridge | 171:3a7713b1edbc | 314 | uint32_t RESERVED2[1]; /**< Reserved for future use **/ |
AnnaBridge | 171:3a7713b1edbc | 315 | __IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */ |
AnnaBridge | 171:3a7713b1edbc | 316 | uint32_t RESERVED3[1]; /**< Reserved for future use **/ |
AnnaBridge | 171:3a7713b1edbc | 317 | __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ |
AnnaBridge | 171:3a7713b1edbc | 318 | uint32_t RESERVED4[1]; /**< Reserved for future use **/ |
AnnaBridge | 171:3a7713b1edbc | 319 | __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 320 | |
AnnaBridge | 171:3a7713b1edbc | 321 | uint32_t RESERVED5[1]; /**< Reserved for future use **/ |
AnnaBridge | 171:3a7713b1edbc | 322 | __IOM uint32_t ROUTE; /**< I/O Routing Register */ |
AnnaBridge | 171:3a7713b1edbc | 323 | __IOM uint32_t LOCK; /**< Configuration Lock Register */ |
AnnaBridge | 171:3a7713b1edbc | 324 | } CMU_TypeDef; /** @} */ |
AnnaBridge | 171:3a7713b1edbc | 325 | |
AnnaBridge | 171:3a7713b1edbc | 326 | #include "efm32gg_lesense_st.h" |
AnnaBridge | 171:3a7713b1edbc | 327 | #include "efm32gg_lesense_buf.h" |
AnnaBridge | 171:3a7713b1edbc | 328 | #include "efm32gg_lesense_ch.h" |
AnnaBridge | 171:3a7713b1edbc | 329 | #include "efm32gg_lesense.h" |
AnnaBridge | 171:3a7713b1edbc | 330 | #include "efm32gg_rtc.h" |
AnnaBridge | 171:3a7713b1edbc | 331 | #include "efm32gg_letimer.h" |
AnnaBridge | 171:3a7713b1edbc | 332 | #include "efm32gg_ebi.h" |
AnnaBridge | 171:3a7713b1edbc | 333 | #include "efm32gg_usart.h" |
AnnaBridge | 171:3a7713b1edbc | 334 | #include "efm32gg_timer_cc.h" |
AnnaBridge | 171:3a7713b1edbc | 335 | #include "efm32gg_timer.h" |
AnnaBridge | 171:3a7713b1edbc | 336 | #include "efm32gg_acmp.h" |
AnnaBridge | 171:3a7713b1edbc | 337 | #include "efm32gg_i2c.h" |
AnnaBridge | 171:3a7713b1edbc | 338 | #include "efm32gg_gpio_p.h" |
AnnaBridge | 171:3a7713b1edbc | 339 | #include "efm32gg_gpio.h" |
AnnaBridge | 171:3a7713b1edbc | 340 | #include "efm32gg_vcmp.h" |
AnnaBridge | 171:3a7713b1edbc | 341 | #include "efm32gg_prs_ch.h" |
AnnaBridge | 171:3a7713b1edbc | 342 | |
AnnaBridge | 171:3a7713b1edbc | 343 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 344 | * @defgroup EFM32GG290F512_PRS EFM32GG290F512 PRS |
AnnaBridge | 171:3a7713b1edbc | 345 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 346 | * @brief EFM32GG290F512_PRS Register Declaration |
AnnaBridge | 171:3a7713b1edbc | 347 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 348 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 349 | { |
AnnaBridge | 171:3a7713b1edbc | 350 | __IOM uint32_t SWPULSE; /**< Software Pulse Register */ |
AnnaBridge | 171:3a7713b1edbc | 351 | __IOM uint32_t SWLEVEL; /**< Software Level Register */ |
AnnaBridge | 171:3a7713b1edbc | 352 | __IOM uint32_t ROUTE; /**< I/O Routing Register */ |
AnnaBridge | 171:3a7713b1edbc | 353 | |
AnnaBridge | 171:3a7713b1edbc | 354 | uint32_t RESERVED0[1]; /**< Reserved registers */ |
AnnaBridge | 171:3a7713b1edbc | 355 | PRS_CH_TypeDef CH[12]; /**< Channel registers */ |
AnnaBridge | 171:3a7713b1edbc | 356 | } PRS_TypeDef; /** @} */ |
AnnaBridge | 171:3a7713b1edbc | 357 | |
AnnaBridge | 171:3a7713b1edbc | 358 | #include "efm32gg_leuart.h" |
AnnaBridge | 171:3a7713b1edbc | 359 | #include "efm32gg_pcnt.h" |
AnnaBridge | 171:3a7713b1edbc | 360 | #include "efm32gg_adc.h" |
AnnaBridge | 171:3a7713b1edbc | 361 | #include "efm32gg_dac.h" |
AnnaBridge | 171:3a7713b1edbc | 362 | #include "efm32gg_burtc_ret.h" |
AnnaBridge | 171:3a7713b1edbc | 363 | #include "efm32gg_burtc.h" |
AnnaBridge | 171:3a7713b1edbc | 364 | #include "efm32gg_wdog.h" |
AnnaBridge | 171:3a7713b1edbc | 365 | #include "efm32gg_etm.h" |
AnnaBridge | 171:3a7713b1edbc | 366 | #include "efm32gg_dma_descriptor.h" |
AnnaBridge | 171:3a7713b1edbc | 367 | #include "efm32gg_devinfo.h" |
AnnaBridge | 171:3a7713b1edbc | 368 | #include "efm32gg_romtable.h" |
AnnaBridge | 171:3a7713b1edbc | 369 | #include "efm32gg_calibrate.h" |
AnnaBridge | 171:3a7713b1edbc | 370 | |
AnnaBridge | 171:3a7713b1edbc | 371 | /** @} End of group EFM32GG290F512_Peripheral_TypeDefs */ |
AnnaBridge | 171:3a7713b1edbc | 372 | |
AnnaBridge | 171:3a7713b1edbc | 373 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 374 | * @defgroup EFM32GG290F512_Peripheral_Base EFM32GG290F512 Peripheral Memory Map |
AnnaBridge | 171:3a7713b1edbc | 375 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 376 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 377 | |
AnnaBridge | 171:3a7713b1edbc | 378 | #define DMA_BASE (0x400C2000UL) /**< DMA base address */ |
AnnaBridge | 171:3a7713b1edbc | 379 | #define AES_BASE (0x400E0000UL) /**< AES base address */ |
AnnaBridge | 171:3a7713b1edbc | 380 | #define MSC_BASE (0x400C0000UL) /**< MSC base address */ |
AnnaBridge | 171:3a7713b1edbc | 381 | #define EMU_BASE (0x400C6000UL) /**< EMU base address */ |
AnnaBridge | 171:3a7713b1edbc | 382 | #define RMU_BASE (0x400CA000UL) /**< RMU base address */ |
AnnaBridge | 171:3a7713b1edbc | 383 | #define CMU_BASE (0x400C8000UL) /**< CMU base address */ |
AnnaBridge | 171:3a7713b1edbc | 384 | #define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */ |
AnnaBridge | 171:3a7713b1edbc | 385 | #define RTC_BASE (0x40080000UL) /**< RTC base address */ |
AnnaBridge | 171:3a7713b1edbc | 386 | #define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 387 | #define EBI_BASE (0x40008000UL) /**< EBI base address */ |
AnnaBridge | 171:3a7713b1edbc | 388 | #define USART0_BASE (0x4000C000UL) /**< USART0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 389 | #define USART1_BASE (0x4000C400UL) /**< USART1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 390 | #define USART2_BASE (0x4000C800UL) /**< USART2 base address */ |
AnnaBridge | 171:3a7713b1edbc | 391 | #define UART0_BASE (0x4000E000UL) /**< UART0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 392 | #define UART1_BASE (0x4000E400UL) /**< UART1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 393 | #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 394 | #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 395 | #define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */ |
AnnaBridge | 171:3a7713b1edbc | 396 | #define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */ |
AnnaBridge | 171:3a7713b1edbc | 397 | #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 398 | #define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 399 | #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 400 | #define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 401 | #define GPIO_BASE (0x40006000UL) /**< GPIO base address */ |
AnnaBridge | 171:3a7713b1edbc | 402 | #define VCMP_BASE (0x40000000UL) /**< VCMP base address */ |
AnnaBridge | 171:3a7713b1edbc | 403 | #define PRS_BASE (0x400CC000UL) /**< PRS base address */ |
AnnaBridge | 171:3a7713b1edbc | 404 | #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 405 | #define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 406 | #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 407 | #define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 408 | #define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */ |
AnnaBridge | 171:3a7713b1edbc | 409 | #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 410 | #define DAC0_BASE (0x40004000UL) /**< DAC0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 411 | #define BURTC_BASE (0x40081000UL) /**< BURTC base address */ |
AnnaBridge | 171:3a7713b1edbc | 412 | #define WDOG_BASE (0x40088000UL) /**< WDOG base address */ |
AnnaBridge | 171:3a7713b1edbc | 413 | #define ETM_BASE (0xE0041000UL) /**< ETM base address */ |
AnnaBridge | 171:3a7713b1edbc | 414 | #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */ |
AnnaBridge | 171:3a7713b1edbc | 415 | #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ |
AnnaBridge | 171:3a7713b1edbc | 416 | #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ |
AnnaBridge | 171:3a7713b1edbc | 417 | #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ |
AnnaBridge | 171:3a7713b1edbc | 418 | #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ |
AnnaBridge | 171:3a7713b1edbc | 419 | |
AnnaBridge | 171:3a7713b1edbc | 420 | /** @} End of group EFM32GG290F512_Peripheral_Base */ |
AnnaBridge | 171:3a7713b1edbc | 421 | |
AnnaBridge | 171:3a7713b1edbc | 422 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 423 | * @defgroup EFM32GG290F512_Peripheral_Declaration EFM32GG290F512 Peripheral Declarations |
AnnaBridge | 171:3a7713b1edbc | 424 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 425 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 426 | |
AnnaBridge | 171:3a7713b1edbc | 427 | #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 428 | #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 429 | #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 430 | #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 431 | #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 432 | #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 433 | #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 434 | #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 435 | #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 436 | #define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 437 | #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 438 | #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 439 | #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 440 | #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 441 | #define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 442 | #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 443 | #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 444 | #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 445 | #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 446 | #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 447 | #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 448 | #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 449 | #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 450 | #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 451 | #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 452 | #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 453 | #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 454 | #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 455 | #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 456 | #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 457 | #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 458 | #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 459 | #define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 460 | #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 461 | #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 462 | #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 463 | #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 464 | #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 465 | #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 466 | |
AnnaBridge | 171:3a7713b1edbc | 467 | /** @} End of group EFM32GG290F512_Peripheral_Declaration */ |
AnnaBridge | 171:3a7713b1edbc | 468 | |
AnnaBridge | 171:3a7713b1edbc | 469 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 470 | * @defgroup EFM32GG290F512_BitFields EFM32GG290F512 Bit Fields |
AnnaBridge | 171:3a7713b1edbc | 471 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 472 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 473 | |
AnnaBridge | 171:3a7713b1edbc | 474 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 475 | * @addtogroup EFM32GG290F512_PRS_Signals |
AnnaBridge | 171:3a7713b1edbc | 476 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 477 | * @brief PRS Signal names |
AnnaBridge | 171:3a7713b1edbc | 478 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 479 | #define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */ |
AnnaBridge | 171:3a7713b1edbc | 480 | #define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */ |
AnnaBridge | 171:3a7713b1edbc | 481 | #define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */ |
AnnaBridge | 171:3a7713b1edbc | 482 | #define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */ |
AnnaBridge | 171:3a7713b1edbc | 483 | #define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */ |
AnnaBridge | 171:3a7713b1edbc | 484 | #define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */ |
AnnaBridge | 171:3a7713b1edbc | 485 | #define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */ |
AnnaBridge | 171:3a7713b1edbc | 486 | #define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */ |
AnnaBridge | 171:3a7713b1edbc | 487 | #define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */ |
AnnaBridge | 171:3a7713b1edbc | 488 | #define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */ |
AnnaBridge | 171:3a7713b1edbc | 489 | #define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */ |
AnnaBridge | 171:3a7713b1edbc | 490 | #define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */ |
AnnaBridge | 171:3a7713b1edbc | 491 | #define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */ |
AnnaBridge | 171:3a7713b1edbc | 492 | #define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */ |
AnnaBridge | 171:3a7713b1edbc | 493 | #define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */ |
AnnaBridge | 171:3a7713b1edbc | 494 | #define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */ |
AnnaBridge | 171:3a7713b1edbc | 495 | #define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */ |
AnnaBridge | 171:3a7713b1edbc | 496 | #define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */ |
AnnaBridge | 171:3a7713b1edbc | 497 | #define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */ |
AnnaBridge | 171:3a7713b1edbc | 498 | #define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */ |
AnnaBridge | 171:3a7713b1edbc | 499 | #define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */ |
AnnaBridge | 171:3a7713b1edbc | 500 | #define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */ |
AnnaBridge | 171:3a7713b1edbc | 501 | #define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */ |
AnnaBridge | 171:3a7713b1edbc | 502 | #define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */ |
AnnaBridge | 171:3a7713b1edbc | 503 | #define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */ |
AnnaBridge | 171:3a7713b1edbc | 504 | #define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */ |
AnnaBridge | 171:3a7713b1edbc | 505 | #define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */ |
AnnaBridge | 171:3a7713b1edbc | 506 | #define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */ |
AnnaBridge | 171:3a7713b1edbc | 507 | #define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */ |
AnnaBridge | 171:3a7713b1edbc | 508 | #define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */ |
AnnaBridge | 171:3a7713b1edbc | 509 | #define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */ |
AnnaBridge | 171:3a7713b1edbc | 510 | #define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */ |
AnnaBridge | 171:3a7713b1edbc | 511 | #define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */ |
AnnaBridge | 171:3a7713b1edbc | 512 | #define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */ |
AnnaBridge | 171:3a7713b1edbc | 513 | #define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */ |
AnnaBridge | 171:3a7713b1edbc | 514 | #define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */ |
AnnaBridge | 171:3a7713b1edbc | 515 | #define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */ |
AnnaBridge | 171:3a7713b1edbc | 516 | #define PRS_UART0_TXC ((41 << 16) + 1) /**< PRS USART 0 TX complete */ |
AnnaBridge | 171:3a7713b1edbc | 517 | #define PRS_UART0_RXDATAV ((41 << 16) + 2) /**< PRS USART 0 RX Data Valid */ |
AnnaBridge | 171:3a7713b1edbc | 518 | #define PRS_UART1_TXC ((42 << 16) + 1) /**< PRS USART 0 TX complete */ |
AnnaBridge | 171:3a7713b1edbc | 519 | #define PRS_UART1_RXDATAV ((42 << 16) + 2) /**< PRS USART 0 RX Data Valid */ |
AnnaBridge | 171:3a7713b1edbc | 520 | #define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */ |
AnnaBridge | 171:3a7713b1edbc | 521 | #define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */ |
AnnaBridge | 171:3a7713b1edbc | 522 | #define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */ |
AnnaBridge | 171:3a7713b1edbc | 523 | #define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */ |
AnnaBridge | 171:3a7713b1edbc | 524 | #define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */ |
AnnaBridge | 171:3a7713b1edbc | 525 | #define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */ |
AnnaBridge | 171:3a7713b1edbc | 526 | #define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */ |
AnnaBridge | 171:3a7713b1edbc | 527 | #define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */ |
AnnaBridge | 171:3a7713b1edbc | 528 | #define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */ |
AnnaBridge | 171:3a7713b1edbc | 529 | #define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */ |
AnnaBridge | 171:3a7713b1edbc | 530 | #define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */ |
AnnaBridge | 171:3a7713b1edbc | 531 | #define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */ |
AnnaBridge | 171:3a7713b1edbc | 532 | #define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */ |
AnnaBridge | 171:3a7713b1edbc | 533 | #define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */ |
AnnaBridge | 171:3a7713b1edbc | 534 | #define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */ |
AnnaBridge | 171:3a7713b1edbc | 535 | #define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */ |
AnnaBridge | 171:3a7713b1edbc | 536 | #define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */ |
AnnaBridge | 171:3a7713b1edbc | 537 | #define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */ |
AnnaBridge | 171:3a7713b1edbc | 538 | #define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */ |
AnnaBridge | 171:3a7713b1edbc | 539 | #define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */ |
AnnaBridge | 171:3a7713b1edbc | 540 | #define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ |
AnnaBridge | 171:3a7713b1edbc | 541 | #define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ |
AnnaBridge | 171:3a7713b1edbc | 542 | #define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ |
AnnaBridge | 171:3a7713b1edbc | 543 | #define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ |
AnnaBridge | 171:3a7713b1edbc | 544 | #define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ |
AnnaBridge | 171:3a7713b1edbc | 545 | #define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ |
AnnaBridge | 171:3a7713b1edbc | 546 | #define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ |
AnnaBridge | 171:3a7713b1edbc | 547 | #define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ |
AnnaBridge | 171:3a7713b1edbc | 548 | #define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ |
AnnaBridge | 171:3a7713b1edbc | 549 | #define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ |
AnnaBridge | 171:3a7713b1edbc | 550 | #define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ |
AnnaBridge | 171:3a7713b1edbc | 551 | #define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ |
AnnaBridge | 171:3a7713b1edbc | 552 | #define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ |
AnnaBridge | 171:3a7713b1edbc | 553 | #define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ |
AnnaBridge | 171:3a7713b1edbc | 554 | #define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ |
AnnaBridge | 171:3a7713b1edbc | 555 | #define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ |
AnnaBridge | 171:3a7713b1edbc | 556 | #define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */ |
AnnaBridge | 171:3a7713b1edbc | 557 | #define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */ |
AnnaBridge | 171:3a7713b1edbc | 558 | #define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */ |
AnnaBridge | 171:3a7713b1edbc | 559 | |
AnnaBridge | 171:3a7713b1edbc | 560 | /** @} End of group EFM32GG290F512_PRS */ |
AnnaBridge | 171:3a7713b1edbc | 561 | |
AnnaBridge | 171:3a7713b1edbc | 562 | #include "efm32gg_dmareq.h" |
AnnaBridge | 171:3a7713b1edbc | 563 | #include "efm32gg_dmactrl.h" |
AnnaBridge | 171:3a7713b1edbc | 564 | #include "efm32gg_uart.h" |
AnnaBridge | 171:3a7713b1edbc | 565 | |
AnnaBridge | 171:3a7713b1edbc | 566 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 567 | * @defgroup EFM32GG290F512_CMU_BitFields EFM32GG290F512_CMU Bit Fields |
AnnaBridge | 171:3a7713b1edbc | 568 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 569 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 570 | |
AnnaBridge | 171:3a7713b1edbc | 571 | /* Bit fields for CMU CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 572 | #define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 573 | #define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 574 | #define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */ |
AnnaBridge | 171:3a7713b1edbc | 575 | #define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */ |
AnnaBridge | 171:3a7713b1edbc | 576 | #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 577 | #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 578 | #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 579 | #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 580 | #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 581 | #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 582 | #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 583 | #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 584 | #define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */ |
AnnaBridge | 171:3a7713b1edbc | 585 | #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */ |
AnnaBridge | 171:3a7713b1edbc | 586 | #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 587 | #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 588 | #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 589 | #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 590 | #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 591 | #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 592 | #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 593 | #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 594 | #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 595 | #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 596 | #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */ |
AnnaBridge | 171:3a7713b1edbc | 597 | #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */ |
AnnaBridge | 171:3a7713b1edbc | 598 | #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 599 | #define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 600 | #define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 601 | #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 602 | #define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 603 | #define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 604 | #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */ |
AnnaBridge | 171:3a7713b1edbc | 605 | #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */ |
AnnaBridge | 171:3a7713b1edbc | 606 | #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */ |
AnnaBridge | 171:3a7713b1edbc | 607 | #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 608 | #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 609 | #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */ |
AnnaBridge | 171:3a7713b1edbc | 610 | #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */ |
AnnaBridge | 171:3a7713b1edbc | 611 | #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 612 | #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 613 | #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 614 | #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 615 | #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 616 | #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 617 | #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 618 | #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 619 | #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 620 | #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 621 | #define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */ |
AnnaBridge | 171:3a7713b1edbc | 622 | #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */ |
AnnaBridge | 171:3a7713b1edbc | 623 | #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 624 | #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 625 | #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 626 | #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 627 | #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 628 | #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 629 | #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 630 | #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 631 | #define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */ |
AnnaBridge | 171:3a7713b1edbc | 632 | #define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */ |
AnnaBridge | 171:3a7713b1edbc | 633 | #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */ |
AnnaBridge | 171:3a7713b1edbc | 634 | #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 635 | #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 636 | #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 637 | #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 638 | #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 639 | #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 640 | #define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 641 | #define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 642 | #define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 643 | #define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 644 | #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */ |
AnnaBridge | 171:3a7713b1edbc | 645 | #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */ |
AnnaBridge | 171:3a7713b1edbc | 646 | #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */ |
AnnaBridge | 171:3a7713b1edbc | 647 | #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 648 | #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 649 | #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */ |
AnnaBridge | 171:3a7713b1edbc | 650 | #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */ |
AnnaBridge | 171:3a7713b1edbc | 651 | #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 652 | #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 653 | #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 654 | #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 655 | #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 656 | #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 657 | #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 658 | #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 659 | #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 660 | #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 661 | #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */ |
AnnaBridge | 171:3a7713b1edbc | 662 | #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */ |
AnnaBridge | 171:3a7713b1edbc | 663 | #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 664 | #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 665 | #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 666 | #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 667 | #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 668 | #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 669 | #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 670 | #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 671 | #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 672 | #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 673 | #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 674 | #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 675 | #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 676 | #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 677 | #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 678 | #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 679 | #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 680 | #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 681 | #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */ |
AnnaBridge | 171:3a7713b1edbc | 682 | #define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */ |
AnnaBridge | 171:3a7713b1edbc | 683 | #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 684 | #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 685 | #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 686 | #define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 687 | #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 688 | #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 689 | #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 690 | #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 691 | #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 692 | #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 693 | #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 694 | #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 695 | #define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 696 | #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 697 | #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 698 | #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 699 | #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 700 | #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 701 | #define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */ |
AnnaBridge | 171:3a7713b1edbc | 702 | #define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */ |
AnnaBridge | 171:3a7713b1edbc | 703 | #define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */ |
AnnaBridge | 171:3a7713b1edbc | 704 | #define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 705 | #define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 706 | #define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 707 | #define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 708 | #define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 709 | #define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 710 | #define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */ |
AnnaBridge | 171:3a7713b1edbc | 711 | #define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */ |
AnnaBridge | 171:3a7713b1edbc | 712 | #define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */ |
AnnaBridge | 171:3a7713b1edbc | 713 | #define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 714 | #define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 715 | |
AnnaBridge | 171:3a7713b1edbc | 716 | /* Bit fields for CMU HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 717 | #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 718 | #define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 719 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 720 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 721 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 722 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 723 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 724 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 725 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 726 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 727 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 728 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 729 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 730 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 731 | #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 732 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 733 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 734 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 735 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 736 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 737 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 738 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 739 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 740 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 741 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 742 | #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 743 | #define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */ |
AnnaBridge | 171:3a7713b1edbc | 744 | #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */ |
AnnaBridge | 171:3a7713b1edbc | 745 | #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */ |
AnnaBridge | 171:3a7713b1edbc | 746 | #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 747 | #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 748 | #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 749 | #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 750 | #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 751 | #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 752 | |
AnnaBridge | 171:3a7713b1edbc | 753 | /* Bit fields for CMU HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 754 | #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 755 | #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 756 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 757 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 758 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 759 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 760 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 761 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 762 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 763 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 764 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 765 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 766 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 767 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 768 | #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 769 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 770 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 771 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 772 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 773 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 774 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 775 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 776 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 777 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 778 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 779 | #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 780 | #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */ |
AnnaBridge | 171:3a7713b1edbc | 781 | #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */ |
AnnaBridge | 171:3a7713b1edbc | 782 | #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */ |
AnnaBridge | 171:3a7713b1edbc | 783 | #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 784 | #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */ |
AnnaBridge | 171:3a7713b1edbc | 785 | |
AnnaBridge | 171:3a7713b1edbc | 786 | /* Bit fields for CMU HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 787 | #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 788 | #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 789 | #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ |
AnnaBridge | 171:3a7713b1edbc | 790 | #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */ |
AnnaBridge | 171:3a7713b1edbc | 791 | #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 792 | #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 793 | #define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */ |
AnnaBridge | 171:3a7713b1edbc | 794 | #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */ |
AnnaBridge | 171:3a7713b1edbc | 795 | #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 796 | #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 797 | #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 798 | #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 799 | #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 800 | #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 801 | #define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 802 | #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 803 | #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 804 | #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 805 | #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 806 | #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 807 | #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 808 | #define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 809 | #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */ |
AnnaBridge | 171:3a7713b1edbc | 810 | #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */ |
AnnaBridge | 171:3a7713b1edbc | 811 | #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 812 | #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 813 | |
AnnaBridge | 171:3a7713b1edbc | 814 | /* Bit fields for CMU LFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 815 | #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 816 | #define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 817 | #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ |
AnnaBridge | 171:3a7713b1edbc | 818 | #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ |
AnnaBridge | 171:3a7713b1edbc | 819 | #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 820 | #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 821 | |
AnnaBridge | 171:3a7713b1edbc | 822 | /* Bit fields for CMU AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 823 | #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 824 | #define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 825 | #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ |
AnnaBridge | 171:3a7713b1edbc | 826 | #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */ |
AnnaBridge | 171:3a7713b1edbc | 827 | #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 828 | #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 829 | #define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */ |
AnnaBridge | 171:3a7713b1edbc | 830 | #define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */ |
AnnaBridge | 171:3a7713b1edbc | 831 | #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 832 | #define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 833 | #define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 834 | #define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 835 | #define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 836 | #define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 837 | #define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 838 | #define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 839 | #define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 840 | #define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 841 | #define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 842 | #define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 843 | #define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 844 | #define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 845 | |
AnnaBridge | 171:3a7713b1edbc | 846 | /* Bit fields for CMU CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 847 | #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 848 | #define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 849 | #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ |
AnnaBridge | 171:3a7713b1edbc | 850 | #define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ |
AnnaBridge | 171:3a7713b1edbc | 851 | #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 852 | #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 853 | #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 854 | #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 855 | #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 856 | #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 857 | #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 858 | #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 859 | #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 860 | #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 861 | #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 862 | #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 863 | #define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */ |
AnnaBridge | 171:3a7713b1edbc | 864 | #define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */ |
AnnaBridge | 171:3a7713b1edbc | 865 | #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 866 | #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 867 | #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 868 | #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 869 | #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 870 | #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 871 | #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 872 | #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 873 | #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 874 | #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 875 | #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 876 | #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 877 | #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 878 | #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 879 | #define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */ |
AnnaBridge | 171:3a7713b1edbc | 880 | #define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */ |
AnnaBridge | 171:3a7713b1edbc | 881 | #define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */ |
AnnaBridge | 171:3a7713b1edbc | 882 | #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 883 | #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 884 | |
AnnaBridge | 171:3a7713b1edbc | 885 | /* Bit fields for CMU CALCNT */ |
AnnaBridge | 171:3a7713b1edbc | 886 | #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ |
AnnaBridge | 171:3a7713b1edbc | 887 | #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ |
AnnaBridge | 171:3a7713b1edbc | 888 | #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ |
AnnaBridge | 171:3a7713b1edbc | 889 | #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ |
AnnaBridge | 171:3a7713b1edbc | 890 | #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ |
AnnaBridge | 171:3a7713b1edbc | 891 | #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ |
AnnaBridge | 171:3a7713b1edbc | 892 | |
AnnaBridge | 171:3a7713b1edbc | 893 | /* Bit fields for CMU OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 894 | #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 895 | #define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 896 | #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ |
AnnaBridge | 171:3a7713b1edbc | 897 | #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ |
AnnaBridge | 171:3a7713b1edbc | 898 | #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ |
AnnaBridge | 171:3a7713b1edbc | 899 | #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 900 | #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 901 | #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ |
AnnaBridge | 171:3a7713b1edbc | 902 | #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ |
AnnaBridge | 171:3a7713b1edbc | 903 | #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ |
AnnaBridge | 171:3a7713b1edbc | 904 | #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 905 | #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 906 | #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ |
AnnaBridge | 171:3a7713b1edbc | 907 | #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ |
AnnaBridge | 171:3a7713b1edbc | 908 | #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ |
AnnaBridge | 171:3a7713b1edbc | 909 | #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 910 | #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 911 | #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ |
AnnaBridge | 171:3a7713b1edbc | 912 | #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ |
AnnaBridge | 171:3a7713b1edbc | 913 | #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ |
AnnaBridge | 171:3a7713b1edbc | 914 | #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 915 | #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 916 | #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ |
AnnaBridge | 171:3a7713b1edbc | 917 | #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ |
AnnaBridge | 171:3a7713b1edbc | 918 | #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ |
AnnaBridge | 171:3a7713b1edbc | 919 | #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 920 | #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 921 | #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ |
AnnaBridge | 171:3a7713b1edbc | 922 | #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ |
AnnaBridge | 171:3a7713b1edbc | 923 | #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ |
AnnaBridge | 171:3a7713b1edbc | 924 | #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 925 | #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 926 | #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ |
AnnaBridge | 171:3a7713b1edbc | 927 | #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ |
AnnaBridge | 171:3a7713b1edbc | 928 | #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ |
AnnaBridge | 171:3a7713b1edbc | 929 | #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 930 | #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 931 | #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ |
AnnaBridge | 171:3a7713b1edbc | 932 | #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ |
AnnaBridge | 171:3a7713b1edbc | 933 | #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ |
AnnaBridge | 171:3a7713b1edbc | 934 | #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 935 | #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 936 | #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ |
AnnaBridge | 171:3a7713b1edbc | 937 | #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ |
AnnaBridge | 171:3a7713b1edbc | 938 | #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ |
AnnaBridge | 171:3a7713b1edbc | 939 | #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 940 | #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 941 | #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ |
AnnaBridge | 171:3a7713b1edbc | 942 | #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ |
AnnaBridge | 171:3a7713b1edbc | 943 | #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ |
AnnaBridge | 171:3a7713b1edbc | 944 | #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 945 | #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 171:3a7713b1edbc | 946 | |
AnnaBridge | 171:3a7713b1edbc | 947 | /* Bit fields for CMU CMD */ |
AnnaBridge | 171:3a7713b1edbc | 948 | #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 949 | #define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 950 | #define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 951 | #define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 952 | #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 953 | #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 954 | #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 955 | #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 956 | #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 957 | #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 958 | #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 959 | #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 960 | #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 961 | #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 962 | #define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */ |
AnnaBridge | 171:3a7713b1edbc | 963 | #define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */ |
AnnaBridge | 171:3a7713b1edbc | 964 | #define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */ |
AnnaBridge | 171:3a7713b1edbc | 965 | #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 966 | #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 967 | #define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */ |
AnnaBridge | 171:3a7713b1edbc | 968 | #define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */ |
AnnaBridge | 171:3a7713b1edbc | 969 | #define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */ |
AnnaBridge | 171:3a7713b1edbc | 970 | #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 971 | #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ |
AnnaBridge | 171:3a7713b1edbc | 972 | |
AnnaBridge | 171:3a7713b1edbc | 973 | /* Bit fields for CMU LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 974 | #define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 975 | #define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 976 | #define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ |
AnnaBridge | 171:3a7713b1edbc | 977 | #define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */ |
AnnaBridge | 171:3a7713b1edbc | 978 | #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 979 | #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 980 | #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 981 | #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 982 | #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 983 | #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 984 | #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 985 | #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 986 | #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 987 | #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 988 | #define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */ |
AnnaBridge | 171:3a7713b1edbc | 989 | #define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */ |
AnnaBridge | 171:3a7713b1edbc | 990 | #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 991 | #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 992 | #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 993 | #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 994 | #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 995 | #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 996 | #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 997 | #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 998 | #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 999 | #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1000 | #define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */ |
AnnaBridge | 171:3a7713b1edbc | 1001 | #define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */ |
AnnaBridge | 171:3a7713b1edbc | 1002 | #define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */ |
AnnaBridge | 171:3a7713b1edbc | 1003 | #define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1004 | #define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1005 | #define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1006 | #define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1007 | #define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1008 | #define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1009 | #define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */ |
AnnaBridge | 171:3a7713b1edbc | 1010 | #define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */ |
AnnaBridge | 171:3a7713b1edbc | 1011 | #define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */ |
AnnaBridge | 171:3a7713b1edbc | 1012 | #define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1013 | #define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1014 | #define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1015 | #define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1016 | #define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1017 | #define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1018 | |
AnnaBridge | 171:3a7713b1edbc | 1019 | /* Bit fields for CMU STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1020 | #define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1021 | #define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1022 | #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ |
AnnaBridge | 171:3a7713b1edbc | 1023 | #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ |
AnnaBridge | 171:3a7713b1edbc | 1024 | #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ |
AnnaBridge | 171:3a7713b1edbc | 1025 | #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1026 | #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1027 | #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ |
AnnaBridge | 171:3a7713b1edbc | 1028 | #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1029 | #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1030 | #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1031 | #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1032 | #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ |
AnnaBridge | 171:3a7713b1edbc | 1033 | #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ |
AnnaBridge | 171:3a7713b1edbc | 1034 | #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ |
AnnaBridge | 171:3a7713b1edbc | 1035 | #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1036 | #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1037 | #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ |
AnnaBridge | 171:3a7713b1edbc | 1038 | #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1039 | #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1040 | #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1041 | #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1042 | #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ |
AnnaBridge | 171:3a7713b1edbc | 1043 | #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ |
AnnaBridge | 171:3a7713b1edbc | 1044 | #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ |
AnnaBridge | 171:3a7713b1edbc | 1045 | #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1046 | #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1047 | #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ |
AnnaBridge | 171:3a7713b1edbc | 1048 | #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1049 | #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1050 | #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1051 | #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1052 | #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ |
AnnaBridge | 171:3a7713b1edbc | 1053 | #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ |
AnnaBridge | 171:3a7713b1edbc | 1054 | #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ |
AnnaBridge | 171:3a7713b1edbc | 1055 | #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1056 | #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1057 | #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ |
AnnaBridge | 171:3a7713b1edbc | 1058 | #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1059 | #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1060 | #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1061 | #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1062 | #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ |
AnnaBridge | 171:3a7713b1edbc | 1063 | #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ |
AnnaBridge | 171:3a7713b1edbc | 1064 | #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ |
AnnaBridge | 171:3a7713b1edbc | 1065 | #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1066 | #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1067 | #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ |
AnnaBridge | 171:3a7713b1edbc | 1068 | #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1069 | #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1070 | #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1071 | #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1072 | #define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */ |
AnnaBridge | 171:3a7713b1edbc | 1073 | #define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1074 | #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1075 | #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1076 | #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1077 | #define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */ |
AnnaBridge | 171:3a7713b1edbc | 1078 | #define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1079 | #define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1080 | #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1081 | #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1082 | #define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */ |
AnnaBridge | 171:3a7713b1edbc | 1083 | #define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1084 | #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1085 | #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1086 | #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1087 | #define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */ |
AnnaBridge | 171:3a7713b1edbc | 1088 | #define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1089 | #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1090 | #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1091 | #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1092 | #define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */ |
AnnaBridge | 171:3a7713b1edbc | 1093 | #define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */ |
AnnaBridge | 171:3a7713b1edbc | 1094 | #define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */ |
AnnaBridge | 171:3a7713b1edbc | 1095 | #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1096 | #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 171:3a7713b1edbc | 1097 | |
AnnaBridge | 171:3a7713b1edbc | 1098 | /* Bit fields for CMU IF */ |
AnnaBridge | 171:3a7713b1edbc | 1099 | #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 1100 | #define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 1101 | #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1102 | #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1103 | #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1104 | #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 1105 | #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 1106 | #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1107 | #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1108 | #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1109 | #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 1110 | #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 1111 | #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1112 | #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1113 | #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1114 | #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 1115 | #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 1116 | #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1117 | #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1118 | #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1119 | #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 1120 | #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 1121 | #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1122 | #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1123 | #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1124 | #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 1125 | #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 1126 | #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1127 | #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ |
AnnaBridge | 171:3a7713b1edbc | 1128 | #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ |
AnnaBridge | 171:3a7713b1edbc | 1129 | #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 1130 | #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 1131 | #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1132 | #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ |
AnnaBridge | 171:3a7713b1edbc | 1133 | #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ |
AnnaBridge | 171:3a7713b1edbc | 1134 | #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 1135 | #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 171:3a7713b1edbc | 1136 | |
AnnaBridge | 171:3a7713b1edbc | 1137 | /* Bit fields for CMU IFS */ |
AnnaBridge | 171:3a7713b1edbc | 1138 | #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 1139 | #define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 1140 | #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */ |
AnnaBridge | 171:3a7713b1edbc | 1141 | #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1142 | #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1143 | #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 1144 | #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 1145 | #define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */ |
AnnaBridge | 171:3a7713b1edbc | 1146 | #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1147 | #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1148 | #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 1149 | #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 1150 | #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */ |
AnnaBridge | 171:3a7713b1edbc | 1151 | #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1152 | #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1153 | #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 1154 | #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 1155 | #define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */ |
AnnaBridge | 171:3a7713b1edbc | 1156 | #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1157 | #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1158 | #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 1159 | #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 1160 | #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */ |
AnnaBridge | 171:3a7713b1edbc | 1161 | #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1162 | #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1163 | #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 1164 | #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 1165 | #define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */ |
AnnaBridge | 171:3a7713b1edbc | 1166 | #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ |
AnnaBridge | 171:3a7713b1edbc | 1167 | #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ |
AnnaBridge | 171:3a7713b1edbc | 1168 | #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 1169 | #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 1170 | #define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */ |
AnnaBridge | 171:3a7713b1edbc | 1171 | #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ |
AnnaBridge | 171:3a7713b1edbc | 1172 | #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ |
AnnaBridge | 171:3a7713b1edbc | 1173 | #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 1174 | #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 171:3a7713b1edbc | 1175 | |
AnnaBridge | 171:3a7713b1edbc | 1176 | /* Bit fields for CMU IFC */ |
AnnaBridge | 171:3a7713b1edbc | 1177 | #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 1178 | #define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 1179 | #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */ |
AnnaBridge | 171:3a7713b1edbc | 1180 | #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1181 | #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1182 | #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 1183 | #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 1184 | #define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */ |
AnnaBridge | 171:3a7713b1edbc | 1185 | #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1186 | #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1187 | #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 1188 | #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 1189 | #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */ |
AnnaBridge | 171:3a7713b1edbc | 1190 | #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1191 | #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1192 | #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 1193 | #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 1194 | #define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */ |
AnnaBridge | 171:3a7713b1edbc | 1195 | #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1196 | #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1197 | #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 1198 | #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 1199 | #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */ |
AnnaBridge | 171:3a7713b1edbc | 1200 | #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1201 | #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1202 | #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 1203 | #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 1204 | #define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */ |
AnnaBridge | 171:3a7713b1edbc | 1205 | #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ |
AnnaBridge | 171:3a7713b1edbc | 1206 | #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ |
AnnaBridge | 171:3a7713b1edbc | 1207 | #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 1208 | #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 1209 | #define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */ |
AnnaBridge | 171:3a7713b1edbc | 1210 | #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ |
AnnaBridge | 171:3a7713b1edbc | 1211 | #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ |
AnnaBridge | 171:3a7713b1edbc | 1212 | #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 1213 | #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 171:3a7713b1edbc | 1214 | |
AnnaBridge | 171:3a7713b1edbc | 1215 | /* Bit fields for CMU IEN */ |
AnnaBridge | 171:3a7713b1edbc | 1216 | #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 1217 | #define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 1218 | #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1219 | #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1220 | #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1221 | #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 1222 | #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 1223 | #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1224 | #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1225 | #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1226 | #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 1227 | #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 1228 | #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1229 | #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1230 | #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1231 | #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 1232 | #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 1233 | #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1234 | #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1235 | #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1236 | #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 1237 | #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 1238 | #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1239 | #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1240 | #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ |
AnnaBridge | 171:3a7713b1edbc | 1241 | #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 1242 | #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 1243 | #define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1244 | #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ |
AnnaBridge | 171:3a7713b1edbc | 1245 | #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ |
AnnaBridge | 171:3a7713b1edbc | 1246 | #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 1247 | #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 1248 | #define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1249 | #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ |
AnnaBridge | 171:3a7713b1edbc | 1250 | #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ |
AnnaBridge | 171:3a7713b1edbc | 1251 | #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 1252 | #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 171:3a7713b1edbc | 1253 | |
AnnaBridge | 171:3a7713b1edbc | 1254 | /* Bit fields for CMU HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1255 | #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1256 | #define _CMU_HFCORECLKEN0_MASK 0x00000033UL /**< Mask for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1257 | #define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1258 | #define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */ |
AnnaBridge | 171:3a7713b1edbc | 1259 | #define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */ |
AnnaBridge | 171:3a7713b1edbc | 1260 | #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1261 | #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1262 | #define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1263 | #define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */ |
AnnaBridge | 171:3a7713b1edbc | 1264 | #define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */ |
AnnaBridge | 171:3a7713b1edbc | 1265 | #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1266 | #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1267 | #define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1268 | #define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */ |
AnnaBridge | 171:3a7713b1edbc | 1269 | #define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */ |
AnnaBridge | 171:3a7713b1edbc | 1270 | #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1271 | #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1272 | #define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1273 | #define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */ |
AnnaBridge | 171:3a7713b1edbc | 1274 | #define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */ |
AnnaBridge | 171:3a7713b1edbc | 1275 | #define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1276 | #define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1277 | |
AnnaBridge | 171:3a7713b1edbc | 1278 | /* Bit fields for CMU HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1279 | #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1280 | #define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1281 | #define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1282 | #define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */ |
AnnaBridge | 171:3a7713b1edbc | 1283 | #define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */ |
AnnaBridge | 171:3a7713b1edbc | 1284 | #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1285 | #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1286 | #define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1287 | #define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */ |
AnnaBridge | 171:3a7713b1edbc | 1288 | #define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */ |
AnnaBridge | 171:3a7713b1edbc | 1289 | #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1290 | #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1291 | #define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1292 | #define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */ |
AnnaBridge | 171:3a7713b1edbc | 1293 | #define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */ |
AnnaBridge | 171:3a7713b1edbc | 1294 | #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1295 | #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1296 | #define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1297 | #define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */ |
AnnaBridge | 171:3a7713b1edbc | 1298 | #define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */ |
AnnaBridge | 171:3a7713b1edbc | 1299 | #define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1300 | #define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1301 | #define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1302 | #define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */ |
AnnaBridge | 171:3a7713b1edbc | 1303 | #define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */ |
AnnaBridge | 171:3a7713b1edbc | 1304 | #define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1305 | #define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1306 | #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1307 | #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */ |
AnnaBridge | 171:3a7713b1edbc | 1308 | #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */ |
AnnaBridge | 171:3a7713b1edbc | 1309 | #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1310 | #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1311 | #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1312 | #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */ |
AnnaBridge | 171:3a7713b1edbc | 1313 | #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */ |
AnnaBridge | 171:3a7713b1edbc | 1314 | #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1315 | #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1316 | #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1317 | #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */ |
AnnaBridge | 171:3a7713b1edbc | 1318 | #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */ |
AnnaBridge | 171:3a7713b1edbc | 1319 | #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1320 | #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1321 | #define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1322 | #define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */ |
AnnaBridge | 171:3a7713b1edbc | 1323 | #define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */ |
AnnaBridge | 171:3a7713b1edbc | 1324 | #define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1325 | #define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1326 | #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1327 | #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */ |
AnnaBridge | 171:3a7713b1edbc | 1328 | #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */ |
AnnaBridge | 171:3a7713b1edbc | 1329 | #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1330 | #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1331 | #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1332 | #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */ |
AnnaBridge | 171:3a7713b1edbc | 1333 | #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */ |
AnnaBridge | 171:3a7713b1edbc | 1334 | #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1335 | #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1336 | #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1337 | #define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */ |
AnnaBridge | 171:3a7713b1edbc | 1338 | #define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */ |
AnnaBridge | 171:3a7713b1edbc | 1339 | #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1340 | #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1341 | #define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1342 | #define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */ |
AnnaBridge | 171:3a7713b1edbc | 1343 | #define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */ |
AnnaBridge | 171:3a7713b1edbc | 1344 | #define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1345 | #define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1346 | #define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1347 | #define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */ |
AnnaBridge | 171:3a7713b1edbc | 1348 | #define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */ |
AnnaBridge | 171:3a7713b1edbc | 1349 | #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1350 | #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1351 | #define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1352 | #define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */ |
AnnaBridge | 171:3a7713b1edbc | 1353 | #define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */ |
AnnaBridge | 171:3a7713b1edbc | 1354 | #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1355 | #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1356 | #define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1357 | #define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */ |
AnnaBridge | 171:3a7713b1edbc | 1358 | #define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */ |
AnnaBridge | 171:3a7713b1edbc | 1359 | #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1360 | #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1361 | #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1362 | #define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1363 | #define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1364 | #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1365 | #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1366 | #define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1367 | #define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1368 | #define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1369 | #define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1370 | #define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1371 | |
AnnaBridge | 171:3a7713b1edbc | 1372 | /* Bit fields for CMU SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 1373 | #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 1374 | #define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 1375 | #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */ |
AnnaBridge | 171:3a7713b1edbc | 1376 | #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1377 | #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1378 | #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 1379 | #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 1380 | #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */ |
AnnaBridge | 171:3a7713b1edbc | 1381 | #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1382 | #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1383 | #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 1384 | #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 1385 | #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ |
AnnaBridge | 171:3a7713b1edbc | 1386 | #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1387 | #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1388 | #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 1389 | #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 1390 | #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ |
AnnaBridge | 171:3a7713b1edbc | 1391 | #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1392 | #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1393 | #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 1394 | #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 171:3a7713b1edbc | 1395 | |
AnnaBridge | 171:3a7713b1edbc | 1396 | /* Bit fields for CMU FREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 1397 | #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 1398 | #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 1399 | #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ |
AnnaBridge | 171:3a7713b1edbc | 1400 | #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 1401 | #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 1402 | #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 1403 | #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 1404 | #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 1405 | #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 1406 | #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 1407 | #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ |
AnnaBridge | 171:3a7713b1edbc | 1408 | |
AnnaBridge | 171:3a7713b1edbc | 1409 | /* Bit fields for CMU LFACLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1410 | #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1411 | #define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1412 | #define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1413 | #define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */ |
AnnaBridge | 171:3a7713b1edbc | 1414 | #define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */ |
AnnaBridge | 171:3a7713b1edbc | 1415 | #define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1416 | #define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1417 | #define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1418 | #define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */ |
AnnaBridge | 171:3a7713b1edbc | 1419 | #define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */ |
AnnaBridge | 171:3a7713b1edbc | 1420 | #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1421 | #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1422 | #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1423 | #define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */ |
AnnaBridge | 171:3a7713b1edbc | 1424 | #define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */ |
AnnaBridge | 171:3a7713b1edbc | 1425 | #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1426 | #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1427 | |
AnnaBridge | 171:3a7713b1edbc | 1428 | /* Bit fields for CMU LFBCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1429 | #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1430 | #define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1431 | #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1432 | #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ |
AnnaBridge | 171:3a7713b1edbc | 1433 | #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ |
AnnaBridge | 171:3a7713b1edbc | 1434 | #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1435 | #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1436 | #define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1437 | #define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ |
AnnaBridge | 171:3a7713b1edbc | 1438 | #define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ |
AnnaBridge | 171:3a7713b1edbc | 1439 | #define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1440 | #define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ |
AnnaBridge | 171:3a7713b1edbc | 1441 | |
AnnaBridge | 171:3a7713b1edbc | 1442 | /* Bit fields for CMU LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1443 | #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1444 | #define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1445 | #define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */ |
AnnaBridge | 171:3a7713b1edbc | 1446 | #define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */ |
AnnaBridge | 171:3a7713b1edbc | 1447 | #define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1448 | #define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1449 | #define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1450 | #define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1451 | #define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1452 | #define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1453 | #define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1454 | #define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1455 | #define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ |
AnnaBridge | 171:3a7713b1edbc | 1456 | #define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */ |
AnnaBridge | 171:3a7713b1edbc | 1457 | #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1458 | #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1459 | #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1460 | #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1461 | #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1462 | #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1463 | #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1464 | #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1465 | #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1466 | #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1467 | #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1468 | #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1469 | #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1470 | #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1471 | #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1472 | #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1473 | #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1474 | #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1475 | #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1476 | #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1477 | #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1478 | #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1479 | #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1480 | #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1481 | #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1482 | #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1483 | #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1484 | #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1485 | #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1486 | #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1487 | #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1488 | #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1489 | #define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */ |
AnnaBridge | 171:3a7713b1edbc | 1490 | #define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */ |
AnnaBridge | 171:3a7713b1edbc | 1491 | #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1492 | #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1493 | #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1494 | #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1495 | #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1496 | #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1497 | #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1498 | #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1499 | #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1500 | #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1501 | #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1502 | #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1503 | #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1504 | #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1505 | #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1506 | #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1507 | #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1508 | #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1509 | #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1510 | #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1511 | #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1512 | #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1513 | #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1514 | #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1515 | #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1516 | #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1517 | #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1518 | #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1519 | #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1520 | #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1521 | #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1522 | #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1523 | |
AnnaBridge | 171:3a7713b1edbc | 1524 | /* Bit fields for CMU LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1525 | #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1526 | #define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1527 | #define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ |
AnnaBridge | 171:3a7713b1edbc | 1528 | #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ |
AnnaBridge | 171:3a7713b1edbc | 1529 | #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1530 | #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1531 | #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1532 | #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1533 | #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1534 | #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1535 | #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1536 | #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1537 | #define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ |
AnnaBridge | 171:3a7713b1edbc | 1538 | #define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ |
AnnaBridge | 171:3a7713b1edbc | 1539 | #define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1540 | #define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1541 | #define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1542 | #define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1543 | #define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1544 | #define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1545 | #define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1546 | #define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ |
AnnaBridge | 171:3a7713b1edbc | 1547 | |
AnnaBridge | 171:3a7713b1edbc | 1548 | /* Bit fields for CMU PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1549 | #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1550 | #define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1551 | #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1552 | #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ |
AnnaBridge | 171:3a7713b1edbc | 1553 | #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ |
AnnaBridge | 171:3a7713b1edbc | 1554 | #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1555 | #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1556 | #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 1557 | #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1558 | #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1559 | #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1560 | #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1561 | #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1562 | #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1563 | #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1564 | #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1565 | #define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1566 | #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ |
AnnaBridge | 171:3a7713b1edbc | 1567 | #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ |
AnnaBridge | 171:3a7713b1edbc | 1568 | #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1569 | #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1570 | #define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 1571 | #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1572 | #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1573 | #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1574 | #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1575 | #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1576 | #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1577 | #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1578 | #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1579 | #define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1580 | #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ |
AnnaBridge | 171:3a7713b1edbc | 1581 | #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ |
AnnaBridge | 171:3a7713b1edbc | 1582 | #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1583 | #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1584 | #define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 1585 | #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1586 | #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1587 | #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1588 | #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1589 | #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1590 | #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1591 | #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1592 | #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1593 | |
AnnaBridge | 171:3a7713b1edbc | 1594 | /* Bit fields for CMU ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1595 | #define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1596 | #define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1597 | #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1598 | #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ |
AnnaBridge | 171:3a7713b1edbc | 1599 | #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ |
AnnaBridge | 171:3a7713b1edbc | 1600 | #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1601 | #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1602 | #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1603 | #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ |
AnnaBridge | 171:3a7713b1edbc | 1604 | #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ |
AnnaBridge | 171:3a7713b1edbc | 1605 | #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1606 | #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1607 | #define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */ |
AnnaBridge | 171:3a7713b1edbc | 1608 | #define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */ |
AnnaBridge | 171:3a7713b1edbc | 1609 | #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1610 | #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1611 | #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1612 | #define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1613 | #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1614 | #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1615 | #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1616 | #define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1617 | |
AnnaBridge | 171:3a7713b1edbc | 1618 | /* Bit fields for CMU LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1619 | #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1620 | #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1621 | #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ |
AnnaBridge | 171:3a7713b1edbc | 1622 | #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ |
AnnaBridge | 171:3a7713b1edbc | 1623 | #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1624 | #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1625 | #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1626 | #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1627 | #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1628 | #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1629 | #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1630 | #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1631 | #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1632 | #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ |
AnnaBridge | 171:3a7713b1edbc | 1633 | |
AnnaBridge | 171:3a7713b1edbc | 1634 | /** @} End of group EFM32GG290F512_CMU */ |
AnnaBridge | 171:3a7713b1edbc | 1635 | |
AnnaBridge | 171:3a7713b1edbc | 1636 | |
AnnaBridge | 171:3a7713b1edbc | 1637 | |
AnnaBridge | 171:3a7713b1edbc | 1638 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 1639 | * @defgroup EFM32GG290F512_PRS_BitFields EFM32GG290F512_PRS Bit Fields |
AnnaBridge | 171:3a7713b1edbc | 1640 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1641 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 1642 | |
AnnaBridge | 171:3a7713b1edbc | 1643 | /* Bit fields for PRS SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1644 | #define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1645 | #define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1646 | #define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ |
AnnaBridge | 171:3a7713b1edbc | 1647 | #define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1648 | #define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1649 | #define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1650 | #define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1651 | #define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ |
AnnaBridge | 171:3a7713b1edbc | 1652 | #define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1653 | #define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1654 | #define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1655 | #define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1656 | #define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ |
AnnaBridge | 171:3a7713b1edbc | 1657 | #define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1658 | #define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1659 | #define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1660 | #define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1661 | #define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ |
AnnaBridge | 171:3a7713b1edbc | 1662 | #define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1663 | #define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1664 | #define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1665 | #define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1666 | #define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ |
AnnaBridge | 171:3a7713b1edbc | 1667 | #define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1668 | #define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1669 | #define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1670 | #define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1671 | #define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ |
AnnaBridge | 171:3a7713b1edbc | 1672 | #define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1673 | #define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1674 | #define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1675 | #define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1676 | #define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ |
AnnaBridge | 171:3a7713b1edbc | 1677 | #define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1678 | #define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1679 | #define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1680 | #define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1681 | #define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ |
AnnaBridge | 171:3a7713b1edbc | 1682 | #define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1683 | #define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1684 | #define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1685 | #define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1686 | #define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ |
AnnaBridge | 171:3a7713b1edbc | 1687 | #define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1688 | #define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1689 | #define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1690 | #define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1691 | #define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ |
AnnaBridge | 171:3a7713b1edbc | 1692 | #define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1693 | #define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1694 | #define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1695 | #define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1696 | #define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ |
AnnaBridge | 171:3a7713b1edbc | 1697 | #define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1698 | #define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1699 | #define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1700 | #define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1701 | #define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ |
AnnaBridge | 171:3a7713b1edbc | 1702 | #define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1703 | #define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1704 | #define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1705 | #define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 171:3a7713b1edbc | 1706 | |
AnnaBridge | 171:3a7713b1edbc | 1707 | /* Bit fields for PRS SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1708 | #define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1709 | #define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1710 | #define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ |
AnnaBridge | 171:3a7713b1edbc | 1711 | #define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1712 | #define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1713 | #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1714 | #define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1715 | #define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ |
AnnaBridge | 171:3a7713b1edbc | 1716 | #define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1717 | #define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1718 | #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1719 | #define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1720 | #define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ |
AnnaBridge | 171:3a7713b1edbc | 1721 | #define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1722 | #define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1723 | #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1724 | #define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1725 | #define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ |
AnnaBridge | 171:3a7713b1edbc | 1726 | #define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1727 | #define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1728 | #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1729 | #define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1730 | #define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ |
AnnaBridge | 171:3a7713b1edbc | 1731 | #define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1732 | #define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1733 | #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1734 | #define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1735 | #define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ |
AnnaBridge | 171:3a7713b1edbc | 1736 | #define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1737 | #define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1738 | #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1739 | #define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1740 | #define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ |
AnnaBridge | 171:3a7713b1edbc | 1741 | #define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1742 | #define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1743 | #define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1744 | #define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1745 | #define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ |
AnnaBridge | 171:3a7713b1edbc | 1746 | #define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1747 | #define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1748 | #define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1749 | #define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1750 | #define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ |
AnnaBridge | 171:3a7713b1edbc | 1751 | #define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1752 | #define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1753 | #define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1754 | #define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1755 | #define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ |
AnnaBridge | 171:3a7713b1edbc | 1756 | #define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1757 | #define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1758 | #define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1759 | #define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1760 | #define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ |
AnnaBridge | 171:3a7713b1edbc | 1761 | #define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1762 | #define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1763 | #define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1764 | #define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1765 | #define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ |
AnnaBridge | 171:3a7713b1edbc | 1766 | #define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1767 | #define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1768 | #define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1769 | #define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 171:3a7713b1edbc | 1770 | |
AnnaBridge | 171:3a7713b1edbc | 1771 | /* Bit fields for PRS ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1772 | #define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1773 | #define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1774 | #define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1775 | #define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ |
AnnaBridge | 171:3a7713b1edbc | 1776 | #define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ |
AnnaBridge | 171:3a7713b1edbc | 1777 | #define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1778 | #define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1779 | #define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1780 | #define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ |
AnnaBridge | 171:3a7713b1edbc | 1781 | #define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ |
AnnaBridge | 171:3a7713b1edbc | 1782 | #define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1783 | #define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1784 | #define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1785 | #define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ |
AnnaBridge | 171:3a7713b1edbc | 1786 | #define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ |
AnnaBridge | 171:3a7713b1edbc | 1787 | #define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1788 | #define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1789 | #define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1790 | #define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ |
AnnaBridge | 171:3a7713b1edbc | 1791 | #define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ |
AnnaBridge | 171:3a7713b1edbc | 1792 | #define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1793 | #define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1794 | #define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */ |
AnnaBridge | 171:3a7713b1edbc | 1795 | #define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */ |
AnnaBridge | 171:3a7713b1edbc | 1796 | #define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1797 | #define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1798 | #define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1799 | #define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1800 | #define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1801 | #define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */ |
AnnaBridge | 171:3a7713b1edbc | 1802 | |
AnnaBridge | 171:3a7713b1edbc | 1803 | /* Bit fields for PRS CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1804 | #define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1805 | #define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1806 | #define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1807 | #define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ |
AnnaBridge | 171:3a7713b1edbc | 1808 | #define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1809 | #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1810 | #define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1811 | #define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1812 | #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1813 | #define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1814 | #define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1815 | #define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1816 | #define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1817 | #define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1818 | #define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1819 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1820 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1821 | #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1822 | #define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1823 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1824 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1825 | #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1826 | #define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1827 | #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1828 | #define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1829 | #define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1830 | #define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1831 | #define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1832 | #define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1833 | #define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1834 | #define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1835 | #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1836 | #define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1837 | #define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1838 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1839 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1840 | #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1841 | #define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1842 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1843 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1844 | #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1845 | #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1846 | #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1847 | #define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1848 | #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1849 | #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1850 | #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1851 | #define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1852 | #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1853 | #define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1854 | #define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1855 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1856 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1857 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1858 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1859 | #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1860 | #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1861 | #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1862 | #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1863 | #define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1864 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1865 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1866 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1867 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1868 | #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1869 | #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1870 | #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1871 | #define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1872 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1873 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1874 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1875 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1876 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1877 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1878 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1879 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1880 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1881 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1882 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1883 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1884 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1885 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1886 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1887 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1888 | #define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1889 | #define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1890 | #define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1891 | #define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1892 | #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1893 | #define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1894 | #define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1895 | #define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1896 | #define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1897 | #define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1898 | #define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1899 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1900 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1901 | #define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1902 | #define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1903 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1904 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1905 | #define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1906 | #define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1907 | #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1908 | #define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1909 | #define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1910 | #define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1911 | #define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1912 | #define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1913 | #define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1914 | #define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1915 | #define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1916 | #define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1917 | #define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1918 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1919 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1920 | #define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1921 | #define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1922 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1923 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1924 | #define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1925 | #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1926 | #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1927 | #define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1928 | #define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1929 | #define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1930 | #define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1931 | #define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1932 | #define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1933 | #define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1934 | #define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1935 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1936 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1937 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1938 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1939 | #define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1940 | #define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1941 | #define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1942 | #define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1943 | #define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1944 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1945 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1946 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1947 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1948 | #define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1949 | #define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1950 | #define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1951 | #define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1952 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1953 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1954 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1955 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1956 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1957 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1958 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1959 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1960 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1961 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1962 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1963 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1964 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1965 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1966 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1967 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1968 | #define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */ |
AnnaBridge | 171:3a7713b1edbc | 1969 | #define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */ |
AnnaBridge | 171:3a7713b1edbc | 1970 | #define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1971 | #define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1972 | #define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1973 | #define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1974 | #define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1975 | #define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1976 | #define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1977 | #define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1978 | #define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1979 | #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1980 | #define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1981 | #define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1982 | #define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1983 | #define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1984 | #define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL /**< Mode UART0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1985 | #define _PRS_CH_CTRL_SOURCESEL_UART1 0x0000002AUL /**< Mode UART1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1986 | #define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1987 | #define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1988 | #define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1989 | #define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1990 | #define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1991 | #define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1992 | #define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1993 | #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1994 | #define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1995 | #define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1996 | #define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1997 | #define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1998 | #define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 1999 | #define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2000 | #define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2001 | #define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2002 | #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2003 | #define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2004 | #define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2005 | #define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2006 | #define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2007 | #define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2008 | #define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2009 | #define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2010 | #define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2011 | #define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2012 | #define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2013 | #define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2014 | #define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2015 | #define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2016 | #define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */ |
AnnaBridge | 171:3a7713b1edbc | 2017 | #define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */ |
AnnaBridge | 171:3a7713b1edbc | 2018 | #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2019 | #define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2020 | #define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2021 | #define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2022 | #define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2023 | #define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2024 | #define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2025 | #define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2026 | #define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2027 | #define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2028 | #define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */ |
AnnaBridge | 171:3a7713b1edbc | 2029 | #define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */ |
AnnaBridge | 171:3a7713b1edbc | 2030 | #define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */ |
AnnaBridge | 171:3a7713b1edbc | 2031 | #define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2032 | #define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 2033 | |
AnnaBridge | 171:3a7713b1edbc | 2034 | /** @} End of group EFM32GG290F512_PRS */ |
AnnaBridge | 171:3a7713b1edbc | 2035 | |
AnnaBridge | 171:3a7713b1edbc | 2036 | |
AnnaBridge | 171:3a7713b1edbc | 2037 | |
AnnaBridge | 171:3a7713b1edbc | 2038 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 2039 | * @defgroup EFM32GG290F512_UNLOCK EFM32GG290F512 Unlock Codes |
AnnaBridge | 171:3a7713b1edbc | 2040 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2041 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 2042 | #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ |
AnnaBridge | 171:3a7713b1edbc | 2043 | #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ |
AnnaBridge | 171:3a7713b1edbc | 2044 | #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ |
AnnaBridge | 171:3a7713b1edbc | 2045 | #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ |
AnnaBridge | 171:3a7713b1edbc | 2046 | #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ |
AnnaBridge | 171:3a7713b1edbc | 2047 | #define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */ |
AnnaBridge | 171:3a7713b1edbc | 2048 | |
AnnaBridge | 171:3a7713b1edbc | 2049 | /** @} End of group EFM32GG290F512_UNLOCK */ |
AnnaBridge | 171:3a7713b1edbc | 2050 | |
AnnaBridge | 171:3a7713b1edbc | 2051 | /** @} End of group EFM32GG290F512_BitFields */ |
AnnaBridge | 171:3a7713b1edbc | 2052 | |
AnnaBridge | 171:3a7713b1edbc | 2053 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 2054 | * @defgroup EFM32GG290F512_Alternate_Function EFM32GG290F512 Alternate Function |
AnnaBridge | 171:3a7713b1edbc | 2055 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2056 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 2057 | |
AnnaBridge | 171:3a7713b1edbc | 2058 | #include "efm32gg_af_ports.h" |
AnnaBridge | 171:3a7713b1edbc | 2059 | #include "efm32gg_af_pins.h" |
AnnaBridge | 171:3a7713b1edbc | 2060 | |
AnnaBridge | 171:3a7713b1edbc | 2061 | /** @} End of group EFM32GG290F512_Alternate_Function */ |
AnnaBridge | 171:3a7713b1edbc | 2062 | |
AnnaBridge | 171:3a7713b1edbc | 2063 | /**************************************************************************//** |
AnnaBridge | 171:3a7713b1edbc | 2064 | * @brief Set the value of a bit field within a register. |
AnnaBridge | 171:3a7713b1edbc | 2065 | * |
AnnaBridge | 171:3a7713b1edbc | 2066 | * @param REG |
AnnaBridge | 171:3a7713b1edbc | 2067 | * The register to update |
AnnaBridge | 171:3a7713b1edbc | 2068 | * @param MASK |
AnnaBridge | 171:3a7713b1edbc | 2069 | * The mask for the bit field to update |
AnnaBridge | 171:3a7713b1edbc | 2070 | * @param VALUE |
AnnaBridge | 171:3a7713b1edbc | 2071 | * The value to write to the bit field |
AnnaBridge | 171:3a7713b1edbc | 2072 | * @param OFFSET |
AnnaBridge | 171:3a7713b1edbc | 2073 | * The number of bits that the field is offset within the register. |
AnnaBridge | 171:3a7713b1edbc | 2074 | * 0 (zero) means LSB. |
AnnaBridge | 171:3a7713b1edbc | 2075 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 2076 | #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ |
AnnaBridge | 171:3a7713b1edbc | 2077 | REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); |
AnnaBridge | 171:3a7713b1edbc | 2078 | |
AnnaBridge | 171:3a7713b1edbc | 2079 | /** @} End of group EFM32GG290F512 */ |
AnnaBridge | 171:3a7713b1edbc | 2080 | |
AnnaBridge | 171:3a7713b1edbc | 2081 | /** @} End of group Parts */ |
AnnaBridge | 171:3a7713b1edbc | 2082 | |
AnnaBridge | 171:3a7713b1edbc | 2083 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 2084 | } |
AnnaBridge | 171:3a7713b1edbc | 2085 | #endif |
AnnaBridge | 171:3a7713b1edbc | 2086 | #endif /* EFM32GG290F512_H */ |