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TARGET_EFM32GG_STK3700/TOOLCHAIN_GCC_ARM/em_cmu.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_EFM32ZG_STK3200/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h@160:5571c4ff569f 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 2 * @file em_cmu.h
AnnaBridge 156:ff21514d8981 3 * @brief Clock management unit (CMU) API
Anna Bridge 160:5571c4ff569f 4 * @version 5.3.3
AnnaBridge 156:ff21514d8981 5 *******************************************************************************
Anna Bridge 160:5571c4ff569f 6 * # License
AnnaBridge 156:ff21514d8981 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 156:ff21514d8981 8 *******************************************************************************
AnnaBridge 156:ff21514d8981 9 *
AnnaBridge 156:ff21514d8981 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 156:ff21514d8981 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 156:ff21514d8981 12 * freely, subject to the following restrictions:
AnnaBridge 156:ff21514d8981 13 *
AnnaBridge 156:ff21514d8981 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 156:ff21514d8981 15 * claim that you wrote the original software.
AnnaBridge 156:ff21514d8981 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 156:ff21514d8981 17 * misrepresented as being the original software.
AnnaBridge 156:ff21514d8981 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 156:ff21514d8981 19 *
AnnaBridge 156:ff21514d8981 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
AnnaBridge 156:ff21514d8981 21 * obligation to support this Software. Silicon Labs is providing the
AnnaBridge 156:ff21514d8981 22 * Software "AS IS", with no express or implied warranties of any kind,
AnnaBridge 156:ff21514d8981 23 * including, but not limited to, any implied warranties of merchantability
AnnaBridge 156:ff21514d8981 24 * or fitness for any particular purpose or warranties against infringement
AnnaBridge 156:ff21514d8981 25 * of any proprietary rights of a third party.
AnnaBridge 156:ff21514d8981 26 *
AnnaBridge 156:ff21514d8981 27 * Silicon Labs will not be liable for any consequential, incidental, or
AnnaBridge 156:ff21514d8981 28 * special damages, or any other relief, or for any claim by any third party,
AnnaBridge 156:ff21514d8981 29 * arising from your use of this Software.
AnnaBridge 156:ff21514d8981 30 *
AnnaBridge 156:ff21514d8981 31 ******************************************************************************/
AnnaBridge 156:ff21514d8981 32 #ifndef EM_CMU_H
AnnaBridge 156:ff21514d8981 33 #define EM_CMU_H
AnnaBridge 156:ff21514d8981 34
AnnaBridge 156:ff21514d8981 35 #include "em_device.h"
Anna Bridge 160:5571c4ff569f 36 #if defined(CMU_PRESENT)
AnnaBridge 156:ff21514d8981 37
AnnaBridge 156:ff21514d8981 38 #include <stdbool.h>
AnnaBridge 156:ff21514d8981 39 #include "em_assert.h"
AnnaBridge 156:ff21514d8981 40 #include "em_bus.h"
AnnaBridge 156:ff21514d8981 41
AnnaBridge 156:ff21514d8981 42 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 43 extern "C" {
AnnaBridge 156:ff21514d8981 44 #endif
AnnaBridge 156:ff21514d8981 45
AnnaBridge 156:ff21514d8981 46 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 47 * @addtogroup emlib
AnnaBridge 156:ff21514d8981 48 * @{
AnnaBridge 156:ff21514d8981 49 ******************************************************************************/
AnnaBridge 156:ff21514d8981 50
AnnaBridge 156:ff21514d8981 51 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 52 * @addtogroup CMU
AnnaBridge 156:ff21514d8981 53 * @{
AnnaBridge 156:ff21514d8981 54 ******************************************************************************/
AnnaBridge 156:ff21514d8981 55
AnnaBridge 156:ff21514d8981 56 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
AnnaBridge 156:ff21514d8981 57
AnnaBridge 156:ff21514d8981 58 /* Select register id's, for internal use. */
AnnaBridge 156:ff21514d8981 59 #define CMU_NOSEL_REG 0
AnnaBridge 156:ff21514d8981 60 #define CMU_HFCLKSEL_REG 1
AnnaBridge 156:ff21514d8981 61 #define CMU_LFACLKSEL_REG 2
AnnaBridge 156:ff21514d8981 62 #define CMU_LFBCLKSEL_REG 3
AnnaBridge 156:ff21514d8981 63 #define CMU_LFCCLKSEL_REG 4
AnnaBridge 156:ff21514d8981 64 #define CMU_LFECLKSEL_REG 5
AnnaBridge 156:ff21514d8981 65 #define CMU_DBGCLKSEL_REG 6
AnnaBridge 156:ff21514d8981 66 #define CMU_USBCCLKSEL_REG 7
Anna Bridge 160:5571c4ff569f 67 #define CMU_ADC0ASYNCSEL_REG 8
Anna Bridge 160:5571c4ff569f 68 #define CMU_ADC1ASYNCSEL_REG 9
Anna Bridge 160:5571c4ff569f 69 #define CMU_SDIOREFSEL_REG 10
Anna Bridge 160:5571c4ff569f 70 #define CMU_QSPI0REFSEL_REG 11
Anna Bridge 160:5571c4ff569f 71 #define CMU_USBRCLKSEL_REG 12
AnnaBridge 156:ff21514d8981 72
AnnaBridge 156:ff21514d8981 73 #define CMU_SEL_REG_POS 0
AnnaBridge 156:ff21514d8981 74 #define CMU_SEL_REG_MASK 0xf
AnnaBridge 156:ff21514d8981 75
AnnaBridge 156:ff21514d8981 76 /* Divisor/prescaler register id's, for internal use. */
AnnaBridge 156:ff21514d8981 77 #define CMU_NODIV_REG 0
AnnaBridge 156:ff21514d8981 78 #define CMU_NOPRESC_REG 0
AnnaBridge 156:ff21514d8981 79 #define CMU_HFPRESC_REG 1
AnnaBridge 156:ff21514d8981 80 #define CMU_HFCLKDIV_REG 1
AnnaBridge 156:ff21514d8981 81 #define CMU_HFEXPPRESC_REG 2
AnnaBridge 156:ff21514d8981 82 #define CMU_HFCLKLEPRESC_REG 3
AnnaBridge 156:ff21514d8981 83 #define CMU_HFPERPRESC_REG 4
AnnaBridge 156:ff21514d8981 84 #define CMU_HFPERCLKDIV_REG 4
AnnaBridge 156:ff21514d8981 85 #define CMU_HFCOREPRESC_REG 5
AnnaBridge 156:ff21514d8981 86 #define CMU_HFCORECLKDIV_REG 5
AnnaBridge 156:ff21514d8981 87 #define CMU_LFAPRESC0_REG 6
AnnaBridge 156:ff21514d8981 88 #define CMU_LFBPRESC0_REG 7
AnnaBridge 156:ff21514d8981 89 #define CMU_LFEPRESC0_REG 8
Anna Bridge 160:5571c4ff569f 90 #define CMU_ADCASYNCDIV_REG 9
AnnaBridge 156:ff21514d8981 91
AnnaBridge 156:ff21514d8981 92 #define CMU_PRESC_REG_POS 4
AnnaBridge 156:ff21514d8981 93 #define CMU_DIV_REG_POS CMU_PRESC_REG_POS
AnnaBridge 156:ff21514d8981 94 #define CMU_PRESC_REG_MASK 0xf
AnnaBridge 156:ff21514d8981 95 #define CMU_DIV_REG_MASK CMU_PRESC_REG_MASK
AnnaBridge 156:ff21514d8981 96
AnnaBridge 156:ff21514d8981 97 /* Enable register id's, for internal use. */
AnnaBridge 156:ff21514d8981 98 #define CMU_NO_EN_REG 0
AnnaBridge 156:ff21514d8981 99 #define CMU_CTRL_EN_REG 1
AnnaBridge 156:ff21514d8981 100 #define CMU_HFPERCLKDIV_EN_REG 1
AnnaBridge 156:ff21514d8981 101 #define CMU_HFPERCLKEN0_EN_REG 2
AnnaBridge 156:ff21514d8981 102 #define CMU_HFCORECLKEN0_EN_REG 3
AnnaBridge 156:ff21514d8981 103 #define CMU_HFBUSCLKEN0_EN_REG 5
AnnaBridge 156:ff21514d8981 104 #define CMU_LFACLKEN0_EN_REG 6
AnnaBridge 156:ff21514d8981 105 #define CMU_LFBCLKEN0_EN_REG 7
AnnaBridge 156:ff21514d8981 106 #define CMU_LFCCLKEN0_EN_REG 8
AnnaBridge 156:ff21514d8981 107 #define CMU_LFECLKEN0_EN_REG 9
AnnaBridge 156:ff21514d8981 108 #define CMU_PCNT_EN_REG 10
Anna Bridge 160:5571c4ff569f 109 #define CMU_SDIOREF_EN_REG 11
Anna Bridge 160:5571c4ff569f 110 #define CMU_QSPI0REF_EN_REG 12
Anna Bridge 160:5571c4ff569f 111 #define CMU_QSPI1REF_EN_REG 13
Anna Bridge 160:5571c4ff569f 112 #define CMU_HFPERCLKEN1_EN_REG 14
Anna Bridge 160:5571c4ff569f 113 #define CMU_USBRCLK_EN_REG 15
AnnaBridge 156:ff21514d8981 114
AnnaBridge 156:ff21514d8981 115 #define CMU_EN_REG_POS 8
AnnaBridge 156:ff21514d8981 116 #define CMU_EN_REG_MASK 0xf
AnnaBridge 156:ff21514d8981 117
AnnaBridge 156:ff21514d8981 118 /* Enable register bit positions, for internal use. */
AnnaBridge 156:ff21514d8981 119 #define CMU_EN_BIT_POS 12
AnnaBridge 156:ff21514d8981 120 #define CMU_EN_BIT_MASK 0x1f
AnnaBridge 156:ff21514d8981 121
AnnaBridge 156:ff21514d8981 122 /* Clock branch bitfield positions, for internal use. */
AnnaBridge 156:ff21514d8981 123 #define CMU_HF_CLK_BRANCH 0
AnnaBridge 156:ff21514d8981 124 #define CMU_HFCORE_CLK_BRANCH 1
AnnaBridge 156:ff21514d8981 125 #define CMU_HFPER_CLK_BRANCH 2
AnnaBridge 156:ff21514d8981 126 #define CMU_HFBUS_CLK_BRANCH 4
AnnaBridge 156:ff21514d8981 127 #define CMU_HFEXP_CLK_BRANCH 5
AnnaBridge 156:ff21514d8981 128 #define CMU_DBG_CLK_BRANCH 6
AnnaBridge 156:ff21514d8981 129 #define CMU_AUX_CLK_BRANCH 7
AnnaBridge 156:ff21514d8981 130 #define CMU_RTC_CLK_BRANCH 8
AnnaBridge 156:ff21514d8981 131 #define CMU_RTCC_CLK_BRANCH 9
AnnaBridge 156:ff21514d8981 132 #define CMU_LETIMER0_CLK_BRANCH 10
AnnaBridge 156:ff21514d8981 133 #define CMU_LEUART0_CLK_BRANCH 11
AnnaBridge 156:ff21514d8981 134 #define CMU_LEUART1_CLK_BRANCH 12
AnnaBridge 156:ff21514d8981 135 #define CMU_LFA_CLK_BRANCH 13
AnnaBridge 156:ff21514d8981 136 #define CMU_LFB_CLK_BRANCH 14
AnnaBridge 156:ff21514d8981 137 #define CMU_LFC_CLK_BRANCH 15
AnnaBridge 156:ff21514d8981 138 #define CMU_LFE_CLK_BRANCH 16
AnnaBridge 156:ff21514d8981 139 #define CMU_USBC_CLK_BRANCH 17
AnnaBridge 156:ff21514d8981 140 #define CMU_USBLE_CLK_BRANCH 18
AnnaBridge 156:ff21514d8981 141 #define CMU_LCDPRE_CLK_BRANCH 19
AnnaBridge 156:ff21514d8981 142 #define CMU_LCD_CLK_BRANCH 20
AnnaBridge 156:ff21514d8981 143 #define CMU_LESENSE_CLK_BRANCH 21
AnnaBridge 156:ff21514d8981 144 #define CMU_CSEN_LF_CLK_BRANCH 22
Anna Bridge 160:5571c4ff569f 145 #define CMU_ADC0ASYNC_CLK_BRANCH 23
Anna Bridge 160:5571c4ff569f 146 #define CMU_ADC1ASYNC_CLK_BRANCH 24
Anna Bridge 160:5571c4ff569f 147 #define CMU_SDIOREF_CLK_BRANCH 25
Anna Bridge 160:5571c4ff569f 148 #define CMU_QSPI0REF_CLK_BRANCH 26
Anna Bridge 160:5571c4ff569f 149 #define CMU_USBR_CLK_BRANCH 27
AnnaBridge 156:ff21514d8981 150
AnnaBridge 156:ff21514d8981 151 #define CMU_CLK_BRANCH_POS 17
AnnaBridge 156:ff21514d8981 152 #define CMU_CLK_BRANCH_MASK 0x1f
AnnaBridge 156:ff21514d8981 153
Anna Bridge 160:5571c4ff569f 154 #if defined(_EMU_CMD_EM01VSCALE0_MASK)
AnnaBridge 156:ff21514d8981 155 /* Max clock frequency for VSCALE voltages */
AnnaBridge 156:ff21514d8981 156 #define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 20000000
AnnaBridge 156:ff21514d8981 157 #endif
Anna Bridge 160:5571c4ff569f 158
Anna Bridge 160:5571c4ff569f 159 #if defined(USB_PRESENT) && defined(_CMU_HFCORECLKEN0_USBC_MASK)
Anna Bridge 160:5571c4ff569f 160 #define USBC_CLOCK_PRESENT
Anna Bridge 160:5571c4ff569f 161 #endif
Anna Bridge 160:5571c4ff569f 162 #if defined(USB_PRESENT) && defined(_CMU_USBCTRL_MASK)
Anna Bridge 160:5571c4ff569f 163 #define USBR_CLOCK_PRESENT
Anna Bridge 160:5571c4ff569f 164 #endif
Anna Bridge 160:5571c4ff569f 165
AnnaBridge 156:ff21514d8981 166 /** @endcond */
AnnaBridge 156:ff21514d8981 167
AnnaBridge 156:ff21514d8981 168 /*******************************************************************************
AnnaBridge 156:ff21514d8981 169 ******************************** ENUMS ************************************
AnnaBridge 156:ff21514d8981 170 ******************************************************************************/
AnnaBridge 156:ff21514d8981 171
AnnaBridge 156:ff21514d8981 172 /** Clock divisors. These values are valid for prescalers. */
AnnaBridge 156:ff21514d8981 173 #define cmuClkDiv_1 1 /**< Divide clock by 1. */
AnnaBridge 156:ff21514d8981 174 #define cmuClkDiv_2 2 /**< Divide clock by 2. */
AnnaBridge 156:ff21514d8981 175 #define cmuClkDiv_4 4 /**< Divide clock by 4. */
AnnaBridge 156:ff21514d8981 176 #define cmuClkDiv_8 8 /**< Divide clock by 8. */
AnnaBridge 156:ff21514d8981 177 #define cmuClkDiv_16 16 /**< Divide clock by 16. */
AnnaBridge 156:ff21514d8981 178 #define cmuClkDiv_32 32 /**< Divide clock by 32. */
AnnaBridge 156:ff21514d8981 179 #define cmuClkDiv_64 64 /**< Divide clock by 64. */
AnnaBridge 156:ff21514d8981 180 #define cmuClkDiv_128 128 /**< Divide clock by 128. */
AnnaBridge 156:ff21514d8981 181 #define cmuClkDiv_256 256 /**< Divide clock by 256. */
AnnaBridge 156:ff21514d8981 182 #define cmuClkDiv_512 512 /**< Divide clock by 512. */
AnnaBridge 156:ff21514d8981 183 #define cmuClkDiv_1024 1024 /**< Divide clock by 1024. */
AnnaBridge 156:ff21514d8981 184 #define cmuClkDiv_2048 2048 /**< Divide clock by 2048. */
AnnaBridge 156:ff21514d8981 185 #define cmuClkDiv_4096 4096 /**< Divide clock by 4096. */
AnnaBridge 156:ff21514d8981 186 #define cmuClkDiv_8192 8192 /**< Divide clock by 8192. */
AnnaBridge 156:ff21514d8981 187 #define cmuClkDiv_16384 16384 /**< Divide clock by 16384. */
AnnaBridge 156:ff21514d8981 188 #define cmuClkDiv_32768 32768 /**< Divide clock by 32768. */
AnnaBridge 156:ff21514d8981 189
AnnaBridge 156:ff21514d8981 190 /** Clock divider configuration */
AnnaBridge 156:ff21514d8981 191 typedef uint32_t CMU_ClkDiv_TypeDef;
AnnaBridge 156:ff21514d8981 192
Anna Bridge 160:5571c4ff569f 193 #if defined(_SILICON_LABS_32B_SERIES_1)
AnnaBridge 156:ff21514d8981 194 /** Clockprescaler configuration */
AnnaBridge 156:ff21514d8981 195 typedef uint32_t CMU_ClkPresc_TypeDef;
AnnaBridge 156:ff21514d8981 196 #endif
AnnaBridge 156:ff21514d8981 197
Anna Bridge 160:5571c4ff569f 198 #if defined(_CMU_HFRCOCTRL_BAND_MASK)
AnnaBridge 156:ff21514d8981 199 /** High frequency system RCO bands */
Anna Bridge 160:5571c4ff569f 200 typedef enum {
AnnaBridge 156:ff21514d8981 201 cmuHFRCOBand_1MHz = _CMU_HFRCOCTRL_BAND_1MHZ, /**< 1MHz HFRCO band */
AnnaBridge 156:ff21514d8981 202 cmuHFRCOBand_7MHz = _CMU_HFRCOCTRL_BAND_7MHZ, /**< 7MHz HFRCO band */
AnnaBridge 156:ff21514d8981 203 cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ, /**< 11MHz HFRCO band */
AnnaBridge 156:ff21514d8981 204 cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ, /**< 14MHz HFRCO band */
AnnaBridge 156:ff21514d8981 205 cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ, /**< 21MHz HFRCO band */
Anna Bridge 160:5571c4ff569f 206 #if defined(CMU_HFRCOCTRL_BAND_28MHZ)
AnnaBridge 156:ff21514d8981 207 cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ, /**< 28MHz HFRCO band */
AnnaBridge 156:ff21514d8981 208 #endif
AnnaBridge 156:ff21514d8981 209 } CMU_HFRCOBand_TypeDef;
AnnaBridge 156:ff21514d8981 210 #endif /* _CMU_HFRCOCTRL_BAND_MASK */
AnnaBridge 156:ff21514d8981 211
Anna Bridge 160:5571c4ff569f 212 #if defined(_CMU_AUXHFRCOCTRL_BAND_MASK)
AnnaBridge 156:ff21514d8981 213 /** AUX High frequency RCO bands */
Anna Bridge 160:5571c4ff569f 214 typedef enum {
AnnaBridge 156:ff21514d8981 215 cmuAUXHFRCOBand_1MHz = _CMU_AUXHFRCOCTRL_BAND_1MHZ, /**< 1MHz RC band */
AnnaBridge 156:ff21514d8981 216 cmuAUXHFRCOBand_7MHz = _CMU_AUXHFRCOCTRL_BAND_7MHZ, /**< 7MHz RC band */
AnnaBridge 156:ff21514d8981 217 cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ, /**< 11MHz RC band */
AnnaBridge 156:ff21514d8981 218 cmuAUXHFRCOBand_14MHz = _CMU_AUXHFRCOCTRL_BAND_14MHZ, /**< 14MHz RC band */
AnnaBridge 156:ff21514d8981 219 cmuAUXHFRCOBand_21MHz = _CMU_AUXHFRCOCTRL_BAND_21MHZ, /**< 21MHz RC band */
Anna Bridge 160:5571c4ff569f 220 #if defined(CMU_AUXHFRCOCTRL_BAND_28MHZ)
AnnaBridge 156:ff21514d8981 221 cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ, /**< 28MHz RC band */
AnnaBridge 156:ff21514d8981 222 #endif
AnnaBridge 156:ff21514d8981 223 } CMU_AUXHFRCOBand_TypeDef;
AnnaBridge 156:ff21514d8981 224 #endif
AnnaBridge 156:ff21514d8981 225
Anna Bridge 160:5571c4ff569f 226 #if defined(_CMU_USHFRCOCONF_BAND_MASK)
AnnaBridge 156:ff21514d8981 227 /** USB High frequency RC bands. */
Anna Bridge 160:5571c4ff569f 228 typedef enum {
AnnaBridge 156:ff21514d8981 229 /** 24MHz RC band. */
AnnaBridge 156:ff21514d8981 230 cmuUSHFRCOBand_24MHz = _CMU_USHFRCOCONF_BAND_24MHZ,
AnnaBridge 156:ff21514d8981 231 /** 48MHz RC band. */
AnnaBridge 156:ff21514d8981 232 cmuUSHFRCOBand_48MHz = _CMU_USHFRCOCONF_BAND_48MHZ,
AnnaBridge 156:ff21514d8981 233 } CMU_USHFRCOBand_TypeDef;
AnnaBridge 156:ff21514d8981 234 #endif
AnnaBridge 156:ff21514d8981 235
Anna Bridge 160:5571c4ff569f 236 #if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK)
Anna Bridge 160:5571c4ff569f 237 /** High USHFRCO bands */
Anna Bridge 160:5571c4ff569f 238 typedef enum {
Anna Bridge 160:5571c4ff569f 239 cmuUSHFRCOFreq_16M0Hz = 16000000U, /**< 16MHz RC band */
Anna Bridge 160:5571c4ff569f 240 cmuUSHFRCOFreq_32M0Hz = 32000000U, /**< 32MHz RC band */
Anna Bridge 160:5571c4ff569f 241 cmuUSHFRCOFreq_48M0Hz = 48000000U, /**< 48MHz RC band */
Anna Bridge 160:5571c4ff569f 242 cmuUSHFRCOFreq_50M0Hz = 50000000U, /**< 50MHz RC band */
Anna Bridge 160:5571c4ff569f 243 cmuUSHFRCOFreq_UserDefined = 0,
Anna Bridge 160:5571c4ff569f 244 } CMU_USHFRCOFreq_TypeDef;
Anna Bridge 160:5571c4ff569f 245 #define CMU_USHFRCO_MIN cmuUSHFRCOFreq_16M0Hz
Anna Bridge 160:5571c4ff569f 246 #define CMU_USHFRCO_MAX cmuUSHFRCOFreq_50M0Hz
Anna Bridge 160:5571c4ff569f 247 #endif
Anna Bridge 160:5571c4ff569f 248
Anna Bridge 160:5571c4ff569f 249 #if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK)
AnnaBridge 156:ff21514d8981 250 /** High frequency system RCO bands */
Anna Bridge 160:5571c4ff569f 251 typedef enum {
AnnaBridge 156:ff21514d8981 252 cmuHFRCOFreq_1M0Hz = 1000000U, /**< 1MHz RC band */
AnnaBridge 156:ff21514d8981 253 cmuHFRCOFreq_2M0Hz = 2000000U, /**< 2MHz RC band */
AnnaBridge 156:ff21514d8981 254 cmuHFRCOFreq_4M0Hz = 4000000U, /**< 4MHz RC band */
AnnaBridge 156:ff21514d8981 255 cmuHFRCOFreq_7M0Hz = 7000000U, /**< 7MHz RC band */
AnnaBridge 156:ff21514d8981 256 cmuHFRCOFreq_13M0Hz = 13000000U, /**< 13MHz RC band */
AnnaBridge 156:ff21514d8981 257 cmuHFRCOFreq_16M0Hz = 16000000U, /**< 16MHz RC band */
AnnaBridge 156:ff21514d8981 258 cmuHFRCOFreq_19M0Hz = 19000000U, /**< 19MHz RC band */
AnnaBridge 156:ff21514d8981 259 cmuHFRCOFreq_26M0Hz = 26000000U, /**< 26MHz RC band */
AnnaBridge 156:ff21514d8981 260 cmuHFRCOFreq_32M0Hz = 32000000U, /**< 32MHz RC band */
AnnaBridge 156:ff21514d8981 261 cmuHFRCOFreq_38M0Hz = 38000000U, /**< 38MHz RC band */
Anna Bridge 160:5571c4ff569f 262 #if defined(_DEVINFO_HFRCOCAL13_MASK)
Anna Bridge 160:5571c4ff569f 263 cmuHFRCOFreq_48M0Hz = 48000000U, /**< 48MHz RC band */
Anna Bridge 160:5571c4ff569f 264 #endif
Anna Bridge 160:5571c4ff569f 265 #if defined(_DEVINFO_HFRCOCAL14_MASK)
Anna Bridge 160:5571c4ff569f 266 cmuHFRCOFreq_56M0Hz = 56000000U, /**< 56MHz RC band */
Anna Bridge 160:5571c4ff569f 267 #endif
Anna Bridge 160:5571c4ff569f 268 #if defined(_DEVINFO_HFRCOCAL15_MASK)
Anna Bridge 160:5571c4ff569f 269 cmuHFRCOFreq_64M0Hz = 64000000U, /**< 64MHz RC band */
Anna Bridge 160:5571c4ff569f 270 #endif
Anna Bridge 160:5571c4ff569f 271 #if defined(_DEVINFO_HFRCOCAL16_MASK)
Anna Bridge 160:5571c4ff569f 272 cmuHFRCOFreq_72M0Hz = 72000000U, /**< 72MHz RC band */
Anna Bridge 160:5571c4ff569f 273 #endif
AnnaBridge 156:ff21514d8981 274 cmuHFRCOFreq_UserDefined = 0,
AnnaBridge 156:ff21514d8981 275 } CMU_HFRCOFreq_TypeDef;
AnnaBridge 156:ff21514d8981 276 #define CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz
Anna Bridge 160:5571c4ff569f 277 #if defined(_DEVINFO_HFRCOCAL16_MASK)
Anna Bridge 160:5571c4ff569f 278 #define CMU_HFRCO_MAX cmuHFRCOFreq_72M0Hz
Anna Bridge 160:5571c4ff569f 279 #elif defined(_DEVINFO_HFRCOCAL15_MASK)
Anna Bridge 160:5571c4ff569f 280 #define CMU_HFRCO_MAX cmuHFRCOFreq_64M0Hz
Anna Bridge 160:5571c4ff569f 281 #elif defined(_DEVINFO_HFRCOCAL14_MASK)
Anna Bridge 160:5571c4ff569f 282 #define CMU_HFRCO_MAX cmuHFRCOFreq_56M0Hz
Anna Bridge 160:5571c4ff569f 283 #elif defined(_DEVINFO_HFRCOCAL13_MASK)
Anna Bridge 160:5571c4ff569f 284 #define CMU_HFRCO_MAX cmuHFRCOFreq_48M0Hz
Anna Bridge 160:5571c4ff569f 285 #else
AnnaBridge 156:ff21514d8981 286 #define CMU_HFRCO_MAX cmuHFRCOFreq_38M0Hz
AnnaBridge 156:ff21514d8981 287 #endif
Anna Bridge 160:5571c4ff569f 288 #endif
AnnaBridge 156:ff21514d8981 289
Anna Bridge 160:5571c4ff569f 290 #if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK)
AnnaBridge 156:ff21514d8981 291 /** AUX High frequency RCO bands */
Anna Bridge 160:5571c4ff569f 292 typedef enum {
AnnaBridge 156:ff21514d8981 293 cmuAUXHFRCOFreq_1M0Hz = 1000000U, /**< 1MHz RC band */
AnnaBridge 156:ff21514d8981 294 cmuAUXHFRCOFreq_2M0Hz = 2000000U, /**< 2MHz RC band */
AnnaBridge 156:ff21514d8981 295 cmuAUXHFRCOFreq_4M0Hz = 4000000U, /**< 4MHz RC band */
AnnaBridge 156:ff21514d8981 296 cmuAUXHFRCOFreq_7M0Hz = 7000000U, /**< 7MHz RC band */
AnnaBridge 156:ff21514d8981 297 cmuAUXHFRCOFreq_13M0Hz = 13000000U, /**< 13MHz RC band */
AnnaBridge 156:ff21514d8981 298 cmuAUXHFRCOFreq_16M0Hz = 16000000U, /**< 16MHz RC band */
AnnaBridge 156:ff21514d8981 299 cmuAUXHFRCOFreq_19M0Hz = 19000000U, /**< 19MHz RC band */
AnnaBridge 156:ff21514d8981 300 cmuAUXHFRCOFreq_26M0Hz = 26000000U, /**< 26MHz RC band */
AnnaBridge 156:ff21514d8981 301 cmuAUXHFRCOFreq_32M0Hz = 32000000U, /**< 32MHz RC band */
AnnaBridge 156:ff21514d8981 302 cmuAUXHFRCOFreq_38M0Hz = 38000000U, /**< 38MHz RC band */
Anna Bridge 160:5571c4ff569f 303 #if defined(_DEVINFO_AUXHFRCOCAL14_MASK)
Anna Bridge 160:5571c4ff569f 304 cmuAUXHFRCOFreq_48M0Hz = 48000000U, /**< 48MHz RC band */
Anna Bridge 160:5571c4ff569f 305 cmuAUXHFRCOFreq_50M0Hz = 50000000U, /**< 50MHz RC band */
Anna Bridge 160:5571c4ff569f 306 #endif
AnnaBridge 156:ff21514d8981 307 cmuAUXHFRCOFreq_UserDefined = 0,
AnnaBridge 156:ff21514d8981 308 } CMU_AUXHFRCOFreq_TypeDef;
AnnaBridge 156:ff21514d8981 309 #define CMU_AUXHFRCO_MIN cmuAUXHFRCOFreq_1M0Hz
Anna Bridge 160:5571c4ff569f 310 #if defined(_DEVINFO_AUXHFRCOCAL14_MASK)
Anna Bridge 160:5571c4ff569f 311 #define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_50M0Hz
Anna Bridge 160:5571c4ff569f 312 #else
AnnaBridge 156:ff21514d8981 313 #define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_38M0Hz
AnnaBridge 156:ff21514d8981 314 #endif
Anna Bridge 160:5571c4ff569f 315 #endif
AnnaBridge 156:ff21514d8981 316
AnnaBridge 156:ff21514d8981 317 /** Clock points in CMU. Please refer to CMU overview in reference manual. */
Anna Bridge 160:5571c4ff569f 318 typedef enum {
AnnaBridge 156:ff21514d8981 319 /*******************/
AnnaBridge 156:ff21514d8981 320 /* HF clock branch */
AnnaBridge 156:ff21514d8981 321 /*******************/
AnnaBridge 156:ff21514d8981 322
AnnaBridge 156:ff21514d8981 323 /** High frequency clock */
Anna Bridge 160:5571c4ff569f 324 #if defined(_CMU_CTRL_HFCLKDIV_MASK) \
Anna Bridge 160:5571c4ff569f 325 || defined(_CMU_HFPRESC_MASK)
AnnaBridge 156:ff21514d8981 326 cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 327 | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 328 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 329 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 330 | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 331 #else
AnnaBridge 156:ff21514d8981 332 cmuClock_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 333 | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 334 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 335 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 336 | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 337 #endif
AnnaBridge 156:ff21514d8981 338
AnnaBridge 156:ff21514d8981 339 /** Debug clock */
AnnaBridge 156:ff21514d8981 340 cmuClock_DBG = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 341 | (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 342 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 343 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 344 | (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 345
AnnaBridge 156:ff21514d8981 346 /** AUX clock */
AnnaBridge 156:ff21514d8981 347 cmuClock_AUX = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 348 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 349 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 350 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 351 | (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 352
Anna Bridge 160:5571c4ff569f 353 #if defined(_CMU_HFEXPPRESC_MASK)
AnnaBridge 156:ff21514d8981 354 /**********************/
AnnaBridge 156:ff21514d8981 355 /* HF export sub-branch */
AnnaBridge 156:ff21514d8981 356 /**********************/
AnnaBridge 156:ff21514d8981 357
AnnaBridge 156:ff21514d8981 358 /** Export clock */
AnnaBridge 156:ff21514d8981 359 cmuClock_EXPORT = (CMU_HFEXPPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 360 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 361 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 362 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 363 | (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 364 #endif
AnnaBridge 156:ff21514d8981 365
Anna Bridge 160:5571c4ff569f 366 #if defined(_CMU_HFBUSCLKEN0_MASK)
AnnaBridge 156:ff21514d8981 367 /**********************************/
Anna Bridge 160:5571c4ff569f 368 /* HF bus clock sub-branch */
Anna Bridge 160:5571c4ff569f 369 /**********************************/
AnnaBridge 156:ff21514d8981 370
AnnaBridge 156:ff21514d8981 371 /** High frequency bus clock. */
AnnaBridge 156:ff21514d8981 372 cmuClock_BUS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 373 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 374 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 375 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 376 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 377
Anna Bridge 160:5571c4ff569f 378 #if defined(CMU_HFBUSCLKEN0_CRYPTO)
AnnaBridge 156:ff21514d8981 379 /** Cryptography accelerator clock. */
AnnaBridge 156:ff21514d8981 380 cmuClock_CRYPTO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 381 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 382 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 383 | (_CMU_HFBUSCLKEN0_CRYPTO_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 384 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 385 #endif
AnnaBridge 156:ff21514d8981 386
Anna Bridge 160:5571c4ff569f 387 #if defined(CMU_HFBUSCLKEN0_CRYPTO0)
AnnaBridge 156:ff21514d8981 388 /** Cryptography accelerator 0 clock. */
AnnaBridge 156:ff21514d8981 389 cmuClock_CRYPTO0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 390 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 391 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 392 | (_CMU_HFBUSCLKEN0_CRYPTO0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 393 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 394 #endif
AnnaBridge 156:ff21514d8981 395
Anna Bridge 160:5571c4ff569f 396 #if defined(CMU_HFBUSCLKEN0_CRYPTO1)
AnnaBridge 156:ff21514d8981 397 /** Cryptography accelerator 1 clock. */
AnnaBridge 156:ff21514d8981 398 cmuClock_CRYPTO1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 399 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 400 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 401 | (_CMU_HFBUSCLKEN0_CRYPTO1_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 402 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 403 #endif
AnnaBridge 156:ff21514d8981 404
Anna Bridge 160:5571c4ff569f 405 #if defined(CMU_HFBUSCLKEN0_LDMA)
AnnaBridge 156:ff21514d8981 406 /** Direct memory access controller clock. */
AnnaBridge 156:ff21514d8981 407 cmuClock_LDMA = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 408 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 409 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 410 | (_CMU_HFBUSCLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 411 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 412 #endif
AnnaBridge 156:ff21514d8981 413
Anna Bridge 160:5571c4ff569f 414 #if defined(CMU_HFBUSCLKEN0_QSPI0)
Anna Bridge 160:5571c4ff569f 415 /** Quad SPI clock. */
Anna Bridge 160:5571c4ff569f 416 cmuClock_QSPI0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
Anna Bridge 160:5571c4ff569f 417 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 418 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 419 | (_CMU_HFBUSCLKEN0_QSPI0_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 420 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 421 #endif
Anna Bridge 160:5571c4ff569f 422
Anna Bridge 160:5571c4ff569f 423 #if defined(CMU_HFBUSCLKEN0_GPCRC)
AnnaBridge 156:ff21514d8981 424 /** General purpose cyclic redundancy checksum clock. */
AnnaBridge 156:ff21514d8981 425 cmuClock_GPCRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 426 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 427 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 428 | (_CMU_HFBUSCLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 429 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 430 #endif
AnnaBridge 156:ff21514d8981 431
Anna Bridge 160:5571c4ff569f 432 #if defined(CMU_HFBUSCLKEN0_GPIO)
AnnaBridge 156:ff21514d8981 433 /** General purpose input/output clock. */
AnnaBridge 156:ff21514d8981 434 cmuClock_GPIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 435 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 436 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 437 | (_CMU_HFBUSCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 438 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 439 #endif
AnnaBridge 156:ff21514d8981 440
AnnaBridge 156:ff21514d8981 441 /** Low energy clock divided down from HFBUSCLK. */
AnnaBridge 156:ff21514d8981 442 cmuClock_HFLE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 443 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 444 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 445 | (_CMU_HFBUSCLKEN0_LE_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 446 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 447
Anna Bridge 160:5571c4ff569f 448 #if defined(CMU_HFBUSCLKEN0_PRS)
AnnaBridge 156:ff21514d8981 449 /** Peripheral reflex system clock. */
AnnaBridge 156:ff21514d8981 450 cmuClock_PRS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 451 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 452 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 453 | (_CMU_HFBUSCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 454 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 455 #endif
AnnaBridge 156:ff21514d8981 456 #endif
AnnaBridge 156:ff21514d8981 457
AnnaBridge 156:ff21514d8981 458 /**********************************/
AnnaBridge 156:ff21514d8981 459 /* HF peripheral clock sub-branch */
AnnaBridge 156:ff21514d8981 460 /**********************************/
AnnaBridge 156:ff21514d8981 461
AnnaBridge 156:ff21514d8981 462 /** High frequency peripheral clock */
Anna Bridge 160:5571c4ff569f 463 #if defined(_CMU_HFPRESC_MASK)
AnnaBridge 156:ff21514d8981 464 cmuClock_HFPER = (CMU_HFPERPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 465 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 466 | (CMU_CTRL_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 467 | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 468 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 469 #else
AnnaBridge 156:ff21514d8981 470 cmuClock_HFPER = (CMU_HFPERCLKDIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 471 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 472 | (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 473 | (_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 474 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 475 #endif
AnnaBridge 156:ff21514d8981 476
Anna Bridge 160:5571c4ff569f 477 #if defined(CMU_HFPERCLKEN0_USART0)
AnnaBridge 156:ff21514d8981 478 /** Universal sync/async receiver/transmitter 0 clock. */
AnnaBridge 156:ff21514d8981 479 cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 480 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 481 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 482 | (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 483 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 484 #endif
AnnaBridge 156:ff21514d8981 485
Anna Bridge 160:5571c4ff569f 486 #if defined(CMU_HFPERCLKEN0_USARTRF0)
AnnaBridge 156:ff21514d8981 487 /** Universal sync/async receiver/transmitter 0 clock. */
AnnaBridge 156:ff21514d8981 488 cmuClock_USARTRF0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 489 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 490 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 491 | (_CMU_HFPERCLKEN0_USARTRF0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 492 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 493 #endif
AnnaBridge 156:ff21514d8981 494
Anna Bridge 160:5571c4ff569f 495 #if defined(CMU_HFPERCLKEN0_USARTRF1)
AnnaBridge 156:ff21514d8981 496 /** Universal sync/async receiver/transmitter 0 clock. */
AnnaBridge 156:ff21514d8981 497 cmuClock_USARTRF1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 498 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 499 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 500 | (_CMU_HFPERCLKEN0_USARTRF1_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 501 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 502 #endif
AnnaBridge 156:ff21514d8981 503
Anna Bridge 160:5571c4ff569f 504 #if defined(CMU_HFPERCLKEN0_USART1)
AnnaBridge 156:ff21514d8981 505 /** Universal sync/async receiver/transmitter 1 clock. */
AnnaBridge 156:ff21514d8981 506 cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 507 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 508 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 509 | (_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 510 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 511 #endif
AnnaBridge 156:ff21514d8981 512
Anna Bridge 160:5571c4ff569f 513 #if defined(CMU_HFPERCLKEN0_USART2)
AnnaBridge 156:ff21514d8981 514 /** Universal sync/async receiver/transmitter 2 clock. */
AnnaBridge 156:ff21514d8981 515 cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 516 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 517 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 518 | (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 519 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 520 #endif
AnnaBridge 156:ff21514d8981 521
Anna Bridge 160:5571c4ff569f 522 #if defined(CMU_HFPERCLKEN0_USART3)
AnnaBridge 156:ff21514d8981 523 /** Universal sync/async receiver/transmitter 3 clock. */
AnnaBridge 156:ff21514d8981 524 cmuClock_USART3 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 525 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 526 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 527 | (_CMU_HFPERCLKEN0_USART3_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 528 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 529 #endif
AnnaBridge 156:ff21514d8981 530
Anna Bridge 160:5571c4ff569f 531 #if defined(CMU_HFPERCLKEN0_USART4)
AnnaBridge 156:ff21514d8981 532 /** Universal sync/async receiver/transmitter 4 clock. */
AnnaBridge 156:ff21514d8981 533 cmuClock_USART4 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 534 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 535 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 536 | (_CMU_HFPERCLKEN0_USART4_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 537 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 538 #endif
AnnaBridge 156:ff21514d8981 539
Anna Bridge 160:5571c4ff569f 540 #if defined(CMU_HFPERCLKEN0_USART5)
AnnaBridge 156:ff21514d8981 541 /** Universal sync/async receiver/transmitter 5 clock. */
AnnaBridge 156:ff21514d8981 542 cmuClock_USART5 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 543 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 544 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 545 | (_CMU_HFPERCLKEN0_USART5_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 546 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 547 #endif
AnnaBridge 156:ff21514d8981 548
Anna Bridge 160:5571c4ff569f 549 #if defined(CMU_HFPERCLKEN0_UART0)
AnnaBridge 156:ff21514d8981 550 /** Universal async receiver/transmitter 0 clock. */
AnnaBridge 156:ff21514d8981 551 cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 552 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 553 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 554 | (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 555 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 556 #elif defined(_CMU_HFPERCLKEN1_UART0_MASK)
Anna Bridge 160:5571c4ff569f 557 /** Universal async receiver/transmitter 0 clock. */
Anna Bridge 160:5571c4ff569f 558 cmuClock_UART0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
Anna Bridge 160:5571c4ff569f 559 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 560 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 561 | (_CMU_HFPERCLKEN1_UART0_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 562 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 563 #endif
AnnaBridge 156:ff21514d8981 564
Anna Bridge 160:5571c4ff569f 565 #if defined(CMU_HFPERCLKEN0_UART1)
AnnaBridge 156:ff21514d8981 566 /** Universal async receiver/transmitter 1 clock. */
AnnaBridge 156:ff21514d8981 567 cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 568 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 569 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 570 | (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 571 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 572 #elif defined(_CMU_HFPERCLKEN1_UART1_MASK)
Anna Bridge 160:5571c4ff569f 573 /** Universal async receiver/transmitter 1 clock. */
Anna Bridge 160:5571c4ff569f 574 cmuClock_UART1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
Anna Bridge 160:5571c4ff569f 575 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 576 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 577 | (_CMU_HFPERCLKEN1_UART1_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 578 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 579 #endif
AnnaBridge 156:ff21514d8981 580
Anna Bridge 160:5571c4ff569f 581 #if defined(CMU_HFPERCLKEN0_TIMER0)
AnnaBridge 156:ff21514d8981 582 /** Timer 0 clock. */
AnnaBridge 156:ff21514d8981 583 cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 584 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 585 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 586 | (_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 587 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 588 #endif
AnnaBridge 156:ff21514d8981 589
Anna Bridge 160:5571c4ff569f 590 #if defined(CMU_HFPERCLKEN0_TIMER1)
AnnaBridge 156:ff21514d8981 591 /** Timer 1 clock. */
AnnaBridge 156:ff21514d8981 592 cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 593 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 594 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 595 | (_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 596 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 597 #endif
AnnaBridge 156:ff21514d8981 598
Anna Bridge 160:5571c4ff569f 599 #if defined(CMU_HFPERCLKEN0_TIMER2)
AnnaBridge 156:ff21514d8981 600 /** Timer 2 clock. */
AnnaBridge 156:ff21514d8981 601 cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 602 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 603 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 604 | (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 605 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 606 #endif
AnnaBridge 156:ff21514d8981 607
Anna Bridge 160:5571c4ff569f 608 #if defined(CMU_HFPERCLKEN0_TIMER3)
AnnaBridge 156:ff21514d8981 609 /** Timer 3 clock. */
AnnaBridge 156:ff21514d8981 610 cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 611 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 612 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 613 | (_CMU_HFPERCLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 614 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 615 #endif
AnnaBridge 156:ff21514d8981 616
Anna Bridge 160:5571c4ff569f 617 #if defined(CMU_HFPERCLKEN0_TIMER4)
Anna Bridge 160:5571c4ff569f 618 /** Timer 4 clock. */
Anna Bridge 160:5571c4ff569f 619 cmuClock_TIMER4 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 620 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 621 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 622 | (_CMU_HFPERCLKEN0_TIMER4_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 623 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 624 #endif
Anna Bridge 160:5571c4ff569f 625
Anna Bridge 160:5571c4ff569f 626 #if defined(CMU_HFPERCLKEN0_TIMER5)
Anna Bridge 160:5571c4ff569f 627 /** Timer 5 clock. */
Anna Bridge 160:5571c4ff569f 628 cmuClock_TIMER5 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 629 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 630 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 631 | (_CMU_HFPERCLKEN0_TIMER5_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 632 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 633 #endif
Anna Bridge 160:5571c4ff569f 634
Anna Bridge 160:5571c4ff569f 635 #if defined(CMU_HFPERCLKEN0_TIMER6)
Anna Bridge 160:5571c4ff569f 636 /** Timer 6 clock. */
Anna Bridge 160:5571c4ff569f 637 cmuClock_TIMER6 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 638 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 639 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 640 | (_CMU_HFPERCLKEN0_TIMER6_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 641 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 642 #endif
AnnaBridge 156:ff21514d8981 643
Anna Bridge 160:5571c4ff569f 644 #if defined(CMU_HFPERCLKEN0_WTIMER0)
Anna Bridge 160:5571c4ff569f 645 /** Wide Timer 0 clock. */
Anna Bridge 160:5571c4ff569f 646 cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 647 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 648 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 649 | (_CMU_HFPERCLKEN0_WTIMER0_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 650 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 651 #elif defined(CMU_HFPERCLKEN1_WTIMER0)
Anna Bridge 160:5571c4ff569f 652 /** Wide Timer 0 clock. */
Anna Bridge 160:5571c4ff569f 653 cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 654 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 655 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 656 | (_CMU_HFPERCLKEN1_WTIMER0_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 657 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 658 #endif
Anna Bridge 160:5571c4ff569f 659
Anna Bridge 160:5571c4ff569f 660 #if defined(CMU_HFPERCLKEN0_WTIMER1)
Anna Bridge 160:5571c4ff569f 661 /** Wide Timer 1 clock. */
Anna Bridge 160:5571c4ff569f 662 cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 663 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 664 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 665 | (_CMU_HFPERCLKEN0_WTIMER1_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 666 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 667 #elif defined(CMU_HFPERCLKEN1_WTIMER1)
AnnaBridge 156:ff21514d8981 668 /** Wide Timer 1 clock. */
AnnaBridge 156:ff21514d8981 669 cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 670 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 671 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 672 | (_CMU_HFPERCLKEN1_WTIMER1_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 673 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 674 #endif
AnnaBridge 156:ff21514d8981 675
Anna Bridge 160:5571c4ff569f 676 #if defined(CMU_HFPERCLKEN1_WTIMER2)
Anna Bridge 160:5571c4ff569f 677 /** Wide Timer 2 clock. */
Anna Bridge 160:5571c4ff569f 678 cmuClock_WTIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 679 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 680 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 681 | (_CMU_HFPERCLKEN1_WTIMER2_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 682 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 683 #endif
Anna Bridge 160:5571c4ff569f 684
Anna Bridge 160:5571c4ff569f 685 #if defined(CMU_HFPERCLKEN1_WTIMER3)
Anna Bridge 160:5571c4ff569f 686 /** Wide Timer 3 clock. */
Anna Bridge 160:5571c4ff569f 687 cmuClock_WTIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 688 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 689 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 690 | (_CMU_HFPERCLKEN1_WTIMER3_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 691 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 692 #endif
Anna Bridge 160:5571c4ff569f 693
Anna Bridge 160:5571c4ff569f 694 #if defined(CMU_HFPERCLKEN0_CRYOTIMER)
AnnaBridge 156:ff21514d8981 695 /** CRYOtimer clock. */
AnnaBridge 156:ff21514d8981 696 cmuClock_CRYOTIMER = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 697 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 698 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 699 | (_CMU_HFPERCLKEN0_CRYOTIMER_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 700 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 701 #endif
AnnaBridge 156:ff21514d8981 702
Anna Bridge 160:5571c4ff569f 703 #if defined(CMU_HFPERCLKEN0_ACMP0)
AnnaBridge 156:ff21514d8981 704 /** Analog comparator 0 clock. */
AnnaBridge 156:ff21514d8981 705 cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 706 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 707 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 708 | (_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 709 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 710 #endif
AnnaBridge 156:ff21514d8981 711
Anna Bridge 160:5571c4ff569f 712 #if defined(CMU_HFPERCLKEN0_ACMP1)
AnnaBridge 156:ff21514d8981 713 /** Analog comparator 1 clock. */
AnnaBridge 156:ff21514d8981 714 cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 715 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 716 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 717 | (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 718 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 719 #endif
AnnaBridge 156:ff21514d8981 720
Anna Bridge 160:5571c4ff569f 721 #if defined(CMU_HFPERCLKEN0_ACMP2)
Anna Bridge 160:5571c4ff569f 722 /** Analog comparator 2 clock. */
Anna Bridge 160:5571c4ff569f 723 cmuClock_ACMP2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 724 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 725 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 726 | (_CMU_HFPERCLKEN0_ACMP2_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 727 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 728 #endif
Anna Bridge 160:5571c4ff569f 729
Anna Bridge 160:5571c4ff569f 730 #if defined(CMU_HFPERCLKEN0_ACMP3)
Anna Bridge 160:5571c4ff569f 731 /** Analog comparator 3 clock. */
Anna Bridge 160:5571c4ff569f 732 cmuClock_ACMP3 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 733 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 734 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 735 | (_CMU_HFPERCLKEN0_ACMP3_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 736 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 737 #endif
Anna Bridge 160:5571c4ff569f 738
Anna Bridge 160:5571c4ff569f 739 #if defined(CMU_HFPERCLKEN0_PRS)
AnnaBridge 156:ff21514d8981 740 /** Peripheral reflex system clock. */
AnnaBridge 156:ff21514d8981 741 cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 742 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 743 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 744 | (_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 745 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 746 #endif
AnnaBridge 156:ff21514d8981 747
Anna Bridge 160:5571c4ff569f 748 #if defined(CMU_HFPERCLKEN0_DAC0)
AnnaBridge 156:ff21514d8981 749 /** Digital to analog converter 0 clock. */
AnnaBridge 156:ff21514d8981 750 cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 751 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 752 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 753 | (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 754 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 755 #endif
AnnaBridge 156:ff21514d8981 756
Anna Bridge 160:5571c4ff569f 757 #if defined(CMU_HFPERCLKEN0_VDAC0)
AnnaBridge 156:ff21514d8981 758 /** Voltage digital to analog converter 0 clock. */
AnnaBridge 156:ff21514d8981 759 cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 760 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 761 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 762 | (_CMU_HFPERCLKEN0_VDAC0_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 763 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 764 #elif defined(CMU_HFPERCLKEN1_VDAC0)
Anna Bridge 160:5571c4ff569f 765 /** Voltage digital to analog converter 0 clock. */
Anna Bridge 160:5571c4ff569f 766 cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 767 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 768 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 769 | (_CMU_HFPERCLKEN1_VDAC0_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 770 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 771 #endif
AnnaBridge 156:ff21514d8981 772
Anna Bridge 160:5571c4ff569f 773 #if defined(CMU_HFPERCLKEN0_IDAC0)
AnnaBridge 156:ff21514d8981 774 /** Current digital to analog converter 0 clock. */
AnnaBridge 156:ff21514d8981 775 cmuClock_IDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 776 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 777 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 778 | (_CMU_HFPERCLKEN0_IDAC0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 779 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 780 #endif
AnnaBridge 156:ff21514d8981 781
Anna Bridge 160:5571c4ff569f 782 #if defined(CMU_HFPERCLKEN0_GPIO)
AnnaBridge 156:ff21514d8981 783 /** General purpose input/output clock. */
AnnaBridge 156:ff21514d8981 784 cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 785 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 786 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 787 | (_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 788 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 789 #endif
AnnaBridge 156:ff21514d8981 790
Anna Bridge 160:5571c4ff569f 791 #if defined(CMU_HFPERCLKEN0_VCMP)
AnnaBridge 156:ff21514d8981 792 /** Voltage comparator clock. */
AnnaBridge 156:ff21514d8981 793 cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 794 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 795 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 796 | (_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 797 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 798 #endif
AnnaBridge 156:ff21514d8981 799
Anna Bridge 160:5571c4ff569f 800 #if defined(CMU_HFPERCLKEN0_ADC0)
AnnaBridge 156:ff21514d8981 801 /** Analog to digital converter 0 clock. */
AnnaBridge 156:ff21514d8981 802 cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 803 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 804 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 805 | (_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 806 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 807 #endif
AnnaBridge 156:ff21514d8981 808
Anna Bridge 160:5571c4ff569f 809 #if defined(CMU_HFPERCLKEN0_ADC1)
Anna Bridge 160:5571c4ff569f 810 /** Analog to digital converter 1 clock. */
Anna Bridge 160:5571c4ff569f 811 cmuClock_ADC1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 812 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 813 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 814 | (_CMU_HFPERCLKEN0_ADC1_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 815 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 816 #endif
Anna Bridge 160:5571c4ff569f 817
Anna Bridge 160:5571c4ff569f 818 #if defined(CMU_HFPERCLKEN0_I2C0)
AnnaBridge 156:ff21514d8981 819 /** I2C 0 clock. */
AnnaBridge 156:ff21514d8981 820 cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 821 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 822 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 823 | (_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 824 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 825 #endif
AnnaBridge 156:ff21514d8981 826
Anna Bridge 160:5571c4ff569f 827 #if defined(CMU_HFPERCLKEN0_I2C1)
AnnaBridge 156:ff21514d8981 828 /** I2C 1 clock. */
AnnaBridge 156:ff21514d8981 829 cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 830 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 831 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 832 | (_CMU_HFPERCLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 833 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 834 #endif
AnnaBridge 156:ff21514d8981 835
Anna Bridge 160:5571c4ff569f 836 #if defined(CMU_HFPERCLKEN0_I2C2)
AnnaBridge 156:ff21514d8981 837 /** I2C 2 clock. */
AnnaBridge 156:ff21514d8981 838 cmuClock_I2C2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 839 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 840 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 841 | (_CMU_HFPERCLKEN0_I2C2_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 842 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 843 #endif
AnnaBridge 156:ff21514d8981 844
Anna Bridge 160:5571c4ff569f 845 #if defined(CMU_HFPERCLKEN0_CSEN)
Anna Bridge 160:5571c4ff569f 846 /** Capacitive Sense HF clock */
Anna Bridge 160:5571c4ff569f 847 cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 848 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 849 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 850 | (_CMU_HFPERCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 851 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 852 #elif defined(CMU_HFPERCLKEN1_CSEN)
AnnaBridge 156:ff21514d8981 853 /** Capacitive Sense HF clock */
AnnaBridge 156:ff21514d8981 854 cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 855 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 856 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 857 | (_CMU_HFPERCLKEN1_CSEN_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 858 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 859 #endif
Anna Bridge 160:5571c4ff569f 860
Anna Bridge 160:5571c4ff569f 861 #if defined(CMU_HFPERCLKEN0_TRNG0)
Anna Bridge 160:5571c4ff569f 862 /** True random number generator clock */
Anna Bridge 160:5571c4ff569f 863 cmuClock_TRNG0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 864 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 865 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 866 | (_CMU_HFPERCLKEN0_TRNG0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 867 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 868 #endif
AnnaBridge 156:ff21514d8981 869
Anna Bridge 160:5571c4ff569f 870 #if defined(_CMU_HFPERCLKEN1_CAN0_MASK)
Anna Bridge 160:5571c4ff569f 871 /** Controller Area Network 0 clock. */
Anna Bridge 160:5571c4ff569f 872 cmuClock_CAN0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 873 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 874 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 875 | (_CMU_HFPERCLKEN1_CAN0_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 876 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 877 #endif
Anna Bridge 160:5571c4ff569f 878
Anna Bridge 160:5571c4ff569f 879 #if defined(_CMU_HFPERCLKEN1_CAN1_MASK)
Anna Bridge 160:5571c4ff569f 880 /** Controller Area Network 1 clock. */
Anna Bridge 160:5571c4ff569f 881 cmuClock_CAN1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
Anna Bridge 160:5571c4ff569f 882 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 883 | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 884 | (_CMU_HFPERCLKEN1_CAN1_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 885 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 886 #endif
AnnaBridge 156:ff21514d8981 887
AnnaBridge 156:ff21514d8981 888 /**********************/
AnnaBridge 156:ff21514d8981 889 /* HF core sub-branch */
AnnaBridge 156:ff21514d8981 890 /**********************/
AnnaBridge 156:ff21514d8981 891
AnnaBridge 156:ff21514d8981 892 /** Core clock */
AnnaBridge 156:ff21514d8981 893 cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 894 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 895 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 896 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 897 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 898
Anna Bridge 160:5571c4ff569f 899 #if defined(CMU_HFCORECLKEN0_AES)
AnnaBridge 156:ff21514d8981 900 /** Advanced encryption standard accelerator clock. */
AnnaBridge 156:ff21514d8981 901 cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 902 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 903 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 904 | (_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 905 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 906 #endif
AnnaBridge 156:ff21514d8981 907
Anna Bridge 160:5571c4ff569f 908 #if defined(CMU_HFCORECLKEN0_DMA)
AnnaBridge 156:ff21514d8981 909 /** Direct memory access controller clock. */
AnnaBridge 156:ff21514d8981 910 cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 911 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 912 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 913 | (_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 914 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 915 #endif
AnnaBridge 156:ff21514d8981 916
Anna Bridge 160:5571c4ff569f 917 #if defined(CMU_HFCORECLKEN0_LE)
AnnaBridge 156:ff21514d8981 918 /** Low energy clock divided down from HFCORECLK. */
AnnaBridge 156:ff21514d8981 919 cmuClock_HFLE = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 920 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 921 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 922 | (_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 923 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 924 #endif
AnnaBridge 156:ff21514d8981 925
Anna Bridge 160:5571c4ff569f 926 #if defined(CMU_HFCORECLKEN0_EBI)
AnnaBridge 156:ff21514d8981 927 /** External bus interface clock. */
AnnaBridge 156:ff21514d8981 928 cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 929 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 930 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 931 | (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 932 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 933 #elif defined(_CMU_HFBUSCLKEN0_EBI_MASK)
Anna Bridge 160:5571c4ff569f 934 /** External bus interface clock. */
Anna Bridge 160:5571c4ff569f 935 cmuClock_EBI = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
Anna Bridge 160:5571c4ff569f 936 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 937 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 938 | (_CMU_HFBUSCLKEN0_EBI_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 939 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 940 #endif
AnnaBridge 156:ff21514d8981 941
Anna Bridge 160:5571c4ff569f 942 #if defined(_CMU_HFBUSCLKEN0_ETH_MASK)
Anna Bridge 160:5571c4ff569f 943 /** Ethernet clock. */
Anna Bridge 160:5571c4ff569f 944 cmuClock_ETH = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
Anna Bridge 160:5571c4ff569f 945 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 946 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 947 | (_CMU_HFBUSCLKEN0_ETH_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 948 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 949 #endif
Anna Bridge 160:5571c4ff569f 950
Anna Bridge 160:5571c4ff569f 951 #if defined(_CMU_HFBUSCLKEN0_SDIO_MASK)
Anna Bridge 160:5571c4ff569f 952 /** SDIO clock. */
Anna Bridge 160:5571c4ff569f 953 cmuClock_SDIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
Anna Bridge 160:5571c4ff569f 954 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 955 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 956 | (_CMU_HFBUSCLKEN0_SDIO_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 957 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 958 #endif
Anna Bridge 160:5571c4ff569f 959
Anna Bridge 160:5571c4ff569f 960 #if defined(USBC_CLOCK_PRESENT)
AnnaBridge 156:ff21514d8981 961 /** USB Core clock. */
AnnaBridge 156:ff21514d8981 962 cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 963 | (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 964 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 965 | (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 966 | (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 967 #endif
Anna Bridge 160:5571c4ff569f 968 #if defined (USBR_CLOCK_PRESENT)
Anna Bridge 160:5571c4ff569f 969 /** USB Rate clock. */
Anna Bridge 160:5571c4ff569f 970 cmuClock_USBR = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 971 | (CMU_USBRCLKSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 972 | (CMU_USBRCLK_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 973 | (_CMU_USBCTRL_USBCLKEN_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 974 | (CMU_USBR_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 975 #endif
AnnaBridge 156:ff21514d8981 976
Anna Bridge 160:5571c4ff569f 977 #if defined(CMU_HFCORECLKEN0_USB)
AnnaBridge 156:ff21514d8981 978 /** USB clock. */
AnnaBridge 156:ff21514d8981 979 cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 980 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 981 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 982 | (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 983 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 984 #elif defined(CMU_HFBUSCLKEN0_USB)
Anna Bridge 160:5571c4ff569f 985 /** USB clock. */
Anna Bridge 160:5571c4ff569f 986 cmuClock_USB = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
Anna Bridge 160:5571c4ff569f 987 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 988 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 989 | (_CMU_HFBUSCLKEN0_USB_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 990 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 991 #endif
AnnaBridge 156:ff21514d8981 992
AnnaBridge 156:ff21514d8981 993 /***************/
AnnaBridge 156:ff21514d8981 994 /* LF A branch */
AnnaBridge 156:ff21514d8981 995 /***************/
AnnaBridge 156:ff21514d8981 996
AnnaBridge 156:ff21514d8981 997 /** Low frequency A clock */
AnnaBridge 156:ff21514d8981 998 cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 999 | (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 1000 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 1001 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 1002 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 1003
Anna Bridge 160:5571c4ff569f 1004 #if defined(CMU_LFACLKEN0_RTC)
AnnaBridge 156:ff21514d8981 1005 /** Real time counter clock. */
AnnaBridge 156:ff21514d8981 1006 cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 1007 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 1008 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 1009 | (_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 1010 | (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 1011 #endif
AnnaBridge 156:ff21514d8981 1012
Anna Bridge 160:5571c4ff569f 1013 #if defined(CMU_LFACLKEN0_LETIMER0)
AnnaBridge 156:ff21514d8981 1014 /** Low energy timer 0 clock. */
AnnaBridge 156:ff21514d8981 1015 cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 1016 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 1017 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 1018 | (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 1019 | (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 1020 #endif
AnnaBridge 156:ff21514d8981 1021
Anna Bridge 160:5571c4ff569f 1022 #if defined(CMU_LFACLKEN0_LETIMER1)
Anna Bridge 160:5571c4ff569f 1023 /** Low energy timer 1 clock. */
Anna Bridge 160:5571c4ff569f 1024 cmuClock_LETIMER1 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 1025 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 1026 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 1027 | (_CMU_LFACLKEN0_LETIMER1_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 1028 | (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 1029 #endif
Anna Bridge 160:5571c4ff569f 1030
Anna Bridge 160:5571c4ff569f 1031 #if defined(CMU_LFACLKEN0_LCD)
AnnaBridge 156:ff21514d8981 1032 /** Liquid crystal display, pre FDIV clock. */
AnnaBridge 156:ff21514d8981 1033 cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 1034 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 1035 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 1036 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 1037 | (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 1038
AnnaBridge 156:ff21514d8981 1039 /** Liquid crystal display clock. Please notice that FDIV prescaler
AnnaBridge 156:ff21514d8981 1040 * must be set by special API. */
AnnaBridge 156:ff21514d8981 1041 cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 1042 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 1043 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 1044 | (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 1045 | (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 1046 #endif
AnnaBridge 156:ff21514d8981 1047
Anna Bridge 160:5571c4ff569f 1048 #if defined(CMU_PCNTCTRL_PCNT0CLKEN)
AnnaBridge 156:ff21514d8981 1049 /** Pulse counter 0 clock. */
AnnaBridge 156:ff21514d8981 1050 cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 1051 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 1052 | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 1053 | (_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 1054 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 1055 #endif
AnnaBridge 156:ff21514d8981 1056
Anna Bridge 160:5571c4ff569f 1057 #if defined(CMU_PCNTCTRL_PCNT1CLKEN)
AnnaBridge 156:ff21514d8981 1058 /** Pulse counter 1 clock. */
AnnaBridge 156:ff21514d8981 1059 cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 1060 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 1061 | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 1062 | (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 1063 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 1064 #endif
AnnaBridge 156:ff21514d8981 1065
Anna Bridge 160:5571c4ff569f 1066 #if defined(CMU_PCNTCTRL_PCNT2CLKEN)
AnnaBridge 156:ff21514d8981 1067 /** Pulse counter 2 clock. */
AnnaBridge 156:ff21514d8981 1068 cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 1069 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 1070 | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 1071 | (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 1072 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 1073 #endif
Anna Bridge 160:5571c4ff569f 1074 #if defined(CMU_LFACLKEN0_LESENSE)
AnnaBridge 156:ff21514d8981 1075 /** LESENSE clock. */
AnnaBridge 156:ff21514d8981 1076 cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 1077 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 1078 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 1079 | (_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 1080 | (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 1081 #endif
AnnaBridge 156:ff21514d8981 1082
AnnaBridge 156:ff21514d8981 1083 /***************/
AnnaBridge 156:ff21514d8981 1084 /* LF B branch */
AnnaBridge 156:ff21514d8981 1085 /***************/
AnnaBridge 156:ff21514d8981 1086
AnnaBridge 156:ff21514d8981 1087 /** Low frequency B clock */
AnnaBridge 156:ff21514d8981 1088 cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 1089 | (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 1090 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 1091 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 1092 | (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 1093
Anna Bridge 160:5571c4ff569f 1094 #if defined(CMU_LFBCLKEN0_LEUART0)
AnnaBridge 156:ff21514d8981 1095 /** Low energy universal asynchronous receiver/transmitter 0 clock. */
AnnaBridge 156:ff21514d8981 1096 cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 1097 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 1098 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 1099 | (_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 1100 | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 1101 #endif
AnnaBridge 156:ff21514d8981 1102
Anna Bridge 160:5571c4ff569f 1103 #if defined(CMU_LFBCLKEN0_CSEN)
AnnaBridge 156:ff21514d8981 1104 /** Capacitive Sense LF clock. */
AnnaBridge 156:ff21514d8981 1105 cmuClock_CSEN_LF = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 1106 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 1107 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 1108 | (_CMU_LFBCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 1109 | (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 1110 #endif
AnnaBridge 156:ff21514d8981 1111
Anna Bridge 160:5571c4ff569f 1112 #if defined(CMU_LFBCLKEN0_LEUART1)
AnnaBridge 156:ff21514d8981 1113 /** Low energy universal asynchronous receiver/transmitter 1 clock. */
AnnaBridge 156:ff21514d8981 1114 cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 1115 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 1116 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 1117 | (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 1118 | (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 1119 #endif
AnnaBridge 156:ff21514d8981 1120
Anna Bridge 160:5571c4ff569f 1121 #if defined(CMU_LFBCLKEN0_SYSTICK)
AnnaBridge 156:ff21514d8981 1122 /** Cortex SYSTICK LF clock. */
AnnaBridge 156:ff21514d8981 1123 cmuClock_SYSTICK = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 1124 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 1125 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 1126 | (_CMU_LFBCLKEN0_SYSTICK_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 1127 | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 1128 #endif
AnnaBridge 156:ff21514d8981 1129
Anna Bridge 160:5571c4ff569f 1130 #if defined(_CMU_LFCCLKEN0_MASK)
AnnaBridge 156:ff21514d8981 1131 /***************/
AnnaBridge 156:ff21514d8981 1132 /* LF C branch */
AnnaBridge 156:ff21514d8981 1133 /***************/
AnnaBridge 156:ff21514d8981 1134
AnnaBridge 156:ff21514d8981 1135 /** Low frequency C clock */
AnnaBridge 156:ff21514d8981 1136 cmuClock_LFC = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 1137 | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 1138 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 1139 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 1140 | (CMU_LFC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 1141
Anna Bridge 160:5571c4ff569f 1142 #if defined(CMU_LFCCLKEN0_USBLE)
AnnaBridge 156:ff21514d8981 1143 /** USB LE clock. */
AnnaBridge 156:ff21514d8981 1144 cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 1145 | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 1146 | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 1147 | (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 1148 | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 1149 #elif defined(CMU_LFCCLKEN0_USB)
Anna Bridge 160:5571c4ff569f 1150 /** USB LE clock. */
Anna Bridge 160:5571c4ff569f 1151 cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 1152 | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 1153 | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 1154 | (_CMU_LFCCLKEN0_USB_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 1155 | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 1156 #endif
AnnaBridge 156:ff21514d8981 1157 #endif
AnnaBridge 156:ff21514d8981 1158
Anna Bridge 160:5571c4ff569f 1159 #if defined(_CMU_LFECLKEN0_MASK)
AnnaBridge 156:ff21514d8981 1160 /***************/
AnnaBridge 156:ff21514d8981 1161 /* LF E branch */
AnnaBridge 156:ff21514d8981 1162 /***************/
AnnaBridge 156:ff21514d8981 1163
Anna Bridge 160:5571c4ff569f 1164 /** Low frequency E clock */
AnnaBridge 156:ff21514d8981 1165 cmuClock_LFE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 1166 | (CMU_LFECLKSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 1167 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 1168 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 1169 | (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 1170
Anna Bridge 160:5571c4ff569f 1171 /** Real-time counter and calendar clock. */
Anna Bridge 160:5571c4ff569f 1172 #if defined (CMU_LFECLKEN0_RTCC)
AnnaBridge 156:ff21514d8981 1173 cmuClock_RTCC = (CMU_LFEPRESC0_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 1174 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 1175 | (CMU_LFECLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 1176 | (_CMU_LFECLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 1177 | (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 1178 #endif
AnnaBridge 156:ff21514d8981 1179 #endif
AnnaBridge 156:ff21514d8981 1180
Anna Bridge 160:5571c4ff569f 1181 /**********************************/
Anna Bridge 160:5571c4ff569f 1182 /* Asynchronous peripheral clocks */
Anna Bridge 160:5571c4ff569f 1183 /**********************************/
Anna Bridge 160:5571c4ff569f 1184
Anna Bridge 160:5571c4ff569f 1185 #if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK)
Anna Bridge 160:5571c4ff569f 1186 /** ADC0 asynchronous clock. */
Anna Bridge 160:5571c4ff569f 1187 cmuClock_ADC0ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 1188 | (CMU_ADC0ASYNCSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 1189 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 1190 | (0 << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 1191 | (CMU_ADC0ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 1192 #endif
Anna Bridge 160:5571c4ff569f 1193
Anna Bridge 160:5571c4ff569f 1194 #if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK)
Anna Bridge 160:5571c4ff569f 1195 /** ADC1 asynchronous clock. */
Anna Bridge 160:5571c4ff569f 1196 cmuClock_ADC1ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 1197 | (CMU_ADC1ASYNCSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 1198 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 1199 | (0 << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 1200 | (CMU_ADC1ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 1201 #endif
Anna Bridge 160:5571c4ff569f 1202
Anna Bridge 160:5571c4ff569f 1203 #if defined(_CMU_SDIOCTRL_SDIOCLKDIS_MASK)
Anna Bridge 160:5571c4ff569f 1204 /** SDIO reference clock. */
Anna Bridge 160:5571c4ff569f 1205 cmuClock_SDIOREF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 1206 | (CMU_SDIOREFSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 1207 | (CMU_SDIOREF_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 1208 | (_CMU_SDIOCTRL_SDIOCLKDIS_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 1209 | (CMU_SDIOREF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 1210 #endif
Anna Bridge 160:5571c4ff569f 1211
Anna Bridge 160:5571c4ff569f 1212 #if defined(_CMU_QSPICTRL_QSPI0CLKDIS_MASK)
Anna Bridge 160:5571c4ff569f 1213 /** QSPI0 reference clock. */
Anna Bridge 160:5571c4ff569f 1214 cmuClock_QSPI0REF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Anna Bridge 160:5571c4ff569f 1215 | (CMU_QSPI0REFSEL_REG << CMU_SEL_REG_POS)
Anna Bridge 160:5571c4ff569f 1216 | (CMU_QSPI0REF_EN_REG << CMU_EN_REG_POS)
Anna Bridge 160:5571c4ff569f 1217 | (_CMU_QSPICTRL_QSPI0CLKDIS_SHIFT << CMU_EN_BIT_POS)
Anna Bridge 160:5571c4ff569f 1218 | (CMU_QSPI0REF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Anna Bridge 160:5571c4ff569f 1219 #endif
AnnaBridge 156:ff21514d8981 1220 } CMU_Clock_TypeDef;
AnnaBridge 156:ff21514d8981 1221
AnnaBridge 156:ff21514d8981 1222 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
AnnaBridge 156:ff21514d8981 1223 /* Deprecated CMU_Clock_TypeDef member */
AnnaBridge 156:ff21514d8981 1224 #define cmuClock_CORELE cmuClock_HFLE
AnnaBridge 156:ff21514d8981 1225 /** @endcond */
AnnaBridge 156:ff21514d8981 1226
AnnaBridge 156:ff21514d8981 1227 /** Oscillator types. */
Anna Bridge 160:5571c4ff569f 1228 typedef enum {
AnnaBridge 156:ff21514d8981 1229 cmuOsc_LFXO, /**< Low frequency crystal oscillator. */
AnnaBridge 156:ff21514d8981 1230 cmuOsc_LFRCO, /**< Low frequency RC oscillator. */
AnnaBridge 156:ff21514d8981 1231 cmuOsc_HFXO, /**< High frequency crystal oscillator. */
AnnaBridge 156:ff21514d8981 1232 cmuOsc_HFRCO, /**< High frequency RC oscillator. */
AnnaBridge 156:ff21514d8981 1233 cmuOsc_AUXHFRCO, /**< Auxiliary high frequency RC oscillator. */
Anna Bridge 160:5571c4ff569f 1234 #if defined(_CMU_STATUS_USHFRCOENS_MASK)
AnnaBridge 156:ff21514d8981 1235 cmuOsc_USHFRCO, /**< USB high frequency RC oscillator */
AnnaBridge 156:ff21514d8981 1236 #endif
Anna Bridge 160:5571c4ff569f 1237 #if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO)
AnnaBridge 156:ff21514d8981 1238 cmuOsc_ULFRCO, /**< Ultra low frequency RC oscillator. */
AnnaBridge 156:ff21514d8981 1239 #endif
Anna Bridge 160:5571c4ff569f 1240 #if defined(_CMU_STATUS_PLFRCOENS_MASK)
AnnaBridge 156:ff21514d8981 1241 cmuOsc_PLFRCO, /**< Precision Low Frequency Oscillator. */
AnnaBridge 156:ff21514d8981 1242 #endif
AnnaBridge 156:ff21514d8981 1243 } CMU_Osc_TypeDef;
AnnaBridge 156:ff21514d8981 1244
AnnaBridge 156:ff21514d8981 1245 /** Oscillator modes. */
Anna Bridge 160:5571c4ff569f 1246 typedef enum {
AnnaBridge 156:ff21514d8981 1247 cmuOscMode_Crystal, /**< Crystal oscillator. */
AnnaBridge 156:ff21514d8981 1248 cmuOscMode_AcCoupled, /**< AC coupled buffer. */
AnnaBridge 156:ff21514d8981 1249 cmuOscMode_External, /**< External digital clock. */
AnnaBridge 156:ff21514d8981 1250 } CMU_OscMode_TypeDef;
AnnaBridge 156:ff21514d8981 1251
AnnaBridge 156:ff21514d8981 1252 /** Selectable clock sources. */
Anna Bridge 160:5571c4ff569f 1253 typedef enum {
AnnaBridge 156:ff21514d8981 1254 cmuSelect_Error, /**< Usage error. */
AnnaBridge 156:ff21514d8981 1255 cmuSelect_Disabled, /**< Clock selector disabled. */
AnnaBridge 156:ff21514d8981 1256 cmuSelect_LFXO, /**< Low frequency crystal oscillator. */
AnnaBridge 156:ff21514d8981 1257 cmuSelect_LFRCO, /**< Low frequency RC oscillator. */
AnnaBridge 156:ff21514d8981 1258 cmuSelect_HFXO, /**< High frequency crystal oscillator. */
AnnaBridge 156:ff21514d8981 1259 cmuSelect_HFRCO, /**< High frequency RC oscillator. */
AnnaBridge 156:ff21514d8981 1260 cmuSelect_HFCLKLE, /**< High frequency LE clock divided by 2 or 4. */
AnnaBridge 156:ff21514d8981 1261 cmuSelect_AUXHFRCO, /**< Auxilliary clock source can be used for debug clock */
Anna Bridge 160:5571c4ff569f 1262 cmuSelect_HFSRCCLK, /**< High frequency source clock */
AnnaBridge 156:ff21514d8981 1263 cmuSelect_HFCLK, /**< Divided HFCLK on Giant for debug clock, undivided on
AnnaBridge 156:ff21514d8981 1264 Tiny Gecko and for USBC (not used on Gecko) */
Anna Bridge 160:5571c4ff569f 1265 #if defined(CMU_STATUS_USHFRCOENS)
AnnaBridge 156:ff21514d8981 1266 cmuSelect_USHFRCO, /**< USB high frequency RC oscillator */
AnnaBridge 156:ff21514d8981 1267 #endif
Anna Bridge 160:5571c4ff569f 1268 #if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2)
Anna Bridge 160:5571c4ff569f 1269 cmuSelect_USHFRCODIV2, /**< USB high frequency RC oscillator / 2 */
AnnaBridge 156:ff21514d8981 1270 #endif
Anna Bridge 160:5571c4ff569f 1271 #if defined(CMU_HFXOCTRL_HFXOX2EN)
Anna Bridge 160:5571c4ff569f 1272 cmuSelect_HFXOX2, /**< High frequency crystal oscillator x 2. */
Anna Bridge 160:5571c4ff569f 1273 #endif
Anna Bridge 160:5571c4ff569f 1274 #if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO)
AnnaBridge 156:ff21514d8981 1275 cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */
AnnaBridge 156:ff21514d8981 1276 #endif
Anna Bridge 160:5571c4ff569f 1277 #if defined(_CMU_STATUS_PLFRCOENS_MASK)
AnnaBridge 156:ff21514d8981 1278 cmuSelect_PLFRCO, /**< Precision Low Frequency Oscillator. */
AnnaBridge 156:ff21514d8981 1279 #endif
AnnaBridge 156:ff21514d8981 1280 } CMU_Select_TypeDef;
AnnaBridge 156:ff21514d8981 1281
Anna Bridge 160:5571c4ff569f 1282 #if defined(CMU_HFCORECLKEN0_LE)
AnnaBridge 156:ff21514d8981 1283 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
AnnaBridge 156:ff21514d8981 1284 /* Deprecated CMU_Select_TypeDef member */
AnnaBridge 156:ff21514d8981 1285 #define cmuSelect_CORELEDIV2 cmuSelect_HFCLKLE
AnnaBridge 156:ff21514d8981 1286 /** @endcond */
AnnaBridge 156:ff21514d8981 1287 #endif
AnnaBridge 156:ff21514d8981 1288
Anna Bridge 160:5571c4ff569f 1289 #if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK)
AnnaBridge 156:ff21514d8981 1290 /** HFXO tuning modes */
Anna Bridge 160:5571c4ff569f 1291 typedef enum {
AnnaBridge 156:ff21514d8981 1292 cmuHFXOTuningMode_Auto = 0,
Anna Bridge 160:5571c4ff569f 1293 cmuHFXOTuningMode_PeakDetectCommand = CMU_CMD_HFXOPEAKDETSTART, /**< Run peak detect optimization only */
Anna Bridge 160:5571c4ff569f 1294 #if defined(CMU_CMD_HFXOSHUNTOPTSTART)
AnnaBridge 156:ff21514d8981 1295 cmuHFXOTuningMode_ShuntCommand = CMU_CMD_HFXOSHUNTOPTSTART, /**< Run shunt current optimization only */
AnnaBridge 156:ff21514d8981 1296 cmuHFXOTuningMode_PeakShuntCommand = CMU_CMD_HFXOPEAKDETSTART /**< Run peak and shunt current optimization */
AnnaBridge 156:ff21514d8981 1297 | CMU_CMD_HFXOSHUNTOPTSTART,
Anna Bridge 160:5571c4ff569f 1298 #endif
AnnaBridge 156:ff21514d8981 1299 } CMU_HFXOTuningMode_TypeDef;
AnnaBridge 156:ff21514d8981 1300 #endif
AnnaBridge 156:ff21514d8981 1301
Anna Bridge 160:5571c4ff569f 1302 #if defined(_CMU_CTRL_LFXOBOOST_MASK)
AnnaBridge 156:ff21514d8981 1303 /** LFXO Boost values. */
Anna Bridge 160:5571c4ff569f 1304 typedef enum {
AnnaBridge 156:ff21514d8981 1305 cmuLfxoBoost70 = 0x0,
AnnaBridge 156:ff21514d8981 1306 cmuLfxoBoost100 = 0x2,
Anna Bridge 160:5571c4ff569f 1307 #if defined(_EMU_AUXCTRL_REDLFXOBOOST_MASK)
AnnaBridge 156:ff21514d8981 1308 cmuLfxoBoost70Reduced = 0x1,
AnnaBridge 156:ff21514d8981 1309 cmuLfxoBoost100Reduced = 0x3,
AnnaBridge 156:ff21514d8981 1310 #endif
AnnaBridge 156:ff21514d8981 1311 } CMU_LFXOBoost_TypeDef;
AnnaBridge 156:ff21514d8981 1312 #endif
AnnaBridge 156:ff21514d8981 1313
Anna Bridge 160:5571c4ff569f 1314 #if defined(CMU_OSCENCMD_DPLLEN)
Anna Bridge 160:5571c4ff569f 1315 /** DPLL reference clock selector. */
Anna Bridge 160:5571c4ff569f 1316 typedef enum {
Anna Bridge 160:5571c4ff569f 1317 cmuDPLLClkSel_Hfxo = _CMU_DPLLCTRL_REFSEL_HFXO, /**< HFXO is DPLL reference clock. */
Anna Bridge 160:5571c4ff569f 1318 cmuDPLLClkSel_Lfxo = _CMU_DPLLCTRL_REFSEL_LFXO, /**< LFXO is DPLL reference clock. */
Anna Bridge 160:5571c4ff569f 1319 cmuDPLLClkSel_Clkin0 = _CMU_DPLLCTRL_REFSEL_CLKIN0 /**< CLKIN0 is DPLL reference clock. */
Anna Bridge 160:5571c4ff569f 1320 } CMU_DPLLClkSel_TypeDef;
Anna Bridge 160:5571c4ff569f 1321
Anna Bridge 160:5571c4ff569f 1322 /** DPLL reference clock edge detect selector. */
Anna Bridge 160:5571c4ff569f 1323 typedef enum {
Anna Bridge 160:5571c4ff569f 1324 cmuDPLLEdgeSel_Fall = _CMU_DPLLCTRL_EDGESEL_FALL, /**< Detect falling edge of reference clock. */
Anna Bridge 160:5571c4ff569f 1325 cmuDPLLEdgeSel_Rise = _CMU_DPLLCTRL_EDGESEL_RISE /**< Detect rising edge of reference clock. */
Anna Bridge 160:5571c4ff569f 1326 } CMU_DPLLEdgeSel_TypeDef;
Anna Bridge 160:5571c4ff569f 1327
Anna Bridge 160:5571c4ff569f 1328 /** DPLL lock mode selector. */
Anna Bridge 160:5571c4ff569f 1329 typedef enum {
Anna Bridge 160:5571c4ff569f 1330 cmuDPLLLockMode_Freq = _CMU_DPLLCTRL_MODE_FREQLL, /**< Frequency lock mode. */
Anna Bridge 160:5571c4ff569f 1331 cmuDPLLLockMode_Phase = _CMU_DPLLCTRL_MODE_PHASELL /**< Phase lock mode. */
Anna Bridge 160:5571c4ff569f 1332 } CMU_DPLLLockMode_TypeDef;
Anna Bridge 160:5571c4ff569f 1333 #endif // CMU_OSCENCMD_DPLLEN
Anna Bridge 160:5571c4ff569f 1334
AnnaBridge 156:ff21514d8981 1335 /*******************************************************************************
AnnaBridge 156:ff21514d8981 1336 ******************************* STRUCTS ***********************************
AnnaBridge 156:ff21514d8981 1337 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1338
AnnaBridge 156:ff21514d8981 1339 /** LFXO initialization structure. Init values should be obtained from a configuration tool,
AnnaBridge 156:ff21514d8981 1340 app note or xtal datasheet */
Anna Bridge 160:5571c4ff569f 1341 typedef struct {
Anna Bridge 160:5571c4ff569f 1342 #if defined(_CMU_LFXOCTRL_MASK)
AnnaBridge 156:ff21514d8981 1343 uint8_t ctune; /**< CTUNE (load capacitance) value */
AnnaBridge 156:ff21514d8981 1344 uint8_t gain; /**< Gain / max startup margin */
AnnaBridge 156:ff21514d8981 1345 #else
AnnaBridge 156:ff21514d8981 1346 CMU_LFXOBoost_TypeDef boost; /**< LFXO boost */
AnnaBridge 156:ff21514d8981 1347 #endif
AnnaBridge 156:ff21514d8981 1348 uint8_t timeout; /**< Startup delay */
AnnaBridge 156:ff21514d8981 1349 CMU_OscMode_TypeDef mode; /**< Oscillator mode */
AnnaBridge 156:ff21514d8981 1350 } CMU_LFXOInit_TypeDef;
AnnaBridge 156:ff21514d8981 1351
Anna Bridge 160:5571c4ff569f 1352 #if defined(_CMU_LFXOCTRL_MASK)
AnnaBridge 156:ff21514d8981 1353 /** Default LFXO initialization values for platform 2 devices which contain a
AnnaBridge 156:ff21514d8981 1354 * separate LFXOCTRL register. */
Anna Bridge 160:5571c4ff569f 1355 #define CMU_LFXOINIT_DEFAULT \
Anna Bridge 160:5571c4ff569f 1356 { \
Anna Bridge 160:5571c4ff569f 1357 _CMU_LFXOCTRL_TUNING_DEFAULT, /* Default CTUNE value, 0 */ \
Anna Bridge 160:5571c4ff569f 1358 _CMU_LFXOCTRL_GAIN_DEFAULT, /* Default gain, 2 */ \
Anna Bridge 160:5571c4ff569f 1359 _CMU_LFXOCTRL_TIMEOUT_DEFAULT, /* Default start-up delay, 32k cycles */ \
Anna Bridge 160:5571c4ff569f 1360 cmuOscMode_Crystal, /* Crystal oscillator */ \
AnnaBridge 156:ff21514d8981 1361 }
AnnaBridge 156:ff21514d8981 1362 #define CMU_LFXOINIT_EXTERNAL_CLOCK \
AnnaBridge 156:ff21514d8981 1363 { \
AnnaBridge 156:ff21514d8981 1364 0, /* No CTUNE value needed */ \
AnnaBridge 156:ff21514d8981 1365 0, /* No LFXO startup gain */ \
AnnaBridge 156:ff21514d8981 1366 _CMU_LFXOCTRL_TIMEOUT_2CYCLES, /* Minimal lfxo start-up delay, 2 cycles */ \
AnnaBridge 156:ff21514d8981 1367 cmuOscMode_External, /* External digital clock */ \
AnnaBridge 156:ff21514d8981 1368 }
AnnaBridge 156:ff21514d8981 1369 #else
AnnaBridge 156:ff21514d8981 1370 /** Default LFXO initialization values for platform 1 devices. */
Anna Bridge 160:5571c4ff569f 1371 #define CMU_LFXOINIT_DEFAULT \
Anna Bridge 160:5571c4ff569f 1372 { \
Anna Bridge 160:5571c4ff569f 1373 cmuLfxoBoost70, \
Anna Bridge 160:5571c4ff569f 1374 _CMU_CTRL_LFXOTIMEOUT_DEFAULT, \
Anna Bridge 160:5571c4ff569f 1375 cmuOscMode_Crystal, \
AnnaBridge 156:ff21514d8981 1376 }
Anna Bridge 160:5571c4ff569f 1377 #define CMU_LFXOINIT_EXTERNAL_CLOCK \
Anna Bridge 160:5571c4ff569f 1378 { \
Anna Bridge 160:5571c4ff569f 1379 cmuLfxoBoost70, \
Anna Bridge 160:5571c4ff569f 1380 _CMU_CTRL_LFXOTIMEOUT_8CYCLES, \
Anna Bridge 160:5571c4ff569f 1381 cmuOscMode_External, \
AnnaBridge 156:ff21514d8981 1382 }
AnnaBridge 156:ff21514d8981 1383 #endif
AnnaBridge 156:ff21514d8981 1384
AnnaBridge 156:ff21514d8981 1385 /** HFXO initialization structure. Init values should be obtained from a configuration tool,
AnnaBridge 156:ff21514d8981 1386 app note or xtal datasheet */
Anna Bridge 160:5571c4ff569f 1387 typedef struct {
Anna Bridge 160:5571c4ff569f 1388 #if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100)
Anna Bridge 160:5571c4ff569f 1389 uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */
Anna Bridge 160:5571c4ff569f 1390 uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */
Anna Bridge 160:5571c4ff569f 1391 uint16_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */
Anna Bridge 160:5571c4ff569f 1392 uint16_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */
Anna Bridge 160:5571c4ff569f 1393 uint8_t timeoutPeakDetect; /**< Timeout - peak detection */
Anna Bridge 160:5571c4ff569f 1394 uint8_t timeoutSteady; /**< Timeout - steady-state */
Anna Bridge 160:5571c4ff569f 1395 uint8_t timeoutStartup; /**< Timeout - startup */
Anna Bridge 160:5571c4ff569f 1396 #elif defined(_CMU_HFXOCTRL_MASK)
AnnaBridge 156:ff21514d8981 1397 bool lowPowerMode; /**< Enable low-power mode */
AnnaBridge 156:ff21514d8981 1398 bool autoStartEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */
AnnaBridge 156:ff21514d8981 1399 bool autoSelEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */
AnnaBridge 156:ff21514d8981 1400 bool autoStartSelOnRacWakeup; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */
AnnaBridge 156:ff21514d8981 1401 uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */
AnnaBridge 156:ff21514d8981 1402 uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */
AnnaBridge 156:ff21514d8981 1403 uint8_t regIshSteadyState; /**< Shunt steady-state current */
AnnaBridge 156:ff21514d8981 1404 uint8_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */
AnnaBridge 156:ff21514d8981 1405 uint8_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */
AnnaBridge 156:ff21514d8981 1406 uint8_t thresholdPeakDetect; /**< Peak detection threshold */
AnnaBridge 156:ff21514d8981 1407 uint8_t timeoutShuntOptimization; /**< Timeout - shunt optimization */
AnnaBridge 156:ff21514d8981 1408 uint8_t timeoutPeakDetect; /**< Timeout - peak detection */
AnnaBridge 156:ff21514d8981 1409 uint8_t timeoutSteady; /**< Timeout - steady-state */
AnnaBridge 156:ff21514d8981 1410 uint8_t timeoutStartup; /**< Timeout - startup */
AnnaBridge 156:ff21514d8981 1411 #else
AnnaBridge 156:ff21514d8981 1412 uint8_t boost; /**< HFXO Boost, 0=50% 1=70%, 2=80%, 3=100% */
AnnaBridge 156:ff21514d8981 1413 uint8_t timeout; /**< Startup delay */
AnnaBridge 156:ff21514d8981 1414 bool glitchDetector; /**< Enable/disable glitch detector */
AnnaBridge 156:ff21514d8981 1415 #endif
AnnaBridge 156:ff21514d8981 1416 CMU_OscMode_TypeDef mode; /**< Oscillator mode */
AnnaBridge 156:ff21514d8981 1417 } CMU_HFXOInit_TypeDef;
AnnaBridge 156:ff21514d8981 1418
Anna Bridge 160:5571c4ff569f 1419 #if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100)
Anna Bridge 160:5571c4ff569f 1420 #define CMU_HFXOINIT_DEFAULT \
Anna Bridge 160:5571c4ff569f 1421 { \
Anna Bridge 160:5571c4ff569f 1422 _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
Anna Bridge 160:5571c4ff569f 1423 _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
Anna Bridge 160:5571c4ff569f 1424 _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \
Anna Bridge 160:5571c4ff569f 1425 _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \
Anna Bridge 160:5571c4ff569f 1426 _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \
Anna Bridge 160:5571c4ff569f 1427 _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \
Anna Bridge 160:5571c4ff569f 1428 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
Anna Bridge 160:5571c4ff569f 1429 cmuOscMode_Crystal, \
Anna Bridge 160:5571c4ff569f 1430 }
Anna Bridge 160:5571c4ff569f 1431 #define CMU_HFXOINIT_EXTERNAL_CLOCK \
Anna Bridge 160:5571c4ff569f 1432 { \
Anna Bridge 160:5571c4ff569f 1433 _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
Anna Bridge 160:5571c4ff569f 1434 _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
Anna Bridge 160:5571c4ff569f 1435 _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \
Anna Bridge 160:5571c4ff569f 1436 _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \
Anna Bridge 160:5571c4ff569f 1437 _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \
Anna Bridge 160:5571c4ff569f 1438 _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \
Anna Bridge 160:5571c4ff569f 1439 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
Anna Bridge 160:5571c4ff569f 1440 cmuOscMode_External, \
Anna Bridge 160:5571c4ff569f 1441 }
Anna Bridge 160:5571c4ff569f 1442 #elif defined(_CMU_HFXOCTRL_MASK)
AnnaBridge 156:ff21514d8981 1443 /**
AnnaBridge 156:ff21514d8981 1444 * Default HFXO initialization values for Platform 2 devices which contain a
AnnaBridge 156:ff21514d8981 1445 * separate HFXOCTRL register.
AnnaBridge 156:ff21514d8981 1446 */
Anna Bridge 160:5571c4ff569f 1447 #if defined(_EFR_DEVICE)
Anna Bridge 160:5571c4ff569f 1448 #define CMU_HFXOINIT_DEFAULT \
Anna Bridge 160:5571c4ff569f 1449 { \
Anna Bridge 160:5571c4ff569f 1450 false, /* Low-noise mode for EFR32 */ \
Anna Bridge 160:5571c4ff569f 1451 false, /* @deprecated no longer in use */ \
Anna Bridge 160:5571c4ff569f 1452 false, /* @deprecated no longer in use */ \
Anna Bridge 160:5571c4ff569f 1453 false, /* @deprecated no longer in use */ \
Anna Bridge 160:5571c4ff569f 1454 _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
Anna Bridge 160:5571c4ff569f 1455 _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
Anna Bridge 160:5571c4ff569f 1456 0xA, /* Default Shunt steady-state current */ \
Anna Bridge 160:5571c4ff569f 1457 0x20, /* Matching errata fix in @ref CHIP_Init() */ \
Anna Bridge 160:5571c4ff569f 1458 0x7, /* Recommended steady-state XO core bias current */ \
Anna Bridge 160:5571c4ff569f 1459 0x6, /* Recommended peak detection threshold */ \
Anna Bridge 160:5571c4ff569f 1460 0x2, /* Recommended shunt optimization timeout */ \
Anna Bridge 160:5571c4ff569f 1461 0xA, /* Recommended peak detection timeout */ \
Anna Bridge 160:5571c4ff569f 1462 0x4, /* Recommended steady timeout */ \
Anna Bridge 160:5571c4ff569f 1463 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
Anna Bridge 160:5571c4ff569f 1464 cmuOscMode_Crystal, \
Anna Bridge 160:5571c4ff569f 1465 }
AnnaBridge 156:ff21514d8981 1466 #else /* EFM32 device */
Anna Bridge 160:5571c4ff569f 1467 #define CMU_HFXOINIT_DEFAULT \
Anna Bridge 160:5571c4ff569f 1468 { \
Anna Bridge 160:5571c4ff569f 1469 true, /* Low-power mode for EFM32 */ \
Anna Bridge 160:5571c4ff569f 1470 false, /* @deprecated no longer in use */ \
Anna Bridge 160:5571c4ff569f 1471 false, /* @deprecated no longer in use */ \
Anna Bridge 160:5571c4ff569f 1472 false, /* @deprecated no longer in use */ \
Anna Bridge 160:5571c4ff569f 1473 _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
Anna Bridge 160:5571c4ff569f 1474 _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
Anna Bridge 160:5571c4ff569f 1475 0xA, /* Default shunt steady-state current */ \
Anna Bridge 160:5571c4ff569f 1476 0x20, /* Matching errata fix in @ref CHIP_Init() */ \
Anna Bridge 160:5571c4ff569f 1477 0x7, /* Recommended steady-state osc core bias current */ \
Anna Bridge 160:5571c4ff569f 1478 0x6, /* Recommended peak detection threshold */ \
Anna Bridge 160:5571c4ff569f 1479 0x2, /* Recommended shunt optimization timeout */ \
Anna Bridge 160:5571c4ff569f 1480 0xA, /* Recommended peak detection timeout */ \
Anna Bridge 160:5571c4ff569f 1481 0x4, /* Recommended steady timeout */ \
Anna Bridge 160:5571c4ff569f 1482 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
Anna Bridge 160:5571c4ff569f 1483 cmuOscMode_Crystal, \
Anna Bridge 160:5571c4ff569f 1484 }
AnnaBridge 156:ff21514d8981 1485 #endif /* _EFR_DEVICE */
Anna Bridge 160:5571c4ff569f 1486 #define CMU_HFXOINIT_EXTERNAL_CLOCK \
Anna Bridge 160:5571c4ff569f 1487 { \
Anna Bridge 160:5571c4ff569f 1488 true, /* Low-power mode */ \
Anna Bridge 160:5571c4ff569f 1489 false, /* @deprecated no longer in use */ \
Anna Bridge 160:5571c4ff569f 1490 false, /* @deprecated no longer in use */ \
Anna Bridge 160:5571c4ff569f 1491 false, /* @deprecated no longer in use */ \
Anna Bridge 160:5571c4ff569f 1492 0, /* Startup CTUNE=0 recommended for external clock */ \
Anna Bridge 160:5571c4ff569f 1493 0, /* Steady CTUNE=0 recommended for external clock */ \
Anna Bridge 160:5571c4ff569f 1494 0xA, /* Default shunt steady-state current */ \
Anna Bridge 160:5571c4ff569f 1495 0, /* Startup IBTRIMXOCORE=0 recommended for external clock */ \
Anna Bridge 160:5571c4ff569f 1496 0, /* Steady IBTRIMXOCORE=0 recommended for external clock */ \
Anna Bridge 160:5571c4ff569f 1497 0x6, /* Recommended peak detection threshold */ \
Anna Bridge 160:5571c4ff569f 1498 0x2, /* Recommended shunt optimization timeout */ \
Anna Bridge 160:5571c4ff569f 1499 0x0, /* Peak-detect not recommended for external clock usage */ \
Anna Bridge 160:5571c4ff569f 1500 _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES, /* Minimal steady timeout */ \
Anna Bridge 160:5571c4ff569f 1501 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES, /* Minimal startup timeout */ \
Anna Bridge 160:5571c4ff569f 1502 cmuOscMode_External, \
Anna Bridge 160:5571c4ff569f 1503 }
AnnaBridge 156:ff21514d8981 1504 #else /* _CMU_HFXOCTRL_MASK */
AnnaBridge 156:ff21514d8981 1505 /**
AnnaBridge 156:ff21514d8981 1506 * Default HFXO initialization values for Platform 1 devices.
AnnaBridge 156:ff21514d8981 1507 */
Anna Bridge 160:5571c4ff569f 1508 #define CMU_HFXOINIT_DEFAULT \
Anna Bridge 160:5571c4ff569f 1509 { \
Anna Bridge 160:5571c4ff569f 1510 _CMU_CTRL_HFXOBOOST_DEFAULT, /* 100% HFXO boost */ \
Anna Bridge 160:5571c4ff569f 1511 _CMU_CTRL_HFXOTIMEOUT_DEFAULT, /* 16k startup delay */ \
Anna Bridge 160:5571c4ff569f 1512 false, /* Disable glitch detector */ \
Anna Bridge 160:5571c4ff569f 1513 cmuOscMode_Crystal, /* Crystal oscillator */ \
Anna Bridge 160:5571c4ff569f 1514 }
Anna Bridge 160:5571c4ff569f 1515 #define CMU_HFXOINIT_EXTERNAL_CLOCK \
Anna Bridge 160:5571c4ff569f 1516 { \
Anna Bridge 160:5571c4ff569f 1517 0, /* Minimal HFXO boost, 50% */ \
Anna Bridge 160:5571c4ff569f 1518 _CMU_CTRL_HFXOTIMEOUT_8CYCLES, /* Minimal startup delay, 8 cycles */ \
Anna Bridge 160:5571c4ff569f 1519 false, /* Disable glitch detector */ \
Anna Bridge 160:5571c4ff569f 1520 cmuOscMode_External, /* External digital clock */ \
Anna Bridge 160:5571c4ff569f 1521 }
AnnaBridge 156:ff21514d8981 1522 #endif /* _CMU_HFXOCTRL_MASK */
AnnaBridge 156:ff21514d8981 1523
Anna Bridge 160:5571c4ff569f 1524 #if defined(CMU_OSCENCMD_DPLLEN)
Anna Bridge 160:5571c4ff569f 1525 /** DPLL initialization structure. Frequency will be Fref*(N+1)/(M+1). */
Anna Bridge 160:5571c4ff569f 1526 typedef struct {
Anna Bridge 160:5571c4ff569f 1527 uint32_t frequency; /**< PLL frequency value, max 40 MHz. */
Anna Bridge 160:5571c4ff569f 1528 uint16_t n; /**< Factor N. 32 <= N <= 4095 */
Anna Bridge 160:5571c4ff569f 1529 uint16_t m; /**< Factor M. M <= 4095 */
Anna Bridge 160:5571c4ff569f 1530 uint8_t ssInterval; /**< Spread spectrum update interval. */
Anna Bridge 160:5571c4ff569f 1531 uint8_t ssAmplitude; /**< Spread spectrum amplitude. */
Anna Bridge 160:5571c4ff569f 1532 CMU_DPLLClkSel_TypeDef refClk; /**< Reference clock selector. */
Anna Bridge 160:5571c4ff569f 1533 CMU_DPLLEdgeSel_TypeDef edgeSel; /**< Reference clock edge detect selector. */
Anna Bridge 160:5571c4ff569f 1534 CMU_DPLLLockMode_TypeDef lockMode; /**< DPLL lock mode selector. */
Anna Bridge 160:5571c4ff569f 1535 bool autoRecover; /**< Enable automatic lock recovery. */
Anna Bridge 160:5571c4ff569f 1536 } CMU_DPLLInit_TypeDef;
Anna Bridge 160:5571c4ff569f 1537
Anna Bridge 160:5571c4ff569f 1538 /**
Anna Bridge 160:5571c4ff569f 1539 * DPLL initialization values for 39,998,805 Hz using LFXO as reference
Anna Bridge 160:5571c4ff569f 1540 * clock, M=2 and N=3661.
Anna Bridge 160:5571c4ff569f 1541 */
Anna Bridge 160:5571c4ff569f 1542 #define CMU_DPLL_LFXO_TO_40MHZ \
Anna Bridge 160:5571c4ff569f 1543 { \
Anna Bridge 160:5571c4ff569f 1544 39998805, /* Target frequency. */ \
Anna Bridge 160:5571c4ff569f 1545 3661, /* Factor N. */ \
Anna Bridge 160:5571c4ff569f 1546 2, /* Factor M. */ \
Anna Bridge 160:5571c4ff569f 1547 0, /* No spread spectrum clocking. */ \
Anna Bridge 160:5571c4ff569f 1548 0, /* No spread spectrum clocking. */ \
Anna Bridge 160:5571c4ff569f 1549 cmuDPLLClkSel_Lfxo, /* Select LFXO as reference clock. */ \
Anna Bridge 160:5571c4ff569f 1550 cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
Anna Bridge 160:5571c4ff569f 1551 cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
Anna Bridge 160:5571c4ff569f 1552 true /* Enable automatic lock recovery. */ \
Anna Bridge 160:5571c4ff569f 1553 }
Anna Bridge 160:5571c4ff569f 1554 #endif // CMU_OSCENCMD_DPLLEN
AnnaBridge 156:ff21514d8981 1555
AnnaBridge 156:ff21514d8981 1556 /*******************************************************************************
AnnaBridge 156:ff21514d8981 1557 ***************************** PROTOTYPES **********************************
AnnaBridge 156:ff21514d8981 1558 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1559
Anna Bridge 160:5571c4ff569f 1560 #if defined(_CMU_AUXHFRCOCTRL_BAND_MASK)
AnnaBridge 156:ff21514d8981 1561 CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void);
AnnaBridge 156:ff21514d8981 1562 void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band);
AnnaBridge 156:ff21514d8981 1563
Anna Bridge 160:5571c4ff569f 1564 #elif defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK)
AnnaBridge 156:ff21514d8981 1565 CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void);
AnnaBridge 156:ff21514d8981 1566 void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq);
AnnaBridge 156:ff21514d8981 1567 #endif
AnnaBridge 156:ff21514d8981 1568
AnnaBridge 156:ff21514d8981 1569 uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference);
AnnaBridge 156:ff21514d8981 1570
Anna Bridge 160:5571c4ff569f 1571 #if defined(_CMU_CALCTRL_UPSEL_MASK) && defined(_CMU_CALCTRL_DOWNSEL_MASK)
AnnaBridge 156:ff21514d8981 1572 void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,
AnnaBridge 156:ff21514d8981 1573 CMU_Osc_TypeDef upSel);
AnnaBridge 156:ff21514d8981 1574 #endif
AnnaBridge 156:ff21514d8981 1575
AnnaBridge 156:ff21514d8981 1576 uint32_t CMU_CalibrateCountGet(void);
AnnaBridge 156:ff21514d8981 1577 void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable);
AnnaBridge 156:ff21514d8981 1578 CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock);
AnnaBridge 156:ff21514d8981 1579 void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div);
AnnaBridge 156:ff21514d8981 1580 uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock);
AnnaBridge 156:ff21514d8981 1581
Anna Bridge 160:5571c4ff569f 1582 #if defined(_SILICON_LABS_32B_SERIES_1)
AnnaBridge 156:ff21514d8981 1583 void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, uint32_t presc);
AnnaBridge 156:ff21514d8981 1584 uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock);
AnnaBridge 156:ff21514d8981 1585 #endif
AnnaBridge 156:ff21514d8981 1586
AnnaBridge 156:ff21514d8981 1587 void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref);
AnnaBridge 156:ff21514d8981 1588 CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock);
Anna Bridge 160:5571c4ff569f 1589
Anna Bridge 160:5571c4ff569f 1590 #if defined(CMU_OSCENCMD_DPLLEN)
Anna Bridge 160:5571c4ff569f 1591 bool CMU_DPLLLock(CMU_DPLLInit_TypeDef *init);
Anna Bridge 160:5571c4ff569f 1592 #endif
AnnaBridge 156:ff21514d8981 1593 void CMU_FreezeEnable(bool enable);
AnnaBridge 156:ff21514d8981 1594
Anna Bridge 160:5571c4ff569f 1595 #if defined(_CMU_HFRCOCTRL_BAND_MASK)
AnnaBridge 156:ff21514d8981 1596 CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void);
AnnaBridge 156:ff21514d8981 1597 void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band);
AnnaBridge 156:ff21514d8981 1598
Anna Bridge 160:5571c4ff569f 1599 #elif defined(_CMU_HFRCOCTRL_FREQRANGE_MASK)
AnnaBridge 156:ff21514d8981 1600 CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void);
AnnaBridge 156:ff21514d8981 1601 void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq);
AnnaBridge 156:ff21514d8981 1602 #endif
AnnaBridge 156:ff21514d8981 1603
AnnaBridge 156:ff21514d8981 1604 uint32_t CMU_HFRCOStartupDelayGet(void);
AnnaBridge 156:ff21514d8981 1605 void CMU_HFRCOStartupDelaySet(uint32_t delay);
AnnaBridge 156:ff21514d8981 1606
Anna Bridge 160:5571c4ff569f 1607 #if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK)
Anna Bridge 160:5571c4ff569f 1608 CMU_USHFRCOFreq_TypeDef CMU_USHFRCOBandGet(void);
Anna Bridge 160:5571c4ff569f 1609 void CMU_USHFRCOBandSet(CMU_USHFRCOFreq_TypeDef setFreq);
Anna Bridge 160:5571c4ff569f 1610 #endif
Anna Bridge 160:5571c4ff569f 1611
Anna Bridge 160:5571c4ff569f 1612 #if defined(_CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK)
AnnaBridge 156:ff21514d8981 1613 void CMU_HFXOAutostartEnable(uint32_t userSel,
AnnaBridge 156:ff21514d8981 1614 bool enEM0EM1Start,
AnnaBridge 156:ff21514d8981 1615 bool enEM0EM1StartSel);
AnnaBridge 156:ff21514d8981 1616 #endif
AnnaBridge 156:ff21514d8981 1617
AnnaBridge 156:ff21514d8981 1618 void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit);
AnnaBridge 156:ff21514d8981 1619
AnnaBridge 156:ff21514d8981 1620 uint32_t CMU_LCDClkFDIVGet(void);
AnnaBridge 156:ff21514d8981 1621 void CMU_LCDClkFDIVSet(uint32_t div);
AnnaBridge 156:ff21514d8981 1622 void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit);
AnnaBridge 156:ff21514d8981 1623
AnnaBridge 156:ff21514d8981 1624 void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait);
AnnaBridge 156:ff21514d8981 1625 uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);
AnnaBridge 156:ff21514d8981 1626 void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val);
AnnaBridge 156:ff21514d8981 1627
Anna Bridge 160:5571c4ff569f 1628 #if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK)
AnnaBridge 156:ff21514d8981 1629 bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode);
AnnaBridge 156:ff21514d8981 1630 bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc,
AnnaBridge 156:ff21514d8981 1631 CMU_HFXOTuningMode_TypeDef mode,
AnnaBridge 156:ff21514d8981 1632 bool wait);
AnnaBridge 156:ff21514d8981 1633 #endif
Anna Bridge 160:5571c4ff569f 1634 void CMU_UpdateWaitStates(uint32_t freq, int vscale);
AnnaBridge 156:ff21514d8981 1635
AnnaBridge 156:ff21514d8981 1636 bool CMU_PCNTClockExternalGet(unsigned int instance);
AnnaBridge 156:ff21514d8981 1637 void CMU_PCNTClockExternalSet(unsigned int instance, bool external);
AnnaBridge 156:ff21514d8981 1638
Anna Bridge 160:5571c4ff569f 1639 #if defined(_CMU_USHFRCOCONF_BAND_MASK)
AnnaBridge 156:ff21514d8981 1640 CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void);
AnnaBridge 156:ff21514d8981 1641 void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band);
AnnaBridge 156:ff21514d8981 1642 #endif
Anna Bridge 160:5571c4ff569f 1643 void CMU_UpdateWaitStates(uint32_t freq, int vscale);
AnnaBridge 156:ff21514d8981 1644
Anna Bridge 160:5571c4ff569f 1645 #if defined(CMU_CALCTRL_CONT)
AnnaBridge 156:ff21514d8981 1646 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1647 * @brief
AnnaBridge 156:ff21514d8981 1648 * Configures continuous calibration mode
AnnaBridge 156:ff21514d8981 1649 * @param[in] enable
AnnaBridge 156:ff21514d8981 1650 * If true, enables continuous calibration, if false disables continuous
AnnaBridge 156:ff21514d8981 1651 * calibrartion
AnnaBridge 156:ff21514d8981 1652 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1653 __STATIC_INLINE void CMU_CalibrateCont(bool enable)
AnnaBridge 156:ff21514d8981 1654 {
AnnaBridge 156:ff21514d8981 1655 BUS_RegBitWrite(&(CMU->CALCTRL), _CMU_CALCTRL_CONT_SHIFT, enable);
AnnaBridge 156:ff21514d8981 1656 }
AnnaBridge 156:ff21514d8981 1657 #endif
AnnaBridge 156:ff21514d8981 1658
AnnaBridge 156:ff21514d8981 1659 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1660 * @brief
AnnaBridge 156:ff21514d8981 1661 * Starts calibration
AnnaBridge 156:ff21514d8981 1662 * @note
Anna Bridge 160:5571c4ff569f 1663 * This call is usually invoked after @ref CMU_CalibrateConfig() and possibly
Anna Bridge 160:5571c4ff569f 1664 * @ref CMU_CalibrateCont()
AnnaBridge 156:ff21514d8981 1665 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1666 __STATIC_INLINE void CMU_CalibrateStart(void)
AnnaBridge 156:ff21514d8981 1667 {
AnnaBridge 156:ff21514d8981 1668 CMU->CMD = CMU_CMD_CALSTART;
AnnaBridge 156:ff21514d8981 1669 }
AnnaBridge 156:ff21514d8981 1670
Anna Bridge 160:5571c4ff569f 1671 #if defined(CMU_CMD_CALSTOP)
AnnaBridge 156:ff21514d8981 1672 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1673 * @brief
AnnaBridge 156:ff21514d8981 1674 * Stop the calibration counters
AnnaBridge 156:ff21514d8981 1675 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1676 __STATIC_INLINE void CMU_CalibrateStop(void)
AnnaBridge 156:ff21514d8981 1677 {
AnnaBridge 156:ff21514d8981 1678 CMU->CMD = CMU_CMD_CALSTOP;
AnnaBridge 156:ff21514d8981 1679 }
AnnaBridge 156:ff21514d8981 1680 #endif
AnnaBridge 156:ff21514d8981 1681
AnnaBridge 156:ff21514d8981 1682 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1683 * @brief
AnnaBridge 156:ff21514d8981 1684 * Convert dividend to logarithmic value. Only works for even
AnnaBridge 156:ff21514d8981 1685 * numbers equal to 2^n.
AnnaBridge 156:ff21514d8981 1686 *
AnnaBridge 156:ff21514d8981 1687 * @param[in] div
AnnaBridge 156:ff21514d8981 1688 * Unscaled dividend.
AnnaBridge 156:ff21514d8981 1689 *
AnnaBridge 156:ff21514d8981 1690 * @return
AnnaBridge 156:ff21514d8981 1691 * Logarithm of 2, as used by fixed prescalers.
AnnaBridge 156:ff21514d8981 1692 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1693 __STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div)
AnnaBridge 156:ff21514d8981 1694 {
AnnaBridge 156:ff21514d8981 1695 uint32_t log2;
AnnaBridge 156:ff21514d8981 1696
AnnaBridge 156:ff21514d8981 1697 /* Fixed 2^n prescalers take argument of 32768 or less. */
AnnaBridge 156:ff21514d8981 1698 EFM_ASSERT((div > 0U) && (div <= 32768U));
AnnaBridge 156:ff21514d8981 1699
AnnaBridge 156:ff21514d8981 1700 /* Count leading zeroes and "reverse" result */
AnnaBridge 156:ff21514d8981 1701 log2 = (31U - __CLZ(div));
AnnaBridge 156:ff21514d8981 1702
AnnaBridge 156:ff21514d8981 1703 return log2;
AnnaBridge 156:ff21514d8981 1704 }
AnnaBridge 156:ff21514d8981 1705
Anna Bridge 160:5571c4ff569f 1706 #if defined(CMU_OSCENCMD_DPLLEN)
Anna Bridge 160:5571c4ff569f 1707 /***************************************************************************//**
Anna Bridge 160:5571c4ff569f 1708 * @brief
Anna Bridge 160:5571c4ff569f 1709 * Unlock the DPLL.
Anna Bridge 160:5571c4ff569f 1710 * @note
Anna Bridge 160:5571c4ff569f 1711 * The HFRCO is not turned off.
Anna Bridge 160:5571c4ff569f 1712 ******************************************************************************/
Anna Bridge 160:5571c4ff569f 1713 __STATIC_INLINE void CMU_DPLLUnlock(void)
Anna Bridge 160:5571c4ff569f 1714 {
Anna Bridge 160:5571c4ff569f 1715 CMU->OSCENCMD = CMU_OSCENCMD_DPLLDIS;
Anna Bridge 160:5571c4ff569f 1716 }
Anna Bridge 160:5571c4ff569f 1717 #endif
AnnaBridge 156:ff21514d8981 1718
AnnaBridge 156:ff21514d8981 1719 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1720 * @brief
AnnaBridge 156:ff21514d8981 1721 * Clear one or more pending CMU interrupts.
AnnaBridge 156:ff21514d8981 1722 *
AnnaBridge 156:ff21514d8981 1723 * @param[in] flags
AnnaBridge 156:ff21514d8981 1724 * CMU interrupt sources to clear.
AnnaBridge 156:ff21514d8981 1725 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1726 __STATIC_INLINE void CMU_IntClear(uint32_t flags)
AnnaBridge 156:ff21514d8981 1727 {
AnnaBridge 156:ff21514d8981 1728 CMU->IFC = flags;
AnnaBridge 156:ff21514d8981 1729 }
AnnaBridge 156:ff21514d8981 1730
AnnaBridge 156:ff21514d8981 1731 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1732 * @brief
AnnaBridge 156:ff21514d8981 1733 * Disable one or more CMU interrupts.
AnnaBridge 156:ff21514d8981 1734 *
AnnaBridge 156:ff21514d8981 1735 * @param[in] flags
AnnaBridge 156:ff21514d8981 1736 * CMU interrupt sources to disable.
AnnaBridge 156:ff21514d8981 1737 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1738 __STATIC_INLINE void CMU_IntDisable(uint32_t flags)
AnnaBridge 156:ff21514d8981 1739 {
AnnaBridge 156:ff21514d8981 1740 CMU->IEN &= ~flags;
AnnaBridge 156:ff21514d8981 1741 }
AnnaBridge 156:ff21514d8981 1742
AnnaBridge 156:ff21514d8981 1743 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1744 * @brief
AnnaBridge 156:ff21514d8981 1745 * Enable one or more CMU interrupts.
AnnaBridge 156:ff21514d8981 1746 *
AnnaBridge 156:ff21514d8981 1747 * @note
AnnaBridge 156:ff21514d8981 1748 * Depending on the use, a pending interrupt may already be set prior to
Anna Bridge 160:5571c4ff569f 1749 * enabling the interrupt. Consider using @ref CMU_IntClear() prior to enabling
AnnaBridge 156:ff21514d8981 1750 * if such a pending interrupt should be ignored.
AnnaBridge 156:ff21514d8981 1751 *
AnnaBridge 156:ff21514d8981 1752 * @param[in] flags
AnnaBridge 156:ff21514d8981 1753 * CMU interrupt sources to enable.
AnnaBridge 156:ff21514d8981 1754 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1755 __STATIC_INLINE void CMU_IntEnable(uint32_t flags)
AnnaBridge 156:ff21514d8981 1756 {
AnnaBridge 156:ff21514d8981 1757 CMU->IEN |= flags;
AnnaBridge 156:ff21514d8981 1758 }
AnnaBridge 156:ff21514d8981 1759
AnnaBridge 156:ff21514d8981 1760 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1761 * @brief
AnnaBridge 156:ff21514d8981 1762 * Get pending CMU interrupts.
AnnaBridge 156:ff21514d8981 1763 *
AnnaBridge 156:ff21514d8981 1764 * @return
AnnaBridge 156:ff21514d8981 1765 * CMU interrupt sources pending.
AnnaBridge 156:ff21514d8981 1766 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1767 __STATIC_INLINE uint32_t CMU_IntGet(void)
AnnaBridge 156:ff21514d8981 1768 {
AnnaBridge 156:ff21514d8981 1769 return CMU->IF;
AnnaBridge 156:ff21514d8981 1770 }
AnnaBridge 156:ff21514d8981 1771
AnnaBridge 156:ff21514d8981 1772 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1773 * @brief
AnnaBridge 156:ff21514d8981 1774 * Get enabled and pending CMU interrupt flags.
AnnaBridge 156:ff21514d8981 1775 *
AnnaBridge 156:ff21514d8981 1776 * @details
AnnaBridge 156:ff21514d8981 1777 * Useful for handling more interrupt sources in the same interrupt handler.
AnnaBridge 156:ff21514d8981 1778 *
AnnaBridge 156:ff21514d8981 1779 * @note
AnnaBridge 156:ff21514d8981 1780 * The event bits are not cleared by the use of this function.
AnnaBridge 156:ff21514d8981 1781 *
AnnaBridge 156:ff21514d8981 1782 * @return
AnnaBridge 156:ff21514d8981 1783 * Pending and enabled CMU interrupt sources
AnnaBridge 156:ff21514d8981 1784 * The return value is the bitwise AND of
AnnaBridge 156:ff21514d8981 1785 * - the enabled interrupt sources in CMU_IEN and
AnnaBridge 156:ff21514d8981 1786 * - the pending interrupt flags CMU_IF
AnnaBridge 156:ff21514d8981 1787 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1788 __STATIC_INLINE uint32_t CMU_IntGetEnabled(void)
AnnaBridge 156:ff21514d8981 1789 {
AnnaBridge 156:ff21514d8981 1790 uint32_t ien;
AnnaBridge 156:ff21514d8981 1791
AnnaBridge 156:ff21514d8981 1792 ien = CMU->IEN;
AnnaBridge 156:ff21514d8981 1793 return CMU->IF & ien;
AnnaBridge 156:ff21514d8981 1794 }
AnnaBridge 156:ff21514d8981 1795
AnnaBridge 156:ff21514d8981 1796 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 1797 * @brief
AnnaBridge 156:ff21514d8981 1798 * Set one or more pending CMU interrupts.
AnnaBridge 156:ff21514d8981 1799 *
AnnaBridge 156:ff21514d8981 1800 * @param[in] flags
AnnaBridge 156:ff21514d8981 1801 * CMU interrupt sources to set to pending.
AnnaBridge 156:ff21514d8981 1802 *****************************************************************************/
AnnaBridge 156:ff21514d8981 1803 __STATIC_INLINE void CMU_IntSet(uint32_t flags)
AnnaBridge 156:ff21514d8981 1804 {
AnnaBridge 156:ff21514d8981 1805 CMU->IFS = flags;
AnnaBridge 156:ff21514d8981 1806 }
AnnaBridge 156:ff21514d8981 1807
AnnaBridge 156:ff21514d8981 1808 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1809 * @brief
AnnaBridge 156:ff21514d8981 1810 * Lock the CMU in order to protect some of its registers against unintended
AnnaBridge 156:ff21514d8981 1811 * modification.
AnnaBridge 156:ff21514d8981 1812 *
AnnaBridge 156:ff21514d8981 1813 * @details
AnnaBridge 156:ff21514d8981 1814 * Please refer to the reference manual for CMU registers that will be
AnnaBridge 156:ff21514d8981 1815 * locked.
AnnaBridge 156:ff21514d8981 1816 *
AnnaBridge 156:ff21514d8981 1817 * @note
AnnaBridge 156:ff21514d8981 1818 * If locking the CMU registers, they must be unlocked prior to using any
AnnaBridge 156:ff21514d8981 1819 * CMU API functions modifying CMU registers protected by the lock.
AnnaBridge 156:ff21514d8981 1820 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1821 __STATIC_INLINE void CMU_Lock(void)
AnnaBridge 156:ff21514d8981 1822 {
AnnaBridge 156:ff21514d8981 1823 CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
AnnaBridge 156:ff21514d8981 1824 }
AnnaBridge 156:ff21514d8981 1825
AnnaBridge 156:ff21514d8981 1826 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1827 * @brief
AnnaBridge 156:ff21514d8981 1828 * Convert logarithm of 2 prescaler to division factor.
AnnaBridge 156:ff21514d8981 1829 *
AnnaBridge 156:ff21514d8981 1830 * @param[in] log2
AnnaBridge 156:ff21514d8981 1831 * Logarithm of 2, as used by fixed prescalers.
AnnaBridge 156:ff21514d8981 1832 *
AnnaBridge 156:ff21514d8981 1833 * @return
AnnaBridge 156:ff21514d8981 1834 * Dividend.
AnnaBridge 156:ff21514d8981 1835 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1836 __STATIC_INLINE uint32_t CMU_Log2ToDiv(uint32_t log2)
AnnaBridge 156:ff21514d8981 1837 {
AnnaBridge 156:ff21514d8981 1838 return 1 << log2;
AnnaBridge 156:ff21514d8981 1839 }
AnnaBridge 156:ff21514d8981 1840
Anna Bridge 160:5571c4ff569f 1841 #if defined(_SILICON_LABS_32B_SERIES_1)
AnnaBridge 156:ff21514d8981 1842 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1843 * @brief
AnnaBridge 156:ff21514d8981 1844 * Convert prescaler dividend to logarithmic value. Only works for even
AnnaBridge 156:ff21514d8981 1845 * numbers equal to 2^n.
AnnaBridge 156:ff21514d8981 1846 *
AnnaBridge 156:ff21514d8981 1847 * @param[in] presc
AnnaBridge 156:ff21514d8981 1848 * Unscaled dividend (dividend = presc + 1).
AnnaBridge 156:ff21514d8981 1849 *
AnnaBridge 156:ff21514d8981 1850 * @return
AnnaBridge 156:ff21514d8981 1851 * Logarithm of 2, as used by fixed 2^n prescalers.
AnnaBridge 156:ff21514d8981 1852 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1853 __STATIC_INLINE uint32_t CMU_PrescToLog2(CMU_ClkPresc_TypeDef presc)
AnnaBridge 156:ff21514d8981 1854 {
AnnaBridge 156:ff21514d8981 1855 uint32_t log2;
AnnaBridge 156:ff21514d8981 1856
AnnaBridge 156:ff21514d8981 1857 /* Integer prescalers take argument less than 32768. */
AnnaBridge 156:ff21514d8981 1858 EFM_ASSERT(presc < 32768U);
AnnaBridge 156:ff21514d8981 1859
AnnaBridge 156:ff21514d8981 1860 /* Count leading zeroes and "reverse" result */
AnnaBridge 156:ff21514d8981 1861 log2 = (31U - __CLZ(presc + 1));
AnnaBridge 156:ff21514d8981 1862
AnnaBridge 156:ff21514d8981 1863 /* Check that presc is a 2^n number */
AnnaBridge 156:ff21514d8981 1864 EFM_ASSERT(presc == (CMU_Log2ToDiv(log2) - 1));
AnnaBridge 156:ff21514d8981 1865
AnnaBridge 156:ff21514d8981 1866 return log2;
AnnaBridge 156:ff21514d8981 1867 }
AnnaBridge 156:ff21514d8981 1868 #endif
AnnaBridge 156:ff21514d8981 1869
AnnaBridge 156:ff21514d8981 1870 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1871 * @brief
AnnaBridge 156:ff21514d8981 1872 * Unlock the CMU so that writing to locked registers again is possible.
AnnaBridge 156:ff21514d8981 1873 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1874 __STATIC_INLINE void CMU_Unlock(void)
AnnaBridge 156:ff21514d8981 1875 {
AnnaBridge 156:ff21514d8981 1876 CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
AnnaBridge 156:ff21514d8981 1877 }
AnnaBridge 156:ff21514d8981 1878
Anna Bridge 160:5571c4ff569f 1879 #if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK)
AnnaBridge 156:ff21514d8981 1880 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1881 * @brief
AnnaBridge 156:ff21514d8981 1882 * Get current HFRCO frequency.
AnnaBridge 156:ff21514d8981 1883 *
AnnaBridge 156:ff21514d8981 1884 * @deprecated
AnnaBridge 156:ff21514d8981 1885 * Deprecated function. New code should use @ref CMU_HFRCOBandGet().
AnnaBridge 156:ff21514d8981 1886 *
AnnaBridge 156:ff21514d8981 1887 * @return
AnnaBridge 156:ff21514d8981 1888 * HFRCO frequency
AnnaBridge 156:ff21514d8981 1889 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1890 __STATIC_INLINE CMU_HFRCOFreq_TypeDef CMU_HFRCOFreqGet(void)
AnnaBridge 156:ff21514d8981 1891 {
AnnaBridge 156:ff21514d8981 1892 return CMU_HFRCOBandGet();
AnnaBridge 156:ff21514d8981 1893 }
AnnaBridge 156:ff21514d8981 1894
AnnaBridge 156:ff21514d8981 1895 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1896 * @brief
AnnaBridge 156:ff21514d8981 1897 * Set HFRCO calibration for the selected target frequency
AnnaBridge 156:ff21514d8981 1898 *
AnnaBridge 156:ff21514d8981 1899 * @deprecated
AnnaBridge 156:ff21514d8981 1900 * Deprecated function. New code should use @ref CMU_HFRCOBandSet().
AnnaBridge 156:ff21514d8981 1901 *
AnnaBridge 156:ff21514d8981 1902 * @param[in] setFreq
AnnaBridge 156:ff21514d8981 1903 * HFRCO frequency to set
AnnaBridge 156:ff21514d8981 1904 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1905 __STATIC_INLINE void CMU_HFRCOFreqSet(CMU_HFRCOFreq_TypeDef setFreq)
AnnaBridge 156:ff21514d8981 1906 {
AnnaBridge 156:ff21514d8981 1907 CMU_HFRCOBandSet(setFreq);
AnnaBridge 156:ff21514d8981 1908 }
AnnaBridge 156:ff21514d8981 1909 #endif
AnnaBridge 156:ff21514d8981 1910
Anna Bridge 160:5571c4ff569f 1911 #if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK)
AnnaBridge 156:ff21514d8981 1912 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1913 * @brief
AnnaBridge 156:ff21514d8981 1914 * Get current AUXHFRCO frequency.
AnnaBridge 156:ff21514d8981 1915 *
AnnaBridge 156:ff21514d8981 1916 * @deprecated
AnnaBridge 156:ff21514d8981 1917 * Deprecated function. New code should use @ref CMU_AUXHFRCOBandGet().
AnnaBridge 156:ff21514d8981 1918 *
AnnaBridge 156:ff21514d8981 1919 * @return
AnnaBridge 156:ff21514d8981 1920 * AUXHFRCO frequency
AnnaBridge 156:ff21514d8981 1921 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1922 __STATIC_INLINE CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOFreqGet(void)
AnnaBridge 156:ff21514d8981 1923 {
AnnaBridge 156:ff21514d8981 1924 return CMU_AUXHFRCOBandGet();
AnnaBridge 156:ff21514d8981 1925 }
AnnaBridge 156:ff21514d8981 1926
AnnaBridge 156:ff21514d8981 1927 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1928 * @brief
AnnaBridge 156:ff21514d8981 1929 * Set AUXHFRCO calibration for the selected target frequency
AnnaBridge 156:ff21514d8981 1930 *
AnnaBridge 156:ff21514d8981 1931 * @deprecated
AnnaBridge 156:ff21514d8981 1932 * Deprecated function. New code should use @ref CMU_AUXHFRCOBandSet().
AnnaBridge 156:ff21514d8981 1933 *
AnnaBridge 156:ff21514d8981 1934 * @param[in] setFreq
AnnaBridge 156:ff21514d8981 1935 * AUXHFRCO frequency to set
AnnaBridge 156:ff21514d8981 1936 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1937 __STATIC_INLINE void CMU_AUXHFRCOFreqSet(CMU_AUXHFRCOFreq_TypeDef setFreq)
AnnaBridge 156:ff21514d8981 1938 {
AnnaBridge 156:ff21514d8981 1939 CMU_AUXHFRCOBandSet(setFreq);
AnnaBridge 156:ff21514d8981 1940 }
AnnaBridge 156:ff21514d8981 1941 #endif
AnnaBridge 156:ff21514d8981 1942
AnnaBridge 156:ff21514d8981 1943 /** @} (end addtogroup CMU) */
AnnaBridge 156:ff21514d8981 1944 /** @} (end addtogroup emlib) */
AnnaBridge 156:ff21514d8981 1945
AnnaBridge 156:ff21514d8981 1946 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 1947 }
AnnaBridge 156:ff21514d8981 1948 #endif
AnnaBridge 156:ff21514d8981 1949
AnnaBridge 156:ff21514d8981 1950 #endif /* defined( CMU_PRESENT ) */
AnnaBridge 156:ff21514d8981 1951 #endif /* EM_CMU_H */