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TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_STD/em_qspi.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_EFM32ZG_STK3200/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_qspi.h@160:5571c4ff569f
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Anna Bridge |
160:5571c4ff569f | 1 | /***************************************************************************//** |
Anna Bridge |
160:5571c4ff569f | 2 | * @file em_qspi.h |
Anna Bridge |
160:5571c4ff569f | 3 | * @brief QSPI Octal-SPI Flash Controller API |
Anna Bridge |
160:5571c4ff569f | 4 | * @version 5.3.3 |
Anna Bridge |
160:5571c4ff569f | 5 | ******************************************************************************* |
Anna Bridge |
160:5571c4ff569f | 6 | * # License |
Anna Bridge |
160:5571c4ff569f | 7 | * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b> |
Anna Bridge |
160:5571c4ff569f | 8 | ******************************************************************************* |
Anna Bridge |
160:5571c4ff569f | 9 | * |
Anna Bridge |
160:5571c4ff569f | 10 | * Permission is granted to anyone to use this software for any purpose, |
Anna Bridge |
160:5571c4ff569f | 11 | * including commercial applications, and to alter it and redistribute it |
Anna Bridge |
160:5571c4ff569f | 12 | * freely, subject to the following restrictions: |
Anna Bridge |
160:5571c4ff569f | 13 | * |
Anna Bridge |
160:5571c4ff569f | 14 | * 1. The origin of this software must not be misrepresented; you must not |
Anna Bridge |
160:5571c4ff569f | 15 | * claim that you wrote the original software. |
Anna Bridge |
160:5571c4ff569f | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
Anna Bridge |
160:5571c4ff569f | 17 | * misrepresented as being the original software. |
Anna Bridge |
160:5571c4ff569f | 18 | * 3. This notice may not be removed or altered from any source distribution. |
Anna Bridge |
160:5571c4ff569f | 19 | * |
Anna Bridge |
160:5571c4ff569f | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no |
Anna Bridge |
160:5571c4ff569f | 21 | * obligation to support this Software. Silicon Labs is providing the |
Anna Bridge |
160:5571c4ff569f | 22 | * Software "AS IS", with no express or implied warranties of any kind, |
Anna Bridge |
160:5571c4ff569f | 23 | * including, but not limited to, any implied warranties of merchantability |
Anna Bridge |
160:5571c4ff569f | 24 | * or fitness for any particular purpose or warranties against infringement |
Anna Bridge |
160:5571c4ff569f | 25 | * of any proprietary rights of a third party. |
Anna Bridge |
160:5571c4ff569f | 26 | * |
Anna Bridge |
160:5571c4ff569f | 27 | * Silicon Labs will not be liable for any consequential, incidental, or |
Anna Bridge |
160:5571c4ff569f | 28 | * special damages, or any other relief, or for any claim by any third party, |
Anna Bridge |
160:5571c4ff569f | 29 | * arising from your use of this Software. |
Anna Bridge |
160:5571c4ff569f | 30 | * |
Anna Bridge |
160:5571c4ff569f | 31 | ******************************************************************************/ |
Anna Bridge |
160:5571c4ff569f | 32 | |
Anna Bridge |
160:5571c4ff569f | 33 | #ifndef EM_QSPI_H |
Anna Bridge |
160:5571c4ff569f | 34 | #define EM_QSPI_H |
Anna Bridge |
160:5571c4ff569f | 35 | |
Anna Bridge |
160:5571c4ff569f | 36 | #include "em_device.h" |
Anna Bridge |
160:5571c4ff569f | 37 | #if defined(QSPI_COUNT) && (QSPI_COUNT > 0) |
Anna Bridge |
160:5571c4ff569f | 38 | |
Anna Bridge |
160:5571c4ff569f | 39 | #ifdef __cplusplus |
Anna Bridge |
160:5571c4ff569f | 40 | extern "C" { |
Anna Bridge |
160:5571c4ff569f | 41 | #endif |
Anna Bridge |
160:5571c4ff569f | 42 | |
Anna Bridge |
160:5571c4ff569f | 43 | #include "em_bus.h" |
Anna Bridge |
160:5571c4ff569f | 44 | #include <stdbool.h> |
Anna Bridge |
160:5571c4ff569f | 45 | |
Anna Bridge |
160:5571c4ff569f | 46 | /***************************************************************************//** |
Anna Bridge |
160:5571c4ff569f | 47 | * @addtogroup emlib |
Anna Bridge |
160:5571c4ff569f | 48 | * @{ |
Anna Bridge |
160:5571c4ff569f | 49 | ******************************************************************************/ |
Anna Bridge |
160:5571c4ff569f | 50 | |
Anna Bridge |
160:5571c4ff569f | 51 | /***************************************************************************//** |
Anna Bridge |
160:5571c4ff569f | 52 | * @addtogroup QSPI |
Anna Bridge |
160:5571c4ff569f | 53 | * @{ |
Anna Bridge |
160:5571c4ff569f | 54 | ******************************************************************************/ |
Anna Bridge |
160:5571c4ff569f | 55 | |
Anna Bridge |
160:5571c4ff569f | 56 | /******************************************************************************* |
Anna Bridge |
160:5571c4ff569f | 57 | ******************************* DEFINES *********************************** |
Anna Bridge |
160:5571c4ff569f | 58 | ******************************************************************************/ |
Anna Bridge |
160:5571c4ff569f | 59 | |
Anna Bridge |
160:5571c4ff569f | 60 | /******************************************************************************* |
Anna Bridge |
160:5571c4ff569f | 61 | ******************************** ENUMS ************************************ |
Anna Bridge |
160:5571c4ff569f | 62 | ******************************************************************************/ |
Anna Bridge |
160:5571c4ff569f | 63 | |
Anna Bridge |
160:5571c4ff569f | 64 | /** Transfer type. */ |
Anna Bridge |
160:5571c4ff569f | 65 | typedef enum { |
Anna Bridge |
160:5571c4ff569f | 66 | /** Single IO mode. DQ0 used for output and DQ1 as input. */ |
Anna Bridge |
160:5571c4ff569f | 67 | qspiTransferSingle = 0, |
Anna Bridge |
160:5571c4ff569f | 68 | |
Anna Bridge |
160:5571c4ff569f | 69 | /** Dual I/O transfer. DQ0 and DQ1 are used as both inputs and outputs. */ |
Anna Bridge |
160:5571c4ff569f | 70 | qspiTransferDual = 1, |
Anna Bridge |
160:5571c4ff569f | 71 | |
Anna Bridge |
160:5571c4ff569f | 72 | /** Quad I/O transfer. DQ0, DQ1, DQ2 and DQ3 are used as both inputs and outputs. */ |
Anna Bridge |
160:5571c4ff569f | 73 | qspiTransferQuad = 2, |
Anna Bridge |
160:5571c4ff569f | 74 | |
Anna Bridge |
160:5571c4ff569f | 75 | /** Octal I/O transfer. DQ[7:0] are used as both inputs and outputs. */ |
Anna Bridge |
160:5571c4ff569f | 76 | qspiTransferOctal = 3 |
Anna Bridge |
160:5571c4ff569f | 77 | } QSPI_TransferType_TypeDef; |
Anna Bridge |
160:5571c4ff569f | 78 | |
Anna Bridge |
160:5571c4ff569f | 79 | /******************************************************************************* |
Anna Bridge |
160:5571c4ff569f | 80 | ******************************* STRUCTS *********************************** |
Anna Bridge |
160:5571c4ff569f | 81 | ******************************************************************************/ |
Anna Bridge |
160:5571c4ff569f | 82 | |
Anna Bridge |
160:5571c4ff569f | 83 | /** QSPI Device Read Instruction Configuration structure. */ |
Anna Bridge |
160:5571c4ff569f | 84 | typedef struct { |
Anna Bridge |
160:5571c4ff569f | 85 | /** Read opcode in non-xip mode. */ |
Anna Bridge |
160:5571c4ff569f | 86 | uint8_t opCode; |
Anna Bridge |
160:5571c4ff569f | 87 | |
Anna Bridge |
160:5571c4ff569f | 88 | /** Number of dummy read clock cycles. */ |
Anna Bridge |
160:5571c4ff569f | 89 | uint8_t dummyCycles; |
Anna Bridge |
160:5571c4ff569f | 90 | |
Anna Bridge |
160:5571c4ff569f | 91 | /** Transfer type used for address. */ |
Anna Bridge |
160:5571c4ff569f | 92 | QSPI_TransferType_TypeDef addrTransfer; |
Anna Bridge |
160:5571c4ff569f | 93 | |
Anna Bridge |
160:5571c4ff569f | 94 | /** Transfer type used for data. */ |
Anna Bridge |
160:5571c4ff569f | 95 | QSPI_TransferType_TypeDef dataTransfer; |
Anna Bridge |
160:5571c4ff569f | 96 | |
Anna Bridge |
160:5571c4ff569f | 97 | /** Transfer type used for instruction. */ |
Anna Bridge |
160:5571c4ff569f | 98 | QSPI_TransferType_TypeDef instTransfer; |
Anna Bridge |
160:5571c4ff569f | 99 | } QSPI_ReadConfig_TypeDef; |
Anna Bridge |
160:5571c4ff569f | 100 | |
Anna Bridge |
160:5571c4ff569f | 101 | /** Default read configuration structure. */ |
Anna Bridge |
160:5571c4ff569f | 102 | #define QSPI_READCONFIG_DEFAULT \ |
Anna Bridge |
160:5571c4ff569f | 103 | { \ |
Anna Bridge |
160:5571c4ff569f | 104 | 0x03, /* 0x03 is the standard read opcode. */ \ |
Anna Bridge |
160:5571c4ff569f | 105 | 0, /* 0 dummy cycles. */ \ |
Anna Bridge |
160:5571c4ff569f | 106 | qspiTransferSingle, /* Single I/O mode. */ \ |
Anna Bridge |
160:5571c4ff569f | 107 | qspiTransferSingle, /* Single I/O mode. */ \ |
Anna Bridge |
160:5571c4ff569f | 108 | qspiTransferSingle, /* Single I/O mode. */ \ |
Anna Bridge |
160:5571c4ff569f | 109 | } |
Anna Bridge |
160:5571c4ff569f | 110 | |
Anna Bridge |
160:5571c4ff569f | 111 | /** QSPI Device Write Instruction Configuration structure. */ |
Anna Bridge |
160:5571c4ff569f | 112 | typedef struct { |
Anna Bridge |
160:5571c4ff569f | 113 | /** Write opcode. */ |
Anna Bridge |
160:5571c4ff569f | 114 | uint8_t opCode; |
Anna Bridge |
160:5571c4ff569f | 115 | |
Anna Bridge |
160:5571c4ff569f | 116 | /** Number of dummy read clock cycles. */ |
Anna Bridge |
160:5571c4ff569f | 117 | uint8_t dummyCycles; |
Anna Bridge |
160:5571c4ff569f | 118 | |
Anna Bridge |
160:5571c4ff569f | 119 | /** Transfer type used for address. */ |
Anna Bridge |
160:5571c4ff569f | 120 | QSPI_TransferType_TypeDef addrTransfer; |
Anna Bridge |
160:5571c4ff569f | 121 | |
Anna Bridge |
160:5571c4ff569f | 122 | /** Transfer type used for data. */ |
Anna Bridge |
160:5571c4ff569f | 123 | QSPI_TransferType_TypeDef dataTransfer; |
Anna Bridge |
160:5571c4ff569f | 124 | |
Anna Bridge |
160:5571c4ff569f | 125 | /** |
Anna Bridge |
160:5571c4ff569f | 126 | * @brief |
Anna Bridge |
160:5571c4ff569f | 127 | * Enable/disable automatic issuing of WEL (Write Enable Latch) |
Anna Bridge |
160:5571c4ff569f | 128 | * command before a write operation. |
Anna Bridge |
160:5571c4ff569f | 129 | * |
Anna Bridge |
160:5571c4ff569f | 130 | * @details |
Anna Bridge |
160:5571c4ff569f | 131 | * When writing to a flash device the write enable latch (WEL) |
Anna Bridge |
160:5571c4ff569f | 132 | * within the flash device itself must be high before a write sequence can be |
Anna Bridge |
160:5571c4ff569f | 133 | * issued. The QSPI peripheral can automatically issue the write enable latch |
Anna Bridge |
160:5571c4ff569f | 134 | * command before triggering a write sequence. The command used for enabling |
Anna Bridge |
160:5571c4ff569f | 135 | * the write enable latch is WREN (0x06) and is common between devices. */ |
Anna Bridge |
160:5571c4ff569f | 136 | bool autoWEL; |
Anna Bridge |
160:5571c4ff569f | 137 | } QSPI_WriteConfig_TypeDef; |
Anna Bridge |
160:5571c4ff569f | 138 | |
Anna Bridge |
160:5571c4ff569f | 139 | /** Default write configuration structure. */ |
Anna Bridge |
160:5571c4ff569f | 140 | #define QSPI_WRITECONFIG_DEFAULT \ |
Anna Bridge |
160:5571c4ff569f | 141 | { \ |
Anna Bridge |
160:5571c4ff569f | 142 | 0x02, /* 0x02 is the standard write opcode. */ \ |
Anna Bridge |
160:5571c4ff569f | 143 | 0, /* 0 dummy cycles. */ \ |
Anna Bridge |
160:5571c4ff569f | 144 | qspiTransferSingle, /* Single I/O mode. */ \ |
Anna Bridge |
160:5571c4ff569f | 145 | qspiTransferSingle, /* Single I/O mode. */ \ |
Anna Bridge |
160:5571c4ff569f | 146 | true, /* Send WEL command automatically. */ \ |
Anna Bridge |
160:5571c4ff569f | 147 | } |
Anna Bridge |
160:5571c4ff569f | 148 | |
Anna Bridge |
160:5571c4ff569f | 149 | /** QSPI Device Delay Configuration structure. */ |
Anna Bridge |
160:5571c4ff569f | 150 | typedef struct { |
Anna Bridge |
160:5571c4ff569f | 151 | /** The minimal delay to keep the chip select line de-asserted between |
Anna Bridge |
160:5571c4ff569f | 152 | * two transactions. */ |
Anna Bridge |
160:5571c4ff569f | 153 | uint8_t deassert; |
Anna Bridge |
160:5571c4ff569f | 154 | |
Anna Bridge |
160:5571c4ff569f | 155 | /** Delay between one chip select being de-activated and the |
Anna Bridge |
160:5571c4ff569f | 156 | * activation of another. */ |
Anna Bridge |
160:5571c4ff569f | 157 | uint8_t deviceSwitch; |
Anna Bridge |
160:5571c4ff569f | 158 | |
Anna Bridge |
160:5571c4ff569f | 159 | /** Delay between last bit and chip select de-assert. */ |
Anna Bridge |
160:5571c4ff569f | 160 | uint8_t lastBit; |
Anna Bridge |
160:5571c4ff569f | 161 | |
Anna Bridge |
160:5571c4ff569f | 162 | /** Delay chip select assert and first bit in a transaction. */ |
Anna Bridge |
160:5571c4ff569f | 163 | uint8_t firstBit; |
Anna Bridge |
160:5571c4ff569f | 164 | } QSPI_DelayConfig_TypeDef; |
Anna Bridge |
160:5571c4ff569f | 165 | |
Anna Bridge |
160:5571c4ff569f | 166 | /** Defines command to be executed using STIG mechanism. */ |
Anna Bridge |
160:5571c4ff569f | 167 | typedef struct { |
Anna Bridge |
160:5571c4ff569f | 168 | /** command op-code */ |
Anna Bridge |
160:5571c4ff569f | 169 | uint8_t cmdOpcode; |
Anna Bridge |
160:5571c4ff569f | 170 | /** Number of Read Data Bytes */ |
Anna Bridge |
160:5571c4ff569f | 171 | uint16_t readDataSize; |
Anna Bridge |
160:5571c4ff569f | 172 | /** Number of Address Bytes */ |
Anna Bridge |
160:5571c4ff569f | 173 | uint8_t addrSize; |
Anna Bridge |
160:5571c4ff569f | 174 | /** Number of Write Data Bytes */ |
Anna Bridge |
160:5571c4ff569f | 175 | uint8_t writeDataSize; |
Anna Bridge |
160:5571c4ff569f | 176 | /** Number of dummy cycles */ |
Anna Bridge |
160:5571c4ff569f | 177 | uint8_t dummyCycles; |
Anna Bridge |
160:5571c4ff569f | 178 | /** Mode Bit Configuration register are sent following the address bytes. */ |
Anna Bridge |
160:5571c4ff569f | 179 | bool modeBitEnable; |
Anna Bridge |
160:5571c4ff569f | 180 | /** flash command address */ |
Anna Bridge |
160:5571c4ff569f | 181 | uint32_t address; |
Anna Bridge |
160:5571c4ff569f | 182 | /** buffer for read data */ |
Anna Bridge |
160:5571c4ff569f | 183 | void * readBuffer; |
Anna Bridge |
160:5571c4ff569f | 184 | /** buffer with data to write */ |
Anna Bridge |
160:5571c4ff569f | 185 | void * writeBuffer; |
Anna Bridge |
160:5571c4ff569f | 186 | } QSPI_StigCmd_TypeDef; |
Anna Bridge |
160:5571c4ff569f | 187 | |
Anna Bridge |
160:5571c4ff569f | 188 | /** QSPI initialization structure. */ |
Anna Bridge |
160:5571c4ff569f | 189 | typedef struct { |
Anna Bridge |
160:5571c4ff569f | 190 | /** Enable/disable Quad SPI when initialization is completed. */ |
Anna Bridge |
160:5571c4ff569f | 191 | bool enable; |
Anna Bridge |
160:5571c4ff569f | 192 | |
Anna Bridge |
160:5571c4ff569f | 193 | /** |
Anna Bridge |
160:5571c4ff569f | 194 | * Master mode baude rate divisor. Values can be even numbers in the range |
Anna Bridge |
160:5571c4ff569f | 195 | * [2-32] inclusive. */ |
Anna Bridge |
160:5571c4ff569f | 196 | uint8_t divisor; |
Anna Bridge |
160:5571c4ff569f | 197 | } QSPI_Init_TypeDef; |
Anna Bridge |
160:5571c4ff569f | 198 | |
Anna Bridge |
160:5571c4ff569f | 199 | /** Default configuration for QSPI_Init_TypeDef structure. */ |
Anna Bridge |
160:5571c4ff569f | 200 | #define QSPI_INIT_DEFAULT \ |
Anna Bridge |
160:5571c4ff569f | 201 | { \ |
Anna Bridge |
160:5571c4ff569f | 202 | true, /* Enable Quad SPI. */ \ |
Anna Bridge |
160:5571c4ff569f | 203 | 32, /* Divide QSPI clock by 32. */ \ |
Anna Bridge |
160:5571c4ff569f | 204 | } |
Anna Bridge |
160:5571c4ff569f | 205 | |
Anna Bridge |
160:5571c4ff569f | 206 | /******************************************************************************* |
Anna Bridge |
160:5571c4ff569f | 207 | ****************************** PROTOTYPES ********************************* |
Anna Bridge |
160:5571c4ff569f | 208 | ******************************************************************************/ |
Anna Bridge |
160:5571c4ff569f | 209 | |
Anna Bridge |
160:5571c4ff569f | 210 | void QSPI_Init(QSPI_TypeDef * qspi, const QSPI_Init_TypeDef * init); |
Anna Bridge |
160:5571c4ff569f | 211 | void QSPI_ReadConfig(QSPI_TypeDef * qspi, const QSPI_ReadConfig_TypeDef * config); |
Anna Bridge |
160:5571c4ff569f | 212 | void QSPI_WriteConfig(QSPI_TypeDef * qspi, const QSPI_WriteConfig_TypeDef * config); |
Anna Bridge |
160:5571c4ff569f | 213 | void QSPI_ExecStigCmd(QSPI_TypeDef * qspi, const QSPI_StigCmd_TypeDef * stigCmd); |
Anna Bridge |
160:5571c4ff569f | 214 | |
Anna Bridge |
160:5571c4ff569f | 215 | /***************************************************************************//** |
Anna Bridge |
160:5571c4ff569f | 216 | * @brief |
Anna Bridge |
160:5571c4ff569f | 217 | * Wait for the QSPI to go into idle state. |
Anna Bridge |
160:5571c4ff569f | 218 | * |
Anna Bridge |
160:5571c4ff569f | 219 | * @param[in] qspi |
Anna Bridge |
160:5571c4ff569f | 220 | * Pointer to QSPI peripheral register block. |
Anna Bridge |
160:5571c4ff569f | 221 | ******************************************************************************/ |
Anna Bridge |
160:5571c4ff569f | 222 | __STATIC_INLINE void QSPI_WaitForIdle(QSPI_TypeDef * qspi) |
Anna Bridge |
160:5571c4ff569f | 223 | { |
Anna Bridge |
160:5571c4ff569f | 224 | while ((qspi->CONFIG & _QSPI_CONFIG_IDLE_MASK) == 0) |
Anna Bridge |
160:5571c4ff569f | 225 | ; |
Anna Bridge |
160:5571c4ff569f | 226 | } |
Anna Bridge |
160:5571c4ff569f | 227 | |
Anna Bridge |
160:5571c4ff569f | 228 | /***************************************************************************//** |
Anna Bridge |
160:5571c4ff569f | 229 | * @brief |
Anna Bridge |
160:5571c4ff569f | 230 | * Get the fill level of the write partition of the QSPI internal SRAM. |
Anna Bridge |
160:5571c4ff569f | 231 | * |
Anna Bridge |
160:5571c4ff569f | 232 | * @param[in] qspi |
Anna Bridge |
160:5571c4ff569f | 233 | * Pointer to QSPI peripheral register block. |
Anna Bridge |
160:5571c4ff569f | 234 | * |
Anna Bridge |
160:5571c4ff569f | 235 | * @return |
Anna Bridge |
160:5571c4ff569f | 236 | * SRAM fill level of the write partition. The value is the number of 4 byte |
Anna Bridge |
160:5571c4ff569f | 237 | * words in the write partition. |
Anna Bridge |
160:5571c4ff569f | 238 | ******************************************************************************/ |
Anna Bridge |
160:5571c4ff569f | 239 | __STATIC_INLINE uint16_t QSPI_GetWriteLevel(QSPI_TypeDef * qspi) |
Anna Bridge |
160:5571c4ff569f | 240 | { |
Anna Bridge |
160:5571c4ff569f | 241 | return (qspi->SRAMFILL & _QSPI_SRAMFILL_SRAMFILLINDACWRITE_MASK) |
Anna Bridge |
160:5571c4ff569f | 242 | >> _QSPI_SRAMFILL_SRAMFILLINDACWRITE_SHIFT; |
Anna Bridge |
160:5571c4ff569f | 243 | } |
Anna Bridge |
160:5571c4ff569f | 244 | |
Anna Bridge |
160:5571c4ff569f | 245 | /***************************************************************************//** |
Anna Bridge |
160:5571c4ff569f | 246 | * @brief |
Anna Bridge |
160:5571c4ff569f | 247 | * Get the fill level of the read partition of the QSPI internal SRAM. |
Anna Bridge |
160:5571c4ff569f | 248 | * |
Anna Bridge |
160:5571c4ff569f | 249 | * @param[in] qspi |
Anna Bridge |
160:5571c4ff569f | 250 | * Pointer to QSPI peripheral register block. |
Anna Bridge |
160:5571c4ff569f | 251 | * |
Anna Bridge |
160:5571c4ff569f | 252 | * @return |
Anna Bridge |
160:5571c4ff569f | 253 | * SRAM fill level of the read partition. The value is the number of 4 byte |
Anna Bridge |
160:5571c4ff569f | 254 | * words in the read partition. |
Anna Bridge |
160:5571c4ff569f | 255 | ******************************************************************************/ |
Anna Bridge |
160:5571c4ff569f | 256 | __STATIC_INLINE uint16_t QSPI_GetReadLevel(QSPI_TypeDef * qspi) |
Anna Bridge |
160:5571c4ff569f | 257 | { |
Anna Bridge |
160:5571c4ff569f | 258 | return (qspi->SRAMFILL & _QSPI_SRAMFILL_SRAMFILLINDACREAD_MASK) |
Anna Bridge |
160:5571c4ff569f | 259 | >> _QSPI_SRAMFILL_SRAMFILLINDACREAD_SHIFT; |
Anna Bridge |
160:5571c4ff569f | 260 | } |
Anna Bridge |
160:5571c4ff569f | 261 | |
Anna Bridge |
160:5571c4ff569f | 262 | /***************************************************************************//** |
Anna Bridge |
160:5571c4ff569f | 263 | * @brief |
Anna Bridge |
160:5571c4ff569f | 264 | * Enable/disable Quad SPI. |
Anna Bridge |
160:5571c4ff569f | 265 | * |
Anna Bridge |
160:5571c4ff569f | 266 | * @param[in] qspi |
Anna Bridge |
160:5571c4ff569f | 267 | * Pointer to QSPI peripheral register block. |
Anna Bridge |
160:5571c4ff569f | 268 | * |
Anna Bridge |
160:5571c4ff569f | 269 | * @param[in] enable |
Anna Bridge |
160:5571c4ff569f | 270 | * true to enable quad spi, false to disable quad spi. |
Anna Bridge |
160:5571c4ff569f | 271 | ******************************************************************************/ |
Anna Bridge |
160:5571c4ff569f | 272 | __STATIC_INLINE void QSPI_Enable(QSPI_TypeDef * qspi, bool enable) |
Anna Bridge |
160:5571c4ff569f | 273 | { |
Anna Bridge |
160:5571c4ff569f | 274 | BUS_RegBitWrite(&qspi->CONFIG, _QSPI_CONFIG_ENBSPI_SHIFT, enable ? 1 : 0); |
Anna Bridge |
160:5571c4ff569f | 275 | } |
Anna Bridge |
160:5571c4ff569f | 276 | |
Anna Bridge |
160:5571c4ff569f | 277 | /***************************************************************************//** |
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160:5571c4ff569f | 278 | * @brief |
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160:5571c4ff569f | 279 | * Get the current interrupt flags. |
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160:5571c4ff569f | 280 | * |
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160:5571c4ff569f | 281 | * @param[in] qspi |
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160:5571c4ff569f | 282 | * Pointer to QSPI peripheral register block. |
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160:5571c4ff569f | 283 | * |
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160:5571c4ff569f | 284 | * @return |
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160:5571c4ff569f | 285 | * This functions returns the current interrupt flags that are set. |
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160:5571c4ff569f | 286 | ******************************************************************************/ |
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160:5571c4ff569f | 287 | __STATIC_INLINE uint32_t QSPI_IntGet(QSPI_TypeDef * qspi) |
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160:5571c4ff569f | 288 | { |
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160:5571c4ff569f | 289 | return qspi->IRQSTATUS; |
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160:5571c4ff569f | 290 | } |
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160:5571c4ff569f | 291 | |
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160:5571c4ff569f | 292 | /***************************************************************************//** |
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160:5571c4ff569f | 293 | * @brief |
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160:5571c4ff569f | 294 | * Clear interrupt flags |
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160:5571c4ff569f | 295 | * |
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160:5571c4ff569f | 296 | * @param[in] qspi |
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160:5571c4ff569f | 297 | * Pointer to QSPI peripheral register block. |
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160:5571c4ff569f | 298 | * |
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160:5571c4ff569f | 299 | * @param[in] flags |
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160:5571c4ff569f | 300 | * The interrupt flags to clear. |
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160:5571c4ff569f | 301 | ******************************************************************************/ |
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160:5571c4ff569f | 302 | __STATIC_INLINE void QSPI_IntClear(QSPI_TypeDef * qspi, uint32_t flags) |
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160:5571c4ff569f | 303 | { |
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160:5571c4ff569f | 304 | qspi->IRQSTATUS = flags; |
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160:5571c4ff569f | 305 | } |
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160:5571c4ff569f | 306 | |
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160:5571c4ff569f | 307 | /***************************************************************************//** |
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160:5571c4ff569f | 308 | * @brief |
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160:5571c4ff569f | 309 | * Enable interrupts. |
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160:5571c4ff569f | 310 | * |
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160:5571c4ff569f | 311 | * @param[in] qspi |
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160:5571c4ff569f | 312 | * Pointer to QSPI peripheral register block. |
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160:5571c4ff569f | 313 | * |
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160:5571c4ff569f | 314 | * @param[in] flags |
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160:5571c4ff569f | 315 | * The interrupt flags to enable. |
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160:5571c4ff569f | 316 | ******************************************************************************/ |
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160:5571c4ff569f | 317 | __STATIC_INLINE void QSPI_IntEnable(QSPI_TypeDef * qspi, uint32_t flags) |
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160:5571c4ff569f | 318 | { |
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160:5571c4ff569f | 319 | qspi->IRQMASK = flags & (~_QSPI_IRQMASK_MASK); |
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160:5571c4ff569f | 320 | } |
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160:5571c4ff569f | 321 | |
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160:5571c4ff569f | 322 | /***************************************************************************//** |
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160:5571c4ff569f | 323 | * @brief |
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160:5571c4ff569f | 324 | * Disable interrupts. |
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160:5571c4ff569f | 325 | * |
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160:5571c4ff569f | 326 | * @param[in] qspi |
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160:5571c4ff569f | 327 | * Pointer to QSPI peripheral register block. |
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160:5571c4ff569f | 328 | * |
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160:5571c4ff569f | 329 | * @param[in] flags |
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160:5571c4ff569f | 330 | * The interrupt flags to disable. |
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160:5571c4ff569f | 331 | ******************************************************************************/ |
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160:5571c4ff569f | 332 | __STATIC_INLINE void QSPI_IntDisable(QSPI_TypeDef * qspi, uint32_t flags) |
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160:5571c4ff569f | 333 | { |
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160:5571c4ff569f | 334 | qspi->IRQMASK = ~flags & (~_QSPI_IRQMASK_MASK); |
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160:5571c4ff569f | 335 | } |
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160:5571c4ff569f | 336 | |
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160:5571c4ff569f | 337 | /** @} (end addtogroup QSPI) */ |
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160:5571c4ff569f | 338 | /** @} (end addtogroup emlib) */ |
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160:5571c4ff569f | 339 | |
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160:5571c4ff569f | 340 | #ifdef __cplusplus |
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160:5571c4ff569f | 341 | } |
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160:5571c4ff569f | 342 | #endif |
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160:5571c4ff569f | 343 | |
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160:5571c4ff569f | 344 | #endif /* defined(QSPI_COUNT) && (QSPI_COUNT > 0) */ |
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160:5571c4ff569f | 345 | #endif /* EM_QSPI_H */ |