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TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/stm32f7xx_hal_dfsdm.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f7xx_hal_dfsdm.h |
AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of DFSDM HAL module. |
AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
AnnaBridge | 171:3a7713b1edbc | 8 | * |
AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
AnnaBridge | 171:3a7713b1edbc | 10 | * |
AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 32 | * |
AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 34 | */ |
AnnaBridge | 171:3a7713b1edbc | 35 | |
AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F7xx_HAL_DFSDM_H |
AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F7xx_HAL_DFSDM_H |
AnnaBridge | 171:3a7713b1edbc | 39 | |
AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
AnnaBridge | 171:3a7713b1edbc | 43 | |
AnnaBridge | 171:3a7713b1edbc | 44 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 45 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 46 | #include "stm32f7xx_hal_def.h" |
AnnaBridge | 171:3a7713b1edbc | 47 | |
AnnaBridge | 171:3a7713b1edbc | 48 | /** @addtogroup STM32F7xx_HAL_Driver |
AnnaBridge | 171:3a7713b1edbc | 49 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 50 | */ |
AnnaBridge | 171:3a7713b1edbc | 51 | |
AnnaBridge | 171:3a7713b1edbc | 52 | /** @addtogroup DFSDM |
AnnaBridge | 171:3a7713b1edbc | 53 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 54 | */ |
AnnaBridge | 171:3a7713b1edbc | 55 | |
AnnaBridge | 171:3a7713b1edbc | 56 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 57 | /** @defgroup DFSDM_Exported_Types DFSDM Exported Types |
AnnaBridge | 171:3a7713b1edbc | 58 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 59 | */ |
AnnaBridge | 171:3a7713b1edbc | 60 | |
AnnaBridge | 171:3a7713b1edbc | 61 | /** |
AnnaBridge | 171:3a7713b1edbc | 62 | * @brief HAL DFSDM Channel states definition |
AnnaBridge | 171:3a7713b1edbc | 63 | */ |
AnnaBridge | 171:3a7713b1edbc | 64 | typedef enum |
AnnaBridge | 171:3a7713b1edbc | 65 | { |
AnnaBridge | 171:3a7713b1edbc | 66 | HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */ |
AnnaBridge | 171:3a7713b1edbc | 67 | HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */ |
AnnaBridge | 171:3a7713b1edbc | 68 | HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */ |
AnnaBridge | 171:3a7713b1edbc | 69 | }HAL_DFSDM_Channel_StateTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 70 | |
AnnaBridge | 171:3a7713b1edbc | 71 | /** |
AnnaBridge | 171:3a7713b1edbc | 72 | * @brief DFSDM channel output clock structure definition |
AnnaBridge | 171:3a7713b1edbc | 73 | */ |
AnnaBridge | 171:3a7713b1edbc | 74 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 75 | { |
AnnaBridge | 171:3a7713b1edbc | 76 | FunctionalState Activation; /*!< Output clock enable/disable */ |
AnnaBridge | 171:3a7713b1edbc | 77 | uint32_t Selection; /*!< Output clock is system clock or audio clock. |
AnnaBridge | 171:3a7713b1edbc | 78 | This parameter can be a value of @ref DFSDM_Channel_OuputClock */ |
AnnaBridge | 171:3a7713b1edbc | 79 | uint32_t Divider; /*!< Output clock divider. |
AnnaBridge | 171:3a7713b1edbc | 80 | This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ |
AnnaBridge | 171:3a7713b1edbc | 81 | }DFSDM_Channel_OutputClockTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 82 | |
AnnaBridge | 171:3a7713b1edbc | 83 | /** |
AnnaBridge | 171:3a7713b1edbc | 84 | * @brief DFSDM channel input structure definition |
AnnaBridge | 171:3a7713b1edbc | 85 | */ |
AnnaBridge | 171:3a7713b1edbc | 86 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 87 | { |
AnnaBridge | 171:3a7713b1edbc | 88 | uint32_t Multiplexer; /*!< Input is external serial inputs or internal register. |
AnnaBridge | 171:3a7713b1edbc | 89 | This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */ |
AnnaBridge | 171:3a7713b1edbc | 90 | uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register. |
AnnaBridge | 171:3a7713b1edbc | 91 | This parameter can be a value of @ref DFSDM_Channel_DataPacking */ |
AnnaBridge | 171:3a7713b1edbc | 92 | uint32_t Pins; /*!< Input pins are taken from same or following channel. |
AnnaBridge | 171:3a7713b1edbc | 93 | This parameter can be a value of @ref DFSDM_Channel_InputPins */ |
AnnaBridge | 171:3a7713b1edbc | 94 | }DFSDM_Channel_InputTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 95 | |
AnnaBridge | 171:3a7713b1edbc | 96 | /** |
AnnaBridge | 171:3a7713b1edbc | 97 | * @brief DFSDM channel serial interface structure definition |
AnnaBridge | 171:3a7713b1edbc | 98 | */ |
AnnaBridge | 171:3a7713b1edbc | 99 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 100 | { |
AnnaBridge | 171:3a7713b1edbc | 101 | uint32_t Type; /*!< SPI or Manchester modes. |
AnnaBridge | 171:3a7713b1edbc | 102 | This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */ |
AnnaBridge | 171:3a7713b1edbc | 103 | uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point). |
AnnaBridge | 171:3a7713b1edbc | 104 | This parameter can be a value of @ref DFSDM_Channel_SpiClock */ |
AnnaBridge | 171:3a7713b1edbc | 105 | }DFSDM_Channel_SerialInterfaceTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 106 | |
AnnaBridge | 171:3a7713b1edbc | 107 | /** |
AnnaBridge | 171:3a7713b1edbc | 108 | * @brief DFSDM channel analog watchdog structure definition |
AnnaBridge | 171:3a7713b1edbc | 109 | */ |
AnnaBridge | 171:3a7713b1edbc | 110 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 111 | { |
AnnaBridge | 171:3a7713b1edbc | 112 | uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order. |
AnnaBridge | 171:3a7713b1edbc | 113 | This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */ |
AnnaBridge | 171:3a7713b1edbc | 114 | uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio. |
AnnaBridge | 171:3a7713b1edbc | 115 | This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ |
AnnaBridge | 171:3a7713b1edbc | 116 | }DFSDM_Channel_AwdTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 117 | |
AnnaBridge | 171:3a7713b1edbc | 118 | /** |
AnnaBridge | 171:3a7713b1edbc | 119 | * @brief DFSDM channel init structure definition |
AnnaBridge | 171:3a7713b1edbc | 120 | */ |
AnnaBridge | 171:3a7713b1edbc | 121 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 122 | { |
AnnaBridge | 171:3a7713b1edbc | 123 | DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */ |
AnnaBridge | 171:3a7713b1edbc | 124 | DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */ |
AnnaBridge | 171:3a7713b1edbc | 125 | DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */ |
AnnaBridge | 171:3a7713b1edbc | 126 | DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */ |
AnnaBridge | 171:3a7713b1edbc | 127 | int32_t Offset; /*!< DFSDM channel offset. |
AnnaBridge | 171:3a7713b1edbc | 128 | This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ |
AnnaBridge | 171:3a7713b1edbc | 129 | uint32_t RightBitShift; /*!< DFSDM channel right bit shift. |
AnnaBridge | 171:3a7713b1edbc | 130 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ |
AnnaBridge | 171:3a7713b1edbc | 131 | }DFSDM_Channel_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 132 | |
AnnaBridge | 171:3a7713b1edbc | 133 | /** |
AnnaBridge | 171:3a7713b1edbc | 134 | * @brief DFSDM channel handle structure definition |
AnnaBridge | 171:3a7713b1edbc | 135 | */ |
AnnaBridge | 171:3a7713b1edbc | 136 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 137 | { |
AnnaBridge | 171:3a7713b1edbc | 138 | DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ |
AnnaBridge | 171:3a7713b1edbc | 139 | DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ |
AnnaBridge | 171:3a7713b1edbc | 140 | HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ |
AnnaBridge | 171:3a7713b1edbc | 141 | }DFSDM_Channel_HandleTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 142 | |
AnnaBridge | 171:3a7713b1edbc | 143 | /** |
AnnaBridge | 171:3a7713b1edbc | 144 | * @brief HAL DFSDM Filter states definition |
AnnaBridge | 171:3a7713b1edbc | 145 | */ |
AnnaBridge | 171:3a7713b1edbc | 146 | typedef enum |
AnnaBridge | 171:3a7713b1edbc | 147 | { |
AnnaBridge | 171:3a7713b1edbc | 148 | HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */ |
AnnaBridge | 171:3a7713b1edbc | 149 | HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */ |
AnnaBridge | 171:3a7713b1edbc | 150 | HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */ |
AnnaBridge | 171:3a7713b1edbc | 151 | HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */ |
AnnaBridge | 171:3a7713b1edbc | 152 | HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */ |
AnnaBridge | 171:3a7713b1edbc | 153 | HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */ |
AnnaBridge | 171:3a7713b1edbc | 154 | }HAL_DFSDM_Filter_StateTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 155 | |
AnnaBridge | 171:3a7713b1edbc | 156 | /** |
AnnaBridge | 171:3a7713b1edbc | 157 | * @brief DFSDM filter regular conversion parameters structure definition |
AnnaBridge | 171:3a7713b1edbc | 158 | */ |
AnnaBridge | 171:3a7713b1edbc | 159 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 160 | { |
AnnaBridge | 171:3a7713b1edbc | 161 | uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous. |
AnnaBridge | 171:3a7713b1edbc | 162 | This parameter can be a value of @ref DFSDM_Filter_Trigger */ |
AnnaBridge | 171:3a7713b1edbc | 163 | FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */ |
AnnaBridge | 171:3a7713b1edbc | 164 | FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */ |
AnnaBridge | 171:3a7713b1edbc | 165 | }DFSDM_Filter_RegularParamTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 166 | |
AnnaBridge | 171:3a7713b1edbc | 167 | /** |
AnnaBridge | 171:3a7713b1edbc | 168 | * @brief DFSDM filter injected conversion parameters structure definition |
AnnaBridge | 171:3a7713b1edbc | 169 | */ |
AnnaBridge | 171:3a7713b1edbc | 170 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 171 | { |
AnnaBridge | 171:3a7713b1edbc | 172 | uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous. |
AnnaBridge | 171:3a7713b1edbc | 173 | This parameter can be a value of @ref DFSDM_Filter_Trigger */ |
AnnaBridge | 171:3a7713b1edbc | 174 | FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */ |
AnnaBridge | 171:3a7713b1edbc | 175 | FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */ |
AnnaBridge | 171:3a7713b1edbc | 176 | uint32_t ExtTrigger; /*!< External trigger. |
AnnaBridge | 171:3a7713b1edbc | 177 | This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */ |
AnnaBridge | 171:3a7713b1edbc | 178 | uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both. |
AnnaBridge | 171:3a7713b1edbc | 179 | This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */ |
AnnaBridge | 171:3a7713b1edbc | 180 | }DFSDM_Filter_InjectedParamTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 181 | |
AnnaBridge | 171:3a7713b1edbc | 182 | /** |
AnnaBridge | 171:3a7713b1edbc | 183 | * @brief DFSDM filter parameters structure definition |
AnnaBridge | 171:3a7713b1edbc | 184 | */ |
AnnaBridge | 171:3a7713b1edbc | 185 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 186 | { |
AnnaBridge | 171:3a7713b1edbc | 187 | uint32_t SincOrder; /*!< Sinc filter order. |
AnnaBridge | 171:3a7713b1edbc | 188 | This parameter can be a value of @ref DFSDM_Filter_SincOrder */ |
AnnaBridge | 171:3a7713b1edbc | 189 | uint32_t Oversampling; /*!< Filter oversampling ratio. |
AnnaBridge | 171:3a7713b1edbc | 190 | This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ |
AnnaBridge | 171:3a7713b1edbc | 191 | uint32_t IntOversampling; /*!< Integrator oversampling ratio. |
AnnaBridge | 171:3a7713b1edbc | 192 | This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ |
AnnaBridge | 171:3a7713b1edbc | 193 | }DFSDM_Filter_FilterParamTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 194 | |
AnnaBridge | 171:3a7713b1edbc | 195 | /** |
AnnaBridge | 171:3a7713b1edbc | 196 | * @brief DFSDM filter init structure definition |
AnnaBridge | 171:3a7713b1edbc | 197 | */ |
AnnaBridge | 171:3a7713b1edbc | 198 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 199 | { |
AnnaBridge | 171:3a7713b1edbc | 200 | DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */ |
AnnaBridge | 171:3a7713b1edbc | 201 | DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */ |
AnnaBridge | 171:3a7713b1edbc | 202 | DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */ |
AnnaBridge | 171:3a7713b1edbc | 203 | }DFSDM_Filter_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 204 | |
AnnaBridge | 171:3a7713b1edbc | 205 | /** |
AnnaBridge | 171:3a7713b1edbc | 206 | * @brief DFSDM filter handle structure definition |
AnnaBridge | 171:3a7713b1edbc | 207 | */ |
AnnaBridge | 171:3a7713b1edbc | 208 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 209 | { |
AnnaBridge | 171:3a7713b1edbc | 210 | DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ |
AnnaBridge | 171:3a7713b1edbc | 211 | DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ |
AnnaBridge | 171:3a7713b1edbc | 212 | DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */ |
AnnaBridge | 171:3a7713b1edbc | 213 | DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */ |
AnnaBridge | 171:3a7713b1edbc | 214 | uint32_t RegularContMode; /*!< Regular conversion continuous mode */ |
AnnaBridge | 171:3a7713b1edbc | 215 | uint32_t RegularTrigger; /*!< Trigger used for regular conversion */ |
AnnaBridge | 171:3a7713b1edbc | 216 | uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */ |
AnnaBridge | 171:3a7713b1edbc | 217 | uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */ |
AnnaBridge | 171:3a7713b1edbc | 218 | FunctionalState InjectedScanMode; /*!< Injected scanning mode */ |
AnnaBridge | 171:3a7713b1edbc | 219 | uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ |
AnnaBridge | 171:3a7713b1edbc | 220 | uint32_t InjConvRemaining; /*!< Injected conversions remaining */ |
AnnaBridge | 171:3a7713b1edbc | 221 | HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ |
AnnaBridge | 171:3a7713b1edbc | 222 | uint32_t ErrorCode; /*!< DFSDM filter error code */ |
AnnaBridge | 171:3a7713b1edbc | 223 | }DFSDM_Filter_HandleTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 224 | |
AnnaBridge | 171:3a7713b1edbc | 225 | /** |
AnnaBridge | 171:3a7713b1edbc | 226 | * @brief DFSDM filter analog watchdog parameters structure definition |
AnnaBridge | 171:3a7713b1edbc | 227 | */ |
AnnaBridge | 171:3a7713b1edbc | 228 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 229 | { |
AnnaBridge | 171:3a7713b1edbc | 230 | uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter. |
AnnaBridge | 171:3a7713b1edbc | 231 | This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */ |
AnnaBridge | 171:3a7713b1edbc | 232 | uint32_t Channel; /*!< Analog watchdog channel selection. |
AnnaBridge | 171:3a7713b1edbc | 233 | This parameter can be a values combination of @ref DFSDM_Channel_Selection */ |
AnnaBridge | 171:3a7713b1edbc | 234 | int32_t HighThreshold; /*!< High threshold for the analog watchdog. |
AnnaBridge | 171:3a7713b1edbc | 235 | This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ |
AnnaBridge | 171:3a7713b1edbc | 236 | int32_t LowThreshold; /*!< Low threshold for the analog watchdog. |
AnnaBridge | 171:3a7713b1edbc | 237 | This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ |
AnnaBridge | 171:3a7713b1edbc | 238 | uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event. |
AnnaBridge | 171:3a7713b1edbc | 239 | This parameter can be a values combination of @ref DFSDM_BreakSignals */ |
AnnaBridge | 171:3a7713b1edbc | 240 | uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event. |
AnnaBridge | 171:3a7713b1edbc | 241 | This parameter can be a values combination of @ref DFSDM_BreakSignals */ |
AnnaBridge | 171:3a7713b1edbc | 242 | }DFSDM_Filter_AwdParamTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 243 | |
AnnaBridge | 171:3a7713b1edbc | 244 | /** |
AnnaBridge | 171:3a7713b1edbc | 245 | * @} |
AnnaBridge | 171:3a7713b1edbc | 246 | */ |
AnnaBridge | 171:3a7713b1edbc | 247 | /* End of exported types -----------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 248 | |
AnnaBridge | 171:3a7713b1edbc | 249 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 250 | /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants |
AnnaBridge | 171:3a7713b1edbc | 251 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 252 | */ |
AnnaBridge | 171:3a7713b1edbc | 253 | |
AnnaBridge | 171:3a7713b1edbc | 254 | /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection |
AnnaBridge | 171:3a7713b1edbc | 255 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 256 | */ |
AnnaBridge | 171:3a7713b1edbc | 257 | #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) /*!< Source for ouput clock is system clock */ |
AnnaBridge | 171:3a7713b1edbc | 258 | #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */ |
AnnaBridge | 171:3a7713b1edbc | 259 | /** |
AnnaBridge | 171:3a7713b1edbc | 260 | * @} |
AnnaBridge | 171:3a7713b1edbc | 261 | */ |
AnnaBridge | 171:3a7713b1edbc | 262 | |
AnnaBridge | 171:3a7713b1edbc | 263 | /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer |
AnnaBridge | 171:3a7713b1edbc | 264 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 265 | */ |
AnnaBridge | 171:3a7713b1edbc | 266 | #define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */ |
AnnaBridge | 171:3a7713b1edbc | 267 | #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */ |
AnnaBridge | 171:3a7713b1edbc | 268 | /** |
AnnaBridge | 171:3a7713b1edbc | 269 | * @} |
AnnaBridge | 171:3a7713b1edbc | 270 | */ |
AnnaBridge | 171:3a7713b1edbc | 271 | |
AnnaBridge | 171:3a7713b1edbc | 272 | /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing |
AnnaBridge | 171:3a7713b1edbc | 273 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 274 | */ |
AnnaBridge | 171:3a7713b1edbc | 275 | #define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U) /*!< Standard data packing mode */ |
AnnaBridge | 171:3a7713b1edbc | 276 | #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */ |
AnnaBridge | 171:3a7713b1edbc | 277 | #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */ |
AnnaBridge | 171:3a7713b1edbc | 278 | /** |
AnnaBridge | 171:3a7713b1edbc | 279 | * @} |
AnnaBridge | 171:3a7713b1edbc | 280 | */ |
AnnaBridge | 171:3a7713b1edbc | 281 | |
AnnaBridge | 171:3a7713b1edbc | 282 | /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins |
AnnaBridge | 171:3a7713b1edbc | 283 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 284 | */ |
AnnaBridge | 171:3a7713b1edbc | 285 | #define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U) /*!< Input from pins on same channel */ |
AnnaBridge | 171:3a7713b1edbc | 286 | #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */ |
AnnaBridge | 171:3a7713b1edbc | 287 | /** |
AnnaBridge | 171:3a7713b1edbc | 288 | * @} |
AnnaBridge | 171:3a7713b1edbc | 289 | */ |
AnnaBridge | 171:3a7713b1edbc | 290 | |
AnnaBridge | 171:3a7713b1edbc | 291 | /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type |
AnnaBridge | 171:3a7713b1edbc | 292 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 293 | */ |
AnnaBridge | 171:3a7713b1edbc | 294 | #define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U) /*!< SPI with rising edge */ |
AnnaBridge | 171:3a7713b1edbc | 295 | #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */ |
AnnaBridge | 171:3a7713b1edbc | 296 | #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */ |
AnnaBridge | 171:3a7713b1edbc | 297 | #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */ |
AnnaBridge | 171:3a7713b1edbc | 298 | /** |
AnnaBridge | 171:3a7713b1edbc | 299 | * @} |
AnnaBridge | 171:3a7713b1edbc | 300 | */ |
AnnaBridge | 171:3a7713b1edbc | 301 | |
AnnaBridge | 171:3a7713b1edbc | 302 | /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection |
AnnaBridge | 171:3a7713b1edbc | 303 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 304 | */ |
AnnaBridge | 171:3a7713b1edbc | 305 | #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U) /*!< External SPI clock */ |
AnnaBridge | 171:3a7713b1edbc | 306 | #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */ |
AnnaBridge | 171:3a7713b1edbc | 307 | #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */ |
AnnaBridge | 171:3a7713b1edbc | 308 | #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */ |
AnnaBridge | 171:3a7713b1edbc | 309 | /** |
AnnaBridge | 171:3a7713b1edbc | 310 | * @} |
AnnaBridge | 171:3a7713b1edbc | 311 | */ |
AnnaBridge | 171:3a7713b1edbc | 312 | |
AnnaBridge | 171:3a7713b1edbc | 313 | /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order |
AnnaBridge | 171:3a7713b1edbc | 314 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 315 | */ |
AnnaBridge | 171:3a7713b1edbc | 316 | #define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */ |
AnnaBridge | 171:3a7713b1edbc | 317 | #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */ |
AnnaBridge | 171:3a7713b1edbc | 318 | #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */ |
AnnaBridge | 171:3a7713b1edbc | 319 | #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */ |
AnnaBridge | 171:3a7713b1edbc | 320 | /** |
AnnaBridge | 171:3a7713b1edbc | 321 | * @} |
AnnaBridge | 171:3a7713b1edbc | 322 | */ |
AnnaBridge | 171:3a7713b1edbc | 323 | |
AnnaBridge | 171:3a7713b1edbc | 324 | /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger |
AnnaBridge | 171:3a7713b1edbc | 325 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 326 | */ |
AnnaBridge | 171:3a7713b1edbc | 327 | #define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U) /*!< Software trigger */ |
AnnaBridge | 171:3a7713b1edbc | 328 | #define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /*!< Synchronous with DFSDM_FLT0 */ |
AnnaBridge | 171:3a7713b1edbc | 329 | #define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U) /*!< External trigger (only for injected conversion) */ |
AnnaBridge | 171:3a7713b1edbc | 330 | /** |
AnnaBridge | 171:3a7713b1edbc | 331 | * @} |
AnnaBridge | 171:3a7713b1edbc | 332 | */ |
AnnaBridge | 171:3a7713b1edbc | 333 | |
AnnaBridge | 171:3a7713b1edbc | 334 | /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger |
AnnaBridge | 171:3a7713b1edbc | 335 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 336 | */ |
AnnaBridge | 171:3a7713b1edbc | 337 | #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */ |
AnnaBridge | 171:3a7713b1edbc | 338 | #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ |
AnnaBridge | 171:3a7713b1edbc | 339 | #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ |
AnnaBridge | 171:3a7713b1edbc | 340 | #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1, 2 and 3 */ |
AnnaBridge | 171:3a7713b1edbc | 341 | #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 0, 1, 2 and 3 */ |
AnnaBridge | 171:3a7713b1edbc | 342 | #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ |
AnnaBridge | 171:3a7713b1edbc | 343 | #define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ |
AnnaBridge | 171:3a7713b1edbc | 344 | #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \ |
AnnaBridge | 171:3a7713b1edbc | 345 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ |
AnnaBridge | 171:3a7713b1edbc | 346 | #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For DFSDM filter 0, 1, 2 and 3 */ |
AnnaBridge | 171:3a7713b1edbc | 347 | #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */ |
AnnaBridge | 171:3a7713b1edbc | 348 | #define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \ |
AnnaBridge | 171:3a7713b1edbc | 349 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */ |
AnnaBridge | 171:3a7713b1edbc | 350 | #define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \ |
AnnaBridge | 171:3a7713b1edbc | 351 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */ |
AnnaBridge | 171:3a7713b1edbc | 352 | /** |
AnnaBridge | 171:3a7713b1edbc | 353 | * @} |
AnnaBridge | 171:3a7713b1edbc | 354 | */ |
AnnaBridge | 171:3a7713b1edbc | 355 | |
AnnaBridge | 171:3a7713b1edbc | 356 | /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge |
AnnaBridge | 171:3a7713b1edbc | 357 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 358 | */ |
AnnaBridge | 171:3a7713b1edbc | 359 | #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */ |
AnnaBridge | 171:3a7713b1edbc | 360 | #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */ |
AnnaBridge | 171:3a7713b1edbc | 361 | #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */ |
AnnaBridge | 171:3a7713b1edbc | 362 | /** |
AnnaBridge | 171:3a7713b1edbc | 363 | * @} |
AnnaBridge | 171:3a7713b1edbc | 364 | */ |
AnnaBridge | 171:3a7713b1edbc | 365 | |
AnnaBridge | 171:3a7713b1edbc | 366 | /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order |
AnnaBridge | 171:3a7713b1edbc | 367 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 368 | */ |
AnnaBridge | 171:3a7713b1edbc | 369 | #define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */ |
AnnaBridge | 171:3a7713b1edbc | 370 | #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */ |
AnnaBridge | 171:3a7713b1edbc | 371 | #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */ |
AnnaBridge | 171:3a7713b1edbc | 372 | #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */ |
AnnaBridge | 171:3a7713b1edbc | 373 | #define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */ |
AnnaBridge | 171:3a7713b1edbc | 374 | #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */ |
AnnaBridge | 171:3a7713b1edbc | 375 | /** |
AnnaBridge | 171:3a7713b1edbc | 376 | * @} |
AnnaBridge | 171:3a7713b1edbc | 377 | */ |
AnnaBridge | 171:3a7713b1edbc | 378 | |
AnnaBridge | 171:3a7713b1edbc | 379 | /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source |
AnnaBridge | 171:3a7713b1edbc | 380 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 381 | */ |
AnnaBridge | 171:3a7713b1edbc | 382 | #define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U) /*!< From digital filter */ |
AnnaBridge | 171:3a7713b1edbc | 383 | #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */ |
AnnaBridge | 171:3a7713b1edbc | 384 | /** |
AnnaBridge | 171:3a7713b1edbc | 385 | * @} |
AnnaBridge | 171:3a7713b1edbc | 386 | */ |
AnnaBridge | 171:3a7713b1edbc | 387 | |
AnnaBridge | 171:3a7713b1edbc | 388 | /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code |
AnnaBridge | 171:3a7713b1edbc | 389 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 390 | */ |
AnnaBridge | 171:3a7713b1edbc | 391 | #define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ |
AnnaBridge | 171:3a7713b1edbc | 392 | #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U) /*!< Overrun occurs during regular conversion */ |
AnnaBridge | 171:3a7713b1edbc | 393 | #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /*!< Overrun occurs during injected conversion */ |
AnnaBridge | 171:3a7713b1edbc | 394 | #define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U) /*!< DMA error occurs */ |
AnnaBridge | 171:3a7713b1edbc | 395 | /** |
AnnaBridge | 171:3a7713b1edbc | 396 | * @} |
AnnaBridge | 171:3a7713b1edbc | 397 | */ |
AnnaBridge | 171:3a7713b1edbc | 398 | |
AnnaBridge | 171:3a7713b1edbc | 399 | /** @defgroup DFSDM_BreakSignals DFSDM break signals |
AnnaBridge | 171:3a7713b1edbc | 400 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 401 | */ |
AnnaBridge | 171:3a7713b1edbc | 402 | #define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /*!< No break signal */ |
AnnaBridge | 171:3a7713b1edbc | 403 | #define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U) /*!< Break signal 0 */ |
AnnaBridge | 171:3a7713b1edbc | 404 | #define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U) /*!< Break signal 1 */ |
AnnaBridge | 171:3a7713b1edbc | 405 | #define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U) /*!< Break signal 2 */ |
AnnaBridge | 171:3a7713b1edbc | 406 | #define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U) /*!< Break signal 3 */ |
AnnaBridge | 171:3a7713b1edbc | 407 | /** |
AnnaBridge | 171:3a7713b1edbc | 408 | * @} |
AnnaBridge | 171:3a7713b1edbc | 409 | */ |
AnnaBridge | 171:3a7713b1edbc | 410 | |
AnnaBridge | 171:3a7713b1edbc | 411 | /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection |
AnnaBridge | 171:3a7713b1edbc | 412 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 413 | */ |
AnnaBridge | 171:3a7713b1edbc | 414 | /* DFSDM Channels ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 415 | /* The DFSDM channels are defined as follows: |
AnnaBridge | 171:3a7713b1edbc | 416 | - in 16-bit LSB the channel mask is set |
AnnaBridge | 171:3a7713b1edbc | 417 | - in 16-bit MSB the channel number is set |
AnnaBridge | 171:3a7713b1edbc | 418 | e.g. for channel 5 definition: |
AnnaBridge | 171:3a7713b1edbc | 419 | - the channel mask is 0x00000020 (bit 5 is set) |
AnnaBridge | 171:3a7713b1edbc | 420 | - the channel number 5 is 0x00050000 |
AnnaBridge | 171:3a7713b1edbc | 421 | --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */ |
AnnaBridge | 171:3a7713b1edbc | 422 | #define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U) |
AnnaBridge | 171:3a7713b1edbc | 423 | #define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U) |
AnnaBridge | 171:3a7713b1edbc | 424 | #define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U) |
AnnaBridge | 171:3a7713b1edbc | 425 | #define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U) |
AnnaBridge | 171:3a7713b1edbc | 426 | #define DFSDM_CHANNEL_4 ((uint32_t)0x00040010U) |
AnnaBridge | 171:3a7713b1edbc | 427 | #define DFSDM_CHANNEL_5 ((uint32_t)0x00050020U) |
AnnaBridge | 171:3a7713b1edbc | 428 | #define DFSDM_CHANNEL_6 ((uint32_t)0x00060040U) |
AnnaBridge | 171:3a7713b1edbc | 429 | #define DFSDM_CHANNEL_7 ((uint32_t)0x00070080U) |
AnnaBridge | 171:3a7713b1edbc | 430 | /** |
AnnaBridge | 171:3a7713b1edbc | 431 | * @} |
AnnaBridge | 171:3a7713b1edbc | 432 | */ |
AnnaBridge | 171:3a7713b1edbc | 433 | |
AnnaBridge | 171:3a7713b1edbc | 434 | /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode |
AnnaBridge | 171:3a7713b1edbc | 435 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 436 | */ |
AnnaBridge | 171:3a7713b1edbc | 437 | #define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U) /*!< Conversion are not continuous */ |
AnnaBridge | 171:3a7713b1edbc | 438 | #define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U) /*!< Conversion are continuous */ |
AnnaBridge | 171:3a7713b1edbc | 439 | /** |
AnnaBridge | 171:3a7713b1edbc | 440 | * @} |
AnnaBridge | 171:3a7713b1edbc | 441 | */ |
AnnaBridge | 171:3a7713b1edbc | 442 | |
AnnaBridge | 171:3a7713b1edbc | 443 | /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold |
AnnaBridge | 171:3a7713b1edbc | 444 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 445 | */ |
AnnaBridge | 171:3a7713b1edbc | 446 | #define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U) /*!< Analog watchdog high threshold */ |
AnnaBridge | 171:3a7713b1edbc | 447 | #define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U) /*!< Analog watchdog low threshold */ |
AnnaBridge | 171:3a7713b1edbc | 448 | /** |
AnnaBridge | 171:3a7713b1edbc | 449 | * @} |
AnnaBridge | 171:3a7713b1edbc | 450 | */ |
AnnaBridge | 171:3a7713b1edbc | 451 | |
AnnaBridge | 171:3a7713b1edbc | 452 | /** |
AnnaBridge | 171:3a7713b1edbc | 453 | * @} |
AnnaBridge | 171:3a7713b1edbc | 454 | */ |
AnnaBridge | 171:3a7713b1edbc | 455 | /* End of exported constants -------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 456 | |
AnnaBridge | 171:3a7713b1edbc | 457 | /* Exported macros -----------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 458 | /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros |
AnnaBridge | 171:3a7713b1edbc | 459 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 460 | */ |
AnnaBridge | 171:3a7713b1edbc | 461 | |
AnnaBridge | 171:3a7713b1edbc | 462 | /** @brief Reset DFSDM channel handle state. |
AnnaBridge | 171:3a7713b1edbc | 463 | * @param __HANDLE__ DFSDM channel handle. |
AnnaBridge | 171:3a7713b1edbc | 464 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 465 | */ |
AnnaBridge | 171:3a7713b1edbc | 466 | #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) |
AnnaBridge | 171:3a7713b1edbc | 467 | |
AnnaBridge | 171:3a7713b1edbc | 468 | /** @brief Reset DFSDM filter handle state. |
AnnaBridge | 171:3a7713b1edbc | 469 | * @param __HANDLE__ DFSDM filter handle. |
AnnaBridge | 171:3a7713b1edbc | 470 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 471 | */ |
AnnaBridge | 171:3a7713b1edbc | 472 | #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) |
AnnaBridge | 171:3a7713b1edbc | 473 | |
AnnaBridge | 171:3a7713b1edbc | 474 | /** |
AnnaBridge | 171:3a7713b1edbc | 475 | * @} |
AnnaBridge | 171:3a7713b1edbc | 476 | */ |
AnnaBridge | 171:3a7713b1edbc | 477 | /* End of exported macros ----------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 478 | |
AnnaBridge | 171:3a7713b1edbc | 479 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 480 | /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions |
AnnaBridge | 171:3a7713b1edbc | 481 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 482 | */ |
AnnaBridge | 171:3a7713b1edbc | 483 | |
AnnaBridge | 171:3a7713b1edbc | 484 | /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions |
AnnaBridge | 171:3a7713b1edbc | 485 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 486 | */ |
AnnaBridge | 171:3a7713b1edbc | 487 | /* Channel initialization and de-initialization functions *********************/ |
AnnaBridge | 171:3a7713b1edbc | 488 | HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 171:3a7713b1edbc | 489 | HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 171:3a7713b1edbc | 490 | void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 171:3a7713b1edbc | 491 | void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 171:3a7713b1edbc | 492 | /** |
AnnaBridge | 171:3a7713b1edbc | 493 | * @} |
AnnaBridge | 171:3a7713b1edbc | 494 | */ |
AnnaBridge | 171:3a7713b1edbc | 495 | |
AnnaBridge | 171:3a7713b1edbc | 496 | /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions |
AnnaBridge | 171:3a7713b1edbc | 497 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 498 | */ |
AnnaBridge | 171:3a7713b1edbc | 499 | /* Channel operation functions ************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 500 | HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 171:3a7713b1edbc | 501 | HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 171:3a7713b1edbc | 502 | HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 171:3a7713b1edbc | 503 | HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 171:3a7713b1edbc | 504 | |
AnnaBridge | 171:3a7713b1edbc | 505 | HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); |
AnnaBridge | 171:3a7713b1edbc | 506 | HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); |
AnnaBridge | 171:3a7713b1edbc | 507 | HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 171:3a7713b1edbc | 508 | HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 171:3a7713b1edbc | 509 | |
AnnaBridge | 171:3a7713b1edbc | 510 | int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 171:3a7713b1edbc | 511 | HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); |
AnnaBridge | 171:3a7713b1edbc | 512 | |
AnnaBridge | 171:3a7713b1edbc | 513 | HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); |
AnnaBridge | 171:3a7713b1edbc | 514 | HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); |
AnnaBridge | 171:3a7713b1edbc | 515 | |
AnnaBridge | 171:3a7713b1edbc | 516 | void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 171:3a7713b1edbc | 517 | void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 171:3a7713b1edbc | 518 | /** |
AnnaBridge | 171:3a7713b1edbc | 519 | * @} |
AnnaBridge | 171:3a7713b1edbc | 520 | */ |
AnnaBridge | 171:3a7713b1edbc | 521 | |
AnnaBridge | 171:3a7713b1edbc | 522 | /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function |
AnnaBridge | 171:3a7713b1edbc | 523 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 524 | */ |
AnnaBridge | 171:3a7713b1edbc | 525 | /* Channel state function *****************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 526 | HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 171:3a7713b1edbc | 527 | /** |
AnnaBridge | 171:3a7713b1edbc | 528 | * @} |
AnnaBridge | 171:3a7713b1edbc | 529 | */ |
AnnaBridge | 171:3a7713b1edbc | 530 | |
AnnaBridge | 171:3a7713b1edbc | 531 | /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions |
AnnaBridge | 171:3a7713b1edbc | 532 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 533 | */ |
AnnaBridge | 171:3a7713b1edbc | 534 | /* Filter initialization and de-initialization functions *********************/ |
AnnaBridge | 171:3a7713b1edbc | 535 | HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 536 | HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 537 | void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 538 | void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 539 | /** |
AnnaBridge | 171:3a7713b1edbc | 540 | * @} |
AnnaBridge | 171:3a7713b1edbc | 541 | */ |
AnnaBridge | 171:3a7713b1edbc | 542 | |
AnnaBridge | 171:3a7713b1edbc | 543 | /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions |
AnnaBridge | 171:3a7713b1edbc | 544 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 545 | */ |
AnnaBridge | 171:3a7713b1edbc | 546 | /* Filter control functions *********************/ |
AnnaBridge | 171:3a7713b1edbc | 547 | HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, |
AnnaBridge | 171:3a7713b1edbc | 548 | uint32_t Channel, |
AnnaBridge | 171:3a7713b1edbc | 549 | uint32_t ContinuousMode); |
AnnaBridge | 171:3a7713b1edbc | 550 | HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, |
AnnaBridge | 171:3a7713b1edbc | 551 | uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 552 | /** |
AnnaBridge | 171:3a7713b1edbc | 553 | * @} |
AnnaBridge | 171:3a7713b1edbc | 554 | */ |
AnnaBridge | 171:3a7713b1edbc | 555 | |
AnnaBridge | 171:3a7713b1edbc | 556 | /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions |
AnnaBridge | 171:3a7713b1edbc | 557 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 558 | */ |
AnnaBridge | 171:3a7713b1edbc | 559 | /* Filter operation functions *********************/ |
AnnaBridge | 171:3a7713b1edbc | 560 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 561 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 562 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); |
AnnaBridge | 171:3a7713b1edbc | 563 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); |
AnnaBridge | 171:3a7713b1edbc | 564 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 565 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 566 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 567 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 568 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 569 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); |
AnnaBridge | 171:3a7713b1edbc | 570 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); |
AnnaBridge | 171:3a7713b1edbc | 571 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 572 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 573 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 574 | HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, |
AnnaBridge | 171:3a7713b1edbc | 575 | DFSDM_Filter_AwdParamTypeDef* awdParam); |
AnnaBridge | 171:3a7713b1edbc | 576 | HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 577 | HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 578 | HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 579 | |
AnnaBridge | 171:3a7713b1edbc | 580 | int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); |
AnnaBridge | 171:3a7713b1edbc | 581 | int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); |
AnnaBridge | 171:3a7713b1edbc | 582 | int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); |
AnnaBridge | 171:3a7713b1edbc | 583 | int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); |
AnnaBridge | 171:3a7713b1edbc | 584 | uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 585 | |
AnnaBridge | 171:3a7713b1edbc | 586 | void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 587 | |
AnnaBridge | 171:3a7713b1edbc | 588 | HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); |
AnnaBridge | 171:3a7713b1edbc | 589 | HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); |
AnnaBridge | 171:3a7713b1edbc | 590 | |
AnnaBridge | 171:3a7713b1edbc | 591 | void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 592 | void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 593 | void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 594 | void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 595 | void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); |
AnnaBridge | 171:3a7713b1edbc | 596 | void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 597 | /** |
AnnaBridge | 171:3a7713b1edbc | 598 | * @} |
AnnaBridge | 171:3a7713b1edbc | 599 | */ |
AnnaBridge | 171:3a7713b1edbc | 600 | |
AnnaBridge | 171:3a7713b1edbc | 601 | /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions |
AnnaBridge | 171:3a7713b1edbc | 602 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 603 | */ |
AnnaBridge | 171:3a7713b1edbc | 604 | /* Filter state functions *****************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 605 | HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 606 | uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 171:3a7713b1edbc | 607 | /** |
AnnaBridge | 171:3a7713b1edbc | 608 | * @} |
AnnaBridge | 171:3a7713b1edbc | 609 | */ |
AnnaBridge | 171:3a7713b1edbc | 610 | |
AnnaBridge | 171:3a7713b1edbc | 611 | /** |
AnnaBridge | 171:3a7713b1edbc | 612 | * @} |
AnnaBridge | 171:3a7713b1edbc | 613 | */ |
AnnaBridge | 171:3a7713b1edbc | 614 | /* End of exported functions -------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 615 | |
AnnaBridge | 171:3a7713b1edbc | 616 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 617 | /** @defgroup DFSDM_Private_Macros DFSDM Private Macros |
AnnaBridge | 171:3a7713b1edbc | 618 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 619 | */ |
AnnaBridge | 171:3a7713b1edbc | 620 | #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ |
AnnaBridge | 171:3a7713b1edbc | 621 | ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) |
AnnaBridge | 171:3a7713b1edbc | 622 | #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256)) |
AnnaBridge | 171:3a7713b1edbc | 623 | #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ |
AnnaBridge | 171:3a7713b1edbc | 624 | ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) |
AnnaBridge | 171:3a7713b1edbc | 625 | #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ |
AnnaBridge | 171:3a7713b1edbc | 626 | ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ |
AnnaBridge | 171:3a7713b1edbc | 627 | ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) |
AnnaBridge | 171:3a7713b1edbc | 628 | #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \ |
AnnaBridge | 171:3a7713b1edbc | 629 | ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS)) |
AnnaBridge | 171:3a7713b1edbc | 630 | #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \ |
AnnaBridge | 171:3a7713b1edbc | 631 | ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \ |
AnnaBridge | 171:3a7713b1edbc | 632 | ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \ |
AnnaBridge | 171:3a7713b1edbc | 633 | ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING)) |
AnnaBridge | 171:3a7713b1edbc | 634 | #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \ |
AnnaBridge | 171:3a7713b1edbc | 635 | ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \ |
AnnaBridge | 171:3a7713b1edbc | 636 | ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \ |
AnnaBridge | 171:3a7713b1edbc | 637 | ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING)) |
AnnaBridge | 171:3a7713b1edbc | 638 | #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \ |
AnnaBridge | 171:3a7713b1edbc | 639 | ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \ |
AnnaBridge | 171:3a7713b1edbc | 640 | ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \ |
AnnaBridge | 171:3a7713b1edbc | 641 | ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) |
AnnaBridge | 171:3a7713b1edbc | 642 | #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32)) |
AnnaBridge | 171:3a7713b1edbc | 643 | #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) |
AnnaBridge | 171:3a7713b1edbc | 644 | #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F) |
AnnaBridge | 171:3a7713b1edbc | 645 | #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF) |
AnnaBridge | 171:3a7713b1edbc | 646 | #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ |
AnnaBridge | 171:3a7713b1edbc | 647 | ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) |
AnnaBridge | 171:3a7713b1edbc | 648 | #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ |
AnnaBridge | 171:3a7713b1edbc | 649 | ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \ |
AnnaBridge | 171:3a7713b1edbc | 650 | ((TRIG) == DFSDM_FILTER_EXT_TRIGGER)) |
AnnaBridge | 171:3a7713b1edbc | 651 | #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ |
AnnaBridge | 171:3a7713b1edbc | 652 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2)|| \ |
AnnaBridge | 171:3a7713b1edbc | 653 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ |
AnnaBridge | 171:3a7713b1edbc | 654 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2)|| \ |
AnnaBridge | 171:3a7713b1edbc | 655 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ |
AnnaBridge | 171:3a7713b1edbc | 656 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ |
AnnaBridge | 171:3a7713b1edbc | 657 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \ |
AnnaBridge | 171:3a7713b1edbc | 658 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ |
AnnaBridge | 171:3a7713b1edbc | 659 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ |
AnnaBridge | 171:3a7713b1edbc | 660 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ |
AnnaBridge | 171:3a7713b1edbc | 661 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) ||\ |
AnnaBridge | 171:3a7713b1edbc | 662 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT)) |
AnnaBridge | 171:3a7713b1edbc | 663 | #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \ |
AnnaBridge | 171:3a7713b1edbc | 664 | ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \ |
AnnaBridge | 171:3a7713b1edbc | 665 | ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES)) |
AnnaBridge | 171:3a7713b1edbc | 666 | #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \ |
AnnaBridge | 171:3a7713b1edbc | 667 | ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \ |
AnnaBridge | 171:3a7713b1edbc | 668 | ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \ |
AnnaBridge | 171:3a7713b1edbc | 669 | ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \ |
AnnaBridge | 171:3a7713b1edbc | 670 | ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \ |
AnnaBridge | 171:3a7713b1edbc | 671 | ((ORDER) == DFSDM_FILTER_SINC5_ORDER)) |
AnnaBridge | 171:3a7713b1edbc | 672 | #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024)) |
AnnaBridge | 171:3a7713b1edbc | 673 | #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256)) |
AnnaBridge | 171:3a7713b1edbc | 674 | #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \ |
AnnaBridge | 171:3a7713b1edbc | 675 | ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) |
AnnaBridge | 171:3a7713b1edbc | 676 | #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) |
AnnaBridge | 171:3a7713b1edbc | 677 | #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU) |
AnnaBridge | 171:3a7713b1edbc | 678 | #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ |
AnnaBridge | 171:3a7713b1edbc | 679 | ((CHANNEL) == DFSDM_CHANNEL_1) || \ |
AnnaBridge | 171:3a7713b1edbc | 680 | ((CHANNEL) == DFSDM_CHANNEL_2) || \ |
AnnaBridge | 171:3a7713b1edbc | 681 | ((CHANNEL) == DFSDM_CHANNEL_3) || \ |
AnnaBridge | 171:3a7713b1edbc | 682 | ((CHANNEL) == DFSDM_CHANNEL_4) || \ |
AnnaBridge | 171:3a7713b1edbc | 683 | ((CHANNEL) == DFSDM_CHANNEL_5) || \ |
AnnaBridge | 171:3a7713b1edbc | 684 | ((CHANNEL) == DFSDM_CHANNEL_6) || \ |
AnnaBridge | 171:3a7713b1edbc | 685 | ((CHANNEL) == DFSDM_CHANNEL_7)) |
AnnaBridge | 171:3a7713b1edbc | 686 | #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU)) |
AnnaBridge | 171:3a7713b1edbc | 687 | #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ |
AnnaBridge | 171:3a7713b1edbc | 688 | ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) |
AnnaBridge | 171:3a7713b1edbc | 689 | /** |
AnnaBridge | 171:3a7713b1edbc | 690 | * @} |
AnnaBridge | 171:3a7713b1edbc | 691 | */ |
AnnaBridge | 171:3a7713b1edbc | 692 | /* End of private macros -----------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 693 | |
AnnaBridge | 171:3a7713b1edbc | 694 | /** |
AnnaBridge | 171:3a7713b1edbc | 695 | * @} |
AnnaBridge | 171:3a7713b1edbc | 696 | */ |
AnnaBridge | 171:3a7713b1edbc | 697 | |
AnnaBridge | 171:3a7713b1edbc | 698 | /** |
AnnaBridge | 171:3a7713b1edbc | 699 | * @} |
AnnaBridge | 171:3a7713b1edbc | 700 | */ |
AnnaBridge | 171:3a7713b1edbc | 701 | #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 702 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 703 | } |
AnnaBridge | 171:3a7713b1edbc | 704 | #endif |
AnnaBridge | 171:3a7713b1edbc | 705 | |
AnnaBridge | 171:3a7713b1edbc | 706 | #endif /* __STM32F7xx_HAL_DFSDM_H */ |
AnnaBridge | 171:3a7713b1edbc | 707 | |
AnnaBridge | 171:3a7713b1edbc | 708 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |