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TARGET_DISCO_F303VC/TOOLCHAIN_ARM_STD/stm32f3xx_ll_dac.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_DISCO_F303VC/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_dac.h@168:b9e159c1930a
mbed library. Release version 164
Who changed what in which revision?
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AnnaBridge | 163:e59c8e839560 | 1 | /** |
AnnaBridge | 163:e59c8e839560 | 2 | ****************************************************************************** |
AnnaBridge | 163:e59c8e839560 | 3 | * @file stm32f3xx_ll_dac.h |
AnnaBridge | 163:e59c8e839560 | 4 | * @author MCD Application Team |
AnnaBridge | 163:e59c8e839560 | 5 | * @brief Header file of DAC LL module. |
AnnaBridge | 163:e59c8e839560 | 6 | ****************************************************************************** |
AnnaBridge | 163:e59c8e839560 | 7 | * @attention |
AnnaBridge | 163:e59c8e839560 | 8 | * |
AnnaBridge | 163:e59c8e839560 | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
AnnaBridge | 163:e59c8e839560 | 10 | * |
AnnaBridge | 163:e59c8e839560 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 163:e59c8e839560 | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 163:e59c8e839560 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 163:e59c8e839560 | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 163:e59c8e839560 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 163:e59c8e839560 | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 163:e59c8e839560 | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 163:e59c8e839560 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 163:e59c8e839560 | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 163:e59c8e839560 | 20 | * without specific prior written permission. |
AnnaBridge | 163:e59c8e839560 | 21 | * |
AnnaBridge | 163:e59c8e839560 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 163:e59c8e839560 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 163:e59c8e839560 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 163:e59c8e839560 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 163:e59c8e839560 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 163:e59c8e839560 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 163:e59c8e839560 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 163:e59c8e839560 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 163:e59c8e839560 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 163:e59c8e839560 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 163:e59c8e839560 | 32 | * |
AnnaBridge | 163:e59c8e839560 | 33 | ****************************************************************************** |
AnnaBridge | 163:e59c8e839560 | 34 | */ |
AnnaBridge | 163:e59c8e839560 | 35 | |
AnnaBridge | 163:e59c8e839560 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 37 | #ifndef __STM32F3xx_LL_DAC_H |
AnnaBridge | 163:e59c8e839560 | 38 | #define __STM32F3xx_LL_DAC_H |
AnnaBridge | 163:e59c8e839560 | 39 | |
AnnaBridge | 163:e59c8e839560 | 40 | #ifdef __cplusplus |
AnnaBridge | 163:e59c8e839560 | 41 | extern "C" { |
AnnaBridge | 163:e59c8e839560 | 42 | #endif |
AnnaBridge | 163:e59c8e839560 | 43 | |
AnnaBridge | 163:e59c8e839560 | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 45 | #include "stm32f3xx.h" |
AnnaBridge | 163:e59c8e839560 | 46 | |
AnnaBridge | 163:e59c8e839560 | 47 | /** @addtogroup STM32F3xx_LL_Driver |
AnnaBridge | 163:e59c8e839560 | 48 | * @{ |
AnnaBridge | 163:e59c8e839560 | 49 | */ |
AnnaBridge | 163:e59c8e839560 | 50 | |
AnnaBridge | 163:e59c8e839560 | 51 | #if defined (DAC1) || defined (DAC2) |
AnnaBridge | 163:e59c8e839560 | 52 | |
AnnaBridge | 163:e59c8e839560 | 53 | /** @defgroup DAC_LL DAC |
AnnaBridge | 163:e59c8e839560 | 54 | * @{ |
AnnaBridge | 163:e59c8e839560 | 55 | */ |
AnnaBridge | 163:e59c8e839560 | 56 | |
AnnaBridge | 163:e59c8e839560 | 57 | /* Private types -------------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 58 | /* Private variables ---------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 59 | |
AnnaBridge | 163:e59c8e839560 | 60 | /* Private constants ---------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 61 | /** @defgroup DAC_LL_Private_Constants DAC Private Constants |
AnnaBridge | 163:e59c8e839560 | 62 | * @{ |
AnnaBridge | 163:e59c8e839560 | 63 | */ |
AnnaBridge | 163:e59c8e839560 | 64 | |
AnnaBridge | 163:e59c8e839560 | 65 | /* Internal masks for DAC channels definition */ |
AnnaBridge | 163:e59c8e839560 | 66 | /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ |
AnnaBridge | 163:e59c8e839560 | 67 | /* - channel bits position into register CR */ |
AnnaBridge | 163:e59c8e839560 | 68 | /* - channel bits position into register SWTRIG */ |
AnnaBridge | 163:e59c8e839560 | 69 | /* - channel register offset of data holding register DHRx */ |
AnnaBridge | 163:e59c8e839560 | 70 | /* - channel register offset of data output register DORx */ |
AnnaBridge | 163:e59c8e839560 | 71 | #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ |
AnnaBridge | 163:e59c8e839560 | 72 | #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ |
AnnaBridge | 163:e59c8e839560 | 73 | #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) |
AnnaBridge | 163:e59c8e839560 | 74 | |
AnnaBridge | 163:e59c8e839560 | 75 | #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ |
AnnaBridge | 163:e59c8e839560 | 76 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 163:e59c8e839560 | 77 | #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ |
AnnaBridge | 163:e59c8e839560 | 78 | #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) |
AnnaBridge | 163:e59c8e839560 | 79 | #else |
AnnaBridge | 163:e59c8e839560 | 80 | #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1) |
AnnaBridge | 163:e59c8e839560 | 81 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 163:e59c8e839560 | 82 | |
AnnaBridge | 163:e59c8e839560 | 83 | #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */ |
AnnaBridge | 163:e59c8e839560 | 84 | #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
AnnaBridge | 163:e59c8e839560 | 85 | #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
AnnaBridge | 163:e59c8e839560 | 86 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 163:e59c8e839560 | 87 | #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ |
AnnaBridge | 163:e59c8e839560 | 88 | #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
AnnaBridge | 163:e59c8e839560 | 89 | #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
AnnaBridge | 163:e59c8e839560 | 90 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 163:e59c8e839560 | 91 | #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U |
AnnaBridge | 163:e59c8e839560 | 92 | #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U |
AnnaBridge | 163:e59c8e839560 | 93 | #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U |
AnnaBridge | 163:e59c8e839560 | 94 | #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) |
AnnaBridge | 163:e59c8e839560 | 95 | |
AnnaBridge | 163:e59c8e839560 | 96 | #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ |
AnnaBridge | 163:e59c8e839560 | 97 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 163:e59c8e839560 | 98 | #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ |
AnnaBridge | 163:e59c8e839560 | 99 | #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) |
AnnaBridge | 163:e59c8e839560 | 100 | #else |
AnnaBridge | 163:e59c8e839560 | 101 | #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET) |
AnnaBridge | 163:e59c8e839560 | 102 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 163:e59c8e839560 | 103 | |
AnnaBridge | 163:e59c8e839560 | 104 | /* DAC registers bits positions */ |
AnnaBridge | 163:e59c8e839560 | 105 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 163:e59c8e839560 | 106 | #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */ |
AnnaBridge | 163:e59c8e839560 | 107 | #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */ |
AnnaBridge | 163:e59c8e839560 | 108 | #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */ |
AnnaBridge | 163:e59c8e839560 | 109 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 163:e59c8e839560 | 110 | |
AnnaBridge | 163:e59c8e839560 | 111 | /* Miscellaneous data */ |
AnnaBridge | 163:e59c8e839560 | 112 | #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ |
AnnaBridge | 163:e59c8e839560 | 113 | |
AnnaBridge | 163:e59c8e839560 | 114 | /** |
AnnaBridge | 163:e59c8e839560 | 115 | * @} |
AnnaBridge | 163:e59c8e839560 | 116 | */ |
AnnaBridge | 163:e59c8e839560 | 117 | |
AnnaBridge | 163:e59c8e839560 | 118 | |
AnnaBridge | 163:e59c8e839560 | 119 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 120 | /** @defgroup DAC_LL_Private_Macros DAC Private Macros |
AnnaBridge | 163:e59c8e839560 | 121 | * @{ |
AnnaBridge | 163:e59c8e839560 | 122 | */ |
AnnaBridge | 163:e59c8e839560 | 123 | |
AnnaBridge | 163:e59c8e839560 | 124 | /** |
AnnaBridge | 163:e59c8e839560 | 125 | * @brief Driver macro reserved for internal use: isolate bits with the |
AnnaBridge | 163:e59c8e839560 | 126 | * selected mask and shift them to the register LSB |
AnnaBridge | 163:e59c8e839560 | 127 | * (shift mask on register position bit 0). |
AnnaBridge | 163:e59c8e839560 | 128 | * @param __BITS__ Bits in register 32 bits |
AnnaBridge | 163:e59c8e839560 | 129 | * @param __MASK__ Mask in register 32 bits |
AnnaBridge | 163:e59c8e839560 | 130 | * @retval Bits in register 32 bits |
AnnaBridge | 163:e59c8e839560 | 131 | */ |
AnnaBridge | 163:e59c8e839560 | 132 | #define __DAC_MASK_SHIFT(__BITS__, __MASK__) \ |
AnnaBridge | 163:e59c8e839560 | 133 | (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) |
AnnaBridge | 163:e59c8e839560 | 134 | |
AnnaBridge | 163:e59c8e839560 | 135 | /** |
AnnaBridge | 163:e59c8e839560 | 136 | * @brief Driver macro reserved for internal use: set a pointer to |
AnnaBridge | 163:e59c8e839560 | 137 | * a register from a register basis from which an offset |
AnnaBridge | 163:e59c8e839560 | 138 | * is applied. |
AnnaBridge | 163:e59c8e839560 | 139 | * @param __REG__ Register basis from which the offset is applied. |
AnnaBridge | 163:e59c8e839560 | 140 | * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). |
AnnaBridge | 163:e59c8e839560 | 141 | * @retval Pointer to register address |
AnnaBridge | 163:e59c8e839560 | 142 | */ |
AnnaBridge | 163:e59c8e839560 | 143 | #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ |
AnnaBridge | 163:e59c8e839560 | 144 | ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) |
AnnaBridge | 163:e59c8e839560 | 145 | |
AnnaBridge | 163:e59c8e839560 | 146 | /** |
AnnaBridge | 163:e59c8e839560 | 147 | * @} |
AnnaBridge | 163:e59c8e839560 | 148 | */ |
AnnaBridge | 163:e59c8e839560 | 149 | |
AnnaBridge | 163:e59c8e839560 | 150 | |
AnnaBridge | 163:e59c8e839560 | 151 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 152 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 163:e59c8e839560 | 153 | /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure |
AnnaBridge | 163:e59c8e839560 | 154 | * @{ |
AnnaBridge | 163:e59c8e839560 | 155 | */ |
AnnaBridge | 163:e59c8e839560 | 156 | |
AnnaBridge | 163:e59c8e839560 | 157 | /** |
AnnaBridge | 163:e59c8e839560 | 158 | * @brief Structure definition of some features of DAC instance. |
AnnaBridge | 163:e59c8e839560 | 159 | */ |
AnnaBridge | 163:e59c8e839560 | 160 | typedef struct |
AnnaBridge | 163:e59c8e839560 | 161 | { |
AnnaBridge | 163:e59c8e839560 | 162 | uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line). |
AnnaBridge | 163:e59c8e839560 | 163 | This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE |
AnnaBridge | 163:e59c8e839560 | 164 | |
AnnaBridge | 163:e59c8e839560 | 165 | This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */ |
AnnaBridge | 163:e59c8e839560 | 166 | |
AnnaBridge | 163:e59c8e839560 | 167 | uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. |
AnnaBridge | 163:e59c8e839560 | 168 | This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE |
AnnaBridge | 163:e59c8e839560 | 169 | |
AnnaBridge | 163:e59c8e839560 | 170 | This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */ |
AnnaBridge | 163:e59c8e839560 | 171 | |
AnnaBridge | 163:e59c8e839560 | 172 | uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. |
AnnaBridge | 163:e59c8e839560 | 173 | If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS |
AnnaBridge | 163:e59c8e839560 | 174 | If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE |
AnnaBridge | 163:e59c8e839560 | 175 | @note If waveform automatic generation mode is disabled, this parameter is discarded. |
AnnaBridge | 163:e59c8e839560 | 176 | |
AnnaBridge | 163:e59c8e839560 | 177 | This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */ |
AnnaBridge | 163:e59c8e839560 | 178 | |
AnnaBridge | 163:e59c8e839560 | 179 | uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. |
AnnaBridge | 163:e59c8e839560 | 180 | This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER |
AnnaBridge | 163:e59c8e839560 | 181 | |
AnnaBridge | 163:e59c8e839560 | 182 | This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */ |
AnnaBridge | 163:e59c8e839560 | 183 | |
AnnaBridge | 163:e59c8e839560 | 184 | } LL_DAC_InitTypeDef; |
AnnaBridge | 163:e59c8e839560 | 185 | |
AnnaBridge | 163:e59c8e839560 | 186 | /** |
AnnaBridge | 163:e59c8e839560 | 187 | * @} |
AnnaBridge | 163:e59c8e839560 | 188 | */ |
AnnaBridge | 163:e59c8e839560 | 189 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 163:e59c8e839560 | 190 | |
AnnaBridge | 163:e59c8e839560 | 191 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 192 | /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants |
AnnaBridge | 163:e59c8e839560 | 193 | * @{ |
AnnaBridge | 163:e59c8e839560 | 194 | */ |
AnnaBridge | 163:e59c8e839560 | 195 | |
AnnaBridge | 163:e59c8e839560 | 196 | /** @defgroup DAC_LL_EC_GET_FLAG DAC flags |
AnnaBridge | 163:e59c8e839560 | 197 | * @brief Flags defines which can be used with LL_DAC_ReadReg function |
AnnaBridge | 163:e59c8e839560 | 198 | * @{ |
AnnaBridge | 163:e59c8e839560 | 199 | */ |
AnnaBridge | 163:e59c8e839560 | 200 | /* DAC channel 1 flags */ |
AnnaBridge | 163:e59c8e839560 | 201 | #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ |
AnnaBridge | 163:e59c8e839560 | 202 | |
AnnaBridge | 163:e59c8e839560 | 203 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 163:e59c8e839560 | 204 | /* DAC channel 2 flags */ |
AnnaBridge | 163:e59c8e839560 | 205 | #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ |
AnnaBridge | 163:e59c8e839560 | 206 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 163:e59c8e839560 | 207 | /** |
AnnaBridge | 163:e59c8e839560 | 208 | * @} |
AnnaBridge | 163:e59c8e839560 | 209 | */ |
AnnaBridge | 163:e59c8e839560 | 210 | |
AnnaBridge | 163:e59c8e839560 | 211 | /** @defgroup DAC_LL_EC_IT DAC interruptions |
AnnaBridge | 163:e59c8e839560 | 212 | * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions |
AnnaBridge | 163:e59c8e839560 | 213 | * @{ |
AnnaBridge | 163:e59c8e839560 | 214 | */ |
AnnaBridge | 163:e59c8e839560 | 215 | #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ |
AnnaBridge | 163:e59c8e839560 | 216 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 163:e59c8e839560 | 217 | #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ |
AnnaBridge | 163:e59c8e839560 | 218 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 163:e59c8e839560 | 219 | /** |
AnnaBridge | 163:e59c8e839560 | 220 | * @} |
AnnaBridge | 163:e59c8e839560 | 221 | */ |
AnnaBridge | 163:e59c8e839560 | 222 | |
AnnaBridge | 163:e59c8e839560 | 223 | /** @defgroup DAC_LL_EC_CHANNEL DAC channels |
AnnaBridge | 163:e59c8e839560 | 224 | * @{ |
AnnaBridge | 163:e59c8e839560 | 225 | */ |
AnnaBridge | 163:e59c8e839560 | 226 | #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ |
AnnaBridge | 163:e59c8e839560 | 227 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 163:e59c8e839560 | 228 | #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ |
AnnaBridge | 163:e59c8e839560 | 229 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 163:e59c8e839560 | 230 | /** |
AnnaBridge | 163:e59c8e839560 | 231 | * @} |
AnnaBridge | 163:e59c8e839560 | 232 | */ |
AnnaBridge | 163:e59c8e839560 | 233 | |
AnnaBridge | 163:e59c8e839560 | 234 | /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source |
AnnaBridge | 163:e59c8e839560 | 235 | * @{ |
AnnaBridge | 163:e59c8e839560 | 236 | */ |
AnnaBridge | 163:e59c8e839560 | 237 | #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ |
AnnaBridge | 163:e59c8e839560 | 238 | #if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) |
AnnaBridge | 163:e59c8e839560 | 239 | #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 240 | #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM3_TRGO for TIM3 selection. */ |
AnnaBridge | 163:e59c8e839560 | 241 | #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 242 | #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 243 | #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 244 | #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 245 | #define LL_DAC_TRIG_EXT_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM3_TRGO) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM8_TRGO for TIM8 selection. */ |
AnnaBridge | 163:e59c8e839560 | 246 | #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ |
AnnaBridge | 163:e59c8e839560 | 247 | |
AnnaBridge | 163:e59c8e839560 | 248 | #elif defined(STM32F303x8) || defined(STM32F328xx) |
AnnaBridge | 163:e59c8e839560 | 249 | #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 250 | #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 251 | #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 252 | #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 253 | #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 254 | #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ |
AnnaBridge | 163:e59c8e839560 | 255 | |
AnnaBridge | 163:e59c8e839560 | 256 | #elif defined(STM32F302xE) || defined(STM32F302xC) || defined(STM32F302x8) |
AnnaBridge | 163:e59c8e839560 | 257 | #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 258 | #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 259 | #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 260 | #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 261 | #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 ) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 262 | #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ |
AnnaBridge | 163:e59c8e839560 | 263 | |
AnnaBridge | 163:e59c8e839560 | 264 | #elif defined(STM32F301x8) || defined(STM32F318xx) |
AnnaBridge | 163:e59c8e839560 | 265 | #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 266 | #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 267 | #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 268 | #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ |
AnnaBridge | 163:e59c8e839560 | 269 | |
AnnaBridge | 163:e59c8e839560 | 270 | #elif defined(STM32F373xC) || defined(STM32F378xx) |
AnnaBridge | 163:e59c8e839560 | 271 | #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 272 | #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 273 | #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 274 | #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 275 | #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 276 | #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 277 | #define LL_DAC_TRIG_EXT_TIM18_TRGO (LL_DAC_TRIG_EXT_TIM5_TRGO) /*!< DAC channel conversion trigger from external IP: TIM18 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 278 | #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ |
AnnaBridge | 163:e59c8e839560 | 279 | |
AnnaBridge | 163:e59c8e839560 | 280 | #elif defined(STM32F334x8) |
AnnaBridge | 163:e59c8e839560 | 281 | #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 282 | #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM3_TRGO for TIM3 selection. */ |
AnnaBridge | 163:e59c8e839560 | 283 | #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 284 | #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ |
AnnaBridge | 163:e59c8e839560 | 285 | #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG3_REMAP_TIM15_TRGO for TIM15 selection. */ |
AnnaBridge | 163:e59c8e839560 | 286 | #define LL_DAC_TRIGGER_HRTIM1_DACTRG1 (LL_DAC_TRIG_EXT_TIM15_TRGO) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG1. Available only on DAC instance: DAC1. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG3_REMAP_HRTIM1_DAC1_TRIG1 for HRTIM1 TRIG1 selection. */ |
AnnaBridge | 163:e59c8e839560 | 287 | #define LL_DAC_TRIGGER_HRTIM1_DACTRG2 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG2. Available only on DAC instance: DAC2. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG5_REMAP_HRTIM1_DAC1_TRIG2 for HRTIM1 TRIG2 selection. */ |
AnnaBridge | 163:e59c8e839560 | 288 | #define LL_DAC_TRIGGER_HRTIM1_DACTRG3 (LL_DAC_TRIGGER_HRTIM1_DACTRG2) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG3. */ |
AnnaBridge | 163:e59c8e839560 | 289 | #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ |
AnnaBridge | 163:e59c8e839560 | 290 | |
AnnaBridge | 163:e59c8e839560 | 291 | #endif |
AnnaBridge | 163:e59c8e839560 | 292 | /** |
AnnaBridge | 163:e59c8e839560 | 293 | * @} |
AnnaBridge | 163:e59c8e839560 | 294 | */ |
AnnaBridge | 163:e59c8e839560 | 295 | |
AnnaBridge | 163:e59c8e839560 | 296 | /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode |
AnnaBridge | 163:e59c8e839560 | 297 | * @{ |
AnnaBridge | 163:e59c8e839560 | 298 | */ |
AnnaBridge | 163:e59c8e839560 | 299 | #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */ |
AnnaBridge | 163:e59c8e839560 | 300 | #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ |
AnnaBridge | 163:e59c8e839560 | 301 | #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ |
AnnaBridge | 163:e59c8e839560 | 302 | /** |
AnnaBridge | 163:e59c8e839560 | 303 | * @} |
AnnaBridge | 163:e59c8e839560 | 304 | */ |
AnnaBridge | 163:e59c8e839560 | 305 | |
AnnaBridge | 163:e59c8e839560 | 306 | /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits |
AnnaBridge | 163:e59c8e839560 | 307 | * @{ |
AnnaBridge | 163:e59c8e839560 | 308 | */ |
AnnaBridge | 163:e59c8e839560 | 309 | #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 310 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 311 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 312 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 313 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 314 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 315 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 316 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 317 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 318 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 319 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 320 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 321 | /** |
AnnaBridge | 163:e59c8e839560 | 322 | * @} |
AnnaBridge | 163:e59c8e839560 | 323 | */ |
AnnaBridge | 163:e59c8e839560 | 324 | |
AnnaBridge | 163:e59c8e839560 | 325 | /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude |
AnnaBridge | 163:e59c8e839560 | 326 | * @{ |
AnnaBridge | 163:e59c8e839560 | 327 | */ |
AnnaBridge | 163:e59c8e839560 | 328 | #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 329 | #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 330 | #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 331 | #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 332 | #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 333 | #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 334 | #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 335 | #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 336 | #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 337 | #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 338 | #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 339 | #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 163:e59c8e839560 | 340 | /** |
AnnaBridge | 163:e59c8e839560 | 341 | * @} |
AnnaBridge | 163:e59c8e839560 | 342 | */ |
AnnaBridge | 163:e59c8e839560 | 343 | |
AnnaBridge | 163:e59c8e839560 | 344 | /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer |
AnnaBridge | 163:e59c8e839560 | 345 | * @{ |
AnnaBridge | 163:e59c8e839560 | 346 | */ |
AnnaBridge | 163:e59c8e839560 | 347 | #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ |
AnnaBridge | 163:e59c8e839560 | 348 | #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ |
AnnaBridge | 163:e59c8e839560 | 349 | |
AnnaBridge | 163:e59c8e839560 | 350 | #if defined(DAC_CR_OUTEN1) || defined(DAC_CR_OUTEN2) |
AnnaBridge | 163:e59c8e839560 | 351 | #define LL_DAC_OUTPUT_SWITCH_DISABLE (LL_DAC_OUTPUT_BUFFER_ENABLE) /*!< Feature specific to STM32F303x6/8 and STM32F328: On DAC1 channel 2, output buffer is replaced by a switch to connect DAC channel output to pin PA5. On DAC2 channel 1, output buffer is replaced by a switch to connect DAC channel output to pin PA6. Selection of switch disabled: DAC channel output not connected to GPIO. */ |
AnnaBridge | 163:e59c8e839560 | 352 | #define LL_DAC_OUTPUT_SWITCH_ENABLE (LL_DAC_OUTPUT_BUFFER_DISABLE) /*!< Feature specific to STM32F303x6/8 and STM32F328: On DAC1 channel 2, output buffer is replaced by a switch to connect DAC channel output to pin PA5. On DAC2 channel 1, output buffer is replaced by a switch to connect DAC channel output to pin PA6. */ |
AnnaBridge | 163:e59c8e839560 | 353 | #endif |
AnnaBridge | 163:e59c8e839560 | 354 | /** |
AnnaBridge | 163:e59c8e839560 | 355 | * @} |
AnnaBridge | 163:e59c8e839560 | 356 | */ |
AnnaBridge | 163:e59c8e839560 | 357 | |
AnnaBridge | 163:e59c8e839560 | 358 | |
AnnaBridge | 163:e59c8e839560 | 359 | /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution |
AnnaBridge | 163:e59c8e839560 | 360 | * @{ |
AnnaBridge | 163:e59c8e839560 | 361 | */ |
AnnaBridge | 163:e59c8e839560 | 362 | #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */ |
AnnaBridge | 163:e59c8e839560 | 363 | #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */ |
AnnaBridge | 163:e59c8e839560 | 364 | /** |
AnnaBridge | 163:e59c8e839560 | 365 | * @} |
AnnaBridge | 163:e59c8e839560 | 366 | */ |
AnnaBridge | 163:e59c8e839560 | 367 | |
AnnaBridge | 163:e59c8e839560 | 368 | /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose |
AnnaBridge | 163:e59c8e839560 | 369 | * @{ |
AnnaBridge | 163:e59c8e839560 | 370 | */ |
AnnaBridge | 163:e59c8e839560 | 371 | /* List of DAC registers intended to be used (most commonly) with */ |
AnnaBridge | 163:e59c8e839560 | 372 | /* DMA transfer. */ |
AnnaBridge | 163:e59c8e839560 | 373 | /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ |
AnnaBridge | 163:e59c8e839560 | 374 | #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */ |
AnnaBridge | 163:e59c8e839560 | 375 | #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */ |
AnnaBridge | 163:e59c8e839560 | 376 | #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */ |
AnnaBridge | 163:e59c8e839560 | 377 | /** |
AnnaBridge | 163:e59c8e839560 | 378 | * @} |
AnnaBridge | 163:e59c8e839560 | 379 | */ |
AnnaBridge | 163:e59c8e839560 | 380 | |
AnnaBridge | 163:e59c8e839560 | 381 | /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays |
AnnaBridge | 163:e59c8e839560 | 382 | * @note Only DAC IP HW delays are defined in DAC LL driver driver, |
AnnaBridge | 163:e59c8e839560 | 383 | * not timeout values. |
AnnaBridge | 163:e59c8e839560 | 384 | * For details on delays values, refer to descriptions in source code |
AnnaBridge | 163:e59c8e839560 | 385 | * above each literal definition. |
AnnaBridge | 163:e59c8e839560 | 386 | * @{ |
AnnaBridge | 163:e59c8e839560 | 387 | */ |
AnnaBridge | 163:e59c8e839560 | 388 | |
AnnaBridge | 163:e59c8e839560 | 389 | /* Delay for DAC channel voltage settling time from DAC channel startup */ |
AnnaBridge | 163:e59c8e839560 | 390 | /* (transition from disable to enable). */ |
AnnaBridge | 163:e59c8e839560 | 391 | /* Note: DAC channel startup time depends on board application environment: */ |
AnnaBridge | 163:e59c8e839560 | 392 | /* impedance connected to DAC channel output. */ |
AnnaBridge | 163:e59c8e839560 | 393 | /* The delay below is specified under conditions: */ |
AnnaBridge | 163:e59c8e839560 | 394 | /* - voltage maximum transition (lowest to highest value) */ |
AnnaBridge | 163:e59c8e839560 | 395 | /* - until voltage reaches final value +-1LSB */ |
AnnaBridge | 163:e59c8e839560 | 396 | /* - DAC channel output buffer enabled */ |
AnnaBridge | 163:e59c8e839560 | 397 | /* - load impedance of 5kOhm (min), 50pF (max) */ |
AnnaBridge | 163:e59c8e839560 | 398 | /* Literal set to maximum value (refer to device datasheet, */ |
AnnaBridge | 163:e59c8e839560 | 399 | /* parameter "tWAKEUP"). */ |
AnnaBridge | 163:e59c8e839560 | 400 | /* Unit: us */ |
AnnaBridge | 163:e59c8e839560 | 401 | #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ |
AnnaBridge | 163:e59c8e839560 | 402 | |
AnnaBridge | 163:e59c8e839560 | 403 | /* Delay for DAC channel voltage settling time. */ |
AnnaBridge | 163:e59c8e839560 | 404 | /* Note: DAC channel startup time depends on board application environment: */ |
AnnaBridge | 163:e59c8e839560 | 405 | /* impedance connected to DAC channel output. */ |
AnnaBridge | 163:e59c8e839560 | 406 | /* The delay below is specified under conditions: */ |
AnnaBridge | 163:e59c8e839560 | 407 | /* - voltage maximum transition (lowest to highest value) */ |
AnnaBridge | 163:e59c8e839560 | 408 | /* - until voltage reaches final value +-1LSB */ |
AnnaBridge | 163:e59c8e839560 | 409 | /* - DAC channel output buffer enabled */ |
AnnaBridge | 163:e59c8e839560 | 410 | /* - load impedance of 5kOhm min, 50pF max */ |
AnnaBridge | 163:e59c8e839560 | 411 | /* Literal set to maximum value (refer to device datasheet, */ |
AnnaBridge | 163:e59c8e839560 | 412 | /* parameter "tSETTLING"). */ |
AnnaBridge | 163:e59c8e839560 | 413 | /* Unit: us */ |
AnnaBridge | 163:e59c8e839560 | 414 | #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */ |
AnnaBridge | 163:e59c8e839560 | 415 | /** |
AnnaBridge | 163:e59c8e839560 | 416 | * @} |
AnnaBridge | 163:e59c8e839560 | 417 | */ |
AnnaBridge | 163:e59c8e839560 | 418 | |
AnnaBridge | 163:e59c8e839560 | 419 | /** |
AnnaBridge | 163:e59c8e839560 | 420 | * @} |
AnnaBridge | 163:e59c8e839560 | 421 | */ |
AnnaBridge | 163:e59c8e839560 | 422 | |
AnnaBridge | 163:e59c8e839560 | 423 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 424 | /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros |
AnnaBridge | 163:e59c8e839560 | 425 | * @{ |
AnnaBridge | 163:e59c8e839560 | 426 | */ |
AnnaBridge | 163:e59c8e839560 | 427 | |
AnnaBridge | 163:e59c8e839560 | 428 | /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros |
AnnaBridge | 163:e59c8e839560 | 429 | * @{ |
AnnaBridge | 163:e59c8e839560 | 430 | */ |
AnnaBridge | 163:e59c8e839560 | 431 | |
AnnaBridge | 163:e59c8e839560 | 432 | /** |
AnnaBridge | 163:e59c8e839560 | 433 | * @brief Write a value in DAC register |
AnnaBridge | 163:e59c8e839560 | 434 | * @param __INSTANCE__ DAC Instance |
AnnaBridge | 163:e59c8e839560 | 435 | * @param __REG__ Register to be written |
AnnaBridge | 163:e59c8e839560 | 436 | * @param __VALUE__ Value to be written in the register |
AnnaBridge | 163:e59c8e839560 | 437 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 438 | */ |
AnnaBridge | 163:e59c8e839560 | 439 | #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
AnnaBridge | 163:e59c8e839560 | 440 | |
AnnaBridge | 163:e59c8e839560 | 441 | /** |
AnnaBridge | 163:e59c8e839560 | 442 | * @brief Read a value in DAC register |
AnnaBridge | 163:e59c8e839560 | 443 | * @param __INSTANCE__ DAC Instance |
AnnaBridge | 163:e59c8e839560 | 444 | * @param __REG__ Register to be read |
AnnaBridge | 163:e59c8e839560 | 445 | * @retval Register value |
AnnaBridge | 163:e59c8e839560 | 446 | */ |
AnnaBridge | 163:e59c8e839560 | 447 | #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
AnnaBridge | 163:e59c8e839560 | 448 | |
AnnaBridge | 163:e59c8e839560 | 449 | /** |
AnnaBridge | 163:e59c8e839560 | 450 | * @} |
AnnaBridge | 163:e59c8e839560 | 451 | */ |
AnnaBridge | 163:e59c8e839560 | 452 | |
AnnaBridge | 163:e59c8e839560 | 453 | /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro |
AnnaBridge | 163:e59c8e839560 | 454 | * @{ |
AnnaBridge | 163:e59c8e839560 | 455 | */ |
AnnaBridge | 163:e59c8e839560 | 456 | |
AnnaBridge | 163:e59c8e839560 | 457 | /** |
AnnaBridge | 163:e59c8e839560 | 458 | * @brief Helper macro to get DAC channel number in decimal format |
AnnaBridge | 163:e59c8e839560 | 459 | * from literals LL_DAC_CHANNEL_x. |
AnnaBridge | 163:e59c8e839560 | 460 | * Example: |
AnnaBridge | 163:e59c8e839560 | 461 | * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) |
AnnaBridge | 163:e59c8e839560 | 462 | * will return decimal number "1". |
AnnaBridge | 163:e59c8e839560 | 463 | * @note The input can be a value from functions where a channel |
AnnaBridge | 163:e59c8e839560 | 464 | * number is returned. |
AnnaBridge | 163:e59c8e839560 | 465 | * @param __CHANNEL__ This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 466 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 467 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 468 | * |
AnnaBridge | 163:e59c8e839560 | 469 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 470 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 471 | * @retval 1...2 (value "2" depending on DAC channel 2 availability) |
AnnaBridge | 163:e59c8e839560 | 472 | */ |
AnnaBridge | 163:e59c8e839560 | 473 | #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ |
AnnaBridge | 163:e59c8e839560 | 474 | ((__CHANNEL__) & DAC_SWTR_CHX_MASK) |
AnnaBridge | 163:e59c8e839560 | 475 | |
AnnaBridge | 163:e59c8e839560 | 476 | /** |
AnnaBridge | 163:e59c8e839560 | 477 | * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x |
AnnaBridge | 163:e59c8e839560 | 478 | * from number in decimal format. |
AnnaBridge | 163:e59c8e839560 | 479 | * Example: |
AnnaBridge | 163:e59c8e839560 | 480 | * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) |
AnnaBridge | 163:e59c8e839560 | 481 | * will return a data equivalent to "LL_DAC_CHANNEL_1". |
AnnaBridge | 163:e59c8e839560 | 482 | * @note If the input parameter does not correspond to a DAC channel, |
AnnaBridge | 163:e59c8e839560 | 483 | * this macro returns value '0'. |
AnnaBridge | 163:e59c8e839560 | 484 | * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability) |
AnnaBridge | 163:e59c8e839560 | 485 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 486 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 487 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 488 | * |
AnnaBridge | 163:e59c8e839560 | 489 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 490 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 491 | */ |
AnnaBridge | 163:e59c8e839560 | 492 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 163:e59c8e839560 | 493 | #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ |
AnnaBridge | 163:e59c8e839560 | 494 | (((__DECIMAL_NB__) == 1U) \ |
AnnaBridge | 163:e59c8e839560 | 495 | ? ( \ |
AnnaBridge | 163:e59c8e839560 | 496 | LL_DAC_CHANNEL_1 \ |
AnnaBridge | 163:e59c8e839560 | 497 | ) \ |
AnnaBridge | 163:e59c8e839560 | 498 | : \ |
AnnaBridge | 163:e59c8e839560 | 499 | (((__DECIMAL_NB__) == 2U) \ |
AnnaBridge | 163:e59c8e839560 | 500 | ? ( \ |
AnnaBridge | 163:e59c8e839560 | 501 | LL_DAC_CHANNEL_2 \ |
AnnaBridge | 163:e59c8e839560 | 502 | ) \ |
AnnaBridge | 163:e59c8e839560 | 503 | : \ |
AnnaBridge | 163:e59c8e839560 | 504 | ( \ |
AnnaBridge | 163:e59c8e839560 | 505 | 0 \ |
AnnaBridge | 163:e59c8e839560 | 506 | ) \ |
AnnaBridge | 163:e59c8e839560 | 507 | ) \ |
AnnaBridge | 163:e59c8e839560 | 508 | ) |
AnnaBridge | 163:e59c8e839560 | 509 | #else |
AnnaBridge | 163:e59c8e839560 | 510 | #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ |
AnnaBridge | 163:e59c8e839560 | 511 | (((__DECIMAL_NB__) == 1U) \ |
AnnaBridge | 163:e59c8e839560 | 512 | ? ( \ |
AnnaBridge | 163:e59c8e839560 | 513 | LL_DAC_CHANNEL_1 \ |
AnnaBridge | 163:e59c8e839560 | 514 | ) \ |
AnnaBridge | 163:e59c8e839560 | 515 | : \ |
AnnaBridge | 163:e59c8e839560 | 516 | ( \ |
AnnaBridge | 163:e59c8e839560 | 517 | 0 \ |
AnnaBridge | 163:e59c8e839560 | 518 | ) \ |
AnnaBridge | 163:e59c8e839560 | 519 | ) |
AnnaBridge | 163:e59c8e839560 | 520 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 163:e59c8e839560 | 521 | |
AnnaBridge | 163:e59c8e839560 | 522 | /** |
AnnaBridge | 163:e59c8e839560 | 523 | * @brief Helper macro to define the DAC conversion data full-scale digital |
AnnaBridge | 163:e59c8e839560 | 524 | * value corresponding to the selected DAC resolution. |
AnnaBridge | 163:e59c8e839560 | 525 | * @note DAC conversion data full-scale corresponds to voltage range |
AnnaBridge | 163:e59c8e839560 | 526 | * determined by analog voltage references Vref+ and Vref- |
AnnaBridge | 163:e59c8e839560 | 527 | * (refer to reference manual). |
AnnaBridge | 163:e59c8e839560 | 528 | * @param __DAC_RESOLUTION__ This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 529 | * @arg @ref LL_DAC_RESOLUTION_12B |
AnnaBridge | 163:e59c8e839560 | 530 | * @arg @ref LL_DAC_RESOLUTION_8B |
AnnaBridge | 163:e59c8e839560 | 531 | * @retval ADC conversion data equivalent voltage value (unit: mVolt) |
AnnaBridge | 163:e59c8e839560 | 532 | */ |
AnnaBridge | 163:e59c8e839560 | 533 | #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ |
AnnaBridge | 163:e59c8e839560 | 534 | ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U)) |
AnnaBridge | 163:e59c8e839560 | 535 | |
AnnaBridge | 163:e59c8e839560 | 536 | /** |
AnnaBridge | 163:e59c8e839560 | 537 | * @brief Helper macro to calculate the DAC conversion data (unit: digital |
AnnaBridge | 163:e59c8e839560 | 538 | * value) corresponding to a voltage (unit: mVolt). |
AnnaBridge | 163:e59c8e839560 | 539 | * @note This helper macro is intended to provide input data in voltage |
AnnaBridge | 163:e59c8e839560 | 540 | * rather than digital value, |
AnnaBridge | 163:e59c8e839560 | 541 | * to be used with LL DAC functions such as |
AnnaBridge | 163:e59c8e839560 | 542 | * @ref LL_DAC_ConvertData12RightAligned(). |
AnnaBridge | 163:e59c8e839560 | 543 | * @note Analog reference voltage (Vref+) must be either known from |
AnnaBridge | 163:e59c8e839560 | 544 | * user board environment or can be calculated using ADC measurement |
AnnaBridge | 163:e59c8e839560 | 545 | * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). |
AnnaBridge | 163:e59c8e839560 | 546 | * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) |
AnnaBridge | 163:e59c8e839560 | 547 | * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel |
AnnaBridge | 163:e59c8e839560 | 548 | * (unit: mVolt). |
AnnaBridge | 163:e59c8e839560 | 549 | * @param __DAC_RESOLUTION__ This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 550 | * @arg @ref LL_DAC_RESOLUTION_12B |
AnnaBridge | 163:e59c8e839560 | 551 | * @arg @ref LL_DAC_RESOLUTION_8B |
AnnaBridge | 163:e59c8e839560 | 552 | * @retval DAC conversion data (unit: digital value) |
AnnaBridge | 163:e59c8e839560 | 553 | */ |
AnnaBridge | 163:e59c8e839560 | 554 | #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ |
AnnaBridge | 163:e59c8e839560 | 555 | __DAC_VOLTAGE__,\ |
AnnaBridge | 163:e59c8e839560 | 556 | __DAC_RESOLUTION__) \ |
AnnaBridge | 163:e59c8e839560 | 557 | ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ |
AnnaBridge | 163:e59c8e839560 | 558 | / (__VREFANALOG_VOLTAGE__) \ |
AnnaBridge | 163:e59c8e839560 | 559 | ) |
AnnaBridge | 163:e59c8e839560 | 560 | |
AnnaBridge | 163:e59c8e839560 | 561 | /** |
AnnaBridge | 163:e59c8e839560 | 562 | * @} |
AnnaBridge | 163:e59c8e839560 | 563 | */ |
AnnaBridge | 163:e59c8e839560 | 564 | |
AnnaBridge | 163:e59c8e839560 | 565 | /** |
AnnaBridge | 163:e59c8e839560 | 566 | * @} |
AnnaBridge | 163:e59c8e839560 | 567 | */ |
AnnaBridge | 163:e59c8e839560 | 568 | |
AnnaBridge | 163:e59c8e839560 | 569 | |
AnnaBridge | 163:e59c8e839560 | 570 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 571 | /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions |
AnnaBridge | 163:e59c8e839560 | 572 | * @{ |
AnnaBridge | 163:e59c8e839560 | 573 | */ |
AnnaBridge | 163:e59c8e839560 | 574 | /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels |
AnnaBridge | 163:e59c8e839560 | 575 | * @{ |
AnnaBridge | 163:e59c8e839560 | 576 | */ |
AnnaBridge | 163:e59c8e839560 | 577 | |
AnnaBridge | 163:e59c8e839560 | 578 | /** |
AnnaBridge | 163:e59c8e839560 | 579 | * @brief Set the conversion trigger source for the selected DAC channel. |
AnnaBridge | 163:e59c8e839560 | 580 | * @note For conversion trigger source to be effective, DAC trigger |
AnnaBridge | 163:e59c8e839560 | 581 | * must be enabled using function @ref LL_DAC_EnableTrigger(). |
AnnaBridge | 163:e59c8e839560 | 582 | * @note To set conversion trigger source, DAC channel must be disabled. |
AnnaBridge | 163:e59c8e839560 | 583 | * Otherwise, the setting is discarded. |
AnnaBridge | 163:e59c8e839560 | 584 | * @note Availability of parameters of trigger sources from timer |
AnnaBridge | 163:e59c8e839560 | 585 | * depends on timers availability on the selected device. |
AnnaBridge | 163:e59c8e839560 | 586 | * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n |
AnnaBridge | 163:e59c8e839560 | 587 | * CR TSEL2 LL_DAC_SetTriggerSource |
AnnaBridge | 163:e59c8e839560 | 588 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 589 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 590 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 591 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 592 | * |
AnnaBridge | 163:e59c8e839560 | 593 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 594 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 595 | * @param TriggerSource This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 596 | * @arg @ref LL_DAC_TRIG_SOFTWARE |
AnnaBridge | 163:e59c8e839560 | 597 | * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO |
AnnaBridge | 163:e59c8e839560 | 598 | * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO (1) |
AnnaBridge | 163:e59c8e839560 | 599 | * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO (1) |
AnnaBridge | 163:e59c8e839560 | 600 | * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO (1) |
AnnaBridge | 163:e59c8e839560 | 601 | * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO |
AnnaBridge | 163:e59c8e839560 | 602 | * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO (1) |
AnnaBridge | 163:e59c8e839560 | 603 | * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (1) |
AnnaBridge | 163:e59c8e839560 | 604 | * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO (1) |
AnnaBridge | 163:e59c8e839560 | 605 | * @arg @ref LL_DAC_TRIG_EXT_TIM18_TRGO (1) |
AnnaBridge | 163:e59c8e839560 | 606 | * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG1 (1) |
AnnaBridge | 163:e59c8e839560 | 607 | * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG2 (1)(2) |
AnnaBridge | 163:e59c8e839560 | 608 | * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG3 (1) (3) |
AnnaBridge | 163:e59c8e839560 | 609 | * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 |
AnnaBridge | 163:e59c8e839560 | 610 | * |
AnnaBridge | 163:e59c8e839560 | 611 | * (1) On STM32F3, parameter not available on all devices |
AnnaBridge | 163:e59c8e839560 | 612 | * (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).\n |
AnnaBridge | 163:e59c8e839560 | 613 | * (3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device). |
AnnaBridge | 163:e59c8e839560 | 614 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 615 | */ |
AnnaBridge | 163:e59c8e839560 | 616 | __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource) |
AnnaBridge | 163:e59c8e839560 | 617 | { |
AnnaBridge | 163:e59c8e839560 | 618 | MODIFY_REG(DACx->CR, |
AnnaBridge | 163:e59c8e839560 | 619 | DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
AnnaBridge | 163:e59c8e839560 | 620 | TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 163:e59c8e839560 | 621 | } |
AnnaBridge | 163:e59c8e839560 | 622 | |
AnnaBridge | 163:e59c8e839560 | 623 | /** |
AnnaBridge | 163:e59c8e839560 | 624 | * @brief Get the conversion trigger source for the selected DAC channel. |
AnnaBridge | 163:e59c8e839560 | 625 | * @note For conversion trigger source to be effective, DAC trigger |
AnnaBridge | 163:e59c8e839560 | 626 | * must be enabled using function @ref LL_DAC_EnableTrigger(). |
AnnaBridge | 163:e59c8e839560 | 627 | * @note Availability of parameters of trigger sources from timer |
AnnaBridge | 163:e59c8e839560 | 628 | * depends on timers availability on the selected device. |
AnnaBridge | 163:e59c8e839560 | 629 | * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n |
AnnaBridge | 163:e59c8e839560 | 630 | * CR TSEL2 LL_DAC_GetTriggerSource |
AnnaBridge | 163:e59c8e839560 | 631 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 632 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 633 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 634 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 635 | * |
AnnaBridge | 163:e59c8e839560 | 636 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 637 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 638 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 639 | * @arg @ref LL_DAC_TRIG_SOFTWARE |
AnnaBridge | 163:e59c8e839560 | 640 | * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO |
AnnaBridge | 163:e59c8e839560 | 641 | * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO (1) |
AnnaBridge | 163:e59c8e839560 | 642 | * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO (1) |
AnnaBridge | 163:e59c8e839560 | 643 | * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO (1) |
AnnaBridge | 163:e59c8e839560 | 644 | * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO |
AnnaBridge | 163:e59c8e839560 | 645 | * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO (1) |
AnnaBridge | 163:e59c8e839560 | 646 | * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (1) |
AnnaBridge | 163:e59c8e839560 | 647 | * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO (1) |
AnnaBridge | 163:e59c8e839560 | 648 | * @arg @ref LL_DAC_TRIG_EXT_TIM18_TRGO (1) |
AnnaBridge | 163:e59c8e839560 | 649 | * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG1 (1) |
AnnaBridge | 163:e59c8e839560 | 650 | * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG2 (1)(2) |
AnnaBridge | 163:e59c8e839560 | 651 | * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG3 (1) (3) |
AnnaBridge | 163:e59c8e839560 | 652 | * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 |
AnnaBridge | 163:e59c8e839560 | 653 | * |
AnnaBridge | 163:e59c8e839560 | 654 | * (1) On STM32F3, parameter not available on all devices |
AnnaBridge | 163:e59c8e839560 | 655 | * (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).\n |
AnnaBridge | 163:e59c8e839560 | 656 | * (3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device). |
AnnaBridge | 163:e59c8e839560 | 657 | */ |
AnnaBridge | 163:e59c8e839560 | 658 | __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 163:e59c8e839560 | 659 | { |
AnnaBridge | 163:e59c8e839560 | 660 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 163:e59c8e839560 | 661 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
AnnaBridge | 163:e59c8e839560 | 662 | ); |
AnnaBridge | 163:e59c8e839560 | 663 | } |
AnnaBridge | 163:e59c8e839560 | 664 | |
AnnaBridge | 163:e59c8e839560 | 665 | /** |
AnnaBridge | 163:e59c8e839560 | 666 | * @brief Set the waveform automatic generation mode |
AnnaBridge | 163:e59c8e839560 | 667 | * for the selected DAC channel. |
AnnaBridge | 163:e59c8e839560 | 668 | * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n |
AnnaBridge | 163:e59c8e839560 | 669 | * CR WAVE2 LL_DAC_SetWaveAutoGeneration |
AnnaBridge | 163:e59c8e839560 | 670 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 671 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 672 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 673 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 674 | * |
AnnaBridge | 163:e59c8e839560 | 675 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 676 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 677 | * @param WaveAutoGeneration This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 678 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE |
AnnaBridge | 163:e59c8e839560 | 679 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE |
AnnaBridge | 163:e59c8e839560 | 680 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE |
AnnaBridge | 163:e59c8e839560 | 681 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 682 | */ |
AnnaBridge | 163:e59c8e839560 | 683 | __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration) |
AnnaBridge | 163:e59c8e839560 | 684 | { |
AnnaBridge | 163:e59c8e839560 | 685 | MODIFY_REG(DACx->CR, |
AnnaBridge | 163:e59c8e839560 | 686 | DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
AnnaBridge | 163:e59c8e839560 | 687 | WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 163:e59c8e839560 | 688 | } |
AnnaBridge | 163:e59c8e839560 | 689 | |
AnnaBridge | 163:e59c8e839560 | 690 | /** |
AnnaBridge | 163:e59c8e839560 | 691 | * @brief Get the waveform automatic generation mode |
AnnaBridge | 163:e59c8e839560 | 692 | * for the selected DAC channel. |
AnnaBridge | 163:e59c8e839560 | 693 | * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n |
AnnaBridge | 163:e59c8e839560 | 694 | * CR WAVE2 LL_DAC_GetWaveAutoGeneration |
AnnaBridge | 163:e59c8e839560 | 695 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 696 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 697 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 698 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 699 | * |
AnnaBridge | 163:e59c8e839560 | 700 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 701 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 702 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 703 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE |
AnnaBridge | 163:e59c8e839560 | 704 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE |
AnnaBridge | 163:e59c8e839560 | 705 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE |
AnnaBridge | 163:e59c8e839560 | 706 | */ |
AnnaBridge | 163:e59c8e839560 | 707 | __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 163:e59c8e839560 | 708 | { |
AnnaBridge | 163:e59c8e839560 | 709 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 163:e59c8e839560 | 710 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
AnnaBridge | 163:e59c8e839560 | 711 | ); |
AnnaBridge | 163:e59c8e839560 | 712 | } |
AnnaBridge | 163:e59c8e839560 | 713 | |
AnnaBridge | 163:e59c8e839560 | 714 | /** |
AnnaBridge | 163:e59c8e839560 | 715 | * @brief Set the noise waveform generation for the selected DAC channel: |
AnnaBridge | 163:e59c8e839560 | 716 | * Noise mode and parameters LFSR (linear feedback shift register). |
AnnaBridge | 163:e59c8e839560 | 717 | * @note For wave generation to be effective, DAC channel |
AnnaBridge | 163:e59c8e839560 | 718 | * wave generation mode must be enabled using |
AnnaBridge | 163:e59c8e839560 | 719 | * function @ref LL_DAC_SetWaveAutoGeneration(). |
AnnaBridge | 163:e59c8e839560 | 720 | * @note This setting can be set when the selected DAC channel is disabled |
AnnaBridge | 163:e59c8e839560 | 721 | * (otherwise, the setting operation is ignored). |
AnnaBridge | 163:e59c8e839560 | 722 | * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n |
AnnaBridge | 163:e59c8e839560 | 723 | * CR MAMP2 LL_DAC_SetWaveNoiseLFSR |
AnnaBridge | 163:e59c8e839560 | 724 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 725 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 726 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 727 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 728 | * |
AnnaBridge | 163:e59c8e839560 | 729 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 730 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 731 | * @param NoiseLFSRMask This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 732 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 |
AnnaBridge | 163:e59c8e839560 | 733 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 |
AnnaBridge | 163:e59c8e839560 | 734 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 |
AnnaBridge | 163:e59c8e839560 | 735 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 |
AnnaBridge | 163:e59c8e839560 | 736 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 |
AnnaBridge | 163:e59c8e839560 | 737 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 |
AnnaBridge | 163:e59c8e839560 | 738 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 |
AnnaBridge | 163:e59c8e839560 | 739 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 |
AnnaBridge | 163:e59c8e839560 | 740 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 |
AnnaBridge | 163:e59c8e839560 | 741 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 |
AnnaBridge | 163:e59c8e839560 | 742 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 |
AnnaBridge | 163:e59c8e839560 | 743 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 |
AnnaBridge | 163:e59c8e839560 | 744 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 745 | */ |
AnnaBridge | 163:e59c8e839560 | 746 | __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask) |
AnnaBridge | 163:e59c8e839560 | 747 | { |
AnnaBridge | 163:e59c8e839560 | 748 | MODIFY_REG(DACx->CR, |
AnnaBridge | 163:e59c8e839560 | 749 | DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
AnnaBridge | 163:e59c8e839560 | 750 | NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 163:e59c8e839560 | 751 | } |
AnnaBridge | 163:e59c8e839560 | 752 | |
AnnaBridge | 163:e59c8e839560 | 753 | /** |
AnnaBridge | 163:e59c8e839560 | 754 | * @brief Set the noise waveform generation for the selected DAC channel: |
AnnaBridge | 163:e59c8e839560 | 755 | * Noise mode and parameters LFSR (linear feedback shift register). |
AnnaBridge | 163:e59c8e839560 | 756 | * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n |
AnnaBridge | 163:e59c8e839560 | 757 | * CR MAMP2 LL_DAC_GetWaveNoiseLFSR |
AnnaBridge | 163:e59c8e839560 | 758 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 759 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 760 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 761 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 762 | * |
AnnaBridge | 163:e59c8e839560 | 763 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 764 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 765 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 766 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 |
AnnaBridge | 163:e59c8e839560 | 767 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 |
AnnaBridge | 163:e59c8e839560 | 768 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 |
AnnaBridge | 163:e59c8e839560 | 769 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 |
AnnaBridge | 163:e59c8e839560 | 770 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 |
AnnaBridge | 163:e59c8e839560 | 771 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 |
AnnaBridge | 163:e59c8e839560 | 772 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 |
AnnaBridge | 163:e59c8e839560 | 773 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 |
AnnaBridge | 163:e59c8e839560 | 774 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 |
AnnaBridge | 163:e59c8e839560 | 775 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 |
AnnaBridge | 163:e59c8e839560 | 776 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 |
AnnaBridge | 163:e59c8e839560 | 777 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 |
AnnaBridge | 163:e59c8e839560 | 778 | */ |
AnnaBridge | 163:e59c8e839560 | 779 | __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 163:e59c8e839560 | 780 | { |
AnnaBridge | 163:e59c8e839560 | 781 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 163:e59c8e839560 | 782 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
AnnaBridge | 163:e59c8e839560 | 783 | ); |
AnnaBridge | 163:e59c8e839560 | 784 | } |
AnnaBridge | 163:e59c8e839560 | 785 | |
AnnaBridge | 163:e59c8e839560 | 786 | /** |
AnnaBridge | 163:e59c8e839560 | 787 | * @brief Set the triangle waveform generation for the selected DAC channel: |
AnnaBridge | 163:e59c8e839560 | 788 | * triangle mode and amplitude. |
AnnaBridge | 163:e59c8e839560 | 789 | * @note For wave generation to be effective, DAC channel |
AnnaBridge | 163:e59c8e839560 | 790 | * wave generation mode must be enabled using |
AnnaBridge | 163:e59c8e839560 | 791 | * function @ref LL_DAC_SetWaveAutoGeneration(). |
AnnaBridge | 163:e59c8e839560 | 792 | * @note This setting can be set when the selected DAC channel is disabled |
AnnaBridge | 163:e59c8e839560 | 793 | * (otherwise, the setting operation is ignored). |
AnnaBridge | 163:e59c8e839560 | 794 | * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n |
AnnaBridge | 163:e59c8e839560 | 795 | * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude |
AnnaBridge | 163:e59c8e839560 | 796 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 797 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 798 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 799 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 800 | * |
AnnaBridge | 163:e59c8e839560 | 801 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 802 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 803 | * @param TriangleAmplitude This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 804 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 |
AnnaBridge | 163:e59c8e839560 | 805 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 |
AnnaBridge | 163:e59c8e839560 | 806 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 |
AnnaBridge | 163:e59c8e839560 | 807 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 |
AnnaBridge | 163:e59c8e839560 | 808 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 |
AnnaBridge | 163:e59c8e839560 | 809 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 |
AnnaBridge | 163:e59c8e839560 | 810 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 |
AnnaBridge | 163:e59c8e839560 | 811 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 |
AnnaBridge | 163:e59c8e839560 | 812 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 |
AnnaBridge | 163:e59c8e839560 | 813 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 |
AnnaBridge | 163:e59c8e839560 | 814 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 |
AnnaBridge | 163:e59c8e839560 | 815 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 |
AnnaBridge | 163:e59c8e839560 | 816 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 817 | */ |
AnnaBridge | 163:e59c8e839560 | 818 | __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude) |
AnnaBridge | 163:e59c8e839560 | 819 | { |
AnnaBridge | 163:e59c8e839560 | 820 | MODIFY_REG(DACx->CR, |
AnnaBridge | 163:e59c8e839560 | 821 | DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
AnnaBridge | 163:e59c8e839560 | 822 | TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 163:e59c8e839560 | 823 | } |
AnnaBridge | 163:e59c8e839560 | 824 | |
AnnaBridge | 163:e59c8e839560 | 825 | /** |
AnnaBridge | 163:e59c8e839560 | 826 | * @brief Set the triangle waveform generation for the selected DAC channel: |
AnnaBridge | 163:e59c8e839560 | 827 | * triangle mode and amplitude. |
AnnaBridge | 163:e59c8e839560 | 828 | * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n |
AnnaBridge | 163:e59c8e839560 | 829 | * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude |
AnnaBridge | 163:e59c8e839560 | 830 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 831 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 832 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 833 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 834 | * |
AnnaBridge | 163:e59c8e839560 | 835 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 836 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 837 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 838 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 |
AnnaBridge | 163:e59c8e839560 | 839 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 |
AnnaBridge | 163:e59c8e839560 | 840 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 |
AnnaBridge | 163:e59c8e839560 | 841 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 |
AnnaBridge | 163:e59c8e839560 | 842 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 |
AnnaBridge | 163:e59c8e839560 | 843 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 |
AnnaBridge | 163:e59c8e839560 | 844 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 |
AnnaBridge | 163:e59c8e839560 | 845 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 |
AnnaBridge | 163:e59c8e839560 | 846 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 |
AnnaBridge | 163:e59c8e839560 | 847 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 |
AnnaBridge | 163:e59c8e839560 | 848 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 |
AnnaBridge | 163:e59c8e839560 | 849 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 |
AnnaBridge | 163:e59c8e839560 | 850 | */ |
AnnaBridge | 163:e59c8e839560 | 851 | __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 163:e59c8e839560 | 852 | { |
AnnaBridge | 163:e59c8e839560 | 853 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 163:e59c8e839560 | 854 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
AnnaBridge | 163:e59c8e839560 | 855 | ); |
AnnaBridge | 163:e59c8e839560 | 856 | } |
AnnaBridge | 163:e59c8e839560 | 857 | |
AnnaBridge | 163:e59c8e839560 | 858 | /** |
AnnaBridge | 163:e59c8e839560 | 859 | * @brief Set the output buffer for the selected DAC channel. |
AnnaBridge | 163:e59c8e839560 | 860 | * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n |
AnnaBridge | 163:e59c8e839560 | 861 | * CR BOFF2 LL_DAC_SetOutputBuffer |
AnnaBridge | 163:e59c8e839560 | 862 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 863 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 864 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 865 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 866 | * |
AnnaBridge | 163:e59c8e839560 | 867 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 868 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 869 | * @param OutputBuffer This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 870 | * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE |
AnnaBridge | 163:e59c8e839560 | 871 | * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE |
AnnaBridge | 163:e59c8e839560 | 872 | * @arg @ref LL_DAC_OUTPUT_SWITCH_DISABLE (1) |
AnnaBridge | 163:e59c8e839560 | 873 | * @arg @ref LL_DAC_OUTPUT_SWITCH_ENABLE (1) |
AnnaBridge | 163:e59c8e839560 | 874 | * |
AnnaBridge | 163:e59c8e839560 | 875 | * (1) Feature specific to STM32F303x6/8 and STM32F328: |
AnnaBridge | 163:e59c8e839560 | 876 | * On DAC1 channel 2, output buffer is replaced by a switch |
AnnaBridge | 163:e59c8e839560 | 877 | * to connect DAC channel output to pin PA5. |
AnnaBridge | 163:e59c8e839560 | 878 | * On DAC2 channel 1, output buffer is replaced by a switch |
AnnaBridge | 163:e59c8e839560 | 879 | * to connect DAC channel output to pin PA6. |
AnnaBridge | 163:e59c8e839560 | 880 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 881 | */ |
AnnaBridge | 163:e59c8e839560 | 882 | __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) |
AnnaBridge | 163:e59c8e839560 | 883 | { |
AnnaBridge | 163:e59c8e839560 | 884 | MODIFY_REG(DACx->CR, |
AnnaBridge | 163:e59c8e839560 | 885 | DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
AnnaBridge | 163:e59c8e839560 | 886 | OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 163:e59c8e839560 | 887 | } |
AnnaBridge | 163:e59c8e839560 | 888 | |
AnnaBridge | 163:e59c8e839560 | 889 | /** |
AnnaBridge | 163:e59c8e839560 | 890 | * @brief Get the output buffer state for the selected DAC channel. |
AnnaBridge | 163:e59c8e839560 | 891 | * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n |
AnnaBridge | 163:e59c8e839560 | 892 | * CR BOFF2 LL_DAC_GetOutputBuffer |
AnnaBridge | 163:e59c8e839560 | 893 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 894 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 895 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 896 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 897 | * |
AnnaBridge | 163:e59c8e839560 | 898 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 899 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 900 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 901 | * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE |
AnnaBridge | 163:e59c8e839560 | 902 | * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE |
AnnaBridge | 163:e59c8e839560 | 903 | * @arg @ref LL_DAC_OUTPUT_SWITCH_DISABLE (1) |
AnnaBridge | 163:e59c8e839560 | 904 | * @arg @ref LL_DAC_OUTPUT_SWITCH_ENABLE (1) |
AnnaBridge | 163:e59c8e839560 | 905 | * |
AnnaBridge | 163:e59c8e839560 | 906 | * (1) Feature specific to STM32F303x6/8 and STM32F328: |
AnnaBridge | 163:e59c8e839560 | 907 | * On DAC1 channel 2, output buffer is replaced by a switch |
AnnaBridge | 163:e59c8e839560 | 908 | * to connect DAC channel output to pin PA5. |
AnnaBridge | 163:e59c8e839560 | 909 | * On DAC2 channel 1, output buffer is replaced by a switch |
AnnaBridge | 163:e59c8e839560 | 910 | * to connect DAC channel output to pin PA6. |
AnnaBridge | 163:e59c8e839560 | 911 | */ |
AnnaBridge | 163:e59c8e839560 | 912 | __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 163:e59c8e839560 | 913 | { |
AnnaBridge | 163:e59c8e839560 | 914 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 163:e59c8e839560 | 915 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
AnnaBridge | 163:e59c8e839560 | 916 | ); |
AnnaBridge | 163:e59c8e839560 | 917 | } |
AnnaBridge | 163:e59c8e839560 | 918 | |
AnnaBridge | 163:e59c8e839560 | 919 | /** |
AnnaBridge | 163:e59c8e839560 | 920 | * @} |
AnnaBridge | 163:e59c8e839560 | 921 | */ |
AnnaBridge | 163:e59c8e839560 | 922 | |
AnnaBridge | 163:e59c8e839560 | 923 | /** @defgroup DAC_LL_EF_DMA_Management DMA Management |
AnnaBridge | 163:e59c8e839560 | 924 | * @{ |
AnnaBridge | 163:e59c8e839560 | 925 | */ |
AnnaBridge | 163:e59c8e839560 | 926 | |
AnnaBridge | 163:e59c8e839560 | 927 | /** |
AnnaBridge | 163:e59c8e839560 | 928 | * @brief Enable DAC DMA transfer request of the selected channel. |
AnnaBridge | 163:e59c8e839560 | 929 | * @note To configure DMA source address (peripheral address), |
AnnaBridge | 163:e59c8e839560 | 930 | * use function @ref LL_DAC_DMA_GetRegAddr(). |
AnnaBridge | 163:e59c8e839560 | 931 | * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n |
AnnaBridge | 163:e59c8e839560 | 932 | * CR DMAEN2 LL_DAC_EnableDMAReq |
AnnaBridge | 163:e59c8e839560 | 933 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 934 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 935 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 936 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 937 | * |
AnnaBridge | 163:e59c8e839560 | 938 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 939 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 940 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 941 | */ |
AnnaBridge | 163:e59c8e839560 | 942 | __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 163:e59c8e839560 | 943 | { |
AnnaBridge | 163:e59c8e839560 | 944 | SET_BIT(DACx->CR, |
AnnaBridge | 163:e59c8e839560 | 945 | DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 163:e59c8e839560 | 946 | } |
AnnaBridge | 163:e59c8e839560 | 947 | |
AnnaBridge | 163:e59c8e839560 | 948 | /** |
AnnaBridge | 163:e59c8e839560 | 949 | * @brief Disable DAC DMA transfer request of the selected channel. |
AnnaBridge | 163:e59c8e839560 | 950 | * @note To configure DMA source address (peripheral address), |
AnnaBridge | 163:e59c8e839560 | 951 | * use function @ref LL_DAC_DMA_GetRegAddr(). |
AnnaBridge | 163:e59c8e839560 | 952 | * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n |
AnnaBridge | 163:e59c8e839560 | 953 | * CR DMAEN2 LL_DAC_DisableDMAReq |
AnnaBridge | 163:e59c8e839560 | 954 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 955 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 956 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 957 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 958 | * |
AnnaBridge | 163:e59c8e839560 | 959 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 960 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 961 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 962 | */ |
AnnaBridge | 163:e59c8e839560 | 963 | __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 163:e59c8e839560 | 964 | { |
AnnaBridge | 163:e59c8e839560 | 965 | CLEAR_BIT(DACx->CR, |
AnnaBridge | 163:e59c8e839560 | 966 | DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 163:e59c8e839560 | 967 | } |
AnnaBridge | 163:e59c8e839560 | 968 | |
AnnaBridge | 163:e59c8e839560 | 969 | /** |
AnnaBridge | 163:e59c8e839560 | 970 | * @brief Get DAC DMA transfer request state of the selected channel. |
AnnaBridge | 163:e59c8e839560 | 971 | * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) |
AnnaBridge | 163:e59c8e839560 | 972 | * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n |
AnnaBridge | 163:e59c8e839560 | 973 | * CR DMAEN2 LL_DAC_IsDMAReqEnabled |
AnnaBridge | 163:e59c8e839560 | 974 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 975 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 976 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 977 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 978 | * |
AnnaBridge | 163:e59c8e839560 | 979 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 980 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 981 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 982 | */ |
AnnaBridge | 163:e59c8e839560 | 983 | __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 163:e59c8e839560 | 984 | { |
AnnaBridge | 163:e59c8e839560 | 985 | return (READ_BIT(DACx->CR, |
AnnaBridge | 163:e59c8e839560 | 986 | DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 163:e59c8e839560 | 987 | == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); |
AnnaBridge | 163:e59c8e839560 | 988 | } |
AnnaBridge | 163:e59c8e839560 | 989 | |
AnnaBridge | 163:e59c8e839560 | 990 | /** |
AnnaBridge | 163:e59c8e839560 | 991 | * @brief Function to help to configure DMA transfer to DAC: retrieve the |
AnnaBridge | 163:e59c8e839560 | 992 | * DAC register address from DAC instance and a list of DAC registers |
AnnaBridge | 163:e59c8e839560 | 993 | * intended to be used (most commonly) with DMA transfer. |
AnnaBridge | 163:e59c8e839560 | 994 | * @note These DAC registers are data holding registers: |
AnnaBridge | 163:e59c8e839560 | 995 | * when DAC conversion is requested, DAC generates a DMA transfer |
AnnaBridge | 163:e59c8e839560 | 996 | * request to have data available in DAC data holding registers. |
AnnaBridge | 163:e59c8e839560 | 997 | * @note This macro is intended to be used with LL DMA driver, refer to |
AnnaBridge | 163:e59c8e839560 | 998 | * function "LL_DMA_ConfigAddresses()". |
AnnaBridge | 163:e59c8e839560 | 999 | * Example: |
AnnaBridge | 163:e59c8e839560 | 1000 | * LL_DMA_ConfigAddresses(DMA1, |
AnnaBridge | 163:e59c8e839560 | 1001 | * LL_DMA_CHANNEL_1, |
AnnaBridge | 163:e59c8e839560 | 1002 | * (uint32_t)&< array or variable >, |
AnnaBridge | 163:e59c8e839560 | 1003 | * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), |
AnnaBridge | 163:e59c8e839560 | 1004 | * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); |
AnnaBridge | 163:e59c8e839560 | 1005 | * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n |
AnnaBridge | 163:e59c8e839560 | 1006 | * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n |
AnnaBridge | 163:e59c8e839560 | 1007 | * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n |
AnnaBridge | 163:e59c8e839560 | 1008 | * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n |
AnnaBridge | 163:e59c8e839560 | 1009 | * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n |
AnnaBridge | 163:e59c8e839560 | 1010 | * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr |
AnnaBridge | 163:e59c8e839560 | 1011 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1012 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1013 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 1014 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 1015 | * |
AnnaBridge | 163:e59c8e839560 | 1016 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 1017 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 1018 | * @param Register This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1019 | * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED |
AnnaBridge | 163:e59c8e839560 | 1020 | * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED |
AnnaBridge | 163:e59c8e839560 | 1021 | * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED |
AnnaBridge | 163:e59c8e839560 | 1022 | * @retval DAC register address |
AnnaBridge | 163:e59c8e839560 | 1023 | */ |
AnnaBridge | 163:e59c8e839560 | 1024 | __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) |
AnnaBridge | 163:e59c8e839560 | 1025 | { |
AnnaBridge | 163:e59c8e839560 | 1026 | /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ |
AnnaBridge | 163:e59c8e839560 | 1027 | /* DAC channel selected. */ |
AnnaBridge | 163:e59c8e839560 | 1028 | return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register)))); |
AnnaBridge | 163:e59c8e839560 | 1029 | } |
AnnaBridge | 163:e59c8e839560 | 1030 | /** |
AnnaBridge | 163:e59c8e839560 | 1031 | * @} |
AnnaBridge | 163:e59c8e839560 | 1032 | */ |
AnnaBridge | 163:e59c8e839560 | 1033 | |
AnnaBridge | 163:e59c8e839560 | 1034 | /** @defgroup DAC_LL_EF_Operation Operation on DAC channels |
AnnaBridge | 163:e59c8e839560 | 1035 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1036 | */ |
AnnaBridge | 163:e59c8e839560 | 1037 | |
AnnaBridge | 163:e59c8e839560 | 1038 | /** |
AnnaBridge | 163:e59c8e839560 | 1039 | * @brief Enable DAC selected channel. |
AnnaBridge | 163:e59c8e839560 | 1040 | * @rmtoll CR EN1 LL_DAC_Enable\n |
AnnaBridge | 163:e59c8e839560 | 1041 | * CR EN2 LL_DAC_Enable |
AnnaBridge | 163:e59c8e839560 | 1042 | * @note After enable from off state, DAC channel requires a delay |
AnnaBridge | 163:e59c8e839560 | 1043 | * for output voltage to reach accuracy +/- 1 LSB. |
AnnaBridge | 163:e59c8e839560 | 1044 | * Refer to device datasheet, parameter "tWAKEUP". |
AnnaBridge | 163:e59c8e839560 | 1045 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1046 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1047 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 1048 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 1049 | * |
AnnaBridge | 163:e59c8e839560 | 1050 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 1051 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 1052 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1053 | */ |
AnnaBridge | 163:e59c8e839560 | 1054 | __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 163:e59c8e839560 | 1055 | { |
AnnaBridge | 163:e59c8e839560 | 1056 | SET_BIT(DACx->CR, |
AnnaBridge | 163:e59c8e839560 | 1057 | DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 163:e59c8e839560 | 1058 | } |
AnnaBridge | 163:e59c8e839560 | 1059 | |
AnnaBridge | 163:e59c8e839560 | 1060 | /** |
AnnaBridge | 163:e59c8e839560 | 1061 | * @brief Disable DAC selected channel. |
AnnaBridge | 163:e59c8e839560 | 1062 | * @rmtoll CR EN1 LL_DAC_Disable\n |
AnnaBridge | 163:e59c8e839560 | 1063 | * CR EN2 LL_DAC_Disable |
AnnaBridge | 163:e59c8e839560 | 1064 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1065 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1066 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 1067 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 1068 | * |
AnnaBridge | 163:e59c8e839560 | 1069 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 1070 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 1071 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1072 | */ |
AnnaBridge | 163:e59c8e839560 | 1073 | __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 163:e59c8e839560 | 1074 | { |
AnnaBridge | 163:e59c8e839560 | 1075 | CLEAR_BIT(DACx->CR, |
AnnaBridge | 163:e59c8e839560 | 1076 | DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 163:e59c8e839560 | 1077 | } |
AnnaBridge | 163:e59c8e839560 | 1078 | |
AnnaBridge | 163:e59c8e839560 | 1079 | /** |
AnnaBridge | 163:e59c8e839560 | 1080 | * @brief Get DAC enable state of the selected channel. |
AnnaBridge | 163:e59c8e839560 | 1081 | * (0: DAC channel is disabled, 1: DAC channel is enabled) |
AnnaBridge | 163:e59c8e839560 | 1082 | * @rmtoll CR EN1 LL_DAC_IsEnabled\n |
AnnaBridge | 163:e59c8e839560 | 1083 | * CR EN2 LL_DAC_IsEnabled |
AnnaBridge | 163:e59c8e839560 | 1084 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1085 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1086 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 1087 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 1088 | * |
AnnaBridge | 163:e59c8e839560 | 1089 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 1090 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 1091 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 1092 | */ |
AnnaBridge | 163:e59c8e839560 | 1093 | __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 163:e59c8e839560 | 1094 | { |
AnnaBridge | 163:e59c8e839560 | 1095 | return (READ_BIT(DACx->CR, |
AnnaBridge | 163:e59c8e839560 | 1096 | DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 163:e59c8e839560 | 1097 | == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); |
AnnaBridge | 163:e59c8e839560 | 1098 | } |
AnnaBridge | 163:e59c8e839560 | 1099 | |
AnnaBridge | 163:e59c8e839560 | 1100 | /** |
AnnaBridge | 163:e59c8e839560 | 1101 | * @brief Enable DAC trigger of the selected channel. |
AnnaBridge | 163:e59c8e839560 | 1102 | * @note - If DAC trigger is disabled, DAC conversion is performed |
AnnaBridge | 163:e59c8e839560 | 1103 | * automatically once the data holding register is updated, |
AnnaBridge | 163:e59c8e839560 | 1104 | * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": |
AnnaBridge | 163:e59c8e839560 | 1105 | * @ref LL_DAC_ConvertData12RightAligned(), ... |
AnnaBridge | 163:e59c8e839560 | 1106 | * - If DAC trigger is enabled, DAC conversion is performed |
AnnaBridge | 163:e59c8e839560 | 1107 | * only when a hardware of software trigger event is occurring. |
AnnaBridge | 163:e59c8e839560 | 1108 | * Select trigger source using |
AnnaBridge | 163:e59c8e839560 | 1109 | * function @ref LL_DAC_SetTriggerSource(). |
AnnaBridge | 163:e59c8e839560 | 1110 | * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n |
AnnaBridge | 163:e59c8e839560 | 1111 | * CR TEN2 LL_DAC_EnableTrigger |
AnnaBridge | 163:e59c8e839560 | 1112 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1113 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1114 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 1115 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 1116 | * |
AnnaBridge | 163:e59c8e839560 | 1117 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 1118 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 1119 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1120 | */ |
AnnaBridge | 163:e59c8e839560 | 1121 | __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 163:e59c8e839560 | 1122 | { |
AnnaBridge | 163:e59c8e839560 | 1123 | SET_BIT(DACx->CR, |
AnnaBridge | 163:e59c8e839560 | 1124 | DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 163:e59c8e839560 | 1125 | } |
AnnaBridge | 163:e59c8e839560 | 1126 | |
AnnaBridge | 163:e59c8e839560 | 1127 | /** |
AnnaBridge | 163:e59c8e839560 | 1128 | * @brief Disable DAC trigger of the selected channel. |
AnnaBridge | 163:e59c8e839560 | 1129 | * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n |
AnnaBridge | 163:e59c8e839560 | 1130 | * CR TEN2 LL_DAC_DisableTrigger |
AnnaBridge | 163:e59c8e839560 | 1131 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1132 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1133 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 1134 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 1135 | * |
AnnaBridge | 163:e59c8e839560 | 1136 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 1137 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 1138 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1139 | */ |
AnnaBridge | 163:e59c8e839560 | 1140 | __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 163:e59c8e839560 | 1141 | { |
AnnaBridge | 163:e59c8e839560 | 1142 | CLEAR_BIT(DACx->CR, |
AnnaBridge | 163:e59c8e839560 | 1143 | DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 163:e59c8e839560 | 1144 | } |
AnnaBridge | 163:e59c8e839560 | 1145 | |
AnnaBridge | 163:e59c8e839560 | 1146 | /** |
AnnaBridge | 163:e59c8e839560 | 1147 | * @brief Get DAC trigger state of the selected channel. |
AnnaBridge | 163:e59c8e839560 | 1148 | * (0: DAC trigger is disabled, 1: DAC trigger is enabled) |
AnnaBridge | 163:e59c8e839560 | 1149 | * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n |
AnnaBridge | 163:e59c8e839560 | 1150 | * CR TEN2 LL_DAC_IsTriggerEnabled |
AnnaBridge | 163:e59c8e839560 | 1151 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1152 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1153 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 1154 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 1155 | * |
AnnaBridge | 163:e59c8e839560 | 1156 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 1157 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 1158 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 1159 | */ |
AnnaBridge | 163:e59c8e839560 | 1160 | __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 163:e59c8e839560 | 1161 | { |
AnnaBridge | 163:e59c8e839560 | 1162 | return (READ_BIT(DACx->CR, |
AnnaBridge | 163:e59c8e839560 | 1163 | DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 163:e59c8e839560 | 1164 | == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); |
AnnaBridge | 163:e59c8e839560 | 1165 | } |
AnnaBridge | 163:e59c8e839560 | 1166 | |
AnnaBridge | 163:e59c8e839560 | 1167 | /** |
AnnaBridge | 163:e59c8e839560 | 1168 | * @brief Trig DAC conversion by software for the selected DAC channel. |
AnnaBridge | 163:e59c8e839560 | 1169 | * @note Preliminarily, DAC trigger must be set to software trigger |
AnnaBridge | 163:e59c8e839560 | 1170 | * using function @ref LL_DAC_SetTriggerSource() |
AnnaBridge | 163:e59c8e839560 | 1171 | * with parameter "LL_DAC_TRIGGER_SOFTWARE". |
AnnaBridge | 163:e59c8e839560 | 1172 | * and DAC trigger must be enabled using |
AnnaBridge | 163:e59c8e839560 | 1173 | * function @ref LL_DAC_EnableTrigger(). |
AnnaBridge | 163:e59c8e839560 | 1174 | * @note For devices featuring DAC with 2 channels: this function |
AnnaBridge | 163:e59c8e839560 | 1175 | * can perform a SW start of both DAC channels simultaneously. |
AnnaBridge | 163:e59c8e839560 | 1176 | * Two channels can be selected as parameter. |
AnnaBridge | 163:e59c8e839560 | 1177 | * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2) |
AnnaBridge | 163:e59c8e839560 | 1178 | * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n |
AnnaBridge | 163:e59c8e839560 | 1179 | * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion |
AnnaBridge | 163:e59c8e839560 | 1180 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1181 | * @param DAC_Channel This parameter can a combination of the following values: |
AnnaBridge | 163:e59c8e839560 | 1182 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 1183 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 1184 | * |
AnnaBridge | 163:e59c8e839560 | 1185 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 1186 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 1187 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1188 | */ |
AnnaBridge | 163:e59c8e839560 | 1189 | __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 163:e59c8e839560 | 1190 | { |
AnnaBridge | 163:e59c8e839560 | 1191 | SET_BIT(DACx->SWTRIGR, |
AnnaBridge | 163:e59c8e839560 | 1192 | (DAC_Channel & DAC_SWTR_CHX_MASK)); |
AnnaBridge | 163:e59c8e839560 | 1193 | } |
AnnaBridge | 163:e59c8e839560 | 1194 | |
AnnaBridge | 163:e59c8e839560 | 1195 | /** |
AnnaBridge | 163:e59c8e839560 | 1196 | * @brief Set the data to be loaded in the data holding register |
AnnaBridge | 163:e59c8e839560 | 1197 | * in format 12 bits left alignment (LSB aligned on bit 0), |
AnnaBridge | 163:e59c8e839560 | 1198 | * for the selected DAC channel. |
AnnaBridge | 163:e59c8e839560 | 1199 | * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n |
AnnaBridge | 163:e59c8e839560 | 1200 | * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned |
AnnaBridge | 163:e59c8e839560 | 1201 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1202 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1203 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 1204 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 1205 | * |
AnnaBridge | 163:e59c8e839560 | 1206 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 1207 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 1208 | * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF |
AnnaBridge | 163:e59c8e839560 | 1209 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1210 | */ |
AnnaBridge | 163:e59c8e839560 | 1211 | __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) |
AnnaBridge | 163:e59c8e839560 | 1212 | { |
AnnaBridge | 163:e59c8e839560 | 1213 | register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK)); |
AnnaBridge | 163:e59c8e839560 | 1214 | |
AnnaBridge | 163:e59c8e839560 | 1215 | MODIFY_REG(*preg, |
AnnaBridge | 163:e59c8e839560 | 1216 | DAC_DHR12R1_DACC1DHR, |
AnnaBridge | 163:e59c8e839560 | 1217 | Data); |
AnnaBridge | 163:e59c8e839560 | 1218 | } |
AnnaBridge | 163:e59c8e839560 | 1219 | |
AnnaBridge | 163:e59c8e839560 | 1220 | /** |
AnnaBridge | 163:e59c8e839560 | 1221 | * @brief Set the data to be loaded in the data holding register |
AnnaBridge | 163:e59c8e839560 | 1222 | * in format 12 bits left alignment (MSB aligned on bit 15), |
AnnaBridge | 163:e59c8e839560 | 1223 | * for the selected DAC channel. |
AnnaBridge | 163:e59c8e839560 | 1224 | * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n |
AnnaBridge | 163:e59c8e839560 | 1225 | * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned |
AnnaBridge | 163:e59c8e839560 | 1226 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1227 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1228 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 1229 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 1230 | * |
AnnaBridge | 163:e59c8e839560 | 1231 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 1232 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 1233 | * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF |
AnnaBridge | 163:e59c8e839560 | 1234 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1235 | */ |
AnnaBridge | 163:e59c8e839560 | 1236 | __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) |
AnnaBridge | 163:e59c8e839560 | 1237 | { |
AnnaBridge | 163:e59c8e839560 | 1238 | register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK)); |
AnnaBridge | 163:e59c8e839560 | 1239 | |
AnnaBridge | 163:e59c8e839560 | 1240 | MODIFY_REG(*preg, |
AnnaBridge | 163:e59c8e839560 | 1241 | DAC_DHR12L1_DACC1DHR, |
AnnaBridge | 163:e59c8e839560 | 1242 | Data); |
AnnaBridge | 163:e59c8e839560 | 1243 | } |
AnnaBridge | 163:e59c8e839560 | 1244 | |
AnnaBridge | 163:e59c8e839560 | 1245 | /** |
AnnaBridge | 163:e59c8e839560 | 1246 | * @brief Set the data to be loaded in the data holding register |
AnnaBridge | 163:e59c8e839560 | 1247 | * in format 8 bits left alignment (LSB aligned on bit 0), |
AnnaBridge | 163:e59c8e839560 | 1248 | * for the selected DAC channel. |
AnnaBridge | 163:e59c8e839560 | 1249 | * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n |
AnnaBridge | 163:e59c8e839560 | 1250 | * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned |
AnnaBridge | 163:e59c8e839560 | 1251 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1252 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1253 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 1254 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 1255 | * |
AnnaBridge | 163:e59c8e839560 | 1256 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 1257 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 1258 | * @param Data Value between Min_Data=0x00 and Max_Data=0xFF |
AnnaBridge | 163:e59c8e839560 | 1259 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1260 | */ |
AnnaBridge | 163:e59c8e839560 | 1261 | __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) |
AnnaBridge | 163:e59c8e839560 | 1262 | { |
AnnaBridge | 163:e59c8e839560 | 1263 | register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK)); |
AnnaBridge | 163:e59c8e839560 | 1264 | |
AnnaBridge | 163:e59c8e839560 | 1265 | MODIFY_REG(*preg, |
AnnaBridge | 163:e59c8e839560 | 1266 | DAC_DHR8R1_DACC1DHR, |
AnnaBridge | 163:e59c8e839560 | 1267 | Data); |
AnnaBridge | 163:e59c8e839560 | 1268 | } |
AnnaBridge | 163:e59c8e839560 | 1269 | |
AnnaBridge | 163:e59c8e839560 | 1270 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 163:e59c8e839560 | 1271 | /** |
AnnaBridge | 163:e59c8e839560 | 1272 | * @brief Set the data to be loaded in the data holding register |
AnnaBridge | 163:e59c8e839560 | 1273 | * in format 12 bits left alignment (LSB aligned on bit 0), |
AnnaBridge | 163:e59c8e839560 | 1274 | * for both DAC channels. |
AnnaBridge | 163:e59c8e839560 | 1275 | * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n |
AnnaBridge | 163:e59c8e839560 | 1276 | * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned |
AnnaBridge | 163:e59c8e839560 | 1277 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1278 | * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF |
AnnaBridge | 163:e59c8e839560 | 1279 | * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF |
AnnaBridge | 163:e59c8e839560 | 1280 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1281 | */ |
AnnaBridge | 163:e59c8e839560 | 1282 | __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) |
AnnaBridge | 163:e59c8e839560 | 1283 | { |
AnnaBridge | 163:e59c8e839560 | 1284 | MODIFY_REG(DACx->DHR12RD, |
AnnaBridge | 163:e59c8e839560 | 1285 | (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), |
AnnaBridge | 163:e59c8e839560 | 1286 | ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); |
AnnaBridge | 163:e59c8e839560 | 1287 | } |
AnnaBridge | 163:e59c8e839560 | 1288 | |
AnnaBridge | 163:e59c8e839560 | 1289 | /** |
AnnaBridge | 163:e59c8e839560 | 1290 | * @brief Set the data to be loaded in the data holding register |
AnnaBridge | 163:e59c8e839560 | 1291 | * in format 12 bits left alignment (MSB aligned on bit 15), |
AnnaBridge | 163:e59c8e839560 | 1292 | * for both DAC channels. |
AnnaBridge | 163:e59c8e839560 | 1293 | * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n |
AnnaBridge | 163:e59c8e839560 | 1294 | * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned |
AnnaBridge | 163:e59c8e839560 | 1295 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1296 | * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF |
AnnaBridge | 163:e59c8e839560 | 1297 | * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF |
AnnaBridge | 163:e59c8e839560 | 1298 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1299 | */ |
AnnaBridge | 163:e59c8e839560 | 1300 | __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) |
AnnaBridge | 163:e59c8e839560 | 1301 | { |
AnnaBridge | 163:e59c8e839560 | 1302 | /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ |
AnnaBridge | 163:e59c8e839560 | 1303 | /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ |
AnnaBridge | 163:e59c8e839560 | 1304 | /* the 4 LSB must be taken into account for the shift value. */ |
AnnaBridge | 163:e59c8e839560 | 1305 | MODIFY_REG(DACx->DHR12LD, |
AnnaBridge | 163:e59c8e839560 | 1306 | (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR), |
AnnaBridge | 163:e59c8e839560 | 1307 | ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1)); |
AnnaBridge | 163:e59c8e839560 | 1308 | } |
AnnaBridge | 163:e59c8e839560 | 1309 | |
AnnaBridge | 163:e59c8e839560 | 1310 | /** |
AnnaBridge | 163:e59c8e839560 | 1311 | * @brief Set the data to be loaded in the data holding register |
AnnaBridge | 163:e59c8e839560 | 1312 | * in format 8 bits left alignment (LSB aligned on bit 0), |
AnnaBridge | 163:e59c8e839560 | 1313 | * for both DAC channels. |
AnnaBridge | 163:e59c8e839560 | 1314 | * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n |
AnnaBridge | 163:e59c8e839560 | 1315 | * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned |
AnnaBridge | 163:e59c8e839560 | 1316 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1317 | * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF |
AnnaBridge | 163:e59c8e839560 | 1318 | * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF |
AnnaBridge | 163:e59c8e839560 | 1319 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1320 | */ |
AnnaBridge | 163:e59c8e839560 | 1321 | __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) |
AnnaBridge | 163:e59c8e839560 | 1322 | { |
AnnaBridge | 163:e59c8e839560 | 1323 | MODIFY_REG(DACx->DHR8RD, |
AnnaBridge | 163:e59c8e839560 | 1324 | (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), |
AnnaBridge | 163:e59c8e839560 | 1325 | ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); |
AnnaBridge | 163:e59c8e839560 | 1326 | } |
AnnaBridge | 163:e59c8e839560 | 1327 | |
AnnaBridge | 163:e59c8e839560 | 1328 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 163:e59c8e839560 | 1329 | /** |
AnnaBridge | 163:e59c8e839560 | 1330 | * @brief Retrieve output data currently generated for the selected DAC channel. |
AnnaBridge | 163:e59c8e839560 | 1331 | * @note Whatever alignment and resolution settings |
AnnaBridge | 163:e59c8e839560 | 1332 | * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": |
AnnaBridge | 163:e59c8e839560 | 1333 | * @ref LL_DAC_ConvertData12RightAligned(), ...), |
AnnaBridge | 163:e59c8e839560 | 1334 | * output data format is 12 bits right aligned (LSB aligned on bit 0). |
AnnaBridge | 163:e59c8e839560 | 1335 | * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n |
AnnaBridge | 163:e59c8e839560 | 1336 | * DOR2 DACC2DOR LL_DAC_RetrieveOutputData |
AnnaBridge | 163:e59c8e839560 | 1337 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1338 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1339 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 163:e59c8e839560 | 1340 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 163:e59c8e839560 | 1341 | * |
AnnaBridge | 163:e59c8e839560 | 1342 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 163:e59c8e839560 | 1343 | * Refer to device datasheet for channels availability. |
AnnaBridge | 163:e59c8e839560 | 1344 | * @retval Value between Min_Data=0x000 and Max_Data=0xFFF |
AnnaBridge | 163:e59c8e839560 | 1345 | */ |
AnnaBridge | 163:e59c8e839560 | 1346 | __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 163:e59c8e839560 | 1347 | { |
AnnaBridge | 163:e59c8e839560 | 1348 | register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK)); |
AnnaBridge | 163:e59c8e839560 | 1349 | |
AnnaBridge | 163:e59c8e839560 | 1350 | return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); |
AnnaBridge | 163:e59c8e839560 | 1351 | } |
AnnaBridge | 163:e59c8e839560 | 1352 | |
AnnaBridge | 163:e59c8e839560 | 1353 | /** |
AnnaBridge | 163:e59c8e839560 | 1354 | * @} |
AnnaBridge | 163:e59c8e839560 | 1355 | */ |
AnnaBridge | 163:e59c8e839560 | 1356 | |
AnnaBridge | 163:e59c8e839560 | 1357 | /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management |
AnnaBridge | 163:e59c8e839560 | 1358 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1359 | */ |
AnnaBridge | 163:e59c8e839560 | 1360 | /** |
AnnaBridge | 163:e59c8e839560 | 1361 | * @brief Get DAC underrun flag for DAC channel 1 |
AnnaBridge | 163:e59c8e839560 | 1362 | * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 |
AnnaBridge | 163:e59c8e839560 | 1363 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1364 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 1365 | */ |
AnnaBridge | 163:e59c8e839560 | 1366 | __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) |
AnnaBridge | 163:e59c8e839560 | 1367 | { |
AnnaBridge | 163:e59c8e839560 | 1368 | return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)); |
AnnaBridge | 163:e59c8e839560 | 1369 | } |
AnnaBridge | 163:e59c8e839560 | 1370 | |
AnnaBridge | 163:e59c8e839560 | 1371 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 163:e59c8e839560 | 1372 | /** |
AnnaBridge | 163:e59c8e839560 | 1373 | * @brief Get DAC underrun flag for DAC channel 2 |
AnnaBridge | 163:e59c8e839560 | 1374 | * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 |
AnnaBridge | 163:e59c8e839560 | 1375 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1376 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 1377 | */ |
AnnaBridge | 163:e59c8e839560 | 1378 | __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) |
AnnaBridge | 163:e59c8e839560 | 1379 | { |
AnnaBridge | 163:e59c8e839560 | 1380 | return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)); |
AnnaBridge | 163:e59c8e839560 | 1381 | } |
AnnaBridge | 163:e59c8e839560 | 1382 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 163:e59c8e839560 | 1383 | |
AnnaBridge | 163:e59c8e839560 | 1384 | /** |
AnnaBridge | 163:e59c8e839560 | 1385 | * @brief Clear DAC underrun flag for DAC channel 1 |
AnnaBridge | 163:e59c8e839560 | 1386 | * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 |
AnnaBridge | 163:e59c8e839560 | 1387 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1388 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1389 | */ |
AnnaBridge | 163:e59c8e839560 | 1390 | __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx) |
AnnaBridge | 163:e59c8e839560 | 1391 | { |
AnnaBridge | 163:e59c8e839560 | 1392 | WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1); |
AnnaBridge | 163:e59c8e839560 | 1393 | } |
AnnaBridge | 163:e59c8e839560 | 1394 | |
AnnaBridge | 163:e59c8e839560 | 1395 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 163:e59c8e839560 | 1396 | /** |
AnnaBridge | 163:e59c8e839560 | 1397 | * @brief Clear DAC underrun flag for DAC channel 2 |
AnnaBridge | 163:e59c8e839560 | 1398 | * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 |
AnnaBridge | 163:e59c8e839560 | 1399 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1400 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1401 | */ |
AnnaBridge | 163:e59c8e839560 | 1402 | __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx) |
AnnaBridge | 163:e59c8e839560 | 1403 | { |
AnnaBridge | 163:e59c8e839560 | 1404 | WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2); |
AnnaBridge | 163:e59c8e839560 | 1405 | } |
AnnaBridge | 163:e59c8e839560 | 1406 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 163:e59c8e839560 | 1407 | |
AnnaBridge | 163:e59c8e839560 | 1408 | /** |
AnnaBridge | 163:e59c8e839560 | 1409 | * @} |
AnnaBridge | 163:e59c8e839560 | 1410 | */ |
AnnaBridge | 163:e59c8e839560 | 1411 | |
AnnaBridge | 163:e59c8e839560 | 1412 | /** @defgroup DAC_LL_EF_IT_Management IT management |
AnnaBridge | 163:e59c8e839560 | 1413 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1414 | */ |
AnnaBridge | 163:e59c8e839560 | 1415 | |
AnnaBridge | 163:e59c8e839560 | 1416 | /** |
AnnaBridge | 163:e59c8e839560 | 1417 | * @brief Enable DMA underrun interrupt for DAC channel 1 |
AnnaBridge | 163:e59c8e839560 | 1418 | * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1 |
AnnaBridge | 163:e59c8e839560 | 1419 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1420 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1421 | */ |
AnnaBridge | 163:e59c8e839560 | 1422 | __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx) |
AnnaBridge | 163:e59c8e839560 | 1423 | { |
AnnaBridge | 163:e59c8e839560 | 1424 | SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); |
AnnaBridge | 163:e59c8e839560 | 1425 | } |
AnnaBridge | 163:e59c8e839560 | 1426 | |
AnnaBridge | 163:e59c8e839560 | 1427 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 163:e59c8e839560 | 1428 | /** |
AnnaBridge | 163:e59c8e839560 | 1429 | * @brief Enable DMA underrun interrupt for DAC channel 2 |
AnnaBridge | 163:e59c8e839560 | 1430 | * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 |
AnnaBridge | 163:e59c8e839560 | 1431 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1432 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1433 | */ |
AnnaBridge | 163:e59c8e839560 | 1434 | __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx) |
AnnaBridge | 163:e59c8e839560 | 1435 | { |
AnnaBridge | 163:e59c8e839560 | 1436 | SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); |
AnnaBridge | 163:e59c8e839560 | 1437 | } |
AnnaBridge | 163:e59c8e839560 | 1438 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 163:e59c8e839560 | 1439 | |
AnnaBridge | 163:e59c8e839560 | 1440 | /** |
AnnaBridge | 163:e59c8e839560 | 1441 | * @brief Disable DMA underrun interrupt for DAC channel 1 |
AnnaBridge | 163:e59c8e839560 | 1442 | * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 |
AnnaBridge | 163:e59c8e839560 | 1443 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1444 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1445 | */ |
AnnaBridge | 163:e59c8e839560 | 1446 | __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) |
AnnaBridge | 163:e59c8e839560 | 1447 | { |
AnnaBridge | 163:e59c8e839560 | 1448 | CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); |
AnnaBridge | 163:e59c8e839560 | 1449 | } |
AnnaBridge | 163:e59c8e839560 | 1450 | |
AnnaBridge | 163:e59c8e839560 | 1451 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 163:e59c8e839560 | 1452 | /** |
AnnaBridge | 163:e59c8e839560 | 1453 | * @brief Disable DMA underrun interrupt for DAC channel 2 |
AnnaBridge | 163:e59c8e839560 | 1454 | * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 |
AnnaBridge | 163:e59c8e839560 | 1455 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1456 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1457 | */ |
AnnaBridge | 163:e59c8e839560 | 1458 | __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) |
AnnaBridge | 163:e59c8e839560 | 1459 | { |
AnnaBridge | 163:e59c8e839560 | 1460 | CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); |
AnnaBridge | 163:e59c8e839560 | 1461 | } |
AnnaBridge | 163:e59c8e839560 | 1462 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 163:e59c8e839560 | 1463 | |
AnnaBridge | 163:e59c8e839560 | 1464 | /** |
AnnaBridge | 163:e59c8e839560 | 1465 | * @brief Get DMA underrun interrupt for DAC channel 1 |
AnnaBridge | 163:e59c8e839560 | 1466 | * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 |
AnnaBridge | 163:e59c8e839560 | 1467 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1468 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 1469 | */ |
AnnaBridge | 163:e59c8e839560 | 1470 | __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) |
AnnaBridge | 163:e59c8e839560 | 1471 | { |
AnnaBridge | 163:e59c8e839560 | 1472 | return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)); |
AnnaBridge | 163:e59c8e839560 | 1473 | } |
AnnaBridge | 163:e59c8e839560 | 1474 | |
AnnaBridge | 163:e59c8e839560 | 1475 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 163:e59c8e839560 | 1476 | /** |
AnnaBridge | 163:e59c8e839560 | 1477 | * @brief Get DMA underrun interrupt for DAC channel 2 |
AnnaBridge | 163:e59c8e839560 | 1478 | * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 |
AnnaBridge | 163:e59c8e839560 | 1479 | * @param DACx DAC instance |
AnnaBridge | 163:e59c8e839560 | 1480 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 1481 | */ |
AnnaBridge | 163:e59c8e839560 | 1482 | __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) |
AnnaBridge | 163:e59c8e839560 | 1483 | { |
AnnaBridge | 163:e59c8e839560 | 1484 | return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)); |
AnnaBridge | 163:e59c8e839560 | 1485 | } |
AnnaBridge | 163:e59c8e839560 | 1486 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 163:e59c8e839560 | 1487 | |
AnnaBridge | 163:e59c8e839560 | 1488 | /** |
AnnaBridge | 163:e59c8e839560 | 1489 | * @} |
AnnaBridge | 163:e59c8e839560 | 1490 | */ |
AnnaBridge | 163:e59c8e839560 | 1491 | |
AnnaBridge | 163:e59c8e839560 | 1492 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 163:e59c8e839560 | 1493 | /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions |
AnnaBridge | 163:e59c8e839560 | 1494 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1495 | */ |
AnnaBridge | 163:e59c8e839560 | 1496 | |
AnnaBridge | 163:e59c8e839560 | 1497 | ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx); |
AnnaBridge | 163:e59c8e839560 | 1498 | ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct); |
AnnaBridge | 163:e59c8e839560 | 1499 | void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct); |
AnnaBridge | 163:e59c8e839560 | 1500 | |
AnnaBridge | 163:e59c8e839560 | 1501 | /** |
AnnaBridge | 163:e59c8e839560 | 1502 | * @} |
AnnaBridge | 163:e59c8e839560 | 1503 | */ |
AnnaBridge | 163:e59c8e839560 | 1504 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 163:e59c8e839560 | 1505 | |
AnnaBridge | 163:e59c8e839560 | 1506 | /** |
AnnaBridge | 163:e59c8e839560 | 1507 | * @} |
AnnaBridge | 163:e59c8e839560 | 1508 | */ |
AnnaBridge | 163:e59c8e839560 | 1509 | |
AnnaBridge | 163:e59c8e839560 | 1510 | /** |
AnnaBridge | 163:e59c8e839560 | 1511 | * @} |
AnnaBridge | 163:e59c8e839560 | 1512 | */ |
AnnaBridge | 163:e59c8e839560 | 1513 | |
AnnaBridge | 163:e59c8e839560 | 1514 | #endif /* DAC1 || DAC2 */ |
AnnaBridge | 163:e59c8e839560 | 1515 | |
AnnaBridge | 163:e59c8e839560 | 1516 | /** |
AnnaBridge | 163:e59c8e839560 | 1517 | * @} |
AnnaBridge | 163:e59c8e839560 | 1518 | */ |
AnnaBridge | 163:e59c8e839560 | 1519 | |
AnnaBridge | 163:e59c8e839560 | 1520 | #ifdef __cplusplus |
AnnaBridge | 163:e59c8e839560 | 1521 | } |
AnnaBridge | 163:e59c8e839560 | 1522 | #endif |
AnnaBridge | 163:e59c8e839560 | 1523 | |
AnnaBridge | 163:e59c8e839560 | 1524 | #endif /* __STM32F3xx_LL_DAC_H */ |
AnnaBridge | 163:e59c8e839560 | 1525 | |
AnnaBridge | 163:e59c8e839560 | 1526 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |