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TARGET_NUCLEO_F756ZG/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma.h@138:093f2bd7b9eb, 2017-03-14 (annotated)
- Committer:
- <>
- Date:
- Tue Mar 14 16:20:51 2017 +0000
- Revision:
- 138:093f2bd7b9eb
- Parent:
- 135:176b8275d35d
- Child:
- 139:856d2700e60b
Release 138 of the mbed library
Ports for Upcoming Targets
Fixes and Changes
3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716
3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741
3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780
3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831
3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836
3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840
3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844
3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850
3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860
3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880
3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795
3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828
3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842
3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843
3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879
3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902
3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 126:abea610beb85 | 1 | /** |
| AnnaBridge | 126:abea610beb85 | 2 | ****************************************************************************** |
| AnnaBridge | 126:abea610beb85 | 3 | * @file stm32f7xx_hal_dma.h |
| AnnaBridge | 126:abea610beb85 | 4 | * @author MCD Application Team |
| <> | 135:176b8275d35d | 5 | * @version V1.1.2 |
| <> | 135:176b8275d35d | 6 | * @date 23-September-2016 |
| AnnaBridge | 126:abea610beb85 | 7 | * @brief Header file of DMA HAL module. |
| AnnaBridge | 126:abea610beb85 | 8 | ****************************************************************************** |
| AnnaBridge | 126:abea610beb85 | 9 | * @attention |
| AnnaBridge | 126:abea610beb85 | 10 | * |
| AnnaBridge | 126:abea610beb85 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 126:abea610beb85 | 12 | * |
| AnnaBridge | 126:abea610beb85 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 126:abea610beb85 | 14 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 126:abea610beb85 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 126:abea610beb85 | 16 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 126:abea610beb85 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 126:abea610beb85 | 18 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 126:abea610beb85 | 19 | * and/or other materials provided with the distribution. |
| AnnaBridge | 126:abea610beb85 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 126:abea610beb85 | 21 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 126:abea610beb85 | 22 | * without specific prior written permission. |
| AnnaBridge | 126:abea610beb85 | 23 | * |
| AnnaBridge | 126:abea610beb85 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 126:abea610beb85 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 126:abea610beb85 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 126:abea610beb85 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 126:abea610beb85 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 126:abea610beb85 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 126:abea610beb85 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 126:abea610beb85 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 126:abea610beb85 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 126:abea610beb85 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 126:abea610beb85 | 34 | * |
| AnnaBridge | 126:abea610beb85 | 35 | ****************************************************************************** |
| AnnaBridge | 126:abea610beb85 | 36 | */ |
| AnnaBridge | 126:abea610beb85 | 37 | |
| AnnaBridge | 126:abea610beb85 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 126:abea610beb85 | 39 | #ifndef __STM32F7xx_HAL_DMA_H |
| AnnaBridge | 126:abea610beb85 | 40 | #define __STM32F7xx_HAL_DMA_H |
| AnnaBridge | 126:abea610beb85 | 41 | |
| AnnaBridge | 126:abea610beb85 | 42 | #ifdef __cplusplus |
| AnnaBridge | 126:abea610beb85 | 43 | extern "C" { |
| AnnaBridge | 126:abea610beb85 | 44 | #endif |
| AnnaBridge | 126:abea610beb85 | 45 | |
| AnnaBridge | 126:abea610beb85 | 46 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 126:abea610beb85 | 47 | #include "stm32f7xx_hal_def.h" |
| AnnaBridge | 126:abea610beb85 | 48 | |
| AnnaBridge | 126:abea610beb85 | 49 | /** @addtogroup STM32F7xx_HAL_Driver |
| AnnaBridge | 126:abea610beb85 | 50 | * @{ |
| AnnaBridge | 126:abea610beb85 | 51 | */ |
| AnnaBridge | 126:abea610beb85 | 52 | |
| AnnaBridge | 126:abea610beb85 | 53 | /** @addtogroup DMA |
| AnnaBridge | 126:abea610beb85 | 54 | * @{ |
| AnnaBridge | 126:abea610beb85 | 55 | */ |
| AnnaBridge | 126:abea610beb85 | 56 | |
| AnnaBridge | 126:abea610beb85 | 57 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 126:abea610beb85 | 58 | |
| AnnaBridge | 126:abea610beb85 | 59 | /** @defgroup DMA_Exported_Types DMA Exported Types |
| AnnaBridge | 126:abea610beb85 | 60 | * @brief DMA Exported Types |
| AnnaBridge | 126:abea610beb85 | 61 | * @{ |
| AnnaBridge | 126:abea610beb85 | 62 | */ |
| AnnaBridge | 126:abea610beb85 | 63 | |
| AnnaBridge | 126:abea610beb85 | 64 | /** |
| AnnaBridge | 126:abea610beb85 | 65 | * @brief DMA Configuration Structure definition |
| AnnaBridge | 126:abea610beb85 | 66 | */ |
| AnnaBridge | 126:abea610beb85 | 67 | typedef struct |
| AnnaBridge | 126:abea610beb85 | 68 | { |
| AnnaBridge | 126:abea610beb85 | 69 | uint32_t Channel; /*!< Specifies the channel used for the specified stream. |
| AnnaBridge | 126:abea610beb85 | 70 | This parameter can be a value of @ref DMAEx_Channel_selection */ |
| AnnaBridge | 126:abea610beb85 | 71 | |
| AnnaBridge | 126:abea610beb85 | 72 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
| AnnaBridge | 126:abea610beb85 | 73 | from memory to memory or from peripheral to memory. |
| AnnaBridge | 126:abea610beb85 | 74 | This parameter can be a value of @ref DMA_Data_transfer_direction */ |
| AnnaBridge | 126:abea610beb85 | 75 | |
| AnnaBridge | 126:abea610beb85 | 76 | uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. |
| AnnaBridge | 126:abea610beb85 | 77 | This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ |
| AnnaBridge | 126:abea610beb85 | 78 | |
| AnnaBridge | 126:abea610beb85 | 79 | uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. |
| AnnaBridge | 126:abea610beb85 | 80 | This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
| AnnaBridge | 126:abea610beb85 | 81 | |
| AnnaBridge | 126:abea610beb85 | 82 | uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. |
| AnnaBridge | 126:abea610beb85 | 83 | This parameter can be a value of @ref DMA_Peripheral_data_size */ |
| AnnaBridge | 126:abea610beb85 | 84 | |
| AnnaBridge | 126:abea610beb85 | 85 | uint32_t MemDataAlignment; /*!< Specifies the Memory data width. |
| AnnaBridge | 126:abea610beb85 | 86 | This parameter can be a value of @ref DMA_Memory_data_size */ |
| AnnaBridge | 126:abea610beb85 | 87 | |
| AnnaBridge | 126:abea610beb85 | 88 | uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. |
| AnnaBridge | 126:abea610beb85 | 89 | This parameter can be a value of @ref DMA_mode |
| AnnaBridge | 126:abea610beb85 | 90 | @note The circular buffer mode cannot be used if the memory-to-memory |
| AnnaBridge | 126:abea610beb85 | 91 | data transfer is configured on the selected Stream */ |
| AnnaBridge | 126:abea610beb85 | 92 | |
| AnnaBridge | 126:abea610beb85 | 93 | uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. |
| AnnaBridge | 126:abea610beb85 | 94 | This parameter can be a value of @ref DMA_Priority_level */ |
| AnnaBridge | 126:abea610beb85 | 95 | |
| AnnaBridge | 126:abea610beb85 | 96 | uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. |
| AnnaBridge | 126:abea610beb85 | 97 | This parameter can be a value of @ref DMA_FIFO_direct_mode |
| AnnaBridge | 126:abea610beb85 | 98 | @note The Direct mode (FIFO mode disabled) cannot be used if the |
| AnnaBridge | 126:abea610beb85 | 99 | memory-to-memory data transfer is configured on the selected stream */ |
| AnnaBridge | 126:abea610beb85 | 100 | |
| AnnaBridge | 126:abea610beb85 | 101 | uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. |
| AnnaBridge | 126:abea610beb85 | 102 | This parameter can be a value of @ref DMA_FIFO_threshold_level */ |
| AnnaBridge | 126:abea610beb85 | 103 | |
| AnnaBridge | 126:abea610beb85 | 104 | uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. |
| AnnaBridge | 126:abea610beb85 | 105 | It specifies the amount of data to be transferred in a single non interruptible |
| AnnaBridge | 126:abea610beb85 | 106 | transaction. |
| AnnaBridge | 126:abea610beb85 | 107 | This parameter can be a value of @ref DMA_Memory_burst |
| AnnaBridge | 126:abea610beb85 | 108 | @note The burst mode is possible only if the address Increment mode is enabled. */ |
| AnnaBridge | 126:abea610beb85 | 109 | |
| AnnaBridge | 126:abea610beb85 | 110 | uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. |
| AnnaBridge | 126:abea610beb85 | 111 | It specifies the amount of data to be transferred in a single non interruptible |
| AnnaBridge | 126:abea610beb85 | 112 | transaction. |
| AnnaBridge | 126:abea610beb85 | 113 | This parameter can be a value of @ref DMA_Peripheral_burst |
| AnnaBridge | 126:abea610beb85 | 114 | @note The burst mode is possible only if the address Increment mode is enabled. */ |
| AnnaBridge | 126:abea610beb85 | 115 | }DMA_InitTypeDef; |
| AnnaBridge | 126:abea610beb85 | 116 | |
| AnnaBridge | 126:abea610beb85 | 117 | /** |
| AnnaBridge | 126:abea610beb85 | 118 | * @brief HAL DMA State structures definition |
| AnnaBridge | 126:abea610beb85 | 119 | */ |
| AnnaBridge | 126:abea610beb85 | 120 | typedef enum |
| AnnaBridge | 126:abea610beb85 | 121 | { |
| AnnaBridge | 126:abea610beb85 | 122 | HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ |
| AnnaBridge | 126:abea610beb85 | 123 | HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ |
| AnnaBridge | 126:abea610beb85 | 124 | HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ |
| AnnaBridge | 126:abea610beb85 | 125 | HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ |
| AnnaBridge | 126:abea610beb85 | 126 | HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ |
| AnnaBridge | 126:abea610beb85 | 127 | HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ |
| AnnaBridge | 126:abea610beb85 | 128 | }HAL_DMA_StateTypeDef; |
| AnnaBridge | 126:abea610beb85 | 129 | |
| AnnaBridge | 126:abea610beb85 | 130 | /** |
| AnnaBridge | 126:abea610beb85 | 131 | * @brief HAL DMA Error Code structure definition |
| AnnaBridge | 126:abea610beb85 | 132 | */ |
| AnnaBridge | 126:abea610beb85 | 133 | typedef enum |
| AnnaBridge | 126:abea610beb85 | 134 | { |
| AnnaBridge | 126:abea610beb85 | 135 | HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ |
| AnnaBridge | 126:abea610beb85 | 136 | HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ |
| AnnaBridge | 126:abea610beb85 | 137 | }HAL_DMA_LevelCompleteTypeDef; |
| AnnaBridge | 126:abea610beb85 | 138 | |
| AnnaBridge | 126:abea610beb85 | 139 | /** |
| AnnaBridge | 126:abea610beb85 | 140 | * @brief HAL DMA Error Code structure definition |
| AnnaBridge | 126:abea610beb85 | 141 | */ |
| AnnaBridge | 126:abea610beb85 | 142 | typedef enum |
| AnnaBridge | 126:abea610beb85 | 143 | { |
| AnnaBridge | 126:abea610beb85 | 144 | HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ |
| AnnaBridge | 126:abea610beb85 | 145 | HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ |
| AnnaBridge | 126:abea610beb85 | 146 | HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ |
| AnnaBridge | 126:abea610beb85 | 147 | HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ |
| AnnaBridge | 126:abea610beb85 | 148 | HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ |
| AnnaBridge | 126:abea610beb85 | 149 | HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ |
| AnnaBridge | 126:abea610beb85 | 150 | HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ |
| AnnaBridge | 126:abea610beb85 | 151 | }HAL_DMA_CallbackIDTypeDef; |
| AnnaBridge | 126:abea610beb85 | 152 | |
| AnnaBridge | 126:abea610beb85 | 153 | /** |
| AnnaBridge | 126:abea610beb85 | 154 | * @brief DMA handle Structure definition |
| AnnaBridge | 126:abea610beb85 | 155 | */ |
| AnnaBridge | 126:abea610beb85 | 156 | typedef struct __DMA_HandleTypeDef |
| AnnaBridge | 126:abea610beb85 | 157 | { |
| AnnaBridge | 126:abea610beb85 | 158 | DMA_Stream_TypeDef *Instance; /*!< Register base address */ |
| AnnaBridge | 126:abea610beb85 | 159 | |
| AnnaBridge | 126:abea610beb85 | 160 | DMA_InitTypeDef Init; /*!< DMA communication parameters */ |
| AnnaBridge | 126:abea610beb85 | 161 | |
| AnnaBridge | 126:abea610beb85 | 162 | HAL_LockTypeDef Lock; /*!< DMA locking object */ |
| AnnaBridge | 126:abea610beb85 | 163 | |
| AnnaBridge | 126:abea610beb85 | 164 | __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
| AnnaBridge | 126:abea610beb85 | 165 | |
| AnnaBridge | 126:abea610beb85 | 166 | void *Parent; /*!< Parent object state */ |
| AnnaBridge | 126:abea610beb85 | 167 | |
| AnnaBridge | 126:abea610beb85 | 168 | void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
| AnnaBridge | 126:abea610beb85 | 169 | |
| AnnaBridge | 126:abea610beb85 | 170 | void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
| AnnaBridge | 126:abea610beb85 | 171 | |
| AnnaBridge | 126:abea610beb85 | 172 | void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ |
| AnnaBridge | 126:abea610beb85 | 173 | |
| AnnaBridge | 126:abea610beb85 | 174 | void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ |
| AnnaBridge | 126:abea610beb85 | 175 | |
| AnnaBridge | 126:abea610beb85 | 176 | void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
| AnnaBridge | 126:abea610beb85 | 177 | |
| AnnaBridge | 126:abea610beb85 | 178 | void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ |
| AnnaBridge | 126:abea610beb85 | 179 | |
| AnnaBridge | 126:abea610beb85 | 180 | __IO uint32_t ErrorCode; /*!< DMA Error code */ |
| AnnaBridge | 126:abea610beb85 | 181 | |
| AnnaBridge | 126:abea610beb85 | 182 | uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ |
| AnnaBridge | 126:abea610beb85 | 183 | |
| AnnaBridge | 126:abea610beb85 | 184 | uint32_t StreamIndex; /*!< DMA Stream Index */ |
| AnnaBridge | 126:abea610beb85 | 185 | |
| AnnaBridge | 126:abea610beb85 | 186 | }DMA_HandleTypeDef; |
| AnnaBridge | 126:abea610beb85 | 187 | |
| AnnaBridge | 126:abea610beb85 | 188 | /** |
| AnnaBridge | 126:abea610beb85 | 189 | * @} |
| AnnaBridge | 126:abea610beb85 | 190 | */ |
| AnnaBridge | 126:abea610beb85 | 191 | |
| AnnaBridge | 126:abea610beb85 | 192 | |
| AnnaBridge | 126:abea610beb85 | 193 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 126:abea610beb85 | 194 | |
| AnnaBridge | 126:abea610beb85 | 195 | /** @defgroup DMA_Exported_Constants DMA Exported Constants |
| AnnaBridge | 126:abea610beb85 | 196 | * @brief DMA Exported constants |
| AnnaBridge | 126:abea610beb85 | 197 | * @{ |
| AnnaBridge | 126:abea610beb85 | 198 | */ |
| AnnaBridge | 126:abea610beb85 | 199 | |
| AnnaBridge | 126:abea610beb85 | 200 | /** @defgroup DMA_Error_Code DMA Error Code |
| AnnaBridge | 126:abea610beb85 | 201 | * @brief DMA Error Code |
| AnnaBridge | 126:abea610beb85 | 202 | * @{ |
| AnnaBridge | 126:abea610beb85 | 203 | */ |
| AnnaBridge | 126:abea610beb85 | 204 | #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ |
| AnnaBridge | 126:abea610beb85 | 205 | #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ |
| AnnaBridge | 126:abea610beb85 | 206 | #define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U) /*!< FIFO error */ |
| AnnaBridge | 126:abea610beb85 | 207 | #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U) /*!< Direct Mode error */ |
| AnnaBridge | 126:abea610beb85 | 208 | #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ |
| AnnaBridge | 126:abea610beb85 | 209 | #define HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U) /*!< Parameter error */ |
| AnnaBridge | 126:abea610beb85 | 210 | #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort requested with no Xfer ongoing */ |
| AnnaBridge | 126:abea610beb85 | 211 | #define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */ |
| AnnaBridge | 126:abea610beb85 | 212 | /** |
| AnnaBridge | 126:abea610beb85 | 213 | * @} |
| AnnaBridge | 126:abea610beb85 | 214 | */ |
| AnnaBridge | 126:abea610beb85 | 215 | |
| AnnaBridge | 126:abea610beb85 | 216 | /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction |
| AnnaBridge | 126:abea610beb85 | 217 | * @brief DMA data transfer direction |
| AnnaBridge | 126:abea610beb85 | 218 | * @{ |
| AnnaBridge | 126:abea610beb85 | 219 | */ |
| AnnaBridge | 126:abea610beb85 | 220 | #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ |
| AnnaBridge | 126:abea610beb85 | 221 | #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ |
| AnnaBridge | 126:abea610beb85 | 222 | #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ |
| AnnaBridge | 126:abea610beb85 | 223 | /** |
| AnnaBridge | 126:abea610beb85 | 224 | * @} |
| AnnaBridge | 126:abea610beb85 | 225 | */ |
| AnnaBridge | 126:abea610beb85 | 226 | |
| AnnaBridge | 126:abea610beb85 | 227 | /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode |
| AnnaBridge | 126:abea610beb85 | 228 | * @brief DMA peripheral incremented mode |
| AnnaBridge | 126:abea610beb85 | 229 | * @{ |
| AnnaBridge | 126:abea610beb85 | 230 | */ |
| AnnaBridge | 126:abea610beb85 | 231 | #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ |
| AnnaBridge | 126:abea610beb85 | 232 | #define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */ |
| AnnaBridge | 126:abea610beb85 | 233 | /** |
| AnnaBridge | 126:abea610beb85 | 234 | * @} |
| AnnaBridge | 126:abea610beb85 | 235 | */ |
| AnnaBridge | 126:abea610beb85 | 236 | |
| AnnaBridge | 126:abea610beb85 | 237 | /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode |
| AnnaBridge | 126:abea610beb85 | 238 | * @brief DMA memory incremented mode |
| AnnaBridge | 126:abea610beb85 | 239 | * @{ |
| AnnaBridge | 126:abea610beb85 | 240 | */ |
| AnnaBridge | 126:abea610beb85 | 241 | #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ |
| AnnaBridge | 126:abea610beb85 | 242 | #define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */ |
| AnnaBridge | 126:abea610beb85 | 243 | /** |
| AnnaBridge | 126:abea610beb85 | 244 | * @} |
| AnnaBridge | 126:abea610beb85 | 245 | */ |
| AnnaBridge | 126:abea610beb85 | 246 | |
| AnnaBridge | 126:abea610beb85 | 247 | /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size |
| AnnaBridge | 126:abea610beb85 | 248 | * @brief DMA peripheral data size |
| AnnaBridge | 126:abea610beb85 | 249 | * @{ |
| AnnaBridge | 126:abea610beb85 | 250 | */ |
| AnnaBridge | 126:abea610beb85 | 251 | #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */ |
| AnnaBridge | 126:abea610beb85 | 252 | #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ |
| AnnaBridge | 126:abea610beb85 | 253 | #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ |
| AnnaBridge | 126:abea610beb85 | 254 | /** |
| AnnaBridge | 126:abea610beb85 | 255 | * @} |
| AnnaBridge | 126:abea610beb85 | 256 | */ |
| AnnaBridge | 126:abea610beb85 | 257 | |
| AnnaBridge | 126:abea610beb85 | 258 | /** @defgroup DMA_Memory_data_size DMA Memory data size |
| AnnaBridge | 126:abea610beb85 | 259 | * @brief DMA memory data size |
| AnnaBridge | 126:abea610beb85 | 260 | * @{ |
| AnnaBridge | 126:abea610beb85 | 261 | */ |
| AnnaBridge | 126:abea610beb85 | 262 | #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */ |
| AnnaBridge | 126:abea610beb85 | 263 | #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ |
| AnnaBridge | 126:abea610beb85 | 264 | #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ |
| AnnaBridge | 126:abea610beb85 | 265 | /** |
| AnnaBridge | 126:abea610beb85 | 266 | * @} |
| AnnaBridge | 126:abea610beb85 | 267 | */ |
| AnnaBridge | 126:abea610beb85 | 268 | |
| AnnaBridge | 126:abea610beb85 | 269 | /** @defgroup DMA_mode DMA mode |
| AnnaBridge | 126:abea610beb85 | 270 | * @brief DMA mode |
| AnnaBridge | 126:abea610beb85 | 271 | * @{ |
| AnnaBridge | 126:abea610beb85 | 272 | */ |
| AnnaBridge | 126:abea610beb85 | 273 | #define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ |
| AnnaBridge | 126:abea610beb85 | 274 | #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ |
| AnnaBridge | 126:abea610beb85 | 275 | #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ |
| AnnaBridge | 126:abea610beb85 | 276 | /** |
| AnnaBridge | 126:abea610beb85 | 277 | * @} |
| AnnaBridge | 126:abea610beb85 | 278 | */ |
| AnnaBridge | 126:abea610beb85 | 279 | |
| AnnaBridge | 126:abea610beb85 | 280 | /** @defgroup DMA_Priority_level DMA Priority level |
| AnnaBridge | 126:abea610beb85 | 281 | * @brief DMA priority levels |
| AnnaBridge | 126:abea610beb85 | 282 | * @{ |
| AnnaBridge | 126:abea610beb85 | 283 | */ |
| AnnaBridge | 126:abea610beb85 | 284 | #define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */ |
| AnnaBridge | 126:abea610beb85 | 285 | #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ |
| AnnaBridge | 126:abea610beb85 | 286 | #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ |
| AnnaBridge | 126:abea610beb85 | 287 | #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ |
| AnnaBridge | 126:abea610beb85 | 288 | /** |
| AnnaBridge | 126:abea610beb85 | 289 | * @} |
| AnnaBridge | 126:abea610beb85 | 290 | */ |
| AnnaBridge | 126:abea610beb85 | 291 | |
| AnnaBridge | 126:abea610beb85 | 292 | /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode |
| AnnaBridge | 126:abea610beb85 | 293 | * @brief DMA FIFO direct mode |
| AnnaBridge | 126:abea610beb85 | 294 | * @{ |
| AnnaBridge | 126:abea610beb85 | 295 | */ |
| AnnaBridge | 126:abea610beb85 | 296 | #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */ |
| AnnaBridge | 126:abea610beb85 | 297 | #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ |
| AnnaBridge | 126:abea610beb85 | 298 | /** |
| AnnaBridge | 126:abea610beb85 | 299 | * @} |
| AnnaBridge | 126:abea610beb85 | 300 | */ |
| AnnaBridge | 126:abea610beb85 | 301 | |
| AnnaBridge | 126:abea610beb85 | 302 | /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level |
| AnnaBridge | 126:abea610beb85 | 303 | * @brief DMA FIFO level |
| AnnaBridge | 126:abea610beb85 | 304 | * @{ |
| AnnaBridge | 126:abea610beb85 | 305 | */ |
| AnnaBridge | 126:abea610beb85 | 306 | #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */ |
| AnnaBridge | 126:abea610beb85 | 307 | #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ |
| AnnaBridge | 126:abea610beb85 | 308 | #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ |
| AnnaBridge | 126:abea610beb85 | 309 | #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ |
| AnnaBridge | 126:abea610beb85 | 310 | /** |
| AnnaBridge | 126:abea610beb85 | 311 | * @} |
| AnnaBridge | 126:abea610beb85 | 312 | */ |
| AnnaBridge | 126:abea610beb85 | 313 | |
| AnnaBridge | 126:abea610beb85 | 314 | /** @defgroup DMA_Memory_burst DMA Memory burst |
| AnnaBridge | 126:abea610beb85 | 315 | * @brief DMA memory burst |
| AnnaBridge | 126:abea610beb85 | 316 | * @{ |
| AnnaBridge | 126:abea610beb85 | 317 | */ |
| AnnaBridge | 126:abea610beb85 | 318 | #define DMA_MBURST_SINGLE ((uint32_t)0x00000000U) |
| AnnaBridge | 126:abea610beb85 | 319 | #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) |
| AnnaBridge | 126:abea610beb85 | 320 | #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) |
| AnnaBridge | 126:abea610beb85 | 321 | #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) |
| AnnaBridge | 126:abea610beb85 | 322 | /** |
| AnnaBridge | 126:abea610beb85 | 323 | * @} |
| AnnaBridge | 126:abea610beb85 | 324 | */ |
| AnnaBridge | 126:abea610beb85 | 325 | |
| AnnaBridge | 126:abea610beb85 | 326 | /** @defgroup DMA_Peripheral_burst DMA Peripheral burst |
| AnnaBridge | 126:abea610beb85 | 327 | * @brief DMA peripheral burst |
| AnnaBridge | 126:abea610beb85 | 328 | * @{ |
| AnnaBridge | 126:abea610beb85 | 329 | */ |
| AnnaBridge | 126:abea610beb85 | 330 | #define DMA_PBURST_SINGLE ((uint32_t)0x00000000U) |
| AnnaBridge | 126:abea610beb85 | 331 | #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) |
| AnnaBridge | 126:abea610beb85 | 332 | #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) |
| AnnaBridge | 126:abea610beb85 | 333 | #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) |
| AnnaBridge | 126:abea610beb85 | 334 | /** |
| AnnaBridge | 126:abea610beb85 | 335 | * @} |
| AnnaBridge | 126:abea610beb85 | 336 | */ |
| AnnaBridge | 126:abea610beb85 | 337 | |
| AnnaBridge | 126:abea610beb85 | 338 | /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions |
| AnnaBridge | 126:abea610beb85 | 339 | * @brief DMA interrupts definition |
| AnnaBridge | 126:abea610beb85 | 340 | * @{ |
| AnnaBridge | 126:abea610beb85 | 341 | */ |
| AnnaBridge | 126:abea610beb85 | 342 | #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) |
| AnnaBridge | 126:abea610beb85 | 343 | #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) |
| AnnaBridge | 126:abea610beb85 | 344 | #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) |
| AnnaBridge | 126:abea610beb85 | 345 | #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) |
| AnnaBridge | 126:abea610beb85 | 346 | #define DMA_IT_FE ((uint32_t)0x00000080U) |
| AnnaBridge | 126:abea610beb85 | 347 | /** |
| AnnaBridge | 126:abea610beb85 | 348 | * @} |
| AnnaBridge | 126:abea610beb85 | 349 | */ |
| AnnaBridge | 126:abea610beb85 | 350 | |
| AnnaBridge | 126:abea610beb85 | 351 | /** @defgroup DMA_flag_definitions DMA flag definitions |
| AnnaBridge | 126:abea610beb85 | 352 | * @brief DMA flag definitions |
| AnnaBridge | 126:abea610beb85 | 353 | * @{ |
| AnnaBridge | 126:abea610beb85 | 354 | */ |
| AnnaBridge | 126:abea610beb85 | 355 | #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U) |
| AnnaBridge | 126:abea610beb85 | 356 | #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U) |
| AnnaBridge | 126:abea610beb85 | 357 | #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U) |
| AnnaBridge | 126:abea610beb85 | 358 | #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U) |
| AnnaBridge | 126:abea610beb85 | 359 | #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U) |
| AnnaBridge | 126:abea610beb85 | 360 | #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U) |
| AnnaBridge | 126:abea610beb85 | 361 | #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U) |
| AnnaBridge | 126:abea610beb85 | 362 | #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U) |
| AnnaBridge | 126:abea610beb85 | 363 | #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U) |
| AnnaBridge | 126:abea610beb85 | 364 | #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U) |
| AnnaBridge | 126:abea610beb85 | 365 | #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U) |
| AnnaBridge | 126:abea610beb85 | 366 | #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U) |
| AnnaBridge | 126:abea610beb85 | 367 | #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U) |
| AnnaBridge | 126:abea610beb85 | 368 | #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U) |
| AnnaBridge | 126:abea610beb85 | 369 | #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U) |
| AnnaBridge | 126:abea610beb85 | 370 | #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U) |
| AnnaBridge | 126:abea610beb85 | 371 | #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U) |
| AnnaBridge | 126:abea610beb85 | 372 | #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U) |
| AnnaBridge | 126:abea610beb85 | 373 | #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U) |
| AnnaBridge | 126:abea610beb85 | 374 | #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U) |
| AnnaBridge | 126:abea610beb85 | 375 | /** |
| AnnaBridge | 126:abea610beb85 | 376 | * @} |
| AnnaBridge | 126:abea610beb85 | 377 | */ |
| AnnaBridge | 126:abea610beb85 | 378 | |
| AnnaBridge | 126:abea610beb85 | 379 | /** |
| AnnaBridge | 126:abea610beb85 | 380 | * @} |
| AnnaBridge | 126:abea610beb85 | 381 | */ |
| AnnaBridge | 126:abea610beb85 | 382 | |
| AnnaBridge | 126:abea610beb85 | 383 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 126:abea610beb85 | 384 | |
| AnnaBridge | 126:abea610beb85 | 385 | /** @brief Reset DMA handle state |
| AnnaBridge | 126:abea610beb85 | 386 | * @param __HANDLE__: specifies the DMA handle. |
| AnnaBridge | 126:abea610beb85 | 387 | * @retval None |
| AnnaBridge | 126:abea610beb85 | 388 | */ |
| AnnaBridge | 126:abea610beb85 | 389 | #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
| AnnaBridge | 126:abea610beb85 | 390 | |
| AnnaBridge | 126:abea610beb85 | 391 | /** |
| AnnaBridge | 126:abea610beb85 | 392 | * @brief Return the current DMA Stream FIFO filled level. |
| AnnaBridge | 126:abea610beb85 | 393 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 126:abea610beb85 | 394 | * @retval The FIFO filling state. |
| AnnaBridge | 126:abea610beb85 | 395 | * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full |
| AnnaBridge | 126:abea610beb85 | 396 | * and not empty. |
| AnnaBridge | 126:abea610beb85 | 397 | * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. |
| AnnaBridge | 126:abea610beb85 | 398 | * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. |
| AnnaBridge | 126:abea610beb85 | 399 | * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. |
| AnnaBridge | 126:abea610beb85 | 400 | * - DMA_FIFOStatus_Empty: when FIFO is empty |
| AnnaBridge | 126:abea610beb85 | 401 | * - DMA_FIFOStatus_Full: when FIFO is full |
| AnnaBridge | 126:abea610beb85 | 402 | */ |
| AnnaBridge | 126:abea610beb85 | 403 | #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) |
| AnnaBridge | 126:abea610beb85 | 404 | |
| AnnaBridge | 126:abea610beb85 | 405 | /** |
| AnnaBridge | 126:abea610beb85 | 406 | * @brief Enable the specified DMA Stream. |
| AnnaBridge | 126:abea610beb85 | 407 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 126:abea610beb85 | 408 | * @retval None |
| AnnaBridge | 126:abea610beb85 | 409 | */ |
| AnnaBridge | 126:abea610beb85 | 410 | #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) |
| AnnaBridge | 126:abea610beb85 | 411 | |
| AnnaBridge | 126:abea610beb85 | 412 | /** |
| AnnaBridge | 126:abea610beb85 | 413 | * @brief Disable the specified DMA Stream. |
| AnnaBridge | 126:abea610beb85 | 414 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 126:abea610beb85 | 415 | * @retval None |
| AnnaBridge | 126:abea610beb85 | 416 | */ |
| AnnaBridge | 126:abea610beb85 | 417 | #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) |
| AnnaBridge | 126:abea610beb85 | 418 | |
| AnnaBridge | 126:abea610beb85 | 419 | /* Interrupt & Flag management */ |
| AnnaBridge | 126:abea610beb85 | 420 | |
| AnnaBridge | 126:abea610beb85 | 421 | /** |
| AnnaBridge | 126:abea610beb85 | 422 | * @brief Return the current DMA Stream transfer complete flag. |
| AnnaBridge | 126:abea610beb85 | 423 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 126:abea610beb85 | 424 | * @retval The specified transfer complete flag index. |
| AnnaBridge | 126:abea610beb85 | 425 | */ |
| AnnaBridge | 126:abea610beb85 | 426 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| AnnaBridge | 126:abea610beb85 | 427 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ |
| AnnaBridge | 126:abea610beb85 | 428 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ |
| AnnaBridge | 126:abea610beb85 | 429 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ |
| AnnaBridge | 126:abea610beb85 | 430 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ |
| AnnaBridge | 126:abea610beb85 | 431 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ |
| AnnaBridge | 126:abea610beb85 | 432 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ |
| AnnaBridge | 126:abea610beb85 | 433 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ |
| AnnaBridge | 126:abea610beb85 | 434 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ |
| AnnaBridge | 126:abea610beb85 | 435 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ |
| AnnaBridge | 126:abea610beb85 | 436 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ |
| AnnaBridge | 126:abea610beb85 | 437 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ |
| AnnaBridge | 126:abea610beb85 | 438 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ |
| AnnaBridge | 126:abea610beb85 | 439 | DMA_FLAG_TCIF3_7) |
| AnnaBridge | 126:abea610beb85 | 440 | |
| AnnaBridge | 126:abea610beb85 | 441 | /** |
| AnnaBridge | 126:abea610beb85 | 442 | * @brief Return the current DMA Stream half transfer complete flag. |
| AnnaBridge | 126:abea610beb85 | 443 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 126:abea610beb85 | 444 | * @retval The specified half transfer complete flag index. |
| AnnaBridge | 126:abea610beb85 | 445 | */ |
| AnnaBridge | 126:abea610beb85 | 446 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| AnnaBridge | 126:abea610beb85 | 447 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ |
| AnnaBridge | 126:abea610beb85 | 448 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ |
| AnnaBridge | 126:abea610beb85 | 449 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ |
| AnnaBridge | 126:abea610beb85 | 450 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ |
| AnnaBridge | 126:abea610beb85 | 451 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ |
| AnnaBridge | 126:abea610beb85 | 452 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ |
| AnnaBridge | 126:abea610beb85 | 453 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ |
| AnnaBridge | 126:abea610beb85 | 454 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ |
| AnnaBridge | 126:abea610beb85 | 455 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ |
| AnnaBridge | 126:abea610beb85 | 456 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ |
| AnnaBridge | 126:abea610beb85 | 457 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ |
| AnnaBridge | 126:abea610beb85 | 458 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ |
| AnnaBridge | 126:abea610beb85 | 459 | DMA_FLAG_HTIF3_7) |
| AnnaBridge | 126:abea610beb85 | 460 | |
| AnnaBridge | 126:abea610beb85 | 461 | /** |
| AnnaBridge | 126:abea610beb85 | 462 | * @brief Return the current DMA Stream transfer error flag. |
| AnnaBridge | 126:abea610beb85 | 463 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 126:abea610beb85 | 464 | * @retval The specified transfer error flag index. |
| AnnaBridge | 126:abea610beb85 | 465 | */ |
| AnnaBridge | 126:abea610beb85 | 466 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| AnnaBridge | 126:abea610beb85 | 467 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ |
| AnnaBridge | 126:abea610beb85 | 468 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ |
| AnnaBridge | 126:abea610beb85 | 469 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ |
| AnnaBridge | 126:abea610beb85 | 470 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ |
| AnnaBridge | 126:abea610beb85 | 471 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ |
| AnnaBridge | 126:abea610beb85 | 472 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ |
| AnnaBridge | 126:abea610beb85 | 473 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ |
| AnnaBridge | 126:abea610beb85 | 474 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ |
| AnnaBridge | 126:abea610beb85 | 475 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ |
| AnnaBridge | 126:abea610beb85 | 476 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ |
| AnnaBridge | 126:abea610beb85 | 477 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ |
| AnnaBridge | 126:abea610beb85 | 478 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ |
| AnnaBridge | 126:abea610beb85 | 479 | DMA_FLAG_TEIF3_7) |
| AnnaBridge | 126:abea610beb85 | 480 | |
| AnnaBridge | 126:abea610beb85 | 481 | /** |
| AnnaBridge | 126:abea610beb85 | 482 | * @brief Return the current DMA Stream FIFO error flag. |
| AnnaBridge | 126:abea610beb85 | 483 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 126:abea610beb85 | 484 | * @retval The specified FIFO error flag index. |
| AnnaBridge | 126:abea610beb85 | 485 | */ |
| AnnaBridge | 126:abea610beb85 | 486 | #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ |
| AnnaBridge | 126:abea610beb85 | 487 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ |
| AnnaBridge | 126:abea610beb85 | 488 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ |
| AnnaBridge | 126:abea610beb85 | 489 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ |
| AnnaBridge | 126:abea610beb85 | 490 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ |
| AnnaBridge | 126:abea610beb85 | 491 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ |
| AnnaBridge | 126:abea610beb85 | 492 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ |
| AnnaBridge | 126:abea610beb85 | 493 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ |
| AnnaBridge | 126:abea610beb85 | 494 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ |
| AnnaBridge | 126:abea610beb85 | 495 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ |
| AnnaBridge | 126:abea610beb85 | 496 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ |
| AnnaBridge | 126:abea610beb85 | 497 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ |
| AnnaBridge | 126:abea610beb85 | 498 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ |
| AnnaBridge | 126:abea610beb85 | 499 | DMA_FLAG_FEIF3_7) |
| AnnaBridge | 126:abea610beb85 | 500 | |
| AnnaBridge | 126:abea610beb85 | 501 | /** |
| AnnaBridge | 126:abea610beb85 | 502 | * @brief Return the current DMA Stream direct mode error flag. |
| AnnaBridge | 126:abea610beb85 | 503 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 126:abea610beb85 | 504 | * @retval The specified direct mode error flag index. |
| AnnaBridge | 126:abea610beb85 | 505 | */ |
| AnnaBridge | 126:abea610beb85 | 506 | #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ |
| AnnaBridge | 126:abea610beb85 | 507 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ |
| AnnaBridge | 126:abea610beb85 | 508 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ |
| AnnaBridge | 126:abea610beb85 | 509 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ |
| AnnaBridge | 126:abea610beb85 | 510 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ |
| AnnaBridge | 126:abea610beb85 | 511 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ |
| AnnaBridge | 126:abea610beb85 | 512 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ |
| AnnaBridge | 126:abea610beb85 | 513 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ |
| AnnaBridge | 126:abea610beb85 | 514 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ |
| AnnaBridge | 126:abea610beb85 | 515 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ |
| AnnaBridge | 126:abea610beb85 | 516 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ |
| AnnaBridge | 126:abea610beb85 | 517 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ |
| AnnaBridge | 126:abea610beb85 | 518 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ |
| AnnaBridge | 126:abea610beb85 | 519 | DMA_FLAG_DMEIF3_7) |
| AnnaBridge | 126:abea610beb85 | 520 | |
| AnnaBridge | 126:abea610beb85 | 521 | /** |
| AnnaBridge | 126:abea610beb85 | 522 | * @brief Get the DMA Stream pending flags. |
| AnnaBridge | 126:abea610beb85 | 523 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 126:abea610beb85 | 524 | * @param __FLAG__: Get the specified flag. |
| AnnaBridge | 126:abea610beb85 | 525 | * This parameter can be any combination of the following values: |
| AnnaBridge | 126:abea610beb85 | 526 | * @arg DMA_FLAG_TCIFx: Transfer complete flag. |
| AnnaBridge | 126:abea610beb85 | 527 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag. |
| AnnaBridge | 126:abea610beb85 | 528 | * @arg DMA_FLAG_TEIFx: Transfer error flag. |
| AnnaBridge | 126:abea610beb85 | 529 | * @arg DMA_FLAG_DMEIFx: Direct mode error flag. |
| AnnaBridge | 126:abea610beb85 | 530 | * @arg DMA_FLAG_FEIFx: FIFO error flag. |
| AnnaBridge | 126:abea610beb85 | 531 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. |
| AnnaBridge | 126:abea610beb85 | 532 | * @retval The state of FLAG (SET or RESET). |
| AnnaBridge | 126:abea610beb85 | 533 | */ |
| AnnaBridge | 126:abea610beb85 | 534 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ |
| AnnaBridge | 126:abea610beb85 | 535 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ |
| AnnaBridge | 126:abea610beb85 | 536 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ |
| AnnaBridge | 126:abea610beb85 | 537 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) |
| AnnaBridge | 126:abea610beb85 | 538 | |
| AnnaBridge | 126:abea610beb85 | 539 | /** |
| AnnaBridge | 126:abea610beb85 | 540 | * @brief Clear the DMA Stream pending flags. |
| AnnaBridge | 126:abea610beb85 | 541 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 126:abea610beb85 | 542 | * @param __FLAG__: specifies the flag to clear. |
| AnnaBridge | 126:abea610beb85 | 543 | * This parameter can be any combination of the following values: |
| AnnaBridge | 126:abea610beb85 | 544 | * @arg DMA_FLAG_TCIFx: Transfer complete flag. |
| AnnaBridge | 126:abea610beb85 | 545 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag. |
| AnnaBridge | 126:abea610beb85 | 546 | * @arg DMA_FLAG_TEIFx: Transfer error flag. |
| AnnaBridge | 126:abea610beb85 | 547 | * @arg DMA_FLAG_DMEIFx: Direct mode error flag. |
| AnnaBridge | 126:abea610beb85 | 548 | * @arg DMA_FLAG_FEIFx: FIFO error flag. |
| AnnaBridge | 126:abea610beb85 | 549 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. |
| AnnaBridge | 126:abea610beb85 | 550 | * @retval None |
| AnnaBridge | 126:abea610beb85 | 551 | */ |
| AnnaBridge | 126:abea610beb85 | 552 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
| AnnaBridge | 126:abea610beb85 | 553 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ |
| AnnaBridge | 126:abea610beb85 | 554 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ |
| AnnaBridge | 126:abea610beb85 | 555 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) |
| AnnaBridge | 126:abea610beb85 | 556 | |
| AnnaBridge | 126:abea610beb85 | 557 | /** |
| AnnaBridge | 126:abea610beb85 | 558 | * @brief Enable the specified DMA Stream interrupts. |
| AnnaBridge | 126:abea610beb85 | 559 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 126:abea610beb85 | 560 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| AnnaBridge | 126:abea610beb85 | 561 | * This parameter can be one of the following values: |
| AnnaBridge | 126:abea610beb85 | 562 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
| AnnaBridge | 126:abea610beb85 | 563 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
| AnnaBridge | 126:abea610beb85 | 564 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
| AnnaBridge | 126:abea610beb85 | 565 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
| AnnaBridge | 126:abea610beb85 | 566 | * @arg DMA_IT_DME: Direct mode error interrupt. |
| AnnaBridge | 126:abea610beb85 | 567 | * @retval None |
| AnnaBridge | 126:abea610beb85 | 568 | */ |
| AnnaBridge | 126:abea610beb85 | 569 | #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
| AnnaBridge | 126:abea610beb85 | 570 | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) |
| AnnaBridge | 126:abea610beb85 | 571 | |
| AnnaBridge | 126:abea610beb85 | 572 | /** |
| AnnaBridge | 126:abea610beb85 | 573 | * @brief Disable the specified DMA Stream interrupts. |
| AnnaBridge | 126:abea610beb85 | 574 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 126:abea610beb85 | 575 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| AnnaBridge | 126:abea610beb85 | 576 | * This parameter can be one of the following values: |
| AnnaBridge | 126:abea610beb85 | 577 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
| AnnaBridge | 126:abea610beb85 | 578 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
| AnnaBridge | 126:abea610beb85 | 579 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
| AnnaBridge | 126:abea610beb85 | 580 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
| AnnaBridge | 126:abea610beb85 | 581 | * @arg DMA_IT_DME: Direct mode error interrupt. |
| AnnaBridge | 126:abea610beb85 | 582 | * @retval None |
| AnnaBridge | 126:abea610beb85 | 583 | */ |
| AnnaBridge | 126:abea610beb85 | 584 | #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
| AnnaBridge | 126:abea610beb85 | 585 | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) |
| AnnaBridge | 126:abea610beb85 | 586 | |
| AnnaBridge | 126:abea610beb85 | 587 | /** |
| AnnaBridge | 126:abea610beb85 | 588 | * @brief Check whether the specified DMA Stream interrupt is enabled or not. |
| AnnaBridge | 126:abea610beb85 | 589 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 126:abea610beb85 | 590 | * @param __INTERRUPT__: specifies the DMA interrupt source to check. |
| AnnaBridge | 126:abea610beb85 | 591 | * This parameter can be one of the following values: |
| AnnaBridge | 126:abea610beb85 | 592 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
| AnnaBridge | 126:abea610beb85 | 593 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
| AnnaBridge | 126:abea610beb85 | 594 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
| AnnaBridge | 126:abea610beb85 | 595 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
| AnnaBridge | 126:abea610beb85 | 596 | * @arg DMA_IT_DME: Direct mode error interrupt. |
| AnnaBridge | 126:abea610beb85 | 597 | * @retval The state of DMA_IT. |
| AnnaBridge | 126:abea610beb85 | 598 | */ |
| AnnaBridge | 126:abea610beb85 | 599 | #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
| AnnaBridge | 126:abea610beb85 | 600 | ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ |
| AnnaBridge | 126:abea610beb85 | 601 | ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) |
| AnnaBridge | 126:abea610beb85 | 602 | |
| AnnaBridge | 126:abea610beb85 | 603 | /** |
| AnnaBridge | 126:abea610beb85 | 604 | * @brief Writes the number of data units to be transferred on the DMA Stream. |
| AnnaBridge | 126:abea610beb85 | 605 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 126:abea610beb85 | 606 | * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) |
| AnnaBridge | 126:abea610beb85 | 607 | * Number of data items depends only on the Peripheral data format. |
| AnnaBridge | 126:abea610beb85 | 608 | * |
| AnnaBridge | 126:abea610beb85 | 609 | * @note If Peripheral data format is Bytes: number of data units is equal |
| AnnaBridge | 126:abea610beb85 | 610 | * to total number of bytes to be transferred. |
| AnnaBridge | 126:abea610beb85 | 611 | * |
| AnnaBridge | 126:abea610beb85 | 612 | * @note If Peripheral data format is Half-Word: number of data units is |
| AnnaBridge | 126:abea610beb85 | 613 | * equal to total number of bytes to be transferred / 2. |
| AnnaBridge | 126:abea610beb85 | 614 | * |
| AnnaBridge | 126:abea610beb85 | 615 | * @note If Peripheral data format is Word: number of data units is equal |
| AnnaBridge | 126:abea610beb85 | 616 | * to total number of bytes to be transferred / 4. |
| AnnaBridge | 126:abea610beb85 | 617 | * |
| AnnaBridge | 126:abea610beb85 | 618 | * @retval The number of remaining data units in the current DMAy Streamx transfer. |
| AnnaBridge | 126:abea610beb85 | 619 | */ |
| AnnaBridge | 126:abea610beb85 | 620 | #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) |
| AnnaBridge | 126:abea610beb85 | 621 | |
| AnnaBridge | 126:abea610beb85 | 622 | /** |
| AnnaBridge | 126:abea610beb85 | 623 | * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. |
| AnnaBridge | 126:abea610beb85 | 624 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 126:abea610beb85 | 625 | * |
| AnnaBridge | 126:abea610beb85 | 626 | * @retval The number of remaining data units in the current DMA Stream transfer. |
| AnnaBridge | 126:abea610beb85 | 627 | */ |
| AnnaBridge | 126:abea610beb85 | 628 | #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) |
| AnnaBridge | 126:abea610beb85 | 629 | |
| AnnaBridge | 126:abea610beb85 | 630 | |
| AnnaBridge | 126:abea610beb85 | 631 | /* Include DMA HAL Extension module */ |
| AnnaBridge | 126:abea610beb85 | 632 | #include "stm32f7xx_hal_dma_ex.h" |
| AnnaBridge | 126:abea610beb85 | 633 | |
| AnnaBridge | 126:abea610beb85 | 634 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 126:abea610beb85 | 635 | |
| AnnaBridge | 126:abea610beb85 | 636 | /** @defgroup DMA_Exported_Functions DMA Exported Functions |
| AnnaBridge | 126:abea610beb85 | 637 | * @brief DMA Exported functions |
| AnnaBridge | 126:abea610beb85 | 638 | * @{ |
| AnnaBridge | 126:abea610beb85 | 639 | */ |
| AnnaBridge | 126:abea610beb85 | 640 | |
| AnnaBridge | 126:abea610beb85 | 641 | /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions |
| AnnaBridge | 126:abea610beb85 | 642 | * @brief Initialization and de-initialization functions |
| AnnaBridge | 126:abea610beb85 | 643 | * @{ |
| AnnaBridge | 126:abea610beb85 | 644 | */ |
| AnnaBridge | 126:abea610beb85 | 645 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 126:abea610beb85 | 646 | HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 126:abea610beb85 | 647 | /** |
| AnnaBridge | 126:abea610beb85 | 648 | * @} |
| AnnaBridge | 126:abea610beb85 | 649 | */ |
| AnnaBridge | 126:abea610beb85 | 650 | |
| AnnaBridge | 126:abea610beb85 | 651 | /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions |
| AnnaBridge | 126:abea610beb85 | 652 | * @brief I/O operation functions |
| AnnaBridge | 126:abea610beb85 | 653 | * @{ |
| AnnaBridge | 126:abea610beb85 | 654 | */ |
| AnnaBridge | 126:abea610beb85 | 655 | HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| AnnaBridge | 126:abea610beb85 | 656 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| AnnaBridge | 126:abea610beb85 | 657 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 126:abea610beb85 | 658 | HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 126:abea610beb85 | 659 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); |
| AnnaBridge | 126:abea610beb85 | 660 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 126:abea610beb85 | 661 | HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 126:abea610beb85 | 662 | HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); |
| AnnaBridge | 126:abea610beb85 | 663 | HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); |
| AnnaBridge | 126:abea610beb85 | 664 | |
| AnnaBridge | 126:abea610beb85 | 665 | /** |
| AnnaBridge | 126:abea610beb85 | 666 | * @} |
| AnnaBridge | 126:abea610beb85 | 667 | */ |
| AnnaBridge | 126:abea610beb85 | 668 | |
| AnnaBridge | 126:abea610beb85 | 669 | /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions |
| AnnaBridge | 126:abea610beb85 | 670 | * @brief Peripheral State functions |
| AnnaBridge | 126:abea610beb85 | 671 | * @{ |
| AnnaBridge | 126:abea610beb85 | 672 | */ |
| AnnaBridge | 126:abea610beb85 | 673 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 126:abea610beb85 | 674 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 126:abea610beb85 | 675 | /** |
| AnnaBridge | 126:abea610beb85 | 676 | * @} |
| AnnaBridge | 126:abea610beb85 | 677 | */ |
| AnnaBridge | 126:abea610beb85 | 678 | /** |
| AnnaBridge | 126:abea610beb85 | 679 | * @} |
| AnnaBridge | 126:abea610beb85 | 680 | */ |
| AnnaBridge | 126:abea610beb85 | 681 | /* Private Constants -------------------------------------------------------------*/ |
| AnnaBridge | 126:abea610beb85 | 682 | /** @defgroup DMA_Private_Constants DMA Private Constants |
| AnnaBridge | 126:abea610beb85 | 683 | * @brief DMA private defines and constants |
| AnnaBridge | 126:abea610beb85 | 684 | * @{ |
| AnnaBridge | 126:abea610beb85 | 685 | */ |
| AnnaBridge | 126:abea610beb85 | 686 | /** |
| AnnaBridge | 126:abea610beb85 | 687 | * @} |
| AnnaBridge | 126:abea610beb85 | 688 | */ |
| AnnaBridge | 126:abea610beb85 | 689 | |
| AnnaBridge | 126:abea610beb85 | 690 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 126:abea610beb85 | 691 | /** @defgroup DMA_Private_Macros DMA Private Macros |
| AnnaBridge | 126:abea610beb85 | 692 | * @brief DMA private macros |
| AnnaBridge | 126:abea610beb85 | 693 | * @{ |
| AnnaBridge | 126:abea610beb85 | 694 | */ |
| AnnaBridge | 126:abea610beb85 | 695 | #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
| AnnaBridge | 126:abea610beb85 | 696 | ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ |
| AnnaBridge | 126:abea610beb85 | 697 | ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) |
| AnnaBridge | 126:abea610beb85 | 698 | |
| AnnaBridge | 126:abea610beb85 | 699 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) |
| AnnaBridge | 126:abea610beb85 | 700 | |
| AnnaBridge | 126:abea610beb85 | 701 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
| AnnaBridge | 126:abea610beb85 | 702 | ((STATE) == DMA_PINC_DISABLE)) |
| AnnaBridge | 126:abea610beb85 | 703 | |
| AnnaBridge | 126:abea610beb85 | 704 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
| AnnaBridge | 126:abea610beb85 | 705 | ((STATE) == DMA_MINC_DISABLE)) |
| AnnaBridge | 126:abea610beb85 | 706 | |
| AnnaBridge | 126:abea610beb85 | 707 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
| AnnaBridge | 126:abea610beb85 | 708 | ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ |
| AnnaBridge | 126:abea610beb85 | 709 | ((SIZE) == DMA_PDATAALIGN_WORD)) |
| AnnaBridge | 126:abea610beb85 | 710 | |
| AnnaBridge | 126:abea610beb85 | 711 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
| AnnaBridge | 126:abea610beb85 | 712 | ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ |
| AnnaBridge | 126:abea610beb85 | 713 | ((SIZE) == DMA_MDATAALIGN_WORD )) |
| AnnaBridge | 126:abea610beb85 | 714 | |
| AnnaBridge | 126:abea610beb85 | 715 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
| AnnaBridge | 126:abea610beb85 | 716 | ((MODE) == DMA_CIRCULAR) || \ |
| AnnaBridge | 126:abea610beb85 | 717 | ((MODE) == DMA_PFCTRL)) |
| AnnaBridge | 126:abea610beb85 | 718 | |
| AnnaBridge | 126:abea610beb85 | 719 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
| AnnaBridge | 126:abea610beb85 | 720 | ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ |
| AnnaBridge | 126:abea610beb85 | 721 | ((PRIORITY) == DMA_PRIORITY_HIGH) || \ |
| AnnaBridge | 126:abea610beb85 | 722 | ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) |
| AnnaBridge | 126:abea610beb85 | 723 | |
| AnnaBridge | 126:abea610beb85 | 724 | #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ |
| AnnaBridge | 126:abea610beb85 | 725 | ((STATE) == DMA_FIFOMODE_ENABLE)) |
| AnnaBridge | 126:abea610beb85 | 726 | |
| AnnaBridge | 126:abea610beb85 | 727 | #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ |
| AnnaBridge | 126:abea610beb85 | 728 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ |
| AnnaBridge | 126:abea610beb85 | 729 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ |
| AnnaBridge | 126:abea610beb85 | 730 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) |
| AnnaBridge | 126:abea610beb85 | 731 | |
| AnnaBridge | 126:abea610beb85 | 732 | #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ |
| AnnaBridge | 126:abea610beb85 | 733 | ((BURST) == DMA_MBURST_INC4) || \ |
| AnnaBridge | 126:abea610beb85 | 734 | ((BURST) == DMA_MBURST_INC8) || \ |
| AnnaBridge | 126:abea610beb85 | 735 | ((BURST) == DMA_MBURST_INC16)) |
| AnnaBridge | 126:abea610beb85 | 736 | |
| AnnaBridge | 126:abea610beb85 | 737 | #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ |
| AnnaBridge | 126:abea610beb85 | 738 | ((BURST) == DMA_PBURST_INC4) || \ |
| AnnaBridge | 126:abea610beb85 | 739 | ((BURST) == DMA_PBURST_INC8) || \ |
| AnnaBridge | 126:abea610beb85 | 740 | ((BURST) == DMA_PBURST_INC16)) |
| AnnaBridge | 126:abea610beb85 | 741 | /** |
| AnnaBridge | 126:abea610beb85 | 742 | * @} |
| AnnaBridge | 126:abea610beb85 | 743 | */ |
| AnnaBridge | 126:abea610beb85 | 744 | |
| AnnaBridge | 126:abea610beb85 | 745 | /* Private functions ---------------------------------------------------------*/ |
| AnnaBridge | 126:abea610beb85 | 746 | /** @defgroup DMA_Private_Functions DMA Private Functions |
| AnnaBridge | 126:abea610beb85 | 747 | * @brief DMA private functions |
| AnnaBridge | 126:abea610beb85 | 748 | * @{ |
| AnnaBridge | 126:abea610beb85 | 749 | */ |
| AnnaBridge | 126:abea610beb85 | 750 | /** |
| AnnaBridge | 126:abea610beb85 | 751 | * @} |
| AnnaBridge | 126:abea610beb85 | 752 | */ |
| AnnaBridge | 126:abea610beb85 | 753 | |
| AnnaBridge | 126:abea610beb85 | 754 | /** |
| AnnaBridge | 126:abea610beb85 | 755 | * @} |
| AnnaBridge | 126:abea610beb85 | 756 | */ |
| AnnaBridge | 126:abea610beb85 | 757 | |
| AnnaBridge | 126:abea610beb85 | 758 | /** |
| AnnaBridge | 126:abea610beb85 | 759 | * @} |
| AnnaBridge | 126:abea610beb85 | 760 | */ |
| AnnaBridge | 126:abea610beb85 | 761 | |
| AnnaBridge | 126:abea610beb85 | 762 | #ifdef __cplusplus |
| AnnaBridge | 126:abea610beb85 | 763 | } |
| AnnaBridge | 126:abea610beb85 | 764 | #endif |
| AnnaBridge | 126:abea610beb85 | 765 | |
| AnnaBridge | 126:abea610beb85 | 766 | #endif /* __STM32F7xx_HAL_DMA_H */ |
| AnnaBridge | 126:abea610beb85 | 767 | |
| AnnaBridge | 126:abea610beb85 | 768 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
