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TARGET_NUCLEO_F756ZG/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cortex.h@138:093f2bd7b9eb, 2017-03-14 (annotated)
- Committer:
- <>
- Date:
- Tue Mar 14 16:20:51 2017 +0000
- Revision:
- 138:093f2bd7b9eb
- Parent:
- 135:176b8275d35d
- Child:
- 139:856d2700e60b
Release 138 of the mbed library
Ports for Upcoming Targets
Fixes and Changes
3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716
3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741
3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780
3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831
3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836
3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840
3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844
3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850
3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860
3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880
3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795
3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828
3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842
3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843
3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879
3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902
3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 126:abea610beb85 | 1 | /** |
| AnnaBridge | 126:abea610beb85 | 2 | ****************************************************************************** |
| AnnaBridge | 126:abea610beb85 | 3 | * @file stm32f7xx_hal_cortex.h |
| AnnaBridge | 126:abea610beb85 | 4 | * @author MCD Application Team |
| <> | 135:176b8275d35d | 5 | * @version V1.1.2 |
| <> | 135:176b8275d35d | 6 | * @date 23-September-2016 |
| AnnaBridge | 126:abea610beb85 | 7 | * @brief Header file of CORTEX HAL module. |
| AnnaBridge | 126:abea610beb85 | 8 | ****************************************************************************** |
| AnnaBridge | 126:abea610beb85 | 9 | * @attention |
| AnnaBridge | 126:abea610beb85 | 10 | * |
| AnnaBridge | 126:abea610beb85 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 126:abea610beb85 | 12 | * |
| AnnaBridge | 126:abea610beb85 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 126:abea610beb85 | 14 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 126:abea610beb85 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 126:abea610beb85 | 16 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 126:abea610beb85 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 126:abea610beb85 | 18 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 126:abea610beb85 | 19 | * and/or other materials provided with the distribution. |
| AnnaBridge | 126:abea610beb85 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 126:abea610beb85 | 21 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 126:abea610beb85 | 22 | * without specific prior written permission. |
| AnnaBridge | 126:abea610beb85 | 23 | * |
| AnnaBridge | 126:abea610beb85 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 126:abea610beb85 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 126:abea610beb85 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 126:abea610beb85 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 126:abea610beb85 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 126:abea610beb85 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 126:abea610beb85 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 126:abea610beb85 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 126:abea610beb85 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 126:abea610beb85 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 126:abea610beb85 | 34 | * |
| AnnaBridge | 126:abea610beb85 | 35 | ****************************************************************************** |
| AnnaBridge | 126:abea610beb85 | 36 | */ |
| AnnaBridge | 126:abea610beb85 | 37 | |
| AnnaBridge | 126:abea610beb85 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 126:abea610beb85 | 39 | #ifndef __STM32F7xx_HAL_CORTEX_H |
| AnnaBridge | 126:abea610beb85 | 40 | #define __STM32F7xx_HAL_CORTEX_H |
| AnnaBridge | 126:abea610beb85 | 41 | |
| AnnaBridge | 126:abea610beb85 | 42 | #ifdef __cplusplus |
| AnnaBridge | 126:abea610beb85 | 43 | extern "C" { |
| AnnaBridge | 126:abea610beb85 | 44 | #endif |
| AnnaBridge | 126:abea610beb85 | 45 | |
| AnnaBridge | 126:abea610beb85 | 46 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 126:abea610beb85 | 47 | #include "stm32f7xx_hal_def.h" |
| AnnaBridge | 126:abea610beb85 | 48 | |
| AnnaBridge | 126:abea610beb85 | 49 | /** @addtogroup STM32F7xx_HAL_Driver |
| AnnaBridge | 126:abea610beb85 | 50 | * @{ |
| AnnaBridge | 126:abea610beb85 | 51 | */ |
| AnnaBridge | 126:abea610beb85 | 52 | |
| AnnaBridge | 126:abea610beb85 | 53 | /** @addtogroup CORTEX |
| AnnaBridge | 126:abea610beb85 | 54 | * @{ |
| AnnaBridge | 126:abea610beb85 | 55 | */ |
| AnnaBridge | 126:abea610beb85 | 56 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 126:abea610beb85 | 57 | /** @defgroup CORTEX_Exported_Types Cortex Exported Types |
| AnnaBridge | 126:abea610beb85 | 58 | * @{ |
| AnnaBridge | 126:abea610beb85 | 59 | */ |
| AnnaBridge | 126:abea610beb85 | 60 | |
| AnnaBridge | 126:abea610beb85 | 61 | #if (__MPU_PRESENT == 1) |
| AnnaBridge | 126:abea610beb85 | 62 | /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition |
| AnnaBridge | 126:abea610beb85 | 63 | * @brief MPU Region initialization structure |
| AnnaBridge | 126:abea610beb85 | 64 | * @{ |
| AnnaBridge | 126:abea610beb85 | 65 | */ |
| AnnaBridge | 126:abea610beb85 | 66 | typedef struct |
| AnnaBridge | 126:abea610beb85 | 67 | { |
| AnnaBridge | 126:abea610beb85 | 68 | uint8_t Enable; /*!< Specifies the status of the region. |
| AnnaBridge | 126:abea610beb85 | 69 | This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ |
| AnnaBridge | 126:abea610beb85 | 70 | uint8_t Number; /*!< Specifies the number of the region to protect. |
| AnnaBridge | 126:abea610beb85 | 71 | This parameter can be a value of @ref CORTEX_MPU_Region_Number */ |
| AnnaBridge | 126:abea610beb85 | 72 | uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ |
| AnnaBridge | 126:abea610beb85 | 73 | uint8_t Size; /*!< Specifies the size of the region to protect. |
| AnnaBridge | 126:abea610beb85 | 74 | This parameter can be a value of @ref CORTEX_MPU_Region_Size */ |
| AnnaBridge | 126:abea610beb85 | 75 | uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. |
| AnnaBridge | 126:abea610beb85 | 76 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
| AnnaBridge | 126:abea610beb85 | 77 | uint8_t TypeExtField; /*!< Specifies the TEX field level. |
| AnnaBridge | 126:abea610beb85 | 78 | This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ |
| AnnaBridge | 126:abea610beb85 | 79 | uint8_t AccessPermission; /*!< Specifies the region access permission type. |
| AnnaBridge | 126:abea610beb85 | 80 | This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ |
| AnnaBridge | 126:abea610beb85 | 81 | uint8_t DisableExec; /*!< Specifies the instruction access status. |
| AnnaBridge | 126:abea610beb85 | 82 | This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ |
| AnnaBridge | 126:abea610beb85 | 83 | uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. |
| AnnaBridge | 126:abea610beb85 | 84 | This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ |
| AnnaBridge | 126:abea610beb85 | 85 | uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. |
| AnnaBridge | 126:abea610beb85 | 86 | This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ |
| AnnaBridge | 126:abea610beb85 | 87 | uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. |
| AnnaBridge | 126:abea610beb85 | 88 | This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ |
| AnnaBridge | 126:abea610beb85 | 89 | }MPU_Region_InitTypeDef; |
| AnnaBridge | 126:abea610beb85 | 90 | /** |
| AnnaBridge | 126:abea610beb85 | 91 | * @} |
| AnnaBridge | 126:abea610beb85 | 92 | */ |
| AnnaBridge | 126:abea610beb85 | 93 | #endif /* __MPU_PRESENT */ |
| AnnaBridge | 126:abea610beb85 | 94 | |
| AnnaBridge | 126:abea610beb85 | 95 | /** |
| AnnaBridge | 126:abea610beb85 | 96 | * @} |
| AnnaBridge | 126:abea610beb85 | 97 | */ |
| AnnaBridge | 126:abea610beb85 | 98 | |
| AnnaBridge | 126:abea610beb85 | 99 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 126:abea610beb85 | 100 | |
| AnnaBridge | 126:abea610beb85 | 101 | /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants |
| AnnaBridge | 126:abea610beb85 | 102 | * @{ |
| AnnaBridge | 126:abea610beb85 | 103 | */ |
| AnnaBridge | 126:abea610beb85 | 104 | |
| AnnaBridge | 126:abea610beb85 | 105 | /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group |
| AnnaBridge | 126:abea610beb85 | 106 | * @{ |
| AnnaBridge | 126:abea610beb85 | 107 | */ |
| AnnaBridge | 126:abea610beb85 | 108 | #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority |
| AnnaBridge | 126:abea610beb85 | 109 | 4 bits for subpriority */ |
| AnnaBridge | 126:abea610beb85 | 110 | #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority |
| AnnaBridge | 126:abea610beb85 | 111 | 3 bits for subpriority */ |
| AnnaBridge | 126:abea610beb85 | 112 | #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority |
| AnnaBridge | 126:abea610beb85 | 113 | 2 bits for subpriority */ |
| AnnaBridge | 126:abea610beb85 | 114 | #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority |
| AnnaBridge | 126:abea610beb85 | 115 | 1 bits for subpriority */ |
| AnnaBridge | 126:abea610beb85 | 116 | #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority |
| AnnaBridge | 126:abea610beb85 | 117 | 0 bits for subpriority */ |
| AnnaBridge | 126:abea610beb85 | 118 | /** |
| AnnaBridge | 126:abea610beb85 | 119 | * @} |
| AnnaBridge | 126:abea610beb85 | 120 | */ |
| AnnaBridge | 126:abea610beb85 | 121 | |
| AnnaBridge | 126:abea610beb85 | 122 | /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source |
| AnnaBridge | 126:abea610beb85 | 123 | * @{ |
| AnnaBridge | 126:abea610beb85 | 124 | */ |
| AnnaBridge | 126:abea610beb85 | 125 | #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) |
| AnnaBridge | 126:abea610beb85 | 126 | #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) |
| AnnaBridge | 126:abea610beb85 | 127 | |
| AnnaBridge | 126:abea610beb85 | 128 | /** |
| AnnaBridge | 126:abea610beb85 | 129 | * @} |
| AnnaBridge | 126:abea610beb85 | 130 | */ |
| AnnaBridge | 126:abea610beb85 | 131 | |
| AnnaBridge | 126:abea610beb85 | 132 | #if (__MPU_PRESENT == 1) |
| AnnaBridge | 126:abea610beb85 | 133 | /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control |
| AnnaBridge | 126:abea610beb85 | 134 | * @{ |
| AnnaBridge | 126:abea610beb85 | 135 | */ |
| AnnaBridge | 126:abea610beb85 | 136 | #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) |
| AnnaBridge | 126:abea610beb85 | 137 | #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U) |
| AnnaBridge | 126:abea610beb85 | 138 | #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U) |
| AnnaBridge | 126:abea610beb85 | 139 | #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U) |
| AnnaBridge | 126:abea610beb85 | 140 | /** |
| AnnaBridge | 126:abea610beb85 | 141 | * @} |
| AnnaBridge | 126:abea610beb85 | 142 | */ |
| AnnaBridge | 126:abea610beb85 | 143 | |
| AnnaBridge | 126:abea610beb85 | 144 | /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable |
| AnnaBridge | 126:abea610beb85 | 145 | * @{ |
| AnnaBridge | 126:abea610beb85 | 146 | */ |
| AnnaBridge | 126:abea610beb85 | 147 | #define MPU_REGION_ENABLE ((uint8_t)0x01U) |
| AnnaBridge | 126:abea610beb85 | 148 | #define MPU_REGION_DISABLE ((uint8_t)0x00U) |
| AnnaBridge | 126:abea610beb85 | 149 | /** |
| AnnaBridge | 126:abea610beb85 | 150 | * @} |
| AnnaBridge | 126:abea610beb85 | 151 | */ |
| AnnaBridge | 126:abea610beb85 | 152 | |
| AnnaBridge | 126:abea610beb85 | 153 | /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access |
| AnnaBridge | 126:abea610beb85 | 154 | * @{ |
| AnnaBridge | 126:abea610beb85 | 155 | */ |
| AnnaBridge | 126:abea610beb85 | 156 | #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U) |
| AnnaBridge | 126:abea610beb85 | 157 | #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U) |
| AnnaBridge | 126:abea610beb85 | 158 | /** |
| AnnaBridge | 126:abea610beb85 | 159 | * @} |
| AnnaBridge | 126:abea610beb85 | 160 | */ |
| AnnaBridge | 126:abea610beb85 | 161 | |
| AnnaBridge | 126:abea610beb85 | 162 | /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable |
| AnnaBridge | 126:abea610beb85 | 163 | * @{ |
| AnnaBridge | 126:abea610beb85 | 164 | */ |
| AnnaBridge | 126:abea610beb85 | 165 | #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U) |
| AnnaBridge | 126:abea610beb85 | 166 | #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U) |
| AnnaBridge | 126:abea610beb85 | 167 | /** |
| AnnaBridge | 126:abea610beb85 | 168 | * @} |
| AnnaBridge | 126:abea610beb85 | 169 | */ |
| AnnaBridge | 126:abea610beb85 | 170 | |
| AnnaBridge | 126:abea610beb85 | 171 | /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable |
| AnnaBridge | 126:abea610beb85 | 172 | * @{ |
| AnnaBridge | 126:abea610beb85 | 173 | */ |
| AnnaBridge | 126:abea610beb85 | 174 | #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U) |
| AnnaBridge | 126:abea610beb85 | 175 | #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U) |
| AnnaBridge | 126:abea610beb85 | 176 | /** |
| AnnaBridge | 126:abea610beb85 | 177 | * @} |
| AnnaBridge | 126:abea610beb85 | 178 | */ |
| AnnaBridge | 126:abea610beb85 | 179 | |
| AnnaBridge | 126:abea610beb85 | 180 | /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable |
| AnnaBridge | 126:abea610beb85 | 181 | * @{ |
| AnnaBridge | 126:abea610beb85 | 182 | */ |
| AnnaBridge | 126:abea610beb85 | 183 | #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U) |
| AnnaBridge | 126:abea610beb85 | 184 | #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U) |
| AnnaBridge | 126:abea610beb85 | 185 | /** |
| AnnaBridge | 126:abea610beb85 | 186 | * @} |
| AnnaBridge | 126:abea610beb85 | 187 | */ |
| AnnaBridge | 126:abea610beb85 | 188 | |
| AnnaBridge | 126:abea610beb85 | 189 | /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels |
| AnnaBridge | 126:abea610beb85 | 190 | * @{ |
| AnnaBridge | 126:abea610beb85 | 191 | */ |
| AnnaBridge | 126:abea610beb85 | 192 | #define MPU_TEX_LEVEL0 ((uint8_t)0x00U) |
| AnnaBridge | 126:abea610beb85 | 193 | #define MPU_TEX_LEVEL1 ((uint8_t)0x01U) |
| AnnaBridge | 126:abea610beb85 | 194 | #define MPU_TEX_LEVEL2 ((uint8_t)0x02U) |
| AnnaBridge | 126:abea610beb85 | 195 | /** |
| AnnaBridge | 126:abea610beb85 | 196 | * @} |
| AnnaBridge | 126:abea610beb85 | 197 | */ |
| AnnaBridge | 126:abea610beb85 | 198 | |
| AnnaBridge | 126:abea610beb85 | 199 | /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size |
| AnnaBridge | 126:abea610beb85 | 200 | * @{ |
| AnnaBridge | 126:abea610beb85 | 201 | */ |
| AnnaBridge | 126:abea610beb85 | 202 | #define MPU_REGION_SIZE_32B ((uint8_t)0x04U) |
| AnnaBridge | 126:abea610beb85 | 203 | #define MPU_REGION_SIZE_64B ((uint8_t)0x05U) |
| AnnaBridge | 126:abea610beb85 | 204 | #define MPU_REGION_SIZE_128B ((uint8_t)0x06U) |
| AnnaBridge | 126:abea610beb85 | 205 | #define MPU_REGION_SIZE_256B ((uint8_t)0x07U) |
| AnnaBridge | 126:abea610beb85 | 206 | #define MPU_REGION_SIZE_512B ((uint8_t)0x08U) |
| AnnaBridge | 126:abea610beb85 | 207 | #define MPU_REGION_SIZE_1KB ((uint8_t)0x09U) |
| AnnaBridge | 126:abea610beb85 | 208 | #define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) |
| AnnaBridge | 126:abea610beb85 | 209 | #define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) |
| AnnaBridge | 126:abea610beb85 | 210 | #define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) |
| AnnaBridge | 126:abea610beb85 | 211 | #define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) |
| AnnaBridge | 126:abea610beb85 | 212 | #define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) |
| AnnaBridge | 126:abea610beb85 | 213 | #define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) |
| AnnaBridge | 126:abea610beb85 | 214 | #define MPU_REGION_SIZE_128KB ((uint8_t)0x10U) |
| AnnaBridge | 126:abea610beb85 | 215 | #define MPU_REGION_SIZE_256KB ((uint8_t)0x11U) |
| AnnaBridge | 126:abea610beb85 | 216 | #define MPU_REGION_SIZE_512KB ((uint8_t)0x12U) |
| AnnaBridge | 126:abea610beb85 | 217 | #define MPU_REGION_SIZE_1MB ((uint8_t)0x13U) |
| AnnaBridge | 126:abea610beb85 | 218 | #define MPU_REGION_SIZE_2MB ((uint8_t)0x14U) |
| AnnaBridge | 126:abea610beb85 | 219 | #define MPU_REGION_SIZE_4MB ((uint8_t)0x15U) |
| AnnaBridge | 126:abea610beb85 | 220 | #define MPU_REGION_SIZE_8MB ((uint8_t)0x16U) |
| AnnaBridge | 126:abea610beb85 | 221 | #define MPU_REGION_SIZE_16MB ((uint8_t)0x17U) |
| AnnaBridge | 126:abea610beb85 | 222 | #define MPU_REGION_SIZE_32MB ((uint8_t)0x18U) |
| AnnaBridge | 126:abea610beb85 | 223 | #define MPU_REGION_SIZE_64MB ((uint8_t)0x19U) |
| AnnaBridge | 126:abea610beb85 | 224 | #define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) |
| AnnaBridge | 126:abea610beb85 | 225 | #define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) |
| AnnaBridge | 126:abea610beb85 | 226 | #define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) |
| AnnaBridge | 126:abea610beb85 | 227 | #define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) |
| AnnaBridge | 126:abea610beb85 | 228 | #define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) |
| AnnaBridge | 126:abea610beb85 | 229 | #define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) |
| AnnaBridge | 126:abea610beb85 | 230 | /** |
| AnnaBridge | 126:abea610beb85 | 231 | * @} |
| AnnaBridge | 126:abea610beb85 | 232 | */ |
| AnnaBridge | 126:abea610beb85 | 233 | |
| AnnaBridge | 126:abea610beb85 | 234 | /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes |
| AnnaBridge | 126:abea610beb85 | 235 | * @{ |
| AnnaBridge | 126:abea610beb85 | 236 | */ |
| AnnaBridge | 126:abea610beb85 | 237 | #define MPU_REGION_NO_ACCESS ((uint8_t)0x00U) |
| AnnaBridge | 126:abea610beb85 | 238 | #define MPU_REGION_PRIV_RW ((uint8_t)0x01U) |
| AnnaBridge | 126:abea610beb85 | 239 | #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U) |
| AnnaBridge | 126:abea610beb85 | 240 | #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U) |
| AnnaBridge | 126:abea610beb85 | 241 | #define MPU_REGION_PRIV_RO ((uint8_t)0x05U) |
| AnnaBridge | 126:abea610beb85 | 242 | #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U) |
| AnnaBridge | 126:abea610beb85 | 243 | /** |
| AnnaBridge | 126:abea610beb85 | 244 | * @} |
| AnnaBridge | 126:abea610beb85 | 245 | */ |
| AnnaBridge | 126:abea610beb85 | 246 | |
| AnnaBridge | 126:abea610beb85 | 247 | /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number |
| AnnaBridge | 126:abea610beb85 | 248 | * @{ |
| AnnaBridge | 126:abea610beb85 | 249 | */ |
| AnnaBridge | 126:abea610beb85 | 250 | #define MPU_REGION_NUMBER0 ((uint8_t)0x00U) |
| AnnaBridge | 126:abea610beb85 | 251 | #define MPU_REGION_NUMBER1 ((uint8_t)0x01U) |
| AnnaBridge | 126:abea610beb85 | 252 | #define MPU_REGION_NUMBER2 ((uint8_t)0x02U) |
| AnnaBridge | 126:abea610beb85 | 253 | #define MPU_REGION_NUMBER3 ((uint8_t)0x03U) |
| AnnaBridge | 126:abea610beb85 | 254 | #define MPU_REGION_NUMBER4 ((uint8_t)0x04U) |
| AnnaBridge | 126:abea610beb85 | 255 | #define MPU_REGION_NUMBER5 ((uint8_t)0x05U) |
| AnnaBridge | 126:abea610beb85 | 256 | #define MPU_REGION_NUMBER6 ((uint8_t)0x06U) |
| AnnaBridge | 126:abea610beb85 | 257 | #define MPU_REGION_NUMBER7 ((uint8_t)0x07U) |
| AnnaBridge | 126:abea610beb85 | 258 | /** |
| AnnaBridge | 126:abea610beb85 | 259 | * @} |
| AnnaBridge | 126:abea610beb85 | 260 | */ |
| AnnaBridge | 126:abea610beb85 | 261 | #endif /* __MPU_PRESENT */ |
| AnnaBridge | 126:abea610beb85 | 262 | |
| AnnaBridge | 126:abea610beb85 | 263 | /** |
| AnnaBridge | 126:abea610beb85 | 264 | * @} |
| AnnaBridge | 126:abea610beb85 | 265 | */ |
| AnnaBridge | 126:abea610beb85 | 266 | |
| AnnaBridge | 126:abea610beb85 | 267 | |
| AnnaBridge | 126:abea610beb85 | 268 | /* Exported Macros -----------------------------------------------------------*/ |
| AnnaBridge | 126:abea610beb85 | 269 | |
| AnnaBridge | 126:abea610beb85 | 270 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 126:abea610beb85 | 271 | /** @addtogroup CORTEX_Exported_Functions |
| AnnaBridge | 126:abea610beb85 | 272 | * @{ |
| AnnaBridge | 126:abea610beb85 | 273 | */ |
| AnnaBridge | 126:abea610beb85 | 274 | |
| AnnaBridge | 126:abea610beb85 | 275 | /** @addtogroup CORTEX_Exported_Functions_Group1 |
| AnnaBridge | 126:abea610beb85 | 276 | * @{ |
| AnnaBridge | 126:abea610beb85 | 277 | */ |
| AnnaBridge | 126:abea610beb85 | 278 | /* Initialization and de-initialization functions *****************************/ |
| AnnaBridge | 126:abea610beb85 | 279 | void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); |
| AnnaBridge | 126:abea610beb85 | 280 | void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); |
| AnnaBridge | 126:abea610beb85 | 281 | void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); |
| AnnaBridge | 126:abea610beb85 | 282 | void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); |
| AnnaBridge | 126:abea610beb85 | 283 | void HAL_NVIC_SystemReset(void); |
| AnnaBridge | 126:abea610beb85 | 284 | uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); |
| AnnaBridge | 126:abea610beb85 | 285 | /** |
| AnnaBridge | 126:abea610beb85 | 286 | * @} |
| AnnaBridge | 126:abea610beb85 | 287 | */ |
| AnnaBridge | 126:abea610beb85 | 288 | |
| AnnaBridge | 126:abea610beb85 | 289 | /** @addtogroup CORTEX_Exported_Functions_Group2 |
| AnnaBridge | 126:abea610beb85 | 290 | * @{ |
| AnnaBridge | 126:abea610beb85 | 291 | */ |
| AnnaBridge | 126:abea610beb85 | 292 | /* Peripheral Control functions ***********************************************/ |
| AnnaBridge | 126:abea610beb85 | 293 | #if (__MPU_PRESENT == 1) |
| <> | 135:176b8275d35d | 294 | void HAL_MPU_Enable(uint32_t MPU_Control); |
| <> | 135:176b8275d35d | 295 | void HAL_MPU_Disable(void); |
| AnnaBridge | 126:abea610beb85 | 296 | void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); |
| AnnaBridge | 126:abea610beb85 | 297 | #endif /* __MPU_PRESENT */ |
| AnnaBridge | 126:abea610beb85 | 298 | uint32_t HAL_NVIC_GetPriorityGrouping(void); |
| AnnaBridge | 126:abea610beb85 | 299 | void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); |
| AnnaBridge | 126:abea610beb85 | 300 | uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); |
| AnnaBridge | 126:abea610beb85 | 301 | void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); |
| AnnaBridge | 126:abea610beb85 | 302 | void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); |
| AnnaBridge | 126:abea610beb85 | 303 | uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); |
| AnnaBridge | 126:abea610beb85 | 304 | void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); |
| AnnaBridge | 126:abea610beb85 | 305 | void HAL_SYSTICK_IRQHandler(void); |
| AnnaBridge | 126:abea610beb85 | 306 | void HAL_SYSTICK_Callback(void); |
| AnnaBridge | 126:abea610beb85 | 307 | /** |
| AnnaBridge | 126:abea610beb85 | 308 | * @} |
| AnnaBridge | 126:abea610beb85 | 309 | */ |
| AnnaBridge | 126:abea610beb85 | 310 | |
| AnnaBridge | 126:abea610beb85 | 311 | /** |
| AnnaBridge | 126:abea610beb85 | 312 | * @} |
| AnnaBridge | 126:abea610beb85 | 313 | */ |
| AnnaBridge | 126:abea610beb85 | 314 | |
| AnnaBridge | 126:abea610beb85 | 315 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 126:abea610beb85 | 316 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 126:abea610beb85 | 317 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 126:abea610beb85 | 318 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 126:abea610beb85 | 319 | /** @defgroup CORTEX_Private_Macros CORTEX Private Macros |
| AnnaBridge | 126:abea610beb85 | 320 | * @{ |
| AnnaBridge | 126:abea610beb85 | 321 | */ |
| AnnaBridge | 126:abea610beb85 | 322 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ |
| AnnaBridge | 126:abea610beb85 | 323 | ((GROUP) == NVIC_PRIORITYGROUP_1) || \ |
| AnnaBridge | 126:abea610beb85 | 324 | ((GROUP) == NVIC_PRIORITYGROUP_2) || \ |
| AnnaBridge | 126:abea610beb85 | 325 | ((GROUP) == NVIC_PRIORITYGROUP_3) || \ |
| AnnaBridge | 126:abea610beb85 | 326 | ((GROUP) == NVIC_PRIORITYGROUP_4)) |
| AnnaBridge | 126:abea610beb85 | 327 | |
| AnnaBridge | 126:abea610beb85 | 328 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) |
| AnnaBridge | 126:abea610beb85 | 329 | |
| AnnaBridge | 126:abea610beb85 | 330 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) |
| AnnaBridge | 126:abea610beb85 | 331 | |
| AnnaBridge | 126:abea610beb85 | 332 | #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) |
| AnnaBridge | 126:abea610beb85 | 333 | |
| AnnaBridge | 126:abea610beb85 | 334 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ |
| AnnaBridge | 126:abea610beb85 | 335 | ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) |
| AnnaBridge | 126:abea610beb85 | 336 | |
| AnnaBridge | 126:abea610beb85 | 337 | #if (__MPU_PRESENT == 1) |
| AnnaBridge | 126:abea610beb85 | 338 | #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ |
| AnnaBridge | 126:abea610beb85 | 339 | ((STATE) == MPU_REGION_DISABLE)) |
| AnnaBridge | 126:abea610beb85 | 340 | |
| AnnaBridge | 126:abea610beb85 | 341 | #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ |
| AnnaBridge | 126:abea610beb85 | 342 | ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) |
| AnnaBridge | 126:abea610beb85 | 343 | |
| AnnaBridge | 126:abea610beb85 | 344 | #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ |
| AnnaBridge | 126:abea610beb85 | 345 | ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) |
| AnnaBridge | 126:abea610beb85 | 346 | |
| AnnaBridge | 126:abea610beb85 | 347 | #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ |
| AnnaBridge | 126:abea610beb85 | 348 | ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) |
| AnnaBridge | 126:abea610beb85 | 349 | |
| AnnaBridge | 126:abea610beb85 | 350 | #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ |
| AnnaBridge | 126:abea610beb85 | 351 | ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) |
| AnnaBridge | 126:abea610beb85 | 352 | |
| AnnaBridge | 126:abea610beb85 | 353 | #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ |
| AnnaBridge | 126:abea610beb85 | 354 | ((TYPE) == MPU_TEX_LEVEL1) || \ |
| AnnaBridge | 126:abea610beb85 | 355 | ((TYPE) == MPU_TEX_LEVEL2)) |
| AnnaBridge | 126:abea610beb85 | 356 | |
| AnnaBridge | 126:abea610beb85 | 357 | #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ |
| AnnaBridge | 126:abea610beb85 | 358 | ((TYPE) == MPU_REGION_PRIV_RW) || \ |
| AnnaBridge | 126:abea610beb85 | 359 | ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ |
| AnnaBridge | 126:abea610beb85 | 360 | ((TYPE) == MPU_REGION_FULL_ACCESS) || \ |
| AnnaBridge | 126:abea610beb85 | 361 | ((TYPE) == MPU_REGION_PRIV_RO) || \ |
| AnnaBridge | 126:abea610beb85 | 362 | ((TYPE) == MPU_REGION_PRIV_RO_URO)) |
| AnnaBridge | 126:abea610beb85 | 363 | |
| AnnaBridge | 126:abea610beb85 | 364 | #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ |
| AnnaBridge | 126:abea610beb85 | 365 | ((NUMBER) == MPU_REGION_NUMBER1) || \ |
| AnnaBridge | 126:abea610beb85 | 366 | ((NUMBER) == MPU_REGION_NUMBER2) || \ |
| AnnaBridge | 126:abea610beb85 | 367 | ((NUMBER) == MPU_REGION_NUMBER3) || \ |
| AnnaBridge | 126:abea610beb85 | 368 | ((NUMBER) == MPU_REGION_NUMBER4) || \ |
| AnnaBridge | 126:abea610beb85 | 369 | ((NUMBER) == MPU_REGION_NUMBER5) || \ |
| AnnaBridge | 126:abea610beb85 | 370 | ((NUMBER) == MPU_REGION_NUMBER6) || \ |
| AnnaBridge | 126:abea610beb85 | 371 | ((NUMBER) == MPU_REGION_NUMBER7)) |
| AnnaBridge | 126:abea610beb85 | 372 | |
| AnnaBridge | 126:abea610beb85 | 373 | #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ |
| AnnaBridge | 126:abea610beb85 | 374 | ((SIZE) == MPU_REGION_SIZE_64B) || \ |
| AnnaBridge | 126:abea610beb85 | 375 | ((SIZE) == MPU_REGION_SIZE_128B) || \ |
| AnnaBridge | 126:abea610beb85 | 376 | ((SIZE) == MPU_REGION_SIZE_256B) || \ |
| AnnaBridge | 126:abea610beb85 | 377 | ((SIZE) == MPU_REGION_SIZE_512B) || \ |
| AnnaBridge | 126:abea610beb85 | 378 | ((SIZE) == MPU_REGION_SIZE_1KB) || \ |
| AnnaBridge | 126:abea610beb85 | 379 | ((SIZE) == MPU_REGION_SIZE_2KB) || \ |
| AnnaBridge | 126:abea610beb85 | 380 | ((SIZE) == MPU_REGION_SIZE_4KB) || \ |
| AnnaBridge | 126:abea610beb85 | 381 | ((SIZE) == MPU_REGION_SIZE_8KB) || \ |
| AnnaBridge | 126:abea610beb85 | 382 | ((SIZE) == MPU_REGION_SIZE_16KB) || \ |
| AnnaBridge | 126:abea610beb85 | 383 | ((SIZE) == MPU_REGION_SIZE_32KB) || \ |
| AnnaBridge | 126:abea610beb85 | 384 | ((SIZE) == MPU_REGION_SIZE_64KB) || \ |
| AnnaBridge | 126:abea610beb85 | 385 | ((SIZE) == MPU_REGION_SIZE_128KB) || \ |
| AnnaBridge | 126:abea610beb85 | 386 | ((SIZE) == MPU_REGION_SIZE_256KB) || \ |
| AnnaBridge | 126:abea610beb85 | 387 | ((SIZE) == MPU_REGION_SIZE_512KB) || \ |
| AnnaBridge | 126:abea610beb85 | 388 | ((SIZE) == MPU_REGION_SIZE_1MB) || \ |
| AnnaBridge | 126:abea610beb85 | 389 | ((SIZE) == MPU_REGION_SIZE_2MB) || \ |
| AnnaBridge | 126:abea610beb85 | 390 | ((SIZE) == MPU_REGION_SIZE_4MB) || \ |
| AnnaBridge | 126:abea610beb85 | 391 | ((SIZE) == MPU_REGION_SIZE_8MB) || \ |
| AnnaBridge | 126:abea610beb85 | 392 | ((SIZE) == MPU_REGION_SIZE_16MB) || \ |
| AnnaBridge | 126:abea610beb85 | 393 | ((SIZE) == MPU_REGION_SIZE_32MB) || \ |
| AnnaBridge | 126:abea610beb85 | 394 | ((SIZE) == MPU_REGION_SIZE_64MB) || \ |
| AnnaBridge | 126:abea610beb85 | 395 | ((SIZE) == MPU_REGION_SIZE_128MB) || \ |
| AnnaBridge | 126:abea610beb85 | 396 | ((SIZE) == MPU_REGION_SIZE_256MB) || \ |
| AnnaBridge | 126:abea610beb85 | 397 | ((SIZE) == MPU_REGION_SIZE_512MB) || \ |
| AnnaBridge | 126:abea610beb85 | 398 | ((SIZE) == MPU_REGION_SIZE_1GB) || \ |
| AnnaBridge | 126:abea610beb85 | 399 | ((SIZE) == MPU_REGION_SIZE_2GB) || \ |
| AnnaBridge | 126:abea610beb85 | 400 | ((SIZE) == MPU_REGION_SIZE_4GB)) |
| AnnaBridge | 126:abea610beb85 | 401 | |
| AnnaBridge | 126:abea610beb85 | 402 | #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) |
| AnnaBridge | 126:abea610beb85 | 403 | #endif /* __MPU_PRESENT */ |
| AnnaBridge | 126:abea610beb85 | 404 | |
| AnnaBridge | 126:abea610beb85 | 405 | /** |
| <> | 135:176b8275d35d | 406 | * @} |
| AnnaBridge | 126:abea610beb85 | 407 | */ |
| AnnaBridge | 126:abea610beb85 | 408 | |
| AnnaBridge | 126:abea610beb85 | 409 | /** |
| AnnaBridge | 126:abea610beb85 | 410 | * @} |
| AnnaBridge | 126:abea610beb85 | 411 | */ |
| AnnaBridge | 126:abea610beb85 | 412 | |
| AnnaBridge | 126:abea610beb85 | 413 | /** |
| AnnaBridge | 126:abea610beb85 | 414 | * @} |
| AnnaBridge | 126:abea610beb85 | 415 | */ |
| AnnaBridge | 126:abea610beb85 | 416 | |
| AnnaBridge | 126:abea610beb85 | 417 | #ifdef __cplusplus |
| AnnaBridge | 126:abea610beb85 | 418 | } |
| AnnaBridge | 126:abea610beb85 | 419 | #endif |
| AnnaBridge | 126:abea610beb85 | 420 | |
| AnnaBridge | 126:abea610beb85 | 421 | #endif /* __STM32F7xx_HAL_CORTEX_H */ |
| AnnaBridge | 126:abea610beb85 | 422 | |
| AnnaBridge | 126:abea610beb85 | 423 | |
| AnnaBridge | 126:abea610beb85 | 424 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
