mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_dma.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of DMA HAL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F0xx_HAL_DMA_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F0xx_HAL_DMA_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup DMA
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /** @defgroup DMA_Exported_Types DMA Exported Types
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /**
<> 144:ef7eb2e8f9f7 62 * @brief DMA Configuration Structure definition
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64 typedef struct
<> 144:ef7eb2e8f9f7 65 {
<> 144:ef7eb2e8f9f7 66 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
<> 144:ef7eb2e8f9f7 67 from memory to memory or from peripheral to memory.
<> 144:ef7eb2e8f9f7 68 This parameter can be a value of @ref DMA_Data_transfer_direction */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
<> 144:ef7eb2e8f9f7 71 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
<> 144:ef7eb2e8f9f7 74 This parameter can be a value of @ref DMA_Memory_incremented_mode */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
<> 144:ef7eb2e8f9f7 77 This parameter can be a value of @ref DMA_Peripheral_data_size */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
<> 144:ef7eb2e8f9f7 80 This parameter can be a value of @ref DMA_Memory_data_size */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
<> 144:ef7eb2e8f9f7 83 This parameter can be a value of @ref DMA_mode
<> 144:ef7eb2e8f9f7 84 @note The circular buffer mode cannot be used if the memory-to-memory
<> 144:ef7eb2e8f9f7 85 data transfer is configured on the selected Channel */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
<> 144:ef7eb2e8f9f7 88 This parameter can be a value of @ref DMA_Priority_level */
<> 144:ef7eb2e8f9f7 89 } DMA_InitTypeDef;
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /**
<> 144:ef7eb2e8f9f7 92 * @brief HAL DMA State structures definition
<> 144:ef7eb2e8f9f7 93 */
<> 144:ef7eb2e8f9f7 94 typedef enum
<> 144:ef7eb2e8f9f7 95 {
<> 156:95d6b41a828b 96 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
<> 156:95d6b41a828b 97 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
<> 156:95d6b41a828b 98 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
<> 156:95d6b41a828b 99 HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */
<> 144:ef7eb2e8f9f7 100 }HAL_DMA_StateTypeDef;
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /**
<> 144:ef7eb2e8f9f7 103 * @brief HAL DMA Error Code structure definition
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105 typedef enum
<> 144:ef7eb2e8f9f7 106 {
<> 156:95d6b41a828b 107 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
<> 156:95d6b41a828b 108 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
<> 156:95d6b41a828b 109 }HAL_DMA_LevelCompleteTypeDef;
<> 156:95d6b41a828b 110
<> 156:95d6b41a828b 111 /**
<> 156:95d6b41a828b 112 * @brief HAL DMA Callback ID structure definition
<> 156:95d6b41a828b 113 */
<> 156:95d6b41a828b 114 typedef enum
<> 156:95d6b41a828b 115 {
<> 156:95d6b41a828b 116 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
<> 156:95d6b41a828b 117 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
<> 156:95d6b41a828b 118 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
<> 156:95d6b41a828b 119 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
<> 156:95d6b41a828b 120 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
<> 156:95d6b41a828b 121
<> 156:95d6b41a828b 122 }HAL_DMA_CallbackIDTypeDef;
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /**
<> 144:ef7eb2e8f9f7 125 * @brief DMA handle Structure definition
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127 typedef struct __DMA_HandleTypeDef
<> 144:ef7eb2e8f9f7 128 {
<> 144:ef7eb2e8f9f7 129 DMA_Channel_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 DMA_InitTypeDef Init; /*!< DMA communication parameters */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 HAL_LockTypeDef Lock; /*!< DMA locking object */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 void *Parent; /*!< Parent object state */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
<> 144:ef7eb2e8f9f7 144
<> 156:95d6b41a828b 145 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 __IO uint32_t ErrorCode; /*!< DMA Error code */
<> 156:95d6b41a828b 148
<> 156:95d6b41a828b 149 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
<> 156:95d6b41a828b 150
<> 156:95d6b41a828b 151 uint32_t ChannelIndex; /*!< DMA Channel Index */
<> 144:ef7eb2e8f9f7 152 } DMA_HandleTypeDef;
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /**
<> 144:ef7eb2e8f9f7 155 * @}
<> 144:ef7eb2e8f9f7 156 */
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /** @defgroup DMA_Exported_Constants DMA Exported Constants
<> 144:ef7eb2e8f9f7 161 * @{
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /** @defgroup DMA_Error_Code DMA Error Code
<> 144:ef7eb2e8f9f7 165 * @{
<> 144:ef7eb2e8f9f7 166 */
<> 156:95d6b41a828b 167 #define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */
<> 156:95d6b41a828b 168 #define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */
<> 156:95d6b41a828b 169 #define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */
<> 156:95d6b41a828b 170 #define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
<> 156:95d6b41a828b 171 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */
<> 144:ef7eb2e8f9f7 172 /**
<> 144:ef7eb2e8f9f7 173 * @}
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
<> 144:ef7eb2e8f9f7 177 * @{
<> 144:ef7eb2e8f9f7 178 */
<> 156:95d6b41a828b 179 #define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */
<> 144:ef7eb2e8f9f7 180 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
<> 144:ef7eb2e8f9f7 181 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /**
<> 144:ef7eb2e8f9f7 184 * @}
<> 144:ef7eb2e8f9f7 185 */
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
<> 144:ef7eb2e8f9f7 188 * @{
<> 144:ef7eb2e8f9f7 189 */
<> 144:ef7eb2e8f9f7 190 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
<> 156:95d6b41a828b 191 #define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */
<> 144:ef7eb2e8f9f7 192 /**
<> 144:ef7eb2e8f9f7 193 * @}
<> 144:ef7eb2e8f9f7 194 */
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
<> 144:ef7eb2e8f9f7 197 * @{
<> 144:ef7eb2e8f9f7 198 */
<> 144:ef7eb2e8f9f7 199 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
<> 156:95d6b41a828b 200 #define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */
<> 144:ef7eb2e8f9f7 201 /**
<> 144:ef7eb2e8f9f7 202 * @}
<> 144:ef7eb2e8f9f7 203 */
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
<> 144:ef7eb2e8f9f7 206 * @{
<> 144:ef7eb2e8f9f7 207 */
<> 156:95d6b41a828b 208 #define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */
<> 144:ef7eb2e8f9f7 209 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
<> 144:ef7eb2e8f9f7 210 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
<> 144:ef7eb2e8f9f7 211 /**
<> 144:ef7eb2e8f9f7 212 * @}
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /** @defgroup DMA_Memory_data_size DMA Memory data size
<> 144:ef7eb2e8f9f7 216 * @{
<> 144:ef7eb2e8f9f7 217 */
<> 156:95d6b41a828b 218 #define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */
<> 144:ef7eb2e8f9f7 219 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
<> 144:ef7eb2e8f9f7 220 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
<> 144:ef7eb2e8f9f7 221 /**
<> 144:ef7eb2e8f9f7 222 * @}
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /** @defgroup DMA_mode DMA mode
<> 144:ef7eb2e8f9f7 226 * @{
<> 144:ef7eb2e8f9f7 227 */
<> 156:95d6b41a828b 228 #define DMA_NORMAL (0x00000000U) /*!< Normal Mode */
<> 144:ef7eb2e8f9f7 229 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
<> 144:ef7eb2e8f9f7 230 /**
<> 144:ef7eb2e8f9f7 231 * @}
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /** @defgroup DMA_Priority_level DMA Priority level
<> 144:ef7eb2e8f9f7 235 * @{
<> 144:ef7eb2e8f9f7 236 */
<> 156:95d6b41a828b 237 #define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */
<> 144:ef7eb2e8f9f7 238 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
<> 144:ef7eb2e8f9f7 239 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
<> 144:ef7eb2e8f9f7 240 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
<> 144:ef7eb2e8f9f7 241 /**
<> 144:ef7eb2e8f9f7 242 * @}
<> 144:ef7eb2e8f9f7 243 */
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
<> 144:ef7eb2e8f9f7 247 * @{
<> 144:ef7eb2e8f9f7 248 */
<> 144:ef7eb2e8f9f7 249 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
<> 144:ef7eb2e8f9f7 250 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
<> 144:ef7eb2e8f9f7 251 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
<> 144:ef7eb2e8f9f7 252 /**
<> 144:ef7eb2e8f9f7 253 * @}
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /** @defgroup DMA_flag_definitions DMA flag definitions
<> 144:ef7eb2e8f9f7 257 * @{
<> 144:ef7eb2e8f9f7 258 */
<> 144:ef7eb2e8f9f7 259
<> 156:95d6b41a828b 260 #define DMA_FLAG_GL1 (0x00000001U) /*!< Channel 1 global interrupt flag */
<> 156:95d6b41a828b 261 #define DMA_FLAG_TC1 (0x00000002U) /*!< Channel 1 transfer complete flag */
<> 156:95d6b41a828b 262 #define DMA_FLAG_HT1 (0x00000004U) /*!< Channel 1 half transfer flag */
<> 156:95d6b41a828b 263 #define DMA_FLAG_TE1 (0x00000008U) /*!< Channel 1 transfer error flag */
<> 156:95d6b41a828b 264 #define DMA_FLAG_GL2 (0x00000010U) /*!< Channel 2 global interrupt flag */
<> 156:95d6b41a828b 265 #define DMA_FLAG_TC2 (0x00000020U) /*!< Channel 2 transfer complete flag */
<> 156:95d6b41a828b 266 #define DMA_FLAG_HT2 (0x00000040U) /*!< Channel 2 half transfer flag */
<> 156:95d6b41a828b 267 #define DMA_FLAG_TE2 (0x00000080U) /*!< Channel 2 transfer error flag */
<> 156:95d6b41a828b 268 #define DMA_FLAG_GL3 (0x00000100U) /*!< Channel 3 global interrupt flag */
<> 156:95d6b41a828b 269 #define DMA_FLAG_TC3 (0x00000200U) /*!< Channel 3 transfer complete flag */
<> 156:95d6b41a828b 270 #define DMA_FLAG_HT3 (0x00000400U) /*!< Channel 3 half transfer flag */
<> 156:95d6b41a828b 271 #define DMA_FLAG_TE3 (0x00000800U) /*!< Channel 3 transfer error flag */
<> 156:95d6b41a828b 272 #define DMA_FLAG_GL4 (0x00001000U) /*!< Channel 4 global interrupt flag */
<> 156:95d6b41a828b 273 #define DMA_FLAG_TC4 (0x00002000U) /*!< Channel 4 transfer complete flag */
<> 156:95d6b41a828b 274 #define DMA_FLAG_HT4 (0x00004000U) /*!< Channel 4 half transfer flag */
<> 156:95d6b41a828b 275 #define DMA_FLAG_TE4 (0x00008000U) /*!< Channel 4 transfer error flag */
<> 156:95d6b41a828b 276 #define DMA_FLAG_GL5 (0x00010000U) /*!< Channel 5 global interrupt flag */
<> 156:95d6b41a828b 277 #define DMA_FLAG_TC5 (0x00020000U) /*!< Channel 5 transfer complete flag */
<> 156:95d6b41a828b 278 #define DMA_FLAG_HT5 (0x00040000U) /*!< Channel 5 half transfer flag */
<> 156:95d6b41a828b 279 #define DMA_FLAG_TE5 (0x00080000U) /*!< Channel 5 transfer error flag */
<> 156:95d6b41a828b 280 #define DMA_FLAG_GL6 (0x00100000U) /*!< Channel 6 global interrupt flag */
<> 156:95d6b41a828b 281 #define DMA_FLAG_TC6 (0x00200000U) /*!< Channel 6 transfer complete flag */
<> 156:95d6b41a828b 282 #define DMA_FLAG_HT6 (0x00400000U) /*!< Channel 6 half transfer flag */
<> 156:95d6b41a828b 283 #define DMA_FLAG_TE6 (0x00800000U) /*!< Channel 6 transfer error flag */
<> 156:95d6b41a828b 284 #define DMA_FLAG_GL7 (0x01000000U) /*!< Channel 7 global interrupt flag */
<> 156:95d6b41a828b 285 #define DMA_FLAG_TC7 (0x02000000U) /*!< Channel 7 transfer complete flag */
<> 156:95d6b41a828b 286 #define DMA_FLAG_HT7 (0x04000000U) /*!< Channel 7 half transfer flag */
<> 156:95d6b41a828b 287 #define DMA_FLAG_TE7 (0x08000000U) /*!< Channel 7 transfer error flag */
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /**
<> 144:ef7eb2e8f9f7 290 * @}
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 #if defined(SYSCFG_CFGR1_DMA_RMP)
<> 144:ef7eb2e8f9f7 294 /** @defgroup HAL_DMA_remapping HAL DMA remapping
<> 144:ef7eb2e8f9f7 295 * Elements values convention: 0xYYYYYYYY
<> 144:ef7eb2e8f9f7 296 * - YYYYYYYY : Position in the SYSCFG register CFGR1
<> 144:ef7eb2e8f9f7 297 * @{
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299 #define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap
<> 144:ef7eb2e8f9f7 300 0: No remap (ADC DMA requests mapped on DMA channel 1
<> 144:ef7eb2e8f9f7 301 1: Remap (ADC DMA requests mapped on DMA channel 2 */
<> 144:ef7eb2e8f9f7 302 #define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap
<> 144:ef7eb2e8f9f7 303 0: No remap (USART1_TX DMA request mapped on DMA channel 2
<> 144:ef7eb2e8f9f7 304 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */
<> 144:ef7eb2e8f9f7 305 #define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap
<> 144:ef7eb2e8f9f7 306 0: No remap (USART1_RX DMA request mapped on DMA channel 3
<> 144:ef7eb2e8f9f7 307 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */
<> 144:ef7eb2e8f9f7 308 #define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap
<> 144:ef7eb2e8f9f7 309 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3)
<> 144:ef7eb2e8f9f7 310 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */
<> 144:ef7eb2e8f9f7 311 #define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap
<> 144:ef7eb2e8f9f7 312 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
<> 144:ef7eb2e8f9f7 313 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */
<> 144:ef7eb2e8f9f7 314 #if defined (STM32F070xB)
<> 144:ef7eb2e8f9f7 315 #define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only.
<> 144:ef7eb2e8f9f7 316 0: Disabled, need to remap before use
<> 144:ef7eb2e8f9f7 317 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 #endif
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
<> 144:ef7eb2e8f9f7 322 #define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only
<> 144:ef7eb2e8f9f7 323 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit)
<> 144:ef7eb2e8f9f7 324 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */
<> 144:ef7eb2e8f9f7 325 #define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only
<> 144:ef7eb2e8f9f7 326 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit)
<> 144:ef7eb2e8f9f7 327 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */
<> 144:ef7eb2e8f9f7 328 #define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only.
<> 144:ef7eb2e8f9f7 329 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively)
<> 144:ef7eb2e8f9f7 330 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
<> 144:ef7eb2e8f9f7 331 #define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only.
<> 144:ef7eb2e8f9f7 332 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively)
<> 144:ef7eb2e8f9f7 333 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
<> 144:ef7eb2e8f9f7 334 #define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only.
<> 144:ef7eb2e8f9f7 335 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively)
<> 144:ef7eb2e8f9f7 336 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
<> 144:ef7eb2e8f9f7 337 #define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only.
<> 144:ef7eb2e8f9f7 338 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively)
<> 144:ef7eb2e8f9f7 339 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */
<> 144:ef7eb2e8f9f7 340 #define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only.
<> 144:ef7eb2e8f9f7 341 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively)
<> 144:ef7eb2e8f9f7 342 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */
<> 144:ef7eb2e8f9f7 343 #define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only.
<> 144:ef7eb2e8f9f7 344 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively)
<> 144:ef7eb2e8f9f7 345 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */
<> 144:ef7eb2e8f9f7 346 #define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only.
<> 144:ef7eb2e8f9f7 347 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4)
<> 144:ef7eb2e8f9f7 348 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */
<> 144:ef7eb2e8f9f7 349 #endif
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /**
<> 144:ef7eb2e8f9f7 352 * @}
<> 144:ef7eb2e8f9f7 353 */
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 #endif /* SYSCFG_CFGR1_DMA_RMP */
<> 144:ef7eb2e8f9f7 356 /**
<> 144:ef7eb2e8f9f7 357 * @}
<> 144:ef7eb2e8f9f7 358 */
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 361 /** @defgroup DMA_Exported_Macros DMA Exported Macros
<> 144:ef7eb2e8f9f7 362 * @{
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /** @brief Reset DMA handle state
Anna Bridge 180:96ed750bd169 366 * @param __HANDLE__ DMA handle.
<> 144:ef7eb2e8f9f7 367 * @retval None
<> 144:ef7eb2e8f9f7 368 */
<> 144:ef7eb2e8f9f7 369 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /**
<> 144:ef7eb2e8f9f7 372 * @brief Enable the specified DMA Channel.
Anna Bridge 180:96ed750bd169 373 * @param __HANDLE__ DMA handle
<> 144:ef7eb2e8f9f7 374 * @retval None
<> 144:ef7eb2e8f9f7 375 */
<> 156:95d6b41a828b 376 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /**
<> 144:ef7eb2e8f9f7 379 * @brief Disable the specified DMA Channel.
Anna Bridge 180:96ed750bd169 380 * @param __HANDLE__ DMA handle
<> 144:ef7eb2e8f9f7 381 * @retval None
<> 144:ef7eb2e8f9f7 382 */
<> 156:95d6b41a828b 383 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /* Interrupt & Flag management */
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /**
<> 144:ef7eb2e8f9f7 389 * @brief Enables the specified DMA Channel interrupts.
Anna Bridge 180:96ed750bd169 390 * @param __HANDLE__ DMA handle
Anna Bridge 180:96ed750bd169 391 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 392 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 393 * @arg DMA_IT_TC: Transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 394 * @arg DMA_IT_HT: Half transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 395 * @arg DMA_IT_TE: Transfer error interrupt mask
<> 144:ef7eb2e8f9f7 396 * @retval None
<> 144:ef7eb2e8f9f7 397 */
<> 156:95d6b41a828b 398 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /**
<> 144:ef7eb2e8f9f7 401 * @brief Disables the specified DMA Channel interrupts.
Anna Bridge 180:96ed750bd169 402 * @param __HANDLE__ DMA handle
Anna Bridge 180:96ed750bd169 403 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 404 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 405 * @arg DMA_IT_TC: Transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 406 * @arg DMA_IT_HT: Half transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 407 * @arg DMA_IT_TE: Transfer error interrupt mask
<> 144:ef7eb2e8f9f7 408 * @retval None
<> 144:ef7eb2e8f9f7 409 */
<> 156:95d6b41a828b 410 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /**
<> 144:ef7eb2e8f9f7 413 * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
Anna Bridge 180:96ed750bd169 414 * @param __HANDLE__ DMA handle
Anna Bridge 180:96ed750bd169 415 * @param __INTERRUPT__ specifies the DMA interrupt source to check.
<> 144:ef7eb2e8f9f7 416 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 417 * @arg DMA_IT_TC: Transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 418 * @arg DMA_IT_HT: Half transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 419 * @arg DMA_IT_TE: Transfer error interrupt mask
<> 144:ef7eb2e8f9f7 420 * @retval The state of DMA_IT (SET or RESET).
<> 144:ef7eb2e8f9f7 421 */
<> 156:95d6b41a828b 422 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /**
<> 144:ef7eb2e8f9f7 425 * @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
Anna Bridge 180:96ed750bd169 426 * @param __HANDLE__ DMA handle
<> 144:ef7eb2e8f9f7 427 *
<> 144:ef7eb2e8f9f7 428 * @retval The number of remaining data units in the current DMA Channel transfer.
<> 144:ef7eb2e8f9f7 429 */
<> 144:ef7eb2e8f9f7 430 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 #if defined(SYSCFG_CFGR1_DMA_RMP)
<> 144:ef7eb2e8f9f7 433 /** @brief DMA remapping enable/disable macros
Anna Bridge 180:96ed750bd169 434 * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_remapping
<> 144:ef7eb2e8f9f7 435 */
<> 144:ef7eb2e8f9f7 436 #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
<> 144:ef7eb2e8f9f7 437 SYSCFG->CFGR1 |= (__DMA_REMAP__); \
<> 144:ef7eb2e8f9f7 438 }while(0)
<> 144:ef7eb2e8f9f7 439 #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
<> 144:ef7eb2e8f9f7 440 SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
<> 144:ef7eb2e8f9f7 441 }while(0)
<> 144:ef7eb2e8f9f7 442 #endif /* SYSCFG_CFGR1_DMA_RMP */
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /**
<> 144:ef7eb2e8f9f7 445 * @}
<> 144:ef7eb2e8f9f7 446 */
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /* Include DMA HAL Extension module */
<> 144:ef7eb2e8f9f7 449 #include "stm32f0xx_hal_dma_ex.h"
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 452 /** @addtogroup DMA_Exported_Functions
<> 144:ef7eb2e8f9f7 453 * @{
<> 144:ef7eb2e8f9f7 454 */
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /** @addtogroup DMA_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 457 * @{
<> 144:ef7eb2e8f9f7 458 */
<> 144:ef7eb2e8f9f7 459 /* Initialization and de-initialization functions *****************************/
<> 144:ef7eb2e8f9f7 460 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 461 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 462 /**
<> 144:ef7eb2e8f9f7 463 * @}
<> 144:ef7eb2e8f9f7 464 */
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /** @addtogroup DMA_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 467 * @{
<> 144:ef7eb2e8f9f7 468 */
<> 144:ef7eb2e8f9f7 469 /* Input and Output operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 470 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 471 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 472 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 473 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 474 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 475 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 476 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
<> 156:95d6b41a828b 477 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
<> 156:95d6b41a828b 478
<> 144:ef7eb2e8f9f7 479 /**
<> 144:ef7eb2e8f9f7 480 * @}
<> 144:ef7eb2e8f9f7 481 */
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 /** @addtogroup DMA_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 484 * @{
<> 144:ef7eb2e8f9f7 485 */
<> 144:ef7eb2e8f9f7 486 /* Peripheral State and Error functions ***************************************/
<> 144:ef7eb2e8f9f7 487 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 488 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 489 /**
<> 144:ef7eb2e8f9f7 490 * @}
<> 144:ef7eb2e8f9f7 491 */
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /**
<> 144:ef7eb2e8f9f7 494 * @}
<> 144:ef7eb2e8f9f7 495 */
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /** @addtogroup DMA_Private_Macros
<> 144:ef7eb2e8f9f7 498 * @{
<> 144:ef7eb2e8f9f7 499 */
<> 144:ef7eb2e8f9f7 500 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
<> 144:ef7eb2e8f9f7 501 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
<> 144:ef7eb2e8f9f7 502 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
<> 144:ef7eb2e8f9f7 503 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
<> 144:ef7eb2e8f9f7 504 ((STATE) == DMA_PINC_DISABLE))
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
<> 144:ef7eb2e8f9f7 507 ((STATE) == DMA_MINC_DISABLE))
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
<> 144:ef7eb2e8f9f7 510 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
<> 144:ef7eb2e8f9f7 511 ((SIZE) == DMA_PDATAALIGN_WORD))
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
<> 144:ef7eb2e8f9f7 514 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
<> 144:ef7eb2e8f9f7 515 ((SIZE) == DMA_MDATAALIGN_WORD ))
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
<> 144:ef7eb2e8f9f7 518 ((MODE) == DMA_CIRCULAR))
<> 144:ef7eb2e8f9f7 519 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
<> 144:ef7eb2e8f9f7 520 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
<> 144:ef7eb2e8f9f7 521 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
<> 144:ef7eb2e8f9f7 522 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
<> 156:95d6b41a828b 523 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 #if defined(SYSCFG_CFGR1_DMA_RMP)
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
<> 144:ef7eb2e8f9f7 528 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
<> 144:ef7eb2e8f9f7 529 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
<> 144:ef7eb2e8f9f7 530 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
<> 144:ef7eb2e8f9f7 531 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
<> 144:ef7eb2e8f9f7 532 ((RMP) == DMA_REMAP_TIM17_DMA_CH2) || \
<> 144:ef7eb2e8f9f7 533 ((RMP) == DMA_REMAP_TIM16_DMA_CH6) || \
<> 144:ef7eb2e8f9f7 534 ((RMP) == DMA_REMAP_TIM17_DMA_CH7) || \
<> 144:ef7eb2e8f9f7 535 ((RMP) == DMA_REMAP_SPI2_DMA_CH67) || \
<> 144:ef7eb2e8f9f7 536 ((RMP) == DMA_REMAP_USART2_DMA_CH67) || \
<> 144:ef7eb2e8f9f7 537 ((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
<> 144:ef7eb2e8f9f7 538 ((RMP) == DMA_REMAP_I2C1_DMA_CH76) || \
<> 144:ef7eb2e8f9f7 539 ((RMP) == DMA_REMAP_TIM1_DMA_CH6) || \
<> 144:ef7eb2e8f9f7 540 ((RMP) == DMA_REMAP_TIM2_DMA_CH7) || \
<> 144:ef7eb2e8f9f7 541 ((RMP) == DMA_REMAP_TIM3_DMA_CH6))
<> 144:ef7eb2e8f9f7 542 #elif defined (STM32F070xB)
<> 144:ef7eb2e8f9f7 543 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
<> 144:ef7eb2e8f9f7 544 ((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
<> 144:ef7eb2e8f9f7 545 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
<> 144:ef7eb2e8f9f7 546 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
<> 144:ef7eb2e8f9f7 547 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
<> 144:ef7eb2e8f9f7 548 ((RMP) == DMA_REMAP_TIM17_DMA_CH2))
<> 144:ef7eb2e8f9f7 549 #else
<> 144:ef7eb2e8f9f7 550 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
<> 144:ef7eb2e8f9f7 551 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
<> 144:ef7eb2e8f9f7 552 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
<> 144:ef7eb2e8f9f7 553 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
<> 144:ef7eb2e8f9f7 554 ((RMP) == DMA_REMAP_TIM17_DMA_CH2))
<> 144:ef7eb2e8f9f7 555 #endif
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 #endif /* SYSCFG_CFGR1_DMA_RMP */
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /**
<> 144:ef7eb2e8f9f7 561 * @}
<> 144:ef7eb2e8f9f7 562 */
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 /**
<> 144:ef7eb2e8f9f7 565 * @}
<> 144:ef7eb2e8f9f7 566 */
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /**
<> 144:ef7eb2e8f9f7 569 * @}
<> 144:ef7eb2e8f9f7 570 */
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 573 }
<> 144:ef7eb2e8f9f7 574 #endif
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 #endif /* __STM32F0xx_HAL_DMA_H */
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 579