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mbed library sources. Supersedes mbed-src.

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targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_dma.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.4.0
<> 144:ef7eb2e8f9f7 6 * @date 27-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of DMA HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F0xx_HAL_DMA_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F0xx_HAL_DMA_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup DMA
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @defgroup DMA_Exported_Types DMA Exported Types
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @brief DMA Configuration Structure definition
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 typedef struct
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
<> 144:ef7eb2e8f9f7 69 from memory to memory or from peripheral to memory.
<> 144:ef7eb2e8f9f7 70 This parameter can be a value of @ref DMA_Data_transfer_direction */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
<> 144:ef7eb2e8f9f7 73 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
<> 144:ef7eb2e8f9f7 76 This parameter can be a value of @ref DMA_Memory_incremented_mode */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
<> 144:ef7eb2e8f9f7 79 This parameter can be a value of @ref DMA_Peripheral_data_size */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
<> 144:ef7eb2e8f9f7 82 This parameter can be a value of @ref DMA_Memory_data_size */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
<> 144:ef7eb2e8f9f7 85 This parameter can be a value of @ref DMA_mode
<> 144:ef7eb2e8f9f7 86 @note The circular buffer mode cannot be used if the memory-to-memory
<> 144:ef7eb2e8f9f7 87 data transfer is configured on the selected Channel */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
<> 144:ef7eb2e8f9f7 90 This parameter can be a value of @ref DMA_Priority_level */
<> 144:ef7eb2e8f9f7 91 } DMA_InitTypeDef;
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /**
<> 144:ef7eb2e8f9f7 94 * @brief DMA Configuration enumeration values definition
<> 144:ef7eb2e8f9f7 95 */
<> 144:ef7eb2e8f9f7 96 typedef enum
<> 144:ef7eb2e8f9f7 97 {
<> 144:ef7eb2e8f9f7 98 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
<> 144:ef7eb2e8f9f7 99 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 } DMA_ControlTypeDef;
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /**
<> 144:ef7eb2e8f9f7 104 * @brief HAL DMA State structures definition
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106 typedef enum
<> 144:ef7eb2e8f9f7 107 {
<> 144:ef7eb2e8f9f7 108 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
<> 144:ef7eb2e8f9f7 109 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
<> 144:ef7eb2e8f9f7 110 HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
<> 144:ef7eb2e8f9f7 111 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
<> 144:ef7eb2e8f9f7 112 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
<> 144:ef7eb2e8f9f7 113 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
<> 144:ef7eb2e8f9f7 114 }HAL_DMA_StateTypeDef;
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /**
<> 144:ef7eb2e8f9f7 117 * @brief HAL DMA Error Code structure definition
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 typedef enum
<> 144:ef7eb2e8f9f7 120 {
<> 144:ef7eb2e8f9f7 121 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
<> 144:ef7eb2e8f9f7 122 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
<> 144:ef7eb2e8f9f7 123 }HAL_DMA_LevelCompleteTypeDef;
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /**
<> 144:ef7eb2e8f9f7 126 * @brief DMA handle Structure definition
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128 typedef struct __DMA_HandleTypeDef
<> 144:ef7eb2e8f9f7 129 {
<> 144:ef7eb2e8f9f7 130 DMA_Channel_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 DMA_InitTypeDef Init; /*!< DMA communication parameters */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 HAL_LockTypeDef Lock; /*!< DMA locking object */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 void *Parent; /*!< Parent object state */
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 __IO uint32_t ErrorCode; /*!< DMA Error code */
<> 144:ef7eb2e8f9f7 149 } DMA_HandleTypeDef;
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /**
<> 144:ef7eb2e8f9f7 152 * @}
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /** @defgroup DMA_Exported_Constants DMA Exported Constants
<> 144:ef7eb2e8f9f7 158 * @{
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /** @defgroup DMA_Error_Code DMA Error Code
<> 144:ef7eb2e8f9f7 162 * @{
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
<> 144:ef7eb2e8f9f7 165 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
<> 144:ef7eb2e8f9f7 166 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004) /*!< no ongoin transfer */
<> 144:ef7eb2e8f9f7 167 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
<> 144:ef7eb2e8f9f7 168 /**
<> 144:ef7eb2e8f9f7 169 * @}
<> 144:ef7eb2e8f9f7 170 */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
<> 144:ef7eb2e8f9f7 173 * @{
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
<> 144:ef7eb2e8f9f7 176 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
<> 144:ef7eb2e8f9f7 177 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /**
<> 144:ef7eb2e8f9f7 180 * @}
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
<> 144:ef7eb2e8f9f7 184 * @{
<> 144:ef7eb2e8f9f7 185 */
<> 144:ef7eb2e8f9f7 186 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
<> 144:ef7eb2e8f9f7 187 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
<> 144:ef7eb2e8f9f7 188 /**
<> 144:ef7eb2e8f9f7 189 * @}
<> 144:ef7eb2e8f9f7 190 */
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
<> 144:ef7eb2e8f9f7 193 * @{
<> 144:ef7eb2e8f9f7 194 */
<> 144:ef7eb2e8f9f7 195 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
<> 144:ef7eb2e8f9f7 196 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
<> 144:ef7eb2e8f9f7 197 /**
<> 144:ef7eb2e8f9f7 198 * @}
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
<> 144:ef7eb2e8f9f7 202 * @{
<> 144:ef7eb2e8f9f7 203 */
<> 144:ef7eb2e8f9f7 204 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
<> 144:ef7eb2e8f9f7 205 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
<> 144:ef7eb2e8f9f7 206 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
<> 144:ef7eb2e8f9f7 207 /**
<> 144:ef7eb2e8f9f7 208 * @}
<> 144:ef7eb2e8f9f7 209 */
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /** @defgroup DMA_Memory_data_size DMA Memory data size
<> 144:ef7eb2e8f9f7 212 * @{
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
<> 144:ef7eb2e8f9f7 215 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
<> 144:ef7eb2e8f9f7 216 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
<> 144:ef7eb2e8f9f7 217 /**
<> 144:ef7eb2e8f9f7 218 * @}
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /** @defgroup DMA_mode DMA mode
<> 144:ef7eb2e8f9f7 222 * @{
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
<> 144:ef7eb2e8f9f7 225 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
<> 144:ef7eb2e8f9f7 226 /**
<> 144:ef7eb2e8f9f7 227 * @}
<> 144:ef7eb2e8f9f7 228 */
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /** @defgroup DMA_Priority_level DMA Priority level
<> 144:ef7eb2e8f9f7 231 * @{
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
<> 144:ef7eb2e8f9f7 234 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
<> 144:ef7eb2e8f9f7 235 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
<> 144:ef7eb2e8f9f7 236 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
<> 144:ef7eb2e8f9f7 237 /**
<> 144:ef7eb2e8f9f7 238 * @}
<> 144:ef7eb2e8f9f7 239 */
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
<> 144:ef7eb2e8f9f7 243 * @{
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
<> 144:ef7eb2e8f9f7 246 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
<> 144:ef7eb2e8f9f7 247 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
<> 144:ef7eb2e8f9f7 248 /**
<> 144:ef7eb2e8f9f7 249 * @}
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /** @defgroup DMA_flag_definitions DMA flag definitions
<> 144:ef7eb2e8f9f7 253 * @{
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 #define DMA_FLAG_GL1 ((uint32_t)0x00000001) /*!< Channel 1 global interrupt flag */
<> 144:ef7eb2e8f9f7 257 #define DMA_FLAG_TC1 ((uint32_t)0x00000002) /*!< Channel 1 transfer complete flag */
<> 144:ef7eb2e8f9f7 258 #define DMA_FLAG_HT1 ((uint32_t)0x00000004) /*!< Channel 1 half transfer flag */
<> 144:ef7eb2e8f9f7 259 #define DMA_FLAG_TE1 ((uint32_t)0x00000008) /*!< Channel 1 transfer error flag */
<> 144:ef7eb2e8f9f7 260 #define DMA_FLAG_GL2 ((uint32_t)0x00000010) /*!< Channel 2 global interrupt flag */
<> 144:ef7eb2e8f9f7 261 #define DMA_FLAG_TC2 ((uint32_t)0x00000020) /*!< Channel 2 transfer complete flag */
<> 144:ef7eb2e8f9f7 262 #define DMA_FLAG_HT2 ((uint32_t)0x00000040) /*!< Channel 2 half transfer flag */
<> 144:ef7eb2e8f9f7 263 #define DMA_FLAG_TE2 ((uint32_t)0x00000080) /*!< Channel 2 transfer error flag */
<> 144:ef7eb2e8f9f7 264 #define DMA_FLAG_GL3 ((uint32_t)0x00000100) /*!< Channel 3 global interrupt flag */
<> 144:ef7eb2e8f9f7 265 #define DMA_FLAG_TC3 ((uint32_t)0x00000200) /*!< Channel 3 transfer complete flag */
<> 144:ef7eb2e8f9f7 266 #define DMA_FLAG_HT3 ((uint32_t)0x00000400) /*!< Channel 3 half transfer flag */
<> 144:ef7eb2e8f9f7 267 #define DMA_FLAG_TE3 ((uint32_t)0x00000800) /*!< Channel 3 transfer error flag */
<> 144:ef7eb2e8f9f7 268 #define DMA_FLAG_GL4 ((uint32_t)0x00001000) /*!< Channel 4 global interrupt flag */
<> 144:ef7eb2e8f9f7 269 #define DMA_FLAG_TC4 ((uint32_t)0x00002000) /*!< Channel 4 transfer complete flag */
<> 144:ef7eb2e8f9f7 270 #define DMA_FLAG_HT4 ((uint32_t)0x00004000) /*!< Channel 4 half transfer flag */
<> 144:ef7eb2e8f9f7 271 #define DMA_FLAG_TE4 ((uint32_t)0x00008000) /*!< Channel 4 transfer error flag */
<> 144:ef7eb2e8f9f7 272 #define DMA_FLAG_GL5 ((uint32_t)0x00010000) /*!< Channel 5 global interrupt flag */
<> 144:ef7eb2e8f9f7 273 #define DMA_FLAG_TC5 ((uint32_t)0x00020000) /*!< Channel 5 transfer complete flag */
<> 144:ef7eb2e8f9f7 274 #define DMA_FLAG_HT5 ((uint32_t)0x00040000) /*!< Channel 5 half transfer flag */
<> 144:ef7eb2e8f9f7 275 #define DMA_FLAG_TE5 ((uint32_t)0x00080000) /*!< Channel 5 transfer error flag */
<> 144:ef7eb2e8f9f7 276 #define DMA_FLAG_GL6 ((uint32_t)0x00100000) /*!< Channel 6 global interrupt flag */
<> 144:ef7eb2e8f9f7 277 #define DMA_FLAG_TC6 ((uint32_t)0x00200000) /*!< Channel 6 transfer complete flag */
<> 144:ef7eb2e8f9f7 278 #define DMA_FLAG_HT6 ((uint32_t)0x00400000) /*!< Channel 6 half transfer flag */
<> 144:ef7eb2e8f9f7 279 #define DMA_FLAG_TE6 ((uint32_t)0x00800000) /*!< Channel 6 transfer error flag */
<> 144:ef7eb2e8f9f7 280 #define DMA_FLAG_GL7 ((uint32_t)0x01000000) /*!< Channel 7 global interrupt flag */
<> 144:ef7eb2e8f9f7 281 #define DMA_FLAG_TC7 ((uint32_t)0x02000000) /*!< Channel 7 transfer complete flag */
<> 144:ef7eb2e8f9f7 282 #define DMA_FLAG_HT7 ((uint32_t)0x04000000) /*!< Channel 7 half transfer flag */
<> 144:ef7eb2e8f9f7 283 #define DMA_FLAG_TE7 ((uint32_t)0x08000000) /*!< Channel 7 transfer error flag */
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /**
<> 144:ef7eb2e8f9f7 286 * @}
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 #if defined(SYSCFG_CFGR1_DMA_RMP)
<> 144:ef7eb2e8f9f7 290 /** @defgroup HAL_DMA_remapping HAL DMA remapping
<> 144:ef7eb2e8f9f7 291 * Elements values convention: 0xYYYYYYYY
<> 144:ef7eb2e8f9f7 292 * - YYYYYYYY : Position in the SYSCFG register CFGR1
<> 144:ef7eb2e8f9f7 293 * @{
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295 #define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap
<> 144:ef7eb2e8f9f7 296 0: No remap (ADC DMA requests mapped on DMA channel 1
<> 144:ef7eb2e8f9f7 297 1: Remap (ADC DMA requests mapped on DMA channel 2 */
<> 144:ef7eb2e8f9f7 298 #define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap
<> 144:ef7eb2e8f9f7 299 0: No remap (USART1_TX DMA request mapped on DMA channel 2
<> 144:ef7eb2e8f9f7 300 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */
<> 144:ef7eb2e8f9f7 301 #define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap
<> 144:ef7eb2e8f9f7 302 0: No remap (USART1_RX DMA request mapped on DMA channel 3
<> 144:ef7eb2e8f9f7 303 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */
<> 144:ef7eb2e8f9f7 304 #define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap
<> 144:ef7eb2e8f9f7 305 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3)
<> 144:ef7eb2e8f9f7 306 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */
<> 144:ef7eb2e8f9f7 307 #define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap
<> 144:ef7eb2e8f9f7 308 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
<> 144:ef7eb2e8f9f7 309 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */
<> 144:ef7eb2e8f9f7 310 #if defined (STM32F070xB)
<> 144:ef7eb2e8f9f7 311 #define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only.
<> 144:ef7eb2e8f9f7 312 0: Disabled, need to remap before use
<> 144:ef7eb2e8f9f7 313 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 #endif
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
<> 144:ef7eb2e8f9f7 318 #define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only
<> 144:ef7eb2e8f9f7 319 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit)
<> 144:ef7eb2e8f9f7 320 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */
<> 144:ef7eb2e8f9f7 321 #define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only
<> 144:ef7eb2e8f9f7 322 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit)
<> 144:ef7eb2e8f9f7 323 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */
<> 144:ef7eb2e8f9f7 324 #define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only.
<> 144:ef7eb2e8f9f7 325 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively)
<> 144:ef7eb2e8f9f7 326 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
<> 144:ef7eb2e8f9f7 327 #define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only.
<> 144:ef7eb2e8f9f7 328 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively)
<> 144:ef7eb2e8f9f7 329 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
<> 144:ef7eb2e8f9f7 330 #define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only.
<> 144:ef7eb2e8f9f7 331 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively)
<> 144:ef7eb2e8f9f7 332 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
<> 144:ef7eb2e8f9f7 333 #define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only.
<> 144:ef7eb2e8f9f7 334 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively)
<> 144:ef7eb2e8f9f7 335 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */
<> 144:ef7eb2e8f9f7 336 #define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only.
<> 144:ef7eb2e8f9f7 337 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively)
<> 144:ef7eb2e8f9f7 338 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */
<> 144:ef7eb2e8f9f7 339 #define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only.
<> 144:ef7eb2e8f9f7 340 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively)
<> 144:ef7eb2e8f9f7 341 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */
<> 144:ef7eb2e8f9f7 342 #define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only.
<> 144:ef7eb2e8f9f7 343 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4)
<> 144:ef7eb2e8f9f7 344 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */
<> 144:ef7eb2e8f9f7 345 #endif
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /**
<> 144:ef7eb2e8f9f7 348 * @}
<> 144:ef7eb2e8f9f7 349 */
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 #endif /* SYSCFG_CFGR1_DMA_RMP */
<> 144:ef7eb2e8f9f7 352 /**
<> 144:ef7eb2e8f9f7 353 * @}
<> 144:ef7eb2e8f9f7 354 */
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 357 /** @defgroup DMA_Exported_Macros DMA Exported Macros
<> 144:ef7eb2e8f9f7 358 * @{
<> 144:ef7eb2e8f9f7 359 */
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /** @brief Reset DMA handle state
<> 144:ef7eb2e8f9f7 362 * @param __HANDLE__: DMA handle.
<> 144:ef7eb2e8f9f7 363 * @retval None
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /**
<> 144:ef7eb2e8f9f7 368 * @brief Enable the specified DMA Channel.
<> 144:ef7eb2e8f9f7 369 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 370 * @retval None
<> 144:ef7eb2e8f9f7 371 */
<> 144:ef7eb2e8f9f7 372 #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /**
<> 144:ef7eb2e8f9f7 375 * @brief Disable the specified DMA Channel.
<> 144:ef7eb2e8f9f7 376 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 377 * @retval None
<> 144:ef7eb2e8f9f7 378 */
<> 144:ef7eb2e8f9f7 379 #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /* Interrupt & Flag management */
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /**
<> 144:ef7eb2e8f9f7 385 * @brief Enables the specified DMA Channel interrupts.
<> 144:ef7eb2e8f9f7 386 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 387 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 388 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 389 * @arg DMA_IT_TC: Transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 390 * @arg DMA_IT_HT: Half transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 391 * @arg DMA_IT_TE: Transfer error interrupt mask
<> 144:ef7eb2e8f9f7 392 * @retval None
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /**
<> 144:ef7eb2e8f9f7 397 * @brief Disables the specified DMA Channel interrupts.
<> 144:ef7eb2e8f9f7 398 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 399 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 400 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 401 * @arg DMA_IT_TC: Transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 402 * @arg DMA_IT_HT: Half transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 403 * @arg DMA_IT_TE: Transfer error interrupt mask
<> 144:ef7eb2e8f9f7 404 * @retval None
<> 144:ef7eb2e8f9f7 405 */
<> 144:ef7eb2e8f9f7 406 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /**
<> 144:ef7eb2e8f9f7 409 * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
<> 144:ef7eb2e8f9f7 410 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 411 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
<> 144:ef7eb2e8f9f7 412 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 413 * @arg DMA_IT_TC: Transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 414 * @arg DMA_IT_HT: Half transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 415 * @arg DMA_IT_TE: Transfer error interrupt mask
<> 144:ef7eb2e8f9f7 416 * @retval The state of DMA_IT (SET or RESET).
<> 144:ef7eb2e8f9f7 417 */
<> 144:ef7eb2e8f9f7 418 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /**
<> 144:ef7eb2e8f9f7 421 * @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
<> 144:ef7eb2e8f9f7 422 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 423 *
<> 144:ef7eb2e8f9f7 424 * @retval The number of remaining data units in the current DMA Channel transfer.
<> 144:ef7eb2e8f9f7 425 */
<> 144:ef7eb2e8f9f7 426 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 #if defined(SYSCFG_CFGR1_DMA_RMP)
<> 144:ef7eb2e8f9f7 429 /** @brief DMA remapping enable/disable macros
<> 144:ef7eb2e8f9f7 430 * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432 #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
<> 144:ef7eb2e8f9f7 433 SYSCFG->CFGR1 |= (__DMA_REMAP__); \
<> 144:ef7eb2e8f9f7 434 }while(0)
<> 144:ef7eb2e8f9f7 435 #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
<> 144:ef7eb2e8f9f7 436 SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
<> 144:ef7eb2e8f9f7 437 }while(0)
<> 144:ef7eb2e8f9f7 438 #endif /* SYSCFG_CFGR1_DMA_RMP */
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 /**
<> 144:ef7eb2e8f9f7 441 * @}
<> 144:ef7eb2e8f9f7 442 */
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /* Include DMA HAL Extension module */
<> 144:ef7eb2e8f9f7 445 #include "stm32f0xx_hal_dma_ex.h"
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 448 /** @addtogroup DMA_Exported_Functions
<> 144:ef7eb2e8f9f7 449 * @{
<> 144:ef7eb2e8f9f7 450 */
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /** @addtogroup DMA_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 453 * @{
<> 144:ef7eb2e8f9f7 454 */
<> 144:ef7eb2e8f9f7 455 /* Initialization and de-initialization functions *****************************/
<> 144:ef7eb2e8f9f7 456 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 457 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 458 /**
<> 144:ef7eb2e8f9f7 459 * @}
<> 144:ef7eb2e8f9f7 460 */
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /** @addtogroup DMA_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 463 * @{
<> 144:ef7eb2e8f9f7 464 */
<> 144:ef7eb2e8f9f7 465 /* Input and Output operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 466 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 467 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 468 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 469 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 470 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 471 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 472 /**
<> 144:ef7eb2e8f9f7 473 * @}
<> 144:ef7eb2e8f9f7 474 */
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /** @addtogroup DMA_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 477 * @{
<> 144:ef7eb2e8f9f7 478 */
<> 144:ef7eb2e8f9f7 479 /* Peripheral State and Error functions ***************************************/
<> 144:ef7eb2e8f9f7 480 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 481 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 482 /**
<> 144:ef7eb2e8f9f7 483 * @}
<> 144:ef7eb2e8f9f7 484 */
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 /**
<> 144:ef7eb2e8f9f7 487 * @}
<> 144:ef7eb2e8f9f7 488 */
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 /** @addtogroup DMA_Private_Macros
<> 144:ef7eb2e8f9f7 491 * @{
<> 144:ef7eb2e8f9f7 492 */
<> 144:ef7eb2e8f9f7 493 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
<> 144:ef7eb2e8f9f7 494 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
<> 144:ef7eb2e8f9f7 495 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
<> 144:ef7eb2e8f9f7 496 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
<> 144:ef7eb2e8f9f7 497 ((STATE) == DMA_PINC_DISABLE))
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
<> 144:ef7eb2e8f9f7 500 ((STATE) == DMA_MINC_DISABLE))
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
<> 144:ef7eb2e8f9f7 503 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
<> 144:ef7eb2e8f9f7 504 ((SIZE) == DMA_PDATAALIGN_WORD))
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
<> 144:ef7eb2e8f9f7 507 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
<> 144:ef7eb2e8f9f7 508 ((SIZE) == DMA_MDATAALIGN_WORD ))
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
<> 144:ef7eb2e8f9f7 511 ((MODE) == DMA_CIRCULAR))
<> 144:ef7eb2e8f9f7 512 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
<> 144:ef7eb2e8f9f7 513 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
<> 144:ef7eb2e8f9f7 514 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
<> 144:ef7eb2e8f9f7 515 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
<> 144:ef7eb2e8f9f7 516 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 #if defined(SYSCFG_CFGR1_DMA_RMP)
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
<> 144:ef7eb2e8f9f7 521 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
<> 144:ef7eb2e8f9f7 522 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
<> 144:ef7eb2e8f9f7 523 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
<> 144:ef7eb2e8f9f7 524 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
<> 144:ef7eb2e8f9f7 525 ((RMP) == DMA_REMAP_TIM17_DMA_CH2) || \
<> 144:ef7eb2e8f9f7 526 ((RMP) == DMA_REMAP_TIM16_DMA_CH6) || \
<> 144:ef7eb2e8f9f7 527 ((RMP) == DMA_REMAP_TIM17_DMA_CH7) || \
<> 144:ef7eb2e8f9f7 528 ((RMP) == DMA_REMAP_SPI2_DMA_CH67) || \
<> 144:ef7eb2e8f9f7 529 ((RMP) == DMA_REMAP_USART2_DMA_CH67) || \
<> 144:ef7eb2e8f9f7 530 ((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
<> 144:ef7eb2e8f9f7 531 ((RMP) == DMA_REMAP_I2C1_DMA_CH76) || \
<> 144:ef7eb2e8f9f7 532 ((RMP) == DMA_REMAP_TIM1_DMA_CH6) || \
<> 144:ef7eb2e8f9f7 533 ((RMP) == DMA_REMAP_TIM2_DMA_CH7) || \
<> 144:ef7eb2e8f9f7 534 ((RMP) == DMA_REMAP_TIM3_DMA_CH6))
<> 144:ef7eb2e8f9f7 535 #elif defined (STM32F070xB)
<> 144:ef7eb2e8f9f7 536 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
<> 144:ef7eb2e8f9f7 537 ((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
<> 144:ef7eb2e8f9f7 538 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
<> 144:ef7eb2e8f9f7 539 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
<> 144:ef7eb2e8f9f7 540 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
<> 144:ef7eb2e8f9f7 541 ((RMP) == DMA_REMAP_TIM17_DMA_CH2))
<> 144:ef7eb2e8f9f7 542 #else
<> 144:ef7eb2e8f9f7 543 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
<> 144:ef7eb2e8f9f7 544 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
<> 144:ef7eb2e8f9f7 545 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
<> 144:ef7eb2e8f9f7 546 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
<> 144:ef7eb2e8f9f7 547 ((RMP) == DMA_REMAP_TIM17_DMA_CH2))
<> 144:ef7eb2e8f9f7 548 #endif
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 #endif /* SYSCFG_CFGR1_DMA_RMP */
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /**
<> 144:ef7eb2e8f9f7 554 * @}
<> 144:ef7eb2e8f9f7 555 */
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /**
<> 144:ef7eb2e8f9f7 558 * @}
<> 144:ef7eb2e8f9f7 559 */
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /**
<> 144:ef7eb2e8f9f7 562 * @}
<> 144:ef7eb2e8f9f7 563 */
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 566 }
<> 144:ef7eb2e8f9f7 567 #endif
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 #endif /* __STM32F0xx_HAL_DMA_H */
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 572