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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.h@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 15:03:32 2017 +0000
Revision:
156:95d6b41a828b
Parent:
149:156823d33999
Child:
180:96ed750bd169
This updates the lib to the mbed lib v134

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_dma.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.5.0
<> 156:95d6b41a828b 6 * @date 04-November-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of DMA HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F0xx_HAL_DMA_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F0xx_HAL_DMA_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup DMA
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @defgroup DMA_Exported_Types DMA Exported Types
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @brief DMA Configuration Structure definition
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 typedef struct
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
<> 144:ef7eb2e8f9f7 69 from memory to memory or from peripheral to memory.
<> 144:ef7eb2e8f9f7 70 This parameter can be a value of @ref DMA_Data_transfer_direction */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
<> 144:ef7eb2e8f9f7 73 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
<> 144:ef7eb2e8f9f7 76 This parameter can be a value of @ref DMA_Memory_incremented_mode */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
<> 144:ef7eb2e8f9f7 79 This parameter can be a value of @ref DMA_Peripheral_data_size */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
<> 144:ef7eb2e8f9f7 82 This parameter can be a value of @ref DMA_Memory_data_size */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
<> 144:ef7eb2e8f9f7 85 This parameter can be a value of @ref DMA_mode
<> 144:ef7eb2e8f9f7 86 @note The circular buffer mode cannot be used if the memory-to-memory
<> 144:ef7eb2e8f9f7 87 data transfer is configured on the selected Channel */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
<> 144:ef7eb2e8f9f7 90 This parameter can be a value of @ref DMA_Priority_level */
<> 144:ef7eb2e8f9f7 91 } DMA_InitTypeDef;
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /**
<> 144:ef7eb2e8f9f7 94 * @brief HAL DMA State structures definition
<> 144:ef7eb2e8f9f7 95 */
<> 144:ef7eb2e8f9f7 96 typedef enum
<> 144:ef7eb2e8f9f7 97 {
<> 156:95d6b41a828b 98 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
<> 156:95d6b41a828b 99 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
<> 156:95d6b41a828b 100 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
<> 156:95d6b41a828b 101 HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */
<> 144:ef7eb2e8f9f7 102 }HAL_DMA_StateTypeDef;
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 /**
<> 144:ef7eb2e8f9f7 105 * @brief HAL DMA Error Code structure definition
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107 typedef enum
<> 144:ef7eb2e8f9f7 108 {
<> 156:95d6b41a828b 109 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
<> 156:95d6b41a828b 110 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
<> 156:95d6b41a828b 111 }HAL_DMA_LevelCompleteTypeDef;
<> 156:95d6b41a828b 112
<> 156:95d6b41a828b 113 /**
<> 156:95d6b41a828b 114 * @brief HAL DMA Callback ID structure definition
<> 156:95d6b41a828b 115 */
<> 156:95d6b41a828b 116 typedef enum
<> 156:95d6b41a828b 117 {
<> 156:95d6b41a828b 118 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
<> 156:95d6b41a828b 119 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
<> 156:95d6b41a828b 120 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
<> 156:95d6b41a828b 121 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
<> 156:95d6b41a828b 122 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
<> 156:95d6b41a828b 123
<> 156:95d6b41a828b 124 }HAL_DMA_CallbackIDTypeDef;
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /**
<> 144:ef7eb2e8f9f7 127 * @brief DMA handle Structure definition
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129 typedef struct __DMA_HandleTypeDef
<> 144:ef7eb2e8f9f7 130 {
<> 144:ef7eb2e8f9f7 131 DMA_Channel_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 DMA_InitTypeDef Init; /*!< DMA communication parameters */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 HAL_LockTypeDef Lock; /*!< DMA locking object */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 void *Parent; /*!< Parent object state */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
<> 144:ef7eb2e8f9f7 146
<> 156:95d6b41a828b 147 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 __IO uint32_t ErrorCode; /*!< DMA Error code */
<> 156:95d6b41a828b 150
<> 156:95d6b41a828b 151 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
<> 156:95d6b41a828b 152
<> 156:95d6b41a828b 153 uint32_t ChannelIndex; /*!< DMA Channel Index */
<> 144:ef7eb2e8f9f7 154 } DMA_HandleTypeDef;
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /**
<> 144:ef7eb2e8f9f7 157 * @}
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /** @defgroup DMA_Exported_Constants DMA Exported Constants
<> 144:ef7eb2e8f9f7 163 * @{
<> 144:ef7eb2e8f9f7 164 */
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /** @defgroup DMA_Error_Code DMA Error Code
<> 144:ef7eb2e8f9f7 167 * @{
<> 144:ef7eb2e8f9f7 168 */
<> 156:95d6b41a828b 169 #define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */
<> 156:95d6b41a828b 170 #define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */
<> 156:95d6b41a828b 171 #define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */
<> 156:95d6b41a828b 172 #define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
<> 156:95d6b41a828b 173 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */
<> 144:ef7eb2e8f9f7 174 /**
<> 144:ef7eb2e8f9f7 175 * @}
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
<> 144:ef7eb2e8f9f7 179 * @{
<> 144:ef7eb2e8f9f7 180 */
<> 156:95d6b41a828b 181 #define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */
<> 144:ef7eb2e8f9f7 182 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
<> 144:ef7eb2e8f9f7 183 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /**
<> 144:ef7eb2e8f9f7 186 * @}
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
<> 144:ef7eb2e8f9f7 190 * @{
<> 144:ef7eb2e8f9f7 191 */
<> 144:ef7eb2e8f9f7 192 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
<> 156:95d6b41a828b 193 #define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */
<> 144:ef7eb2e8f9f7 194 /**
<> 144:ef7eb2e8f9f7 195 * @}
<> 144:ef7eb2e8f9f7 196 */
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
<> 144:ef7eb2e8f9f7 199 * @{
<> 144:ef7eb2e8f9f7 200 */
<> 144:ef7eb2e8f9f7 201 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
<> 156:95d6b41a828b 202 #define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */
<> 144:ef7eb2e8f9f7 203 /**
<> 144:ef7eb2e8f9f7 204 * @}
<> 144:ef7eb2e8f9f7 205 */
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
<> 144:ef7eb2e8f9f7 208 * @{
<> 144:ef7eb2e8f9f7 209 */
<> 156:95d6b41a828b 210 #define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */
<> 144:ef7eb2e8f9f7 211 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
<> 144:ef7eb2e8f9f7 212 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
<> 144:ef7eb2e8f9f7 213 /**
<> 144:ef7eb2e8f9f7 214 * @}
<> 144:ef7eb2e8f9f7 215 */
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /** @defgroup DMA_Memory_data_size DMA Memory data size
<> 144:ef7eb2e8f9f7 218 * @{
<> 144:ef7eb2e8f9f7 219 */
<> 156:95d6b41a828b 220 #define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */
<> 144:ef7eb2e8f9f7 221 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
<> 144:ef7eb2e8f9f7 222 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @}
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /** @defgroup DMA_mode DMA mode
<> 144:ef7eb2e8f9f7 228 * @{
<> 144:ef7eb2e8f9f7 229 */
<> 156:95d6b41a828b 230 #define DMA_NORMAL (0x00000000U) /*!< Normal Mode */
<> 144:ef7eb2e8f9f7 231 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
<> 144:ef7eb2e8f9f7 232 /**
<> 144:ef7eb2e8f9f7 233 * @}
<> 144:ef7eb2e8f9f7 234 */
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /** @defgroup DMA_Priority_level DMA Priority level
<> 144:ef7eb2e8f9f7 237 * @{
<> 144:ef7eb2e8f9f7 238 */
<> 156:95d6b41a828b 239 #define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */
<> 144:ef7eb2e8f9f7 240 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
<> 144:ef7eb2e8f9f7 241 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
<> 144:ef7eb2e8f9f7 242 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
<> 144:ef7eb2e8f9f7 243 /**
<> 144:ef7eb2e8f9f7 244 * @}
<> 144:ef7eb2e8f9f7 245 */
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
<> 144:ef7eb2e8f9f7 249 * @{
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
<> 144:ef7eb2e8f9f7 252 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
<> 144:ef7eb2e8f9f7 253 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
<> 144:ef7eb2e8f9f7 254 /**
<> 144:ef7eb2e8f9f7 255 * @}
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /** @defgroup DMA_flag_definitions DMA flag definitions
<> 144:ef7eb2e8f9f7 259 * @{
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261
<> 156:95d6b41a828b 262 #define DMA_FLAG_GL1 (0x00000001U) /*!< Channel 1 global interrupt flag */
<> 156:95d6b41a828b 263 #define DMA_FLAG_TC1 (0x00000002U) /*!< Channel 1 transfer complete flag */
<> 156:95d6b41a828b 264 #define DMA_FLAG_HT1 (0x00000004U) /*!< Channel 1 half transfer flag */
<> 156:95d6b41a828b 265 #define DMA_FLAG_TE1 (0x00000008U) /*!< Channel 1 transfer error flag */
<> 156:95d6b41a828b 266 #define DMA_FLAG_GL2 (0x00000010U) /*!< Channel 2 global interrupt flag */
<> 156:95d6b41a828b 267 #define DMA_FLAG_TC2 (0x00000020U) /*!< Channel 2 transfer complete flag */
<> 156:95d6b41a828b 268 #define DMA_FLAG_HT2 (0x00000040U) /*!< Channel 2 half transfer flag */
<> 156:95d6b41a828b 269 #define DMA_FLAG_TE2 (0x00000080U) /*!< Channel 2 transfer error flag */
<> 156:95d6b41a828b 270 #define DMA_FLAG_GL3 (0x00000100U) /*!< Channel 3 global interrupt flag */
<> 156:95d6b41a828b 271 #define DMA_FLAG_TC3 (0x00000200U) /*!< Channel 3 transfer complete flag */
<> 156:95d6b41a828b 272 #define DMA_FLAG_HT3 (0x00000400U) /*!< Channel 3 half transfer flag */
<> 156:95d6b41a828b 273 #define DMA_FLAG_TE3 (0x00000800U) /*!< Channel 3 transfer error flag */
<> 156:95d6b41a828b 274 #define DMA_FLAG_GL4 (0x00001000U) /*!< Channel 4 global interrupt flag */
<> 156:95d6b41a828b 275 #define DMA_FLAG_TC4 (0x00002000U) /*!< Channel 4 transfer complete flag */
<> 156:95d6b41a828b 276 #define DMA_FLAG_HT4 (0x00004000U) /*!< Channel 4 half transfer flag */
<> 156:95d6b41a828b 277 #define DMA_FLAG_TE4 (0x00008000U) /*!< Channel 4 transfer error flag */
<> 156:95d6b41a828b 278 #define DMA_FLAG_GL5 (0x00010000U) /*!< Channel 5 global interrupt flag */
<> 156:95d6b41a828b 279 #define DMA_FLAG_TC5 (0x00020000U) /*!< Channel 5 transfer complete flag */
<> 156:95d6b41a828b 280 #define DMA_FLAG_HT5 (0x00040000U) /*!< Channel 5 half transfer flag */
<> 156:95d6b41a828b 281 #define DMA_FLAG_TE5 (0x00080000U) /*!< Channel 5 transfer error flag */
<> 156:95d6b41a828b 282 #define DMA_FLAG_GL6 (0x00100000U) /*!< Channel 6 global interrupt flag */
<> 156:95d6b41a828b 283 #define DMA_FLAG_TC6 (0x00200000U) /*!< Channel 6 transfer complete flag */
<> 156:95d6b41a828b 284 #define DMA_FLAG_HT6 (0x00400000U) /*!< Channel 6 half transfer flag */
<> 156:95d6b41a828b 285 #define DMA_FLAG_TE6 (0x00800000U) /*!< Channel 6 transfer error flag */
<> 156:95d6b41a828b 286 #define DMA_FLAG_GL7 (0x01000000U) /*!< Channel 7 global interrupt flag */
<> 156:95d6b41a828b 287 #define DMA_FLAG_TC7 (0x02000000U) /*!< Channel 7 transfer complete flag */
<> 156:95d6b41a828b 288 #define DMA_FLAG_HT7 (0x04000000U) /*!< Channel 7 half transfer flag */
<> 156:95d6b41a828b 289 #define DMA_FLAG_TE7 (0x08000000U) /*!< Channel 7 transfer error flag */
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /**
<> 144:ef7eb2e8f9f7 292 * @}
<> 144:ef7eb2e8f9f7 293 */
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 #if defined(SYSCFG_CFGR1_DMA_RMP)
<> 144:ef7eb2e8f9f7 296 /** @defgroup HAL_DMA_remapping HAL DMA remapping
<> 144:ef7eb2e8f9f7 297 * Elements values convention: 0xYYYYYYYY
<> 144:ef7eb2e8f9f7 298 * - YYYYYYYY : Position in the SYSCFG register CFGR1
<> 144:ef7eb2e8f9f7 299 * @{
<> 144:ef7eb2e8f9f7 300 */
<> 144:ef7eb2e8f9f7 301 #define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap
<> 144:ef7eb2e8f9f7 302 0: No remap (ADC DMA requests mapped on DMA channel 1
<> 144:ef7eb2e8f9f7 303 1: Remap (ADC DMA requests mapped on DMA channel 2 */
<> 144:ef7eb2e8f9f7 304 #define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap
<> 144:ef7eb2e8f9f7 305 0: No remap (USART1_TX DMA request mapped on DMA channel 2
<> 144:ef7eb2e8f9f7 306 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */
<> 144:ef7eb2e8f9f7 307 #define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap
<> 144:ef7eb2e8f9f7 308 0: No remap (USART1_RX DMA request mapped on DMA channel 3
<> 144:ef7eb2e8f9f7 309 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */
<> 144:ef7eb2e8f9f7 310 #define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap
<> 144:ef7eb2e8f9f7 311 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3)
<> 144:ef7eb2e8f9f7 312 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */
<> 144:ef7eb2e8f9f7 313 #define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap
<> 144:ef7eb2e8f9f7 314 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
<> 144:ef7eb2e8f9f7 315 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */
<> 144:ef7eb2e8f9f7 316 #if defined (STM32F070xB)
<> 144:ef7eb2e8f9f7 317 #define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only.
<> 144:ef7eb2e8f9f7 318 0: Disabled, need to remap before use
<> 144:ef7eb2e8f9f7 319 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 #endif
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
<> 144:ef7eb2e8f9f7 324 #define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only
<> 144:ef7eb2e8f9f7 325 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit)
<> 144:ef7eb2e8f9f7 326 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */
<> 144:ef7eb2e8f9f7 327 #define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only
<> 144:ef7eb2e8f9f7 328 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit)
<> 144:ef7eb2e8f9f7 329 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */
<> 144:ef7eb2e8f9f7 330 #define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only.
<> 144:ef7eb2e8f9f7 331 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively)
<> 144:ef7eb2e8f9f7 332 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
<> 144:ef7eb2e8f9f7 333 #define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only.
<> 144:ef7eb2e8f9f7 334 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively)
<> 144:ef7eb2e8f9f7 335 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
<> 144:ef7eb2e8f9f7 336 #define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only.
<> 144:ef7eb2e8f9f7 337 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively)
<> 144:ef7eb2e8f9f7 338 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
<> 144:ef7eb2e8f9f7 339 #define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only.
<> 144:ef7eb2e8f9f7 340 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively)
<> 144:ef7eb2e8f9f7 341 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */
<> 144:ef7eb2e8f9f7 342 #define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only.
<> 144:ef7eb2e8f9f7 343 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively)
<> 144:ef7eb2e8f9f7 344 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */
<> 144:ef7eb2e8f9f7 345 #define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only.
<> 144:ef7eb2e8f9f7 346 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively)
<> 144:ef7eb2e8f9f7 347 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */
<> 144:ef7eb2e8f9f7 348 #define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only.
<> 144:ef7eb2e8f9f7 349 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4)
<> 144:ef7eb2e8f9f7 350 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */
<> 144:ef7eb2e8f9f7 351 #endif
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /**
<> 144:ef7eb2e8f9f7 354 * @}
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 #endif /* SYSCFG_CFGR1_DMA_RMP */
<> 144:ef7eb2e8f9f7 358 /**
<> 144:ef7eb2e8f9f7 359 * @}
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 363 /** @defgroup DMA_Exported_Macros DMA Exported Macros
<> 144:ef7eb2e8f9f7 364 * @{
<> 144:ef7eb2e8f9f7 365 */
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /** @brief Reset DMA handle state
<> 144:ef7eb2e8f9f7 368 * @param __HANDLE__: DMA handle.
<> 144:ef7eb2e8f9f7 369 * @retval None
<> 144:ef7eb2e8f9f7 370 */
<> 144:ef7eb2e8f9f7 371 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /**
<> 144:ef7eb2e8f9f7 374 * @brief Enable the specified DMA Channel.
<> 144:ef7eb2e8f9f7 375 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 376 * @retval None
<> 144:ef7eb2e8f9f7 377 */
<> 156:95d6b41a828b 378 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /**
<> 144:ef7eb2e8f9f7 381 * @brief Disable the specified DMA Channel.
<> 144:ef7eb2e8f9f7 382 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 383 * @retval None
<> 144:ef7eb2e8f9f7 384 */
<> 156:95d6b41a828b 385 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /* Interrupt & Flag management */
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /**
<> 144:ef7eb2e8f9f7 391 * @brief Enables the specified DMA Channel interrupts.
<> 144:ef7eb2e8f9f7 392 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 393 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 394 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 395 * @arg DMA_IT_TC: Transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 396 * @arg DMA_IT_HT: Half transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 397 * @arg DMA_IT_TE: Transfer error interrupt mask
<> 144:ef7eb2e8f9f7 398 * @retval None
<> 144:ef7eb2e8f9f7 399 */
<> 156:95d6b41a828b 400 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 /**
<> 144:ef7eb2e8f9f7 403 * @brief Disables the specified DMA Channel interrupts.
<> 144:ef7eb2e8f9f7 404 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 405 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 406 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 407 * @arg DMA_IT_TC: Transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 408 * @arg DMA_IT_HT: Half transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 409 * @arg DMA_IT_TE: Transfer error interrupt mask
<> 144:ef7eb2e8f9f7 410 * @retval None
<> 144:ef7eb2e8f9f7 411 */
<> 156:95d6b41a828b 412 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /**
<> 144:ef7eb2e8f9f7 415 * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
<> 144:ef7eb2e8f9f7 416 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 417 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
<> 144:ef7eb2e8f9f7 418 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 419 * @arg DMA_IT_TC: Transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 420 * @arg DMA_IT_HT: Half transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 421 * @arg DMA_IT_TE: Transfer error interrupt mask
<> 144:ef7eb2e8f9f7 422 * @retval The state of DMA_IT (SET or RESET).
<> 144:ef7eb2e8f9f7 423 */
<> 156:95d6b41a828b 424 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /**
<> 144:ef7eb2e8f9f7 427 * @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
<> 144:ef7eb2e8f9f7 428 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 429 *
<> 144:ef7eb2e8f9f7 430 * @retval The number of remaining data units in the current DMA Channel transfer.
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 #if defined(SYSCFG_CFGR1_DMA_RMP)
<> 144:ef7eb2e8f9f7 435 /** @brief DMA remapping enable/disable macros
<> 144:ef7eb2e8f9f7 436 * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping
<> 144:ef7eb2e8f9f7 437 */
<> 144:ef7eb2e8f9f7 438 #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
<> 144:ef7eb2e8f9f7 439 SYSCFG->CFGR1 |= (__DMA_REMAP__); \
<> 144:ef7eb2e8f9f7 440 }while(0)
<> 144:ef7eb2e8f9f7 441 #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
<> 144:ef7eb2e8f9f7 442 SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
<> 144:ef7eb2e8f9f7 443 }while(0)
<> 144:ef7eb2e8f9f7 444 #endif /* SYSCFG_CFGR1_DMA_RMP */
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /**
<> 144:ef7eb2e8f9f7 447 * @}
<> 144:ef7eb2e8f9f7 448 */
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /* Include DMA HAL Extension module */
<> 144:ef7eb2e8f9f7 451 #include "stm32f0xx_hal_dma_ex.h"
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 454 /** @addtogroup DMA_Exported_Functions
<> 144:ef7eb2e8f9f7 455 * @{
<> 144:ef7eb2e8f9f7 456 */
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /** @addtogroup DMA_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 459 * @{
<> 144:ef7eb2e8f9f7 460 */
<> 144:ef7eb2e8f9f7 461 /* Initialization and de-initialization functions *****************************/
<> 144:ef7eb2e8f9f7 462 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 463 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 464 /**
<> 144:ef7eb2e8f9f7 465 * @}
<> 144:ef7eb2e8f9f7 466 */
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /** @addtogroup DMA_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 469 * @{
<> 144:ef7eb2e8f9f7 470 */
<> 144:ef7eb2e8f9f7 471 /* Input and Output operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 472 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 473 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 474 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 475 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 476 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 477 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 478 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
<> 156:95d6b41a828b 479 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
<> 156:95d6b41a828b 480
<> 144:ef7eb2e8f9f7 481 /**
<> 144:ef7eb2e8f9f7 482 * @}
<> 144:ef7eb2e8f9f7 483 */
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /** @addtogroup DMA_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 486 * @{
<> 144:ef7eb2e8f9f7 487 */
<> 144:ef7eb2e8f9f7 488 /* Peripheral State and Error functions ***************************************/
<> 144:ef7eb2e8f9f7 489 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 490 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 491 /**
<> 144:ef7eb2e8f9f7 492 * @}
<> 144:ef7eb2e8f9f7 493 */
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /**
<> 144:ef7eb2e8f9f7 496 * @}
<> 144:ef7eb2e8f9f7 497 */
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 /** @addtogroup DMA_Private_Macros
<> 144:ef7eb2e8f9f7 500 * @{
<> 144:ef7eb2e8f9f7 501 */
<> 144:ef7eb2e8f9f7 502 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
<> 144:ef7eb2e8f9f7 503 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
<> 144:ef7eb2e8f9f7 504 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
<> 144:ef7eb2e8f9f7 505 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
<> 144:ef7eb2e8f9f7 506 ((STATE) == DMA_PINC_DISABLE))
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
<> 144:ef7eb2e8f9f7 509 ((STATE) == DMA_MINC_DISABLE))
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
<> 144:ef7eb2e8f9f7 512 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
<> 144:ef7eb2e8f9f7 513 ((SIZE) == DMA_PDATAALIGN_WORD))
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
<> 144:ef7eb2e8f9f7 516 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
<> 144:ef7eb2e8f9f7 517 ((SIZE) == DMA_MDATAALIGN_WORD ))
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
<> 144:ef7eb2e8f9f7 520 ((MODE) == DMA_CIRCULAR))
<> 144:ef7eb2e8f9f7 521 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
<> 144:ef7eb2e8f9f7 522 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
<> 144:ef7eb2e8f9f7 523 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
<> 144:ef7eb2e8f9f7 524 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
<> 156:95d6b41a828b 525 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 #if defined(SYSCFG_CFGR1_DMA_RMP)
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
<> 144:ef7eb2e8f9f7 530 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
<> 144:ef7eb2e8f9f7 531 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
<> 144:ef7eb2e8f9f7 532 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
<> 144:ef7eb2e8f9f7 533 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
<> 144:ef7eb2e8f9f7 534 ((RMP) == DMA_REMAP_TIM17_DMA_CH2) || \
<> 144:ef7eb2e8f9f7 535 ((RMP) == DMA_REMAP_TIM16_DMA_CH6) || \
<> 144:ef7eb2e8f9f7 536 ((RMP) == DMA_REMAP_TIM17_DMA_CH7) || \
<> 144:ef7eb2e8f9f7 537 ((RMP) == DMA_REMAP_SPI2_DMA_CH67) || \
<> 144:ef7eb2e8f9f7 538 ((RMP) == DMA_REMAP_USART2_DMA_CH67) || \
<> 144:ef7eb2e8f9f7 539 ((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
<> 144:ef7eb2e8f9f7 540 ((RMP) == DMA_REMAP_I2C1_DMA_CH76) || \
<> 144:ef7eb2e8f9f7 541 ((RMP) == DMA_REMAP_TIM1_DMA_CH6) || \
<> 144:ef7eb2e8f9f7 542 ((RMP) == DMA_REMAP_TIM2_DMA_CH7) || \
<> 144:ef7eb2e8f9f7 543 ((RMP) == DMA_REMAP_TIM3_DMA_CH6))
<> 144:ef7eb2e8f9f7 544 #elif defined (STM32F070xB)
<> 144:ef7eb2e8f9f7 545 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
<> 144:ef7eb2e8f9f7 546 ((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
<> 144:ef7eb2e8f9f7 547 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
<> 144:ef7eb2e8f9f7 548 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
<> 144:ef7eb2e8f9f7 549 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
<> 144:ef7eb2e8f9f7 550 ((RMP) == DMA_REMAP_TIM17_DMA_CH2))
<> 144:ef7eb2e8f9f7 551 #else
<> 144:ef7eb2e8f9f7 552 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
<> 144:ef7eb2e8f9f7 553 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
<> 144:ef7eb2e8f9f7 554 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
<> 144:ef7eb2e8f9f7 555 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
<> 144:ef7eb2e8f9f7 556 ((RMP) == DMA_REMAP_TIM17_DMA_CH2))
<> 144:ef7eb2e8f9f7 557 #endif
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 #endif /* SYSCFG_CFGR1_DMA_RMP */
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /**
<> 144:ef7eb2e8f9f7 563 * @}
<> 144:ef7eb2e8f9f7 564 */
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 /**
<> 144:ef7eb2e8f9f7 567 * @}
<> 144:ef7eb2e8f9f7 568 */
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /**
<> 144:ef7eb2e8f9f7 571 * @}
<> 144:ef7eb2e8f9f7 572 */
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 575 }
<> 144:ef7eb2e8f9f7 576 #endif
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 #endif /* __STM32F0xx_HAL_DMA_H */
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 581