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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_dma.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief DMA HAL module driver.
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 8 * functionalities of the Direct Memory Access (DMA) peripheral:
<> 144:ef7eb2e8f9f7 9 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 10 * + IO operation functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral State and errors functions
<> 144:ef7eb2e8f9f7 12 @verbatim
<> 144:ef7eb2e8f9f7 13 ==============================================================================
<> 144:ef7eb2e8f9f7 14 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 [..]
<> 144:ef7eb2e8f9f7 17 (#) Enable and configure the peripheral to be connected to the DMA Channel
<> 144:ef7eb2e8f9f7 18 (except for internal SRAM / FLASH memories: no initialization is
<> 156:95d6b41a828b 19 necessary). Please refer to Reference manual for connection between peripherals
<> 144:ef7eb2e8f9f7 20 and DMA requests .
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 (#) For a given Channel, program the required configuration through the following parameters:
<> 144:ef7eb2e8f9f7 23 Transfer Direction, Source and Destination data formats,
<> 144:ef7eb2e8f9f7 24 Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
<> 144:ef7eb2e8f9f7 25 using HAL_DMA_Init() function.
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
<> 144:ef7eb2e8f9f7 28 detection.
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 (#) Use HAL_DMA_Abort() function to abort the current transfer
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
<> 144:ef7eb2e8f9f7 33 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 34 =================================
<> 144:ef7eb2e8f9f7 35 [..]
<> 144:ef7eb2e8f9f7 36 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
<> 144:ef7eb2e8f9f7 37 address and destination address and the Length of data to be transferred
<> 144:ef7eb2e8f9f7 38 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
<> 144:ef7eb2e8f9f7 39 case a fixed Timeout can be configured by User depending from his application.
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 42 ===================================
<> 144:ef7eb2e8f9f7 43 [..]
<> 144:ef7eb2e8f9f7 44 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
<> 144:ef7eb2e8f9f7 45 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 46 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
<> 144:ef7eb2e8f9f7 47 Source address and destination address and the Length of data to be transferred.
<> 144:ef7eb2e8f9f7 48 In this case the DMA interrupt is configured
<> 156:95d6b41a828b 49 (+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
<> 144:ef7eb2e8f9f7 50 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
<> 144:ef7eb2e8f9f7 51 add his own function by customization of function pointer XferCpltCallback and
<> 144:ef7eb2e8f9f7 52 XferErrorCallback (i.e a member of DMA handle structure).
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 *** DMA HAL driver macros list ***
<> 144:ef7eb2e8f9f7 55 =============================================
<> 144:ef7eb2e8f9f7 56 [..]
<> 144:ef7eb2e8f9f7 57 Below the list of most used macros in DMA HAL driver.
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 [..]
<> 144:ef7eb2e8f9f7 60 (@) You can refer to the DMA HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 @endverbatim
<> 144:ef7eb2e8f9f7 63 ******************************************************************************
<> 144:ef7eb2e8f9f7 64 * @attention
<> 144:ef7eb2e8f9f7 65 *
<> 144:ef7eb2e8f9f7 66 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 67 *
<> 144:ef7eb2e8f9f7 68 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 69 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 70 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 71 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 72 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 73 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 74 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 75 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 76 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 77 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 78 *
<> 144:ef7eb2e8f9f7 79 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 80 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 82 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 85 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 86 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 87 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 88 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 89 *
<> 144:ef7eb2e8f9f7 90 ******************************************************************************
<> 144:ef7eb2e8f9f7 91 */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 94 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 97 * @{
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /** @defgroup DMA DMA
<> 144:ef7eb2e8f9f7 102 * @brief DMA HAL module driver
<> 144:ef7eb2e8f9f7 103 * @{
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 156:95d6b41a828b 106 #ifdef HAL_DMA_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 109 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 110 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 111 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 112 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 113 /** @defgroup DMA_Private_Functions DMA Private Functions
<> 144:ef7eb2e8f9f7 114 * @{
<> 144:ef7eb2e8f9f7 115 */
<> 144:ef7eb2e8f9f7 116 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 156:95d6b41a828b 117 static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 118 /**
<> 144:ef7eb2e8f9f7 119 * @}
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /** @defgroup DMA_Exported_Functions DMA Exported Functions
<> 144:ef7eb2e8f9f7 125 * @{
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 129 * @brief Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 130 *
<> 144:ef7eb2e8f9f7 131 @verbatim
<> 144:ef7eb2e8f9f7 132 ===============================================================================
<> 144:ef7eb2e8f9f7 133 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 134 ===============================================================================
<> 144:ef7eb2e8f9f7 135 [..]
<> 144:ef7eb2e8f9f7 136 This section provides functions allowing to initialize the DMA Channel source
<> 144:ef7eb2e8f9f7 137 and destination addresses, incrementation and data sizes, transfer direction,
<> 144:ef7eb2e8f9f7 138 circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
<> 144:ef7eb2e8f9f7 139 [..]
<> 144:ef7eb2e8f9f7 140 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
<> 144:ef7eb2e8f9f7 141 reference manual.
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 @endverbatim
<> 144:ef7eb2e8f9f7 144 * @{
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /**
<> 156:95d6b41a828b 148 * @brief Initialize the DMA according to the specified
<> 156:95d6b41a828b 149 * parameters in the DMA_InitTypeDef and initialize the associated handle.
Anna Bridge 180:96ed750bd169 150 * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 151 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 152 * @retval HAL status
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 155 {
<> 156:95d6b41a828b 156 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /* Check the DMA handle allocation */
<> 156:95d6b41a828b 159 if(NULL == hdma)
<> 144:ef7eb2e8f9f7 160 {
<> 144:ef7eb2e8f9f7 161 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 162 }
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /* Check the parameters */
<> 144:ef7eb2e8f9f7 165 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
<> 144:ef7eb2e8f9f7 166 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
<> 144:ef7eb2e8f9f7 167 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
<> 144:ef7eb2e8f9f7 168 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
<> 144:ef7eb2e8f9f7 169 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
<> 144:ef7eb2e8f9f7 170 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
<> 144:ef7eb2e8f9f7 171 assert_param(IS_DMA_MODE(hdma->Init.Mode));
<> 144:ef7eb2e8f9f7 172 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 175 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /* Get the CR register value */
<> 144:ef7eb2e8f9f7 178 tmp = hdma->Instance->CCR;
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
<> 144:ef7eb2e8f9f7 181 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
<> 144:ef7eb2e8f9f7 182 DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
<> 144:ef7eb2e8f9f7 183 DMA_CCR_DIR));
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /* Prepare the DMA Channel configuration */
<> 144:ef7eb2e8f9f7 186 tmp |= hdma->Init.Direction |
<> 144:ef7eb2e8f9f7 187 hdma->Init.PeriphInc | hdma->Init.MemInc |
<> 144:ef7eb2e8f9f7 188 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
<> 144:ef7eb2e8f9f7 189 hdma->Init.Mode | hdma->Init.Priority;
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /* Write to DMA Channel CR register */
<> 144:ef7eb2e8f9f7 192 hdma->Instance->CCR = tmp;
<> 144:ef7eb2e8f9f7 193
<> 156:95d6b41a828b 194 /* Initialize DmaBaseAddress and ChannelIndex parameters used
<> 156:95d6b41a828b 195 by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
<> 156:95d6b41a828b 196 DMA_CalcBaseAndBitshift(hdma);
<> 156:95d6b41a828b 197
<> 156:95d6b41a828b 198 /* Clean callbacks */
<> 156:95d6b41a828b 199 hdma->XferCpltCallback = NULL;
<> 156:95d6b41a828b 200 hdma->XferHalfCpltCallback = NULL;
<> 156:95d6b41a828b 201 hdma->XferErrorCallback = NULL;
<> 156:95d6b41a828b 202 hdma->XferAbortCallback = NULL;
<> 156:95d6b41a828b 203
<> 144:ef7eb2e8f9f7 204 /* Initialise the error code */
<> 144:ef7eb2e8f9f7 205 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /* Initialize the DMA state*/
<> 156:95d6b41a828b 208 hdma->State = HAL_DMA_STATE_READY;
<> 156:95d6b41a828b 209
<> 156:95d6b41a828b 210 /* Allocate lock resource and initialize it */
<> 156:95d6b41a828b 211 hdma->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 return HAL_OK;
<> 144:ef7eb2e8f9f7 214 }
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /**
<> 156:95d6b41a828b 217 * @brief DeInitialize the DMA peripheral
Anna Bridge 180:96ed750bd169 218 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 219 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 220 * @retval HAL status
<> 144:ef7eb2e8f9f7 221 */
<> 144:ef7eb2e8f9f7 222 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 223 {
<> 144:ef7eb2e8f9f7 224 /* Check the DMA handle allocation */
<> 156:95d6b41a828b 225 if(NULL == hdma)
<> 144:ef7eb2e8f9f7 226 {
<> 144:ef7eb2e8f9f7 227 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 228 }
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /* Check the parameters */
<> 144:ef7eb2e8f9f7 231 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /* Disable the selected DMA Channelx */
<> 156:95d6b41a828b 234 hdma->Instance->CCR &= ~DMA_CCR_EN;
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /* Reset DMA Channel control register */
<> 156:95d6b41a828b 237 hdma->Instance->CCR = 0U;
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /* Reset DMA Channel Number of Data to Transfer register */
<> 156:95d6b41a828b 240 hdma->Instance->CNDTR = 0U;
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /* Reset DMA Channel peripheral address register */
<> 156:95d6b41a828b 243 hdma->Instance->CPAR = 0U;
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /* Reset DMA Channel memory address register */
<> 156:95d6b41a828b 246 hdma->Instance->CMAR = 0U;
<> 156:95d6b41a828b 247
<> 156:95d6b41a828b 248 /* Get DMA Base Address */
<> 156:95d6b41a828b 249 DMA_CalcBaseAndBitshift(hdma);
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* Clear all flags */
<> 156:95d6b41a828b 252 hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Initialize the error code */
<> 144:ef7eb2e8f9f7 255 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /* Initialize the DMA state */
<> 144:ef7eb2e8f9f7 258 hdma->State = HAL_DMA_STATE_RESET;
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /* Release Lock */
<> 144:ef7eb2e8f9f7 261 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 return HAL_OK;
<> 144:ef7eb2e8f9f7 264 }
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /**
<> 144:ef7eb2e8f9f7 267 * @}
<> 144:ef7eb2e8f9f7 268 */
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
<> 144:ef7eb2e8f9f7 271 * @brief I/O operation functions
<> 144:ef7eb2e8f9f7 272 *
<> 144:ef7eb2e8f9f7 273 @verbatim
<> 144:ef7eb2e8f9f7 274 ===============================================================================
<> 144:ef7eb2e8f9f7 275 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 276 ===============================================================================
<> 144:ef7eb2e8f9f7 277 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 278 (+) Configure the source, destination address and data length and Start DMA transfer
<> 144:ef7eb2e8f9f7 279 (+) Configure the source, destination address and data length and
<> 144:ef7eb2e8f9f7 280 Start DMA transfer with interrupt
<> 144:ef7eb2e8f9f7 281 (+) Abort DMA transfer
<> 144:ef7eb2e8f9f7 282 (+) Poll for transfer complete
<> 144:ef7eb2e8f9f7 283 (+) Handle DMA interrupt request
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 @endverbatim
<> 144:ef7eb2e8f9f7 286 * @{
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /**
<> 156:95d6b41a828b 290 * @brief Start the DMA Transfer.
Anna Bridge 180:96ed750bd169 291 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
Anna Bridge 180:96ed750bd169 292 * the configuration information for the specified DMA Channel.
Anna Bridge 180:96ed750bd169 293 * @param SrcAddress The source memory Buffer address
Anna Bridge 180:96ed750bd169 294 * @param DstAddress The destination memory Buffer address
Anna Bridge 180:96ed750bd169 295 * @param DataLength The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 296 * @retval HAL status
<> 144:ef7eb2e8f9f7 297 */
<> 144:ef7eb2e8f9f7 298 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 156:95d6b41a828b 299 {
<> 156:95d6b41a828b 300 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 301
<> 156:95d6b41a828b 302 /* Check the parameters */
<> 144:ef7eb2e8f9f7 303 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 304
<> 156:95d6b41a828b 305 /* Process locked */
<> 156:95d6b41a828b 306 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 307
<> 156:95d6b41a828b 308 if(HAL_DMA_STATE_READY == hdma->State)
<> 156:95d6b41a828b 309 {
<> 156:95d6b41a828b 310 /* Change DMA peripheral state */
<> 156:95d6b41a828b 311 hdma->State = HAL_DMA_STATE_BUSY;
<> 156:95d6b41a828b 312
<> 156:95d6b41a828b 313 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 156:95d6b41a828b 314
<> 156:95d6b41a828b 315 /* Disable the peripheral */
<> 156:95d6b41a828b 316 hdma->Instance->CCR &= ~DMA_CCR_EN;
<> 156:95d6b41a828b 317
<> 156:95d6b41a828b 318 /* Configure the source, destination address and the data length */
<> 156:95d6b41a828b 319 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 156:95d6b41a828b 320
<> 156:95d6b41a828b 321 /* Enable the Peripheral */
<> 156:95d6b41a828b 322 hdma->Instance->CCR |= DMA_CCR_EN;
<> 156:95d6b41a828b 323 }
<> 156:95d6b41a828b 324 else
<> 156:95d6b41a828b 325 {
<> 156:95d6b41a828b 326 /* Process Unlocked */
<> 156:95d6b41a828b 327 __HAL_UNLOCK(hdma);
<> 156:95d6b41a828b 328
<> 156:95d6b41a828b 329 /* Remain BUSY */
<> 156:95d6b41a828b 330 status = HAL_BUSY;
<> 156:95d6b41a828b 331 }
<> 144:ef7eb2e8f9f7 332
<> 156:95d6b41a828b 333 return status;
<> 144:ef7eb2e8f9f7 334 }
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /**
<> 144:ef7eb2e8f9f7 337 * @brief Start the DMA Transfer with interrupt enabled.
Anna Bridge 180:96ed750bd169 338 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 339 * the configuration information for the specified DMA Channel.
Anna Bridge 180:96ed750bd169 340 * @param SrcAddress The source memory Buffer address
Anna Bridge 180:96ed750bd169 341 * @param DstAddress The destination memory Buffer address
Anna Bridge 180:96ed750bd169 342 * @param DataLength The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 343 * @retval HAL status
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 346 {
<> 156:95d6b41a828b 347 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 348
<> 156:95d6b41a828b 349 /* Check the parameters */
<> 144:ef7eb2e8f9f7 350 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 351
<> 156:95d6b41a828b 352 /* Process locked */
<> 156:95d6b41a828b 353 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 354
<> 156:95d6b41a828b 355 if(HAL_DMA_STATE_READY == hdma->State)
<> 156:95d6b41a828b 356 {
<> 156:95d6b41a828b 357 /* Change DMA peripheral state */
<> 156:95d6b41a828b 358 hdma->State = HAL_DMA_STATE_BUSY;
<> 156:95d6b41a828b 359
<> 156:95d6b41a828b 360 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 156:95d6b41a828b 361
<> 156:95d6b41a828b 362 /* Disable the peripheral */
<> 156:95d6b41a828b 363 hdma->Instance->CCR &= ~DMA_CCR_EN;
<> 156:95d6b41a828b 364
<> 156:95d6b41a828b 365 /* Configure the source, destination address and the data length */
<> 156:95d6b41a828b 366 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 156:95d6b41a828b 367
<> 156:95d6b41a828b 368 /* Enable the transfer complete, & transfer error interrupts */
<> 156:95d6b41a828b 369 /* Half transfer interrupt is optional: enable it only if associated callback is available */
<> 156:95d6b41a828b 370 if(NULL != hdma->XferHalfCpltCallback )
<> 156:95d6b41a828b 371 {
<> 156:95d6b41a828b 372 hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
<> 156:95d6b41a828b 373 }
<> 156:95d6b41a828b 374 else
<> 156:95d6b41a828b 375 {
<> 156:95d6b41a828b 376 hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE);
<> 156:95d6b41a828b 377 hdma->Instance->CCR &= ~DMA_IT_HT;
<> 156:95d6b41a828b 378 }
<> 156:95d6b41a828b 379
<> 156:95d6b41a828b 380 /* Enable the Peripheral */
<> 156:95d6b41a828b 381 hdma->Instance->CCR |= DMA_CCR_EN;
<> 156:95d6b41a828b 382 }
<> 156:95d6b41a828b 383 else
<> 156:95d6b41a828b 384 {
<> 156:95d6b41a828b 385 /* Process Unlocked */
<> 156:95d6b41a828b 386 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 387
<> 156:95d6b41a828b 388 /* Remain BUSY */
<> 156:95d6b41a828b 389 status = HAL_BUSY;
<> 156:95d6b41a828b 390 }
<> 144:ef7eb2e8f9f7 391
<> 156:95d6b41a828b 392 return status;
<> 144:ef7eb2e8f9f7 393 }
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /**
<> 156:95d6b41a828b 396 * @brief Abort the DMA Transfer.
Anna Bridge 180:96ed750bd169 397 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
Anna Bridge 180:96ed750bd169 398 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 399 * @retval HAL status
<> 144:ef7eb2e8f9f7 400 */
<> 144:ef7eb2e8f9f7 401 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 402 {
<> 156:95d6b41a828b 403 /* Disable DMA IT */
<> 156:95d6b41a828b 404 hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
<> 156:95d6b41a828b 405
<> 156:95d6b41a828b 406 /* Disable the channel */
<> 156:95d6b41a828b 407 hdma->Instance->CCR &= ~DMA_CCR_EN;
<> 156:95d6b41a828b 408
<> 156:95d6b41a828b 409 /* Clear all flags */
<> 156:95d6b41a828b 410 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
<> 156:95d6b41a828b 411
<> 156:95d6b41a828b 412 /* Change the DMA state*/
<> 156:95d6b41a828b 413 hdma->State = HAL_DMA_STATE_READY;
<> 156:95d6b41a828b 414
<> 156:95d6b41a828b 415 /* Process Unlocked */
<> 156:95d6b41a828b 416 __HAL_UNLOCK(hdma);
<> 156:95d6b41a828b 417
<> 156:95d6b41a828b 418 return HAL_OK;
<> 144:ef7eb2e8f9f7 419 }
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /**
<> 156:95d6b41a828b 422 * @brief Abort the DMA Transfer in Interrupt mode.
Anna Bridge 180:96ed750bd169 423 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
Anna Bridge 180:96ed750bd169 424 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 425 * @retval HAL status
<> 144:ef7eb2e8f9f7 426 */
<> 144:ef7eb2e8f9f7 427 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 428 {
<> 144:ef7eb2e8f9f7 429 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 if(HAL_DMA_STATE_BUSY != hdma->State)
<> 144:ef7eb2e8f9f7 432 {
<> 144:ef7eb2e8f9f7 433 /* no transfer ongoing */
<> 144:ef7eb2e8f9f7 434 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 437 }
<> 144:ef7eb2e8f9f7 438 else
<> 144:ef7eb2e8f9f7 439 {
<> 156:95d6b41a828b 440
<> 144:ef7eb2e8f9f7 441 /* Disable DMA IT */
<> 156:95d6b41a828b 442 hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /* Disable the channel */
<> 156:95d6b41a828b 445 hdma->Instance->CCR &= ~DMA_CCR_EN;
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /* Clear all flags */
<> 156:95d6b41a828b 448 hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 451 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 454 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /* Call User Abort callback */
<> 144:ef7eb2e8f9f7 457 if(hdma->XferAbortCallback != NULL)
<> 144:ef7eb2e8f9f7 458 {
<> 144:ef7eb2e8f9f7 459 hdma->XferAbortCallback(hdma);
<> 144:ef7eb2e8f9f7 460 }
<> 144:ef7eb2e8f9f7 461 }
<> 144:ef7eb2e8f9f7 462 return status;
<> 144:ef7eb2e8f9f7 463 }
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /**
<> 144:ef7eb2e8f9f7 466 * @brief Polling for transfer complete.
Anna Bridge 180:96ed750bd169 467 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 468 * the configuration information for the specified DMA Channel.
Anna Bridge 180:96ed750bd169 469 * @param CompleteLevel Specifies the DMA level complete.
Anna Bridge 180:96ed750bd169 470 * @param Timeout Timeout duration.
<> 144:ef7eb2e8f9f7 471 * @retval HAL status
<> 144:ef7eb2e8f9f7 472 */
<> 144:ef7eb2e8f9f7 473 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 474 {
<> 144:ef7eb2e8f9f7 475 uint32_t temp;
<> 156:95d6b41a828b 476 uint32_t tickstart = 0U;
<> 156:95d6b41a828b 477
<> 156:95d6b41a828b 478 if(HAL_DMA_STATE_BUSY != hdma->State)
<> 156:95d6b41a828b 479 {
<> 156:95d6b41a828b 480 /* no transfer ongoing */
<> 156:95d6b41a828b 481 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<> 156:95d6b41a828b 482 __HAL_UNLOCK(hdma);
<> 156:95d6b41a828b 483 return HAL_ERROR;
<> 156:95d6b41a828b 484 }
<> 156:95d6b41a828b 485
<> 156:95d6b41a828b 486 /* Polling mode not supported in circular mode */
<> 156:95d6b41a828b 487 if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
<> 156:95d6b41a828b 488 {
<> 156:95d6b41a828b 489 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
<> 156:95d6b41a828b 490 return HAL_ERROR;
<> 156:95d6b41a828b 491 }
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /* Get the level transfer complete flag */
<> 156:95d6b41a828b 494 if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
<> 144:ef7eb2e8f9f7 495 {
<> 144:ef7eb2e8f9f7 496 /* Transfer Complete flag */
<> 156:95d6b41a828b 497 temp = DMA_FLAG_TC1 << hdma->ChannelIndex;
<> 144:ef7eb2e8f9f7 498 }
<> 144:ef7eb2e8f9f7 499 else
<> 144:ef7eb2e8f9f7 500 {
<> 144:ef7eb2e8f9f7 501 /* Half Transfer Complete flag */
<> 156:95d6b41a828b 502 temp = DMA_FLAG_HT1 << hdma->ChannelIndex;
<> 144:ef7eb2e8f9f7 503 }
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /* Get tick */
<> 144:ef7eb2e8f9f7 506 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 507
<> 156:95d6b41a828b 508 while(RESET == (hdma->DmaBaseAddress->ISR & temp))
<> 144:ef7eb2e8f9f7 509 {
<> 156:95d6b41a828b 510 if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))
<> 144:ef7eb2e8f9f7 511 {
<> 156:95d6b41a828b 512 /* When a DMA transfer error occurs */
<> 156:95d6b41a828b 513 /* A hardware clear of its EN bits is performed */
<> 156:95d6b41a828b 514 /* Clear all flags */
<> 156:95d6b41a828b 515 hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /* Update error code */
<> 156:95d6b41a828b 518 hdma->ErrorCode = HAL_DMA_ERROR_TE;
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /* Change the DMA state */
<> 156:95d6b41a828b 521 hdma->State= HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 524 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 527 }
<> 144:ef7eb2e8f9f7 528 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 529 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 530 {
<> 156:95d6b41a828b 531 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 532 {
<> 144:ef7eb2e8f9f7 533 /* Update error code */
<> 156:95d6b41a828b 534 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /* Change the DMA state */
<> 156:95d6b41a828b 537 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 540 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 541
<> 156:95d6b41a828b 542 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 543 }
<> 144:ef7eb2e8f9f7 544 }
<> 144:ef7eb2e8f9f7 545 }
<> 144:ef7eb2e8f9f7 546
<> 156:95d6b41a828b 547 if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
<> 144:ef7eb2e8f9f7 548 {
<> 144:ef7eb2e8f9f7 549 /* Clear the transfer complete flag */
<> 156:95d6b41a828b 550 hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 /* The selected Channelx EN bit is cleared (DMA is disabled and
<> 144:ef7eb2e8f9f7 553 all transfers are complete) */
<> 144:ef7eb2e8f9f7 554 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 555 }
<> 144:ef7eb2e8f9f7 556 else
<> 144:ef7eb2e8f9f7 557 {
<> 144:ef7eb2e8f9f7 558 /* Clear the half transfer complete flag */
<> 156:95d6b41a828b 559 hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
<> 144:ef7eb2e8f9f7 560 }
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /* Process unlocked */
<> 144:ef7eb2e8f9f7 563 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 return HAL_OK;
<> 144:ef7eb2e8f9f7 566 }
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /**
<> 156:95d6b41a828b 569 * @brief Handle DMA interrupt request.
Anna Bridge 180:96ed750bd169 570 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 571 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 572 * @retval None
<> 144:ef7eb2e8f9f7 573 */
<> 144:ef7eb2e8f9f7 574 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 575 {
<> 156:95d6b41a828b 576 uint32_t flag_it = hdma->DmaBaseAddress->ISR;
<> 156:95d6b41a828b 577 uint32_t source_it = hdma->Instance->CCR;
<> 156:95d6b41a828b 578
<> 156:95d6b41a828b 579 /* Half Transfer Complete Interrupt management ******************************/
<> 156:95d6b41a828b 580 if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
<> 144:ef7eb2e8f9f7 581 {
<> 156:95d6b41a828b 582 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
<> 156:95d6b41a828b 583 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
<> 156:95d6b41a828b 584 {
<> 156:95d6b41a828b 585 /* Disable the half transfer interrupt */
<> 156:95d6b41a828b 586 hdma->Instance->CCR &= ~DMA_IT_HT;
<> 156:95d6b41a828b 587 }
<> 156:95d6b41a828b 588
<> 156:95d6b41a828b 589 /* Clear the half transfer complete flag */
<> 156:95d6b41a828b 590 hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
<> 156:95d6b41a828b 591
<> 156:95d6b41a828b 592 /* DMA peripheral state is not updated in Half Transfer */
<> 156:95d6b41a828b 593 /* State is updated only in Transfer Complete case */
<> 156:95d6b41a828b 594
<> 156:95d6b41a828b 595 if(hdma->XferHalfCpltCallback != NULL)
<> 156:95d6b41a828b 596 {
<> 156:95d6b41a828b 597 /* Half transfer callback */
<> 156:95d6b41a828b 598 hdma->XferHalfCpltCallback(hdma);
<> 156:95d6b41a828b 599 }
<> 144:ef7eb2e8f9f7 600 }
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /* Transfer Complete Interrupt management ***********************************/
<> 156:95d6b41a828b 603 else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
<> 144:ef7eb2e8f9f7 604 {
<> 156:95d6b41a828b 605 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
<> 156:95d6b41a828b 606 {
<> 156:95d6b41a828b 607 /* Disable the transfer complete & transfer error interrupts */
<> 156:95d6b41a828b 608 /* if the DMA mode is not CIRCULAR */
<> 156:95d6b41a828b 609 hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
<> 156:95d6b41a828b 610
<> 156:95d6b41a828b 611 /* Change the DMA state */
<> 156:95d6b41a828b 612 hdma->State = HAL_DMA_STATE_READY;
<> 156:95d6b41a828b 613 }
<> 156:95d6b41a828b 614
<> 156:95d6b41a828b 615 /* Clear the transfer complete flag */
<> 156:95d6b41a828b 616 hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
<> 156:95d6b41a828b 617
<> 156:95d6b41a828b 618 /* Process Unlocked */
<> 156:95d6b41a828b 619 __HAL_UNLOCK(hdma);
<> 156:95d6b41a828b 620
<> 156:95d6b41a828b 621 if(hdma->XferCpltCallback != NULL)
<> 156:95d6b41a828b 622 {
<> 156:95d6b41a828b 623 /* Transfer complete callback */
<> 156:95d6b41a828b 624 hdma->XferCpltCallback(hdma);
<> 156:95d6b41a828b 625 }
<> 156:95d6b41a828b 626 }
<> 156:95d6b41a828b 627
<> 156:95d6b41a828b 628 /* Transfer Error Interrupt management ***************************************/
<> 156:95d6b41a828b 629 else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
<> 156:95d6b41a828b 630 {
<> 156:95d6b41a828b 631 /* When a DMA transfer error occurs */
<> 156:95d6b41a828b 632 /* A hardware clear of its EN bits is performed */
<> 156:95d6b41a828b 633 /* Then, disable all DMA interrupts */
<> 156:95d6b41a828b 634 hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
<> 156:95d6b41a828b 635
<> 156:95d6b41a828b 636 /* Clear all flags */
<> 156:95d6b41a828b 637 hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
<> 156:95d6b41a828b 638
<> 156:95d6b41a828b 639 /* Update error code */
<> 156:95d6b41a828b 640 hdma->ErrorCode = HAL_DMA_ERROR_TE;
<> 156:95d6b41a828b 641
<> 156:95d6b41a828b 642 /* Change the DMA state */
<> 156:95d6b41a828b 643 hdma->State = HAL_DMA_STATE_READY;
<> 156:95d6b41a828b 644
<> 156:95d6b41a828b 645 /* Process Unlocked */
<> 156:95d6b41a828b 646 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 647
<> 156:95d6b41a828b 648 if(hdma->XferErrorCallback != NULL)
<> 156:95d6b41a828b 649 {
<> 156:95d6b41a828b 650 /* Transfer error callback */
<> 156:95d6b41a828b 651 hdma->XferErrorCallback(hdma);
<> 156:95d6b41a828b 652 }
<> 156:95d6b41a828b 653 }
<> 156:95d6b41a828b 654 }
<> 144:ef7eb2e8f9f7 655
<> 156:95d6b41a828b 656 /**
<> 156:95d6b41a828b 657 * @brief Register callbacks
Anna Bridge 180:96ed750bd169 658 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 659 * the configuration information for the specified DMA Stream.
Anna Bridge 180:96ed750bd169 660 * @param CallbackID User Callback identifer
<> 156:95d6b41a828b 661 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
Anna Bridge 180:96ed750bd169 662 * @param pCallback pointer to private callback function which has pointer to
<> 156:95d6b41a828b 663 * a DMA_HandleTypeDef structure as parameter.
<> 156:95d6b41a828b 664 * @retval HAL status
<> 156:95d6b41a828b 665 */
<> 156:95d6b41a828b 666 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
<> 156:95d6b41a828b 667 {
<> 156:95d6b41a828b 668 HAL_StatusTypeDef status = HAL_OK;
<> 156:95d6b41a828b 669
<> 156:95d6b41a828b 670 /* Process locked */
<> 156:95d6b41a828b 671 __HAL_LOCK(hdma);
<> 156:95d6b41a828b 672
<> 156:95d6b41a828b 673 if(HAL_DMA_STATE_READY == hdma->State)
<> 156:95d6b41a828b 674 {
<> 156:95d6b41a828b 675 switch (CallbackID)
<> 156:95d6b41a828b 676 {
<> 156:95d6b41a828b 677 case HAL_DMA_XFER_CPLT_CB_ID:
<> 156:95d6b41a828b 678 hdma->XferCpltCallback = pCallback;
<> 156:95d6b41a828b 679 break;
<> 156:95d6b41a828b 680
<> 156:95d6b41a828b 681 case HAL_DMA_XFER_HALFCPLT_CB_ID:
<> 156:95d6b41a828b 682 hdma->XferHalfCpltCallback = pCallback;
<> 156:95d6b41a828b 683 break;
<> 156:95d6b41a828b 684
<> 156:95d6b41a828b 685 case HAL_DMA_XFER_ERROR_CB_ID:
<> 156:95d6b41a828b 686 hdma->XferErrorCallback = pCallback;
<> 156:95d6b41a828b 687 break;
<> 156:95d6b41a828b 688
<> 156:95d6b41a828b 689 case HAL_DMA_XFER_ABORT_CB_ID:
<> 156:95d6b41a828b 690 hdma->XferAbortCallback = pCallback;
<> 156:95d6b41a828b 691 break;
<> 156:95d6b41a828b 692
<> 156:95d6b41a828b 693 default:
<> 156:95d6b41a828b 694 status = HAL_ERROR;
<> 156:95d6b41a828b 695 break;
<> 144:ef7eb2e8f9f7 696 }
<> 144:ef7eb2e8f9f7 697 }
<> 156:95d6b41a828b 698 else
<> 156:95d6b41a828b 699 {
<> 156:95d6b41a828b 700 status = HAL_ERROR;
<> 156:95d6b41a828b 701 }
<> 156:95d6b41a828b 702
<> 156:95d6b41a828b 703 /* Release Lock */
<> 156:95d6b41a828b 704 __HAL_UNLOCK(hdma);
<> 156:95d6b41a828b 705
<> 156:95d6b41a828b 706 return status;
<> 156:95d6b41a828b 707 }
<> 156:95d6b41a828b 708
<> 156:95d6b41a828b 709 /**
<> 156:95d6b41a828b 710 * @brief UnRegister callbacks
Anna Bridge 180:96ed750bd169 711 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 712 * the configuration information for the specified DMA Stream.
Anna Bridge 180:96ed750bd169 713 * @param CallbackID User Callback identifer
<> 156:95d6b41a828b 714 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
<> 156:95d6b41a828b 715 * @retval HAL status
<> 156:95d6b41a828b 716 */
<> 156:95d6b41a828b 717 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
<> 156:95d6b41a828b 718 {
<> 156:95d6b41a828b 719 HAL_StatusTypeDef status = HAL_OK;
<> 156:95d6b41a828b 720
<> 156:95d6b41a828b 721 /* Process locked */
<> 156:95d6b41a828b 722 __HAL_LOCK(hdma);
<> 156:95d6b41a828b 723
<> 156:95d6b41a828b 724 if(HAL_DMA_STATE_READY == hdma->State)
<> 156:95d6b41a828b 725 {
<> 156:95d6b41a828b 726 switch (CallbackID)
<> 156:95d6b41a828b 727 {
<> 156:95d6b41a828b 728 case HAL_DMA_XFER_CPLT_CB_ID:
<> 156:95d6b41a828b 729 hdma->XferCpltCallback = NULL;
<> 156:95d6b41a828b 730 break;
<> 156:95d6b41a828b 731
<> 156:95d6b41a828b 732 case HAL_DMA_XFER_HALFCPLT_CB_ID:
<> 156:95d6b41a828b 733 hdma->XferHalfCpltCallback = NULL;
<> 156:95d6b41a828b 734 break;
<> 156:95d6b41a828b 735
<> 156:95d6b41a828b 736 case HAL_DMA_XFER_ERROR_CB_ID:
<> 156:95d6b41a828b 737 hdma->XferErrorCallback = NULL;
<> 156:95d6b41a828b 738 break;
<> 156:95d6b41a828b 739
<> 156:95d6b41a828b 740 case HAL_DMA_XFER_ABORT_CB_ID:
<> 156:95d6b41a828b 741 hdma->XferAbortCallback = NULL;
<> 156:95d6b41a828b 742 break;
<> 156:95d6b41a828b 743
<> 156:95d6b41a828b 744 case HAL_DMA_XFER_ALL_CB_ID:
<> 156:95d6b41a828b 745 hdma->XferCpltCallback = NULL;
<> 156:95d6b41a828b 746 hdma->XferHalfCpltCallback = NULL;
<> 156:95d6b41a828b 747 hdma->XferErrorCallback = NULL;
<> 156:95d6b41a828b 748 hdma->XferAbortCallback = NULL;
<> 156:95d6b41a828b 749 break;
<> 156:95d6b41a828b 750
<> 156:95d6b41a828b 751 default:
<> 156:95d6b41a828b 752 status = HAL_ERROR;
<> 156:95d6b41a828b 753 break;
<> 156:95d6b41a828b 754 }
<> 156:95d6b41a828b 755 }
<> 156:95d6b41a828b 756 else
<> 156:95d6b41a828b 757 {
<> 156:95d6b41a828b 758 status = HAL_ERROR;
<> 156:95d6b41a828b 759 }
<> 156:95d6b41a828b 760
<> 156:95d6b41a828b 761 /* Release Lock */
<> 156:95d6b41a828b 762 __HAL_UNLOCK(hdma);
<> 156:95d6b41a828b 763
<> 156:95d6b41a828b 764 return status;
<> 156:95d6b41a828b 765 }
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 /**
<> 144:ef7eb2e8f9f7 768 * @}
<> 144:ef7eb2e8f9f7 769 */
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
<> 144:ef7eb2e8f9f7 772 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 773 *
<> 144:ef7eb2e8f9f7 774 @verbatim
<> 144:ef7eb2e8f9f7 775 ===============================================================================
<> 144:ef7eb2e8f9f7 776 ##### State and Errors functions #####
<> 144:ef7eb2e8f9f7 777 ===============================================================================
<> 144:ef7eb2e8f9f7 778 [..]
<> 144:ef7eb2e8f9f7 779 This subsection provides functions allowing to
<> 144:ef7eb2e8f9f7 780 (+) Check the DMA state
<> 144:ef7eb2e8f9f7 781 (+) Get error code
<> 144:ef7eb2e8f9f7 782
<> 144:ef7eb2e8f9f7 783 @endverbatim
<> 144:ef7eb2e8f9f7 784 * @{
<> 144:ef7eb2e8f9f7 785 */
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /**
<> 144:ef7eb2e8f9f7 788 * @brief Returns the DMA state.
Anna Bridge 180:96ed750bd169 789 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 790 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 791 * @retval HAL state
<> 144:ef7eb2e8f9f7 792 */
<> 144:ef7eb2e8f9f7 793 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 794 {
<> 144:ef7eb2e8f9f7 795 return hdma->State;
<> 144:ef7eb2e8f9f7 796 }
<> 144:ef7eb2e8f9f7 797
<> 144:ef7eb2e8f9f7 798 /**
<> 144:ef7eb2e8f9f7 799 * @brief Return the DMA error code
Anna Bridge 180:96ed750bd169 800 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 801 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 802 * @retval DMA Error Code
<> 144:ef7eb2e8f9f7 803 */
<> 144:ef7eb2e8f9f7 804 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 805 {
<> 144:ef7eb2e8f9f7 806 return hdma->ErrorCode;
<> 144:ef7eb2e8f9f7 807 }
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /**
<> 144:ef7eb2e8f9f7 810 * @}
<> 144:ef7eb2e8f9f7 811 */
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 /**
<> 144:ef7eb2e8f9f7 814 * @}
<> 144:ef7eb2e8f9f7 815 */
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 /** @addtogroup DMA_Private_Functions
<> 144:ef7eb2e8f9f7 818 * @{
<> 144:ef7eb2e8f9f7 819 */
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 /**
<> 156:95d6b41a828b 822 * @brief Set the DMA Transfer parameters.
Anna Bridge 180:96ed750bd169 823 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 824 * the configuration information for the specified DMA Channel.
Anna Bridge 180:96ed750bd169 825 * @param SrcAddress The source memory Buffer address
Anna Bridge 180:96ed750bd169 826 * @param DstAddress The destination memory Buffer address
Anna Bridge 180:96ed750bd169 827 * @param DataLength The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 828 * @retval HAL status
<> 144:ef7eb2e8f9f7 829 */
<> 144:ef7eb2e8f9f7 830 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 156:95d6b41a828b 831 {
<> 156:95d6b41a828b 832 /* Clear all flags */
<> 156:95d6b41a828b 833 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
<> 156:95d6b41a828b 834
<> 144:ef7eb2e8f9f7 835 /* Configure DMA Channel data length */
<> 144:ef7eb2e8f9f7 836 hdma->Instance->CNDTR = DataLength;
<> 144:ef7eb2e8f9f7 837
Anna Bridge 180:96ed750bd169 838 /* Memory to Peripheral */
<> 144:ef7eb2e8f9f7 839 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
<> 144:ef7eb2e8f9f7 840 {
<> 144:ef7eb2e8f9f7 841 /* Configure DMA Channel destination address */
<> 144:ef7eb2e8f9f7 842 hdma->Instance->CPAR = DstAddress;
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 /* Configure DMA Channel source address */
<> 144:ef7eb2e8f9f7 845 hdma->Instance->CMAR = SrcAddress;
<> 144:ef7eb2e8f9f7 846 }
Anna Bridge 180:96ed750bd169 847 /* Peripheral to Memory */
<> 144:ef7eb2e8f9f7 848 else
<> 144:ef7eb2e8f9f7 849 {
<> 144:ef7eb2e8f9f7 850 /* Configure DMA Channel source address */
<> 144:ef7eb2e8f9f7 851 hdma->Instance->CPAR = SrcAddress;
<> 144:ef7eb2e8f9f7 852
<> 144:ef7eb2e8f9f7 853 /* Configure DMA Channel destination address */
<> 144:ef7eb2e8f9f7 854 hdma->Instance->CMAR = DstAddress;
<> 144:ef7eb2e8f9f7 855 }
<> 144:ef7eb2e8f9f7 856 }
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /**
<> 156:95d6b41a828b 859 * @brief set the DMA base address and channel index depending on DMA instance
Anna Bridge 180:96ed750bd169 860 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 861 * the configuration information for the specified DMA Stream.
<> 156:95d6b41a828b 862 * @retval None
<> 156:95d6b41a828b 863 */
<> 156:95d6b41a828b 864 static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 865 {
<> 156:95d6b41a828b 866 #if defined (DMA2)
<> 156:95d6b41a828b 867 /* calculation of the channel index */
<> 156:95d6b41a828b 868 if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
<> 156:95d6b41a828b 869 {
<> 156:95d6b41a828b 870 /* DMA1 */
<> 156:95d6b41a828b 871 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
<> 156:95d6b41a828b 872 hdma->DmaBaseAddress = DMA1;
<> 156:95d6b41a828b 873 }
<> 156:95d6b41a828b 874 else
<> 156:95d6b41a828b 875 {
<> 156:95d6b41a828b 876 /* DMA2 */
<> 156:95d6b41a828b 877 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
<> 156:95d6b41a828b 878 hdma->DmaBaseAddress = DMA2;
<> 156:95d6b41a828b 879 }
<> 156:95d6b41a828b 880 #else
<> 156:95d6b41a828b 881 /* calculation of the channel index */
<> 156:95d6b41a828b 882 /* DMA1 */
<> 156:95d6b41a828b 883 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
<> 156:95d6b41a828b 884 hdma->DmaBaseAddress = DMA1;
<> 156:95d6b41a828b 885 #endif
<> 156:95d6b41a828b 886 }
<> 156:95d6b41a828b 887
<> 156:95d6b41a828b 888 /**
<> 144:ef7eb2e8f9f7 889 * @}
<> 144:ef7eb2e8f9f7 890 */
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892 /**
<> 144:ef7eb2e8f9f7 893 * @}
<> 144:ef7eb2e8f9f7 894 */
<> 144:ef7eb2e8f9f7 895 #endif /* HAL_DMA_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /**
<> 144:ef7eb2e8f9f7 898 * @}
<> 144:ef7eb2e8f9f7 899 */
<> 156:95d6b41a828b 900
<> 156:95d6b41a828b 901 /**
<> 156:95d6b41a828b 902 * @}
<> 156:95d6b41a828b 903 */
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/