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mbed library sources. Supersedes mbed-src.

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targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_dma.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.4.0
<> 144:ef7eb2e8f9f7 6 * @date 27-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief DMA HAL module driver.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 10 * functionalities of the Direct Memory Access (DMA) peripheral:
<> 144:ef7eb2e8f9f7 11 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 12 * + IO operation functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State and errors functions
<> 144:ef7eb2e8f9f7 14 @verbatim
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 [..]
<> 144:ef7eb2e8f9f7 19 (#) Enable and configure the peripheral to be connected to the DMA Channel
<> 144:ef7eb2e8f9f7 20 (except for internal SRAM / FLASH memories: no initialization is
<> 144:ef7eb2e8f9f7 21 necessary) please refer to Reference manual for connection between peripherals
<> 144:ef7eb2e8f9f7 22 and DMA requests .
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 (#) For a given Channel, program the required configuration through the following parameters:
<> 144:ef7eb2e8f9f7 25 Transfer Direction, Source and Destination data formats,
<> 144:ef7eb2e8f9f7 26 Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
<> 144:ef7eb2e8f9f7 27 using HAL_DMA_Init() function.
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
<> 144:ef7eb2e8f9f7 30 detection.
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 (#) Use HAL_DMA_Abort() function to abort the current transfer
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
<> 144:ef7eb2e8f9f7 35 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 36 =================================
<> 144:ef7eb2e8f9f7 37 [..]
<> 144:ef7eb2e8f9f7 38 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
<> 144:ef7eb2e8f9f7 39 address and destination address and the Length of data to be transferred
<> 144:ef7eb2e8f9f7 40 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
<> 144:ef7eb2e8f9f7 41 case a fixed Timeout can be configured by User depending from his application.
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 44 ===================================
<> 144:ef7eb2e8f9f7 45 [..]
<> 144:ef7eb2e8f9f7 46 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
<> 144:ef7eb2e8f9f7 47 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 48 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
<> 144:ef7eb2e8f9f7 49 Source address and destination address and the Length of data to be transferred.
<> 144:ef7eb2e8f9f7 50 In this case the DMA interrupt is configured
<> 144:ef7eb2e8f9f7 51 (+) Use HAL_DMAy_Channelx_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
<> 144:ef7eb2e8f9f7 52 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
<> 144:ef7eb2e8f9f7 53 add his own function by customization of function pointer XferCpltCallback and
<> 144:ef7eb2e8f9f7 54 XferErrorCallback (i.e a member of DMA handle structure).
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 *** DMA HAL driver macros list ***
<> 144:ef7eb2e8f9f7 57 =============================================
<> 144:ef7eb2e8f9f7 58 [..]
<> 144:ef7eb2e8f9f7 59 Below the list of most used macros in DMA HAL driver.
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
<> 144:ef7eb2e8f9f7 62 (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
<> 144:ef7eb2e8f9f7 63 (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
<> 144:ef7eb2e8f9f7 64 (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
<> 144:ef7eb2e8f9f7 65 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
<> 144:ef7eb2e8f9f7 66 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
<> 144:ef7eb2e8f9f7 67 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 [..]
<> 144:ef7eb2e8f9f7 70 (@) You can refer to the DMA HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 @endverbatim
<> 144:ef7eb2e8f9f7 73 ******************************************************************************
<> 144:ef7eb2e8f9f7 74 * @attention
<> 144:ef7eb2e8f9f7 75 *
<> 144:ef7eb2e8f9f7 76 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 77 *
<> 144:ef7eb2e8f9f7 78 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 79 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 80 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 81 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 82 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 83 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 84 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 85 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 86 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 87 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 88 *
<> 144:ef7eb2e8f9f7 89 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 90 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 91 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 92 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 93 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 94 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 95 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 96 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 97 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 98 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 99 *
<> 144:ef7eb2e8f9f7 100 ******************************************************************************
<> 144:ef7eb2e8f9f7 101 */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 104 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 107 * @{
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 #ifdef HAL_DMA_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /** @defgroup DMA DMA
<> 144:ef7eb2e8f9f7 113 * @brief DMA HAL module driver
<> 144:ef7eb2e8f9f7 114 * @{
<> 144:ef7eb2e8f9f7 115 */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 119 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 120 /** @defgroup DMA_Private_Constants DMA Private Constants
<> 144:ef7eb2e8f9f7 121 * @{
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123 #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
<> 144:ef7eb2e8f9f7 124 /**
<> 144:ef7eb2e8f9f7 125 * @}
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 129 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 130 /** @defgroup DMA_Private_Macros DMA Private Macros
<> 144:ef7eb2e8f9f7 131 * @{
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133 /**
<> 144:ef7eb2e8f9f7 134 * @}
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 137 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 138 /** @defgroup DMA_Private_Functions DMA Private Functions
<> 144:ef7eb2e8f9f7 139 * @{
<> 144:ef7eb2e8f9f7 140 */
<> 144:ef7eb2e8f9f7 141 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 142 /**
<> 144:ef7eb2e8f9f7 143 * @}
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /** @defgroup DMA_Exported_Functions DMA Exported Functions
<> 144:ef7eb2e8f9f7 149 * @{
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 153 * @brief Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 154 *
<> 144:ef7eb2e8f9f7 155 @verbatim
<> 144:ef7eb2e8f9f7 156 ===============================================================================
<> 144:ef7eb2e8f9f7 157 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 158 ===============================================================================
<> 144:ef7eb2e8f9f7 159 [..]
<> 144:ef7eb2e8f9f7 160 This section provides functions allowing to initialize the DMA Channel source
<> 144:ef7eb2e8f9f7 161 and destination addresses, incrementation and data sizes, transfer direction,
<> 144:ef7eb2e8f9f7 162 circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
<> 144:ef7eb2e8f9f7 163 [..]
<> 144:ef7eb2e8f9f7 164 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
<> 144:ef7eb2e8f9f7 165 reference manual.
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 @endverbatim
<> 144:ef7eb2e8f9f7 168 * @{
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /**
<> 144:ef7eb2e8f9f7 172 * @brief Initializes the DMA according to the specified
<> 144:ef7eb2e8f9f7 173 * parameters in the DMA_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 174 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 175 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 176 * @retval HAL status
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 179 {
<> 144:ef7eb2e8f9f7 180 uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /* Check the DMA handle allocation */
<> 144:ef7eb2e8f9f7 183 if(hdma == NULL)
<> 144:ef7eb2e8f9f7 184 {
<> 144:ef7eb2e8f9f7 185 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 186 }
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /* Check the parameters */
<> 144:ef7eb2e8f9f7 189 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
<> 144:ef7eb2e8f9f7 190 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
<> 144:ef7eb2e8f9f7 191 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
<> 144:ef7eb2e8f9f7 192 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
<> 144:ef7eb2e8f9f7 193 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
<> 144:ef7eb2e8f9f7 194 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
<> 144:ef7eb2e8f9f7 195 assert_param(IS_DMA_MODE(hdma->Init.Mode));
<> 144:ef7eb2e8f9f7 196 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 if(hdma->State == HAL_DMA_STATE_RESET)
<> 144:ef7eb2e8f9f7 199 {
<> 144:ef7eb2e8f9f7 200 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 201 hdma->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 202 }
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 205 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /* Get the CR register value */
<> 144:ef7eb2e8f9f7 208 tmp = hdma->Instance->CCR;
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
<> 144:ef7eb2e8f9f7 211 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
<> 144:ef7eb2e8f9f7 212 DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
<> 144:ef7eb2e8f9f7 213 DMA_CCR_DIR));
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /* Prepare the DMA Channel configuration */
<> 144:ef7eb2e8f9f7 216 tmp |= hdma->Init.Direction |
<> 144:ef7eb2e8f9f7 217 hdma->Init.PeriphInc | hdma->Init.MemInc |
<> 144:ef7eb2e8f9f7 218 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
<> 144:ef7eb2e8f9f7 219 hdma->Init.Mode | hdma->Init.Priority;
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /* Write to DMA Channel CR register */
<> 144:ef7eb2e8f9f7 222 hdma->Instance->CCR = tmp;
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /* Initialise the error code */
<> 144:ef7eb2e8f9f7 225 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /* Initialize the DMA state*/
<> 144:ef7eb2e8f9f7 228 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 return HAL_OK;
<> 144:ef7eb2e8f9f7 231 }
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /**
<> 144:ef7eb2e8f9f7 234 * @brief DeInitializes the DMA peripheral
<> 144:ef7eb2e8f9f7 235 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 236 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 237 * @retval HAL status
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 240 {
<> 144:ef7eb2e8f9f7 241 /* Check the DMA handle allocation */
<> 144:ef7eb2e8f9f7 242 if(hdma == NULL)
<> 144:ef7eb2e8f9f7 243 {
<> 144:ef7eb2e8f9f7 244 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 245 }
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /* Check the parameters */
<> 144:ef7eb2e8f9f7 248 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /* Disable the selected DMA Channelx */
<> 144:ef7eb2e8f9f7 251 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /* Reset DMA Channel control register */
<> 144:ef7eb2e8f9f7 254 hdma->Instance->CCR = 0;
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /* Reset DMA Channel Number of Data to Transfer register */
<> 144:ef7eb2e8f9f7 257 hdma->Instance->CNDTR = 0;
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /* Reset DMA Channel peripheral address register */
<> 144:ef7eb2e8f9f7 260 hdma->Instance->CPAR = 0;
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /* Reset DMA Channel memory address register */
<> 144:ef7eb2e8f9f7 263 hdma->Instance->CMAR = 0;
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /* Clear all flags */
<> 144:ef7eb2e8f9f7 266 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 267 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 268 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /* Initialize the error code */
<> 144:ef7eb2e8f9f7 271 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /* Initialize the DMA state */
<> 144:ef7eb2e8f9f7 274 hdma->State = HAL_DMA_STATE_RESET;
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /* Release Lock */
<> 144:ef7eb2e8f9f7 277 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 return HAL_OK;
<> 144:ef7eb2e8f9f7 280 }
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /**
<> 144:ef7eb2e8f9f7 283 * @}
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
<> 144:ef7eb2e8f9f7 287 * @brief I/O operation functions
<> 144:ef7eb2e8f9f7 288 *
<> 144:ef7eb2e8f9f7 289 @verbatim
<> 144:ef7eb2e8f9f7 290 ===============================================================================
<> 144:ef7eb2e8f9f7 291 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 292 ===============================================================================
<> 144:ef7eb2e8f9f7 293 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 294 (+) Configure the source, destination address and data length and Start DMA transfer
<> 144:ef7eb2e8f9f7 295 (+) Configure the source, destination address and data length and
<> 144:ef7eb2e8f9f7 296 Start DMA transfer with interrupt
<> 144:ef7eb2e8f9f7 297 (+) Abort DMA transfer
<> 144:ef7eb2e8f9f7 298 (+) Poll for transfer complete
<> 144:ef7eb2e8f9f7 299 (+) Handle DMA interrupt request
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 @endverbatim
<> 144:ef7eb2e8f9f7 302 * @{
<> 144:ef7eb2e8f9f7 303 */
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /**
<> 144:ef7eb2e8f9f7 306 * @brief Starts the DMA Transfer.
<> 144:ef7eb2e8f9f7 307 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 308 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 309 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 310 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 311 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 312 * @retval HAL status
<> 144:ef7eb2e8f9f7 313 */
<> 144:ef7eb2e8f9f7 314 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 315 {
<> 144:ef7eb2e8f9f7 316 /* Process locked */
<> 144:ef7eb2e8f9f7 317 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 320 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /* Check the parameters */
<> 144:ef7eb2e8f9f7 323 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /* Disable the peripheral */
<> 144:ef7eb2e8f9f7 326 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /* Configure the source, destination address and the data length */
<> 144:ef7eb2e8f9f7 329 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 332 __HAL_DMA_ENABLE(hdma);
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 return HAL_OK;
<> 144:ef7eb2e8f9f7 335 }
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /**
<> 144:ef7eb2e8f9f7 338 * @brief Start the DMA Transfer with interrupt enabled.
<> 144:ef7eb2e8f9f7 339 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 340 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 341 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 342 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 343 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 344 * @retval HAL status
<> 144:ef7eb2e8f9f7 345 */
<> 144:ef7eb2e8f9f7 346 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 347 {
<> 144:ef7eb2e8f9f7 348 /* Process locked */
<> 144:ef7eb2e8f9f7 349 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 352 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /* Check the parameters */
<> 144:ef7eb2e8f9f7 355 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /* Disable the peripheral */
<> 144:ef7eb2e8f9f7 358 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /* Configure the source, destination address and the data length */
<> 144:ef7eb2e8f9f7 361 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /* Enable the transfer complete interrupt */
<> 144:ef7eb2e8f9f7 364 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /* Enable the Half transfer complete interrupt */
<> 144:ef7eb2e8f9f7 367 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /* Enable the transfer Error interrupt */
<> 144:ef7eb2e8f9f7 370 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 373 __HAL_DMA_ENABLE(hdma);
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 return HAL_OK;
<> 144:ef7eb2e8f9f7 376 }
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /**
<> 144:ef7eb2e8f9f7 379 * @brief Aborts the DMA Transfer.
<> 144:ef7eb2e8f9f7 380 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 381 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 382 *
<> 144:ef7eb2e8f9f7 383 * @note After disabling a DMA Channel, a check for wait until the DMA Channel is
<> 144:ef7eb2e8f9f7 384 * effectively disabled is added. If a Channel is disabled
<> 144:ef7eb2e8f9f7 385 * while a data transfer is ongoing, the current data will be transferred
<> 144:ef7eb2e8f9f7 386 * and the Channel will be effectively disabled only after the transfer of
<> 144:ef7eb2e8f9f7 387 * this single data is finished.
<> 144:ef7eb2e8f9f7 388 * @retval HAL status
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 391 {
<> 144:ef7eb2e8f9f7 392 uint32_t tickstart = 0x00;
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /* Disable the channel */
<> 144:ef7eb2e8f9f7 395 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /* Get tick */
<> 144:ef7eb2e8f9f7 398 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /* Check if the DMA Channel is effectively disabled */
<> 144:ef7eb2e8f9f7 401 while((hdma->Instance->CCR & DMA_CCR_EN) != 0)
<> 144:ef7eb2e8f9f7 402 {
<> 144:ef7eb2e8f9f7 403 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 404 if((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
<> 144:ef7eb2e8f9f7 405 {
<> 144:ef7eb2e8f9f7 406 /* Update error code */
<> 144:ef7eb2e8f9f7 407 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 410 hdma->State = HAL_DMA_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 413 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 416 }
<> 144:ef7eb2e8f9f7 417 }
<> 144:ef7eb2e8f9f7 418 /* Change the DMA state*/
<> 144:ef7eb2e8f9f7 419 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 422 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 return HAL_OK;
<> 144:ef7eb2e8f9f7 425 }
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /**
<> 144:ef7eb2e8f9f7 428 * @brief Aborts the DMA Transfer in Interrupt mode.
<> 144:ef7eb2e8f9f7 429 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 430 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 431 * @retval HAL status
<> 144:ef7eb2e8f9f7 432 */
<> 144:ef7eb2e8f9f7 433 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 434 {
<> 144:ef7eb2e8f9f7 435 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 if(HAL_DMA_STATE_BUSY != hdma->State)
<> 144:ef7eb2e8f9f7 438 {
<> 144:ef7eb2e8f9f7 439 /* no transfer ongoing */
<> 144:ef7eb2e8f9f7 440 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 443 }
<> 144:ef7eb2e8f9f7 444 else
<> 144:ef7eb2e8f9f7 445 {
<> 144:ef7eb2e8f9f7 446 /* Disable DMA IT */
<> 144:ef7eb2e8f9f7 447 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /* Disable the channel */
<> 144:ef7eb2e8f9f7 450 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /* Clear all flags */
<> 144:ef7eb2e8f9f7 453 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 456 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 459 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /* Call User Abort callback */
<> 144:ef7eb2e8f9f7 462 if(hdma->XferAbortCallback != NULL)
<> 144:ef7eb2e8f9f7 463 {
<> 144:ef7eb2e8f9f7 464 hdma->XferAbortCallback(hdma);
<> 144:ef7eb2e8f9f7 465 }
<> 144:ef7eb2e8f9f7 466 }
<> 144:ef7eb2e8f9f7 467 return status;
<> 144:ef7eb2e8f9f7 468 }
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /**
<> 144:ef7eb2e8f9f7 471 * @brief Polling for transfer complete.
<> 144:ef7eb2e8f9f7 472 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 473 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 474 * @param CompleteLevel: Specifies the DMA level complete.
<> 144:ef7eb2e8f9f7 475 * @param Timeout: Timeout duration.
<> 144:ef7eb2e8f9f7 476 * @retval HAL status
<> 144:ef7eb2e8f9f7 477 */
<> 144:ef7eb2e8f9f7 478 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 479 {
<> 144:ef7eb2e8f9f7 480 uint32_t temp;
<> 144:ef7eb2e8f9f7 481 uint32_t tickstart = 0x00;
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 /* Get the level transfer complete flag */
<> 144:ef7eb2e8f9f7 484 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
<> 144:ef7eb2e8f9f7 485 {
<> 144:ef7eb2e8f9f7 486 /* Transfer Complete flag */
<> 144:ef7eb2e8f9f7 487 temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
<> 144:ef7eb2e8f9f7 488 }
<> 144:ef7eb2e8f9f7 489 else
<> 144:ef7eb2e8f9f7 490 {
<> 144:ef7eb2e8f9f7 491 /* Half Transfer Complete flag */
<> 144:ef7eb2e8f9f7 492 temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
<> 144:ef7eb2e8f9f7 493 }
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /* Get tick */
<> 144:ef7eb2e8f9f7 496 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
<> 144:ef7eb2e8f9f7 499 {
<> 144:ef7eb2e8f9f7 500 if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
<> 144:ef7eb2e8f9f7 501 {
<> 144:ef7eb2e8f9f7 502 /* Clear the transfer error flags */
<> 144:ef7eb2e8f9f7 503 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /* Update error code */
<> 144:ef7eb2e8f9f7 506 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 509 hdma->State= HAL_DMA_STATE_ERROR;
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 512 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 515 }
<> 144:ef7eb2e8f9f7 516 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 517 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 518 {
<> 144:ef7eb2e8f9f7 519 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 520 {
<> 144:ef7eb2e8f9f7 521 /* Update error code */
<> 144:ef7eb2e8f9f7 522 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 525 hdma->State = HAL_DMA_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 528 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 531 }
<> 144:ef7eb2e8f9f7 532 }
<> 144:ef7eb2e8f9f7 533 }
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
<> 144:ef7eb2e8f9f7 536 {
<> 144:ef7eb2e8f9f7 537 /* Clear the transfer complete flag */
<> 144:ef7eb2e8f9f7 538 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /* The selected Channelx EN bit is cleared (DMA is disabled and
<> 144:ef7eb2e8f9f7 541 all transfers are complete) */
<> 144:ef7eb2e8f9f7 542 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 }
<> 144:ef7eb2e8f9f7 545 else
<> 144:ef7eb2e8f9f7 546 {
<> 144:ef7eb2e8f9f7 547 /* Clear the half transfer complete flag */
<> 144:ef7eb2e8f9f7 548 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /* The selected Channelx EN bit is cleared (DMA is disabled and
<> 144:ef7eb2e8f9f7 551 all transfers of half buffer are complete) */
<> 144:ef7eb2e8f9f7 552 hdma->State = HAL_DMA_STATE_READY_HALF;
<> 144:ef7eb2e8f9f7 553 }
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /* Process unlocked */
<> 144:ef7eb2e8f9f7 556 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 return HAL_OK;
<> 144:ef7eb2e8f9f7 559 }
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /**
<> 144:ef7eb2e8f9f7 562 * @brief Handles DMA interrupt request.
<> 144:ef7eb2e8f9f7 563 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 564 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 565 * @retval None
<> 144:ef7eb2e8f9f7 566 */
<> 144:ef7eb2e8f9f7 567 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 568 {
<> 144:ef7eb2e8f9f7 569 /* Transfer Error Interrupt management ***************************************/
<> 144:ef7eb2e8f9f7 570 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
<> 144:ef7eb2e8f9f7 571 {
<> 144:ef7eb2e8f9f7 572 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
<> 144:ef7eb2e8f9f7 573 {
<> 144:ef7eb2e8f9f7 574 /* Disable the transfer error interrupt */
<> 144:ef7eb2e8f9f7 575 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /* Clear the transfer error flag */
<> 144:ef7eb2e8f9f7 578 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /* Update error code */
<> 144:ef7eb2e8f9f7 581 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 584 hdma->State = HAL_DMA_STATE_ERROR;
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 587 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 if(hdma->XferErrorCallback != NULL)
<> 144:ef7eb2e8f9f7 590 {
<> 144:ef7eb2e8f9f7 591 /* Transfer error callback */
<> 144:ef7eb2e8f9f7 592 hdma->XferErrorCallback(hdma);
<> 144:ef7eb2e8f9f7 593 }
<> 144:ef7eb2e8f9f7 594 }
<> 144:ef7eb2e8f9f7 595 }
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 /* Half Transfer Complete Interrupt management ******************************/
<> 144:ef7eb2e8f9f7 598 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
<> 144:ef7eb2e8f9f7 599 {
<> 144:ef7eb2e8f9f7 600 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
<> 144:ef7eb2e8f9f7 601 {
<> 144:ef7eb2e8f9f7 602 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
<> 144:ef7eb2e8f9f7 603 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
<> 144:ef7eb2e8f9f7 604 {
<> 144:ef7eb2e8f9f7 605 /* Disable the half transfer interrupt */
<> 144:ef7eb2e8f9f7 606 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
<> 144:ef7eb2e8f9f7 607 }
<> 144:ef7eb2e8f9f7 608 /* Clear the half transfer complete flag */
<> 144:ef7eb2e8f9f7 609 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 612 hdma->State = HAL_DMA_STATE_READY_HALF;
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 if(hdma->XferHalfCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 615 {
<> 144:ef7eb2e8f9f7 616 /* Half transfer callback */
<> 144:ef7eb2e8f9f7 617 hdma->XferHalfCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 618 }
<> 144:ef7eb2e8f9f7 619 }
<> 144:ef7eb2e8f9f7 620 }
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /* Transfer Complete Interrupt management ***********************************/
<> 144:ef7eb2e8f9f7 623 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
<> 144:ef7eb2e8f9f7 624 {
<> 144:ef7eb2e8f9f7 625 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
<> 144:ef7eb2e8f9f7 626 {
<> 144:ef7eb2e8f9f7 627 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
<> 144:ef7eb2e8f9f7 628 {
<> 144:ef7eb2e8f9f7 629 /* Disable the transfer complete interrupt */
<> 144:ef7eb2e8f9f7 630 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
<> 144:ef7eb2e8f9f7 631 }
<> 144:ef7eb2e8f9f7 632 /* Clear the transfer complete flag */
<> 144:ef7eb2e8f9f7 633 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /* Update error code */
<> 144:ef7eb2e8f9f7 636 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_NONE);
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 639 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 642 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 if(hdma->XferCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 645 {
<> 144:ef7eb2e8f9f7 646 /* Transfer complete callback */
<> 144:ef7eb2e8f9f7 647 hdma->XferCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 648 }
<> 144:ef7eb2e8f9f7 649 }
<> 144:ef7eb2e8f9f7 650 }
<> 144:ef7eb2e8f9f7 651 }
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 /**
<> 144:ef7eb2e8f9f7 654 * @}
<> 144:ef7eb2e8f9f7 655 */
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
<> 144:ef7eb2e8f9f7 658 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 659 *
<> 144:ef7eb2e8f9f7 660 @verbatim
<> 144:ef7eb2e8f9f7 661 ===============================================================================
<> 144:ef7eb2e8f9f7 662 ##### State and Errors functions #####
<> 144:ef7eb2e8f9f7 663 ===============================================================================
<> 144:ef7eb2e8f9f7 664 [..]
<> 144:ef7eb2e8f9f7 665 This subsection provides functions allowing to
<> 144:ef7eb2e8f9f7 666 (+) Check the DMA state
<> 144:ef7eb2e8f9f7 667 (+) Get error code
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 @endverbatim
<> 144:ef7eb2e8f9f7 670 * @{
<> 144:ef7eb2e8f9f7 671 */
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 /**
<> 144:ef7eb2e8f9f7 674 * @brief Returns the DMA state.
<> 144:ef7eb2e8f9f7 675 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 676 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 677 * @retval HAL state
<> 144:ef7eb2e8f9f7 678 */
<> 144:ef7eb2e8f9f7 679 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 680 {
<> 144:ef7eb2e8f9f7 681 return hdma->State;
<> 144:ef7eb2e8f9f7 682 }
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 /**
<> 144:ef7eb2e8f9f7 685 * @brief Return the DMA error code
<> 144:ef7eb2e8f9f7 686 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 687 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 688 * @retval DMA Error Code
<> 144:ef7eb2e8f9f7 689 */
<> 144:ef7eb2e8f9f7 690 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 691 {
<> 144:ef7eb2e8f9f7 692 return hdma->ErrorCode;
<> 144:ef7eb2e8f9f7 693 }
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /**
<> 144:ef7eb2e8f9f7 696 * @}
<> 144:ef7eb2e8f9f7 697 */
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /**
<> 144:ef7eb2e8f9f7 700 * @}
<> 144:ef7eb2e8f9f7 701 */
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /** @addtogroup DMA_Private_Functions
<> 144:ef7eb2e8f9f7 704 * @{
<> 144:ef7eb2e8f9f7 705 */
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 /**
<> 144:ef7eb2e8f9f7 708 * @brief Sets the DMA Transfer parameter.
<> 144:ef7eb2e8f9f7 709 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 710 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 711 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 712 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 713 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 714 * @retval HAL status
<> 144:ef7eb2e8f9f7 715 */
<> 144:ef7eb2e8f9f7 716 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 717 {
<> 144:ef7eb2e8f9f7 718 /* Configure DMA Channel data length */
<> 144:ef7eb2e8f9f7 719 hdma->Instance->CNDTR = DataLength;
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /* Peripheral to Memory */
<> 144:ef7eb2e8f9f7 722 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
<> 144:ef7eb2e8f9f7 723 {
<> 144:ef7eb2e8f9f7 724 /* Configure DMA Channel destination address */
<> 144:ef7eb2e8f9f7 725 hdma->Instance->CPAR = DstAddress;
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 /* Configure DMA Channel source address */
<> 144:ef7eb2e8f9f7 728 hdma->Instance->CMAR = SrcAddress;
<> 144:ef7eb2e8f9f7 729 }
<> 144:ef7eb2e8f9f7 730 /* Memory to Peripheral */
<> 144:ef7eb2e8f9f7 731 else
<> 144:ef7eb2e8f9f7 732 {
<> 144:ef7eb2e8f9f7 733 /* Configure DMA Channel source address */
<> 144:ef7eb2e8f9f7 734 hdma->Instance->CPAR = SrcAddress;
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 /* Configure DMA Channel destination address */
<> 144:ef7eb2e8f9f7 737 hdma->Instance->CMAR = DstAddress;
<> 144:ef7eb2e8f9f7 738 }
<> 144:ef7eb2e8f9f7 739 }
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 /**
<> 144:ef7eb2e8f9f7 742 * @}
<> 144:ef7eb2e8f9f7 743 */
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 /**
<> 144:ef7eb2e8f9f7 746 * @}
<> 144:ef7eb2e8f9f7 747 */
<> 144:ef7eb2e8f9f7 748 #endif /* HAL_DMA_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /**
<> 144:ef7eb2e8f9f7 751 * @}
<> 144:ef7eb2e8f9f7 752 */
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/