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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.c@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 15:03:32 2017 +0000
Revision:
156:95d6b41a828b
Parent:
149:156823d33999
Child:
180:96ed750bd169
This updates the lib to the mbed lib v134

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_dma.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.5.0
<> 156:95d6b41a828b 6 * @date 04-November-2016
<> 144:ef7eb2e8f9f7 7 * @brief DMA HAL module driver.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 10 * functionalities of the Direct Memory Access (DMA) peripheral:
<> 144:ef7eb2e8f9f7 11 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 12 * + IO operation functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State and errors functions
<> 144:ef7eb2e8f9f7 14 @verbatim
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 [..]
<> 144:ef7eb2e8f9f7 19 (#) Enable and configure the peripheral to be connected to the DMA Channel
<> 144:ef7eb2e8f9f7 20 (except for internal SRAM / FLASH memories: no initialization is
<> 156:95d6b41a828b 21 necessary). Please refer to Reference manual for connection between peripherals
<> 144:ef7eb2e8f9f7 22 and DMA requests .
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 (#) For a given Channel, program the required configuration through the following parameters:
<> 144:ef7eb2e8f9f7 25 Transfer Direction, Source and Destination data formats,
<> 144:ef7eb2e8f9f7 26 Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
<> 144:ef7eb2e8f9f7 27 using HAL_DMA_Init() function.
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
<> 144:ef7eb2e8f9f7 30 detection.
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 (#) Use HAL_DMA_Abort() function to abort the current transfer
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
<> 144:ef7eb2e8f9f7 35 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 36 =================================
<> 144:ef7eb2e8f9f7 37 [..]
<> 144:ef7eb2e8f9f7 38 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
<> 144:ef7eb2e8f9f7 39 address and destination address and the Length of data to be transferred
<> 144:ef7eb2e8f9f7 40 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
<> 144:ef7eb2e8f9f7 41 case a fixed Timeout can be configured by User depending from his application.
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 44 ===================================
<> 144:ef7eb2e8f9f7 45 [..]
<> 144:ef7eb2e8f9f7 46 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
<> 144:ef7eb2e8f9f7 47 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 48 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
<> 144:ef7eb2e8f9f7 49 Source address and destination address and the Length of data to be transferred.
<> 144:ef7eb2e8f9f7 50 In this case the DMA interrupt is configured
<> 156:95d6b41a828b 51 (+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
<> 144:ef7eb2e8f9f7 52 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
<> 144:ef7eb2e8f9f7 53 add his own function by customization of function pointer XferCpltCallback and
<> 144:ef7eb2e8f9f7 54 XferErrorCallback (i.e a member of DMA handle structure).
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 *** DMA HAL driver macros list ***
<> 144:ef7eb2e8f9f7 57 =============================================
<> 144:ef7eb2e8f9f7 58 [..]
<> 144:ef7eb2e8f9f7 59 Below the list of most used macros in DMA HAL driver.
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 [..]
<> 144:ef7eb2e8f9f7 62 (@) You can refer to the DMA HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 @endverbatim
<> 144:ef7eb2e8f9f7 65 ******************************************************************************
<> 144:ef7eb2e8f9f7 66 * @attention
<> 144:ef7eb2e8f9f7 67 *
<> 144:ef7eb2e8f9f7 68 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 69 *
<> 144:ef7eb2e8f9f7 70 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 71 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 72 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 73 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 74 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 75 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 76 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 77 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 78 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 79 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 80 *
<> 144:ef7eb2e8f9f7 81 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 82 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 83 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 84 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 85 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 86 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 87 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 88 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 89 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 90 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 91 *
<> 144:ef7eb2e8f9f7 92 ******************************************************************************
<> 144:ef7eb2e8f9f7 93 */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 96 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 99 * @{
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /** @defgroup DMA DMA
<> 144:ef7eb2e8f9f7 104 * @brief DMA HAL module driver
<> 144:ef7eb2e8f9f7 105 * @{
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107
<> 156:95d6b41a828b 108 #ifdef HAL_DMA_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 111 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 112 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 113 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 114 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 115 /** @defgroup DMA_Private_Functions DMA Private Functions
<> 144:ef7eb2e8f9f7 116 * @{
<> 144:ef7eb2e8f9f7 117 */
<> 144:ef7eb2e8f9f7 118 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 156:95d6b41a828b 119 static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 120 /**
<> 144:ef7eb2e8f9f7 121 * @}
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /** @defgroup DMA_Exported_Functions DMA Exported Functions
<> 144:ef7eb2e8f9f7 127 * @{
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 131 * @brief Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 132 *
<> 144:ef7eb2e8f9f7 133 @verbatim
<> 144:ef7eb2e8f9f7 134 ===============================================================================
<> 144:ef7eb2e8f9f7 135 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 136 ===============================================================================
<> 144:ef7eb2e8f9f7 137 [..]
<> 144:ef7eb2e8f9f7 138 This section provides functions allowing to initialize the DMA Channel source
<> 144:ef7eb2e8f9f7 139 and destination addresses, incrementation and data sizes, transfer direction,
<> 144:ef7eb2e8f9f7 140 circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
<> 144:ef7eb2e8f9f7 141 [..]
<> 144:ef7eb2e8f9f7 142 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
<> 144:ef7eb2e8f9f7 143 reference manual.
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 @endverbatim
<> 144:ef7eb2e8f9f7 146 * @{
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /**
<> 156:95d6b41a828b 150 * @brief Initialize the DMA according to the specified
<> 156:95d6b41a828b 151 * parameters in the DMA_InitTypeDef and initialize the associated handle.
<> 144:ef7eb2e8f9f7 152 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 153 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 154 * @retval HAL status
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 157 {
<> 156:95d6b41a828b 158 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* Check the DMA handle allocation */
<> 156:95d6b41a828b 161 if(NULL == hdma)
<> 144:ef7eb2e8f9f7 162 {
<> 144:ef7eb2e8f9f7 163 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 164 }
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /* Check the parameters */
<> 144:ef7eb2e8f9f7 167 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
<> 144:ef7eb2e8f9f7 168 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
<> 144:ef7eb2e8f9f7 169 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
<> 144:ef7eb2e8f9f7 170 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
<> 144:ef7eb2e8f9f7 171 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
<> 144:ef7eb2e8f9f7 172 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
<> 144:ef7eb2e8f9f7 173 assert_param(IS_DMA_MODE(hdma->Init.Mode));
<> 144:ef7eb2e8f9f7 174 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 177 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /* Get the CR register value */
<> 144:ef7eb2e8f9f7 180 tmp = hdma->Instance->CCR;
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
<> 144:ef7eb2e8f9f7 183 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
<> 144:ef7eb2e8f9f7 184 DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
<> 144:ef7eb2e8f9f7 185 DMA_CCR_DIR));
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /* Prepare the DMA Channel configuration */
<> 144:ef7eb2e8f9f7 188 tmp |= hdma->Init.Direction |
<> 144:ef7eb2e8f9f7 189 hdma->Init.PeriphInc | hdma->Init.MemInc |
<> 144:ef7eb2e8f9f7 190 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
<> 144:ef7eb2e8f9f7 191 hdma->Init.Mode | hdma->Init.Priority;
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /* Write to DMA Channel CR register */
<> 144:ef7eb2e8f9f7 194 hdma->Instance->CCR = tmp;
<> 144:ef7eb2e8f9f7 195
<> 156:95d6b41a828b 196 /* Initialize DmaBaseAddress and ChannelIndex parameters used
<> 156:95d6b41a828b 197 by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
<> 156:95d6b41a828b 198 DMA_CalcBaseAndBitshift(hdma);
<> 156:95d6b41a828b 199
<> 156:95d6b41a828b 200 /* Clean callbacks */
<> 156:95d6b41a828b 201 hdma->XferCpltCallback = NULL;
<> 156:95d6b41a828b 202 hdma->XferHalfCpltCallback = NULL;
<> 156:95d6b41a828b 203 hdma->XferErrorCallback = NULL;
<> 156:95d6b41a828b 204 hdma->XferAbortCallback = NULL;
<> 156:95d6b41a828b 205
<> 144:ef7eb2e8f9f7 206 /* Initialise the error code */
<> 144:ef7eb2e8f9f7 207 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /* Initialize the DMA state*/
<> 156:95d6b41a828b 210 hdma->State = HAL_DMA_STATE_READY;
<> 156:95d6b41a828b 211
<> 156:95d6b41a828b 212 /* Allocate lock resource and initialize it */
<> 156:95d6b41a828b 213 hdma->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 return HAL_OK;
<> 144:ef7eb2e8f9f7 216 }
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /**
<> 156:95d6b41a828b 219 * @brief DeInitialize the DMA peripheral
<> 144:ef7eb2e8f9f7 220 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 221 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 222 * @retval HAL status
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 225 {
<> 144:ef7eb2e8f9f7 226 /* Check the DMA handle allocation */
<> 156:95d6b41a828b 227 if(NULL == hdma)
<> 144:ef7eb2e8f9f7 228 {
<> 144:ef7eb2e8f9f7 229 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 230 }
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /* Check the parameters */
<> 144:ef7eb2e8f9f7 233 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /* Disable the selected DMA Channelx */
<> 156:95d6b41a828b 236 hdma->Instance->CCR &= ~DMA_CCR_EN;
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /* Reset DMA Channel control register */
<> 156:95d6b41a828b 239 hdma->Instance->CCR = 0U;
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /* Reset DMA Channel Number of Data to Transfer register */
<> 156:95d6b41a828b 242 hdma->Instance->CNDTR = 0U;
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /* Reset DMA Channel peripheral address register */
<> 156:95d6b41a828b 245 hdma->Instance->CPAR = 0U;
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /* Reset DMA Channel memory address register */
<> 156:95d6b41a828b 248 hdma->Instance->CMAR = 0U;
<> 156:95d6b41a828b 249
<> 156:95d6b41a828b 250 /* Get DMA Base Address */
<> 156:95d6b41a828b 251 DMA_CalcBaseAndBitshift(hdma);
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /* Clear all flags */
<> 156:95d6b41a828b 254 hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /* Initialize the error code */
<> 144:ef7eb2e8f9f7 257 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /* Initialize the DMA state */
<> 144:ef7eb2e8f9f7 260 hdma->State = HAL_DMA_STATE_RESET;
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /* Release Lock */
<> 144:ef7eb2e8f9f7 263 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 return HAL_OK;
<> 144:ef7eb2e8f9f7 266 }
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /**
<> 144:ef7eb2e8f9f7 269 * @}
<> 144:ef7eb2e8f9f7 270 */
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
<> 144:ef7eb2e8f9f7 273 * @brief I/O operation functions
<> 144:ef7eb2e8f9f7 274 *
<> 144:ef7eb2e8f9f7 275 @verbatim
<> 144:ef7eb2e8f9f7 276 ===============================================================================
<> 144:ef7eb2e8f9f7 277 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 278 ===============================================================================
<> 144:ef7eb2e8f9f7 279 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 280 (+) Configure the source, destination address and data length and Start DMA transfer
<> 144:ef7eb2e8f9f7 281 (+) Configure the source, destination address and data length and
<> 144:ef7eb2e8f9f7 282 Start DMA transfer with interrupt
<> 144:ef7eb2e8f9f7 283 (+) Abort DMA transfer
<> 144:ef7eb2e8f9f7 284 (+) Poll for transfer complete
<> 144:ef7eb2e8f9f7 285 (+) Handle DMA interrupt request
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 @endverbatim
<> 144:ef7eb2e8f9f7 288 * @{
<> 144:ef7eb2e8f9f7 289 */
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /**
<> 156:95d6b41a828b 292 * @brief Start the DMA Transfer.
<> 144:ef7eb2e8f9f7 293 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 294 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 295 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 296 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 297 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 298 * @retval HAL status
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 156:95d6b41a828b 301 {
<> 156:95d6b41a828b 302 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 303
<> 156:95d6b41a828b 304 /* Check the parameters */
<> 144:ef7eb2e8f9f7 305 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 306
<> 156:95d6b41a828b 307 /* Process locked */
<> 156:95d6b41a828b 308 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 309
<> 156:95d6b41a828b 310 if(HAL_DMA_STATE_READY == hdma->State)
<> 156:95d6b41a828b 311 {
<> 156:95d6b41a828b 312 /* Change DMA peripheral state */
<> 156:95d6b41a828b 313 hdma->State = HAL_DMA_STATE_BUSY;
<> 156:95d6b41a828b 314
<> 156:95d6b41a828b 315 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 156:95d6b41a828b 316
<> 156:95d6b41a828b 317 /* Disable the peripheral */
<> 156:95d6b41a828b 318 hdma->Instance->CCR &= ~DMA_CCR_EN;
<> 156:95d6b41a828b 319
<> 156:95d6b41a828b 320 /* Configure the source, destination address and the data length */
<> 156:95d6b41a828b 321 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 156:95d6b41a828b 322
<> 156:95d6b41a828b 323 /* Enable the Peripheral */
<> 156:95d6b41a828b 324 hdma->Instance->CCR |= DMA_CCR_EN;
<> 156:95d6b41a828b 325 }
<> 156:95d6b41a828b 326 else
<> 156:95d6b41a828b 327 {
<> 156:95d6b41a828b 328 /* Process Unlocked */
<> 156:95d6b41a828b 329 __HAL_UNLOCK(hdma);
<> 156:95d6b41a828b 330
<> 156:95d6b41a828b 331 /* Remain BUSY */
<> 156:95d6b41a828b 332 status = HAL_BUSY;
<> 156:95d6b41a828b 333 }
<> 144:ef7eb2e8f9f7 334
<> 156:95d6b41a828b 335 return status;
<> 144:ef7eb2e8f9f7 336 }
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /**
<> 144:ef7eb2e8f9f7 339 * @brief Start the DMA Transfer with interrupt enabled.
<> 144:ef7eb2e8f9f7 340 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 341 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 342 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 343 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 344 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 345 * @retval HAL status
<> 144:ef7eb2e8f9f7 346 */
<> 144:ef7eb2e8f9f7 347 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 348 {
<> 156:95d6b41a828b 349 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 350
<> 156:95d6b41a828b 351 /* Check the parameters */
<> 144:ef7eb2e8f9f7 352 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 353
<> 156:95d6b41a828b 354 /* Process locked */
<> 156:95d6b41a828b 355 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 356
<> 156:95d6b41a828b 357 if(HAL_DMA_STATE_READY == hdma->State)
<> 156:95d6b41a828b 358 {
<> 156:95d6b41a828b 359 /* Change DMA peripheral state */
<> 156:95d6b41a828b 360 hdma->State = HAL_DMA_STATE_BUSY;
<> 156:95d6b41a828b 361
<> 156:95d6b41a828b 362 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 156:95d6b41a828b 363
<> 156:95d6b41a828b 364 /* Disable the peripheral */
<> 156:95d6b41a828b 365 hdma->Instance->CCR &= ~DMA_CCR_EN;
<> 156:95d6b41a828b 366
<> 156:95d6b41a828b 367 /* Configure the source, destination address and the data length */
<> 156:95d6b41a828b 368 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 156:95d6b41a828b 369
<> 156:95d6b41a828b 370 /* Enable the transfer complete, & transfer error interrupts */
<> 156:95d6b41a828b 371 /* Half transfer interrupt is optional: enable it only if associated callback is available */
<> 156:95d6b41a828b 372 if(NULL != hdma->XferHalfCpltCallback )
<> 156:95d6b41a828b 373 {
<> 156:95d6b41a828b 374 hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
<> 156:95d6b41a828b 375 }
<> 156:95d6b41a828b 376 else
<> 156:95d6b41a828b 377 {
<> 156:95d6b41a828b 378 hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE);
<> 156:95d6b41a828b 379 hdma->Instance->CCR &= ~DMA_IT_HT;
<> 156:95d6b41a828b 380 }
<> 156:95d6b41a828b 381
<> 156:95d6b41a828b 382 /* Enable the Peripheral */
<> 156:95d6b41a828b 383 hdma->Instance->CCR |= DMA_CCR_EN;
<> 156:95d6b41a828b 384 }
<> 156:95d6b41a828b 385 else
<> 156:95d6b41a828b 386 {
<> 156:95d6b41a828b 387 /* Process Unlocked */
<> 156:95d6b41a828b 388 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 389
<> 156:95d6b41a828b 390 /* Remain BUSY */
<> 156:95d6b41a828b 391 status = HAL_BUSY;
<> 156:95d6b41a828b 392 }
<> 144:ef7eb2e8f9f7 393
<> 156:95d6b41a828b 394 return status;
<> 144:ef7eb2e8f9f7 395 }
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /**
<> 156:95d6b41a828b 398 * @brief Abort the DMA Transfer.
<> 144:ef7eb2e8f9f7 399 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 400 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 401 * @retval HAL status
<> 144:ef7eb2e8f9f7 402 */
<> 144:ef7eb2e8f9f7 403 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 404 {
<> 156:95d6b41a828b 405 /* Disable DMA IT */
<> 156:95d6b41a828b 406 hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
<> 156:95d6b41a828b 407
<> 156:95d6b41a828b 408 /* Disable the channel */
<> 156:95d6b41a828b 409 hdma->Instance->CCR &= ~DMA_CCR_EN;
<> 156:95d6b41a828b 410
<> 156:95d6b41a828b 411 /* Clear all flags */
<> 156:95d6b41a828b 412 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
<> 156:95d6b41a828b 413
<> 156:95d6b41a828b 414 /* Change the DMA state*/
<> 156:95d6b41a828b 415 hdma->State = HAL_DMA_STATE_READY;
<> 156:95d6b41a828b 416
<> 156:95d6b41a828b 417 /* Process Unlocked */
<> 156:95d6b41a828b 418 __HAL_UNLOCK(hdma);
<> 156:95d6b41a828b 419
<> 156:95d6b41a828b 420 return HAL_OK;
<> 144:ef7eb2e8f9f7 421 }
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /**
<> 156:95d6b41a828b 424 * @brief Abort the DMA Transfer in Interrupt mode.
<> 144:ef7eb2e8f9f7 425 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 426 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 427 * @retval HAL status
<> 144:ef7eb2e8f9f7 428 */
<> 144:ef7eb2e8f9f7 429 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 430 {
<> 144:ef7eb2e8f9f7 431 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 if(HAL_DMA_STATE_BUSY != hdma->State)
<> 144:ef7eb2e8f9f7 434 {
<> 144:ef7eb2e8f9f7 435 /* no transfer ongoing */
<> 144:ef7eb2e8f9f7 436 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 439 }
<> 144:ef7eb2e8f9f7 440 else
<> 144:ef7eb2e8f9f7 441 {
<> 156:95d6b41a828b 442
<> 144:ef7eb2e8f9f7 443 /* Disable DMA IT */
<> 156:95d6b41a828b 444 hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /* Disable the channel */
<> 156:95d6b41a828b 447 hdma->Instance->CCR &= ~DMA_CCR_EN;
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /* Clear all flags */
<> 156:95d6b41a828b 450 hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 453 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 456 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /* Call User Abort callback */
<> 144:ef7eb2e8f9f7 459 if(hdma->XferAbortCallback != NULL)
<> 144:ef7eb2e8f9f7 460 {
<> 144:ef7eb2e8f9f7 461 hdma->XferAbortCallback(hdma);
<> 144:ef7eb2e8f9f7 462 }
<> 144:ef7eb2e8f9f7 463 }
<> 144:ef7eb2e8f9f7 464 return status;
<> 144:ef7eb2e8f9f7 465 }
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /**
<> 144:ef7eb2e8f9f7 468 * @brief Polling for transfer complete.
<> 144:ef7eb2e8f9f7 469 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 470 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 471 * @param CompleteLevel: Specifies the DMA level complete.
<> 144:ef7eb2e8f9f7 472 * @param Timeout: Timeout duration.
<> 144:ef7eb2e8f9f7 473 * @retval HAL status
<> 144:ef7eb2e8f9f7 474 */
<> 144:ef7eb2e8f9f7 475 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 476 {
<> 144:ef7eb2e8f9f7 477 uint32_t temp;
<> 156:95d6b41a828b 478 uint32_t tickstart = 0U;
<> 156:95d6b41a828b 479
<> 156:95d6b41a828b 480 if(HAL_DMA_STATE_BUSY != hdma->State)
<> 156:95d6b41a828b 481 {
<> 156:95d6b41a828b 482 /* no transfer ongoing */
<> 156:95d6b41a828b 483 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<> 156:95d6b41a828b 484 __HAL_UNLOCK(hdma);
<> 156:95d6b41a828b 485 return HAL_ERROR;
<> 156:95d6b41a828b 486 }
<> 156:95d6b41a828b 487
<> 156:95d6b41a828b 488 /* Polling mode not supported in circular mode */
<> 156:95d6b41a828b 489 if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
<> 156:95d6b41a828b 490 {
<> 156:95d6b41a828b 491 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
<> 156:95d6b41a828b 492 return HAL_ERROR;
<> 156:95d6b41a828b 493 }
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /* Get the level transfer complete flag */
<> 156:95d6b41a828b 496 if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
<> 144:ef7eb2e8f9f7 497 {
<> 144:ef7eb2e8f9f7 498 /* Transfer Complete flag */
<> 156:95d6b41a828b 499 temp = DMA_FLAG_TC1 << hdma->ChannelIndex;
<> 144:ef7eb2e8f9f7 500 }
<> 144:ef7eb2e8f9f7 501 else
<> 144:ef7eb2e8f9f7 502 {
<> 144:ef7eb2e8f9f7 503 /* Half Transfer Complete flag */
<> 156:95d6b41a828b 504 temp = DMA_FLAG_HT1 << hdma->ChannelIndex;
<> 144:ef7eb2e8f9f7 505 }
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /* Get tick */
<> 144:ef7eb2e8f9f7 508 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 509
<> 156:95d6b41a828b 510 while(RESET == (hdma->DmaBaseAddress->ISR & temp))
<> 144:ef7eb2e8f9f7 511 {
<> 156:95d6b41a828b 512 if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))
<> 144:ef7eb2e8f9f7 513 {
<> 156:95d6b41a828b 514 /* When a DMA transfer error occurs */
<> 156:95d6b41a828b 515 /* A hardware clear of its EN bits is performed */
<> 156:95d6b41a828b 516 /* Clear all flags */
<> 156:95d6b41a828b 517 hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 /* Update error code */
<> 156:95d6b41a828b 520 hdma->ErrorCode = HAL_DMA_ERROR_TE;
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /* Change the DMA state */
<> 156:95d6b41a828b 523 hdma->State= HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 526 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 529 }
<> 144:ef7eb2e8f9f7 530 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 531 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 532 {
<> 156:95d6b41a828b 533 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 534 {
<> 144:ef7eb2e8f9f7 535 /* Update error code */
<> 156:95d6b41a828b 536 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /* Change the DMA state */
<> 156:95d6b41a828b 539 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 542 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 543
<> 156:95d6b41a828b 544 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 545 }
<> 144:ef7eb2e8f9f7 546 }
<> 144:ef7eb2e8f9f7 547 }
<> 144:ef7eb2e8f9f7 548
<> 156:95d6b41a828b 549 if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
<> 144:ef7eb2e8f9f7 550 {
<> 144:ef7eb2e8f9f7 551 /* Clear the transfer complete flag */
<> 156:95d6b41a828b 552 hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /* The selected Channelx EN bit is cleared (DMA is disabled and
<> 144:ef7eb2e8f9f7 555 all transfers are complete) */
<> 144:ef7eb2e8f9f7 556 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 557 }
<> 144:ef7eb2e8f9f7 558 else
<> 144:ef7eb2e8f9f7 559 {
<> 144:ef7eb2e8f9f7 560 /* Clear the half transfer complete flag */
<> 156:95d6b41a828b 561 hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
<> 144:ef7eb2e8f9f7 562 }
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 /* Process unlocked */
<> 144:ef7eb2e8f9f7 565 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 return HAL_OK;
<> 144:ef7eb2e8f9f7 568 }
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /**
<> 156:95d6b41a828b 571 * @brief Handle DMA interrupt request.
<> 144:ef7eb2e8f9f7 572 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 573 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 574 * @retval None
<> 144:ef7eb2e8f9f7 575 */
<> 144:ef7eb2e8f9f7 576 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 577 {
<> 156:95d6b41a828b 578 uint32_t flag_it = hdma->DmaBaseAddress->ISR;
<> 156:95d6b41a828b 579 uint32_t source_it = hdma->Instance->CCR;
<> 156:95d6b41a828b 580
<> 156:95d6b41a828b 581 /* Half Transfer Complete Interrupt management ******************************/
<> 156:95d6b41a828b 582 if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
<> 144:ef7eb2e8f9f7 583 {
<> 156:95d6b41a828b 584 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
<> 156:95d6b41a828b 585 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
<> 156:95d6b41a828b 586 {
<> 156:95d6b41a828b 587 /* Disable the half transfer interrupt */
<> 156:95d6b41a828b 588 hdma->Instance->CCR &= ~DMA_IT_HT;
<> 156:95d6b41a828b 589 }
<> 156:95d6b41a828b 590
<> 156:95d6b41a828b 591 /* Clear the half transfer complete flag */
<> 156:95d6b41a828b 592 hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
<> 156:95d6b41a828b 593
<> 156:95d6b41a828b 594 /* DMA peripheral state is not updated in Half Transfer */
<> 156:95d6b41a828b 595 /* State is updated only in Transfer Complete case */
<> 156:95d6b41a828b 596
<> 156:95d6b41a828b 597 if(hdma->XferHalfCpltCallback != NULL)
<> 156:95d6b41a828b 598 {
<> 156:95d6b41a828b 599 /* Half transfer callback */
<> 156:95d6b41a828b 600 hdma->XferHalfCpltCallback(hdma);
<> 156:95d6b41a828b 601 }
<> 144:ef7eb2e8f9f7 602 }
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /* Transfer Complete Interrupt management ***********************************/
<> 156:95d6b41a828b 605 else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
<> 144:ef7eb2e8f9f7 606 {
<> 156:95d6b41a828b 607 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
<> 156:95d6b41a828b 608 {
<> 156:95d6b41a828b 609 /* Disable the transfer complete & transfer error interrupts */
<> 156:95d6b41a828b 610 /* if the DMA mode is not CIRCULAR */
<> 156:95d6b41a828b 611 hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
<> 156:95d6b41a828b 612
<> 156:95d6b41a828b 613 /* Change the DMA state */
<> 156:95d6b41a828b 614 hdma->State = HAL_DMA_STATE_READY;
<> 156:95d6b41a828b 615 }
<> 156:95d6b41a828b 616
<> 156:95d6b41a828b 617 /* Clear the transfer complete flag */
<> 156:95d6b41a828b 618 hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
<> 156:95d6b41a828b 619
<> 156:95d6b41a828b 620 /* Process Unlocked */
<> 156:95d6b41a828b 621 __HAL_UNLOCK(hdma);
<> 156:95d6b41a828b 622
<> 156:95d6b41a828b 623 if(hdma->XferCpltCallback != NULL)
<> 156:95d6b41a828b 624 {
<> 156:95d6b41a828b 625 /* Transfer complete callback */
<> 156:95d6b41a828b 626 hdma->XferCpltCallback(hdma);
<> 156:95d6b41a828b 627 }
<> 156:95d6b41a828b 628 }
<> 156:95d6b41a828b 629
<> 156:95d6b41a828b 630 /* Transfer Error Interrupt management ***************************************/
<> 156:95d6b41a828b 631 else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
<> 156:95d6b41a828b 632 {
<> 156:95d6b41a828b 633 /* When a DMA transfer error occurs */
<> 156:95d6b41a828b 634 /* A hardware clear of its EN bits is performed */
<> 156:95d6b41a828b 635 /* Then, disable all DMA interrupts */
<> 156:95d6b41a828b 636 hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
<> 156:95d6b41a828b 637
<> 156:95d6b41a828b 638 /* Clear all flags */
<> 156:95d6b41a828b 639 hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
<> 156:95d6b41a828b 640
<> 156:95d6b41a828b 641 /* Update error code */
<> 156:95d6b41a828b 642 hdma->ErrorCode = HAL_DMA_ERROR_TE;
<> 156:95d6b41a828b 643
<> 156:95d6b41a828b 644 /* Change the DMA state */
<> 156:95d6b41a828b 645 hdma->State = HAL_DMA_STATE_READY;
<> 156:95d6b41a828b 646
<> 156:95d6b41a828b 647 /* Process Unlocked */
<> 156:95d6b41a828b 648 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 649
<> 156:95d6b41a828b 650 if(hdma->XferErrorCallback != NULL)
<> 156:95d6b41a828b 651 {
<> 156:95d6b41a828b 652 /* Transfer error callback */
<> 156:95d6b41a828b 653 hdma->XferErrorCallback(hdma);
<> 156:95d6b41a828b 654 }
<> 156:95d6b41a828b 655 }
<> 156:95d6b41a828b 656 }
<> 144:ef7eb2e8f9f7 657
<> 156:95d6b41a828b 658 /**
<> 156:95d6b41a828b 659 * @brief Register callbacks
<> 156:95d6b41a828b 660 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 661 * the configuration information for the specified DMA Stream.
<> 156:95d6b41a828b 662 * @param CallbackID: User Callback identifer
<> 156:95d6b41a828b 663 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
<> 156:95d6b41a828b 664 * @param pCallback: pointer to private callback function which has pointer to
<> 156:95d6b41a828b 665 * a DMA_HandleTypeDef structure as parameter.
<> 156:95d6b41a828b 666 * @retval HAL status
<> 156:95d6b41a828b 667 */
<> 156:95d6b41a828b 668 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
<> 156:95d6b41a828b 669 {
<> 156:95d6b41a828b 670 HAL_StatusTypeDef status = HAL_OK;
<> 156:95d6b41a828b 671
<> 156:95d6b41a828b 672 /* Process locked */
<> 156:95d6b41a828b 673 __HAL_LOCK(hdma);
<> 156:95d6b41a828b 674
<> 156:95d6b41a828b 675 if(HAL_DMA_STATE_READY == hdma->State)
<> 156:95d6b41a828b 676 {
<> 156:95d6b41a828b 677 switch (CallbackID)
<> 156:95d6b41a828b 678 {
<> 156:95d6b41a828b 679 case HAL_DMA_XFER_CPLT_CB_ID:
<> 156:95d6b41a828b 680 hdma->XferCpltCallback = pCallback;
<> 156:95d6b41a828b 681 break;
<> 156:95d6b41a828b 682
<> 156:95d6b41a828b 683 case HAL_DMA_XFER_HALFCPLT_CB_ID:
<> 156:95d6b41a828b 684 hdma->XferHalfCpltCallback = pCallback;
<> 156:95d6b41a828b 685 break;
<> 156:95d6b41a828b 686
<> 156:95d6b41a828b 687 case HAL_DMA_XFER_ERROR_CB_ID:
<> 156:95d6b41a828b 688 hdma->XferErrorCallback = pCallback;
<> 156:95d6b41a828b 689 break;
<> 156:95d6b41a828b 690
<> 156:95d6b41a828b 691 case HAL_DMA_XFER_ABORT_CB_ID:
<> 156:95d6b41a828b 692 hdma->XferAbortCallback = pCallback;
<> 156:95d6b41a828b 693 break;
<> 156:95d6b41a828b 694
<> 156:95d6b41a828b 695 default:
<> 156:95d6b41a828b 696 status = HAL_ERROR;
<> 156:95d6b41a828b 697 break;
<> 144:ef7eb2e8f9f7 698 }
<> 144:ef7eb2e8f9f7 699 }
<> 156:95d6b41a828b 700 else
<> 156:95d6b41a828b 701 {
<> 156:95d6b41a828b 702 status = HAL_ERROR;
<> 156:95d6b41a828b 703 }
<> 156:95d6b41a828b 704
<> 156:95d6b41a828b 705 /* Release Lock */
<> 156:95d6b41a828b 706 __HAL_UNLOCK(hdma);
<> 156:95d6b41a828b 707
<> 156:95d6b41a828b 708 return status;
<> 156:95d6b41a828b 709 }
<> 156:95d6b41a828b 710
<> 156:95d6b41a828b 711 /**
<> 156:95d6b41a828b 712 * @brief UnRegister callbacks
<> 156:95d6b41a828b 713 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 714 * the configuration information for the specified DMA Stream.
<> 156:95d6b41a828b 715 * @param CallbackID: User Callback identifer
<> 156:95d6b41a828b 716 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
<> 156:95d6b41a828b 717 * @retval HAL status
<> 156:95d6b41a828b 718 */
<> 156:95d6b41a828b 719 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
<> 156:95d6b41a828b 720 {
<> 156:95d6b41a828b 721 HAL_StatusTypeDef status = HAL_OK;
<> 156:95d6b41a828b 722
<> 156:95d6b41a828b 723 /* Process locked */
<> 156:95d6b41a828b 724 __HAL_LOCK(hdma);
<> 156:95d6b41a828b 725
<> 156:95d6b41a828b 726 if(HAL_DMA_STATE_READY == hdma->State)
<> 156:95d6b41a828b 727 {
<> 156:95d6b41a828b 728 switch (CallbackID)
<> 156:95d6b41a828b 729 {
<> 156:95d6b41a828b 730 case HAL_DMA_XFER_CPLT_CB_ID:
<> 156:95d6b41a828b 731 hdma->XferCpltCallback = NULL;
<> 156:95d6b41a828b 732 break;
<> 156:95d6b41a828b 733
<> 156:95d6b41a828b 734 case HAL_DMA_XFER_HALFCPLT_CB_ID:
<> 156:95d6b41a828b 735 hdma->XferHalfCpltCallback = NULL;
<> 156:95d6b41a828b 736 break;
<> 156:95d6b41a828b 737
<> 156:95d6b41a828b 738 case HAL_DMA_XFER_ERROR_CB_ID:
<> 156:95d6b41a828b 739 hdma->XferErrorCallback = NULL;
<> 156:95d6b41a828b 740 break;
<> 156:95d6b41a828b 741
<> 156:95d6b41a828b 742 case HAL_DMA_XFER_ABORT_CB_ID:
<> 156:95d6b41a828b 743 hdma->XferAbortCallback = NULL;
<> 156:95d6b41a828b 744 break;
<> 156:95d6b41a828b 745
<> 156:95d6b41a828b 746 case HAL_DMA_XFER_ALL_CB_ID:
<> 156:95d6b41a828b 747 hdma->XferCpltCallback = NULL;
<> 156:95d6b41a828b 748 hdma->XferHalfCpltCallback = NULL;
<> 156:95d6b41a828b 749 hdma->XferErrorCallback = NULL;
<> 156:95d6b41a828b 750 hdma->XferAbortCallback = NULL;
<> 156:95d6b41a828b 751 break;
<> 156:95d6b41a828b 752
<> 156:95d6b41a828b 753 default:
<> 156:95d6b41a828b 754 status = HAL_ERROR;
<> 156:95d6b41a828b 755 break;
<> 156:95d6b41a828b 756 }
<> 156:95d6b41a828b 757 }
<> 156:95d6b41a828b 758 else
<> 156:95d6b41a828b 759 {
<> 156:95d6b41a828b 760 status = HAL_ERROR;
<> 156:95d6b41a828b 761 }
<> 156:95d6b41a828b 762
<> 156:95d6b41a828b 763 /* Release Lock */
<> 156:95d6b41a828b 764 __HAL_UNLOCK(hdma);
<> 156:95d6b41a828b 765
<> 156:95d6b41a828b 766 return status;
<> 156:95d6b41a828b 767 }
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /**
<> 144:ef7eb2e8f9f7 770 * @}
<> 144:ef7eb2e8f9f7 771 */
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
<> 144:ef7eb2e8f9f7 774 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 775 *
<> 144:ef7eb2e8f9f7 776 @verbatim
<> 144:ef7eb2e8f9f7 777 ===============================================================================
<> 144:ef7eb2e8f9f7 778 ##### State and Errors functions #####
<> 144:ef7eb2e8f9f7 779 ===============================================================================
<> 144:ef7eb2e8f9f7 780 [..]
<> 144:ef7eb2e8f9f7 781 This subsection provides functions allowing to
<> 144:ef7eb2e8f9f7 782 (+) Check the DMA state
<> 144:ef7eb2e8f9f7 783 (+) Get error code
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785 @endverbatim
<> 144:ef7eb2e8f9f7 786 * @{
<> 144:ef7eb2e8f9f7 787 */
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 /**
<> 144:ef7eb2e8f9f7 790 * @brief Returns the DMA state.
<> 144:ef7eb2e8f9f7 791 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 792 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 793 * @retval HAL state
<> 144:ef7eb2e8f9f7 794 */
<> 144:ef7eb2e8f9f7 795 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 796 {
<> 144:ef7eb2e8f9f7 797 return hdma->State;
<> 144:ef7eb2e8f9f7 798 }
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 /**
<> 144:ef7eb2e8f9f7 801 * @brief Return the DMA error code
<> 144:ef7eb2e8f9f7 802 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 803 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 804 * @retval DMA Error Code
<> 144:ef7eb2e8f9f7 805 */
<> 144:ef7eb2e8f9f7 806 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 807 {
<> 144:ef7eb2e8f9f7 808 return hdma->ErrorCode;
<> 144:ef7eb2e8f9f7 809 }
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 /**
<> 144:ef7eb2e8f9f7 812 * @}
<> 144:ef7eb2e8f9f7 813 */
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 /**
<> 144:ef7eb2e8f9f7 816 * @}
<> 144:ef7eb2e8f9f7 817 */
<> 144:ef7eb2e8f9f7 818
<> 144:ef7eb2e8f9f7 819 /** @addtogroup DMA_Private_Functions
<> 144:ef7eb2e8f9f7 820 * @{
<> 144:ef7eb2e8f9f7 821 */
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 /**
<> 156:95d6b41a828b 824 * @brief Set the DMA Transfer parameters.
<> 144:ef7eb2e8f9f7 825 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 826 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 827 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 828 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 829 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 830 * @retval HAL status
<> 144:ef7eb2e8f9f7 831 */
<> 144:ef7eb2e8f9f7 832 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 156:95d6b41a828b 833 {
<> 156:95d6b41a828b 834 /* Clear all flags */
<> 156:95d6b41a828b 835 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
<> 156:95d6b41a828b 836
<> 144:ef7eb2e8f9f7 837 /* Configure DMA Channel data length */
<> 144:ef7eb2e8f9f7 838 hdma->Instance->CNDTR = DataLength;
<> 144:ef7eb2e8f9f7 839
<> 144:ef7eb2e8f9f7 840 /* Peripheral to Memory */
<> 144:ef7eb2e8f9f7 841 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
<> 144:ef7eb2e8f9f7 842 {
<> 144:ef7eb2e8f9f7 843 /* Configure DMA Channel destination address */
<> 144:ef7eb2e8f9f7 844 hdma->Instance->CPAR = DstAddress;
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 /* Configure DMA Channel source address */
<> 144:ef7eb2e8f9f7 847 hdma->Instance->CMAR = SrcAddress;
<> 144:ef7eb2e8f9f7 848 }
<> 144:ef7eb2e8f9f7 849 /* Memory to Peripheral */
<> 144:ef7eb2e8f9f7 850 else
<> 144:ef7eb2e8f9f7 851 {
<> 144:ef7eb2e8f9f7 852 /* Configure DMA Channel source address */
<> 144:ef7eb2e8f9f7 853 hdma->Instance->CPAR = SrcAddress;
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 /* Configure DMA Channel destination address */
<> 144:ef7eb2e8f9f7 856 hdma->Instance->CMAR = DstAddress;
<> 144:ef7eb2e8f9f7 857 }
<> 144:ef7eb2e8f9f7 858 }
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 /**
<> 156:95d6b41a828b 861 * @brief set the DMA base address and channel index depending on DMA instance
<> 156:95d6b41a828b 862 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 156:95d6b41a828b 863 * the configuration information for the specified DMA Stream.
<> 156:95d6b41a828b 864 * @retval None
<> 156:95d6b41a828b 865 */
<> 156:95d6b41a828b 866 static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 867 {
<> 156:95d6b41a828b 868 #if defined (DMA2)
<> 156:95d6b41a828b 869 /* calculation of the channel index */
<> 156:95d6b41a828b 870 if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
<> 156:95d6b41a828b 871 {
<> 156:95d6b41a828b 872 /* DMA1 */
<> 156:95d6b41a828b 873 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
<> 156:95d6b41a828b 874 hdma->DmaBaseAddress = DMA1;
<> 156:95d6b41a828b 875 }
<> 156:95d6b41a828b 876 else
<> 156:95d6b41a828b 877 {
<> 156:95d6b41a828b 878 /* DMA2 */
<> 156:95d6b41a828b 879 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
<> 156:95d6b41a828b 880 hdma->DmaBaseAddress = DMA2;
<> 156:95d6b41a828b 881 }
<> 156:95d6b41a828b 882 #else
<> 156:95d6b41a828b 883 /* calculation of the channel index */
<> 156:95d6b41a828b 884 /* DMA1 */
<> 156:95d6b41a828b 885 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
<> 156:95d6b41a828b 886 hdma->DmaBaseAddress = DMA1;
<> 156:95d6b41a828b 887 #endif
<> 156:95d6b41a828b 888 }
<> 156:95d6b41a828b 889
<> 156:95d6b41a828b 890 /**
<> 144:ef7eb2e8f9f7 891 * @}
<> 144:ef7eb2e8f9f7 892 */
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 /**
<> 144:ef7eb2e8f9f7 895 * @}
<> 144:ef7eb2e8f9f7 896 */
<> 144:ef7eb2e8f9f7 897 #endif /* HAL_DMA_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 /**
<> 144:ef7eb2e8f9f7 900 * @}
<> 144:ef7eb2e8f9f7 901 */
<> 156:95d6b41a828b 902
<> 156:95d6b41a828b 903 /**
<> 156:95d6b41a828b 904 * @}
<> 156:95d6b41a828b 905 */
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/