mbed official / mbed-dev

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Cypress/TARGET_PSOC6/psoc6_utils.c@188:bcfe06ba3d64, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:46:34 2018 +0000
Revision:
188:bcfe06ba3d64
Child:
189:f392fc9709a3
mbed-dev library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 188:bcfe06ba3d64 1 /*
AnnaBridge 188:bcfe06ba3d64 2 * mbed Microcontroller Library
AnnaBridge 188:bcfe06ba3d64 3 * Copyright (c) 2017-2018 Future Electronics
AnnaBridge 188:bcfe06ba3d64 4 *
AnnaBridge 188:bcfe06ba3d64 5 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 188:bcfe06ba3d64 6 * you may not use this file except in compliance with the License.
AnnaBridge 188:bcfe06ba3d64 7 * You may obtain a copy of the License at
AnnaBridge 188:bcfe06ba3d64 8 *
AnnaBridge 188:bcfe06ba3d64 9 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 188:bcfe06ba3d64 10 *
AnnaBridge 188:bcfe06ba3d64 11 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 188:bcfe06ba3d64 12 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 188:bcfe06ba3d64 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 188:bcfe06ba3d64 14 * See the License for the specific language governing permissions and
AnnaBridge 188:bcfe06ba3d64 15 * limitations under the License.
AnnaBridge 188:bcfe06ba3d64 16 */
AnnaBridge 188:bcfe06ba3d64 17
AnnaBridge 188:bcfe06ba3d64 18 #include "psoc6_utils.h"
AnnaBridge 188:bcfe06ba3d64 19
AnnaBridge 188:bcfe06ba3d64 20 #if defined(__MBED__)
AnnaBridge 188:bcfe06ba3d64 21
AnnaBridge 188:bcfe06ba3d64 22 #include "mbed_critical.h"
AnnaBridge 188:bcfe06ba3d64 23 #include "mbed_error.h"
AnnaBridge 188:bcfe06ba3d64 24
AnnaBridge 188:bcfe06ba3d64 25 #else
AnnaBridge 188:bcfe06ba3d64 26
AnnaBridge 188:bcfe06ba3d64 27 /** Adaptation layer to native Cypress environment */
AnnaBridge 188:bcfe06ba3d64 28 /* Notice, that since we use critical section here only for operations
AnnaBridge 188:bcfe06ba3d64 29 * that do not involve function calls, we can get away with using
AnnaBridge 188:bcfe06ba3d64 30 * a global static variable for interrupt status saving.
AnnaBridge 188:bcfe06ba3d64 31 */
AnnaBridge 188:bcfe06ba3d64 32
AnnaBridge 188:bcfe06ba3d64 33 #include "syslib/cy_syslib.h"
AnnaBridge 188:bcfe06ba3d64 34
AnnaBridge 188:bcfe06ba3d64 35 #define error(arg) CY_ASSERT(0)
AnnaBridge 188:bcfe06ba3d64 36 #define MBED_ASSERT CY_ASSERT
AnnaBridge 188:bcfe06ba3d64 37
AnnaBridge 188:bcfe06ba3d64 38 #define core_util_critical_section_enter() \
AnnaBridge 188:bcfe06ba3d64 39 uint32_t _last_irq_status_ = Cy_SysLib_EnterCriticalSection()
AnnaBridge 188:bcfe06ba3d64 40
AnnaBridge 188:bcfe06ba3d64 41 #define core_util_critical_section_exit() \
AnnaBridge 188:bcfe06ba3d64 42 Cy_SysLib_ExitCriticalSection(_last_irq_status_)
AnnaBridge 188:bcfe06ba3d64 43
AnnaBridge 188:bcfe06ba3d64 44 #endif /* defined(__MBED__) */
AnnaBridge 188:bcfe06ba3d64 45
AnnaBridge 188:bcfe06ba3d64 46
AnnaBridge 188:bcfe06ba3d64 47 #define CY_NUM_PSOC6_PORTS 14
AnnaBridge 188:bcfe06ba3d64 48 #define CY_NUM_DIVIDER_TYPES 4
AnnaBridge 188:bcfe06ba3d64 49 #define NUM_SCB 8
AnnaBridge 188:bcfe06ba3d64 50 #define NUM_TCPWM 32
AnnaBridge 188:bcfe06ba3d64 51
AnnaBridge 188:bcfe06ba3d64 52
AnnaBridge 188:bcfe06ba3d64 53 #if defined(TARGET_MCU_PSOC6_M0) || PSOC6_DYNSRM_DISABLE || !defined(__MBED__)
AnnaBridge 188:bcfe06ba3d64 54
AnnaBridge 188:bcfe06ba3d64 55 /****************************************************************************/
AnnaBridge 188:bcfe06ba3d64 56 /* Dynamic Shared Resource Manager */
AnnaBridge 188:bcfe06ba3d64 57 /****************************************************************************/
AnnaBridge 188:bcfe06ba3d64 58 /*
AnnaBridge 188:bcfe06ba3d64 59 * This part of the code is responsible for management of the hardware
AnnaBridge 188:bcfe06ba3d64 60 * resource shared between both CPUs of the PSoC 6.
AnnaBridge 188:bcfe06ba3d64 61 * It supports allocation, freeing and conflict detection, so that never
AnnaBridge 188:bcfe06ba3d64 62 * both CPUs try to use a single resource.
AnnaBridge 188:bcfe06ba3d64 63 * It also detects conflicts arising from allocation of hardware devices
AnnaBridge 188:bcfe06ba3d64 64 * for different modes of operation and when user tries to assign multiple
AnnaBridge 188:bcfe06ba3d64 65 * functions to the same chip pin.
AnnaBridge 188:bcfe06ba3d64 66 * It supports two modes of operation:
AnnaBridge 188:bcfe06ba3d64 67 * 1. DYNAMIC (default mode)
AnnaBridge 188:bcfe06ba3d64 68 * Resource manager is run on M0 core and M4 core asks it to allocate
AnnaBridge 188:bcfe06ba3d64 69 * or free resources using RPC over IPC mechanism.
AnnaBridge 188:bcfe06ba3d64 70 * M0 core communicates with manager via local function calls.
AnnaBridge 188:bcfe06ba3d64 71 * 2. STATIC (enabled with PSOC6_DYNSRM_DISABLE compilation flag)
AnnaBridge 188:bcfe06ba3d64 72 * In this mode resources are split statically between both cores.
AnnaBridge 188:bcfe06ba3d64 73 * Targets using this mode should add psoc6_static_srm.h file to
AnnaBridge 188:bcfe06ba3d64 74 * each core folder with declarations of resources assigned to it.
AnnaBridge 188:bcfe06ba3d64 75 * See example file for details.
AnnaBridge 188:bcfe06ba3d64 76 */
AnnaBridge 188:bcfe06ba3d64 77
AnnaBridge 188:bcfe06ba3d64 78
AnnaBridge 188:bcfe06ba3d64 79 #if PSOC6_DYNSRM_DISABLE
AnnaBridge 188:bcfe06ba3d64 80
AnnaBridge 188:bcfe06ba3d64 81 #define SRM_INIT_RESOURCE(_type_, _res_, _field_, ...) \
AnnaBridge 188:bcfe06ba3d64 82 do { \
AnnaBridge 188:bcfe06ba3d64 83 struct _init_s_ { \
AnnaBridge 188:bcfe06ba3d64 84 uint8_t idx; \
AnnaBridge 188:bcfe06ba3d64 85 _type_ val; \
AnnaBridge 188:bcfe06ba3d64 86 } init[] = {{0, 0}, __VA_ARGS__}; \
AnnaBridge 188:bcfe06ba3d64 87 uint32_t i; \
AnnaBridge 188:bcfe06ba3d64 88 for (i = 1; i < sizeof(init)/sizeof(struct _init_s_); ++i) \
AnnaBridge 188:bcfe06ba3d64 89 _res_[init[i].idx]_field_ = init[i].val; \
AnnaBridge 188:bcfe06ba3d64 90 } while(0)
AnnaBridge 188:bcfe06ba3d64 91
AnnaBridge 188:bcfe06ba3d64 92 #if defined(TARGET_MCU_PSOC6_M0)
AnnaBridge 188:bcfe06ba3d64 93 /*
AnnaBridge 188:bcfe06ba3d64 94 * On M0 we start with all resources assigned to M4 and then clear reservations
AnnaBridge 188:bcfe06ba3d64 95 * for those assigned to it (M0).
AnnaBridge 188:bcfe06ba3d64 96 */
AnnaBridge 188:bcfe06ba3d64 97 #define SRM_PORT(port, pins) {(port), (uint8_t)~(pins)}
AnnaBridge 188:bcfe06ba3d64 98 #define SRM_DIVIDER(type, dividers) {(type), (uint16_t)~(dividers)}
AnnaBridge 188:bcfe06ba3d64 99 #define SRM_SCB(num) {(num), (0)}
AnnaBridge 188:bcfe06ba3d64 100 #define SRM_TCPWM(num) {(num), (0)}
AnnaBridge 188:bcfe06ba3d64 101
AnnaBridge 188:bcfe06ba3d64 102 #define DEFAULT_PORT_RES 0xff
AnnaBridge 188:bcfe06ba3d64 103 #define DEFAULT_DIVIDER_RES 0xffff
AnnaBridge 188:bcfe06ba3d64 104 #define DEFAULT_SCM_RES 1
AnnaBridge 188:bcfe06ba3d64 105 #define DEFAULT_TCPWM_RES 1
AnnaBridge 188:bcfe06ba3d64 106
AnnaBridge 188:bcfe06ba3d64 107 #else // defined(TARGET_MCU_PSOC6_M0)
AnnaBridge 188:bcfe06ba3d64 108
AnnaBridge 188:bcfe06ba3d64 109 #define SRM_PORT(port, pins) {(port), (pins)}
AnnaBridge 188:bcfe06ba3d64 110 #define SRM_DIVIDER(type, dividers) {(type), (dividers)}
AnnaBridge 188:bcfe06ba3d64 111 #define SRM_SCB(num) {(num), (1)}
AnnaBridge 188:bcfe06ba3d64 112 #define SRM_TCPWM(num) {(num), (1)}
AnnaBridge 188:bcfe06ba3d64 113
AnnaBridge 188:bcfe06ba3d64 114 #define DEFAULT_PORT_RES 0
AnnaBridge 188:bcfe06ba3d64 115 #define DEFAULT_DIVIDER_RES 0
AnnaBridge 188:bcfe06ba3d64 116 #define DEFAULT_DIVIDER8_RES 0
AnnaBridge 188:bcfe06ba3d64 117 #define DEFAULT_SCM_RES 0
AnnaBridge 188:bcfe06ba3d64 118 #define DEFAULT_TCPWM_RES 0
AnnaBridge 188:bcfe06ba3d64 119 #endif // defined(TARGET_MCU_PSOC6_M0)
AnnaBridge 188:bcfe06ba3d64 120
AnnaBridge 188:bcfe06ba3d64 121 #include "psoc6_static_srm.h"
AnnaBridge 188:bcfe06ba3d64 122
AnnaBridge 188:bcfe06ba3d64 123 #else // PSOC6_DYNSRM_DISABLE
AnnaBridge 188:bcfe06ba3d64 124
AnnaBridge 188:bcfe06ba3d64 125 #define DEFAULT_PORT_RES 0
AnnaBridge 188:bcfe06ba3d64 126 #define DEFAULT_DIVIDER_RES 0
AnnaBridge 188:bcfe06ba3d64 127 #define DEFAULT_DIVIDER8_RES 0x3 // dividers 0 & 1 are reserved for us_ticker
AnnaBridge 188:bcfe06ba3d64 128 #define DEFAULT_SCM_RES 0
AnnaBridge 188:bcfe06ba3d64 129 #define DEFAULT_TCPWM_RES 0x3 // 32b counters 0 & 1 are reserved for us_ticker
AnnaBridge 188:bcfe06ba3d64 130
AnnaBridge 188:bcfe06ba3d64 131 #endif // PSOC6_DYNSRM_DISABLE
AnnaBridge 188:bcfe06ba3d64 132
AnnaBridge 188:bcfe06ba3d64 133 static uint8_t port_reservations[CY_NUM_PSOC6_PORTS] = {DEFAULT_PORT_RES};
AnnaBridge 188:bcfe06ba3d64 134
AnnaBridge 188:bcfe06ba3d64 135 typedef struct {
AnnaBridge 188:bcfe06ba3d64 136 const uint32_t max_index;
AnnaBridge 188:bcfe06ba3d64 137 uint32_t current_index;
AnnaBridge 188:bcfe06ba3d64 138 uint32_t reservations;
AnnaBridge 188:bcfe06ba3d64 139 } divider_alloc_t;
AnnaBridge 188:bcfe06ba3d64 140
AnnaBridge 188:bcfe06ba3d64 141 static divider_alloc_t divider_allocations[CY_NUM_DIVIDER_TYPES] = {
AnnaBridge 188:bcfe06ba3d64 142 { PERI_DIV_8_NR - 1, 2, DEFAULT_DIVIDER8_RES }, // CY_SYSCLK_DIV_8_BIT
AnnaBridge 188:bcfe06ba3d64 143 { PERI_DIV_16_NR - 1, 0, DEFAULT_DIVIDER_RES }, // CY_SYSCLK_DIV_16_BIT
AnnaBridge 188:bcfe06ba3d64 144 { PERI_DIV_16_5_NR - 1, 0, DEFAULT_DIVIDER_RES }, // CY_SYSCLK_DIV_16_5_BIT
AnnaBridge 188:bcfe06ba3d64 145 { PERI_DIV_24_5_NR - 1, 0, DEFAULT_DIVIDER_RES } // CY_SYSCLK_DIV_24_5_BIT
AnnaBridge 188:bcfe06ba3d64 146 };
AnnaBridge 188:bcfe06ba3d64 147
AnnaBridge 188:bcfe06ba3d64 148 static uint8_t scb_reservations[NUM_SCB] = {DEFAULT_SCM_RES};
AnnaBridge 188:bcfe06ba3d64 149
AnnaBridge 188:bcfe06ba3d64 150 static uint8_t tcpwm_reservations[NUM_TCPWM] = {DEFAULT_TCPWM_RES};
AnnaBridge 188:bcfe06ba3d64 151
AnnaBridge 188:bcfe06ba3d64 152
AnnaBridge 188:bcfe06ba3d64 153 int cy_reserve_io_pin(PinName pin_name)
AnnaBridge 188:bcfe06ba3d64 154 {
AnnaBridge 188:bcfe06ba3d64 155 uint32_t port = CY_PORT(pin_name);
AnnaBridge 188:bcfe06ba3d64 156 uint32_t pin = CY_PIN(pin_name);
AnnaBridge 188:bcfe06ba3d64 157 int result = (-1);
AnnaBridge 188:bcfe06ba3d64 158
AnnaBridge 188:bcfe06ba3d64 159 if ((port < CY_NUM_PSOC6_PORTS) && (pin <= 7)) {
AnnaBridge 188:bcfe06ba3d64 160 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 161 if (!(port_reservations[port] & (1 << pin))) {
AnnaBridge 188:bcfe06ba3d64 162 port_reservations[port] |= (1 << pin);
AnnaBridge 188:bcfe06ba3d64 163 result = 0;
AnnaBridge 188:bcfe06ba3d64 164 }
AnnaBridge 188:bcfe06ba3d64 165 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 166 } else {
AnnaBridge 188:bcfe06ba3d64 167 error("Trying to reserve non existing port/pin!");
AnnaBridge 188:bcfe06ba3d64 168 }
AnnaBridge 188:bcfe06ba3d64 169 return result;
AnnaBridge 188:bcfe06ba3d64 170 }
AnnaBridge 188:bcfe06ba3d64 171
AnnaBridge 188:bcfe06ba3d64 172
AnnaBridge 188:bcfe06ba3d64 173 void cy_free_io_pin(PinName pin_name)
AnnaBridge 188:bcfe06ba3d64 174 {
AnnaBridge 188:bcfe06ba3d64 175 uint32_t port = CY_PORT(pin_name);
AnnaBridge 188:bcfe06ba3d64 176 uint32_t pin = CY_PIN(pin_name);
AnnaBridge 188:bcfe06ba3d64 177 int result = (-1);
AnnaBridge 188:bcfe06ba3d64 178
AnnaBridge 188:bcfe06ba3d64 179 if ((port < CY_NUM_PSOC6_PORTS) && (pin <= 7)) {
AnnaBridge 188:bcfe06ba3d64 180 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 181 if (port_reservations[port] & (1 << pin)) {
AnnaBridge 188:bcfe06ba3d64 182 port_reservations[port] &= ~(1 << pin);
AnnaBridge 188:bcfe06ba3d64 183 result = 0;
AnnaBridge 188:bcfe06ba3d64 184 }
AnnaBridge 188:bcfe06ba3d64 185 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 186 }
AnnaBridge 188:bcfe06ba3d64 187
AnnaBridge 188:bcfe06ba3d64 188 if (result) {
AnnaBridge 188:bcfe06ba3d64 189 error("Trying to free wrong port/pin.");
AnnaBridge 188:bcfe06ba3d64 190 }
AnnaBridge 188:bcfe06ba3d64 191 }
AnnaBridge 188:bcfe06ba3d64 192
AnnaBridge 188:bcfe06ba3d64 193
AnnaBridge 188:bcfe06ba3d64 194 uint32_t cy_clk_reserve_divider(cy_en_divider_types_t div_type, uint32_t div_num)
AnnaBridge 188:bcfe06ba3d64 195 {
AnnaBridge 188:bcfe06ba3d64 196 uint32_t divider = CY_INVALID_DIVIDER;
AnnaBridge 188:bcfe06ba3d64 197 divider_alloc_t *p_alloc = &divider_allocations[div_type];
AnnaBridge 188:bcfe06ba3d64 198
AnnaBridge 188:bcfe06ba3d64 199 MBED_ASSERT(div_type < CY_NUM_DIVIDER_TYPES);
AnnaBridge 188:bcfe06ba3d64 200 MBED_ASSERT(div_num <= p_alloc->max_index);
AnnaBridge 188:bcfe06ba3d64 201
AnnaBridge 188:bcfe06ba3d64 202 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 203
AnnaBridge 188:bcfe06ba3d64 204 if ((p_alloc->reservations & (1 << div_num)) == 0) {
AnnaBridge 188:bcfe06ba3d64 205 p_alloc->reservations |= (1 << div_num);
AnnaBridge 188:bcfe06ba3d64 206 divider = div_num;
AnnaBridge 188:bcfe06ba3d64 207 p_alloc->current_index = ++div_num;
AnnaBridge 188:bcfe06ba3d64 208 if (p_alloc->current_index > p_alloc->max_index) {
AnnaBridge 188:bcfe06ba3d64 209 p_alloc->current_index = 0;
AnnaBridge 188:bcfe06ba3d64 210 }
AnnaBridge 188:bcfe06ba3d64 211 }
AnnaBridge 188:bcfe06ba3d64 212
AnnaBridge 188:bcfe06ba3d64 213 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 214
AnnaBridge 188:bcfe06ba3d64 215 return divider;
AnnaBridge 188:bcfe06ba3d64 216 }
AnnaBridge 188:bcfe06ba3d64 217
AnnaBridge 188:bcfe06ba3d64 218
AnnaBridge 188:bcfe06ba3d64 219 void cy_clk_free_divider(cy_en_divider_types_t div_type, uint32_t div_num)
AnnaBridge 188:bcfe06ba3d64 220 {
AnnaBridge 188:bcfe06ba3d64 221 int result = (-1);
AnnaBridge 188:bcfe06ba3d64 222 divider_alloc_t *p_alloc = &divider_allocations[div_type];
AnnaBridge 188:bcfe06ba3d64 223
AnnaBridge 188:bcfe06ba3d64 224 MBED_ASSERT(div_type < CY_NUM_DIVIDER_TYPES);
AnnaBridge 188:bcfe06ba3d64 225 MBED_ASSERT(div_num <= p_alloc->max_index);
AnnaBridge 188:bcfe06ba3d64 226
AnnaBridge 188:bcfe06ba3d64 227 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 228
AnnaBridge 188:bcfe06ba3d64 229 if ((p_alloc->reservations & (1 << div_num)) != 0) {
AnnaBridge 188:bcfe06ba3d64 230 p_alloc->reservations &= ~(1 << div_num);
AnnaBridge 188:bcfe06ba3d64 231 result = 0;
AnnaBridge 188:bcfe06ba3d64 232 }
AnnaBridge 188:bcfe06ba3d64 233
AnnaBridge 188:bcfe06ba3d64 234 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 235
AnnaBridge 188:bcfe06ba3d64 236 if (result) {
AnnaBridge 188:bcfe06ba3d64 237 error("Trying to release wrong clock divider.");
AnnaBridge 188:bcfe06ba3d64 238 }
AnnaBridge 188:bcfe06ba3d64 239 }
AnnaBridge 188:bcfe06ba3d64 240
AnnaBridge 188:bcfe06ba3d64 241
AnnaBridge 188:bcfe06ba3d64 242 uint32_t cy_clk_allocate_divider(cy_en_divider_types_t div_type)
AnnaBridge 188:bcfe06ba3d64 243 {
AnnaBridge 188:bcfe06ba3d64 244 uint32_t divider = CY_INVALID_DIVIDER;
AnnaBridge 188:bcfe06ba3d64 245 divider_alloc_t *p_alloc = &divider_allocations[div_type];
AnnaBridge 188:bcfe06ba3d64 246
AnnaBridge 188:bcfe06ba3d64 247 MBED_ASSERT(div_type < CY_NUM_DIVIDER_TYPES);
AnnaBridge 188:bcfe06ba3d64 248
AnnaBridge 188:bcfe06ba3d64 249 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 250
AnnaBridge 188:bcfe06ba3d64 251 MBED_ASSERT(p_alloc->current_index < p_alloc->max_index);
AnnaBridge 188:bcfe06ba3d64 252
AnnaBridge 188:bcfe06ba3d64 253
AnnaBridge 188:bcfe06ba3d64 254 for ( uint32_t first_index = p_alloc->current_index;
AnnaBridge 188:bcfe06ba3d64 255 CY_INVALID_DIVIDER == (divider = cy_clk_reserve_divider(div_type, p_alloc->current_index));
AnnaBridge 188:bcfe06ba3d64 256 ++p_alloc->current_index) {
AnnaBridge 188:bcfe06ba3d64 257 if (p_alloc->current_index > p_alloc->max_index) {
AnnaBridge 188:bcfe06ba3d64 258 p_alloc->current_index = 0;
AnnaBridge 188:bcfe06ba3d64 259 }
AnnaBridge 188:bcfe06ba3d64 260 if (p_alloc->current_index == first_index) {
AnnaBridge 188:bcfe06ba3d64 261 break;
AnnaBridge 188:bcfe06ba3d64 262 }
AnnaBridge 188:bcfe06ba3d64 263 }
AnnaBridge 188:bcfe06ba3d64 264
AnnaBridge 188:bcfe06ba3d64 265 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 266
AnnaBridge 188:bcfe06ba3d64 267 return divider;
AnnaBridge 188:bcfe06ba3d64 268 }
AnnaBridge 188:bcfe06ba3d64 269
AnnaBridge 188:bcfe06ba3d64 270
AnnaBridge 188:bcfe06ba3d64 271 int cy_reserve_scb(uint32_t scb_num)
AnnaBridge 188:bcfe06ba3d64 272 {
AnnaBridge 188:bcfe06ba3d64 273 int result = (-1);
AnnaBridge 188:bcfe06ba3d64 274
AnnaBridge 188:bcfe06ba3d64 275 if (scb_num < NUM_SCB) {
AnnaBridge 188:bcfe06ba3d64 276 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 277 if (scb_reservations[scb_num] == 0) {
AnnaBridge 188:bcfe06ba3d64 278 scb_reservations[scb_num] = 1;
AnnaBridge 188:bcfe06ba3d64 279 }
AnnaBridge 188:bcfe06ba3d64 280 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 281 }
AnnaBridge 188:bcfe06ba3d64 282 return result;
AnnaBridge 188:bcfe06ba3d64 283 }
AnnaBridge 188:bcfe06ba3d64 284
AnnaBridge 188:bcfe06ba3d64 285
AnnaBridge 188:bcfe06ba3d64 286 void cy_free_scb(uint32_t scb_num)
AnnaBridge 188:bcfe06ba3d64 287 {
AnnaBridge 188:bcfe06ba3d64 288 int result = (-1);
AnnaBridge 188:bcfe06ba3d64 289
AnnaBridge 188:bcfe06ba3d64 290 if (scb_num < NUM_SCB) {
AnnaBridge 188:bcfe06ba3d64 291 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 292 if (scb_reservations[scb_num] == 1) {
AnnaBridge 188:bcfe06ba3d64 293 scb_reservations[scb_num] = 0;
AnnaBridge 188:bcfe06ba3d64 294 }
AnnaBridge 188:bcfe06ba3d64 295 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 296 }
AnnaBridge 188:bcfe06ba3d64 297 if (result) {
AnnaBridge 188:bcfe06ba3d64 298 error("Trying to release wrong SCB.");
AnnaBridge 188:bcfe06ba3d64 299 }
AnnaBridge 188:bcfe06ba3d64 300 }
AnnaBridge 188:bcfe06ba3d64 301
AnnaBridge 188:bcfe06ba3d64 302
AnnaBridge 188:bcfe06ba3d64 303 int cy_reserve_tcpwm(uint32_t tcpwm_num)
AnnaBridge 188:bcfe06ba3d64 304 {
AnnaBridge 188:bcfe06ba3d64 305 int result = (-1);
AnnaBridge 188:bcfe06ba3d64 306
AnnaBridge 188:bcfe06ba3d64 307 if (tcpwm_num < NUM_TCPWM) {
AnnaBridge 188:bcfe06ba3d64 308 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 309 if (tcpwm_reservations[tcpwm_num] == 0) {
AnnaBridge 188:bcfe06ba3d64 310 tcpwm_reservations[tcpwm_num] = 1;
AnnaBridge 188:bcfe06ba3d64 311 result = 0;
AnnaBridge 188:bcfe06ba3d64 312 }
AnnaBridge 188:bcfe06ba3d64 313 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 314 }
AnnaBridge 188:bcfe06ba3d64 315 return result;
AnnaBridge 188:bcfe06ba3d64 316 }
AnnaBridge 188:bcfe06ba3d64 317
AnnaBridge 188:bcfe06ba3d64 318
AnnaBridge 188:bcfe06ba3d64 319 void cy_free_tcpwm(uint32_t tcpwm_num)
AnnaBridge 188:bcfe06ba3d64 320 {
AnnaBridge 188:bcfe06ba3d64 321 int result = (-1);
AnnaBridge 188:bcfe06ba3d64 322
AnnaBridge 188:bcfe06ba3d64 323 if (tcpwm_num < NUM_TCPWM) {
AnnaBridge 188:bcfe06ba3d64 324 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 325 if (tcpwm_reservations[tcpwm_num] == 1) {
AnnaBridge 188:bcfe06ba3d64 326 tcpwm_reservations[tcpwm_num] = 0;
AnnaBridge 188:bcfe06ba3d64 327 result = 0;
AnnaBridge 188:bcfe06ba3d64 328 }
AnnaBridge 188:bcfe06ba3d64 329 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 330 }
AnnaBridge 188:bcfe06ba3d64 331 if (result) {
AnnaBridge 188:bcfe06ba3d64 332 error("Trying to release wrong TCPWM.");
AnnaBridge 188:bcfe06ba3d64 333 }
AnnaBridge 188:bcfe06ba3d64 334 }
AnnaBridge 188:bcfe06ba3d64 335
AnnaBridge 188:bcfe06ba3d64 336
AnnaBridge 188:bcfe06ba3d64 337 /*
AnnaBridge 188:bcfe06ba3d64 338 * NVIC channel dynamic allocation (multiplexing) is used only on M0.
AnnaBridge 188:bcfe06ba3d64 339 * On M4 IRQs are statically pre-assigned to NVIC channels.
AnnaBridge 188:bcfe06ba3d64 340 */
AnnaBridge 188:bcfe06ba3d64 341
AnnaBridge 188:bcfe06ba3d64 342 #if defined(TARGET_MCU_PSOC6_M0)
AnnaBridge 188:bcfe06ba3d64 343
AnnaBridge 188:bcfe06ba3d64 344 #define NUM_NVIC_CHANNELS ((uint32_t)(NvicMux31_IRQn - NvicMux0_IRQn) + 1)
AnnaBridge 188:bcfe06ba3d64 345
AnnaBridge 188:bcfe06ba3d64 346 static uint32_t irq_channels[NUM_NVIC_CHANNELS] = {0};
AnnaBridge 188:bcfe06ba3d64 347
AnnaBridge 188:bcfe06ba3d64 348
AnnaBridge 188:bcfe06ba3d64 349 IRQn_Type cy_m0_nvic_allocate_channel(uint32_t channel_id)
AnnaBridge 188:bcfe06ba3d64 350 {
AnnaBridge 188:bcfe06ba3d64 351 IRQn_Type alloc = (IRQn_Type)(-1);
AnnaBridge 188:bcfe06ba3d64 352 uint32_t chn;
AnnaBridge 188:bcfe06ba3d64 353 MBED_ASSERT(channel_id);
AnnaBridge 188:bcfe06ba3d64 354
AnnaBridge 188:bcfe06ba3d64 355 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 356 for (chn = 0; chn < NUM_NVIC_CHANNELS; ++chn) {
AnnaBridge 188:bcfe06ba3d64 357 if (irq_channels[chn] == 0) {
AnnaBridge 188:bcfe06ba3d64 358 irq_channels[chn] = channel_id;
AnnaBridge 188:bcfe06ba3d64 359 alloc = NvicMux0_IRQn + chn;
AnnaBridge 188:bcfe06ba3d64 360 break;
AnnaBridge 188:bcfe06ba3d64 361 irq_channels[chn] = channel_id;
AnnaBridge 188:bcfe06ba3d64 362
AnnaBridge 188:bcfe06ba3d64 363 }
AnnaBridge 188:bcfe06ba3d64 364 }
AnnaBridge 188:bcfe06ba3d64 365 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 366 return alloc;
AnnaBridge 188:bcfe06ba3d64 367 }
AnnaBridge 188:bcfe06ba3d64 368
AnnaBridge 188:bcfe06ba3d64 369 IRQn_Type cy_m0_nvic_reserve_channel(IRQn_Type channel, uint32_t channel_id)
AnnaBridge 188:bcfe06ba3d64 370 {
AnnaBridge 188:bcfe06ba3d64 371 uint32_t chn = channel - NvicMux0_IRQn;
AnnaBridge 188:bcfe06ba3d64 372
AnnaBridge 188:bcfe06ba3d64 373 MBED_ASSERT(chn < NUM_NVIC_CHANNELS);
AnnaBridge 188:bcfe06ba3d64 374 MBED_ASSERT(channel_id);
AnnaBridge 188:bcfe06ba3d64 375
AnnaBridge 188:bcfe06ba3d64 376 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 377 if (irq_channels[chn]) {
AnnaBridge 188:bcfe06ba3d64 378 channel = (IRQn_Type)(-1);
AnnaBridge 188:bcfe06ba3d64 379 } else {
AnnaBridge 188:bcfe06ba3d64 380 irq_channels[chn] = channel_id;
AnnaBridge 188:bcfe06ba3d64 381 }
AnnaBridge 188:bcfe06ba3d64 382 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 383 return channel;
AnnaBridge 188:bcfe06ba3d64 384 }
AnnaBridge 188:bcfe06ba3d64 385
AnnaBridge 188:bcfe06ba3d64 386 void cy_m0_nvic_release_channel(IRQn_Type channel, uint32_t channel_id)
AnnaBridge 188:bcfe06ba3d64 387 {
AnnaBridge 188:bcfe06ba3d64 388 uint32_t chn = channel - NvicMux0_IRQn;
AnnaBridge 188:bcfe06ba3d64 389
AnnaBridge 188:bcfe06ba3d64 390 MBED_ASSERT(chn < NUM_NVIC_CHANNELS);
AnnaBridge 188:bcfe06ba3d64 391 MBED_ASSERT(channel_id);
AnnaBridge 188:bcfe06ba3d64 392
AnnaBridge 188:bcfe06ba3d64 393 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 394 if (irq_channels[chn] == channel_id) {
AnnaBridge 188:bcfe06ba3d64 395 irq_channels[chn] = 0;
AnnaBridge 188:bcfe06ba3d64 396 } else {
AnnaBridge 188:bcfe06ba3d64 397 error("NVIC channel cross-check failed on release.");
AnnaBridge 188:bcfe06ba3d64 398 }
AnnaBridge 188:bcfe06ba3d64 399 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 400 }
AnnaBridge 188:bcfe06ba3d64 401
AnnaBridge 188:bcfe06ba3d64 402 #define CY_BLE_SFLASH_DIE_X_MASK (0x3Fu)
AnnaBridge 188:bcfe06ba3d64 403 #define CY_BLE_SFLASH_DIE_X_BITS (6u)
AnnaBridge 188:bcfe06ba3d64 404 #define CY_BLE_SFLASH_DIE_Y_MASK (0x3Fu)
AnnaBridge 188:bcfe06ba3d64 405 #define CY_BLE_SFLASH_DIE_Y_BITS (6u)
AnnaBridge 188:bcfe06ba3d64 406 #define CY_BLE_SFLASH_DIE_XY_BITS (CY_BLE_SFLASH_DIE_X_BITS + CY_BLE_SFLASH_DIE_Y_BITS)
AnnaBridge 188:bcfe06ba3d64 407 #define CY_BLE_SFLASH_DIE_WAFER_MASK (0x1Fu)
AnnaBridge 188:bcfe06ba3d64 408 #define CY_BLE_SFLASH_DIE_WAFER_BITS (5u)
AnnaBridge 188:bcfe06ba3d64 409 #define CY_BLE_SFLASH_DIE_XYWAFER_BITS (CY_BLE_SFLASH_DIE_XY_BITS + CY_BLE_SFLASH_DIE_WAFER_BITS)
AnnaBridge 188:bcfe06ba3d64 410 #define CY_BLE_SFLASH_DIE_LOT_MASK (0x7Fu)
AnnaBridge 188:bcfe06ba3d64 411 #define CY_BLE_SFLASH_DIE_LOT_BITS (7u)
AnnaBridge 188:bcfe06ba3d64 412
AnnaBridge 188:bcfe06ba3d64 413 static uint8_t cy_ble_deviceAddress[6] = {0x19u, 0x00u, 0x00u, 0x50u, 0xA0u, 0x00u};
AnnaBridge 188:bcfe06ba3d64 414
AnnaBridge 188:bcfe06ba3d64 415 void cy_get_bd_mac_address(uint8_t *buffer)
AnnaBridge 188:bcfe06ba3d64 416 {
AnnaBridge 188:bcfe06ba3d64 417 uint32_t bdAddrLoc;
AnnaBridge 188:bcfe06ba3d64 418 bdAddrLoc = ((uint32_t)SFLASH->DIE_X & (uint32_t)CY_BLE_SFLASH_DIE_X_MASK) |
AnnaBridge 188:bcfe06ba3d64 419 ((uint32_t)(((uint32_t)SFLASH->DIE_Y) & ((uint32_t)CY_BLE_SFLASH_DIE_Y_MASK)) <<
AnnaBridge 188:bcfe06ba3d64 420 CY_BLE_SFLASH_DIE_X_BITS) |
AnnaBridge 188:bcfe06ba3d64 421 ((uint32_t)(((uint32_t)SFLASH->DIE_WAFER) & ((uint32_t)CY_BLE_SFLASH_DIE_WAFER_MASK)) <<
AnnaBridge 188:bcfe06ba3d64 422 CY_BLE_SFLASH_DIE_XY_BITS) |
AnnaBridge 188:bcfe06ba3d64 423 ((uint32_t)(((uint32_t)SFLASH->DIE_LOT[0]) & ((uint32_t)CY_BLE_SFLASH_DIE_LOT_MASK)) <<
AnnaBridge 188:bcfe06ba3d64 424 CY_BLE_SFLASH_DIE_XYWAFER_BITS);
AnnaBridge 188:bcfe06ba3d64 425
AnnaBridge 188:bcfe06ba3d64 426 cy_ble_deviceAddress[0] = (uint8_t)bdAddrLoc;
AnnaBridge 188:bcfe06ba3d64 427 cy_ble_deviceAddress[1] = (uint8_t)(bdAddrLoc >> 8u);
AnnaBridge 188:bcfe06ba3d64 428 cy_ble_deviceAddress[2] = (uint8_t)(bdAddrLoc >> 16u);
AnnaBridge 188:bcfe06ba3d64 429
AnnaBridge 188:bcfe06ba3d64 430 for (int i = 0; i < 6; ++i) {
AnnaBridge 188:bcfe06ba3d64 431 buffer[i] = cy_ble_deviceAddress[i];
AnnaBridge 188:bcfe06ba3d64 432 }
AnnaBridge 188:bcfe06ba3d64 433 }
AnnaBridge 188:bcfe06ba3d64 434
AnnaBridge 188:bcfe06ba3d64 435 #endif // defined(TARGET_MCU_PSOC6_M0)
AnnaBridge 188:bcfe06ba3d64 436
AnnaBridge 188:bcfe06ba3d64 437 #endif // defined(TARGET_MCU_PSOC6_M0) || PSOC6_DSRM_DISABLE || !defined(__MBED__)
AnnaBridge 188:bcfe06ba3d64 438
AnnaBridge 188:bcfe06ba3d64 439 void cy_srm_initialize(void)
AnnaBridge 188:bcfe06ba3d64 440 {
AnnaBridge 188:bcfe06ba3d64 441 #if PSOC6_DYNSRM_DISABLE
AnnaBridge 188:bcfe06ba3d64 442 #ifdef M0_ASSIGNED_PORTS
AnnaBridge 188:bcfe06ba3d64 443 SRM_INIT_RESOURCE(uint8_t, port_reservations,, M0_ASSIGNED_PORTS);
AnnaBridge 188:bcfe06ba3d64 444 #endif
AnnaBridge 188:bcfe06ba3d64 445 #ifdef M0_ASSIGNED_DIVIDERS
AnnaBridge 188:bcfe06ba3d64 446 SRM_INIT_RESOURCE(uint32_t, divider_allocations, .reservations, M0_ASSIGNED_DIVIDERS);
AnnaBridge 188:bcfe06ba3d64 447 #endif
AnnaBridge 188:bcfe06ba3d64 448 #ifdef M0_ASSIGNED_SCBS
AnnaBridge 188:bcfe06ba3d64 449 SRM_INIT_RESOURCE(uint8_t, scb_reservations,, M0_ASSIGNED_SCBS);
AnnaBridge 188:bcfe06ba3d64 450 #endif
AnnaBridge 188:bcfe06ba3d64 451 #ifdef M0_ASSIGNED_TCPWMS
AnnaBridge 188:bcfe06ba3d64 452 SRM_INIT_RESOURCE(uint8_t, tcpwm_reservations,, M0_ASSIGNED_TCPWMS);
AnnaBridge 188:bcfe06ba3d64 453 #endif
AnnaBridge 188:bcfe06ba3d64 454 #endif // PSOC6_DYNSRM_DISABLE
AnnaBridge 188:bcfe06ba3d64 455 }
AnnaBridge 188:bcfe06ba3d64 456