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mbed library sources. Supersedes mbed-src.

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targets/TARGET_Cypress/TARGET_PSOC6/psoc6_utils.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
188:bcfe06ba3d64 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 188:bcfe06ba3d64 1 /*
AnnaBridge 188:bcfe06ba3d64 2 * mbed Microcontroller Library
AnnaBridge 188:bcfe06ba3d64 3 * Copyright (c) 2017-2018 Future Electronics
AnnaBridge 189:f392fc9709a3 4 * Copyright (c) 2018-2019 Cypress Semiconductor Corporation
AnnaBridge 189:f392fc9709a3 5 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 188:bcfe06ba3d64 6 *
AnnaBridge 188:bcfe06ba3d64 7 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 188:bcfe06ba3d64 8 * you may not use this file except in compliance with the License.
AnnaBridge 188:bcfe06ba3d64 9 * You may obtain a copy of the License at
AnnaBridge 188:bcfe06ba3d64 10 *
AnnaBridge 188:bcfe06ba3d64 11 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 188:bcfe06ba3d64 12 *
AnnaBridge 188:bcfe06ba3d64 13 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 188:bcfe06ba3d64 14 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 188:bcfe06ba3d64 15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 188:bcfe06ba3d64 16 * See the License for the specific language governing permissions and
AnnaBridge 188:bcfe06ba3d64 17 * limitations under the License.
AnnaBridge 188:bcfe06ba3d64 18 */
AnnaBridge 188:bcfe06ba3d64 19
AnnaBridge 188:bcfe06ba3d64 20 #include "psoc6_utils.h"
AnnaBridge 188:bcfe06ba3d64 21
AnnaBridge 188:bcfe06ba3d64 22 #if defined(__MBED__)
AnnaBridge 188:bcfe06ba3d64 23
AnnaBridge 188:bcfe06ba3d64 24 #include "mbed_critical.h"
AnnaBridge 188:bcfe06ba3d64 25 #include "mbed_error.h"
AnnaBridge 188:bcfe06ba3d64 26
AnnaBridge 188:bcfe06ba3d64 27 #else
AnnaBridge 188:bcfe06ba3d64 28
AnnaBridge 188:bcfe06ba3d64 29 /** Adaptation layer to native Cypress environment */
AnnaBridge 188:bcfe06ba3d64 30 /* Notice, that since we use critical section here only for operations
AnnaBridge 188:bcfe06ba3d64 31 * that do not involve function calls, we can get away with using
AnnaBridge 188:bcfe06ba3d64 32 * a global static variable for interrupt status saving.
AnnaBridge 188:bcfe06ba3d64 33 */
AnnaBridge 188:bcfe06ba3d64 34
AnnaBridge 188:bcfe06ba3d64 35 #include "syslib/cy_syslib.h"
AnnaBridge 188:bcfe06ba3d64 36
AnnaBridge 188:bcfe06ba3d64 37 #define error(arg) CY_ASSERT(0)
AnnaBridge 188:bcfe06ba3d64 38 #define MBED_ASSERT CY_ASSERT
AnnaBridge 188:bcfe06ba3d64 39
AnnaBridge 188:bcfe06ba3d64 40 #define core_util_critical_section_enter() \
AnnaBridge 188:bcfe06ba3d64 41 uint32_t _last_irq_status_ = Cy_SysLib_EnterCriticalSection()
AnnaBridge 188:bcfe06ba3d64 42
AnnaBridge 188:bcfe06ba3d64 43 #define core_util_critical_section_exit() \
AnnaBridge 188:bcfe06ba3d64 44 Cy_SysLib_ExitCriticalSection(_last_irq_status_)
AnnaBridge 188:bcfe06ba3d64 45
AnnaBridge 188:bcfe06ba3d64 46 #endif /* defined(__MBED__) */
AnnaBridge 188:bcfe06ba3d64 47
AnnaBridge 189:f392fc9709a3 48 #include "cy_crypto_core_hw.h"
AnnaBridge 188:bcfe06ba3d64 49
AnnaBridge 188:bcfe06ba3d64 50 #define CY_NUM_PSOC6_PORTS 14
AnnaBridge 188:bcfe06ba3d64 51 #define CY_NUM_DIVIDER_TYPES 4
AnnaBridge 188:bcfe06ba3d64 52 #define NUM_SCB 8
AnnaBridge 188:bcfe06ba3d64 53 #define NUM_TCPWM 32
AnnaBridge 188:bcfe06ba3d64 54
AnnaBridge 188:bcfe06ba3d64 55
AnnaBridge 188:bcfe06ba3d64 56 #if defined(TARGET_MCU_PSOC6_M0) || PSOC6_DYNSRM_DISABLE || !defined(__MBED__)
AnnaBridge 188:bcfe06ba3d64 57
AnnaBridge 188:bcfe06ba3d64 58 /****************************************************************************/
AnnaBridge 188:bcfe06ba3d64 59 /* Dynamic Shared Resource Manager */
AnnaBridge 188:bcfe06ba3d64 60 /****************************************************************************/
AnnaBridge 188:bcfe06ba3d64 61 /*
AnnaBridge 188:bcfe06ba3d64 62 * This part of the code is responsible for management of the hardware
AnnaBridge 188:bcfe06ba3d64 63 * resource shared between both CPUs of the PSoC 6.
AnnaBridge 188:bcfe06ba3d64 64 * It supports allocation, freeing and conflict detection, so that never
AnnaBridge 188:bcfe06ba3d64 65 * both CPUs try to use a single resource.
AnnaBridge 188:bcfe06ba3d64 66 * It also detects conflicts arising from allocation of hardware devices
AnnaBridge 188:bcfe06ba3d64 67 * for different modes of operation and when user tries to assign multiple
AnnaBridge 188:bcfe06ba3d64 68 * functions to the same chip pin.
AnnaBridge 188:bcfe06ba3d64 69 * It supports two modes of operation:
AnnaBridge 188:bcfe06ba3d64 70 * 1. DYNAMIC (default mode)
AnnaBridge 188:bcfe06ba3d64 71 * Resource manager is run on M0 core and M4 core asks it to allocate
AnnaBridge 188:bcfe06ba3d64 72 * or free resources using RPC over IPC mechanism.
AnnaBridge 188:bcfe06ba3d64 73 * M0 core communicates with manager via local function calls.
AnnaBridge 188:bcfe06ba3d64 74 * 2. STATIC (enabled with PSOC6_DYNSRM_DISABLE compilation flag)
AnnaBridge 188:bcfe06ba3d64 75 * In this mode resources are split statically between both cores.
AnnaBridge 188:bcfe06ba3d64 76 * Targets using this mode should add psoc6_static_srm.h file to
AnnaBridge 188:bcfe06ba3d64 77 * each core folder with declarations of resources assigned to it.
AnnaBridge 188:bcfe06ba3d64 78 * See example file for details.
AnnaBridge 188:bcfe06ba3d64 79 */
AnnaBridge 188:bcfe06ba3d64 80
AnnaBridge 188:bcfe06ba3d64 81
AnnaBridge 188:bcfe06ba3d64 82 #if PSOC6_DYNSRM_DISABLE
AnnaBridge 188:bcfe06ba3d64 83
AnnaBridge 188:bcfe06ba3d64 84 #define SRM_INIT_RESOURCE(_type_, _res_, _field_, ...) \
AnnaBridge 188:bcfe06ba3d64 85 do { \
AnnaBridge 188:bcfe06ba3d64 86 struct _init_s_ { \
AnnaBridge 188:bcfe06ba3d64 87 uint8_t idx; \
AnnaBridge 188:bcfe06ba3d64 88 _type_ val; \
AnnaBridge 188:bcfe06ba3d64 89 } init[] = {{0, 0}, __VA_ARGS__}; \
AnnaBridge 188:bcfe06ba3d64 90 uint32_t i; \
AnnaBridge 188:bcfe06ba3d64 91 for (i = 1; i < sizeof(init)/sizeof(struct _init_s_); ++i) \
AnnaBridge 188:bcfe06ba3d64 92 _res_[init[i].idx]_field_ = init[i].val; \
AnnaBridge 188:bcfe06ba3d64 93 } while(0)
AnnaBridge 188:bcfe06ba3d64 94
AnnaBridge 188:bcfe06ba3d64 95 #if defined(TARGET_MCU_PSOC6_M0)
AnnaBridge 188:bcfe06ba3d64 96 /*
AnnaBridge 188:bcfe06ba3d64 97 * On M0 we start with all resources assigned to M4 and then clear reservations
AnnaBridge 188:bcfe06ba3d64 98 * for those assigned to it (M0).
AnnaBridge 188:bcfe06ba3d64 99 */
AnnaBridge 188:bcfe06ba3d64 100 #define SRM_PORT(port, pins) {(port), (uint8_t)~(pins)}
AnnaBridge 188:bcfe06ba3d64 101 #define SRM_DIVIDER(type, dividers) {(type), (uint16_t)~(dividers)}
AnnaBridge 188:bcfe06ba3d64 102 #define SRM_SCB(num) {(num), (0)}
AnnaBridge 188:bcfe06ba3d64 103 #define SRM_TCPWM(num) {(num), (0)}
AnnaBridge 188:bcfe06ba3d64 104
AnnaBridge 188:bcfe06ba3d64 105 #define DEFAULT_PORT_RES 0xff
AnnaBridge 188:bcfe06ba3d64 106 #define DEFAULT_DIVIDER_RES 0xffff
AnnaBridge 189:f392fc9709a3 107 #define DEFAULT_DIVIDER8_RES 0xffff
AnnaBridge 188:bcfe06ba3d64 108 #define DEFAULT_SCM_RES 1
AnnaBridge 188:bcfe06ba3d64 109 #define DEFAULT_TCPWM_RES 1
AnnaBridge 188:bcfe06ba3d64 110
AnnaBridge 188:bcfe06ba3d64 111 #else // defined(TARGET_MCU_PSOC6_M0)
AnnaBridge 188:bcfe06ba3d64 112
AnnaBridge 188:bcfe06ba3d64 113 #define SRM_PORT(port, pins) {(port), (pins)}
AnnaBridge 188:bcfe06ba3d64 114 #define SRM_DIVIDER(type, dividers) {(type), (dividers)}
AnnaBridge 188:bcfe06ba3d64 115 #define SRM_SCB(num) {(num), (1)}
AnnaBridge 188:bcfe06ba3d64 116 #define SRM_TCPWM(num) {(num), (1)}
AnnaBridge 188:bcfe06ba3d64 117
AnnaBridge 188:bcfe06ba3d64 118 #define DEFAULT_PORT_RES 0
AnnaBridge 188:bcfe06ba3d64 119 #define DEFAULT_DIVIDER_RES 0
AnnaBridge 188:bcfe06ba3d64 120 #define DEFAULT_DIVIDER8_RES 0
AnnaBridge 188:bcfe06ba3d64 121 #define DEFAULT_SCM_RES 0
AnnaBridge 188:bcfe06ba3d64 122 #define DEFAULT_TCPWM_RES 0
AnnaBridge 188:bcfe06ba3d64 123 #endif // defined(TARGET_MCU_PSOC6_M0)
AnnaBridge 188:bcfe06ba3d64 124
AnnaBridge 188:bcfe06ba3d64 125 #include "psoc6_static_srm.h"
AnnaBridge 188:bcfe06ba3d64 126
AnnaBridge 188:bcfe06ba3d64 127 #else // PSOC6_DYNSRM_DISABLE
AnnaBridge 188:bcfe06ba3d64 128
AnnaBridge 188:bcfe06ba3d64 129 #define DEFAULT_PORT_RES 0
AnnaBridge 188:bcfe06ba3d64 130 #define DEFAULT_DIVIDER_RES 0
AnnaBridge 188:bcfe06ba3d64 131 #define DEFAULT_DIVIDER8_RES 0x3 // dividers 0 & 1 are reserved for us_ticker
AnnaBridge 188:bcfe06ba3d64 132 #define DEFAULT_SCM_RES 0
AnnaBridge 188:bcfe06ba3d64 133 #define DEFAULT_TCPWM_RES 0x3 // 32b counters 0 & 1 are reserved for us_ticker
AnnaBridge 188:bcfe06ba3d64 134
AnnaBridge 188:bcfe06ba3d64 135 #endif // PSOC6_DYNSRM_DISABLE
AnnaBridge 188:bcfe06ba3d64 136
AnnaBridge 188:bcfe06ba3d64 137 static uint8_t port_reservations[CY_NUM_PSOC6_PORTS] = {DEFAULT_PORT_RES};
AnnaBridge 188:bcfe06ba3d64 138
AnnaBridge 188:bcfe06ba3d64 139 typedef struct {
AnnaBridge 188:bcfe06ba3d64 140 const uint32_t max_index;
AnnaBridge 188:bcfe06ba3d64 141 uint32_t current_index;
AnnaBridge 188:bcfe06ba3d64 142 uint32_t reservations;
AnnaBridge 188:bcfe06ba3d64 143 } divider_alloc_t;
AnnaBridge 188:bcfe06ba3d64 144
AnnaBridge 188:bcfe06ba3d64 145 static divider_alloc_t divider_allocations[CY_NUM_DIVIDER_TYPES] = {
AnnaBridge 189:f392fc9709a3 146 { PERI_DIV_8_NR - 1, 0, DEFAULT_DIVIDER8_RES }, // CY_SYSCLK_DIV_8_BIT
AnnaBridge 188:bcfe06ba3d64 147 { PERI_DIV_16_NR - 1, 0, DEFAULT_DIVIDER_RES }, // CY_SYSCLK_DIV_16_BIT
AnnaBridge 188:bcfe06ba3d64 148 { PERI_DIV_16_5_NR - 1, 0, DEFAULT_DIVIDER_RES }, // CY_SYSCLK_DIV_16_5_BIT
AnnaBridge 188:bcfe06ba3d64 149 { PERI_DIV_24_5_NR - 1, 0, DEFAULT_DIVIDER_RES } // CY_SYSCLK_DIV_24_5_BIT
AnnaBridge 188:bcfe06ba3d64 150 };
AnnaBridge 188:bcfe06ba3d64 151
AnnaBridge 188:bcfe06ba3d64 152 static uint8_t scb_reservations[NUM_SCB] = {DEFAULT_SCM_RES};
AnnaBridge 188:bcfe06ba3d64 153
AnnaBridge 188:bcfe06ba3d64 154 static uint8_t tcpwm_reservations[NUM_TCPWM] = {DEFAULT_TCPWM_RES};
AnnaBridge 188:bcfe06ba3d64 155
AnnaBridge 188:bcfe06ba3d64 156
AnnaBridge 188:bcfe06ba3d64 157 int cy_reserve_io_pin(PinName pin_name)
AnnaBridge 188:bcfe06ba3d64 158 {
AnnaBridge 188:bcfe06ba3d64 159 uint32_t port = CY_PORT(pin_name);
AnnaBridge 188:bcfe06ba3d64 160 uint32_t pin = CY_PIN(pin_name);
AnnaBridge 188:bcfe06ba3d64 161 int result = (-1);
AnnaBridge 188:bcfe06ba3d64 162
AnnaBridge 188:bcfe06ba3d64 163 if ((port < CY_NUM_PSOC6_PORTS) && (pin <= 7)) {
AnnaBridge 188:bcfe06ba3d64 164 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 165 if (!(port_reservations[port] & (1 << pin))) {
AnnaBridge 188:bcfe06ba3d64 166 port_reservations[port] |= (1 << pin);
AnnaBridge 188:bcfe06ba3d64 167 result = 0;
AnnaBridge 188:bcfe06ba3d64 168 }
AnnaBridge 188:bcfe06ba3d64 169 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 170 } else {
AnnaBridge 188:bcfe06ba3d64 171 error("Trying to reserve non existing port/pin!");
AnnaBridge 188:bcfe06ba3d64 172 }
AnnaBridge 188:bcfe06ba3d64 173 return result;
AnnaBridge 188:bcfe06ba3d64 174 }
AnnaBridge 188:bcfe06ba3d64 175
AnnaBridge 188:bcfe06ba3d64 176
AnnaBridge 188:bcfe06ba3d64 177 void cy_free_io_pin(PinName pin_name)
AnnaBridge 188:bcfe06ba3d64 178 {
AnnaBridge 188:bcfe06ba3d64 179 uint32_t port = CY_PORT(pin_name);
AnnaBridge 188:bcfe06ba3d64 180 uint32_t pin = CY_PIN(pin_name);
AnnaBridge 188:bcfe06ba3d64 181 int result = (-1);
AnnaBridge 188:bcfe06ba3d64 182
AnnaBridge 188:bcfe06ba3d64 183 if ((port < CY_NUM_PSOC6_PORTS) && (pin <= 7)) {
AnnaBridge 188:bcfe06ba3d64 184 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 185 if (port_reservations[port] & (1 << pin)) {
AnnaBridge 188:bcfe06ba3d64 186 port_reservations[port] &= ~(1 << pin);
AnnaBridge 188:bcfe06ba3d64 187 result = 0;
AnnaBridge 188:bcfe06ba3d64 188 }
AnnaBridge 188:bcfe06ba3d64 189 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 190 }
AnnaBridge 188:bcfe06ba3d64 191
AnnaBridge 188:bcfe06ba3d64 192 if (result) {
AnnaBridge 188:bcfe06ba3d64 193 error("Trying to free wrong port/pin.");
AnnaBridge 188:bcfe06ba3d64 194 }
AnnaBridge 188:bcfe06ba3d64 195 }
AnnaBridge 188:bcfe06ba3d64 196
AnnaBridge 188:bcfe06ba3d64 197
AnnaBridge 188:bcfe06ba3d64 198 uint32_t cy_clk_reserve_divider(cy_en_divider_types_t div_type, uint32_t div_num)
AnnaBridge 188:bcfe06ba3d64 199 {
AnnaBridge 188:bcfe06ba3d64 200 uint32_t divider = CY_INVALID_DIVIDER;
AnnaBridge 188:bcfe06ba3d64 201 divider_alloc_t *p_alloc = &divider_allocations[div_type];
AnnaBridge 188:bcfe06ba3d64 202
AnnaBridge 188:bcfe06ba3d64 203 MBED_ASSERT(div_type < CY_NUM_DIVIDER_TYPES);
AnnaBridge 188:bcfe06ba3d64 204 MBED_ASSERT(div_num <= p_alloc->max_index);
AnnaBridge 188:bcfe06ba3d64 205
AnnaBridge 188:bcfe06ba3d64 206 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 207
AnnaBridge 188:bcfe06ba3d64 208 if ((p_alloc->reservations & (1 << div_num)) == 0) {
AnnaBridge 188:bcfe06ba3d64 209 p_alloc->reservations |= (1 << div_num);
AnnaBridge 188:bcfe06ba3d64 210 divider = div_num;
AnnaBridge 188:bcfe06ba3d64 211 p_alloc->current_index = ++div_num;
AnnaBridge 188:bcfe06ba3d64 212 if (p_alloc->current_index > p_alloc->max_index) {
AnnaBridge 188:bcfe06ba3d64 213 p_alloc->current_index = 0;
AnnaBridge 188:bcfe06ba3d64 214 }
AnnaBridge 188:bcfe06ba3d64 215 }
AnnaBridge 188:bcfe06ba3d64 216
AnnaBridge 188:bcfe06ba3d64 217 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 218
AnnaBridge 188:bcfe06ba3d64 219 return divider;
AnnaBridge 188:bcfe06ba3d64 220 }
AnnaBridge 188:bcfe06ba3d64 221
AnnaBridge 188:bcfe06ba3d64 222
AnnaBridge 188:bcfe06ba3d64 223 void cy_clk_free_divider(cy_en_divider_types_t div_type, uint32_t div_num)
AnnaBridge 188:bcfe06ba3d64 224 {
AnnaBridge 188:bcfe06ba3d64 225 int result = (-1);
AnnaBridge 188:bcfe06ba3d64 226 divider_alloc_t *p_alloc = &divider_allocations[div_type];
AnnaBridge 188:bcfe06ba3d64 227
AnnaBridge 188:bcfe06ba3d64 228 MBED_ASSERT(div_type < CY_NUM_DIVIDER_TYPES);
AnnaBridge 188:bcfe06ba3d64 229 MBED_ASSERT(div_num <= p_alloc->max_index);
AnnaBridge 188:bcfe06ba3d64 230
AnnaBridge 188:bcfe06ba3d64 231 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 232
AnnaBridge 188:bcfe06ba3d64 233 if ((p_alloc->reservations & (1 << div_num)) != 0) {
AnnaBridge 188:bcfe06ba3d64 234 p_alloc->reservations &= ~(1 << div_num);
AnnaBridge 188:bcfe06ba3d64 235 result = 0;
AnnaBridge 188:bcfe06ba3d64 236 }
AnnaBridge 188:bcfe06ba3d64 237
AnnaBridge 188:bcfe06ba3d64 238 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 239
AnnaBridge 188:bcfe06ba3d64 240 if (result) {
AnnaBridge 188:bcfe06ba3d64 241 error("Trying to release wrong clock divider.");
AnnaBridge 188:bcfe06ba3d64 242 }
AnnaBridge 188:bcfe06ba3d64 243 }
AnnaBridge 188:bcfe06ba3d64 244
AnnaBridge 188:bcfe06ba3d64 245
AnnaBridge 188:bcfe06ba3d64 246 uint32_t cy_clk_allocate_divider(cy_en_divider_types_t div_type)
AnnaBridge 188:bcfe06ba3d64 247 {
AnnaBridge 188:bcfe06ba3d64 248 uint32_t divider = CY_INVALID_DIVIDER;
AnnaBridge 188:bcfe06ba3d64 249 divider_alloc_t *p_alloc = &divider_allocations[div_type];
AnnaBridge 188:bcfe06ba3d64 250
AnnaBridge 188:bcfe06ba3d64 251 MBED_ASSERT(div_type < CY_NUM_DIVIDER_TYPES);
AnnaBridge 189:f392fc9709a3 252 MBED_ASSERT(p_alloc->current_index < p_alloc->max_index);
AnnaBridge 188:bcfe06ba3d64 253
AnnaBridge 188:bcfe06ba3d64 254 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 255
AnnaBridge 189:f392fc9709a3 256 // Try to reserve current divider
AnnaBridge 189:f392fc9709a3 257 divider = cy_clk_reserve_divider(div_type, p_alloc->current_index);
AnnaBridge 188:bcfe06ba3d64 258
AnnaBridge 189:f392fc9709a3 259 if (CY_INVALID_DIVIDER == divider) {
AnnaBridge 188:bcfe06ba3d64 260
AnnaBridge 189:f392fc9709a3 261 // Store current index
AnnaBridge 189:f392fc9709a3 262 uint32_t first_index = p_alloc->current_index;
AnnaBridge 189:f392fc9709a3 263
AnnaBridge 189:f392fc9709a3 264 // Move index forward before start circular search
AnnaBridge 189:f392fc9709a3 265 ++p_alloc->current_index;
AnnaBridge 188:bcfe06ba3d64 266 if (p_alloc->current_index > p_alloc->max_index) {
AnnaBridge 188:bcfe06ba3d64 267 p_alloc->current_index = 0;
AnnaBridge 188:bcfe06ba3d64 268 }
AnnaBridge 189:f392fc9709a3 269
AnnaBridge 189:f392fc9709a3 270 // Execute circular divider search
AnnaBridge 189:f392fc9709a3 271 for (; (CY_INVALID_DIVIDER == (divider = cy_clk_reserve_divider(div_type, p_alloc->current_index)));
AnnaBridge 189:f392fc9709a3 272 ++p_alloc->current_index) {
AnnaBridge 189:f392fc9709a3 273
AnnaBridge 189:f392fc9709a3 274 if (p_alloc->current_index > p_alloc->max_index) {
AnnaBridge 189:f392fc9709a3 275 p_alloc->current_index = 0;
AnnaBridge 189:f392fc9709a3 276 }
AnnaBridge 189:f392fc9709a3 277
AnnaBridge 189:f392fc9709a3 278 if (p_alloc->current_index == first_index) {
AnnaBridge 189:f392fc9709a3 279 break;
AnnaBridge 189:f392fc9709a3 280 }
AnnaBridge 188:bcfe06ba3d64 281 }
AnnaBridge 188:bcfe06ba3d64 282 }
AnnaBridge 188:bcfe06ba3d64 283
AnnaBridge 188:bcfe06ba3d64 284 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 285
AnnaBridge 188:bcfe06ba3d64 286 return divider;
AnnaBridge 188:bcfe06ba3d64 287 }
AnnaBridge 188:bcfe06ba3d64 288
AnnaBridge 188:bcfe06ba3d64 289
AnnaBridge 188:bcfe06ba3d64 290 int cy_reserve_scb(uint32_t scb_num)
AnnaBridge 188:bcfe06ba3d64 291 {
AnnaBridge 188:bcfe06ba3d64 292 int result = (-1);
AnnaBridge 188:bcfe06ba3d64 293
AnnaBridge 188:bcfe06ba3d64 294 if (scb_num < NUM_SCB) {
AnnaBridge 188:bcfe06ba3d64 295 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 296 if (scb_reservations[scb_num] == 0) {
AnnaBridge 188:bcfe06ba3d64 297 scb_reservations[scb_num] = 1;
AnnaBridge 189:f392fc9709a3 298 result = 0;
AnnaBridge 188:bcfe06ba3d64 299 }
AnnaBridge 188:bcfe06ba3d64 300 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 301 }
AnnaBridge 188:bcfe06ba3d64 302 return result;
AnnaBridge 188:bcfe06ba3d64 303 }
AnnaBridge 188:bcfe06ba3d64 304
AnnaBridge 188:bcfe06ba3d64 305
AnnaBridge 188:bcfe06ba3d64 306 void cy_free_scb(uint32_t scb_num)
AnnaBridge 188:bcfe06ba3d64 307 {
AnnaBridge 188:bcfe06ba3d64 308 int result = (-1);
AnnaBridge 188:bcfe06ba3d64 309
AnnaBridge 188:bcfe06ba3d64 310 if (scb_num < NUM_SCB) {
AnnaBridge 188:bcfe06ba3d64 311 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 312 if (scb_reservations[scb_num] == 1) {
AnnaBridge 188:bcfe06ba3d64 313 scb_reservations[scb_num] = 0;
AnnaBridge 189:f392fc9709a3 314 result = 0;
AnnaBridge 188:bcfe06ba3d64 315 }
AnnaBridge 188:bcfe06ba3d64 316 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 317 }
AnnaBridge 188:bcfe06ba3d64 318 if (result) {
AnnaBridge 188:bcfe06ba3d64 319 error("Trying to release wrong SCB.");
AnnaBridge 188:bcfe06ba3d64 320 }
AnnaBridge 188:bcfe06ba3d64 321 }
AnnaBridge 188:bcfe06ba3d64 322
AnnaBridge 188:bcfe06ba3d64 323
AnnaBridge 188:bcfe06ba3d64 324 int cy_reserve_tcpwm(uint32_t tcpwm_num)
AnnaBridge 188:bcfe06ba3d64 325 {
AnnaBridge 188:bcfe06ba3d64 326 int result = (-1);
AnnaBridge 188:bcfe06ba3d64 327
AnnaBridge 188:bcfe06ba3d64 328 if (tcpwm_num < NUM_TCPWM) {
AnnaBridge 188:bcfe06ba3d64 329 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 330 if (tcpwm_reservations[tcpwm_num] == 0) {
AnnaBridge 188:bcfe06ba3d64 331 tcpwm_reservations[tcpwm_num] = 1;
AnnaBridge 188:bcfe06ba3d64 332 result = 0;
AnnaBridge 188:bcfe06ba3d64 333 }
AnnaBridge 188:bcfe06ba3d64 334 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 335 }
AnnaBridge 188:bcfe06ba3d64 336 return result;
AnnaBridge 188:bcfe06ba3d64 337 }
AnnaBridge 188:bcfe06ba3d64 338
AnnaBridge 188:bcfe06ba3d64 339
AnnaBridge 188:bcfe06ba3d64 340 void cy_free_tcpwm(uint32_t tcpwm_num)
AnnaBridge 188:bcfe06ba3d64 341 {
AnnaBridge 188:bcfe06ba3d64 342 int result = (-1);
AnnaBridge 188:bcfe06ba3d64 343
AnnaBridge 188:bcfe06ba3d64 344 if (tcpwm_num < NUM_TCPWM) {
AnnaBridge 188:bcfe06ba3d64 345 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 346 if (tcpwm_reservations[tcpwm_num] == 1) {
AnnaBridge 188:bcfe06ba3d64 347 tcpwm_reservations[tcpwm_num] = 0;
AnnaBridge 188:bcfe06ba3d64 348 result = 0;
AnnaBridge 188:bcfe06ba3d64 349 }
AnnaBridge 188:bcfe06ba3d64 350 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 351 }
AnnaBridge 188:bcfe06ba3d64 352 if (result) {
AnnaBridge 188:bcfe06ba3d64 353 error("Trying to release wrong TCPWM.");
AnnaBridge 188:bcfe06ba3d64 354 }
AnnaBridge 188:bcfe06ba3d64 355 }
AnnaBridge 188:bcfe06ba3d64 356
AnnaBridge 188:bcfe06ba3d64 357
AnnaBridge 189:f392fc9709a3 358 static uint8_t crypto_reservations[NUM_CRYPTO_HW] = { 0u };
AnnaBridge 189:f392fc9709a3 359
AnnaBridge 189:f392fc9709a3 360 static int cy_crypto_reserved_status(void)
AnnaBridge 189:f392fc9709a3 361 {
AnnaBridge 189:f392fc9709a3 362 return ((int)(crypto_reservations[CY_CRYPTO_TRNG_HW] |
AnnaBridge 189:f392fc9709a3 363 crypto_reservations[CY_CRYPTO_CRC_HW] |
AnnaBridge 189:f392fc9709a3 364 crypto_reservations[CY_CRYPTO_VU_HW] |
AnnaBridge 189:f392fc9709a3 365 crypto_reservations[CY_CRYPTO_COMMON_HW]));
AnnaBridge 189:f392fc9709a3 366 }
AnnaBridge 189:f392fc9709a3 367
AnnaBridge 189:f392fc9709a3 368
AnnaBridge 189:f392fc9709a3 369 int cy_reserve_crypto(cy_en_crypto_submodule_t module_num)
AnnaBridge 189:f392fc9709a3 370 {
AnnaBridge 189:f392fc9709a3 371 int result = (-1);
AnnaBridge 189:f392fc9709a3 372
AnnaBridge 189:f392fc9709a3 373 if (module_num < NUM_CRYPTO_HW)
AnnaBridge 189:f392fc9709a3 374 {
AnnaBridge 189:f392fc9709a3 375 core_util_critical_section_enter();
AnnaBridge 189:f392fc9709a3 376
AnnaBridge 189:f392fc9709a3 377 if (cy_crypto_reserved_status() == 0)
AnnaBridge 189:f392fc9709a3 378 {
AnnaBridge 189:f392fc9709a3 379 /* Enable Crypto IP on demand */
AnnaBridge 189:f392fc9709a3 380 Cy_Crypto_Core_Enable(CRYPTO);
AnnaBridge 189:f392fc9709a3 381 }
AnnaBridge 189:f392fc9709a3 382
AnnaBridge 189:f392fc9709a3 383 if (module_num == CY_CRYPTO_COMMON_HW)
AnnaBridge 189:f392fc9709a3 384 {
AnnaBridge 189:f392fc9709a3 385 if (crypto_reservations[module_num] != 1)
AnnaBridge 189:f392fc9709a3 386 {
AnnaBridge 189:f392fc9709a3 387 crypto_reservations[module_num] = 1;
AnnaBridge 189:f392fc9709a3 388 result = 0;
AnnaBridge 189:f392fc9709a3 389 }
AnnaBridge 189:f392fc9709a3 390 }
AnnaBridge 189:f392fc9709a3 391 else
AnnaBridge 189:f392fc9709a3 392 {
AnnaBridge 189:f392fc9709a3 393 crypto_reservations[module_num] = 1;
AnnaBridge 189:f392fc9709a3 394 result = 0;
AnnaBridge 189:f392fc9709a3 395 }
AnnaBridge 189:f392fc9709a3 396
AnnaBridge 189:f392fc9709a3 397 core_util_critical_section_exit();
AnnaBridge 189:f392fc9709a3 398 }
AnnaBridge 189:f392fc9709a3 399
AnnaBridge 189:f392fc9709a3 400 return result;
AnnaBridge 189:f392fc9709a3 401 }
AnnaBridge 189:f392fc9709a3 402
AnnaBridge 189:f392fc9709a3 403
AnnaBridge 189:f392fc9709a3 404 void cy_free_crypto(cy_en_crypto_submodule_t module_num)
AnnaBridge 189:f392fc9709a3 405 {
AnnaBridge 189:f392fc9709a3 406 int result = (-1);
AnnaBridge 189:f392fc9709a3 407
AnnaBridge 189:f392fc9709a3 408 if (module_num < NUM_CRYPTO_HW)
AnnaBridge 189:f392fc9709a3 409 {
AnnaBridge 189:f392fc9709a3 410 core_util_critical_section_enter();
AnnaBridge 189:f392fc9709a3 411
AnnaBridge 189:f392fc9709a3 412 if (crypto_reservations[module_num] == 1)
AnnaBridge 189:f392fc9709a3 413 {
AnnaBridge 189:f392fc9709a3 414 crypto_reservations[module_num] = 0;
AnnaBridge 189:f392fc9709a3 415
AnnaBridge 189:f392fc9709a3 416 if (cy_crypto_reserved_status() == 0)
AnnaBridge 189:f392fc9709a3 417 {
AnnaBridge 189:f392fc9709a3 418 /* Crypto hardware is still in enabled state; to disable:
AnnaBridge 189:f392fc9709a3 419 Cy_Crypto_Core_Disable(CRYPTO) */
AnnaBridge 189:f392fc9709a3 420 }
AnnaBridge 189:f392fc9709a3 421
AnnaBridge 189:f392fc9709a3 422 result = 0;
AnnaBridge 189:f392fc9709a3 423 }
AnnaBridge 189:f392fc9709a3 424 core_util_critical_section_exit();
AnnaBridge 189:f392fc9709a3 425 }
AnnaBridge 189:f392fc9709a3 426 if (result) {
AnnaBridge 189:f392fc9709a3 427 error("Trying to release wrong CRYPTO hardware submodule.");
AnnaBridge 189:f392fc9709a3 428 }
AnnaBridge 189:f392fc9709a3 429 }
AnnaBridge 189:f392fc9709a3 430
AnnaBridge 189:f392fc9709a3 431
AnnaBridge 188:bcfe06ba3d64 432 /*
AnnaBridge 188:bcfe06ba3d64 433 * NVIC channel dynamic allocation (multiplexing) is used only on M0.
AnnaBridge 188:bcfe06ba3d64 434 * On M4 IRQs are statically pre-assigned to NVIC channels.
AnnaBridge 188:bcfe06ba3d64 435 */
AnnaBridge 188:bcfe06ba3d64 436
AnnaBridge 188:bcfe06ba3d64 437 #if defined(TARGET_MCU_PSOC6_M0)
AnnaBridge 188:bcfe06ba3d64 438
AnnaBridge 188:bcfe06ba3d64 439 #define NUM_NVIC_CHANNELS ((uint32_t)(NvicMux31_IRQn - NvicMux0_IRQn) + 1)
AnnaBridge 188:bcfe06ba3d64 440
AnnaBridge 188:bcfe06ba3d64 441 static uint32_t irq_channels[NUM_NVIC_CHANNELS] = {0};
AnnaBridge 188:bcfe06ba3d64 442
AnnaBridge 188:bcfe06ba3d64 443
AnnaBridge 188:bcfe06ba3d64 444 IRQn_Type cy_m0_nvic_allocate_channel(uint32_t channel_id)
AnnaBridge 188:bcfe06ba3d64 445 {
AnnaBridge 188:bcfe06ba3d64 446 IRQn_Type alloc = (IRQn_Type)(-1);
AnnaBridge 188:bcfe06ba3d64 447 uint32_t chn;
AnnaBridge 188:bcfe06ba3d64 448 MBED_ASSERT(channel_id);
AnnaBridge 188:bcfe06ba3d64 449
AnnaBridge 188:bcfe06ba3d64 450 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 451 for (chn = 0; chn < NUM_NVIC_CHANNELS; ++chn) {
AnnaBridge 188:bcfe06ba3d64 452 if (irq_channels[chn] == 0) {
AnnaBridge 188:bcfe06ba3d64 453 irq_channels[chn] = channel_id;
AnnaBridge 188:bcfe06ba3d64 454 alloc = NvicMux0_IRQn + chn;
AnnaBridge 188:bcfe06ba3d64 455 break;
AnnaBridge 188:bcfe06ba3d64 456 irq_channels[chn] = channel_id;
AnnaBridge 188:bcfe06ba3d64 457
AnnaBridge 188:bcfe06ba3d64 458 }
AnnaBridge 188:bcfe06ba3d64 459 }
AnnaBridge 188:bcfe06ba3d64 460 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 461 return alloc;
AnnaBridge 188:bcfe06ba3d64 462 }
AnnaBridge 188:bcfe06ba3d64 463
AnnaBridge 188:bcfe06ba3d64 464 IRQn_Type cy_m0_nvic_reserve_channel(IRQn_Type channel, uint32_t channel_id)
AnnaBridge 188:bcfe06ba3d64 465 {
AnnaBridge 188:bcfe06ba3d64 466 uint32_t chn = channel - NvicMux0_IRQn;
AnnaBridge 188:bcfe06ba3d64 467
AnnaBridge 188:bcfe06ba3d64 468 MBED_ASSERT(chn < NUM_NVIC_CHANNELS);
AnnaBridge 188:bcfe06ba3d64 469 MBED_ASSERT(channel_id);
AnnaBridge 188:bcfe06ba3d64 470
AnnaBridge 188:bcfe06ba3d64 471 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 472 if (irq_channels[chn]) {
AnnaBridge 189:f392fc9709a3 473 channel = (IRQn_Type)(-1);
AnnaBridge 188:bcfe06ba3d64 474 } else {
AnnaBridge 188:bcfe06ba3d64 475 irq_channels[chn] = channel_id;
AnnaBridge 188:bcfe06ba3d64 476 }
AnnaBridge 188:bcfe06ba3d64 477 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 478 return channel;
AnnaBridge 188:bcfe06ba3d64 479 }
AnnaBridge 188:bcfe06ba3d64 480
AnnaBridge 188:bcfe06ba3d64 481 void cy_m0_nvic_release_channel(IRQn_Type channel, uint32_t channel_id)
AnnaBridge 188:bcfe06ba3d64 482 {
AnnaBridge 188:bcfe06ba3d64 483 uint32_t chn = channel - NvicMux0_IRQn;
AnnaBridge 188:bcfe06ba3d64 484
AnnaBridge 188:bcfe06ba3d64 485 MBED_ASSERT(chn < NUM_NVIC_CHANNELS);
AnnaBridge 188:bcfe06ba3d64 486 MBED_ASSERT(channel_id);
AnnaBridge 188:bcfe06ba3d64 487
AnnaBridge 188:bcfe06ba3d64 488 core_util_critical_section_enter();
AnnaBridge 188:bcfe06ba3d64 489 if (irq_channels[chn] == channel_id) {
AnnaBridge 188:bcfe06ba3d64 490 irq_channels[chn] = 0;
AnnaBridge 188:bcfe06ba3d64 491 } else {
AnnaBridge 188:bcfe06ba3d64 492 error("NVIC channel cross-check failed on release.");
AnnaBridge 188:bcfe06ba3d64 493 }
AnnaBridge 188:bcfe06ba3d64 494 core_util_critical_section_exit();
AnnaBridge 188:bcfe06ba3d64 495 }
AnnaBridge 188:bcfe06ba3d64 496
AnnaBridge 188:bcfe06ba3d64 497 #define CY_BLE_SFLASH_DIE_X_MASK (0x3Fu)
AnnaBridge 188:bcfe06ba3d64 498 #define CY_BLE_SFLASH_DIE_X_BITS (6u)
AnnaBridge 188:bcfe06ba3d64 499 #define CY_BLE_SFLASH_DIE_Y_MASK (0x3Fu)
AnnaBridge 188:bcfe06ba3d64 500 #define CY_BLE_SFLASH_DIE_Y_BITS (6u)
AnnaBridge 188:bcfe06ba3d64 501 #define CY_BLE_SFLASH_DIE_XY_BITS (CY_BLE_SFLASH_DIE_X_BITS + CY_BLE_SFLASH_DIE_Y_BITS)
AnnaBridge 188:bcfe06ba3d64 502 #define CY_BLE_SFLASH_DIE_WAFER_MASK (0x1Fu)
AnnaBridge 188:bcfe06ba3d64 503 #define CY_BLE_SFLASH_DIE_WAFER_BITS (5u)
AnnaBridge 188:bcfe06ba3d64 504 #define CY_BLE_SFLASH_DIE_XYWAFER_BITS (CY_BLE_SFLASH_DIE_XY_BITS + CY_BLE_SFLASH_DIE_WAFER_BITS)
AnnaBridge 188:bcfe06ba3d64 505 #define CY_BLE_SFLASH_DIE_LOT_MASK (0x7Fu)
AnnaBridge 188:bcfe06ba3d64 506 #define CY_BLE_SFLASH_DIE_LOT_BITS (7u)
AnnaBridge 188:bcfe06ba3d64 507
AnnaBridge 188:bcfe06ba3d64 508 static uint8_t cy_ble_deviceAddress[6] = {0x19u, 0x00u, 0x00u, 0x50u, 0xA0u, 0x00u};
AnnaBridge 188:bcfe06ba3d64 509
AnnaBridge 188:bcfe06ba3d64 510 void cy_get_bd_mac_address(uint8_t *buffer)
AnnaBridge 188:bcfe06ba3d64 511 {
AnnaBridge 188:bcfe06ba3d64 512 uint32_t bdAddrLoc;
AnnaBridge 188:bcfe06ba3d64 513 bdAddrLoc = ((uint32_t)SFLASH->DIE_X & (uint32_t)CY_BLE_SFLASH_DIE_X_MASK) |
AnnaBridge 188:bcfe06ba3d64 514 ((uint32_t)(((uint32_t)SFLASH->DIE_Y) & ((uint32_t)CY_BLE_SFLASH_DIE_Y_MASK)) <<
AnnaBridge 188:bcfe06ba3d64 515 CY_BLE_SFLASH_DIE_X_BITS) |
AnnaBridge 188:bcfe06ba3d64 516 ((uint32_t)(((uint32_t)SFLASH->DIE_WAFER) & ((uint32_t)CY_BLE_SFLASH_DIE_WAFER_MASK)) <<
AnnaBridge 188:bcfe06ba3d64 517 CY_BLE_SFLASH_DIE_XY_BITS) |
AnnaBridge 188:bcfe06ba3d64 518 ((uint32_t)(((uint32_t)SFLASH->DIE_LOT[0]) & ((uint32_t)CY_BLE_SFLASH_DIE_LOT_MASK)) <<
AnnaBridge 188:bcfe06ba3d64 519 CY_BLE_SFLASH_DIE_XYWAFER_BITS);
AnnaBridge 188:bcfe06ba3d64 520
AnnaBridge 188:bcfe06ba3d64 521 cy_ble_deviceAddress[0] = (uint8_t)bdAddrLoc;
AnnaBridge 188:bcfe06ba3d64 522 cy_ble_deviceAddress[1] = (uint8_t)(bdAddrLoc >> 8u);
AnnaBridge 188:bcfe06ba3d64 523 cy_ble_deviceAddress[2] = (uint8_t)(bdAddrLoc >> 16u);
AnnaBridge 188:bcfe06ba3d64 524
AnnaBridge 188:bcfe06ba3d64 525 for (int i = 0; i < 6; ++i) {
AnnaBridge 188:bcfe06ba3d64 526 buffer[i] = cy_ble_deviceAddress[i];
AnnaBridge 188:bcfe06ba3d64 527 }
AnnaBridge 188:bcfe06ba3d64 528 }
AnnaBridge 188:bcfe06ba3d64 529
AnnaBridge 188:bcfe06ba3d64 530 #endif // defined(TARGET_MCU_PSOC6_M0)
AnnaBridge 188:bcfe06ba3d64 531
AnnaBridge 188:bcfe06ba3d64 532 #endif // defined(TARGET_MCU_PSOC6_M0) || PSOC6_DSRM_DISABLE || !defined(__MBED__)
AnnaBridge 188:bcfe06ba3d64 533
AnnaBridge 188:bcfe06ba3d64 534 void cy_srm_initialize(void)
AnnaBridge 188:bcfe06ba3d64 535 {
AnnaBridge 189:f392fc9709a3 536 #if defined(TARGET_MCU_PSOC6_M0) || PSOC6_DYNSRM_DISABLE || !defined(__MBED__)
AnnaBridge 189:f392fc9709a3 537 uint32_t i;
AnnaBridge 189:f392fc9709a3 538
AnnaBridge 189:f392fc9709a3 539 for (i = 0; i < CY_NUM_PSOC6_PORTS; ++i) {
AnnaBridge 189:f392fc9709a3 540 port_reservations[i] = DEFAULT_PORT_RES;
AnnaBridge 189:f392fc9709a3 541 }
AnnaBridge 189:f392fc9709a3 542
AnnaBridge 189:f392fc9709a3 543 for (i = 0; i < NUM_SCB; ++i) {
AnnaBridge 189:f392fc9709a3 544 scb_reservations[i] = DEFAULT_SCM_RES;
AnnaBridge 189:f392fc9709a3 545 }
AnnaBridge 189:f392fc9709a3 546
AnnaBridge 189:f392fc9709a3 547 for (i = 0; i < NUM_TCPWM; ++i) {
AnnaBridge 189:f392fc9709a3 548 tcpwm_reservations[i] = DEFAULT_TCPWM_RES;
AnnaBridge 189:f392fc9709a3 549 }
AnnaBridge 189:f392fc9709a3 550
AnnaBridge 188:bcfe06ba3d64 551 #if PSOC6_DYNSRM_DISABLE
AnnaBridge 189:f392fc9709a3 552 #ifdef CYCFG_ASSIGNED_PORTS
AnnaBridge 189:f392fc9709a3 553 SRM_INIT_RESOURCE(uint8_t, port_reservations,, CYCFG_ASSIGNED_PORTS);
AnnaBridge 188:bcfe06ba3d64 554 #endif
AnnaBridge 189:f392fc9709a3 555 #ifdef CYCFG_ASSIGNED_DIVIDERS
AnnaBridge 189:f392fc9709a3 556 SRM_INIT_RESOURCE(uint32_t, divider_allocations, .reservations, CYCFG_ASSIGNED_DIVIDERS);
AnnaBridge 188:bcfe06ba3d64 557 #endif
AnnaBridge 189:f392fc9709a3 558 #ifdef CYCFG_ASSIGNED_SCBS
AnnaBridge 189:f392fc9709a3 559 SRM_INIT_RESOURCE(uint8_t, scb_reservations,, CYCFG_ASSIGNED_SCBS);
AnnaBridge 188:bcfe06ba3d64 560 #endif
AnnaBridge 189:f392fc9709a3 561 #ifdef CYCFG_ASSIGNED_TCPWMS
AnnaBridge 189:f392fc9709a3 562 SRM_INIT_RESOURCE(uint8_t, tcpwm_reservations,, CYCFG_ASSIGNED_TCPWMS);
AnnaBridge 188:bcfe06ba3d64 563 #endif
AnnaBridge 188:bcfe06ba3d64 564 #endif // PSOC6_DYNSRM_DISABLE
AnnaBridge 189:f392fc9709a3 565 #endif // defined(TARGET_MCU_PSOC6_M0) || PSOC6_DSRM_DISABLE || !defined(__MBED__)
AnnaBridge 188:bcfe06ba3d64 566 }
AnnaBridge 188:bcfe06ba3d64 567