mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_nand.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 167:e84263d55307
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f2xx_hal_nand.h |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
AnnaBridge | 167:e84263d55307 | 5 | * @version V1.2.1 |
AnnaBridge | 167:e84263d55307 | 6 | * @date 14-April-2017 |
<> | 144:ef7eb2e8f9f7 | 7 | * @brief Header file of NAND HAL module. |
<> | 144:ef7eb2e8f9f7 | 8 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 9 | * @attention |
<> | 144:ef7eb2e8f9f7 | 10 | * |
AnnaBridge | 167:e84263d55307 | 11 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 12 | * |
<> | 144:ef7eb2e8f9f7 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 14 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 16 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 18 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 19 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 21 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 22 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 23 | * |
<> | 144:ef7eb2e8f9f7 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 34 | * |
<> | 144:ef7eb2e8f9f7 | 35 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 36 | */ |
<> | 144:ef7eb2e8f9f7 | 37 | |
<> | 144:ef7eb2e8f9f7 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 39 | #ifndef __STM32F2xx_HAL_NAND_H |
<> | 144:ef7eb2e8f9f7 | 40 | #define __STM32F2xx_HAL_NAND_H |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 43 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 44 | #endif |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 47 | #include "stm32f2xx_ll_fsmc.h" |
<> | 144:ef7eb2e8f9f7 | 48 | |
<> | 144:ef7eb2e8f9f7 | 49 | |
<> | 144:ef7eb2e8f9f7 | 50 | /** @addtogroup STM32F2xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 51 | * @{ |
<> | 144:ef7eb2e8f9f7 | 52 | */ |
<> | 144:ef7eb2e8f9f7 | 53 | |
<> | 144:ef7eb2e8f9f7 | 54 | /** @addtogroup NAND |
<> | 144:ef7eb2e8f9f7 | 55 | * @{ |
<> | 144:ef7eb2e8f9f7 | 56 | */ |
<> | 144:ef7eb2e8f9f7 | 57 | |
<> | 144:ef7eb2e8f9f7 | 58 | /* Exported typedef ----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 59 | /* Exported types ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 60 | /** @defgroup NAND_Exported_Types NAND Exported Types |
<> | 144:ef7eb2e8f9f7 | 61 | * @{ |
<> | 144:ef7eb2e8f9f7 | 62 | */ |
<> | 144:ef7eb2e8f9f7 | 63 | |
<> | 144:ef7eb2e8f9f7 | 64 | /** |
<> | 144:ef7eb2e8f9f7 | 65 | * @brief HAL NAND State structures definition |
<> | 144:ef7eb2e8f9f7 | 66 | */ |
<> | 144:ef7eb2e8f9f7 | 67 | typedef enum |
<> | 144:ef7eb2e8f9f7 | 68 | { |
<> | 144:ef7eb2e8f9f7 | 69 | HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ |
<> | 144:ef7eb2e8f9f7 | 70 | HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ |
<> | 144:ef7eb2e8f9f7 | 71 | HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ |
<> | 144:ef7eb2e8f9f7 | 72 | HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ |
<> | 144:ef7eb2e8f9f7 | 73 | }HAL_NAND_StateTypeDef; |
<> | 144:ef7eb2e8f9f7 | 74 | |
<> | 144:ef7eb2e8f9f7 | 75 | /** |
<> | 144:ef7eb2e8f9f7 | 76 | * @brief NAND Memory electronic signature Structure definition |
<> | 144:ef7eb2e8f9f7 | 77 | */ |
<> | 144:ef7eb2e8f9f7 | 78 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 79 | { |
<> | 144:ef7eb2e8f9f7 | 80 | /*<! NAND memory electronic signature maker and device IDs */ |
<> | 144:ef7eb2e8f9f7 | 81 | |
<> | 144:ef7eb2e8f9f7 | 82 | uint8_t Maker_Id; |
<> | 144:ef7eb2e8f9f7 | 83 | |
<> | 144:ef7eb2e8f9f7 | 84 | uint8_t Device_Id; |
<> | 144:ef7eb2e8f9f7 | 85 | |
<> | 144:ef7eb2e8f9f7 | 86 | uint8_t Third_Id; |
<> | 144:ef7eb2e8f9f7 | 87 | |
<> | 144:ef7eb2e8f9f7 | 88 | uint8_t Fourth_Id; |
<> | 144:ef7eb2e8f9f7 | 89 | }NAND_IDTypeDef; |
<> | 144:ef7eb2e8f9f7 | 90 | |
<> | 144:ef7eb2e8f9f7 | 91 | /** |
<> | 144:ef7eb2e8f9f7 | 92 | * @brief NAND Memory address Structure definition |
<> | 144:ef7eb2e8f9f7 | 93 | */ |
<> | 144:ef7eb2e8f9f7 | 94 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 95 | { |
AnnaBridge | 167:e84263d55307 | 96 | uint16_t Page; /*!< NAND memory Page address */ |
<> | 144:ef7eb2e8f9f7 | 97 | |
AnnaBridge | 167:e84263d55307 | 98 | uint16_t Plane; /*!< NAND memory Plane address */ |
<> | 144:ef7eb2e8f9f7 | 99 | |
AnnaBridge | 167:e84263d55307 | 100 | uint16_t Block; /*!< NAND memory Block address */ |
<> | 144:ef7eb2e8f9f7 | 101 | |
<> | 144:ef7eb2e8f9f7 | 102 | }NAND_AddressTypeDef; |
<> | 144:ef7eb2e8f9f7 | 103 | |
<> | 144:ef7eb2e8f9f7 | 104 | /** |
<> | 144:ef7eb2e8f9f7 | 105 | * @brief NAND Memory info Structure definition |
<> | 144:ef7eb2e8f9f7 | 106 | */ |
<> | 144:ef7eb2e8f9f7 | 107 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 108 | { |
AnnaBridge | 167:e84263d55307 | 109 | uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes |
AnnaBridge | 167:e84263d55307 | 110 | for 8 bits adressing or words for 16 bits addressing */ |
<> | 144:ef7eb2e8f9f7 | 111 | |
AnnaBridge | 167:e84263d55307 | 112 | uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes |
AnnaBridge | 167:e84263d55307 | 113 | for 8 bits adressing or words for 16 bits addressing */ |
AnnaBridge | 167:e84263d55307 | 114 | |
AnnaBridge | 167:e84263d55307 | 115 | uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ |
<> | 144:ef7eb2e8f9f7 | 116 | |
AnnaBridge | 167:e84263d55307 | 117 | uint32_t BlockNbr; /*!< NAND memory number of total blocks */ |
AnnaBridge | 167:e84263d55307 | 118 | |
AnnaBridge | 167:e84263d55307 | 119 | uint32_t PlaneNbr; /*!< NAND memory number of planes */ |
AnnaBridge | 167:e84263d55307 | 120 | |
AnnaBridge | 167:e84263d55307 | 121 | uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */ |
<> | 144:ef7eb2e8f9f7 | 122 | |
AnnaBridge | 167:e84263d55307 | 123 | FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This |
AnnaBridge | 167:e84263d55307 | 124 | parameter is mandatory for some NAND parts after the read |
AnnaBridge | 167:e84263d55307 | 125 | command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. |
AnnaBridge | 167:e84263d55307 | 126 | Example: Toshiba THTH58BYG3S0HBAI6. |
AnnaBridge | 167:e84263d55307 | 127 | This parameter could be ENABLE or DISABLE |
AnnaBridge | 167:e84263d55307 | 128 | Please check the Read Mode sequnece in the NAND device datasheet */ |
AnnaBridge | 167:e84263d55307 | 129 | }NAND_DeviceConfigTypeDef; |
<> | 144:ef7eb2e8f9f7 | 130 | |
<> | 144:ef7eb2e8f9f7 | 131 | /** |
<> | 144:ef7eb2e8f9f7 | 132 | * @brief NAND handle Structure definition |
<> | 144:ef7eb2e8f9f7 | 133 | */ |
<> | 144:ef7eb2e8f9f7 | 134 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 135 | { |
AnnaBridge | 167:e84263d55307 | 136 | FSMC_NAND_TypeDef *Instance; /*!< Register base address */ |
<> | 144:ef7eb2e8f9f7 | 137 | |
AnnaBridge | 167:e84263d55307 | 138 | FSMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */ |
<> | 144:ef7eb2e8f9f7 | 139 | |
AnnaBridge | 167:e84263d55307 | 140 | HAL_LockTypeDef Lock; /*!< NAND locking object */ |
<> | 144:ef7eb2e8f9f7 | 141 | |
AnnaBridge | 167:e84263d55307 | 142 | __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ |
<> | 144:ef7eb2e8f9f7 | 143 | |
AnnaBridge | 167:e84263d55307 | 144 | NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ |
AnnaBridge | 167:e84263d55307 | 145 | |
<> | 144:ef7eb2e8f9f7 | 146 | }NAND_HandleTypeDef; |
<> | 144:ef7eb2e8f9f7 | 147 | /** |
<> | 144:ef7eb2e8f9f7 | 148 | * @} |
<> | 144:ef7eb2e8f9f7 | 149 | */ |
<> | 144:ef7eb2e8f9f7 | 150 | |
<> | 144:ef7eb2e8f9f7 | 151 | /* Exported constants --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 152 | /* Exported macros ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 153 | /** @defgroup NAND_Exported_Macros NAND Exported Macros |
<> | 144:ef7eb2e8f9f7 | 154 | * @{ |
<> | 144:ef7eb2e8f9f7 | 155 | */ |
<> | 144:ef7eb2e8f9f7 | 156 | |
<> | 144:ef7eb2e8f9f7 | 157 | /** @brief Reset NAND handle state |
<> | 144:ef7eb2e8f9f7 | 158 | * @param __HANDLE__: specifies the NAND handle. |
<> | 144:ef7eb2e8f9f7 | 159 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 160 | */ |
<> | 144:ef7eb2e8f9f7 | 161 | #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) |
<> | 144:ef7eb2e8f9f7 | 162 | |
<> | 144:ef7eb2e8f9f7 | 163 | /** |
<> | 144:ef7eb2e8f9f7 | 164 | * @} |
<> | 144:ef7eb2e8f9f7 | 165 | */ |
<> | 144:ef7eb2e8f9f7 | 166 | |
<> | 144:ef7eb2e8f9f7 | 167 | /* Exported functions --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 168 | /** @addtogroup NAND_Exported_Functions NAND Exported Functions |
<> | 144:ef7eb2e8f9f7 | 169 | * @{ |
<> | 144:ef7eb2e8f9f7 | 170 | */ |
<> | 144:ef7eb2e8f9f7 | 171 | |
<> | 144:ef7eb2e8f9f7 | 172 | /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 173 | * @{ |
<> | 144:ef7eb2e8f9f7 | 174 | */ |
<> | 144:ef7eb2e8f9f7 | 175 | |
<> | 144:ef7eb2e8f9f7 | 176 | /* Initialization/de-initialization functions ********************************/ |
<> | 144:ef7eb2e8f9f7 | 177 | HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); |
<> | 144:ef7eb2e8f9f7 | 178 | HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); |
AnnaBridge | 167:e84263d55307 | 179 | HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); |
AnnaBridge | 167:e84263d55307 | 180 | HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); |
AnnaBridge | 167:e84263d55307 | 181 | void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); |
AnnaBridge | 167:e84263d55307 | 182 | void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); |
<> | 144:ef7eb2e8f9f7 | 183 | void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); |
AnnaBridge | 167:e84263d55307 | 184 | void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); |
<> | 144:ef7eb2e8f9f7 | 185 | |
<> | 144:ef7eb2e8f9f7 | 186 | /** |
<> | 144:ef7eb2e8f9f7 | 187 | * @} |
<> | 144:ef7eb2e8f9f7 | 188 | */ |
<> | 144:ef7eb2e8f9f7 | 189 | |
<> | 144:ef7eb2e8f9f7 | 190 | /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions |
<> | 144:ef7eb2e8f9f7 | 191 | * @{ |
<> | 144:ef7eb2e8f9f7 | 192 | */ |
<> | 144:ef7eb2e8f9f7 | 193 | |
<> | 144:ef7eb2e8f9f7 | 194 | /* IO operation functions ****************************************************/ |
<> | 144:ef7eb2e8f9f7 | 195 | HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); |
AnnaBridge | 167:e84263d55307 | 196 | |
AnnaBridge | 167:e84263d55307 | 197 | HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); |
AnnaBridge | 167:e84263d55307 | 198 | HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); |
AnnaBridge | 167:e84263d55307 | 199 | HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); |
AnnaBridge | 167:e84263d55307 | 200 | HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); |
AnnaBridge | 167:e84263d55307 | 201 | |
AnnaBridge | 167:e84263d55307 | 202 | HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead); |
AnnaBridge | 167:e84263d55307 | 203 | HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite); |
AnnaBridge | 167:e84263d55307 | 204 | HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead); |
AnnaBridge | 167:e84263d55307 | 205 | HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); |
AnnaBridge | 167:e84263d55307 | 206 | |
<> | 144:ef7eb2e8f9f7 | 207 | HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); |
AnnaBridge | 167:e84263d55307 | 208 | |
<> | 144:ef7eb2e8f9f7 | 209 | uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); |
<> | 144:ef7eb2e8f9f7 | 210 | uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); |
<> | 144:ef7eb2e8f9f7 | 211 | |
<> | 144:ef7eb2e8f9f7 | 212 | /** |
<> | 144:ef7eb2e8f9f7 | 213 | * @} |
<> | 144:ef7eb2e8f9f7 | 214 | */ |
<> | 144:ef7eb2e8f9f7 | 215 | |
<> | 144:ef7eb2e8f9f7 | 216 | /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 217 | * @{ |
<> | 144:ef7eb2e8f9f7 | 218 | */ |
<> | 144:ef7eb2e8f9f7 | 219 | |
<> | 144:ef7eb2e8f9f7 | 220 | /* NAND Control functions ****************************************************/ |
<> | 144:ef7eb2e8f9f7 | 221 | HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); |
<> | 144:ef7eb2e8f9f7 | 222 | HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); |
<> | 144:ef7eb2e8f9f7 | 223 | HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); |
<> | 144:ef7eb2e8f9f7 | 224 | |
<> | 144:ef7eb2e8f9f7 | 225 | /** |
<> | 144:ef7eb2e8f9f7 | 226 | * @} |
<> | 144:ef7eb2e8f9f7 | 227 | */ |
<> | 144:ef7eb2e8f9f7 | 228 | |
<> | 144:ef7eb2e8f9f7 | 229 | /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions |
<> | 144:ef7eb2e8f9f7 | 230 | * @{ |
<> | 144:ef7eb2e8f9f7 | 231 | */ |
<> | 144:ef7eb2e8f9f7 | 232 | /* NAND State functions *******************************************************/ |
<> | 144:ef7eb2e8f9f7 | 233 | HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); |
<> | 144:ef7eb2e8f9f7 | 234 | uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); |
<> | 144:ef7eb2e8f9f7 | 235 | /** |
<> | 144:ef7eb2e8f9f7 | 236 | * @} |
<> | 144:ef7eb2e8f9f7 | 237 | */ |
<> | 144:ef7eb2e8f9f7 | 238 | |
<> | 144:ef7eb2e8f9f7 | 239 | /** |
<> | 144:ef7eb2e8f9f7 | 240 | * @} |
<> | 144:ef7eb2e8f9f7 | 241 | */ |
<> | 144:ef7eb2e8f9f7 | 242 | |
<> | 144:ef7eb2e8f9f7 | 243 | /* Private types -------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 244 | /* Private variables ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 245 | /* Private constants ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 246 | /** @defgroup NAND_Private_Constants NAND Private Constants |
<> | 144:ef7eb2e8f9f7 | 247 | * @{ |
<> | 144:ef7eb2e8f9f7 | 248 | */ |
AnnaBridge | 167:e84263d55307 | 249 | #define NAND_DEVICE1 0x70000000U |
AnnaBridge | 167:e84263d55307 | 250 | #define NAND_DEVICE2 0x80000000U |
AnnaBridge | 167:e84263d55307 | 251 | #define NAND_WRITE_TIMEOUT 0x01000000U |
<> | 144:ef7eb2e8f9f7 | 252 | |
<> | 144:ef7eb2e8f9f7 | 253 | #define CMD_AREA ((uint32_t)(1U<<16U)) /* A16 = CLE high */ |
<> | 144:ef7eb2e8f9f7 | 254 | #define ADDR_AREA ((uint32_t)(1U<<17U)) /* A17 = ALE high */ |
<> | 144:ef7eb2e8f9f7 | 255 | |
AnnaBridge | 167:e84263d55307 | 256 | #define NAND_CMD_AREA_A ((uint8_t)0x00) |
AnnaBridge | 167:e84263d55307 | 257 | #define NAND_CMD_AREA_B ((uint8_t)0x01) |
AnnaBridge | 167:e84263d55307 | 258 | #define NAND_CMD_AREA_C ((uint8_t)0x50) |
AnnaBridge | 167:e84263d55307 | 259 | #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) |
<> | 144:ef7eb2e8f9f7 | 260 | |
AnnaBridge | 167:e84263d55307 | 261 | #define NAND_CMD_WRITE0 ((uint8_t)0x80) |
AnnaBridge | 167:e84263d55307 | 262 | #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) |
AnnaBridge | 167:e84263d55307 | 263 | #define NAND_CMD_ERASE0 ((uint8_t)0x60) |
AnnaBridge | 167:e84263d55307 | 264 | #define NAND_CMD_ERASE1 ((uint8_t)0xD0) |
AnnaBridge | 167:e84263d55307 | 265 | #define NAND_CMD_READID ((uint8_t)0x90) |
AnnaBridge | 167:e84263d55307 | 266 | #define NAND_CMD_STATUS ((uint8_t)0x70) |
AnnaBridge | 167:e84263d55307 | 267 | #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) |
AnnaBridge | 167:e84263d55307 | 268 | #define NAND_CMD_RESET ((uint8_t)0xFF) |
<> | 144:ef7eb2e8f9f7 | 269 | |
<> | 144:ef7eb2e8f9f7 | 270 | /* NAND memory status */ |
AnnaBridge | 167:e84263d55307 | 271 | #define NAND_VALID_ADDRESS 0x00000100U |
AnnaBridge | 167:e84263d55307 | 272 | #define NAND_INVALID_ADDRESS 0x00000200U |
AnnaBridge | 167:e84263d55307 | 273 | #define NAND_TIMEOUT_ERROR 0x00000400U |
AnnaBridge | 167:e84263d55307 | 274 | #define NAND_BUSY 0x00000000U |
AnnaBridge | 167:e84263d55307 | 275 | #define NAND_ERROR 0x00000001U |
AnnaBridge | 167:e84263d55307 | 276 | #define NAND_READY 0x00000040U |
<> | 144:ef7eb2e8f9f7 | 277 | /** |
<> | 144:ef7eb2e8f9f7 | 278 | * @} |
<> | 144:ef7eb2e8f9f7 | 279 | */ |
<> | 144:ef7eb2e8f9f7 | 280 | |
<> | 144:ef7eb2e8f9f7 | 281 | /* Private macros ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 282 | /** @defgroup NAND_Private_Macros NAND Private Macros |
<> | 144:ef7eb2e8f9f7 | 283 | * @{ |
<> | 144:ef7eb2e8f9f7 | 284 | */ |
<> | 144:ef7eb2e8f9f7 | 285 | |
<> | 144:ef7eb2e8f9f7 | 286 | /** |
<> | 144:ef7eb2e8f9f7 | 287 | * @brief NAND memory address computation. |
<> | 144:ef7eb2e8f9f7 | 288 | * @param __ADDRESS__: NAND memory address. |
<> | 144:ef7eb2e8f9f7 | 289 | * @param __HANDLE__ : NAND handle. |
<> | 144:ef7eb2e8f9f7 | 290 | * @retval NAND Raw address value |
<> | 144:ef7eb2e8f9f7 | 291 | */ |
<> | 144:ef7eb2e8f9f7 | 292 | #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ |
AnnaBridge | 167:e84263d55307 | 293 | (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) |
AnnaBridge | 167:e84263d55307 | 294 | |
AnnaBridge | 167:e84263d55307 | 295 | /** |
AnnaBridge | 167:e84263d55307 | 296 | * @brief NAND memory Column address computation. |
AnnaBridge | 167:e84263d55307 | 297 | * @param __HANDLE__: NAND handle. |
AnnaBridge | 167:e84263d55307 | 298 | * @retval NAND Raw address value |
AnnaBridge | 167:e84263d55307 | 299 | */ |
AnnaBridge | 167:e84263d55307 | 300 | #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) |
<> | 144:ef7eb2e8f9f7 | 301 | |
<> | 144:ef7eb2e8f9f7 | 302 | /** |
<> | 144:ef7eb2e8f9f7 | 303 | * @brief NAND memory address cycling. |
<> | 144:ef7eb2e8f9f7 | 304 | * @param __ADDRESS__: NAND memory address. |
<> | 144:ef7eb2e8f9f7 | 305 | * @retval NAND address cycling value. |
<> | 144:ef7eb2e8f9f7 | 306 | */ |
<> | 144:ef7eb2e8f9f7 | 307 | #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ |
<> | 144:ef7eb2e8f9f7 | 308 | #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8U) /* 2nd addressing cycle */ |
<> | 144:ef7eb2e8f9f7 | 309 | #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16U) /* 3rd addressing cycle */ |
<> | 144:ef7eb2e8f9f7 | 310 | #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24U) /* 4th addressing cycle */ |
<> | 144:ef7eb2e8f9f7 | 311 | /** |
AnnaBridge | 167:e84263d55307 | 312 | * @brief NAND memory Columns cycling. |
AnnaBridge | 167:e84263d55307 | 313 | * @param __ADDRESS__: NAND memory address. |
AnnaBridge | 167:e84263d55307 | 314 | * @retval NAND Column address cycling value. |
<> | 144:ef7eb2e8f9f7 | 315 | */ |
AnnaBridge | 167:e84263d55307 | 316 | #define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */ |
AnnaBridge | 167:e84263d55307 | 317 | #define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ |
<> | 144:ef7eb2e8f9f7 | 318 | |
<> | 144:ef7eb2e8f9f7 | 319 | |
<> | 144:ef7eb2e8f9f7 | 320 | /** |
<> | 144:ef7eb2e8f9f7 | 321 | * @} |
<> | 144:ef7eb2e8f9f7 | 322 | */ |
<> | 144:ef7eb2e8f9f7 | 323 | /** |
<> | 144:ef7eb2e8f9f7 | 324 | * @} |
<> | 144:ef7eb2e8f9f7 | 325 | */ |
<> | 144:ef7eb2e8f9f7 | 326 | |
<> | 144:ef7eb2e8f9f7 | 327 | /** |
<> | 144:ef7eb2e8f9f7 | 328 | * @} |
<> | 144:ef7eb2e8f9f7 | 329 | */ |
<> | 144:ef7eb2e8f9f7 | 330 | |
<> | 144:ef7eb2e8f9f7 | 331 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 332 | } |
<> | 144:ef7eb2e8f9f7 | 333 | #endif |
<> | 144:ef7eb2e8f9f7 | 334 | |
<> | 144:ef7eb2e8f9f7 | 335 | #endif /* __STM32F2xx_HAL_NAND_H */ |
<> | 144:ef7eb2e8f9f7 | 336 | |
<> | 144:ef7eb2e8f9f7 | 337 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |