mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 180:96ed750bd169
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f0xx_hal_uart_ex.h |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 156:95d6b41a828b | 5 | * @brief Header file of UART HAL Extended module. |
<> | 144:ef7eb2e8f9f7 | 6 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 7 | * @attention |
<> | 144:ef7eb2e8f9f7 | 8 | * |
<> | 144:ef7eb2e8f9f7 | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 12 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 14 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 16 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 17 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 19 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 20 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 21 | * |
<> | 144:ef7eb2e8f9f7 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 32 | * |
<> | 144:ef7eb2e8f9f7 | 33 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 34 | */ |
<> | 144:ef7eb2e8f9f7 | 35 | |
<> | 144:ef7eb2e8f9f7 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 37 | #ifndef __STM32F0xx_HAL_UART_EX_H |
<> | 144:ef7eb2e8f9f7 | 38 | #define __STM32F0xx_HAL_UART_EX_H |
<> | 144:ef7eb2e8f9f7 | 39 | |
<> | 144:ef7eb2e8f9f7 | 40 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 41 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 42 | #endif |
<> | 144:ef7eb2e8f9f7 | 43 | |
<> | 144:ef7eb2e8f9f7 | 44 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 45 | #include "stm32f0xx_hal_def.h" |
<> | 144:ef7eb2e8f9f7 | 46 | |
<> | 144:ef7eb2e8f9f7 | 47 | /** @addtogroup STM32F0xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 48 | * @{ |
<> | 144:ef7eb2e8f9f7 | 49 | */ |
<> | 144:ef7eb2e8f9f7 | 50 | |
<> | 144:ef7eb2e8f9f7 | 51 | /** @addtogroup UARTEx |
<> | 144:ef7eb2e8f9f7 | 52 | * @{ |
<> | 144:ef7eb2e8f9f7 | 53 | */ |
<> | 144:ef7eb2e8f9f7 | 54 | |
<> | 144:ef7eb2e8f9f7 | 55 | /* Exported types ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 56 | #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) |
<> | 144:ef7eb2e8f9f7 | 57 | /** @defgroup UARTEx_Exported_Types UARTEx Exported Types |
<> | 144:ef7eb2e8f9f7 | 58 | * @{ |
<> | 144:ef7eb2e8f9f7 | 59 | */ |
<> | 144:ef7eb2e8f9f7 | 60 | |
<> | 144:ef7eb2e8f9f7 | 61 | /** |
<> | 144:ef7eb2e8f9f7 | 62 | * @brief UART wake up from stop mode parameters |
<> | 144:ef7eb2e8f9f7 | 63 | */ |
<> | 144:ef7eb2e8f9f7 | 64 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 65 | { |
<> | 144:ef7eb2e8f9f7 | 66 | uint32_t WakeUpEvent; /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF). |
<> | 144:ef7eb2e8f9f7 | 67 | This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. |
<> | 144:ef7eb2e8f9f7 | 68 | If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must |
<> | 144:ef7eb2e8f9f7 | 69 | be filled up. */ |
<> | 144:ef7eb2e8f9f7 | 70 | |
<> | 144:ef7eb2e8f9f7 | 71 | uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. |
<> | 156:95d6b41a828b | 72 | This parameter can be a value of @ref UART_WakeUp_Address_Length. */ |
<> | 144:ef7eb2e8f9f7 | 73 | |
<> | 156:95d6b41a828b | 74 | uint8_t Address; /*!< UART/USART node address (7-bit long max). */ |
<> | 144:ef7eb2e8f9f7 | 75 | } UART_WakeUpTypeDef; |
<> | 144:ef7eb2e8f9f7 | 76 | |
<> | 144:ef7eb2e8f9f7 | 77 | /** |
<> | 144:ef7eb2e8f9f7 | 78 | * @} |
<> | 144:ef7eb2e8f9f7 | 79 | */ |
<> | 144:ef7eb2e8f9f7 | 80 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ |
<> | 144:ef7eb2e8f9f7 | 81 | |
<> | 144:ef7eb2e8f9f7 | 82 | /* Exported constants --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 83 | /** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants |
<> | 144:ef7eb2e8f9f7 | 84 | * @{ |
<> | 144:ef7eb2e8f9f7 | 85 | */ |
<> | 144:ef7eb2e8f9f7 | 86 | |
<> | 144:ef7eb2e8f9f7 | 87 | /** @defgroup UARTEx_Word_Length UARTEx Word Length |
<> | 144:ef7eb2e8f9f7 | 88 | * @{ |
<> | 144:ef7eb2e8f9f7 | 89 | */ |
<> | 144:ef7eb2e8f9f7 | 90 | #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ |
<> | 144:ef7eb2e8f9f7 | 91 | defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ |
<> | 144:ef7eb2e8f9f7 | 92 | defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) |
<> | 156:95d6b41a828b | 93 | #define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long UART frame */ |
<> | 156:95d6b41a828b | 94 | #define UART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long UART frame */ |
<> | 156:95d6b41a828b | 95 | #define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long UART frame */ |
<> | 144:ef7eb2e8f9f7 | 96 | #else |
<> | 156:95d6b41a828b | 97 | #define UART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long UART frame */ |
<> | 156:95d6b41a828b | 98 | #define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long UART frame */ |
<> | 144:ef7eb2e8f9f7 | 99 | #endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ |
<> | 144:ef7eb2e8f9f7 | 100 | defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ |
<> | 144:ef7eb2e8f9f7 | 101 | defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */ |
<> | 144:ef7eb2e8f9f7 | 102 | /** |
<> | 144:ef7eb2e8f9f7 | 103 | * @} |
<> | 144:ef7eb2e8f9f7 | 104 | */ |
<> | 144:ef7eb2e8f9f7 | 105 | |
<> | 144:ef7eb2e8f9f7 | 106 | /** @defgroup UARTEx_AutoBaud_Rate_Mode UARTEx Advanced Feature AutoBaud Rate Mode |
<> | 144:ef7eb2e8f9f7 | 107 | * @{ |
<> | 144:ef7eb2e8f9f7 | 108 | */ |
<> | 144:ef7eb2e8f9f7 | 109 | #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ |
<> | 144:ef7eb2e8f9f7 | 110 | defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ |
<> | 144:ef7eb2e8f9f7 | 111 | defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) |
<> | 156:95d6b41a828b | 112 | #define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT (0x00000000U) /*!< Auto Baud rate detection on start bit */ |
<> | 144:ef7eb2e8f9f7 | 113 | #define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) /*!< Auto Baud rate detection on falling edge */ |
<> | 144:ef7eb2e8f9f7 | 114 | #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) /*!< Auto Baud rate detection on 0x7F frame detection */ |
<> | 144:ef7eb2e8f9f7 | 115 | #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) /*!< Auto Baud rate detection on 0x55 frame detection */ |
<> | 144:ef7eb2e8f9f7 | 116 | #else |
<> | 156:95d6b41a828b | 117 | #define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT (0x00000000U) /*!< Auto Baud rate detection on start bit */ |
<> | 144:ef7eb2e8f9f7 | 118 | #define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) /*!< Auto Baud rate detection on falling edge */ |
<> | 144:ef7eb2e8f9f7 | 119 | #endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ |
<> | 144:ef7eb2e8f9f7 | 120 | defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ |
<> | 144:ef7eb2e8f9f7 | 121 | defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */ |
<> | 144:ef7eb2e8f9f7 | 122 | /** |
<> | 144:ef7eb2e8f9f7 | 123 | * @} |
<> | 156:95d6b41a828b | 124 | */ |
<> | 144:ef7eb2e8f9f7 | 125 | |
<> | 144:ef7eb2e8f9f7 | 126 | #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) |
<> | 144:ef7eb2e8f9f7 | 127 | /** @defgroup UARTEx_LIN UARTEx Local Interconnection Network mode |
<> | 144:ef7eb2e8f9f7 | 128 | * @{ |
<> | 144:ef7eb2e8f9f7 | 129 | */ |
<> | 156:95d6b41a828b | 130 | #define UART_LIN_DISABLE (0x00000000U) /*!< Local Interconnect Network disable */ |
<> | 144:ef7eb2e8f9f7 | 131 | #define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) /*!< Local Interconnect Network enable */ |
<> | 144:ef7eb2e8f9f7 | 132 | /** |
<> | 144:ef7eb2e8f9f7 | 133 | * @} |
<> | 156:95d6b41a828b | 134 | */ |
<> | 156:95d6b41a828b | 135 | |
<> | 144:ef7eb2e8f9f7 | 136 | /** @defgroup UARTEx_LIN_Break_Detection UARTEx LIN Break Detection |
<> | 144:ef7eb2e8f9f7 | 137 | * @{ |
<> | 144:ef7eb2e8f9f7 | 138 | */ |
<> | 156:95d6b41a828b | 139 | #define UART_LINBREAKDETECTLENGTH_10B (0x00000000U) /*!< LIN 10-bit break detection length */ |
<> | 144:ef7eb2e8f9f7 | 140 | #define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) /*!< LIN 11-bit break detection length */ |
<> | 144:ef7eb2e8f9f7 | 141 | /** |
<> | 144:ef7eb2e8f9f7 | 142 | * @} |
<> | 156:95d6b41a828b | 143 | */ |
<> | 144:ef7eb2e8f9f7 | 144 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ |
<> | 144:ef7eb2e8f9f7 | 145 | |
<> | 144:ef7eb2e8f9f7 | 146 | /** @defgroup UART_Flags UARTEx Status Flags |
<> | 144:ef7eb2e8f9f7 | 147 | * Elements values convention: 0xXXXX |
<> | 144:ef7eb2e8f9f7 | 148 | * - 0xXXXX : Flag mask in the ISR register |
<> | 144:ef7eb2e8f9f7 | 149 | * @{ |
<> | 144:ef7eb2e8f9f7 | 150 | */ |
<> | 144:ef7eb2e8f9f7 | 151 | #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) |
<> | 156:95d6b41a828b | 152 | #define UART_FLAG_REACK (0x00400000U) /*!< UART receive enable acknowledge flag */ |
<> | 144:ef7eb2e8f9f7 | 153 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ |
<> | 156:95d6b41a828b | 154 | #define UART_FLAG_TEACK (0x00200000U) /*!< UART transmit enable acknowledge flag */ |
<> | 144:ef7eb2e8f9f7 | 155 | #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) |
<> | 156:95d6b41a828b | 156 | #define UART_FLAG_WUF (0x00100000U) /*!< UART wake-up from stop mode flag */ |
<> | 144:ef7eb2e8f9f7 | 157 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ |
<> | 156:95d6b41a828b | 158 | #define UART_FLAG_RWU (0x00080000U) /*!< UART receiver wake-up from mute mode flag */ |
<> | 156:95d6b41a828b | 159 | #define UART_FLAG_SBKF (0x00040000U) /*!< UART send break flag */ |
<> | 156:95d6b41a828b | 160 | #define UART_FLAG_CMF (0x00020000U) /*!< UART character match flag */ |
<> | 156:95d6b41a828b | 161 | #define UART_FLAG_BUSY (0x00010000U) /*!< UART busy flag */ |
<> | 156:95d6b41a828b | 162 | #define UART_FLAG_ABRF (0x00008000U) /*!< UART auto Baud rate flag */ |
<> | 156:95d6b41a828b | 163 | #define UART_FLAG_ABRE (0x00004000U) /*!< UART auto Baud rate error */ |
<> | 144:ef7eb2e8f9f7 | 164 | #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) |
<> | 156:95d6b41a828b | 165 | #define UART_FLAG_EOBF (0x00001000U) /*!< UART end of block flag */ |
<> | 144:ef7eb2e8f9f7 | 166 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ |
<> | 156:95d6b41a828b | 167 | #define UART_FLAG_RTOF (0x00000800U) /*!< UART receiver timeout flag */ |
<> | 156:95d6b41a828b | 168 | #define UART_FLAG_CTS (0x00000400U) /*!< UART clear to send flag */ |
<> | 156:95d6b41a828b | 169 | #define UART_FLAG_CTSIF (0x00000200U) /*!< UART clear to send interrupt flag */ |
<> | 144:ef7eb2e8f9f7 | 170 | #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) |
<> | 156:95d6b41a828b | 171 | #define UART_FLAG_LBDF (0x00000100U) /*!< UART LIN break detection flag (not available on F030xx devices)*/ |
<> | 144:ef7eb2e8f9f7 | 172 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ |
<> | 156:95d6b41a828b | 173 | #define UART_FLAG_TXE (0x00000080U) /*!< UART transmit data register empty */ |
<> | 156:95d6b41a828b | 174 | #define UART_FLAG_TC (0x00000040U) /*!< UART transmission complete */ |
<> | 156:95d6b41a828b | 175 | #define UART_FLAG_RXNE (0x00000020U) /*!< UART read data register not empty */ |
<> | 156:95d6b41a828b | 176 | #define UART_FLAG_IDLE (0x00000010U) /*!< UART idle flag */ |
<> | 156:95d6b41a828b | 177 | #define UART_FLAG_ORE (0x00000008U) /*!< UART overrun error */ |
<> | 156:95d6b41a828b | 178 | #define UART_FLAG_NE (0x00000004U) /*!< UART noise error */ |
<> | 156:95d6b41a828b | 179 | #define UART_FLAG_FE (0x00000002U) /*!< UART frame error */ |
<> | 156:95d6b41a828b | 180 | #define UART_FLAG_PE (0x00000001U) /*!< UART parity error */ |
<> | 144:ef7eb2e8f9f7 | 181 | /** |
<> | 144:ef7eb2e8f9f7 | 182 | * @} |
<> | 144:ef7eb2e8f9f7 | 183 | */ |
<> | 144:ef7eb2e8f9f7 | 184 | |
<> | 144:ef7eb2e8f9f7 | 185 | /** @defgroup UART_Interrupt_definition UARTEx Interrupts Definition |
<> | 156:95d6b41a828b | 186 | * Elements values convention: 000ZZZZZ0XXYYYYYb |
<> | 144:ef7eb2e8f9f7 | 187 | * - YYYYY : Interrupt source position in the XX register (5bits) |
<> | 144:ef7eb2e8f9f7 | 188 | * - XX : Interrupt source register (2bits) |
<> | 144:ef7eb2e8f9f7 | 189 | * - 01: CR1 register |
<> | 144:ef7eb2e8f9f7 | 190 | * - 10: CR2 register |
<> | 144:ef7eb2e8f9f7 | 191 | * - 11: CR3 register |
<> | 144:ef7eb2e8f9f7 | 192 | * - ZZZZZ : Flag position in the ISR register(5bits) |
<> | 156:95d6b41a828b | 193 | * @{ |
<> | 156:95d6b41a828b | 194 | */ |
<> | 156:95d6b41a828b | 195 | #define UART_IT_PE (0x0028U) /*!< UART parity error interruption */ |
<> | 156:95d6b41a828b | 196 | #define UART_IT_TXE (0x0727U) /*!< UART transmit data register empty interruption */ |
<> | 156:95d6b41a828b | 197 | #define UART_IT_TC (0x0626U) /*!< UART transmission complete interruption */ |
<> | 156:95d6b41a828b | 198 | #define UART_IT_RXNE (0x0525U) /*!< UART read data register not empty interruption */ |
<> | 156:95d6b41a828b | 199 | #define UART_IT_IDLE (0x0424U) /*!< UART idle interruption */ |
<> | 144:ef7eb2e8f9f7 | 200 | #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) |
<> | 156:95d6b41a828b | 201 | #define UART_IT_LBD (0x0846U) /*!< UART LIN break detection interruption */ |
<> | 144:ef7eb2e8f9f7 | 202 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ |
<> | 156:95d6b41a828b | 203 | #define UART_IT_CTS (0x096AU) /*!< UART CTS interruption */ |
<> | 156:95d6b41a828b | 204 | #define UART_IT_CM (0x112EU) /*!< UART character match interruption */ |
<> | 144:ef7eb2e8f9f7 | 205 | #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) |
<> | 156:95d6b41a828b | 206 | #define UART_IT_WUF (0x1476U) /*!< UART wake-up from stop mode interruption */ |
<> | 144:ef7eb2e8f9f7 | 207 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ |
<> | 144:ef7eb2e8f9f7 | 208 | /** |
<> | 144:ef7eb2e8f9f7 | 209 | * @} |
<> | 144:ef7eb2e8f9f7 | 210 | */ |
<> | 144:ef7eb2e8f9f7 | 211 | |
<> | 144:ef7eb2e8f9f7 | 212 | |
<> | 144:ef7eb2e8f9f7 | 213 | /** @defgroup UART_IT_CLEAR_Flags UARTEx Interruption Clear Flags |
<> | 144:ef7eb2e8f9f7 | 214 | * @{ |
<> | 144:ef7eb2e8f9f7 | 215 | */ |
<> | 156:95d6b41a828b | 216 | #define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ |
<> | 156:95d6b41a828b | 217 | #define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ |
<> | 156:95d6b41a828b | 218 | #define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ |
<> | 156:95d6b41a828b | 219 | #define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ |
<> | 156:95d6b41a828b | 220 | #define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ |
<> | 156:95d6b41a828b | 221 | #define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ |
<> | 144:ef7eb2e8f9f7 | 222 | #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) |
<> | 144:ef7eb2e8f9f7 | 223 | #define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag (not available on F030xx devices)*/ |
<> | 144:ef7eb2e8f9f7 | 224 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ |
<> | 156:95d6b41a828b | 225 | #define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ |
<> | 156:95d6b41a828b | 226 | #define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */ |
<> | 144:ef7eb2e8f9f7 | 227 | #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) |
<> | 156:95d6b41a828b | 228 | #define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */ |
<> | 144:ef7eb2e8f9f7 | 229 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ |
<> | 156:95d6b41a828b | 230 | #define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ |
<> | 144:ef7eb2e8f9f7 | 231 | #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) |
<> | 144:ef7eb2e8f9f7 | 232 | #define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ |
<> | 144:ef7eb2e8f9f7 | 233 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ |
<> | 144:ef7eb2e8f9f7 | 234 | /** |
<> | 144:ef7eb2e8f9f7 | 235 | * @} |
<> | 156:95d6b41a828b | 236 | */ |
<> | 144:ef7eb2e8f9f7 | 237 | |
<> | 144:ef7eb2e8f9f7 | 238 | /** @defgroup UART_Request_Parameters UARTEx Request Parameters |
<> | 144:ef7eb2e8f9f7 | 239 | * @{ |
<> | 144:ef7eb2e8f9f7 | 240 | */ |
<> | 156:95d6b41a828b | 241 | #define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */ |
<> | 156:95d6b41a828b | 242 | #define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */ |
<> | 156:95d6b41a828b | 243 | #define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */ |
<> | 156:95d6b41a828b | 244 | #define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ |
<> | 144:ef7eb2e8f9f7 | 245 | #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) |
<> | 156:95d6b41a828b | 246 | #define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ |
<> | 144:ef7eb2e8f9f7 | 247 | #else |
<> | 144:ef7eb2e8f9f7 | 248 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ |
<> | 144:ef7eb2e8f9f7 | 249 | /** |
<> | 144:ef7eb2e8f9f7 | 250 | * @} |
<> | 144:ef7eb2e8f9f7 | 251 | */ |
<> | 144:ef7eb2e8f9f7 | 252 | |
<> | 144:ef7eb2e8f9f7 | 253 | #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) |
<> | 144:ef7eb2e8f9f7 | 254 | /** @defgroup UART_Stop_Mode_Enable UARTEx Advanced Feature Stop Mode Enable |
<> | 144:ef7eb2e8f9f7 | 255 | * @{ |
<> | 144:ef7eb2e8f9f7 | 256 | */ |
<> | 156:95d6b41a828b | 257 | #define UART_ADVFEATURE_STOPMODE_DISABLE (0x00000000U) /*!< UART stop mode disable */ |
<> | 144:ef7eb2e8f9f7 | 258 | #define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM) /*!< UART stop mode enable */ |
<> | 144:ef7eb2e8f9f7 | 259 | /** |
<> | 144:ef7eb2e8f9f7 | 260 | * @} |
<> | 156:95d6b41a828b | 261 | */ |
<> | 144:ef7eb2e8f9f7 | 262 | |
<> | 144:ef7eb2e8f9f7 | 263 | /** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection |
<> | 144:ef7eb2e8f9f7 | 264 | * @{ |
<> | 144:ef7eb2e8f9f7 | 265 | */ |
<> | 156:95d6b41a828b | 266 | #define UART_WAKEUP_ON_ADDRESS (0x00000000U) /*!< UART wake-up on address */ |
<> | 144:ef7eb2e8f9f7 | 267 | #define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1) /*!< UART wake-up on start bit */ |
<> | 144:ef7eb2e8f9f7 | 268 | #define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS) /*!< UART wake-up on receive data register not empty */ |
<> | 144:ef7eb2e8f9f7 | 269 | /** |
<> | 144:ef7eb2e8f9f7 | 270 | * @} |
<> | 144:ef7eb2e8f9f7 | 271 | */ |
<> | 144:ef7eb2e8f9f7 | 272 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ |
<> | 144:ef7eb2e8f9f7 | 273 | |
<> | 144:ef7eb2e8f9f7 | 274 | /** |
<> | 144:ef7eb2e8f9f7 | 275 | * @} |
<> | 144:ef7eb2e8f9f7 | 276 | */ |
<> | 144:ef7eb2e8f9f7 | 277 | |
<> | 144:ef7eb2e8f9f7 | 278 | /* Exported macros ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 279 | /** @defgroup UARTEx_Exported_Macros UARTEx Exported Macros |
<> | 144:ef7eb2e8f9f7 | 280 | * @{ |
<> | 144:ef7eb2e8f9f7 | 281 | */ |
<> | 144:ef7eb2e8f9f7 | 282 | |
<> | 144:ef7eb2e8f9f7 | 283 | /** @brief Flush the UART Data registers. |
Anna Bridge |
180:96ed750bd169 | 284 | * @param __HANDLE__ specifies the UART Handle. |
<> | 156:95d6b41a828b | 285 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 286 | */ |
<> | 144:ef7eb2e8f9f7 | 287 | #if !defined(STM32F030x6) && !defined(STM32F030x8) |
<> | 144:ef7eb2e8f9f7 | 288 | #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ |
<> | 144:ef7eb2e8f9f7 | 289 | do{ \ |
<> | 144:ef7eb2e8f9f7 | 290 | SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ |
<> | 144:ef7eb2e8f9f7 | 291 | SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ |
<> | 144:ef7eb2e8f9f7 | 292 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 293 | #else |
<> | 144:ef7eb2e8f9f7 | 294 | #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ |
<> | 144:ef7eb2e8f9f7 | 295 | do{ \ |
<> | 144:ef7eb2e8f9f7 | 296 | SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ |
<> | 144:ef7eb2e8f9f7 | 297 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 298 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ |
<> | 144:ef7eb2e8f9f7 | 299 | |
<> | 144:ef7eb2e8f9f7 | 300 | /** |
<> | 144:ef7eb2e8f9f7 | 301 | * @} |
<> | 144:ef7eb2e8f9f7 | 302 | */ |
<> | 144:ef7eb2e8f9f7 | 303 | |
<> | 144:ef7eb2e8f9f7 | 304 | /* Private macros ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 305 | /** @defgroup UARTEx_Private_Macros UARTEx Private Macros |
<> | 144:ef7eb2e8f9f7 | 306 | * @{ |
<> | 144:ef7eb2e8f9f7 | 307 | */ |
<> | 144:ef7eb2e8f9f7 | 308 | |
<> | 144:ef7eb2e8f9f7 | 309 | /** @brief Report the UART clock source. |
Anna Bridge |
180:96ed750bd169 | 310 | * @param __HANDLE__ specifies the UART Handle. |
Anna Bridge |
180:96ed750bd169 | 311 | * @param __CLOCKSOURCE__ output variable. |
<> | 144:ef7eb2e8f9f7 | 312 | * @retval UART clocking source, written in __CLOCKSOURCE__. |
<> | 144:ef7eb2e8f9f7 | 313 | */ |
<> | 144:ef7eb2e8f9f7 | 314 | #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) |
<> | 144:ef7eb2e8f9f7 | 315 | #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ |
<> | 144:ef7eb2e8f9f7 | 316 | do { \ |
<> | 144:ef7eb2e8f9f7 | 317 | switch(__HAL_RCC_GET_USART1_SOURCE()) \ |
<> | 144:ef7eb2e8f9f7 | 318 | { \ |
<> | 144:ef7eb2e8f9f7 | 319 | case RCC_USART1CLKSOURCE_PCLK1: \ |
<> | 144:ef7eb2e8f9f7 | 320 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 321 | break; \ |
<> | 144:ef7eb2e8f9f7 | 322 | case RCC_USART1CLKSOURCE_HSI: \ |
<> | 144:ef7eb2e8f9f7 | 323 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
<> | 144:ef7eb2e8f9f7 | 324 | break; \ |
<> | 144:ef7eb2e8f9f7 | 325 | case RCC_USART1CLKSOURCE_SYSCLK: \ |
<> | 144:ef7eb2e8f9f7 | 326 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ |
<> | 144:ef7eb2e8f9f7 | 327 | break; \ |
<> | 144:ef7eb2e8f9f7 | 328 | case RCC_USART1CLKSOURCE_LSE: \ |
<> | 144:ef7eb2e8f9f7 | 329 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
<> | 144:ef7eb2e8f9f7 | 330 | break; \ |
<> | 144:ef7eb2e8f9f7 | 331 | default: \ |
<> | 144:ef7eb2e8f9f7 | 332 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
<> | 144:ef7eb2e8f9f7 | 333 | break; \ |
<> | 144:ef7eb2e8f9f7 | 334 | } \ |
<> | 144:ef7eb2e8f9f7 | 335 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 336 | #elif defined (STM32F030x8) || defined (STM32F070x6) || \ |
<> | 144:ef7eb2e8f9f7 | 337 | defined (STM32F042x6) || defined (STM32F048xx) || \ |
<> | 144:ef7eb2e8f9f7 | 338 | defined (STM32F051x8) || defined (STM32F058xx) |
<> | 144:ef7eb2e8f9f7 | 339 | #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ |
<> | 144:ef7eb2e8f9f7 | 340 | do { \ |
<> | 144:ef7eb2e8f9f7 | 341 | if((__HANDLE__)->Instance == USART1) \ |
<> | 144:ef7eb2e8f9f7 | 342 | { \ |
<> | 144:ef7eb2e8f9f7 | 343 | switch(__HAL_RCC_GET_USART1_SOURCE()) \ |
<> | 144:ef7eb2e8f9f7 | 344 | { \ |
<> | 144:ef7eb2e8f9f7 | 345 | case RCC_USART1CLKSOURCE_PCLK1: \ |
<> | 144:ef7eb2e8f9f7 | 346 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 347 | break; \ |
<> | 144:ef7eb2e8f9f7 | 348 | case RCC_USART1CLKSOURCE_HSI: \ |
<> | 144:ef7eb2e8f9f7 | 349 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
<> | 144:ef7eb2e8f9f7 | 350 | break; \ |
<> | 144:ef7eb2e8f9f7 | 351 | case RCC_USART1CLKSOURCE_SYSCLK: \ |
<> | 144:ef7eb2e8f9f7 | 352 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ |
<> | 144:ef7eb2e8f9f7 | 353 | break; \ |
<> | 144:ef7eb2e8f9f7 | 354 | case RCC_USART1CLKSOURCE_LSE: \ |
<> | 144:ef7eb2e8f9f7 | 355 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
<> | 144:ef7eb2e8f9f7 | 356 | break; \ |
<> | 144:ef7eb2e8f9f7 | 357 | default: \ |
<> | 144:ef7eb2e8f9f7 | 358 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
<> | 144:ef7eb2e8f9f7 | 359 | break; \ |
<> | 144:ef7eb2e8f9f7 | 360 | } \ |
<> | 144:ef7eb2e8f9f7 | 361 | } \ |
<> | 144:ef7eb2e8f9f7 | 362 | else if((__HANDLE__)->Instance == USART2) \ |
<> | 144:ef7eb2e8f9f7 | 363 | { \ |
<> | 144:ef7eb2e8f9f7 | 364 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 365 | } \ |
<> | 144:ef7eb2e8f9f7 | 366 | else \ |
<> | 144:ef7eb2e8f9f7 | 367 | { \ |
<> | 144:ef7eb2e8f9f7 | 368 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
<> | 144:ef7eb2e8f9f7 | 369 | } \ |
<> | 144:ef7eb2e8f9f7 | 370 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 371 | #elif defined(STM32F070xB) |
<> | 144:ef7eb2e8f9f7 | 372 | #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ |
<> | 144:ef7eb2e8f9f7 | 373 | do { \ |
<> | 144:ef7eb2e8f9f7 | 374 | if((__HANDLE__)->Instance == USART1) \ |
<> | 144:ef7eb2e8f9f7 | 375 | { \ |
<> | 144:ef7eb2e8f9f7 | 376 | switch(__HAL_RCC_GET_USART1_SOURCE()) \ |
<> | 144:ef7eb2e8f9f7 | 377 | { \ |
<> | 144:ef7eb2e8f9f7 | 378 | case RCC_USART1CLKSOURCE_PCLK1: \ |
<> | 144:ef7eb2e8f9f7 | 379 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 380 | break; \ |
<> | 144:ef7eb2e8f9f7 | 381 | case RCC_USART1CLKSOURCE_HSI: \ |
<> | 144:ef7eb2e8f9f7 | 382 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
<> | 144:ef7eb2e8f9f7 | 383 | break; \ |
<> | 144:ef7eb2e8f9f7 | 384 | case RCC_USART1CLKSOURCE_SYSCLK: \ |
<> | 144:ef7eb2e8f9f7 | 385 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ |
<> | 144:ef7eb2e8f9f7 | 386 | break; \ |
<> | 144:ef7eb2e8f9f7 | 387 | case RCC_USART1CLKSOURCE_LSE: \ |
<> | 144:ef7eb2e8f9f7 | 388 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
<> | 144:ef7eb2e8f9f7 | 389 | break; \ |
<> | 144:ef7eb2e8f9f7 | 390 | default: \ |
<> | 144:ef7eb2e8f9f7 | 391 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
<> | 144:ef7eb2e8f9f7 | 392 | break; \ |
<> | 144:ef7eb2e8f9f7 | 393 | } \ |
<> | 144:ef7eb2e8f9f7 | 394 | } \ |
<> | 144:ef7eb2e8f9f7 | 395 | else if((__HANDLE__)->Instance == USART2) \ |
<> | 144:ef7eb2e8f9f7 | 396 | { \ |
<> | 144:ef7eb2e8f9f7 | 397 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 398 | } \ |
<> | 144:ef7eb2e8f9f7 | 399 | else if((__HANDLE__)->Instance == USART3) \ |
<> | 144:ef7eb2e8f9f7 | 400 | { \ |
<> | 144:ef7eb2e8f9f7 | 401 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 402 | } \ |
<> | 144:ef7eb2e8f9f7 | 403 | else if((__HANDLE__)->Instance == USART4) \ |
<> | 144:ef7eb2e8f9f7 | 404 | { \ |
<> | 144:ef7eb2e8f9f7 | 405 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 406 | } \ |
<> | 144:ef7eb2e8f9f7 | 407 | else \ |
<> | 144:ef7eb2e8f9f7 | 408 | { \ |
<> | 144:ef7eb2e8f9f7 | 409 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
<> | 144:ef7eb2e8f9f7 | 410 | } \ |
<> | 144:ef7eb2e8f9f7 | 411 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 412 | #elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
<> | 144:ef7eb2e8f9f7 | 413 | #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ |
<> | 144:ef7eb2e8f9f7 | 414 | do { \ |
<> | 144:ef7eb2e8f9f7 | 415 | if((__HANDLE__)->Instance == USART1) \ |
<> | 144:ef7eb2e8f9f7 | 416 | { \ |
<> | 144:ef7eb2e8f9f7 | 417 | switch(__HAL_RCC_GET_USART1_SOURCE()) \ |
<> | 144:ef7eb2e8f9f7 | 418 | { \ |
<> | 144:ef7eb2e8f9f7 | 419 | case RCC_USART1CLKSOURCE_PCLK1: \ |
<> | 144:ef7eb2e8f9f7 | 420 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 421 | break; \ |
<> | 144:ef7eb2e8f9f7 | 422 | case RCC_USART1CLKSOURCE_HSI: \ |
<> | 144:ef7eb2e8f9f7 | 423 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
<> | 144:ef7eb2e8f9f7 | 424 | break; \ |
<> | 144:ef7eb2e8f9f7 | 425 | case RCC_USART1CLKSOURCE_SYSCLK: \ |
<> | 144:ef7eb2e8f9f7 | 426 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ |
<> | 144:ef7eb2e8f9f7 | 427 | break; \ |
<> | 144:ef7eb2e8f9f7 | 428 | case RCC_USART1CLKSOURCE_LSE: \ |
<> | 144:ef7eb2e8f9f7 | 429 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
<> | 144:ef7eb2e8f9f7 | 430 | break; \ |
<> | 144:ef7eb2e8f9f7 | 431 | default: \ |
<> | 144:ef7eb2e8f9f7 | 432 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
<> | 144:ef7eb2e8f9f7 | 433 | break; \ |
<> | 144:ef7eb2e8f9f7 | 434 | } \ |
<> | 144:ef7eb2e8f9f7 | 435 | } \ |
<> | 144:ef7eb2e8f9f7 | 436 | else if((__HANDLE__)->Instance == USART2) \ |
<> | 144:ef7eb2e8f9f7 | 437 | { \ |
<> | 144:ef7eb2e8f9f7 | 438 | switch(__HAL_RCC_GET_USART2_SOURCE()) \ |
<> | 144:ef7eb2e8f9f7 | 439 | { \ |
<> | 144:ef7eb2e8f9f7 | 440 | case RCC_USART2CLKSOURCE_PCLK1: \ |
<> | 144:ef7eb2e8f9f7 | 441 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 442 | break; \ |
<> | 144:ef7eb2e8f9f7 | 443 | case RCC_USART2CLKSOURCE_HSI: \ |
<> | 144:ef7eb2e8f9f7 | 444 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
<> | 144:ef7eb2e8f9f7 | 445 | break; \ |
<> | 144:ef7eb2e8f9f7 | 446 | case RCC_USART2CLKSOURCE_SYSCLK: \ |
<> | 144:ef7eb2e8f9f7 | 447 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ |
<> | 144:ef7eb2e8f9f7 | 448 | break; \ |
<> | 144:ef7eb2e8f9f7 | 449 | case RCC_USART2CLKSOURCE_LSE: \ |
<> | 144:ef7eb2e8f9f7 | 450 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
<> | 144:ef7eb2e8f9f7 | 451 | break; \ |
<> | 144:ef7eb2e8f9f7 | 452 | default: \ |
<> | 144:ef7eb2e8f9f7 | 453 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
<> | 144:ef7eb2e8f9f7 | 454 | break; \ |
<> | 144:ef7eb2e8f9f7 | 455 | } \ |
<> | 144:ef7eb2e8f9f7 | 456 | } \ |
<> | 144:ef7eb2e8f9f7 | 457 | else if((__HANDLE__)->Instance == USART3) \ |
<> | 144:ef7eb2e8f9f7 | 458 | { \ |
<> | 144:ef7eb2e8f9f7 | 459 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 460 | } \ |
<> | 144:ef7eb2e8f9f7 | 461 | else if((__HANDLE__)->Instance == USART4) \ |
<> | 144:ef7eb2e8f9f7 | 462 | { \ |
<> | 144:ef7eb2e8f9f7 | 463 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 464 | } \ |
<> | 144:ef7eb2e8f9f7 | 465 | else \ |
<> | 144:ef7eb2e8f9f7 | 466 | { \ |
<> | 144:ef7eb2e8f9f7 | 467 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
<> | 144:ef7eb2e8f9f7 | 468 | } \ |
<> | 144:ef7eb2e8f9f7 | 469 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 470 | #elif defined(STM32F091xC) || defined (STM32F098xx) |
<> | 144:ef7eb2e8f9f7 | 471 | #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ |
<> | 144:ef7eb2e8f9f7 | 472 | do { \ |
<> | 144:ef7eb2e8f9f7 | 473 | if((__HANDLE__)->Instance == USART1) \ |
<> | 144:ef7eb2e8f9f7 | 474 | { \ |
<> | 144:ef7eb2e8f9f7 | 475 | switch(__HAL_RCC_GET_USART1_SOURCE()) \ |
<> | 144:ef7eb2e8f9f7 | 476 | { \ |
<> | 144:ef7eb2e8f9f7 | 477 | case RCC_USART1CLKSOURCE_PCLK1: \ |
<> | 144:ef7eb2e8f9f7 | 478 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 479 | break; \ |
<> | 144:ef7eb2e8f9f7 | 480 | case RCC_USART1CLKSOURCE_HSI: \ |
<> | 144:ef7eb2e8f9f7 | 481 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
<> | 144:ef7eb2e8f9f7 | 482 | break; \ |
<> | 144:ef7eb2e8f9f7 | 483 | case RCC_USART1CLKSOURCE_SYSCLK: \ |
<> | 144:ef7eb2e8f9f7 | 484 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ |
<> | 144:ef7eb2e8f9f7 | 485 | break; \ |
<> | 144:ef7eb2e8f9f7 | 486 | case RCC_USART1CLKSOURCE_LSE: \ |
<> | 144:ef7eb2e8f9f7 | 487 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
<> | 144:ef7eb2e8f9f7 | 488 | break; \ |
<> | 144:ef7eb2e8f9f7 | 489 | default: \ |
<> | 144:ef7eb2e8f9f7 | 490 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
<> | 144:ef7eb2e8f9f7 | 491 | break; \ |
<> | 144:ef7eb2e8f9f7 | 492 | } \ |
<> | 144:ef7eb2e8f9f7 | 493 | } \ |
<> | 144:ef7eb2e8f9f7 | 494 | else if((__HANDLE__)->Instance == USART2) \ |
<> | 144:ef7eb2e8f9f7 | 495 | { \ |
<> | 144:ef7eb2e8f9f7 | 496 | switch(__HAL_RCC_GET_USART2_SOURCE()) \ |
<> | 144:ef7eb2e8f9f7 | 497 | { \ |
<> | 144:ef7eb2e8f9f7 | 498 | case RCC_USART2CLKSOURCE_PCLK1: \ |
<> | 144:ef7eb2e8f9f7 | 499 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 500 | break; \ |
<> | 144:ef7eb2e8f9f7 | 501 | case RCC_USART2CLKSOURCE_HSI: \ |
<> | 144:ef7eb2e8f9f7 | 502 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
<> | 144:ef7eb2e8f9f7 | 503 | break; \ |
<> | 144:ef7eb2e8f9f7 | 504 | case RCC_USART2CLKSOURCE_SYSCLK: \ |
<> | 144:ef7eb2e8f9f7 | 505 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ |
<> | 144:ef7eb2e8f9f7 | 506 | break; \ |
<> | 144:ef7eb2e8f9f7 | 507 | case RCC_USART2CLKSOURCE_LSE: \ |
<> | 144:ef7eb2e8f9f7 | 508 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
<> | 144:ef7eb2e8f9f7 | 509 | break; \ |
<> | 144:ef7eb2e8f9f7 | 510 | default: \ |
<> | 144:ef7eb2e8f9f7 | 511 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
<> | 144:ef7eb2e8f9f7 | 512 | break; \ |
<> | 144:ef7eb2e8f9f7 | 513 | } \ |
<> | 144:ef7eb2e8f9f7 | 514 | } \ |
<> | 144:ef7eb2e8f9f7 | 515 | else if((__HANDLE__)->Instance == USART3) \ |
<> | 144:ef7eb2e8f9f7 | 516 | { \ |
<> | 144:ef7eb2e8f9f7 | 517 | switch(__HAL_RCC_GET_USART3_SOURCE()) \ |
<> | 144:ef7eb2e8f9f7 | 518 | { \ |
<> | 144:ef7eb2e8f9f7 | 519 | case RCC_USART3CLKSOURCE_PCLK1: \ |
<> | 144:ef7eb2e8f9f7 | 520 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 521 | break; \ |
<> | 144:ef7eb2e8f9f7 | 522 | case RCC_USART3CLKSOURCE_HSI: \ |
<> | 144:ef7eb2e8f9f7 | 523 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
<> | 144:ef7eb2e8f9f7 | 524 | break; \ |
<> | 144:ef7eb2e8f9f7 | 525 | case RCC_USART3CLKSOURCE_SYSCLK: \ |
<> | 144:ef7eb2e8f9f7 | 526 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ |
<> | 144:ef7eb2e8f9f7 | 527 | break; \ |
<> | 144:ef7eb2e8f9f7 | 528 | case RCC_USART3CLKSOURCE_LSE: \ |
<> | 144:ef7eb2e8f9f7 | 529 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
<> | 144:ef7eb2e8f9f7 | 530 | break; \ |
<> | 144:ef7eb2e8f9f7 | 531 | default: \ |
<> | 144:ef7eb2e8f9f7 | 532 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
<> | 144:ef7eb2e8f9f7 | 533 | break; \ |
<> | 144:ef7eb2e8f9f7 | 534 | } \ |
<> | 144:ef7eb2e8f9f7 | 535 | } \ |
<> | 144:ef7eb2e8f9f7 | 536 | else if((__HANDLE__)->Instance == USART4) \ |
<> | 144:ef7eb2e8f9f7 | 537 | { \ |
<> | 144:ef7eb2e8f9f7 | 538 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 539 | } \ |
<> | 144:ef7eb2e8f9f7 | 540 | else if((__HANDLE__)->Instance == USART5) \ |
<> | 144:ef7eb2e8f9f7 | 541 | { \ |
<> | 144:ef7eb2e8f9f7 | 542 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 543 | } \ |
<> | 144:ef7eb2e8f9f7 | 544 | else if((__HANDLE__)->Instance == USART6) \ |
<> | 144:ef7eb2e8f9f7 | 545 | { \ |
<> | 144:ef7eb2e8f9f7 | 546 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 547 | } \ |
<> | 144:ef7eb2e8f9f7 | 548 | else if((__HANDLE__)->Instance == USART7) \ |
<> | 144:ef7eb2e8f9f7 | 549 | { \ |
<> | 144:ef7eb2e8f9f7 | 550 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 551 | } \ |
<> | 144:ef7eb2e8f9f7 | 552 | else if((__HANDLE__)->Instance == USART8) \ |
<> | 144:ef7eb2e8f9f7 | 553 | { \ |
<> | 144:ef7eb2e8f9f7 | 554 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 555 | } \ |
<> | 144:ef7eb2e8f9f7 | 556 | else \ |
<> | 144:ef7eb2e8f9f7 | 557 | { \ |
<> | 144:ef7eb2e8f9f7 | 558 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
<> | 144:ef7eb2e8f9f7 | 559 | } \ |
<> | 144:ef7eb2e8f9f7 | 560 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 561 | #elif defined(STM32F030xC) |
<> | 144:ef7eb2e8f9f7 | 562 | #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ |
<> | 144:ef7eb2e8f9f7 | 563 | do { \ |
<> | 144:ef7eb2e8f9f7 | 564 | if((__HANDLE__)->Instance == USART1) \ |
<> | 144:ef7eb2e8f9f7 | 565 | { \ |
<> | 144:ef7eb2e8f9f7 | 566 | switch(__HAL_RCC_GET_USART1_SOURCE()) \ |
<> | 144:ef7eb2e8f9f7 | 567 | { \ |
<> | 144:ef7eb2e8f9f7 | 568 | case RCC_USART1CLKSOURCE_PCLK1: \ |
<> | 144:ef7eb2e8f9f7 | 569 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 570 | break; \ |
<> | 144:ef7eb2e8f9f7 | 571 | case RCC_USART1CLKSOURCE_HSI: \ |
<> | 144:ef7eb2e8f9f7 | 572 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
<> | 144:ef7eb2e8f9f7 | 573 | break; \ |
<> | 144:ef7eb2e8f9f7 | 574 | case RCC_USART1CLKSOURCE_SYSCLK: \ |
<> | 144:ef7eb2e8f9f7 | 575 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ |
<> | 144:ef7eb2e8f9f7 | 576 | break; \ |
<> | 144:ef7eb2e8f9f7 | 577 | case RCC_USART1CLKSOURCE_LSE: \ |
<> | 144:ef7eb2e8f9f7 | 578 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
<> | 144:ef7eb2e8f9f7 | 579 | break; \ |
<> | 144:ef7eb2e8f9f7 | 580 | default: \ |
<> | 144:ef7eb2e8f9f7 | 581 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
<> | 144:ef7eb2e8f9f7 | 582 | break; \ |
<> | 144:ef7eb2e8f9f7 | 583 | } \ |
<> | 144:ef7eb2e8f9f7 | 584 | } \ |
<> | 144:ef7eb2e8f9f7 | 585 | else if((__HANDLE__)->Instance == USART2) \ |
<> | 144:ef7eb2e8f9f7 | 586 | { \ |
<> | 144:ef7eb2e8f9f7 | 587 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 588 | } \ |
<> | 144:ef7eb2e8f9f7 | 589 | else if((__HANDLE__)->Instance == USART3) \ |
<> | 144:ef7eb2e8f9f7 | 590 | { \ |
<> | 144:ef7eb2e8f9f7 | 591 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 592 | } \ |
<> | 144:ef7eb2e8f9f7 | 593 | else if((__HANDLE__)->Instance == USART4) \ |
<> | 144:ef7eb2e8f9f7 | 594 | { \ |
<> | 144:ef7eb2e8f9f7 | 595 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 596 | } \ |
<> | 144:ef7eb2e8f9f7 | 597 | else if((__HANDLE__)->Instance == USART5) \ |
<> | 144:ef7eb2e8f9f7 | 598 | { \ |
<> | 144:ef7eb2e8f9f7 | 599 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 600 | } \ |
<> | 144:ef7eb2e8f9f7 | 601 | else if((__HANDLE__)->Instance == USART6) \ |
<> | 144:ef7eb2e8f9f7 | 602 | { \ |
<> | 144:ef7eb2e8f9f7 | 603 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ |
<> | 144:ef7eb2e8f9f7 | 604 | } \ |
<> | 144:ef7eb2e8f9f7 | 605 | else \ |
<> | 144:ef7eb2e8f9f7 | 606 | { \ |
<> | 144:ef7eb2e8f9f7 | 607 | (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
<> | 144:ef7eb2e8f9f7 | 608 | } \ |
<> | 144:ef7eb2e8f9f7 | 609 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 610 | |
<> | 144:ef7eb2e8f9f7 | 611 | #endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */ |
<> | 144:ef7eb2e8f9f7 | 612 | |
<> | 144:ef7eb2e8f9f7 | 613 | |
<> | 144:ef7eb2e8f9f7 | 614 | /** @brief Compute the UART mask to apply to retrieve the received data |
<> | 144:ef7eb2e8f9f7 | 615 | * according to the word length and to the parity bits activation. |
<> | 144:ef7eb2e8f9f7 | 616 | * @note If PCE = 1, the parity bit is not included in the data extracted |
<> | 144:ef7eb2e8f9f7 | 617 | * by the reception API(). |
<> | 144:ef7eb2e8f9f7 | 618 | * This masking operation is not carried out in the case of |
<> | 144:ef7eb2e8f9f7 | 619 | * DMA transfers. |
Anna Bridge |
180:96ed750bd169 | 620 | * @param __HANDLE__ specifies the UART Handle. |
<> | 144:ef7eb2e8f9f7 | 621 | * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. |
<> | 144:ef7eb2e8f9f7 | 622 | */ |
<> | 144:ef7eb2e8f9f7 | 623 | #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ |
<> | 144:ef7eb2e8f9f7 | 624 | defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ |
<> | 144:ef7eb2e8f9f7 | 625 | defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) |
<> | 144:ef7eb2e8f9f7 | 626 | #define UART_MASK_COMPUTATION(__HANDLE__) \ |
<> | 144:ef7eb2e8f9f7 | 627 | do { \ |
<> | 144:ef7eb2e8f9f7 | 628 | if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ |
<> | 144:ef7eb2e8f9f7 | 629 | { \ |
<> | 144:ef7eb2e8f9f7 | 630 | if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ |
<> | 144:ef7eb2e8f9f7 | 631 | { \ |
<> | 156:95d6b41a828b | 632 | (__HANDLE__)->Mask = 0x01FFU; \ |
<> | 144:ef7eb2e8f9f7 | 633 | } \ |
<> | 144:ef7eb2e8f9f7 | 634 | else \ |
<> | 144:ef7eb2e8f9f7 | 635 | { \ |
<> | 156:95d6b41a828b | 636 | (__HANDLE__)->Mask = 0x00FFU; \ |
<> | 144:ef7eb2e8f9f7 | 637 | } \ |
<> | 144:ef7eb2e8f9f7 | 638 | } \ |
<> | 144:ef7eb2e8f9f7 | 639 | else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ |
<> | 144:ef7eb2e8f9f7 | 640 | { \ |
<> | 144:ef7eb2e8f9f7 | 641 | if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ |
<> | 144:ef7eb2e8f9f7 | 642 | { \ |
<> | 156:95d6b41a828b | 643 | (__HANDLE__)->Mask = 0x00FFU; \ |
<> | 144:ef7eb2e8f9f7 | 644 | } \ |
<> | 144:ef7eb2e8f9f7 | 645 | else \ |
<> | 144:ef7eb2e8f9f7 | 646 | { \ |
<> | 156:95d6b41a828b | 647 | (__HANDLE__)->Mask = 0x007FU; \ |
<> | 144:ef7eb2e8f9f7 | 648 | } \ |
<> | 144:ef7eb2e8f9f7 | 649 | } \ |
<> | 144:ef7eb2e8f9f7 | 650 | else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ |
<> | 144:ef7eb2e8f9f7 | 651 | { \ |
<> | 144:ef7eb2e8f9f7 | 652 | if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ |
<> | 144:ef7eb2e8f9f7 | 653 | { \ |
<> | 156:95d6b41a828b | 654 | (__HANDLE__)->Mask = 0x007FU; \ |
<> | 144:ef7eb2e8f9f7 | 655 | } \ |
<> | 144:ef7eb2e8f9f7 | 656 | else \ |
<> | 144:ef7eb2e8f9f7 | 657 | { \ |
<> | 156:95d6b41a828b | 658 | (__HANDLE__)->Mask = 0x003FU; \ |
<> | 144:ef7eb2e8f9f7 | 659 | } \ |
<> | 144:ef7eb2e8f9f7 | 660 | } \ |
<> | 144:ef7eb2e8f9f7 | 661 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 662 | #else |
<> | 144:ef7eb2e8f9f7 | 663 | #define UART_MASK_COMPUTATION(__HANDLE__) \ |
<> | 144:ef7eb2e8f9f7 | 664 | do { \ |
<> | 144:ef7eb2e8f9f7 | 665 | if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ |
<> | 144:ef7eb2e8f9f7 | 666 | { \ |
<> | 144:ef7eb2e8f9f7 | 667 | if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ |
<> | 144:ef7eb2e8f9f7 | 668 | { \ |
<> | 156:95d6b41a828b | 669 | (__HANDLE__)->Mask = 0x01FFU; \ |
<> | 144:ef7eb2e8f9f7 | 670 | } \ |
<> | 144:ef7eb2e8f9f7 | 671 | else \ |
<> | 144:ef7eb2e8f9f7 | 672 | { \ |
<> | 156:95d6b41a828b | 673 | (__HANDLE__)->Mask = 0x00FFU; \ |
<> | 144:ef7eb2e8f9f7 | 674 | } \ |
<> | 144:ef7eb2e8f9f7 | 675 | } \ |
<> | 144:ef7eb2e8f9f7 | 676 | else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ |
<> | 144:ef7eb2e8f9f7 | 677 | { \ |
<> | 144:ef7eb2e8f9f7 | 678 | if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ |
<> | 144:ef7eb2e8f9f7 | 679 | { \ |
<> | 156:95d6b41a828b | 680 | (__HANDLE__)->Mask = 0x00FFU; \ |
<> | 144:ef7eb2e8f9f7 | 681 | } \ |
<> | 144:ef7eb2e8f9f7 | 682 | else \ |
<> | 144:ef7eb2e8f9f7 | 683 | { \ |
<> | 156:95d6b41a828b | 684 | (__HANDLE__)->Mask = 0x007FU; \ |
<> | 144:ef7eb2e8f9f7 | 685 | } \ |
<> | 144:ef7eb2e8f9f7 | 686 | } \ |
<> | 144:ef7eb2e8f9f7 | 687 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 688 | #endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ |
<> | 144:ef7eb2e8f9f7 | 689 | defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ |
<> | 144:ef7eb2e8f9f7 | 690 | defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */ |
<> | 144:ef7eb2e8f9f7 | 691 | |
<> | 144:ef7eb2e8f9f7 | 692 | /** |
<> | 144:ef7eb2e8f9f7 | 693 | * @brief Ensure that UART frame length is valid. |
Anna Bridge |
180:96ed750bd169 | 694 | * @param __LENGTH__ UART frame length. |
<> | 144:ef7eb2e8f9f7 | 695 | * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) |
<> | 144:ef7eb2e8f9f7 | 696 | */ |
<> | 144:ef7eb2e8f9f7 | 697 | #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ |
<> | 144:ef7eb2e8f9f7 | 698 | defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ |
<> | 144:ef7eb2e8f9f7 | 699 | defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) |
<> | 144:ef7eb2e8f9f7 | 700 | #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ |
<> | 144:ef7eb2e8f9f7 | 701 | ((__LENGTH__) == UART_WORDLENGTH_8B) || \ |
<> | 144:ef7eb2e8f9f7 | 702 | ((__LENGTH__) == UART_WORDLENGTH_9B)) |
<> | 144:ef7eb2e8f9f7 | 703 | #else |
<> | 144:ef7eb2e8f9f7 | 704 | #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_8B) || \ |
<> | 144:ef7eb2e8f9f7 | 705 | ((__LENGTH__) == UART_WORDLENGTH_9B)) |
<> | 144:ef7eb2e8f9f7 | 706 | #endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ |
<> | 144:ef7eb2e8f9f7 | 707 | defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ |
<> | 144:ef7eb2e8f9f7 | 708 | defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */ |
<> | 144:ef7eb2e8f9f7 | 709 | |
<> | 144:ef7eb2e8f9f7 | 710 | /** |
<> | 144:ef7eb2e8f9f7 | 711 | * @brief Ensure that UART auto Baud rate detection mode is valid. |
Anna Bridge |
180:96ed750bd169 | 712 | * @param __MODE__ UART auto Baud rate detection mode. |
<> | 144:ef7eb2e8f9f7 | 713 | * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) |
<> | 144:ef7eb2e8f9f7 | 714 | */ |
<> | 144:ef7eb2e8f9f7 | 715 | #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ |
<> | 144:ef7eb2e8f9f7 | 716 | defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ |
<> | 144:ef7eb2e8f9f7 | 717 | defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) |
<> | 144:ef7eb2e8f9f7 | 718 | #define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ |
<> | 144:ef7eb2e8f9f7 | 719 | ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ |
<> | 144:ef7eb2e8f9f7 | 720 | ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ |
<> | 144:ef7eb2e8f9f7 | 721 | ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) |
<> | 144:ef7eb2e8f9f7 | 722 | #else |
<> | 144:ef7eb2e8f9f7 | 723 | #define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ |
<> | 144:ef7eb2e8f9f7 | 724 | ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE)) |
<> | 144:ef7eb2e8f9f7 | 725 | #endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ |
<> | 144:ef7eb2e8f9f7 | 726 | defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ |
<> | 144:ef7eb2e8f9f7 | 727 | defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */ |
<> | 144:ef7eb2e8f9f7 | 728 | |
<> | 144:ef7eb2e8f9f7 | 729 | |
<> | 144:ef7eb2e8f9f7 | 730 | #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) |
<> | 144:ef7eb2e8f9f7 | 731 | /** |
<> | 144:ef7eb2e8f9f7 | 732 | * @brief Ensure that UART LIN state is valid. |
Anna Bridge |
180:96ed750bd169 | 733 | * @param __LIN__ UART LIN state. |
<> | 144:ef7eb2e8f9f7 | 734 | * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) |
<> | 144:ef7eb2e8f9f7 | 735 | */ |
<> | 144:ef7eb2e8f9f7 | 736 | #define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ |
<> | 144:ef7eb2e8f9f7 | 737 | ((__LIN__) == UART_LIN_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 738 | |
<> | 144:ef7eb2e8f9f7 | 739 | /** |
<> | 144:ef7eb2e8f9f7 | 740 | * @brief Ensure that UART LIN break detection length is valid. |
Anna Bridge |
180:96ed750bd169 | 741 | * @param __LENGTH__ UART LIN break detection length. |
<> | 144:ef7eb2e8f9f7 | 742 | * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) |
<> | 144:ef7eb2e8f9f7 | 743 | */ |
<> | 144:ef7eb2e8f9f7 | 744 | #define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ |
<> | 144:ef7eb2e8f9f7 | 745 | ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) |
<> | 144:ef7eb2e8f9f7 | 746 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ |
<> | 144:ef7eb2e8f9f7 | 747 | |
<> | 144:ef7eb2e8f9f7 | 748 | /** |
<> | 144:ef7eb2e8f9f7 | 749 | * @brief Ensure that UART request parameter is valid. |
Anna Bridge |
180:96ed750bd169 | 750 | * @param __PARAM__ UART request parameter. |
<> | 144:ef7eb2e8f9f7 | 751 | * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) |
<> | 144:ef7eb2e8f9f7 | 752 | */ |
<> | 144:ef7eb2e8f9f7 | 753 | #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) |
<> | 144:ef7eb2e8f9f7 | 754 | #define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ |
<> | 144:ef7eb2e8f9f7 | 755 | ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ |
<> | 144:ef7eb2e8f9f7 | 756 | ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ |
<> | 144:ef7eb2e8f9f7 | 757 | ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ |
<> | 144:ef7eb2e8f9f7 | 758 | ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) |
<> | 144:ef7eb2e8f9f7 | 759 | #else |
<> | 144:ef7eb2e8f9f7 | 760 | #define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ |
<> | 144:ef7eb2e8f9f7 | 761 | ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ |
<> | 144:ef7eb2e8f9f7 | 762 | ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ |
<> | 144:ef7eb2e8f9f7 | 763 | ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST)) |
<> | 144:ef7eb2e8f9f7 | 764 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ |
<> | 144:ef7eb2e8f9f7 | 765 | |
<> | 144:ef7eb2e8f9f7 | 766 | #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) |
<> | 144:ef7eb2e8f9f7 | 767 | /** |
<> | 144:ef7eb2e8f9f7 | 768 | * @brief Ensure that UART stop mode state is valid. |
Anna Bridge |
180:96ed750bd169 | 769 | * @param __STOPMODE__ UART stop mode state. |
<> | 144:ef7eb2e8f9f7 | 770 | * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) |
<> | 144:ef7eb2e8f9f7 | 771 | */ |
<> | 144:ef7eb2e8f9f7 | 772 | #define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ |
<> | 144:ef7eb2e8f9f7 | 773 | ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) |
<> | 156:95d6b41a828b | 774 | |
<> | 144:ef7eb2e8f9f7 | 775 | /** |
<> | 144:ef7eb2e8f9f7 | 776 | * @brief Ensure that UART wake-up selection is valid. |
Anna Bridge |
180:96ed750bd169 | 777 | * @param __WAKE__ UART wake-up selection. |
<> | 144:ef7eb2e8f9f7 | 778 | * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) |
<> | 144:ef7eb2e8f9f7 | 779 | */ |
<> | 144:ef7eb2e8f9f7 | 780 | #define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ |
<> | 144:ef7eb2e8f9f7 | 781 | ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ |
<> | 144:ef7eb2e8f9f7 | 782 | ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) |
<> | 144:ef7eb2e8f9f7 | 783 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ |
<> | 144:ef7eb2e8f9f7 | 784 | |
<> | 144:ef7eb2e8f9f7 | 785 | /** |
<> | 144:ef7eb2e8f9f7 | 786 | * @} |
<> | 144:ef7eb2e8f9f7 | 787 | */ |
<> | 144:ef7eb2e8f9f7 | 788 | |
<> | 144:ef7eb2e8f9f7 | 789 | /* Exported functions --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 790 | /** @addtogroup UARTEx_Exported_Functions |
<> | 144:ef7eb2e8f9f7 | 791 | * @{ |
<> | 144:ef7eb2e8f9f7 | 792 | */ |
<> | 144:ef7eb2e8f9f7 | 793 | |
<> | 144:ef7eb2e8f9f7 | 794 | /** @addtogroup UARTEx_Exported_Functions_Group1 |
<> | 144:ef7eb2e8f9f7 | 795 | * @brief Extended Initialization and Configuration Functions |
<> | 144:ef7eb2e8f9f7 | 796 | * @{ |
<> | 144:ef7eb2e8f9f7 | 797 | */ |
<> | 144:ef7eb2e8f9f7 | 798 | /* Initialization and de-initialization functions ****************************/ |
<> | 144:ef7eb2e8f9f7 | 799 | HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime); |
<> | 144:ef7eb2e8f9f7 | 800 | #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) |
<> | 144:ef7eb2e8f9f7 | 801 | HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); |
<> | 144:ef7eb2e8f9f7 | 802 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ |
<> | 144:ef7eb2e8f9f7 | 803 | /** |
<> | 144:ef7eb2e8f9f7 | 804 | * @} |
<> | 144:ef7eb2e8f9f7 | 805 | */ |
<> | 144:ef7eb2e8f9f7 | 806 | |
<> | 144:ef7eb2e8f9f7 | 807 | /** @addtogroup UARTEx_Exported_Functions_Group2 |
<> | 144:ef7eb2e8f9f7 | 808 | * @brief Extended UART Interrupt handling function |
<> | 144:ef7eb2e8f9f7 | 809 | * @{ |
<> | 144:ef7eb2e8f9f7 | 810 | */ |
<> | 144:ef7eb2e8f9f7 | 811 | |
<> | 144:ef7eb2e8f9f7 | 812 | /* IO operation functions ***************************************************/ |
<> | 144:ef7eb2e8f9f7 | 813 | #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) |
<> | 144:ef7eb2e8f9f7 | 814 | void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); |
<> | 144:ef7eb2e8f9f7 | 815 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ |
<> | 144:ef7eb2e8f9f7 | 816 | /** |
<> | 144:ef7eb2e8f9f7 | 817 | * @} |
<> | 144:ef7eb2e8f9f7 | 818 | */ |
<> | 144:ef7eb2e8f9f7 | 819 | |
<> | 144:ef7eb2e8f9f7 | 820 | /** @addtogroup UARTEx_Exported_Functions_Group3 |
<> | 144:ef7eb2e8f9f7 | 821 | * @brief Extended Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 822 | * @{ |
<> | 144:ef7eb2e8f9f7 | 823 | */ |
<> | 144:ef7eb2e8f9f7 | 824 | |
<> | 144:ef7eb2e8f9f7 | 825 | /* Peripheral Control functions **********************************************/ |
<> | 144:ef7eb2e8f9f7 | 826 | HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); |
<> | 144:ef7eb2e8f9f7 | 827 | #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6) && !defined(STM32F030xC) |
<> | 144:ef7eb2e8f9f7 | 828 | HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); |
<> | 144:ef7eb2e8f9f7 | 829 | HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); |
<> | 144:ef7eb2e8f9f7 | 830 | HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); |
<> | 144:ef7eb2e8f9f7 | 831 | HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); |
<> | 144:ef7eb2e8f9f7 | 832 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ |
<> | 144:ef7eb2e8f9f7 | 833 | /** |
<> | 144:ef7eb2e8f9f7 | 834 | * @} |
<> | 144:ef7eb2e8f9f7 | 835 | */ |
<> | 144:ef7eb2e8f9f7 | 836 | /* Peripheral State functions ************************************************/ |
<> | 144:ef7eb2e8f9f7 | 837 | |
<> | 144:ef7eb2e8f9f7 | 838 | /** |
<> | 144:ef7eb2e8f9f7 | 839 | * @} |
<> | 144:ef7eb2e8f9f7 | 840 | */ |
<> | 144:ef7eb2e8f9f7 | 841 | |
<> | 144:ef7eb2e8f9f7 | 842 | /* Private functions ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 843 | |
<> | 144:ef7eb2e8f9f7 | 844 | /** |
<> | 144:ef7eb2e8f9f7 | 845 | * @} |
<> | 144:ef7eb2e8f9f7 | 846 | */ |
<> | 144:ef7eb2e8f9f7 | 847 | |
<> | 144:ef7eb2e8f9f7 | 848 | /** |
<> | 144:ef7eb2e8f9f7 | 849 | * @} |
<> | 144:ef7eb2e8f9f7 | 850 | */ |
<> | 144:ef7eb2e8f9f7 | 851 | |
<> | 144:ef7eb2e8f9f7 | 852 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 853 | } |
<> | 144:ef7eb2e8f9f7 | 854 | #endif |
<> | 144:ef7eb2e8f9f7 | 855 | |
<> | 144:ef7eb2e8f9f7 | 856 | #endif /* __STM32F0xx_HAL_UART_EX_H */ |
<> | 144:ef7eb2e8f9f7 | 857 | |
<> | 144:ef7eb2e8f9f7 | 858 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
<> | 144:ef7eb2e8f9f7 | 859 |