mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.c@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 180:96ed750bd169
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f0xx_hal_adc.c |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 5 | * @brief This file provides firmware functions to manage the following |
<> | 144:ef7eb2e8f9f7 | 6 | * functionalities of the Analog to Digital Convertor (ADC) |
<> | 144:ef7eb2e8f9f7 | 7 | * peripheral: |
<> | 144:ef7eb2e8f9f7 | 8 | * + Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 9 | * ++ Initialization and Configuration of ADC |
<> | 144:ef7eb2e8f9f7 | 10 | * + Operation functions |
<> | 144:ef7eb2e8f9f7 | 11 | * ++ Start, stop, get result of conversions of regular |
<> | 144:ef7eb2e8f9f7 | 12 | * group, using 3 possible modes: polling, interruption or DMA. |
<> | 144:ef7eb2e8f9f7 | 13 | * + Control functions |
<> | 144:ef7eb2e8f9f7 | 14 | * ++ Channels configuration on regular group |
<> | 144:ef7eb2e8f9f7 | 15 | * ++ Analog Watchdog configuration |
<> | 144:ef7eb2e8f9f7 | 16 | * + State functions |
<> | 144:ef7eb2e8f9f7 | 17 | * ++ ADC state machine management |
<> | 144:ef7eb2e8f9f7 | 18 | * ++ Interrupts and flags management |
<> | 144:ef7eb2e8f9f7 | 19 | * Other functions (extended functions) are available in file |
<> | 144:ef7eb2e8f9f7 | 20 | * "stm32f0xx_hal_adc_ex.c". |
<> | 144:ef7eb2e8f9f7 | 21 | * |
<> | 144:ef7eb2e8f9f7 | 22 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 23 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 24 | ##### ADC peripheral features ##### |
<> | 144:ef7eb2e8f9f7 | 25 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 26 | [..] |
<> | 144:ef7eb2e8f9f7 | 27 | (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution |
<> | 144:ef7eb2e8f9f7 | 28 | |
<> | 144:ef7eb2e8f9f7 | 29 | (+) Interrupt generation at the end of regular conversion and in case of |
<> | 144:ef7eb2e8f9f7 | 30 | analog watchdog or overrun events. |
<> | 144:ef7eb2e8f9f7 | 31 | |
<> | 144:ef7eb2e8f9f7 | 32 | (+) Single and continuous conversion modes. |
<> | 144:ef7eb2e8f9f7 | 33 | |
<> | 144:ef7eb2e8f9f7 | 34 | (+) Scan mode for conversion of several channels sequentially. |
<> | 144:ef7eb2e8f9f7 | 35 | |
<> | 144:ef7eb2e8f9f7 | 36 | (+) Data alignment with in-built data coherency. |
<> | 144:ef7eb2e8f9f7 | 37 | |
<> | 144:ef7eb2e8f9f7 | 38 | (+) Programmable sampling time (common for all channels) |
<> | 144:ef7eb2e8f9f7 | 39 | |
<> | 144:ef7eb2e8f9f7 | 40 | (+) ADC conversion of regular group. |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | (+) External trigger (timer or EXTI) with configurable polarity |
<> | 144:ef7eb2e8f9f7 | 43 | |
<> | 144:ef7eb2e8f9f7 | 44 | (+) DMA request generation for transfer of conversions data of regular group. |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | (+) ADC calibration |
<> | 144:ef7eb2e8f9f7 | 47 | |
<> | 144:ef7eb2e8f9f7 | 48 | (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at |
<> | 144:ef7eb2e8f9f7 | 49 | slower speed. |
<> | 144:ef7eb2e8f9f7 | 50 | |
<> | 144:ef7eb2e8f9f7 | 51 | (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to |
<> | 144:ef7eb2e8f9f7 | 52 | Vdda or to an external voltage reference). |
<> | 144:ef7eb2e8f9f7 | 53 | |
<> | 144:ef7eb2e8f9f7 | 54 | |
<> | 144:ef7eb2e8f9f7 | 55 | ##### How to use this driver ##### |
<> | 144:ef7eb2e8f9f7 | 56 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 57 | [..] |
<> | 144:ef7eb2e8f9f7 | 58 | |
<> | 144:ef7eb2e8f9f7 | 59 | *** Configuration of top level parameters related to ADC *** |
<> | 144:ef7eb2e8f9f7 | 60 | ============================================================ |
<> | 144:ef7eb2e8f9f7 | 61 | [..] |
<> | 144:ef7eb2e8f9f7 | 62 | |
<> | 144:ef7eb2e8f9f7 | 63 | (#) Enable the ADC interface |
<> | 144:ef7eb2e8f9f7 | 64 | (++) As prerequisite, ADC clock must be configured at RCC top level. |
<> | 144:ef7eb2e8f9f7 | 65 | Caution: On STM32F0, ADC clock frequency max is 14MHz (refer |
<> | 144:ef7eb2e8f9f7 | 66 | to device datasheet). |
<> | 144:ef7eb2e8f9f7 | 67 | Therefore, ADC clock prescaler must be configured in |
<> | 144:ef7eb2e8f9f7 | 68 | function of ADC clock source frequency to remain below |
<> | 144:ef7eb2e8f9f7 | 69 | this maximum frequency. |
<> | 144:ef7eb2e8f9f7 | 70 | |
<> | 144:ef7eb2e8f9f7 | 71 | (++) Two clock settings are mandatory: |
<> | 144:ef7eb2e8f9f7 | 72 | (+++) ADC clock (core clock, also possibly conversion clock). |
<> | 144:ef7eb2e8f9f7 | 73 | |
<> | 144:ef7eb2e8f9f7 | 74 | (+++) ADC clock (conversions clock). |
<> | 144:ef7eb2e8f9f7 | 75 | Two possible clock sources: synchronous clock derived from APB clock |
<> | 144:ef7eb2e8f9f7 | 76 | or asynchronous clock derived from ADC dedicated HSI RC oscillator |
<> | 144:ef7eb2e8f9f7 | 77 | 14MHz. |
<> | 144:ef7eb2e8f9f7 | 78 | If asynchronous clock is selected, parameter "HSI14State" must be set either: |
<> | 144:ef7eb2e8f9f7 | 79 | - to "...HSI14State = RCC_HSI14_ADC_CONTROL" to let the ADC control |
<> | 144:ef7eb2e8f9f7 | 80 | the HSI14 oscillator enable/disable (if not used to supply the main |
<> | 144:ef7eb2e8f9f7 | 81 | system clock): feature used if ADC mode LowPowerAutoPowerOff is |
<> | 144:ef7eb2e8f9f7 | 82 | enabled. |
<> | 144:ef7eb2e8f9f7 | 83 | - to "...HSI14State = RCC_HSI14_ON" to maintain the HSI14 oscillator |
<> | 144:ef7eb2e8f9f7 | 84 | always enabled: can be used to supply the main system clock. |
<> | 144:ef7eb2e8f9f7 | 85 | |
<> | 144:ef7eb2e8f9f7 | 86 | (+++) Example: |
<> | 144:ef7eb2e8f9f7 | 87 | Into HAL_ADC_MspInit() (recommended code location) or with |
<> | 144:ef7eb2e8f9f7 | 88 | other device clock parameters configuration: |
<> | 144:ef7eb2e8f9f7 | 89 | (+++) __HAL_RCC_ADC1_CLK_ENABLE(); (mandatory) |
<> | 144:ef7eb2e8f9f7 | 90 | |
<> | 144:ef7eb2e8f9f7 | 91 | HI14 enable or let under control of ADC: (optional: if asynchronous clock selected) |
<> | 144:ef7eb2e8f9f7 | 92 | (+++) RCC_OscInitTypeDef RCC_OscInitStructure; |
<> | 144:ef7eb2e8f9f7 | 93 | (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; |
<> | 144:ef7eb2e8f9f7 | 94 | (+++) RCC_OscInitStructure.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; |
<> | 144:ef7eb2e8f9f7 | 95 | (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_ADC_CONTROL; |
<> | 144:ef7eb2e8f9f7 | 96 | (+++) RCC_OscInitStructure.PLL... (optional if used for system clock) |
<> | 144:ef7eb2e8f9f7 | 97 | (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); |
<> | 144:ef7eb2e8f9f7 | 98 | |
<> | 144:ef7eb2e8f9f7 | 99 | (++) ADC clock source and clock prescaler are configured at ADC level with |
<> | 144:ef7eb2e8f9f7 | 100 | parameter "ClockPrescaler" using function HAL_ADC_Init(). |
<> | 144:ef7eb2e8f9f7 | 101 | |
<> | 144:ef7eb2e8f9f7 | 102 | (#) ADC pins configuration |
<> | 144:ef7eb2e8f9f7 | 103 | (++) Enable the clock for the ADC GPIOs |
<> | 144:ef7eb2e8f9f7 | 104 | using macro __HAL_RCC_GPIOx_CLK_ENABLE() |
<> | 144:ef7eb2e8f9f7 | 105 | (++) Configure these ADC pins in analog mode |
<> | 144:ef7eb2e8f9f7 | 106 | using function HAL_GPIO_Init() |
<> | 144:ef7eb2e8f9f7 | 107 | |
<> | 144:ef7eb2e8f9f7 | 108 | (#) Optionally, in case of usage of ADC with interruptions: |
<> | 144:ef7eb2e8f9f7 | 109 | (++) Configure the NVIC for ADC |
<> | 144:ef7eb2e8f9f7 | 110 | using function HAL_NVIC_EnableIRQ(ADCx_IRQn) |
<> | 144:ef7eb2e8f9f7 | 111 | (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() |
<> | 144:ef7eb2e8f9f7 | 112 | into the function of corresponding ADC interruption vector |
<> | 144:ef7eb2e8f9f7 | 113 | ADCx_IRQHandler(). |
<> | 144:ef7eb2e8f9f7 | 114 | |
<> | 144:ef7eb2e8f9f7 | 115 | (#) Optionally, in case of usage of DMA: |
<> | 144:ef7eb2e8f9f7 | 116 | (++) Configure the DMA (DMA channel, mode normal or circular, ...) |
<> | 144:ef7eb2e8f9f7 | 117 | using function HAL_DMA_Init(). |
<> | 144:ef7eb2e8f9f7 | 118 | (++) Configure the NVIC for DMA |
<> | 144:ef7eb2e8f9f7 | 119 | using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) |
<> | 144:ef7eb2e8f9f7 | 120 | (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() |
<> | 144:ef7eb2e8f9f7 | 121 | into the function of corresponding DMA interruption vector |
<> | 144:ef7eb2e8f9f7 | 122 | DMAx_Channelx_IRQHandler(). |
<> | 144:ef7eb2e8f9f7 | 123 | |
<> | 144:ef7eb2e8f9f7 | 124 | *** Configuration of ADC, group regular, channels parameters *** |
<> | 144:ef7eb2e8f9f7 | 125 | ================================================================ |
<> | 144:ef7eb2e8f9f7 | 126 | [..] |
<> | 144:ef7eb2e8f9f7 | 127 | |
<> | 144:ef7eb2e8f9f7 | 128 | (#) Configure the ADC parameters (resolution, data alignment, ...) |
<> | 144:ef7eb2e8f9f7 | 129 | and regular group parameters (conversion trigger, sequencer, ...) |
<> | 144:ef7eb2e8f9f7 | 130 | using function HAL_ADC_Init(). |
<> | 144:ef7eb2e8f9f7 | 131 | |
<> | 144:ef7eb2e8f9f7 | 132 | (#) Configure the channels for regular group parameters (channel number, |
<> | 144:ef7eb2e8f9f7 | 133 | channel rank into sequencer, ..., into regular group) |
<> | 144:ef7eb2e8f9f7 | 134 | using function HAL_ADC_ConfigChannel(). |
<> | 144:ef7eb2e8f9f7 | 135 | |
<> | 144:ef7eb2e8f9f7 | 136 | (#) Optionally, configure the analog watchdog parameters (channels |
<> | 144:ef7eb2e8f9f7 | 137 | monitored, thresholds, ...) |
<> | 144:ef7eb2e8f9f7 | 138 | using function HAL_ADC_AnalogWDGConfig(). |
<> | 144:ef7eb2e8f9f7 | 139 | |
<> | 144:ef7eb2e8f9f7 | 140 | *** Execution of ADC conversions *** |
<> | 144:ef7eb2e8f9f7 | 141 | ==================================== |
<> | 144:ef7eb2e8f9f7 | 142 | [..] |
<> | 144:ef7eb2e8f9f7 | 143 | |
<> | 144:ef7eb2e8f9f7 | 144 | (#) Optionally, perform an automatic ADC calibration to improve the |
<> | 144:ef7eb2e8f9f7 | 145 | conversion accuracy |
<> | 144:ef7eb2e8f9f7 | 146 | using function HAL_ADCEx_Calibration_Start(). |
<> | 144:ef7eb2e8f9f7 | 147 | |
<> | 144:ef7eb2e8f9f7 | 148 | (#) ADC driver can be used among three modes: polling, interruption, |
<> | 144:ef7eb2e8f9f7 | 149 | transfer by DMA. |
<> | 144:ef7eb2e8f9f7 | 150 | |
<> | 144:ef7eb2e8f9f7 | 151 | (++) ADC conversion by polling: |
<> | 144:ef7eb2e8f9f7 | 152 | (+++) Activate the ADC peripheral and start conversions |
<> | 144:ef7eb2e8f9f7 | 153 | using function HAL_ADC_Start() |
<> | 144:ef7eb2e8f9f7 | 154 | (+++) Wait for ADC conversion completion |
<> | 144:ef7eb2e8f9f7 | 155 | using function HAL_ADC_PollForConversion() |
<> | 144:ef7eb2e8f9f7 | 156 | (+++) Retrieve conversion results |
<> | 144:ef7eb2e8f9f7 | 157 | using function HAL_ADC_GetValue() |
<> | 144:ef7eb2e8f9f7 | 158 | (+++) Stop conversion and disable the ADC peripheral |
<> | 144:ef7eb2e8f9f7 | 159 | using function HAL_ADC_Stop() |
<> | 144:ef7eb2e8f9f7 | 160 | |
<> | 144:ef7eb2e8f9f7 | 161 | (++) ADC conversion by interruption: |
<> | 144:ef7eb2e8f9f7 | 162 | (+++) Activate the ADC peripheral and start conversions |
<> | 144:ef7eb2e8f9f7 | 163 | using function HAL_ADC_Start_IT() |
<> | 144:ef7eb2e8f9f7 | 164 | (+++) Wait for ADC conversion completion by call of function |
<> | 144:ef7eb2e8f9f7 | 165 | HAL_ADC_ConvCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 166 | (this function must be implemented in user program) |
<> | 144:ef7eb2e8f9f7 | 167 | (+++) Retrieve conversion results |
<> | 144:ef7eb2e8f9f7 | 168 | using function HAL_ADC_GetValue() |
<> | 144:ef7eb2e8f9f7 | 169 | (+++) Stop conversion and disable the ADC peripheral |
<> | 144:ef7eb2e8f9f7 | 170 | using function HAL_ADC_Stop_IT() |
<> | 144:ef7eb2e8f9f7 | 171 | |
<> | 144:ef7eb2e8f9f7 | 172 | (++) ADC conversion with transfer by DMA: |
<> | 144:ef7eb2e8f9f7 | 173 | (+++) Activate the ADC peripheral and start conversions |
<> | 144:ef7eb2e8f9f7 | 174 | using function HAL_ADC_Start_DMA() |
<> | 144:ef7eb2e8f9f7 | 175 | (+++) Wait for ADC conversion completion by call of function |
<> | 144:ef7eb2e8f9f7 | 176 | HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 177 | (these functions must be implemented in user program) |
<> | 144:ef7eb2e8f9f7 | 178 | (+++) Conversion results are automatically transferred by DMA into |
<> | 144:ef7eb2e8f9f7 | 179 | destination variable address. |
<> | 144:ef7eb2e8f9f7 | 180 | (+++) Stop conversion and disable the ADC peripheral |
<> | 144:ef7eb2e8f9f7 | 181 | using function HAL_ADC_Stop_DMA() |
<> | 144:ef7eb2e8f9f7 | 182 | |
<> | 144:ef7eb2e8f9f7 | 183 | [..] |
<> | 144:ef7eb2e8f9f7 | 184 | |
<> | 144:ef7eb2e8f9f7 | 185 | (@) Callback functions must be implemented in user program: |
<> | 144:ef7eb2e8f9f7 | 186 | (+@) HAL_ADC_ErrorCallback() |
<> | 144:ef7eb2e8f9f7 | 187 | (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) |
<> | 144:ef7eb2e8f9f7 | 188 | (+@) HAL_ADC_ConvCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 189 | (+@) HAL_ADC_ConvHalfCpltCallback |
<> | 144:ef7eb2e8f9f7 | 190 | |
<> | 144:ef7eb2e8f9f7 | 191 | *** Deinitialization of ADC *** |
<> | 144:ef7eb2e8f9f7 | 192 | ============================================================ |
<> | 144:ef7eb2e8f9f7 | 193 | [..] |
<> | 144:ef7eb2e8f9f7 | 194 | |
<> | 144:ef7eb2e8f9f7 | 195 | (#) Disable the ADC interface |
<> | 144:ef7eb2e8f9f7 | 196 | (++) ADC clock can be hard reset and disabled at RCC top level. |
<> | 144:ef7eb2e8f9f7 | 197 | (++) Hard reset of ADC peripherals |
<> | 144:ef7eb2e8f9f7 | 198 | using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). |
<> | 144:ef7eb2e8f9f7 | 199 | (++) ADC clock disable |
<> | 144:ef7eb2e8f9f7 | 200 | using the equivalent macro/functions as configuration step. |
<> | 144:ef7eb2e8f9f7 | 201 | (+++) Example: |
<> | 144:ef7eb2e8f9f7 | 202 | Into HAL_ADC_MspDeInit() (recommended code location) or with |
<> | 144:ef7eb2e8f9f7 | 203 | other device clock parameters configuration: |
<> | 144:ef7eb2e8f9f7 | 204 | (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; |
<> | 144:ef7eb2e8f9f7 | 205 | (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock) |
<> | 144:ef7eb2e8f9f7 | 206 | (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); |
<> | 144:ef7eb2e8f9f7 | 207 | |
<> | 144:ef7eb2e8f9f7 | 208 | (#) ADC pins configuration |
<> | 144:ef7eb2e8f9f7 | 209 | (++) Disable the clock for the ADC GPIOs |
<> | 144:ef7eb2e8f9f7 | 210 | using macro __HAL_RCC_GPIOx_CLK_DISABLE() |
<> | 144:ef7eb2e8f9f7 | 211 | |
<> | 144:ef7eb2e8f9f7 | 212 | (#) Optionally, in case of usage of ADC with interruptions: |
<> | 144:ef7eb2e8f9f7 | 213 | (++) Disable the NVIC for ADC |
<> | 144:ef7eb2e8f9f7 | 214 | using function HAL_NVIC_EnableIRQ(ADCx_IRQn) |
<> | 144:ef7eb2e8f9f7 | 215 | |
<> | 144:ef7eb2e8f9f7 | 216 | (#) Optionally, in case of usage of DMA: |
<> | 144:ef7eb2e8f9f7 | 217 | (++) Deinitialize the DMA |
<> | 144:ef7eb2e8f9f7 | 218 | using function HAL_DMA_Init(). |
<> | 144:ef7eb2e8f9f7 | 219 | (++) Disable the NVIC for DMA |
<> | 144:ef7eb2e8f9f7 | 220 | using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) |
<> | 144:ef7eb2e8f9f7 | 221 | |
<> | 144:ef7eb2e8f9f7 | 222 | [..] |
<> | 144:ef7eb2e8f9f7 | 223 | |
<> | 144:ef7eb2e8f9f7 | 224 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 225 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 226 | * @attention |
<> | 144:ef7eb2e8f9f7 | 227 | * |
<> | 144:ef7eb2e8f9f7 | 228 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 229 | * |
<> | 144:ef7eb2e8f9f7 | 230 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 231 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 232 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 233 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 234 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 235 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 236 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 237 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 238 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 239 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 240 | * |
<> | 144:ef7eb2e8f9f7 | 241 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 242 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 243 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 244 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 245 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 246 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 247 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 248 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 249 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 250 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 251 | * |
<> | 144:ef7eb2e8f9f7 | 252 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 253 | */ |
<> | 144:ef7eb2e8f9f7 | 254 | |
<> | 144:ef7eb2e8f9f7 | 255 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 256 | #include "stm32f0xx_hal.h" |
<> | 144:ef7eb2e8f9f7 | 257 | |
<> | 144:ef7eb2e8f9f7 | 258 | /** @addtogroup STM32F0xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 259 | * @{ |
<> | 144:ef7eb2e8f9f7 | 260 | */ |
<> | 144:ef7eb2e8f9f7 | 261 | |
<> | 144:ef7eb2e8f9f7 | 262 | /** @defgroup ADC ADC |
<> | 144:ef7eb2e8f9f7 | 263 | * @brief ADC HAL module driver |
<> | 144:ef7eb2e8f9f7 | 264 | * @{ |
<> | 144:ef7eb2e8f9f7 | 265 | */ |
<> | 144:ef7eb2e8f9f7 | 266 | |
<> | 144:ef7eb2e8f9f7 | 267 | #ifdef HAL_ADC_MODULE_ENABLED |
<> | 144:ef7eb2e8f9f7 | 268 | |
<> | 144:ef7eb2e8f9f7 | 269 | /* Private typedef -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 270 | /* Private define ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 271 | /** @defgroup ADC_Private_Constants ADC Private Constants |
<> | 144:ef7eb2e8f9f7 | 272 | * @{ |
<> | 144:ef7eb2e8f9f7 | 273 | */ |
<> | 144:ef7eb2e8f9f7 | 274 | |
<> | 144:ef7eb2e8f9f7 | 275 | /* Fixed timeout values for ADC calibration, enable settling time, disable */ |
<> | 144:ef7eb2e8f9f7 | 276 | /* settling time. */ |
<> | 144:ef7eb2e8f9f7 | 277 | /* Values defined to be higher than worst cases: low clock frequency, */ |
<> | 144:ef7eb2e8f9f7 | 278 | /* maximum prescaler. */ |
<> | 144:ef7eb2e8f9f7 | 279 | /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ |
<> | 144:ef7eb2e8f9f7 | 280 | /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */ |
<> | 144:ef7eb2e8f9f7 | 281 | /* Unit: ms */ |
<> | 156:95d6b41a828b | 282 | #define ADC_ENABLE_TIMEOUT ( 2U) |
<> | 156:95d6b41a828b | 283 | #define ADC_DISABLE_TIMEOUT ( 2U) |
<> | 156:95d6b41a828b | 284 | #define ADC_STOP_CONVERSION_TIMEOUT ( 2U) |
<> | 144:ef7eb2e8f9f7 | 285 | |
<> | 144:ef7eb2e8f9f7 | 286 | /* Delay for ADC stabilization time. */ |
<> | 144:ef7eb2e8f9f7 | 287 | /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ |
<> | 144:ef7eb2e8f9f7 | 288 | /* Unit: us */ |
<> | 156:95d6b41a828b | 289 | #define ADC_STAB_DELAY_US ( 1U) |
<> | 144:ef7eb2e8f9f7 | 290 | |
<> | 144:ef7eb2e8f9f7 | 291 | /* Delay for temperature sensor stabilization time. */ |
<> | 144:ef7eb2e8f9f7 | 292 | /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ |
<> | 144:ef7eb2e8f9f7 | 293 | /* Unit: us */ |
<> | 156:95d6b41a828b | 294 | #define ADC_TEMPSENSOR_DELAY_US ( 10U) |
<> | 144:ef7eb2e8f9f7 | 295 | |
<> | 144:ef7eb2e8f9f7 | 296 | /** |
<> | 144:ef7eb2e8f9f7 | 297 | * @} |
<> | 144:ef7eb2e8f9f7 | 298 | */ |
<> | 144:ef7eb2e8f9f7 | 299 | |
<> | 144:ef7eb2e8f9f7 | 300 | /* Private macro -------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 301 | /* Private variables ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 302 | /* Private function prototypes -----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 303 | /** @defgroup ADC_Private_Functions ADC Private Functions |
<> | 144:ef7eb2e8f9f7 | 304 | * @{ |
<> | 144:ef7eb2e8f9f7 | 305 | */ |
<> | 144:ef7eb2e8f9f7 | 306 | static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); |
<> | 144:ef7eb2e8f9f7 | 307 | static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc); |
<> | 144:ef7eb2e8f9f7 | 308 | static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc); |
<> | 144:ef7eb2e8f9f7 | 309 | static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 310 | static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 311 | static void ADC_DMAError(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 312 | /** |
<> | 144:ef7eb2e8f9f7 | 313 | * @} |
<> | 144:ef7eb2e8f9f7 | 314 | */ |
<> | 144:ef7eb2e8f9f7 | 315 | |
<> | 144:ef7eb2e8f9f7 | 316 | /* Exported functions ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 317 | |
<> | 144:ef7eb2e8f9f7 | 318 | /** @defgroup ADC_Exported_Functions ADC Exported Functions |
<> | 144:ef7eb2e8f9f7 | 319 | * @{ |
<> | 144:ef7eb2e8f9f7 | 320 | */ |
<> | 144:ef7eb2e8f9f7 | 321 | |
<> | 144:ef7eb2e8f9f7 | 322 | /** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 323 | * @brief Initialization and Configuration functions |
<> | 144:ef7eb2e8f9f7 | 324 | * |
<> | 144:ef7eb2e8f9f7 | 325 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 326 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 327 | ##### Initialization and de-initialization functions ##### |
<> | 144:ef7eb2e8f9f7 | 328 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 329 | [..] This section provides functions allowing to: |
<> | 144:ef7eb2e8f9f7 | 330 | (+) Initialize and configure the ADC. |
<> | 144:ef7eb2e8f9f7 | 331 | (+) De-initialize the ADC |
<> | 144:ef7eb2e8f9f7 | 332 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 333 | * @{ |
<> | 144:ef7eb2e8f9f7 | 334 | */ |
<> | 144:ef7eb2e8f9f7 | 335 | |
<> | 144:ef7eb2e8f9f7 | 336 | /** |
<> | 144:ef7eb2e8f9f7 | 337 | * @brief Initializes the ADC peripheral and regular group according to |
<> | 144:ef7eb2e8f9f7 | 338 | * parameters specified in structure "ADC_InitTypeDef". |
<> | 144:ef7eb2e8f9f7 | 339 | * @note As prerequisite, ADC clock must be configured at RCC top level |
<> | 144:ef7eb2e8f9f7 | 340 | * depending on both possible clock sources: APB clock of HSI clock. |
<> | 144:ef7eb2e8f9f7 | 341 | * See commented example code below that can be copied and uncommented |
<> | 144:ef7eb2e8f9f7 | 342 | * into HAL_ADC_MspInit(). |
<> | 144:ef7eb2e8f9f7 | 343 | * @note Possibility to update parameters on the fly: |
<> | 144:ef7eb2e8f9f7 | 344 | * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when |
<> | 144:ef7eb2e8f9f7 | 345 | * coming from ADC state reset. Following calls to this function can |
<> | 144:ef7eb2e8f9f7 | 346 | * be used to reconfigure some parameters of ADC_InitTypeDef |
<> | 144:ef7eb2e8f9f7 | 347 | * structure on the fly, without modifying MSP configuration. If ADC |
<> | 144:ef7eb2e8f9f7 | 348 | * MSP has to be modified again, HAL_ADC_DeInit() must be called |
<> | 144:ef7eb2e8f9f7 | 349 | * before HAL_ADC_Init(). |
<> | 144:ef7eb2e8f9f7 | 350 | * The setting of these parameters is conditioned to ADC state. |
<> | 144:ef7eb2e8f9f7 | 351 | * For parameters constraints, see comments of structure |
<> | 144:ef7eb2e8f9f7 | 352 | * "ADC_InitTypeDef". |
<> | 144:ef7eb2e8f9f7 | 353 | * @note This function configures the ADC within 2 scopes: scope of entire |
<> | 144:ef7eb2e8f9f7 | 354 | * ADC and scope of regular group. For parameters details, see comments |
<> | 144:ef7eb2e8f9f7 | 355 | * of structure "ADC_InitTypeDef". |
Anna Bridge |
180:96ed750bd169 | 356 | * @param hadc ADC handle |
<> | 144:ef7eb2e8f9f7 | 357 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 358 | */ |
<> | 144:ef7eb2e8f9f7 | 359 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 360 | { |
<> | 144:ef7eb2e8f9f7 | 361 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 156:95d6b41a828b | 362 | uint32_t tmpCFGR1 = 0U; |
<> | 144:ef7eb2e8f9f7 | 363 | |
<> | 144:ef7eb2e8f9f7 | 364 | /* Check ADC handle */ |
<> | 144:ef7eb2e8f9f7 | 365 | if(hadc == NULL) |
<> | 144:ef7eb2e8f9f7 | 366 | { |
<> | 144:ef7eb2e8f9f7 | 367 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 368 | } |
<> | 144:ef7eb2e8f9f7 | 369 | |
<> | 144:ef7eb2e8f9f7 | 370 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 371 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 372 | assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); |
<> | 144:ef7eb2e8f9f7 | 373 | assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); |
<> | 144:ef7eb2e8f9f7 | 374 | assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); |
<> | 144:ef7eb2e8f9f7 | 375 | assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); |
<> | 144:ef7eb2e8f9f7 | 376 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
<> | 144:ef7eb2e8f9f7 | 377 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); |
<> | 144:ef7eb2e8f9f7 | 378 | assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); |
<> | 144:ef7eb2e8f9f7 | 379 | assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); |
<> | 144:ef7eb2e8f9f7 | 380 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); |
<> | 144:ef7eb2e8f9f7 | 381 | assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); |
<> | 144:ef7eb2e8f9f7 | 382 | assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); |
<> | 144:ef7eb2e8f9f7 | 383 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); |
<> | 144:ef7eb2e8f9f7 | 384 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff)); |
<> | 144:ef7eb2e8f9f7 | 385 | |
<> | 144:ef7eb2e8f9f7 | 386 | /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ |
<> | 144:ef7eb2e8f9f7 | 387 | /* at RCC top level depending on both possible clock sources: */ |
<> | 144:ef7eb2e8f9f7 | 388 | /* APB clock or HSI clock. */ |
<> | 144:ef7eb2e8f9f7 | 389 | /* Refer to header of this file for more details on clock enabling procedure*/ |
<> | 144:ef7eb2e8f9f7 | 390 | |
<> | 144:ef7eb2e8f9f7 | 391 | /* Actions performed only if ADC is coming from state reset: */ |
<> | 144:ef7eb2e8f9f7 | 392 | /* - Initialization of ADC MSP */ |
<> | 144:ef7eb2e8f9f7 | 393 | /* - ADC voltage regulator enable */ |
<> | 144:ef7eb2e8f9f7 | 394 | if (hadc->State == HAL_ADC_STATE_RESET) |
<> | 144:ef7eb2e8f9f7 | 395 | { |
<> | 144:ef7eb2e8f9f7 | 396 | /* Initialize ADC error code */ |
<> | 144:ef7eb2e8f9f7 | 397 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 398 | |
<> | 144:ef7eb2e8f9f7 | 399 | /* Allocate lock resource and initialize it */ |
<> | 144:ef7eb2e8f9f7 | 400 | hadc->Lock = HAL_UNLOCKED; |
<> | 144:ef7eb2e8f9f7 | 401 | |
<> | 144:ef7eb2e8f9f7 | 402 | /* Init the low level hardware */ |
<> | 144:ef7eb2e8f9f7 | 403 | HAL_ADC_MspInit(hadc); |
<> | 144:ef7eb2e8f9f7 | 404 | } |
<> | 144:ef7eb2e8f9f7 | 405 | |
<> | 144:ef7eb2e8f9f7 | 406 | /* Configuration of ADC parameters if previous preliminary actions are */ |
<> | 144:ef7eb2e8f9f7 | 407 | /* correctly completed. */ |
<> | 144:ef7eb2e8f9f7 | 408 | /* and if there is no conversion on going on regular group (ADC can be */ |
<> | 144:ef7eb2e8f9f7 | 409 | /* enabled anyway, in case of call of this function to update a parameter */ |
<> | 144:ef7eb2e8f9f7 | 410 | /* on the fly). */ |
<> | 144:ef7eb2e8f9f7 | 411 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && |
<> | 144:ef7eb2e8f9f7 | 412 | (tmp_hal_status == HAL_OK) && |
<> | 144:ef7eb2e8f9f7 | 413 | (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) |
<> | 144:ef7eb2e8f9f7 | 414 | { |
<> | 144:ef7eb2e8f9f7 | 415 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 416 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 417 | HAL_ADC_STATE_REG_BUSY, |
<> | 144:ef7eb2e8f9f7 | 418 | HAL_ADC_STATE_BUSY_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 419 | |
<> | 144:ef7eb2e8f9f7 | 420 | /* Parameters update conditioned to ADC state: */ |
<> | 144:ef7eb2e8f9f7 | 421 | /* Parameters that can be updated only when ADC is disabled: */ |
<> | 144:ef7eb2e8f9f7 | 422 | /* - ADC clock mode */ |
<> | 144:ef7eb2e8f9f7 | 423 | /* - ADC clock prescaler */ |
<> | 144:ef7eb2e8f9f7 | 424 | /* - ADC resolution */ |
<> | 144:ef7eb2e8f9f7 | 425 | if (ADC_IS_ENABLE(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 426 | { |
<> | 144:ef7eb2e8f9f7 | 427 | /* Some parameters of this register are not reset, since they are set */ |
<> | 144:ef7eb2e8f9f7 | 428 | /* by other functions and must be kept in case of usage of this */ |
<> | 144:ef7eb2e8f9f7 | 429 | /* function on the fly (update of a parameter of ADC_InitTypeDef */ |
<> | 144:ef7eb2e8f9f7 | 430 | /* without needing to reconfigure all other ADC groups/channels */ |
<> | 144:ef7eb2e8f9f7 | 431 | /* parameters): */ |
<> | 144:ef7eb2e8f9f7 | 432 | /* - internal measurement paths: Vbat, temperature sensor, Vref */ |
<> | 144:ef7eb2e8f9f7 | 433 | /* (set into HAL_ADC_ConfigChannel() ) */ |
<> | 144:ef7eb2e8f9f7 | 434 | |
<> | 144:ef7eb2e8f9f7 | 435 | /* Configuration of ADC resolution */ |
<> | 144:ef7eb2e8f9f7 | 436 | MODIFY_REG(hadc->Instance->CFGR1, |
<> | 144:ef7eb2e8f9f7 | 437 | ADC_CFGR1_RES , |
<> | 144:ef7eb2e8f9f7 | 438 | hadc->Init.Resolution ); |
<> | 144:ef7eb2e8f9f7 | 439 | |
<> | 144:ef7eb2e8f9f7 | 440 | /* Configuration of ADC clock mode: clock source AHB or HSI with */ |
<> | 144:ef7eb2e8f9f7 | 441 | /* selectable prescaler */ |
<> | 144:ef7eb2e8f9f7 | 442 | MODIFY_REG(hadc->Instance->CFGR2 , |
<> | 144:ef7eb2e8f9f7 | 443 | ADC_CFGR2_CKMODE , |
<> | 144:ef7eb2e8f9f7 | 444 | hadc->Init.ClockPrescaler ); |
<> | 144:ef7eb2e8f9f7 | 445 | } |
<> | 144:ef7eb2e8f9f7 | 446 | |
<> | 144:ef7eb2e8f9f7 | 447 | /* Configuration of ADC: */ |
<> | 144:ef7eb2e8f9f7 | 448 | /* - discontinuous mode */ |
<> | 144:ef7eb2e8f9f7 | 449 | /* - LowPowerAutoWait mode */ |
<> | 144:ef7eb2e8f9f7 | 450 | /* - LowPowerAutoPowerOff mode */ |
<> | 144:ef7eb2e8f9f7 | 451 | /* - continuous conversion mode */ |
<> | 144:ef7eb2e8f9f7 | 452 | /* - overrun */ |
<> | 144:ef7eb2e8f9f7 | 453 | /* - external trigger to start conversion */ |
<> | 144:ef7eb2e8f9f7 | 454 | /* - external trigger polarity */ |
<> | 144:ef7eb2e8f9f7 | 455 | /* - data alignment */ |
<> | 144:ef7eb2e8f9f7 | 456 | /* - resolution */ |
<> | 144:ef7eb2e8f9f7 | 457 | /* - scan direction */ |
<> | 144:ef7eb2e8f9f7 | 458 | /* - DMA continuous request */ |
<> | 144:ef7eb2e8f9f7 | 459 | hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN | |
<> | 144:ef7eb2e8f9f7 | 460 | ADC_CFGR1_AUTOFF | |
<> | 144:ef7eb2e8f9f7 | 461 | ADC_CFGR1_AUTDLY | |
<> | 144:ef7eb2e8f9f7 | 462 | ADC_CFGR1_CONT | |
<> | 144:ef7eb2e8f9f7 | 463 | ADC_CFGR1_OVRMOD | |
<> | 144:ef7eb2e8f9f7 | 464 | ADC_CFGR1_EXTSEL | |
<> | 144:ef7eb2e8f9f7 | 465 | ADC_CFGR1_EXTEN | |
<> | 144:ef7eb2e8f9f7 | 466 | ADC_CFGR1_ALIGN | |
<> | 144:ef7eb2e8f9f7 | 467 | ADC_CFGR1_SCANDIR | |
<> | 144:ef7eb2e8f9f7 | 468 | ADC_CFGR1_DMACFG ); |
<> | 144:ef7eb2e8f9f7 | 469 | |
<> | 144:ef7eb2e8f9f7 | 470 | tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT(hadc->Init.LowPowerAutoWait) | |
<> | 144:ef7eb2e8f9f7 | 471 | ADC_CFGR1_AUTOOFF(hadc->Init.LowPowerAutoPowerOff) | |
<> | 144:ef7eb2e8f9f7 | 472 | ADC_CFGR1_CONTINUOUS(hadc->Init.ContinuousConvMode) | |
<> | 144:ef7eb2e8f9f7 | 473 | ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | |
<> | 144:ef7eb2e8f9f7 | 474 | hadc->Init.DataAlign | |
<> | 144:ef7eb2e8f9f7 | 475 | ADC_SCANDIR(hadc->Init.ScanConvMode) | |
<> | 144:ef7eb2e8f9f7 | 476 | ADC_CFGR1_DMACONTREQ(hadc->Init.DMAContinuousRequests) ); |
<> | 144:ef7eb2e8f9f7 | 477 | |
<> | 144:ef7eb2e8f9f7 | 478 | /* Enable discontinuous mode only if continuous mode is disabled */ |
<> | 144:ef7eb2e8f9f7 | 479 | if (hadc->Init.DiscontinuousConvMode == ENABLE) |
<> | 144:ef7eb2e8f9f7 | 480 | { |
<> | 144:ef7eb2e8f9f7 | 481 | if (hadc->Init.ContinuousConvMode == DISABLE) |
<> | 144:ef7eb2e8f9f7 | 482 | { |
<> | 144:ef7eb2e8f9f7 | 483 | /* Enable the selected ADC group regular discontinuous mode */ |
<> | 144:ef7eb2e8f9f7 | 484 | tmpCFGR1 |= ADC_CFGR1_DISCEN; |
<> | 144:ef7eb2e8f9f7 | 485 | } |
<> | 144:ef7eb2e8f9f7 | 486 | else |
<> | 144:ef7eb2e8f9f7 | 487 | { |
<> | 144:ef7eb2e8f9f7 | 488 | /* ADC regular group discontinuous was intended to be enabled, */ |
<> | 144:ef7eb2e8f9f7 | 489 | /* but ADC regular group modes continuous and sequencer discontinuous */ |
<> | 144:ef7eb2e8f9f7 | 490 | /* cannot be enabled simultaneously. */ |
<> | 144:ef7eb2e8f9f7 | 491 | |
<> | 144:ef7eb2e8f9f7 | 492 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 493 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
<> | 144:ef7eb2e8f9f7 | 494 | |
<> | 144:ef7eb2e8f9f7 | 495 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 496 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 497 | } |
<> | 144:ef7eb2e8f9f7 | 498 | } |
<> | 144:ef7eb2e8f9f7 | 499 | |
<> | 144:ef7eb2e8f9f7 | 500 | /* Enable external trigger if trigger selection is different of software */ |
<> | 144:ef7eb2e8f9f7 | 501 | /* start. */ |
<> | 144:ef7eb2e8f9f7 | 502 | /* Note: This configuration keeps the hardware feature of parameter */ |
<> | 144:ef7eb2e8f9f7 | 503 | /* ExternalTrigConvEdge "trigger edge none" equivalent to */ |
<> | 144:ef7eb2e8f9f7 | 504 | /* software start. */ |
<> | 144:ef7eb2e8f9f7 | 505 | if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) |
<> | 144:ef7eb2e8f9f7 | 506 | { |
<> | 144:ef7eb2e8f9f7 | 507 | tmpCFGR1 |= ( hadc->Init.ExternalTrigConv | |
<> | 144:ef7eb2e8f9f7 | 508 | hadc->Init.ExternalTrigConvEdge ); |
<> | 144:ef7eb2e8f9f7 | 509 | } |
<> | 144:ef7eb2e8f9f7 | 510 | |
<> | 144:ef7eb2e8f9f7 | 511 | /* Update ADC configuration register with previous settings */ |
<> | 144:ef7eb2e8f9f7 | 512 | hadc->Instance->CFGR1 |= tmpCFGR1; |
<> | 144:ef7eb2e8f9f7 | 513 | |
<> | 144:ef7eb2e8f9f7 | 514 | /* Channel sampling time configuration */ |
<> | 144:ef7eb2e8f9f7 | 515 | /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ |
<> | 144:ef7eb2e8f9f7 | 516 | /* (obsolete): sampling time set in this function if parameter */ |
<> | 144:ef7eb2e8f9f7 | 517 | /* "SamplingTimeCommon" has been set to a valid sampling time. */ |
<> | 144:ef7eb2e8f9f7 | 518 | /* Otherwise, sampling time is set into ADC channel initialization */ |
<> | 144:ef7eb2e8f9f7 | 519 | /* structure with parameter "SamplingTime" (obsolete). */ |
<> | 144:ef7eb2e8f9f7 | 520 | if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) |
<> | 144:ef7eb2e8f9f7 | 521 | { |
<> | 144:ef7eb2e8f9f7 | 522 | /* Channel sampling time configuration */ |
<> | 144:ef7eb2e8f9f7 | 523 | /* Clear the old sample time */ |
<> | 144:ef7eb2e8f9f7 | 524 | hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); |
<> | 144:ef7eb2e8f9f7 | 525 | |
<> | 144:ef7eb2e8f9f7 | 526 | /* Set the new sample time */ |
<> | 144:ef7eb2e8f9f7 | 527 | hadc->Instance->SMPR |= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon); |
<> | 144:ef7eb2e8f9f7 | 528 | } |
<> | 144:ef7eb2e8f9f7 | 529 | |
<> | 144:ef7eb2e8f9f7 | 530 | /* Check back that ADC registers have effectively been configured to */ |
<> | 144:ef7eb2e8f9f7 | 531 | /* ensure of no potential problem of ADC core IP clocking. */ |
<> | 144:ef7eb2e8f9f7 | 532 | /* Check through register CFGR1 (excluding analog watchdog configuration: */ |
<> | 144:ef7eb2e8f9f7 | 533 | /* set into separate dedicated function, and bits of ADC resolution set */ |
<> | 144:ef7eb2e8f9f7 | 534 | /* out of temporary variable 'tmpCFGR1'). */ |
<> | 144:ef7eb2e8f9f7 | 535 | if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) |
<> | 144:ef7eb2e8f9f7 | 536 | == tmpCFGR1) |
<> | 144:ef7eb2e8f9f7 | 537 | { |
<> | 144:ef7eb2e8f9f7 | 538 | /* Set ADC error code to none */ |
<> | 144:ef7eb2e8f9f7 | 539 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 540 | |
<> | 144:ef7eb2e8f9f7 | 541 | /* Set the ADC state */ |
<> | 144:ef7eb2e8f9f7 | 542 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 543 | HAL_ADC_STATE_BUSY_INTERNAL, |
<> | 144:ef7eb2e8f9f7 | 544 | HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 545 | } |
<> | 144:ef7eb2e8f9f7 | 546 | else |
<> | 144:ef7eb2e8f9f7 | 547 | { |
<> | 144:ef7eb2e8f9f7 | 548 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 549 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 550 | HAL_ADC_STATE_BUSY_INTERNAL, |
<> | 144:ef7eb2e8f9f7 | 551 | HAL_ADC_STATE_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 552 | |
<> | 144:ef7eb2e8f9f7 | 553 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 554 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 555 | |
<> | 144:ef7eb2e8f9f7 | 556 | tmp_hal_status = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 557 | } |
<> | 144:ef7eb2e8f9f7 | 558 | |
<> | 144:ef7eb2e8f9f7 | 559 | } |
<> | 144:ef7eb2e8f9f7 | 560 | else |
<> | 144:ef7eb2e8f9f7 | 561 | { |
<> | 144:ef7eb2e8f9f7 | 562 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 563 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 564 | |
<> | 144:ef7eb2e8f9f7 | 565 | tmp_hal_status = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 566 | } |
<> | 144:ef7eb2e8f9f7 | 567 | |
<> | 144:ef7eb2e8f9f7 | 568 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 569 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 570 | } |
<> | 144:ef7eb2e8f9f7 | 571 | |
<> | 144:ef7eb2e8f9f7 | 572 | |
<> | 144:ef7eb2e8f9f7 | 573 | /** |
<> | 144:ef7eb2e8f9f7 | 574 | * @brief Deinitialize the ADC peripheral registers to their default reset |
<> | 144:ef7eb2e8f9f7 | 575 | * values, with deinitialization of the ADC MSP. |
<> | 144:ef7eb2e8f9f7 | 576 | * @note For devices with several ADCs: reset of ADC common registers is done |
<> | 144:ef7eb2e8f9f7 | 577 | * only if all ADCs sharing the same common group are disabled. |
<> | 144:ef7eb2e8f9f7 | 578 | * If this is not the case, reset of these common parameters reset is |
<> | 144:ef7eb2e8f9f7 | 579 | * bypassed without error reporting: it can be the intended behaviour in |
<> | 144:ef7eb2e8f9f7 | 580 | * case of reset of a single ADC while the other ADCs sharing the same |
<> | 144:ef7eb2e8f9f7 | 581 | * common group is still running. |
Anna Bridge |
180:96ed750bd169 | 582 | * @param hadc ADC handle |
<> | 144:ef7eb2e8f9f7 | 583 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 584 | */ |
<> | 144:ef7eb2e8f9f7 | 585 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 586 | { |
<> | 144:ef7eb2e8f9f7 | 587 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 588 | |
<> | 144:ef7eb2e8f9f7 | 589 | /* Check ADC handle */ |
<> | 144:ef7eb2e8f9f7 | 590 | if(hadc == NULL) |
<> | 144:ef7eb2e8f9f7 | 591 | { |
<> | 144:ef7eb2e8f9f7 | 592 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 593 | } |
<> | 144:ef7eb2e8f9f7 | 594 | |
<> | 144:ef7eb2e8f9f7 | 595 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 596 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 597 | |
<> | 144:ef7eb2e8f9f7 | 598 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 599 | SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 600 | |
<> | 144:ef7eb2e8f9f7 | 601 | /* Stop potential conversion on going, on regular group */ |
<> | 144:ef7eb2e8f9f7 | 602 | tmp_hal_status = ADC_ConversionStop(hadc); |
<> | 144:ef7eb2e8f9f7 | 603 | |
<> | 144:ef7eb2e8f9f7 | 604 | /* Disable ADC peripheral if conversions are effectively stopped */ |
<> | 144:ef7eb2e8f9f7 | 605 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 606 | { |
<> | 144:ef7eb2e8f9f7 | 607 | /* Disable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 608 | tmp_hal_status = ADC_Disable(hadc); |
<> | 144:ef7eb2e8f9f7 | 609 | |
<> | 144:ef7eb2e8f9f7 | 610 | /* Check if ADC is effectively disabled */ |
<> | 144:ef7eb2e8f9f7 | 611 | if (tmp_hal_status != HAL_ERROR) |
<> | 144:ef7eb2e8f9f7 | 612 | { |
<> | 144:ef7eb2e8f9f7 | 613 | /* Change ADC state */ |
<> | 144:ef7eb2e8f9f7 | 614 | hadc->State = HAL_ADC_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 615 | } |
<> | 144:ef7eb2e8f9f7 | 616 | } |
<> | 144:ef7eb2e8f9f7 | 617 | |
<> | 144:ef7eb2e8f9f7 | 618 | |
<> | 144:ef7eb2e8f9f7 | 619 | /* Configuration of ADC parameters if previous preliminary actions are */ |
<> | 144:ef7eb2e8f9f7 | 620 | /* correctly completed. */ |
<> | 144:ef7eb2e8f9f7 | 621 | if (tmp_hal_status != HAL_ERROR) |
<> | 144:ef7eb2e8f9f7 | 622 | { |
<> | 144:ef7eb2e8f9f7 | 623 | |
<> | 144:ef7eb2e8f9f7 | 624 | /* ========== Reset ADC registers ========== */ |
<> | 144:ef7eb2e8f9f7 | 625 | /* Reset register IER */ |
<> | 144:ef7eb2e8f9f7 | 626 | __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD | ADC_IT_OVR | |
<> | 144:ef7eb2e8f9f7 | 627 | ADC_IT_EOS | ADC_IT_EOC | |
<> | 144:ef7eb2e8f9f7 | 628 | ADC_IT_EOSMP | ADC_IT_RDY ) ); |
<> | 144:ef7eb2e8f9f7 | 629 | |
<> | 144:ef7eb2e8f9f7 | 630 | /* Reset register ISR */ |
<> | 144:ef7eb2e8f9f7 | 631 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_OVR | |
<> | 144:ef7eb2e8f9f7 | 632 | ADC_FLAG_EOS | ADC_FLAG_EOC | |
<> | 144:ef7eb2e8f9f7 | 633 | ADC_FLAG_EOSMP | ADC_FLAG_RDY ) ); |
<> | 144:ef7eb2e8f9f7 | 634 | |
<> | 144:ef7eb2e8f9f7 | 635 | /* Reset register CR */ |
<> | 144:ef7eb2e8f9f7 | 636 | /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */ |
<> | 144:ef7eb2e8f9f7 | 637 | /* "read-set": no direct reset applicable. */ |
<> | 144:ef7eb2e8f9f7 | 638 | |
<> | 144:ef7eb2e8f9f7 | 639 | /* Reset register CFGR1 */ |
<> | 144:ef7eb2e8f9f7 | 640 | hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_DISCEN | |
<> | 144:ef7eb2e8f9f7 | 641 | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | |
<> | 144:ef7eb2e8f9f7 | 642 | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES | |
<> | 144:ef7eb2e8f9f7 | 643 | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN ); |
<> | 144:ef7eb2e8f9f7 | 644 | |
<> | 144:ef7eb2e8f9f7 | 645 | /* Reset register CFGR2 */ |
<> | 144:ef7eb2e8f9f7 | 646 | /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */ |
<> | 144:ef7eb2e8f9f7 | 647 | /* already done above. */ |
<> | 144:ef7eb2e8f9f7 | 648 | hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE; |
<> | 144:ef7eb2e8f9f7 | 649 | |
<> | 144:ef7eb2e8f9f7 | 650 | /* Reset register SMPR */ |
<> | 144:ef7eb2e8f9f7 | 651 | hadc->Instance->SMPR &= ~ADC_SMPR_SMP; |
<> | 144:ef7eb2e8f9f7 | 652 | |
<> | 144:ef7eb2e8f9f7 | 653 | /* Reset register TR1 */ |
<> | 144:ef7eb2e8f9f7 | 654 | hadc->Instance->TR &= ~(ADC_TR_HT | ADC_TR_LT); |
<> | 144:ef7eb2e8f9f7 | 655 | |
<> | 144:ef7eb2e8f9f7 | 656 | /* Reset register CHSELR */ |
<> | 144:ef7eb2e8f9f7 | 657 | hadc->Instance->CHSELR &= ~(ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16 | |
<> | 144:ef7eb2e8f9f7 | 658 | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12 | |
<> | 144:ef7eb2e8f9f7 | 659 | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8 | |
<> | 144:ef7eb2e8f9f7 | 660 | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4 | |
<> | 144:ef7eb2e8f9f7 | 661 | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 ); |
<> | 144:ef7eb2e8f9f7 | 662 | |
<> | 144:ef7eb2e8f9f7 | 663 | /* Reset register DR */ |
<> | 144:ef7eb2e8f9f7 | 664 | /* bits in access mode read only, no direct reset applicable*/ |
<> | 144:ef7eb2e8f9f7 | 665 | |
<> | 144:ef7eb2e8f9f7 | 666 | /* Reset register CCR */ |
<> | 144:ef7eb2e8f9f7 | 667 | ADC->CCR &= ~(ADC_CCR_ALL); |
<> | 144:ef7eb2e8f9f7 | 668 | |
<> | 144:ef7eb2e8f9f7 | 669 | /* ========== Hard reset ADC peripheral ========== */ |
<> | 144:ef7eb2e8f9f7 | 670 | /* Performs a global reset of the entire ADC peripheral: ADC state is */ |
<> | 144:ef7eb2e8f9f7 | 671 | /* forced to a similar state after device power-on. */ |
<> | 144:ef7eb2e8f9f7 | 672 | /* If needed, copy-paste and uncomment the following reset code into */ |
<> | 144:ef7eb2e8f9f7 | 673 | /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ |
<> | 144:ef7eb2e8f9f7 | 674 | /* */ |
<> | 144:ef7eb2e8f9f7 | 675 | /* __HAL_RCC_ADC1_FORCE_RESET() */ |
<> | 144:ef7eb2e8f9f7 | 676 | /* __HAL_RCC_ADC1_RELEASE_RESET() */ |
<> | 144:ef7eb2e8f9f7 | 677 | |
<> | 144:ef7eb2e8f9f7 | 678 | /* DeInit the low level hardware */ |
<> | 144:ef7eb2e8f9f7 | 679 | HAL_ADC_MspDeInit(hadc); |
<> | 144:ef7eb2e8f9f7 | 680 | |
<> | 144:ef7eb2e8f9f7 | 681 | /* Set ADC error code to none */ |
<> | 144:ef7eb2e8f9f7 | 682 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 683 | |
<> | 144:ef7eb2e8f9f7 | 684 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 685 | hadc->State = HAL_ADC_STATE_RESET; |
<> | 144:ef7eb2e8f9f7 | 686 | } |
<> | 144:ef7eb2e8f9f7 | 687 | |
<> | 144:ef7eb2e8f9f7 | 688 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 689 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 690 | |
<> | 144:ef7eb2e8f9f7 | 691 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 692 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 693 | } |
<> | 144:ef7eb2e8f9f7 | 694 | |
<> | 144:ef7eb2e8f9f7 | 695 | |
<> | 144:ef7eb2e8f9f7 | 696 | /** |
<> | 144:ef7eb2e8f9f7 | 697 | * @brief Initializes the ADC MSP. |
Anna Bridge |
180:96ed750bd169 | 698 | * @param hadc ADC handle |
<> | 144:ef7eb2e8f9f7 | 699 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 700 | */ |
<> | 144:ef7eb2e8f9f7 | 701 | __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 702 | { |
<> | 144:ef7eb2e8f9f7 | 703 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 704 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 705 | |
<> | 144:ef7eb2e8f9f7 | 706 | /* NOTE : This function should not be modified. When the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 707 | function HAL_ADC_MspInit must be implemented in the user file. |
<> | 144:ef7eb2e8f9f7 | 708 | */ |
<> | 144:ef7eb2e8f9f7 | 709 | } |
<> | 144:ef7eb2e8f9f7 | 710 | |
<> | 144:ef7eb2e8f9f7 | 711 | /** |
<> | 144:ef7eb2e8f9f7 | 712 | * @brief DeInitializes the ADC MSP. |
Anna Bridge |
180:96ed750bd169 | 713 | * @param hadc ADC handle |
<> | 144:ef7eb2e8f9f7 | 714 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 715 | */ |
<> | 144:ef7eb2e8f9f7 | 716 | __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 717 | { |
<> | 144:ef7eb2e8f9f7 | 718 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 719 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 720 | |
<> | 144:ef7eb2e8f9f7 | 721 | /* NOTE : This function should not be modified. When the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 722 | function HAL_ADC_MspDeInit must be implemented in the user file. |
<> | 144:ef7eb2e8f9f7 | 723 | */ |
<> | 144:ef7eb2e8f9f7 | 724 | } |
<> | 144:ef7eb2e8f9f7 | 725 | |
<> | 144:ef7eb2e8f9f7 | 726 | /** |
<> | 144:ef7eb2e8f9f7 | 727 | * @} |
<> | 144:ef7eb2e8f9f7 | 728 | */ |
<> | 144:ef7eb2e8f9f7 | 729 | |
<> | 144:ef7eb2e8f9f7 | 730 | /** @defgroup ADC_Exported_Functions_Group2 IO operation functions |
<> | 144:ef7eb2e8f9f7 | 731 | * @brief IO operation functions |
<> | 144:ef7eb2e8f9f7 | 732 | * |
<> | 144:ef7eb2e8f9f7 | 733 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 734 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 735 | ##### IO operation functions ##### |
<> | 144:ef7eb2e8f9f7 | 736 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 737 | [..] This section provides functions allowing to: |
<> | 144:ef7eb2e8f9f7 | 738 | (+) Start conversion of regular group. |
<> | 144:ef7eb2e8f9f7 | 739 | (+) Stop conversion of regular group. |
<> | 144:ef7eb2e8f9f7 | 740 | (+) Poll for conversion complete on regular group. |
<> | 144:ef7eb2e8f9f7 | 741 | (+) Poll for conversion event. |
<> | 144:ef7eb2e8f9f7 | 742 | (+) Get result of regular channel conversion. |
<> | 144:ef7eb2e8f9f7 | 743 | (+) Start conversion of regular group and enable interruptions. |
<> | 144:ef7eb2e8f9f7 | 744 | (+) Stop conversion of regular group and disable interruptions. |
<> | 144:ef7eb2e8f9f7 | 745 | (+) Handle ADC interrupt request |
<> | 144:ef7eb2e8f9f7 | 746 | (+) Start conversion of regular group and enable DMA transfer. |
<> | 144:ef7eb2e8f9f7 | 747 | (+) Stop conversion of regular group and disable ADC DMA transfer. |
<> | 144:ef7eb2e8f9f7 | 748 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 749 | * @{ |
<> | 144:ef7eb2e8f9f7 | 750 | */ |
<> | 144:ef7eb2e8f9f7 | 751 | |
<> | 144:ef7eb2e8f9f7 | 752 | /** |
<> | 144:ef7eb2e8f9f7 | 753 | * @brief Enables ADC, starts conversion of regular group. |
<> | 144:ef7eb2e8f9f7 | 754 | * Interruptions enabled in this function: None. |
Anna Bridge |
180:96ed750bd169 | 755 | * @param hadc ADC handle |
<> | 144:ef7eb2e8f9f7 | 756 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 757 | */ |
<> | 144:ef7eb2e8f9f7 | 758 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 759 | { |
<> | 144:ef7eb2e8f9f7 | 760 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 761 | |
<> | 144:ef7eb2e8f9f7 | 762 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 763 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 764 | |
<> | 144:ef7eb2e8f9f7 | 765 | /* Perform ADC enable and conversion start if no conversion is on going */ |
<> | 144:ef7eb2e8f9f7 | 766 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 767 | { |
<> | 144:ef7eb2e8f9f7 | 768 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 769 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 770 | |
<> | 144:ef7eb2e8f9f7 | 771 | /* Enable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 772 | /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ |
<> | 144:ef7eb2e8f9f7 | 773 | /* performed automatically by hardware. */ |
<> | 144:ef7eb2e8f9f7 | 774 | if (hadc->Init.LowPowerAutoPowerOff != ENABLE) |
<> | 144:ef7eb2e8f9f7 | 775 | { |
<> | 144:ef7eb2e8f9f7 | 776 | tmp_hal_status = ADC_Enable(hadc); |
<> | 144:ef7eb2e8f9f7 | 777 | } |
<> | 144:ef7eb2e8f9f7 | 778 | |
<> | 144:ef7eb2e8f9f7 | 779 | /* Start conversion if ADC is effectively enabled */ |
<> | 144:ef7eb2e8f9f7 | 780 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 781 | { |
<> | 144:ef7eb2e8f9f7 | 782 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 783 | /* - Clear state bitfield related to regular group conversion results */ |
<> | 144:ef7eb2e8f9f7 | 784 | /* - Set state bitfield related to regular operation */ |
<> | 144:ef7eb2e8f9f7 | 785 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 786 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, |
<> | 144:ef7eb2e8f9f7 | 787 | HAL_ADC_STATE_REG_BUSY); |
<> | 144:ef7eb2e8f9f7 | 788 | |
<> | 144:ef7eb2e8f9f7 | 789 | /* Reset ADC all error code fields */ |
<> | 144:ef7eb2e8f9f7 | 790 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 791 | |
<> | 144:ef7eb2e8f9f7 | 792 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 793 | /* Unlock before starting ADC conversions: in case of potential */ |
<> | 144:ef7eb2e8f9f7 | 794 | /* interruption, to let the process to ADC IRQ Handler. */ |
<> | 144:ef7eb2e8f9f7 | 795 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 796 | |
<> | 144:ef7eb2e8f9f7 | 797 | /* Clear regular group conversion flag and overrun flag */ |
<> | 144:ef7eb2e8f9f7 | 798 | /* (To ensure of no unknown state from potential previous ADC */ |
<> | 144:ef7eb2e8f9f7 | 799 | /* operations) */ |
<> | 144:ef7eb2e8f9f7 | 800 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); |
<> | 144:ef7eb2e8f9f7 | 801 | |
<> | 144:ef7eb2e8f9f7 | 802 | /* Enable conversion of regular group. */ |
<> | 144:ef7eb2e8f9f7 | 803 | /* If software start has been selected, conversion starts immediately. */ |
<> | 144:ef7eb2e8f9f7 | 804 | /* If external trigger has been selected, conversion will start at next */ |
<> | 144:ef7eb2e8f9f7 | 805 | /* trigger event. */ |
<> | 144:ef7eb2e8f9f7 | 806 | hadc->Instance->CR |= ADC_CR_ADSTART; |
<> | 144:ef7eb2e8f9f7 | 807 | } |
<> | 144:ef7eb2e8f9f7 | 808 | } |
<> | 144:ef7eb2e8f9f7 | 809 | else |
<> | 144:ef7eb2e8f9f7 | 810 | { |
<> | 144:ef7eb2e8f9f7 | 811 | tmp_hal_status = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 812 | } |
<> | 144:ef7eb2e8f9f7 | 813 | |
<> | 144:ef7eb2e8f9f7 | 814 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 815 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 816 | } |
<> | 144:ef7eb2e8f9f7 | 817 | |
<> | 144:ef7eb2e8f9f7 | 818 | /** |
<> | 144:ef7eb2e8f9f7 | 819 | * @brief Stop ADC conversion of regular group, disable ADC peripheral. |
Anna Bridge |
180:96ed750bd169 | 820 | * @param hadc ADC handle |
<> | 144:ef7eb2e8f9f7 | 821 | * @retval HAL status. |
<> | 144:ef7eb2e8f9f7 | 822 | */ |
<> | 144:ef7eb2e8f9f7 | 823 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 824 | { |
<> | 144:ef7eb2e8f9f7 | 825 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 826 | |
<> | 144:ef7eb2e8f9f7 | 827 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 828 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 829 | |
<> | 144:ef7eb2e8f9f7 | 830 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 831 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 832 | |
<> | 144:ef7eb2e8f9f7 | 833 | /* 1. Stop potential conversion on going, on regular group */ |
<> | 144:ef7eb2e8f9f7 | 834 | tmp_hal_status = ADC_ConversionStop(hadc); |
<> | 144:ef7eb2e8f9f7 | 835 | |
<> | 144:ef7eb2e8f9f7 | 836 | /* Disable ADC peripheral if conversions are effectively stopped */ |
<> | 144:ef7eb2e8f9f7 | 837 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 838 | { |
<> | 144:ef7eb2e8f9f7 | 839 | /* 2. Disable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 840 | tmp_hal_status = ADC_Disable(hadc); |
<> | 144:ef7eb2e8f9f7 | 841 | |
<> | 144:ef7eb2e8f9f7 | 842 | /* Check if ADC is effectively disabled */ |
<> | 144:ef7eb2e8f9f7 | 843 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 844 | { |
<> | 144:ef7eb2e8f9f7 | 845 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 846 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 847 | HAL_ADC_STATE_REG_BUSY, |
<> | 144:ef7eb2e8f9f7 | 848 | HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 849 | } |
<> | 144:ef7eb2e8f9f7 | 850 | } |
<> | 144:ef7eb2e8f9f7 | 851 | |
<> | 144:ef7eb2e8f9f7 | 852 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 853 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 854 | |
<> | 144:ef7eb2e8f9f7 | 855 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 856 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 857 | } |
<> | 144:ef7eb2e8f9f7 | 858 | |
<> | 144:ef7eb2e8f9f7 | 859 | /** |
<> | 144:ef7eb2e8f9f7 | 860 | * @brief Wait for regular group conversion to be completed. |
<> | 144:ef7eb2e8f9f7 | 861 | * @note ADC conversion flags EOS (end of sequence) and EOC (end of |
<> | 144:ef7eb2e8f9f7 | 862 | * conversion) are cleared by this function, with an exception: |
<> | 144:ef7eb2e8f9f7 | 863 | * if low power feature "LowPowerAutoWait" is enabled, flags are |
<> | 144:ef7eb2e8f9f7 | 864 | * not cleared to not interfere with this feature until data register |
<> | 144:ef7eb2e8f9f7 | 865 | * is read using function HAL_ADC_GetValue(). |
<> | 144:ef7eb2e8f9f7 | 866 | * @note This function cannot be used in a particular setup: ADC configured |
<> | 144:ef7eb2e8f9f7 | 867 | * in DMA mode and polling for end of each conversion (ADC init |
<> | 144:ef7eb2e8f9f7 | 868 | * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). |
<> | 144:ef7eb2e8f9f7 | 869 | * In this case, DMA resets the flag EOC and polling cannot be |
<> | 144:ef7eb2e8f9f7 | 870 | * performed on each conversion. Nevertheless, polling can still |
<> | 144:ef7eb2e8f9f7 | 871 | * be performed on the complete sequence (ADC init |
<> | 144:ef7eb2e8f9f7 | 872 | * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). |
Anna Bridge |
180:96ed750bd169 | 873 | * @param hadc ADC handle |
Anna Bridge |
180:96ed750bd169 | 874 | * @param Timeout Timeout value in millisecond. |
<> | 144:ef7eb2e8f9f7 | 875 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 876 | */ |
<> | 144:ef7eb2e8f9f7 | 877 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 878 | { |
<> | 144:ef7eb2e8f9f7 | 879 | uint32_t tickstart; |
<> | 144:ef7eb2e8f9f7 | 880 | uint32_t tmp_Flag_EOC; |
<> | 144:ef7eb2e8f9f7 | 881 | |
<> | 144:ef7eb2e8f9f7 | 882 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 883 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 884 | |
<> | 144:ef7eb2e8f9f7 | 885 | /* If end of conversion selected to end of sequence */ |
<> | 144:ef7eb2e8f9f7 | 886 | if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) |
<> | 144:ef7eb2e8f9f7 | 887 | { |
<> | 144:ef7eb2e8f9f7 | 888 | tmp_Flag_EOC = ADC_FLAG_EOS; |
<> | 144:ef7eb2e8f9f7 | 889 | } |
<> | 144:ef7eb2e8f9f7 | 890 | /* If end of conversion selected to end of each conversion */ |
<> | 144:ef7eb2e8f9f7 | 891 | else /* ADC_EOC_SINGLE_CONV */ |
<> | 144:ef7eb2e8f9f7 | 892 | { |
<> | 144:ef7eb2e8f9f7 | 893 | /* Verification that ADC configuration is compliant with polling for */ |
<> | 144:ef7eb2e8f9f7 | 894 | /* each conversion: */ |
<> | 144:ef7eb2e8f9f7 | 895 | /* Particular case is ADC configured in DMA mode and ADC sequencer with */ |
<> | 144:ef7eb2e8f9f7 | 896 | /* several ranks and polling for end of each conversion. */ |
<> | 144:ef7eb2e8f9f7 | 897 | /* For code simplicity sake, this particular case is generalized to */ |
<> | 144:ef7eb2e8f9f7 | 898 | /* ADC configured in DMA mode and and polling for end of each conversion. */ |
<> | 144:ef7eb2e8f9f7 | 899 | if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN)) |
<> | 144:ef7eb2e8f9f7 | 900 | { |
<> | 144:ef7eb2e8f9f7 | 901 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 902 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
<> | 144:ef7eb2e8f9f7 | 903 | |
<> | 144:ef7eb2e8f9f7 | 904 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 905 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 906 | |
<> | 144:ef7eb2e8f9f7 | 907 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 908 | } |
<> | 144:ef7eb2e8f9f7 | 909 | else |
<> | 144:ef7eb2e8f9f7 | 910 | { |
<> | 144:ef7eb2e8f9f7 | 911 | tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS); |
<> | 144:ef7eb2e8f9f7 | 912 | } |
<> | 144:ef7eb2e8f9f7 | 913 | } |
<> | 144:ef7eb2e8f9f7 | 914 | |
<> | 144:ef7eb2e8f9f7 | 915 | /* Get tick count */ |
<> | 144:ef7eb2e8f9f7 | 916 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 917 | |
<> | 144:ef7eb2e8f9f7 | 918 | /* Wait until End of Conversion flag is raised */ |
<> | 144:ef7eb2e8f9f7 | 919 | while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) |
<> | 144:ef7eb2e8f9f7 | 920 | { |
<> | 144:ef7eb2e8f9f7 | 921 | /* Check if timeout is disabled (set to infinite wait) */ |
<> | 144:ef7eb2e8f9f7 | 922 | if(Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 923 | { |
<> | 144:ef7eb2e8f9f7 | 924 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 925 | { |
<> | 144:ef7eb2e8f9f7 | 926 | /* Update ADC state machine to timeout */ |
<> | 144:ef7eb2e8f9f7 | 927 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
<> | 144:ef7eb2e8f9f7 | 928 | |
<> | 144:ef7eb2e8f9f7 | 929 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 930 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 931 | |
<> | 144:ef7eb2e8f9f7 | 932 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 933 | } |
<> | 144:ef7eb2e8f9f7 | 934 | } |
<> | 144:ef7eb2e8f9f7 | 935 | } |
<> | 144:ef7eb2e8f9f7 | 936 | |
<> | 144:ef7eb2e8f9f7 | 937 | /* Update ADC state machine */ |
<> | 144:ef7eb2e8f9f7 | 938 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
<> | 144:ef7eb2e8f9f7 | 939 | |
<> | 144:ef7eb2e8f9f7 | 940 | /* Determine whether any further conversion upcoming on group regular */ |
<> | 144:ef7eb2e8f9f7 | 941 | /* by external trigger, continuous mode or scan sequence on going. */ |
<> | 144:ef7eb2e8f9f7 | 942 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
<> | 144:ef7eb2e8f9f7 | 943 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
<> | 144:ef7eb2e8f9f7 | 944 | { |
<> | 144:ef7eb2e8f9f7 | 945 | /* If End of Sequence is reached, disable interrupts */ |
<> | 144:ef7eb2e8f9f7 | 946 | if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) |
<> | 144:ef7eb2e8f9f7 | 947 | { |
<> | 144:ef7eb2e8f9f7 | 948 | /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ |
<> | 144:ef7eb2e8f9f7 | 949 | /* ADSTART==0 (no conversion on going) */ |
<> | 144:ef7eb2e8f9f7 | 950 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 951 | { |
<> | 144:ef7eb2e8f9f7 | 952 | /* Disable ADC end of single conversion interrupt on group regular */ |
<> | 144:ef7eb2e8f9f7 | 953 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
<> | 144:ef7eb2e8f9f7 | 954 | /* HAL_Start_IT(), but is not disabled here because can be used */ |
<> | 144:ef7eb2e8f9f7 | 955 | /* by overrun IRQ process below. */ |
<> | 144:ef7eb2e8f9f7 | 956 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); |
<> | 144:ef7eb2e8f9f7 | 957 | |
<> | 144:ef7eb2e8f9f7 | 958 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 959 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 960 | HAL_ADC_STATE_REG_BUSY, |
<> | 144:ef7eb2e8f9f7 | 961 | HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 962 | } |
<> | 144:ef7eb2e8f9f7 | 963 | else |
<> | 144:ef7eb2e8f9f7 | 964 | { |
<> | 144:ef7eb2e8f9f7 | 965 | /* Change ADC state to error state */ |
<> | 144:ef7eb2e8f9f7 | 966 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
<> | 144:ef7eb2e8f9f7 | 967 | |
<> | 144:ef7eb2e8f9f7 | 968 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 969 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 970 | } |
<> | 144:ef7eb2e8f9f7 | 971 | } |
<> | 144:ef7eb2e8f9f7 | 972 | } |
<> | 144:ef7eb2e8f9f7 | 973 | |
<> | 144:ef7eb2e8f9f7 | 974 | /* Clear end of conversion flag of regular group if low power feature */ |
<> | 144:ef7eb2e8f9f7 | 975 | /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ |
<> | 144:ef7eb2e8f9f7 | 976 | /* until data register is read using function HAL_ADC_GetValue(). */ |
<> | 144:ef7eb2e8f9f7 | 977 | if (hadc->Init.LowPowerAutoWait == DISABLE) |
<> | 144:ef7eb2e8f9f7 | 978 | { |
<> | 144:ef7eb2e8f9f7 | 979 | /* Clear regular group conversion flag */ |
<> | 144:ef7eb2e8f9f7 | 980 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); |
<> | 144:ef7eb2e8f9f7 | 981 | } |
<> | 144:ef7eb2e8f9f7 | 982 | |
<> | 144:ef7eb2e8f9f7 | 983 | /* Return ADC state */ |
<> | 144:ef7eb2e8f9f7 | 984 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 985 | } |
<> | 144:ef7eb2e8f9f7 | 986 | |
<> | 144:ef7eb2e8f9f7 | 987 | /** |
<> | 144:ef7eb2e8f9f7 | 988 | * @brief Poll for conversion event. |
Anna Bridge |
180:96ed750bd169 | 989 | * @param hadc ADC handle |
Anna Bridge |
180:96ed750bd169 | 990 | * @param EventType the ADC event type. |
<> | 144:ef7eb2e8f9f7 | 991 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 992 | * @arg ADC_AWD_EVENT: ADC Analog watchdog event |
<> | 144:ef7eb2e8f9f7 | 993 | * @arg ADC_OVR_EVENT: ADC Overrun event |
Anna Bridge |
180:96ed750bd169 | 994 | * @param Timeout Timeout value in millisecond. |
<> | 144:ef7eb2e8f9f7 | 995 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 996 | */ |
<> | 144:ef7eb2e8f9f7 | 997 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 998 | { |
<> | 144:ef7eb2e8f9f7 | 999 | uint32_t tickstart=0; |
<> | 144:ef7eb2e8f9f7 | 1000 | |
<> | 144:ef7eb2e8f9f7 | 1001 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1002 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1003 | assert_param(IS_ADC_EVENT_TYPE(EventType)); |
<> | 144:ef7eb2e8f9f7 | 1004 | |
<> | 144:ef7eb2e8f9f7 | 1005 | /* Get tick count */ |
<> | 144:ef7eb2e8f9f7 | 1006 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 1007 | |
<> | 144:ef7eb2e8f9f7 | 1008 | /* Check selected event flag */ |
<> | 144:ef7eb2e8f9f7 | 1009 | while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1010 | { |
<> | 144:ef7eb2e8f9f7 | 1011 | /* Check if timeout is disabled (set to infinite wait) */ |
<> | 144:ef7eb2e8f9f7 | 1012 | if(Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 1013 | { |
<> | 156:95d6b41a828b | 1014 | if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 1015 | { |
<> | 144:ef7eb2e8f9f7 | 1016 | /* Update ADC state machine to timeout */ |
<> | 144:ef7eb2e8f9f7 | 1017 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
<> | 144:ef7eb2e8f9f7 | 1018 | |
<> | 144:ef7eb2e8f9f7 | 1019 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1020 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1021 | |
<> | 144:ef7eb2e8f9f7 | 1022 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1023 | } |
<> | 144:ef7eb2e8f9f7 | 1024 | } |
<> | 144:ef7eb2e8f9f7 | 1025 | } |
<> | 144:ef7eb2e8f9f7 | 1026 | |
<> | 144:ef7eb2e8f9f7 | 1027 | switch(EventType) |
<> | 144:ef7eb2e8f9f7 | 1028 | { |
<> | 144:ef7eb2e8f9f7 | 1029 | /* Analog watchdog (level out of window) event */ |
<> | 144:ef7eb2e8f9f7 | 1030 | case ADC_AWD_EVENT: |
<> | 144:ef7eb2e8f9f7 | 1031 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1032 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
<> | 144:ef7eb2e8f9f7 | 1033 | |
<> | 144:ef7eb2e8f9f7 | 1034 | /* Clear ADC analog watchdog flag */ |
<> | 144:ef7eb2e8f9f7 | 1035 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
<> | 144:ef7eb2e8f9f7 | 1036 | break; |
<> | 144:ef7eb2e8f9f7 | 1037 | |
<> | 144:ef7eb2e8f9f7 | 1038 | /* Overrun event */ |
<> | 144:ef7eb2e8f9f7 | 1039 | default: /* Case ADC_OVR_EVENT */ |
<> | 144:ef7eb2e8f9f7 | 1040 | /* If overrun is set to overwrite previous data, overrun event is not */ |
<> | 144:ef7eb2e8f9f7 | 1041 | /* considered as an error. */ |
<> | 144:ef7eb2e8f9f7 | 1042 | /* (cf ref manual "Managing conversions without using the DMA and without */ |
<> | 144:ef7eb2e8f9f7 | 1043 | /* overrun ") */ |
<> | 144:ef7eb2e8f9f7 | 1044 | if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) |
<> | 144:ef7eb2e8f9f7 | 1045 | { |
<> | 144:ef7eb2e8f9f7 | 1046 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1047 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); |
<> | 144:ef7eb2e8f9f7 | 1048 | |
<> | 144:ef7eb2e8f9f7 | 1049 | /* Set ADC error code to overrun */ |
<> | 144:ef7eb2e8f9f7 | 1050 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); |
<> | 144:ef7eb2e8f9f7 | 1051 | } |
<> | 144:ef7eb2e8f9f7 | 1052 | |
<> | 144:ef7eb2e8f9f7 | 1053 | /* Clear ADC Overrun flag */ |
<> | 144:ef7eb2e8f9f7 | 1054 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
<> | 144:ef7eb2e8f9f7 | 1055 | break; |
<> | 144:ef7eb2e8f9f7 | 1056 | } |
<> | 144:ef7eb2e8f9f7 | 1057 | |
<> | 144:ef7eb2e8f9f7 | 1058 | /* Return ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1059 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1060 | } |
<> | 144:ef7eb2e8f9f7 | 1061 | |
<> | 144:ef7eb2e8f9f7 | 1062 | /** |
<> | 144:ef7eb2e8f9f7 | 1063 | * @brief Enables ADC, starts conversion of regular group with interruption. |
<> | 144:ef7eb2e8f9f7 | 1064 | * Interruptions enabled in this function: |
<> | 144:ef7eb2e8f9f7 | 1065 | * - EOC (end of conversion of regular group) or EOS (end of |
<> | 144:ef7eb2e8f9f7 | 1066 | * sequence of regular group) depending on ADC initialization |
<> | 144:ef7eb2e8f9f7 | 1067 | * parameter "EOCSelection" |
<> | 144:ef7eb2e8f9f7 | 1068 | * - overrun (if available) |
<> | 144:ef7eb2e8f9f7 | 1069 | * Each of these interruptions has its dedicated callback function. |
Anna Bridge |
180:96ed750bd169 | 1070 | * @param hadc ADC handle |
<> | 144:ef7eb2e8f9f7 | 1071 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1072 | */ |
<> | 144:ef7eb2e8f9f7 | 1073 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1074 | { |
<> | 144:ef7eb2e8f9f7 | 1075 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1076 | |
<> | 144:ef7eb2e8f9f7 | 1077 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1078 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1079 | |
<> | 144:ef7eb2e8f9f7 | 1080 | /* Perform ADC enable and conversion start if no conversion is on going */ |
<> | 144:ef7eb2e8f9f7 | 1081 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1082 | { |
<> | 144:ef7eb2e8f9f7 | 1083 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1084 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1085 | |
<> | 144:ef7eb2e8f9f7 | 1086 | /* Enable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1087 | /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ |
<> | 144:ef7eb2e8f9f7 | 1088 | /* performed automatically by hardware. */ |
<> | 144:ef7eb2e8f9f7 | 1089 | if (hadc->Init.LowPowerAutoPowerOff != ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1090 | { |
<> | 144:ef7eb2e8f9f7 | 1091 | tmp_hal_status = ADC_Enable(hadc); |
<> | 144:ef7eb2e8f9f7 | 1092 | } |
<> | 144:ef7eb2e8f9f7 | 1093 | |
<> | 144:ef7eb2e8f9f7 | 1094 | /* Start conversion if ADC is effectively enabled */ |
<> | 144:ef7eb2e8f9f7 | 1095 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1096 | { |
<> | 144:ef7eb2e8f9f7 | 1097 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1098 | /* - Clear state bitfield related to regular group conversion results */ |
<> | 144:ef7eb2e8f9f7 | 1099 | /* - Set state bitfield related to regular operation */ |
<> | 144:ef7eb2e8f9f7 | 1100 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 1101 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, |
<> | 144:ef7eb2e8f9f7 | 1102 | HAL_ADC_STATE_REG_BUSY); |
<> | 144:ef7eb2e8f9f7 | 1103 | |
<> | 144:ef7eb2e8f9f7 | 1104 | /* Reset ADC all error code fields */ |
<> | 144:ef7eb2e8f9f7 | 1105 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 1106 | |
<> | 144:ef7eb2e8f9f7 | 1107 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1108 | /* Unlock before starting ADC conversions: in case of potential */ |
<> | 144:ef7eb2e8f9f7 | 1109 | /* interruption, to let the process to ADC IRQ Handler. */ |
<> | 144:ef7eb2e8f9f7 | 1110 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1111 | |
<> | 144:ef7eb2e8f9f7 | 1112 | /* Clear regular group conversion flag and overrun flag */ |
<> | 144:ef7eb2e8f9f7 | 1113 | /* (To ensure of no unknown state from potential previous ADC */ |
<> | 144:ef7eb2e8f9f7 | 1114 | /* operations) */ |
<> | 144:ef7eb2e8f9f7 | 1115 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); |
<> | 144:ef7eb2e8f9f7 | 1116 | |
<> | 144:ef7eb2e8f9f7 | 1117 | /* Enable ADC end of conversion interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1118 | /* Enable ADC overrun interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1119 | switch(hadc->Init.EOCSelection) |
<> | 144:ef7eb2e8f9f7 | 1120 | { |
<> | 144:ef7eb2e8f9f7 | 1121 | case ADC_EOC_SEQ_CONV: |
<> | 144:ef7eb2e8f9f7 | 1122 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
<> | 144:ef7eb2e8f9f7 | 1123 | __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_OVR)); |
<> | 144:ef7eb2e8f9f7 | 1124 | break; |
<> | 144:ef7eb2e8f9f7 | 1125 | /* case ADC_EOC_SINGLE_CONV */ |
<> | 144:ef7eb2e8f9f7 | 1126 | default: |
<> | 144:ef7eb2e8f9f7 | 1127 | __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); |
<> | 144:ef7eb2e8f9f7 | 1128 | break; |
<> | 144:ef7eb2e8f9f7 | 1129 | } |
<> | 144:ef7eb2e8f9f7 | 1130 | |
<> | 144:ef7eb2e8f9f7 | 1131 | /* Enable conversion of regular group. */ |
<> | 144:ef7eb2e8f9f7 | 1132 | /* If software start has been selected, conversion starts immediately. */ |
<> | 144:ef7eb2e8f9f7 | 1133 | /* If external trigger has been selected, conversion will start at next */ |
<> | 144:ef7eb2e8f9f7 | 1134 | /* trigger event. */ |
<> | 144:ef7eb2e8f9f7 | 1135 | hadc->Instance->CR |= ADC_CR_ADSTART; |
<> | 144:ef7eb2e8f9f7 | 1136 | } |
<> | 144:ef7eb2e8f9f7 | 1137 | } |
<> | 144:ef7eb2e8f9f7 | 1138 | else |
<> | 144:ef7eb2e8f9f7 | 1139 | { |
<> | 144:ef7eb2e8f9f7 | 1140 | tmp_hal_status = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1141 | } |
<> | 144:ef7eb2e8f9f7 | 1142 | |
<> | 144:ef7eb2e8f9f7 | 1143 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1144 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 1145 | } |
<> | 144:ef7eb2e8f9f7 | 1146 | |
<> | 144:ef7eb2e8f9f7 | 1147 | |
<> | 144:ef7eb2e8f9f7 | 1148 | /** |
<> | 144:ef7eb2e8f9f7 | 1149 | * @brief Stop ADC conversion of regular group, disable interruption of |
<> | 144:ef7eb2e8f9f7 | 1150 | * end-of-conversion, disable ADC peripheral. |
Anna Bridge |
180:96ed750bd169 | 1151 | * @param hadc ADC handle |
<> | 144:ef7eb2e8f9f7 | 1152 | * @retval HAL status. |
<> | 144:ef7eb2e8f9f7 | 1153 | */ |
<> | 144:ef7eb2e8f9f7 | 1154 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1155 | { |
<> | 144:ef7eb2e8f9f7 | 1156 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1157 | |
<> | 144:ef7eb2e8f9f7 | 1158 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1159 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1160 | |
<> | 144:ef7eb2e8f9f7 | 1161 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1162 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1163 | |
<> | 144:ef7eb2e8f9f7 | 1164 | /* 1. Stop potential conversion on going, on regular group */ |
<> | 144:ef7eb2e8f9f7 | 1165 | tmp_hal_status = ADC_ConversionStop(hadc); |
<> | 144:ef7eb2e8f9f7 | 1166 | |
<> | 144:ef7eb2e8f9f7 | 1167 | /* Disable ADC peripheral if conversions are effectively stopped */ |
<> | 144:ef7eb2e8f9f7 | 1168 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1169 | { |
<> | 144:ef7eb2e8f9f7 | 1170 | /* Disable ADC end of conversion interrupt for regular group */ |
<> | 144:ef7eb2e8f9f7 | 1171 | /* Disable ADC overrun interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1172 | __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); |
<> | 144:ef7eb2e8f9f7 | 1173 | |
<> | 144:ef7eb2e8f9f7 | 1174 | /* 2. Disable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1175 | tmp_hal_status = ADC_Disable(hadc); |
<> | 144:ef7eb2e8f9f7 | 1176 | |
<> | 144:ef7eb2e8f9f7 | 1177 | /* Check if ADC is effectively disabled */ |
<> | 144:ef7eb2e8f9f7 | 1178 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1179 | { |
<> | 144:ef7eb2e8f9f7 | 1180 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1181 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 1182 | HAL_ADC_STATE_REG_BUSY, |
<> | 144:ef7eb2e8f9f7 | 1183 | HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 1184 | } |
<> | 144:ef7eb2e8f9f7 | 1185 | } |
<> | 144:ef7eb2e8f9f7 | 1186 | |
<> | 144:ef7eb2e8f9f7 | 1187 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1188 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1189 | |
<> | 144:ef7eb2e8f9f7 | 1190 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1191 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 1192 | } |
<> | 144:ef7eb2e8f9f7 | 1193 | |
<> | 144:ef7eb2e8f9f7 | 1194 | /** |
<> | 144:ef7eb2e8f9f7 | 1195 | * @brief Enables ADC, starts conversion of regular group and transfers result |
<> | 144:ef7eb2e8f9f7 | 1196 | * through DMA. |
<> | 144:ef7eb2e8f9f7 | 1197 | * Interruptions enabled in this function: |
<> | 144:ef7eb2e8f9f7 | 1198 | * - DMA transfer complete |
<> | 144:ef7eb2e8f9f7 | 1199 | * - DMA half transfer |
<> | 144:ef7eb2e8f9f7 | 1200 | * - overrun |
<> | 144:ef7eb2e8f9f7 | 1201 | * Each of these interruptions has its dedicated callback function. |
Anna Bridge |
180:96ed750bd169 | 1202 | * @param hadc ADC handle |
Anna Bridge |
180:96ed750bd169 | 1203 | * @param pData The destination Buffer address. |
Anna Bridge |
180:96ed750bd169 | 1204 | * @param Length The length of data to be transferred from ADC peripheral to memory. |
<> | 144:ef7eb2e8f9f7 | 1205 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1206 | */ |
<> | 144:ef7eb2e8f9f7 | 1207 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) |
<> | 144:ef7eb2e8f9f7 | 1208 | { |
<> | 144:ef7eb2e8f9f7 | 1209 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1210 | |
<> | 144:ef7eb2e8f9f7 | 1211 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1212 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1213 | |
<> | 144:ef7eb2e8f9f7 | 1214 | /* Perform ADC enable and conversion start if no conversion is on going */ |
<> | 144:ef7eb2e8f9f7 | 1215 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1216 | { |
<> | 144:ef7eb2e8f9f7 | 1217 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1218 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1219 | |
<> | 144:ef7eb2e8f9f7 | 1220 | /* Enable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1221 | /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ |
<> | 144:ef7eb2e8f9f7 | 1222 | /* performed automatically by hardware. */ |
<> | 144:ef7eb2e8f9f7 | 1223 | if (hadc->Init.LowPowerAutoPowerOff != ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1224 | { |
<> | 144:ef7eb2e8f9f7 | 1225 | tmp_hal_status = ADC_Enable(hadc); |
<> | 144:ef7eb2e8f9f7 | 1226 | } |
<> | 144:ef7eb2e8f9f7 | 1227 | |
<> | 144:ef7eb2e8f9f7 | 1228 | /* Start conversion if ADC is effectively enabled */ |
<> | 144:ef7eb2e8f9f7 | 1229 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1230 | { |
<> | 144:ef7eb2e8f9f7 | 1231 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1232 | /* - Clear state bitfield related to regular group conversion results */ |
<> | 144:ef7eb2e8f9f7 | 1233 | /* - Set state bitfield related to regular operation */ |
<> | 144:ef7eb2e8f9f7 | 1234 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 1235 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, |
<> | 144:ef7eb2e8f9f7 | 1236 | HAL_ADC_STATE_REG_BUSY); |
<> | 144:ef7eb2e8f9f7 | 1237 | |
<> | 144:ef7eb2e8f9f7 | 1238 | /* Reset ADC all error code fields */ |
<> | 144:ef7eb2e8f9f7 | 1239 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 1240 | |
<> | 144:ef7eb2e8f9f7 | 1241 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1242 | /* Unlock before starting ADC conversions: in case of potential */ |
<> | 144:ef7eb2e8f9f7 | 1243 | /* interruption, to let the process to ADC IRQ Handler. */ |
<> | 144:ef7eb2e8f9f7 | 1244 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1245 | |
<> | 144:ef7eb2e8f9f7 | 1246 | /* Set the DMA transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1247 | hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; |
<> | 144:ef7eb2e8f9f7 | 1248 | |
<> | 144:ef7eb2e8f9f7 | 1249 | /* Set the DMA half transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1250 | hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; |
<> | 144:ef7eb2e8f9f7 | 1251 | |
<> | 144:ef7eb2e8f9f7 | 1252 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 1253 | hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; |
<> | 144:ef7eb2e8f9f7 | 1254 | |
<> | 144:ef7eb2e8f9f7 | 1255 | |
<> | 144:ef7eb2e8f9f7 | 1256 | /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ |
<> | 144:ef7eb2e8f9f7 | 1257 | /* start (in case of SW start): */ |
<> | 144:ef7eb2e8f9f7 | 1258 | |
<> | 144:ef7eb2e8f9f7 | 1259 | /* Clear regular group conversion flag and overrun flag */ |
<> | 144:ef7eb2e8f9f7 | 1260 | /* (To ensure of no unknown state from potential previous ADC */ |
<> | 144:ef7eb2e8f9f7 | 1261 | /* operations) */ |
<> | 144:ef7eb2e8f9f7 | 1262 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); |
<> | 144:ef7eb2e8f9f7 | 1263 | |
<> | 144:ef7eb2e8f9f7 | 1264 | /* Enable ADC overrun interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1265 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); |
<> | 144:ef7eb2e8f9f7 | 1266 | |
<> | 144:ef7eb2e8f9f7 | 1267 | /* Enable ADC DMA mode */ |
<> | 144:ef7eb2e8f9f7 | 1268 | hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN; |
<> | 144:ef7eb2e8f9f7 | 1269 | |
<> | 144:ef7eb2e8f9f7 | 1270 | /* Start the DMA channel */ |
<> | 144:ef7eb2e8f9f7 | 1271 | HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); |
<> | 144:ef7eb2e8f9f7 | 1272 | |
<> | 144:ef7eb2e8f9f7 | 1273 | /* Enable conversion of regular group. */ |
<> | 144:ef7eb2e8f9f7 | 1274 | /* If software start has been selected, conversion starts immediately. */ |
<> | 144:ef7eb2e8f9f7 | 1275 | /* If external trigger has been selected, conversion will start at next */ |
<> | 144:ef7eb2e8f9f7 | 1276 | /* trigger event. */ |
<> | 144:ef7eb2e8f9f7 | 1277 | hadc->Instance->CR |= ADC_CR_ADSTART; |
<> | 144:ef7eb2e8f9f7 | 1278 | } |
<> | 144:ef7eb2e8f9f7 | 1279 | } |
<> | 144:ef7eb2e8f9f7 | 1280 | else |
<> | 144:ef7eb2e8f9f7 | 1281 | { |
<> | 144:ef7eb2e8f9f7 | 1282 | tmp_hal_status = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1283 | } |
<> | 144:ef7eb2e8f9f7 | 1284 | |
<> | 144:ef7eb2e8f9f7 | 1285 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1286 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 1287 | } |
<> | 144:ef7eb2e8f9f7 | 1288 | |
<> | 144:ef7eb2e8f9f7 | 1289 | /** |
<> | 144:ef7eb2e8f9f7 | 1290 | * @brief Stop ADC conversion of regular group, disable ADC DMA transfer, disable |
<> | 144:ef7eb2e8f9f7 | 1291 | * ADC peripheral. |
<> | 144:ef7eb2e8f9f7 | 1292 | * Each of these interruptions has its dedicated callback function. |
Anna Bridge |
180:96ed750bd169 | 1293 | * @param hadc ADC handle |
<> | 144:ef7eb2e8f9f7 | 1294 | * @retval HAL status. |
<> | 144:ef7eb2e8f9f7 | 1295 | */ |
<> | 144:ef7eb2e8f9f7 | 1296 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1297 | { |
<> | 144:ef7eb2e8f9f7 | 1298 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1299 | |
<> | 144:ef7eb2e8f9f7 | 1300 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1301 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1302 | |
<> | 144:ef7eb2e8f9f7 | 1303 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1304 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1305 | |
<> | 144:ef7eb2e8f9f7 | 1306 | /* 1. Stop potential conversion on going, on regular group */ |
<> | 144:ef7eb2e8f9f7 | 1307 | tmp_hal_status = ADC_ConversionStop(hadc); |
<> | 144:ef7eb2e8f9f7 | 1308 | |
<> | 144:ef7eb2e8f9f7 | 1309 | /* Disable ADC peripheral if conversions are effectively stopped */ |
<> | 144:ef7eb2e8f9f7 | 1310 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1311 | { |
<> | 144:ef7eb2e8f9f7 | 1312 | /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ |
<> | 144:ef7eb2e8f9f7 | 1313 | hadc->Instance->CFGR1 &= ~ADC_CFGR1_DMAEN; |
<> | 144:ef7eb2e8f9f7 | 1314 | |
<> | 144:ef7eb2e8f9f7 | 1315 | /* Disable the DMA channel (in case of DMA in circular mode or stop while */ |
<> | 144:ef7eb2e8f9f7 | 1316 | /* while DMA transfer is on going) */ |
<> | 144:ef7eb2e8f9f7 | 1317 | tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); |
<> | 144:ef7eb2e8f9f7 | 1318 | |
<> | 144:ef7eb2e8f9f7 | 1319 | /* Check if DMA channel effectively disabled */ |
<> | 144:ef7eb2e8f9f7 | 1320 | if (tmp_hal_status != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1321 | { |
<> | 144:ef7eb2e8f9f7 | 1322 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 1323 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); |
<> | 144:ef7eb2e8f9f7 | 1324 | } |
<> | 144:ef7eb2e8f9f7 | 1325 | |
<> | 144:ef7eb2e8f9f7 | 1326 | /* Disable ADC overrun interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1327 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); |
<> | 144:ef7eb2e8f9f7 | 1328 | |
<> | 144:ef7eb2e8f9f7 | 1329 | /* 2. Disable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1330 | /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep */ |
<> | 144:ef7eb2e8f9f7 | 1331 | /* in memory a potential failing status. */ |
<> | 144:ef7eb2e8f9f7 | 1332 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1333 | { |
<> | 144:ef7eb2e8f9f7 | 1334 | tmp_hal_status = ADC_Disable(hadc); |
<> | 144:ef7eb2e8f9f7 | 1335 | } |
<> | 144:ef7eb2e8f9f7 | 1336 | else |
<> | 144:ef7eb2e8f9f7 | 1337 | { |
<> | 144:ef7eb2e8f9f7 | 1338 | ADC_Disable(hadc); |
<> | 144:ef7eb2e8f9f7 | 1339 | } |
<> | 144:ef7eb2e8f9f7 | 1340 | |
<> | 144:ef7eb2e8f9f7 | 1341 | /* Check if ADC is effectively disabled */ |
<> | 144:ef7eb2e8f9f7 | 1342 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1343 | { |
<> | 144:ef7eb2e8f9f7 | 1344 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1345 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 1346 | HAL_ADC_STATE_REG_BUSY, |
<> | 144:ef7eb2e8f9f7 | 1347 | HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 1348 | } |
<> | 144:ef7eb2e8f9f7 | 1349 | |
<> | 144:ef7eb2e8f9f7 | 1350 | } |
<> | 144:ef7eb2e8f9f7 | 1351 | |
<> | 144:ef7eb2e8f9f7 | 1352 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1353 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1354 | |
<> | 144:ef7eb2e8f9f7 | 1355 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1356 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 1357 | } |
<> | 144:ef7eb2e8f9f7 | 1358 | |
<> | 144:ef7eb2e8f9f7 | 1359 | /** |
<> | 144:ef7eb2e8f9f7 | 1360 | * @brief Get ADC regular group conversion result. |
<> | 144:ef7eb2e8f9f7 | 1361 | * @note Reading register DR automatically clears ADC flag EOC |
<> | 144:ef7eb2e8f9f7 | 1362 | * (ADC group regular end of unitary conversion). |
<> | 144:ef7eb2e8f9f7 | 1363 | * @note This function does not clear ADC flag EOS |
<> | 144:ef7eb2e8f9f7 | 1364 | * (ADC group regular end of sequence conversion). |
<> | 144:ef7eb2e8f9f7 | 1365 | * Occurrence of flag EOS rising: |
<> | 144:ef7eb2e8f9f7 | 1366 | * - If sequencer is composed of 1 rank, flag EOS is equivalent |
<> | 144:ef7eb2e8f9f7 | 1367 | * to flag EOC. |
<> | 144:ef7eb2e8f9f7 | 1368 | * - If sequencer is composed of several ranks, during the scan |
<> | 144:ef7eb2e8f9f7 | 1369 | * sequence flag EOC only is raised, at the end of the scan sequence |
<> | 144:ef7eb2e8f9f7 | 1370 | * both flags EOC and EOS are raised. |
<> | 144:ef7eb2e8f9f7 | 1371 | * To clear this flag, either use function: |
<> | 144:ef7eb2e8f9f7 | 1372 | * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming |
<> | 144:ef7eb2e8f9f7 | 1373 | * model polling: @ref HAL_ADC_PollForConversion() |
<> | 144:ef7eb2e8f9f7 | 1374 | * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). |
Anna Bridge |
180:96ed750bd169 | 1375 | * @param hadc ADC handle |
<> | 144:ef7eb2e8f9f7 | 1376 | * @retval ADC group regular conversion data |
<> | 144:ef7eb2e8f9f7 | 1377 | */ |
<> | 144:ef7eb2e8f9f7 | 1378 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1379 | { |
<> | 144:ef7eb2e8f9f7 | 1380 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1381 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1382 | |
<> | 144:ef7eb2e8f9f7 | 1383 | /* Note: EOC flag is not cleared here by software because automatically */ |
<> | 144:ef7eb2e8f9f7 | 1384 | /* cleared by hardware when reading register DR. */ |
<> | 144:ef7eb2e8f9f7 | 1385 | |
<> | 144:ef7eb2e8f9f7 | 1386 | /* Return ADC converted value */ |
<> | 144:ef7eb2e8f9f7 | 1387 | return hadc->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 1388 | } |
<> | 144:ef7eb2e8f9f7 | 1389 | |
<> | 144:ef7eb2e8f9f7 | 1390 | /** |
<> | 144:ef7eb2e8f9f7 | 1391 | * @brief Handles ADC interrupt request. |
Anna Bridge |
180:96ed750bd169 | 1392 | * @param hadc ADC handle |
<> | 144:ef7eb2e8f9f7 | 1393 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1394 | */ |
<> | 144:ef7eb2e8f9f7 | 1395 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1396 | { |
<> | 144:ef7eb2e8f9f7 | 1397 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1398 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1399 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
<> | 144:ef7eb2e8f9f7 | 1400 | assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); |
<> | 144:ef7eb2e8f9f7 | 1401 | |
<> | 144:ef7eb2e8f9f7 | 1402 | /* ========== Check End of Conversion flag for regular group ========== */ |
<> | 144:ef7eb2e8f9f7 | 1403 | if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) || |
<> | 144:ef7eb2e8f9f7 | 1404 | (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) ) |
<> | 144:ef7eb2e8f9f7 | 1405 | { |
<> | 144:ef7eb2e8f9f7 | 1406 | /* Update state machine on conversion status if not in error state */ |
<> | 144:ef7eb2e8f9f7 | 1407 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
<> | 144:ef7eb2e8f9f7 | 1408 | { |
<> | 144:ef7eb2e8f9f7 | 1409 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1410 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
<> | 144:ef7eb2e8f9f7 | 1411 | } |
<> | 144:ef7eb2e8f9f7 | 1412 | |
<> | 144:ef7eb2e8f9f7 | 1413 | /* Determine whether any further conversion upcoming on group regular */ |
<> | 144:ef7eb2e8f9f7 | 1414 | /* by external trigger, continuous mode or scan sequence on going. */ |
<> | 144:ef7eb2e8f9f7 | 1415 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
<> | 144:ef7eb2e8f9f7 | 1416 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
<> | 144:ef7eb2e8f9f7 | 1417 | { |
<> | 144:ef7eb2e8f9f7 | 1418 | /* If End of Sequence is reached, disable interrupts */ |
<> | 144:ef7eb2e8f9f7 | 1419 | if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) |
<> | 144:ef7eb2e8f9f7 | 1420 | { |
<> | 144:ef7eb2e8f9f7 | 1421 | /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ |
<> | 144:ef7eb2e8f9f7 | 1422 | /* ADSTART==0 (no conversion on going) */ |
<> | 144:ef7eb2e8f9f7 | 1423 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1424 | { |
<> | 144:ef7eb2e8f9f7 | 1425 | /* Disable ADC end of single conversion interrupt on group regular */ |
<> | 144:ef7eb2e8f9f7 | 1426 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
<> | 144:ef7eb2e8f9f7 | 1427 | /* HAL_Start_IT(), but is not disabled here because can be used */ |
<> | 144:ef7eb2e8f9f7 | 1428 | /* by overrun IRQ process below. */ |
<> | 144:ef7eb2e8f9f7 | 1429 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); |
<> | 144:ef7eb2e8f9f7 | 1430 | |
<> | 144:ef7eb2e8f9f7 | 1431 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1432 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 1433 | HAL_ADC_STATE_REG_BUSY, |
<> | 144:ef7eb2e8f9f7 | 1434 | HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 1435 | } |
<> | 144:ef7eb2e8f9f7 | 1436 | else |
<> | 144:ef7eb2e8f9f7 | 1437 | { |
<> | 144:ef7eb2e8f9f7 | 1438 | /* Change ADC state to error state */ |
<> | 144:ef7eb2e8f9f7 | 1439 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
<> | 144:ef7eb2e8f9f7 | 1440 | |
<> | 144:ef7eb2e8f9f7 | 1441 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 1442 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 1443 | } |
<> | 144:ef7eb2e8f9f7 | 1444 | } |
<> | 144:ef7eb2e8f9f7 | 1445 | } |
<> | 144:ef7eb2e8f9f7 | 1446 | |
<> | 144:ef7eb2e8f9f7 | 1447 | /* Conversion complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1448 | /* Note: into callback, to determine if conversion has been triggered */ |
<> | 144:ef7eb2e8f9f7 | 1449 | /* from EOC or EOS, possibility to use: */ |
<> | 144:ef7eb2e8f9f7 | 1450 | /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ |
<> | 144:ef7eb2e8f9f7 | 1451 | HAL_ADC_ConvCpltCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 1452 | |
<> | 144:ef7eb2e8f9f7 | 1453 | |
<> | 144:ef7eb2e8f9f7 | 1454 | /* Clear regular group conversion flag */ |
<> | 144:ef7eb2e8f9f7 | 1455 | /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ |
<> | 144:ef7eb2e8f9f7 | 1456 | /* conversion flags clear induces the release of the preserved data.*/ |
<> | 144:ef7eb2e8f9f7 | 1457 | /* Therefore, if the preserved data value is needed, it must be */ |
<> | 144:ef7eb2e8f9f7 | 1458 | /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ |
<> | 144:ef7eb2e8f9f7 | 1459 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) ); |
<> | 144:ef7eb2e8f9f7 | 1460 | } |
<> | 144:ef7eb2e8f9f7 | 1461 | |
<> | 144:ef7eb2e8f9f7 | 1462 | /* ========== Check Analog watchdog flags ========== */ |
<> | 144:ef7eb2e8f9f7 | 1463 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) |
<> | 144:ef7eb2e8f9f7 | 1464 | { |
<> | 144:ef7eb2e8f9f7 | 1465 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1466 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
<> | 144:ef7eb2e8f9f7 | 1467 | |
<> | 144:ef7eb2e8f9f7 | 1468 | /* Level out of window callback */ |
<> | 144:ef7eb2e8f9f7 | 1469 | HAL_ADC_LevelOutOfWindowCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 1470 | |
<> | 144:ef7eb2e8f9f7 | 1471 | /* Clear ADC Analog watchdog flag */ |
<> | 144:ef7eb2e8f9f7 | 1472 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
<> | 144:ef7eb2e8f9f7 | 1473 | |
<> | 144:ef7eb2e8f9f7 | 1474 | } |
<> | 144:ef7eb2e8f9f7 | 1475 | |
<> | 144:ef7eb2e8f9f7 | 1476 | |
<> | 144:ef7eb2e8f9f7 | 1477 | /* ========== Check Overrun flag ========== */ |
<> | 144:ef7eb2e8f9f7 | 1478 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR)) |
<> | 144:ef7eb2e8f9f7 | 1479 | { |
<> | 144:ef7eb2e8f9f7 | 1480 | /* If overrun is set to overwrite previous data (default setting), */ |
<> | 144:ef7eb2e8f9f7 | 1481 | /* overrun event is not considered as an error. */ |
<> | 144:ef7eb2e8f9f7 | 1482 | /* (cf ref manual "Managing conversions without using the DMA and without */ |
<> | 144:ef7eb2e8f9f7 | 1483 | /* overrun ") */ |
<> | 144:ef7eb2e8f9f7 | 1484 | /* Exception for usage with DMA overrun event always considered as an */ |
<> | 144:ef7eb2e8f9f7 | 1485 | /* error. */ |
<> | 144:ef7eb2e8f9f7 | 1486 | if ((hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) || |
<> | 144:ef7eb2e8f9f7 | 1487 | HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) ) |
<> | 144:ef7eb2e8f9f7 | 1488 | { |
<> | 144:ef7eb2e8f9f7 | 1489 | /* Set ADC error code to overrun */ |
<> | 144:ef7eb2e8f9f7 | 1490 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); |
<> | 144:ef7eb2e8f9f7 | 1491 | |
<> | 144:ef7eb2e8f9f7 | 1492 | /* Clear ADC overrun flag */ |
<> | 144:ef7eb2e8f9f7 | 1493 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
<> | 144:ef7eb2e8f9f7 | 1494 | |
<> | 144:ef7eb2e8f9f7 | 1495 | /* Error callback */ |
<> | 144:ef7eb2e8f9f7 | 1496 | HAL_ADC_ErrorCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 1497 | } |
<> | 144:ef7eb2e8f9f7 | 1498 | |
<> | 144:ef7eb2e8f9f7 | 1499 | /* Clear the Overrun flag */ |
<> | 144:ef7eb2e8f9f7 | 1500 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
<> | 144:ef7eb2e8f9f7 | 1501 | } |
<> | 144:ef7eb2e8f9f7 | 1502 | |
<> | 144:ef7eb2e8f9f7 | 1503 | } |
<> | 144:ef7eb2e8f9f7 | 1504 | |
<> | 144:ef7eb2e8f9f7 | 1505 | |
<> | 144:ef7eb2e8f9f7 | 1506 | /** |
<> | 144:ef7eb2e8f9f7 | 1507 | * @brief Conversion complete callback in non blocking mode |
Anna Bridge |
180:96ed750bd169 | 1508 | * @param hadc ADC handle |
<> | 144:ef7eb2e8f9f7 | 1509 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1510 | */ |
<> | 144:ef7eb2e8f9f7 | 1511 | __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1512 | { |
<> | 144:ef7eb2e8f9f7 | 1513 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1514 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 1515 | |
<> | 144:ef7eb2e8f9f7 | 1516 | /* NOTE : This function should not be modified. When the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1517 | function HAL_ADC_ConvCpltCallback must be implemented in the user file. |
<> | 144:ef7eb2e8f9f7 | 1518 | */ |
<> | 144:ef7eb2e8f9f7 | 1519 | } |
<> | 144:ef7eb2e8f9f7 | 1520 | |
<> | 144:ef7eb2e8f9f7 | 1521 | /** |
<> | 144:ef7eb2e8f9f7 | 1522 | * @brief Conversion DMA half-transfer callback in non blocking mode |
Anna Bridge |
180:96ed750bd169 | 1523 | * @param hadc ADC handle |
<> | 144:ef7eb2e8f9f7 | 1524 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1525 | */ |
<> | 144:ef7eb2e8f9f7 | 1526 | __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1527 | { |
<> | 144:ef7eb2e8f9f7 | 1528 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1529 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 1530 | |
<> | 144:ef7eb2e8f9f7 | 1531 | /* NOTE : This function should not be modified. When the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1532 | function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. |
<> | 144:ef7eb2e8f9f7 | 1533 | */ |
<> | 144:ef7eb2e8f9f7 | 1534 | } |
<> | 144:ef7eb2e8f9f7 | 1535 | |
<> | 144:ef7eb2e8f9f7 | 1536 | /** |
<> | 144:ef7eb2e8f9f7 | 1537 | * @brief Analog watchdog callback in non blocking mode. |
Anna Bridge |
180:96ed750bd169 | 1538 | * @param hadc ADC handle |
<> | 144:ef7eb2e8f9f7 | 1539 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1540 | */ |
<> | 144:ef7eb2e8f9f7 | 1541 | __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1542 | { |
<> | 144:ef7eb2e8f9f7 | 1543 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1544 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 1545 | |
<> | 144:ef7eb2e8f9f7 | 1546 | /* NOTE : This function should not be modified. When the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1547 | function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file. |
<> | 144:ef7eb2e8f9f7 | 1548 | */ |
<> | 144:ef7eb2e8f9f7 | 1549 | } |
<> | 144:ef7eb2e8f9f7 | 1550 | |
<> | 144:ef7eb2e8f9f7 | 1551 | /** |
<> | 144:ef7eb2e8f9f7 | 1552 | * @brief ADC error callback in non blocking mode |
<> | 144:ef7eb2e8f9f7 | 1553 | * (ADC conversion with interruption or transfer by DMA) |
Anna Bridge |
180:96ed750bd169 | 1554 | * @param hadc ADC handle |
<> | 144:ef7eb2e8f9f7 | 1555 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1556 | */ |
<> | 144:ef7eb2e8f9f7 | 1557 | __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) |
<> | 144:ef7eb2e8f9f7 | 1558 | { |
<> | 144:ef7eb2e8f9f7 | 1559 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1560 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 1561 | |
<> | 144:ef7eb2e8f9f7 | 1562 | /* NOTE : This function should not be modified. When the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1563 | function HAL_ADC_ErrorCallback must be implemented in the user file. |
<> | 144:ef7eb2e8f9f7 | 1564 | */ |
<> | 144:ef7eb2e8f9f7 | 1565 | } |
<> | 144:ef7eb2e8f9f7 | 1566 | |
<> | 144:ef7eb2e8f9f7 | 1567 | |
<> | 144:ef7eb2e8f9f7 | 1568 | /** |
<> | 144:ef7eb2e8f9f7 | 1569 | * @} |
<> | 144:ef7eb2e8f9f7 | 1570 | */ |
<> | 144:ef7eb2e8f9f7 | 1571 | |
<> | 144:ef7eb2e8f9f7 | 1572 | /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 1573 | * @brief Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 1574 | * |
<> | 144:ef7eb2e8f9f7 | 1575 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 1576 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1577 | ##### Peripheral Control functions ##### |
<> | 144:ef7eb2e8f9f7 | 1578 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1579 | [..] This section provides functions allowing to: |
<> | 144:ef7eb2e8f9f7 | 1580 | (+) Configure channels on regular group |
<> | 144:ef7eb2e8f9f7 | 1581 | (+) Configure the analog watchdog |
<> | 144:ef7eb2e8f9f7 | 1582 | |
<> | 144:ef7eb2e8f9f7 | 1583 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 1584 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1585 | */ |
<> | 144:ef7eb2e8f9f7 | 1586 | |
<> | 144:ef7eb2e8f9f7 | 1587 | /** |
<> | 144:ef7eb2e8f9f7 | 1588 | * @brief Configures the the selected channel to be linked to the regular |
<> | 144:ef7eb2e8f9f7 | 1589 | * group. |
<> | 144:ef7eb2e8f9f7 | 1590 | * @note In case of usage of internal measurement channels: |
<> | 144:ef7eb2e8f9f7 | 1591 | * VrefInt/Vbat/TempSensor. |
<> | 144:ef7eb2e8f9f7 | 1592 | * Sampling time constraints must be respected (sampling time can be |
<> | 144:ef7eb2e8f9f7 | 1593 | * adjusted in function of ADC clock frequency and sampling time |
<> | 144:ef7eb2e8f9f7 | 1594 | * setting). |
<> | 144:ef7eb2e8f9f7 | 1595 | * Refer to device datasheet for timings values, parameters TS_vrefint, |
<> | 144:ef7eb2e8f9f7 | 1596 | * TS_vbat, TS_temp (values rough order: 5us to 17us). |
<> | 144:ef7eb2e8f9f7 | 1597 | * These internal paths can be be disabled using function |
<> | 144:ef7eb2e8f9f7 | 1598 | * HAL_ADC_DeInit(). |
<> | 144:ef7eb2e8f9f7 | 1599 | * @note Possibility to update parameters on the fly: |
<> | 144:ef7eb2e8f9f7 | 1600 | * This function initializes channel into regular group, following |
<> | 144:ef7eb2e8f9f7 | 1601 | * calls to this function can be used to reconfigure some parameters |
<> | 144:ef7eb2e8f9f7 | 1602 | * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting |
<> | 144:ef7eb2e8f9f7 | 1603 | * the ADC. |
<> | 144:ef7eb2e8f9f7 | 1604 | * The setting of these parameters is conditioned to ADC state. |
<> | 144:ef7eb2e8f9f7 | 1605 | * For parameters constraints, see comments of structure |
<> | 144:ef7eb2e8f9f7 | 1606 | * "ADC_ChannelConfTypeDef". |
Anna Bridge |
180:96ed750bd169 | 1607 | * @param hadc ADC handle |
Anna Bridge |
180:96ed750bd169 | 1608 | * @param sConfig Structure of ADC channel for regular group. |
<> | 144:ef7eb2e8f9f7 | 1609 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1610 | */ |
<> | 144:ef7eb2e8f9f7 | 1611 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) |
<> | 144:ef7eb2e8f9f7 | 1612 | { |
<> | 144:ef7eb2e8f9f7 | 1613 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 156:95d6b41a828b | 1614 | __IO uint32_t wait_loop_index = 0U; |
<> | 144:ef7eb2e8f9f7 | 1615 | |
<> | 144:ef7eb2e8f9f7 | 1616 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1617 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1618 | assert_param(IS_ADC_CHANNEL(sConfig->Channel)); |
<> | 144:ef7eb2e8f9f7 | 1619 | assert_param(IS_ADC_RANK(sConfig->Rank)); |
<> | 144:ef7eb2e8f9f7 | 1620 | |
<> | 144:ef7eb2e8f9f7 | 1621 | if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) |
<> | 144:ef7eb2e8f9f7 | 1622 | { |
<> | 144:ef7eb2e8f9f7 | 1623 | assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); |
<> | 144:ef7eb2e8f9f7 | 1624 | } |
<> | 144:ef7eb2e8f9f7 | 1625 | |
<> | 144:ef7eb2e8f9f7 | 1626 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1627 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1628 | |
<> | 144:ef7eb2e8f9f7 | 1629 | /* Parameters update conditioned to ADC state: */ |
<> | 144:ef7eb2e8f9f7 | 1630 | /* Parameters that can be updated when ADC is disabled or enabled without */ |
<> | 144:ef7eb2e8f9f7 | 1631 | /* conversion on going on regular group: */ |
<> | 144:ef7eb2e8f9f7 | 1632 | /* - Channel number */ |
<> | 144:ef7eb2e8f9f7 | 1633 | /* - Channel sampling time */ |
<> | 144:ef7eb2e8f9f7 | 1634 | /* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */ |
<> | 144:ef7eb2e8f9f7 | 1635 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1636 | { |
<> | 144:ef7eb2e8f9f7 | 1637 | /* Configure channel: depending on rank setting, add it or remove it from */ |
<> | 144:ef7eb2e8f9f7 | 1638 | /* ADC conversion sequencer. */ |
<> | 144:ef7eb2e8f9f7 | 1639 | if (sConfig->Rank != ADC_RANK_NONE) |
<> | 144:ef7eb2e8f9f7 | 1640 | { |
<> | 144:ef7eb2e8f9f7 | 1641 | /* Regular sequence configuration */ |
<> | 144:ef7eb2e8f9f7 | 1642 | /* Set the channel selection register from the selected channel */ |
<> | 144:ef7eb2e8f9f7 | 1643 | hadc->Instance->CHSELR |= ADC_CHSELR_CHANNEL(sConfig->Channel); |
<> | 144:ef7eb2e8f9f7 | 1644 | |
<> | 144:ef7eb2e8f9f7 | 1645 | /* Channel sampling time configuration */ |
<> | 144:ef7eb2e8f9f7 | 1646 | /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ |
<> | 144:ef7eb2e8f9f7 | 1647 | /* (obsolete): sampling time set in this function with */ |
<> | 144:ef7eb2e8f9f7 | 1648 | /* parameter "SamplingTime" (obsolete) only if not already set into */ |
<> | 144:ef7eb2e8f9f7 | 1649 | /* ADC initialization structure with parameter "SamplingTimeCommon". */ |
<> | 144:ef7eb2e8f9f7 | 1650 | if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) |
<> | 144:ef7eb2e8f9f7 | 1651 | { |
<> | 144:ef7eb2e8f9f7 | 1652 | /* Modify sampling time if needed (not needed in case of reoccurrence */ |
<> | 144:ef7eb2e8f9f7 | 1653 | /* for several channels programmed consecutively into the sequencer) */ |
<> | 144:ef7eb2e8f9f7 | 1654 | if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc)) |
<> | 144:ef7eb2e8f9f7 | 1655 | { |
<> | 144:ef7eb2e8f9f7 | 1656 | /* Channel sampling time configuration */ |
<> | 144:ef7eb2e8f9f7 | 1657 | /* Clear the old sample time */ |
<> | 144:ef7eb2e8f9f7 | 1658 | hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); |
<> | 144:ef7eb2e8f9f7 | 1659 | |
<> | 144:ef7eb2e8f9f7 | 1660 | /* Set the new sample time */ |
<> | 144:ef7eb2e8f9f7 | 1661 | hadc->Instance->SMPR |= ADC_SMPR_SET(sConfig->SamplingTime); |
<> | 144:ef7eb2e8f9f7 | 1662 | } |
<> | 144:ef7eb2e8f9f7 | 1663 | } |
<> | 144:ef7eb2e8f9f7 | 1664 | |
<> | 144:ef7eb2e8f9f7 | 1665 | /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ |
<> | 144:ef7eb2e8f9f7 | 1666 | /* internal measurement paths enable: If internal channel selected, */ |
<> | 144:ef7eb2e8f9f7 | 1667 | /* enable dedicated internal buffers and path. */ |
<> | 144:ef7eb2e8f9f7 | 1668 | /* Note: these internal measurement paths can be disabled using */ |
<> | 144:ef7eb2e8f9f7 | 1669 | /* HAL_ADC_DeInit() or removing the channel from sequencer with */ |
<> | 144:ef7eb2e8f9f7 | 1670 | /* channel configuration parameter "Rank". */ |
<> | 144:ef7eb2e8f9f7 | 1671 | if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) |
<> | 144:ef7eb2e8f9f7 | 1672 | { |
<> | 144:ef7eb2e8f9f7 | 1673 | /* If Channel_16 is selected, enable Temp. sensor measurement path. */ |
<> | 144:ef7eb2e8f9f7 | 1674 | /* If Channel_17 is selected, enable VREFINT measurement path. */ |
<> | 144:ef7eb2e8f9f7 | 1675 | /* If Channel_18 is selected, enable VBAT measurement path. */ |
<> | 144:ef7eb2e8f9f7 | 1676 | ADC->CCR |= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); |
<> | 144:ef7eb2e8f9f7 | 1677 | |
<> | 144:ef7eb2e8f9f7 | 1678 | /* If Temp. sensor is selected, wait for stabilization delay */ |
<> | 144:ef7eb2e8f9f7 | 1679 | if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) |
<> | 144:ef7eb2e8f9f7 | 1680 | { |
<> | 144:ef7eb2e8f9f7 | 1681 | /* Delay for temperature sensor stabilization time */ |
<> | 144:ef7eb2e8f9f7 | 1682 | /* Compute number of CPU cycles to wait for */ |
<> | 156:95d6b41a828b | 1683 | wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); |
<> | 156:95d6b41a828b | 1684 | while(wait_loop_index != 0U) |
<> | 144:ef7eb2e8f9f7 | 1685 | { |
<> | 144:ef7eb2e8f9f7 | 1686 | wait_loop_index--; |
<> | 144:ef7eb2e8f9f7 | 1687 | } |
<> | 144:ef7eb2e8f9f7 | 1688 | } |
<> | 144:ef7eb2e8f9f7 | 1689 | } |
<> | 144:ef7eb2e8f9f7 | 1690 | } |
<> | 144:ef7eb2e8f9f7 | 1691 | else |
<> | 144:ef7eb2e8f9f7 | 1692 | { |
<> | 144:ef7eb2e8f9f7 | 1693 | /* Regular sequence configuration */ |
<> | 144:ef7eb2e8f9f7 | 1694 | /* Reset the channel selection register from the selected channel */ |
<> | 144:ef7eb2e8f9f7 | 1695 | hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel); |
<> | 144:ef7eb2e8f9f7 | 1696 | |
<> | 144:ef7eb2e8f9f7 | 1697 | /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ |
<> | 144:ef7eb2e8f9f7 | 1698 | /* internal measurement paths disable: If internal channel selected, */ |
<> | 144:ef7eb2e8f9f7 | 1699 | /* disable dedicated internal buffers and path. */ |
<> | 144:ef7eb2e8f9f7 | 1700 | if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) |
<> | 144:ef7eb2e8f9f7 | 1701 | { |
<> | 144:ef7eb2e8f9f7 | 1702 | /* If Channel_16 is selected, disable Temp. sensor measurement path. */ |
<> | 144:ef7eb2e8f9f7 | 1703 | /* If Channel_17 is selected, disable VREFINT measurement path. */ |
<> | 144:ef7eb2e8f9f7 | 1704 | /* If Channel_18 is selected, disable VBAT measurement path. */ |
<> | 144:ef7eb2e8f9f7 | 1705 | ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); |
<> | 144:ef7eb2e8f9f7 | 1706 | } |
<> | 144:ef7eb2e8f9f7 | 1707 | } |
<> | 144:ef7eb2e8f9f7 | 1708 | |
<> | 144:ef7eb2e8f9f7 | 1709 | } |
<> | 144:ef7eb2e8f9f7 | 1710 | |
<> | 144:ef7eb2e8f9f7 | 1711 | /* If a conversion is on going on regular group, no update on regular */ |
<> | 144:ef7eb2e8f9f7 | 1712 | /* channel could be done on neither of the channel configuration structure */ |
<> | 144:ef7eb2e8f9f7 | 1713 | /* parameters. */ |
<> | 144:ef7eb2e8f9f7 | 1714 | else |
<> | 144:ef7eb2e8f9f7 | 1715 | { |
<> | 144:ef7eb2e8f9f7 | 1716 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 1717 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
<> | 144:ef7eb2e8f9f7 | 1718 | |
<> | 144:ef7eb2e8f9f7 | 1719 | tmp_hal_status = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1720 | } |
<> | 144:ef7eb2e8f9f7 | 1721 | |
<> | 144:ef7eb2e8f9f7 | 1722 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1723 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1724 | |
<> | 144:ef7eb2e8f9f7 | 1725 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1726 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 1727 | } |
<> | 144:ef7eb2e8f9f7 | 1728 | |
<> | 144:ef7eb2e8f9f7 | 1729 | |
<> | 144:ef7eb2e8f9f7 | 1730 | /** |
<> | 144:ef7eb2e8f9f7 | 1731 | * @brief Configures the analog watchdog. |
<> | 144:ef7eb2e8f9f7 | 1732 | * @note Possibility to update parameters on the fly: |
<> | 144:ef7eb2e8f9f7 | 1733 | * This function initializes the selected analog watchdog, following |
<> | 144:ef7eb2e8f9f7 | 1734 | * calls to this function can be used to reconfigure some parameters |
<> | 144:ef7eb2e8f9f7 | 1735 | * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting |
<> | 144:ef7eb2e8f9f7 | 1736 | * the ADC. |
<> | 144:ef7eb2e8f9f7 | 1737 | * The setting of these parameters is conditioned to ADC state. |
<> | 144:ef7eb2e8f9f7 | 1738 | * For parameters constraints, see comments of structure |
<> | 144:ef7eb2e8f9f7 | 1739 | * "ADC_AnalogWDGConfTypeDef". |
Anna Bridge |
180:96ed750bd169 | 1740 | * @param hadc ADC handle |
Anna Bridge |
180:96ed750bd169 | 1741 | * @param AnalogWDGConfig Structure of ADC analog watchdog configuration |
<> | 144:ef7eb2e8f9f7 | 1742 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1743 | */ |
<> | 144:ef7eb2e8f9f7 | 1744 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) |
<> | 144:ef7eb2e8f9f7 | 1745 | { |
<> | 144:ef7eb2e8f9f7 | 1746 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1747 | |
<> | 144:ef7eb2e8f9f7 | 1748 | uint32_t tmpAWDHighThresholdShifted; |
<> | 144:ef7eb2e8f9f7 | 1749 | uint32_t tmpAWDLowThresholdShifted; |
<> | 144:ef7eb2e8f9f7 | 1750 | |
<> | 144:ef7eb2e8f9f7 | 1751 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1752 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1753 | assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); |
<> | 144:ef7eb2e8f9f7 | 1754 | assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); |
<> | 144:ef7eb2e8f9f7 | 1755 | |
<> | 144:ef7eb2e8f9f7 | 1756 | /* Verify if threshold is within the selected ADC resolution */ |
<> | 144:ef7eb2e8f9f7 | 1757 | assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); |
<> | 144:ef7eb2e8f9f7 | 1758 | assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); |
<> | 144:ef7eb2e8f9f7 | 1759 | |
<> | 144:ef7eb2e8f9f7 | 1760 | if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) |
<> | 144:ef7eb2e8f9f7 | 1761 | { |
<> | 144:ef7eb2e8f9f7 | 1762 | assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); |
<> | 144:ef7eb2e8f9f7 | 1763 | } |
<> | 144:ef7eb2e8f9f7 | 1764 | |
<> | 144:ef7eb2e8f9f7 | 1765 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1766 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1767 | |
<> | 144:ef7eb2e8f9f7 | 1768 | /* Parameters update conditioned to ADC state: */ |
<> | 144:ef7eb2e8f9f7 | 1769 | /* Parameters that can be updated when ADC is disabled or enabled without */ |
<> | 144:ef7eb2e8f9f7 | 1770 | /* conversion on going on regular group: */ |
<> | 144:ef7eb2e8f9f7 | 1771 | /* - Analog watchdog channels */ |
<> | 144:ef7eb2e8f9f7 | 1772 | /* - Analog watchdog thresholds */ |
<> | 144:ef7eb2e8f9f7 | 1773 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1774 | { |
<> | 144:ef7eb2e8f9f7 | 1775 | /* Configuration of analog watchdog: */ |
<> | 144:ef7eb2e8f9f7 | 1776 | /* - Set the analog watchdog enable mode: one or overall group of */ |
<> | 144:ef7eb2e8f9f7 | 1777 | /* channels. */ |
<> | 144:ef7eb2e8f9f7 | 1778 | /* - Set the Analog watchdog channel (is not used if watchdog */ |
<> | 144:ef7eb2e8f9f7 | 1779 | /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ |
<> | 144:ef7eb2e8f9f7 | 1780 | hadc->Instance->CFGR1 &= ~( ADC_CFGR1_AWDSGL | |
<> | 144:ef7eb2e8f9f7 | 1781 | ADC_CFGR1_AWDEN | |
<> | 144:ef7eb2e8f9f7 | 1782 | ADC_CFGR1_AWDCH ); |
<> | 144:ef7eb2e8f9f7 | 1783 | |
<> | 144:ef7eb2e8f9f7 | 1784 | hadc->Instance->CFGR1 |= ( AnalogWDGConfig->WatchdogMode | |
<> | 144:ef7eb2e8f9f7 | 1785 | ADC_CFGR_AWDCH(AnalogWDGConfig->Channel) ); |
<> | 144:ef7eb2e8f9f7 | 1786 | |
<> | 144:ef7eb2e8f9f7 | 1787 | /* Shift the offset in function of the selected ADC resolution: Thresholds*/ |
<> | 144:ef7eb2e8f9f7 | 1788 | /* have to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ |
<> | 144:ef7eb2e8f9f7 | 1789 | tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); |
<> | 144:ef7eb2e8f9f7 | 1790 | tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); |
<> | 144:ef7eb2e8f9f7 | 1791 | |
<> | 144:ef7eb2e8f9f7 | 1792 | /* Set the high and low thresholds */ |
<> | 144:ef7eb2e8f9f7 | 1793 | hadc->Instance->TR &= ~(ADC_TR_HT | ADC_TR_LT); |
<> | 144:ef7eb2e8f9f7 | 1794 | hadc->Instance->TR |= ( ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | |
<> | 144:ef7eb2e8f9f7 | 1795 | tmpAWDLowThresholdShifted ); |
<> | 144:ef7eb2e8f9f7 | 1796 | |
<> | 144:ef7eb2e8f9f7 | 1797 | /* Clear the ADC Analog watchdog flag (in case of left enabled by */ |
<> | 144:ef7eb2e8f9f7 | 1798 | /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */ |
<> | 144:ef7eb2e8f9f7 | 1799 | /* or HAL_ADC_PollForEvent(). */ |
<> | 144:ef7eb2e8f9f7 | 1800 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD); |
<> | 144:ef7eb2e8f9f7 | 1801 | |
<> | 144:ef7eb2e8f9f7 | 1802 | /* Configure ADC Analog watchdog interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1803 | if(AnalogWDGConfig->ITMode == ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1804 | { |
<> | 144:ef7eb2e8f9f7 | 1805 | /* Enable the ADC Analog watchdog interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1806 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); |
<> | 144:ef7eb2e8f9f7 | 1807 | } |
<> | 144:ef7eb2e8f9f7 | 1808 | else |
<> | 144:ef7eb2e8f9f7 | 1809 | { |
<> | 144:ef7eb2e8f9f7 | 1810 | /* Disable the ADC Analog watchdog interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1811 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); |
<> | 144:ef7eb2e8f9f7 | 1812 | } |
<> | 144:ef7eb2e8f9f7 | 1813 | |
<> | 144:ef7eb2e8f9f7 | 1814 | } |
<> | 144:ef7eb2e8f9f7 | 1815 | /* If a conversion is on going on regular group, no update could be done */ |
<> | 144:ef7eb2e8f9f7 | 1816 | /* on neither of the AWD configuration structure parameters. */ |
<> | 144:ef7eb2e8f9f7 | 1817 | else |
<> | 144:ef7eb2e8f9f7 | 1818 | { |
<> | 144:ef7eb2e8f9f7 | 1819 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 1820 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
<> | 144:ef7eb2e8f9f7 | 1821 | |
<> | 144:ef7eb2e8f9f7 | 1822 | tmp_hal_status = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1823 | } |
<> | 144:ef7eb2e8f9f7 | 1824 | |
<> | 144:ef7eb2e8f9f7 | 1825 | |
<> | 144:ef7eb2e8f9f7 | 1826 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1827 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1828 | |
<> | 144:ef7eb2e8f9f7 | 1829 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1830 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 1831 | } |
<> | 144:ef7eb2e8f9f7 | 1832 | |
<> | 144:ef7eb2e8f9f7 | 1833 | |
<> | 144:ef7eb2e8f9f7 | 1834 | /** |
<> | 144:ef7eb2e8f9f7 | 1835 | * @} |
<> | 144:ef7eb2e8f9f7 | 1836 | */ |
<> | 144:ef7eb2e8f9f7 | 1837 | |
<> | 144:ef7eb2e8f9f7 | 1838 | |
<> | 144:ef7eb2e8f9f7 | 1839 | /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions |
<> | 144:ef7eb2e8f9f7 | 1840 | * @brief Peripheral State functions |
<> | 144:ef7eb2e8f9f7 | 1841 | * |
<> | 144:ef7eb2e8f9f7 | 1842 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 1843 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1844 | ##### Peripheral State and Errors functions ##### |
<> | 144:ef7eb2e8f9f7 | 1845 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1846 | [..] |
<> | 144:ef7eb2e8f9f7 | 1847 | This subsection provides functions to get in run-time the status of the |
<> | 144:ef7eb2e8f9f7 | 1848 | peripheral. |
<> | 144:ef7eb2e8f9f7 | 1849 | (+) Check the ADC state |
<> | 144:ef7eb2e8f9f7 | 1850 | (+) Check the ADC error code |
<> | 144:ef7eb2e8f9f7 | 1851 | |
<> | 144:ef7eb2e8f9f7 | 1852 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 1853 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1854 | */ |
<> | 144:ef7eb2e8f9f7 | 1855 | |
<> | 144:ef7eb2e8f9f7 | 1856 | /** |
<> | 144:ef7eb2e8f9f7 | 1857 | * @brief Return the ADC state |
<> | 144:ef7eb2e8f9f7 | 1858 | * @note ADC state machine is managed by bitfields, ADC status must be |
<> | 144:ef7eb2e8f9f7 | 1859 | * compared with states bits. |
<> | 144:ef7eb2e8f9f7 | 1860 | * For example: |
<> | 144:ef7eb2e8f9f7 | 1861 | * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " |
<> | 144:ef7eb2e8f9f7 | 1862 | * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " |
Anna Bridge |
180:96ed750bd169 | 1863 | * @param hadc ADC handle |
<> | 144:ef7eb2e8f9f7 | 1864 | * @retval HAL state |
<> | 144:ef7eb2e8f9f7 | 1865 | */ |
<> | 144:ef7eb2e8f9f7 | 1866 | uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1867 | { |
<> | 144:ef7eb2e8f9f7 | 1868 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1869 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1870 | |
<> | 144:ef7eb2e8f9f7 | 1871 | /* Return ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1872 | return hadc->State; |
<> | 144:ef7eb2e8f9f7 | 1873 | } |
<> | 144:ef7eb2e8f9f7 | 1874 | |
<> | 144:ef7eb2e8f9f7 | 1875 | /** |
<> | 144:ef7eb2e8f9f7 | 1876 | * @brief Return the ADC error code |
Anna Bridge |
180:96ed750bd169 | 1877 | * @param hadc ADC handle |
<> | 144:ef7eb2e8f9f7 | 1878 | * @retval ADC Error Code |
<> | 144:ef7eb2e8f9f7 | 1879 | */ |
<> | 144:ef7eb2e8f9f7 | 1880 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) |
<> | 144:ef7eb2e8f9f7 | 1881 | { |
<> | 144:ef7eb2e8f9f7 | 1882 | return hadc->ErrorCode; |
<> | 144:ef7eb2e8f9f7 | 1883 | } |
<> | 144:ef7eb2e8f9f7 | 1884 | |
<> | 144:ef7eb2e8f9f7 | 1885 | /** |
<> | 144:ef7eb2e8f9f7 | 1886 | * @} |
<> | 144:ef7eb2e8f9f7 | 1887 | */ |
<> | 144:ef7eb2e8f9f7 | 1888 | |
<> | 144:ef7eb2e8f9f7 | 1889 | /** |
<> | 144:ef7eb2e8f9f7 | 1890 | * @} |
<> | 144:ef7eb2e8f9f7 | 1891 | */ |
<> | 144:ef7eb2e8f9f7 | 1892 | |
<> | 144:ef7eb2e8f9f7 | 1893 | /** @defgroup ADC_Private_Functions ADC Private Functions |
<> | 144:ef7eb2e8f9f7 | 1894 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1895 | */ |
<> | 144:ef7eb2e8f9f7 | 1896 | |
<> | 144:ef7eb2e8f9f7 | 1897 | /** |
<> | 144:ef7eb2e8f9f7 | 1898 | * @brief Enable the selected ADC. |
<> | 144:ef7eb2e8f9f7 | 1899 | * @note Prerequisite condition to use this function: ADC must be disabled |
<> | 144:ef7eb2e8f9f7 | 1900 | * and voltage regulator must be enabled (done into HAL_ADC_Init()). |
<> | 144:ef7eb2e8f9f7 | 1901 | * @note If low power mode AutoPowerOff is enabled, power-on/off phases are |
<> | 144:ef7eb2e8f9f7 | 1902 | * performed automatically by hardware. |
<> | 144:ef7eb2e8f9f7 | 1903 | * In this mode, this function is useless and must not be called because |
<> | 144:ef7eb2e8f9f7 | 1904 | * flag ADC_FLAG_RDY is not usable. |
<> | 144:ef7eb2e8f9f7 | 1905 | * Therefore, this function must be called under condition of |
<> | 144:ef7eb2e8f9f7 | 1906 | * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)". |
Anna Bridge |
180:96ed750bd169 | 1907 | * @param hadc ADC handle |
<> | 144:ef7eb2e8f9f7 | 1908 | * @retval HAL status. |
<> | 144:ef7eb2e8f9f7 | 1909 | */ |
<> | 144:ef7eb2e8f9f7 | 1910 | static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1911 | { |
<> | 156:95d6b41a828b | 1912 | uint32_t tickstart = 0U; |
<> | 156:95d6b41a828b | 1913 | __IO uint32_t wait_loop_index = 0U; |
<> | 144:ef7eb2e8f9f7 | 1914 | |
<> | 144:ef7eb2e8f9f7 | 1915 | /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ |
<> | 144:ef7eb2e8f9f7 | 1916 | /* enabling phase not yet completed: flag ADC ready not yet set). */ |
<> | 144:ef7eb2e8f9f7 | 1917 | /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ |
<> | 144:ef7eb2e8f9f7 | 1918 | /* causes: ADC clock not running, ...). */ |
<> | 144:ef7eb2e8f9f7 | 1919 | if (ADC_IS_ENABLE(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1920 | { |
<> | 144:ef7eb2e8f9f7 | 1921 | /* Check if conditions to enable the ADC are fulfilled */ |
<> | 144:ef7eb2e8f9f7 | 1922 | if (ADC_ENABLING_CONDITIONS(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1923 | { |
<> | 144:ef7eb2e8f9f7 | 1924 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 1925 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 1926 | |
<> | 144:ef7eb2e8f9f7 | 1927 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 1928 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 1929 | |
<> | 144:ef7eb2e8f9f7 | 1930 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1931 | } |
<> | 144:ef7eb2e8f9f7 | 1932 | |
<> | 144:ef7eb2e8f9f7 | 1933 | /* Enable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1934 | __HAL_ADC_ENABLE(hadc); |
<> | 144:ef7eb2e8f9f7 | 1935 | |
<> | 144:ef7eb2e8f9f7 | 1936 | /* Delay for ADC stabilization time */ |
<> | 144:ef7eb2e8f9f7 | 1937 | /* Compute number of CPU cycles to wait for */ |
<> | 156:95d6b41a828b | 1938 | wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); |
<> | 156:95d6b41a828b | 1939 | while(wait_loop_index != 0U) |
<> | 144:ef7eb2e8f9f7 | 1940 | { |
<> | 144:ef7eb2e8f9f7 | 1941 | wait_loop_index--; |
<> | 144:ef7eb2e8f9f7 | 1942 | } |
<> | 144:ef7eb2e8f9f7 | 1943 | |
<> | 144:ef7eb2e8f9f7 | 1944 | /* Get tick count */ |
<> | 144:ef7eb2e8f9f7 | 1945 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 1946 | |
<> | 144:ef7eb2e8f9f7 | 1947 | /* Wait for ADC effectively enabled */ |
<> | 144:ef7eb2e8f9f7 | 1948 | while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1949 | { |
<> | 144:ef7eb2e8f9f7 | 1950 | if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) |
<> | 144:ef7eb2e8f9f7 | 1951 | { |
<> | 144:ef7eb2e8f9f7 | 1952 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 1953 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 1954 | |
<> | 144:ef7eb2e8f9f7 | 1955 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 1956 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 1957 | |
<> | 144:ef7eb2e8f9f7 | 1958 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1959 | } |
<> | 144:ef7eb2e8f9f7 | 1960 | } |
<> | 144:ef7eb2e8f9f7 | 1961 | |
<> | 144:ef7eb2e8f9f7 | 1962 | } |
<> | 144:ef7eb2e8f9f7 | 1963 | |
<> | 144:ef7eb2e8f9f7 | 1964 | /* Return HAL status */ |
<> | 144:ef7eb2e8f9f7 | 1965 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1966 | } |
<> | 144:ef7eb2e8f9f7 | 1967 | |
<> | 144:ef7eb2e8f9f7 | 1968 | /** |
<> | 144:ef7eb2e8f9f7 | 1969 | * @brief Disable the selected ADC. |
<> | 144:ef7eb2e8f9f7 | 1970 | * @note Prerequisite condition to use this function: ADC conversions must be |
<> | 144:ef7eb2e8f9f7 | 1971 | * stopped. |
Anna Bridge |
180:96ed750bd169 | 1972 | * @param hadc ADC handle |
<> | 144:ef7eb2e8f9f7 | 1973 | * @retval HAL status. |
<> | 144:ef7eb2e8f9f7 | 1974 | */ |
<> | 144:ef7eb2e8f9f7 | 1975 | static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1976 | { |
<> | 156:95d6b41a828b | 1977 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 1978 | |
<> | 144:ef7eb2e8f9f7 | 1979 | /* Verification if ADC is not already disabled: */ |
<> | 144:ef7eb2e8f9f7 | 1980 | /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ |
<> | 144:ef7eb2e8f9f7 | 1981 | /* disabled. */ |
<> | 144:ef7eb2e8f9f7 | 1982 | if (ADC_IS_ENABLE(hadc) != RESET) |
<> | 144:ef7eb2e8f9f7 | 1983 | { |
<> | 144:ef7eb2e8f9f7 | 1984 | /* Check if conditions to disable the ADC are fulfilled */ |
<> | 144:ef7eb2e8f9f7 | 1985 | if (ADC_DISABLING_CONDITIONS(hadc) != RESET) |
<> | 144:ef7eb2e8f9f7 | 1986 | { |
<> | 144:ef7eb2e8f9f7 | 1987 | /* Disable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1988 | __HAL_ADC_DISABLE(hadc); |
<> | 144:ef7eb2e8f9f7 | 1989 | } |
<> | 144:ef7eb2e8f9f7 | 1990 | else |
<> | 144:ef7eb2e8f9f7 | 1991 | { |
<> | 144:ef7eb2e8f9f7 | 1992 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 1993 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 1994 | |
<> | 144:ef7eb2e8f9f7 | 1995 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 1996 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 1997 | |
<> | 144:ef7eb2e8f9f7 | 1998 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1999 | } |
<> | 144:ef7eb2e8f9f7 | 2000 | |
<> | 144:ef7eb2e8f9f7 | 2001 | /* Wait for ADC effectively disabled */ |
<> | 144:ef7eb2e8f9f7 | 2002 | /* Get tick count */ |
<> | 144:ef7eb2e8f9f7 | 2003 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 2004 | |
<> | 144:ef7eb2e8f9f7 | 2005 | while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) |
<> | 144:ef7eb2e8f9f7 | 2006 | { |
<> | 144:ef7eb2e8f9f7 | 2007 | if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) |
<> | 144:ef7eb2e8f9f7 | 2008 | { |
<> | 144:ef7eb2e8f9f7 | 2009 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 2010 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 2011 | |
<> | 144:ef7eb2e8f9f7 | 2012 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 2013 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 2014 | |
<> | 144:ef7eb2e8f9f7 | 2015 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 2016 | } |
<> | 144:ef7eb2e8f9f7 | 2017 | } |
<> | 144:ef7eb2e8f9f7 | 2018 | } |
<> | 144:ef7eb2e8f9f7 | 2019 | |
<> | 144:ef7eb2e8f9f7 | 2020 | /* Return HAL status */ |
<> | 144:ef7eb2e8f9f7 | 2021 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2022 | } |
<> | 144:ef7eb2e8f9f7 | 2023 | |
<> | 144:ef7eb2e8f9f7 | 2024 | |
<> | 144:ef7eb2e8f9f7 | 2025 | /** |
<> | 144:ef7eb2e8f9f7 | 2026 | * @brief Stop ADC conversion. |
<> | 144:ef7eb2e8f9f7 | 2027 | * @note Prerequisite condition to use this function: ADC conversions must be |
<> | 144:ef7eb2e8f9f7 | 2028 | * stopped to disable the ADC. |
Anna Bridge |
180:96ed750bd169 | 2029 | * @param hadc ADC handle |
<> | 144:ef7eb2e8f9f7 | 2030 | * @retval HAL status. |
<> | 144:ef7eb2e8f9f7 | 2031 | */ |
<> | 144:ef7eb2e8f9f7 | 2032 | static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 2033 | { |
<> | 156:95d6b41a828b | 2034 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 2035 | |
<> | 144:ef7eb2e8f9f7 | 2036 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 2037 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 2038 | |
<> | 144:ef7eb2e8f9f7 | 2039 | /* Verification if ADC is not already stopped on regular group to bypass */ |
<> | 144:ef7eb2e8f9f7 | 2040 | /* this function if not needed. */ |
<> | 144:ef7eb2e8f9f7 | 2041 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) |
<> | 144:ef7eb2e8f9f7 | 2042 | { |
<> | 144:ef7eb2e8f9f7 | 2043 | |
<> | 144:ef7eb2e8f9f7 | 2044 | /* Stop potential conversion on going on regular group */ |
<> | 144:ef7eb2e8f9f7 | 2045 | /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ |
<> | 144:ef7eb2e8f9f7 | 2046 | if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && |
<> | 144:ef7eb2e8f9f7 | 2047 | HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) |
<> | 144:ef7eb2e8f9f7 | 2048 | { |
<> | 144:ef7eb2e8f9f7 | 2049 | /* Stop conversions on regular group */ |
<> | 144:ef7eb2e8f9f7 | 2050 | hadc->Instance->CR |= ADC_CR_ADSTP; |
<> | 144:ef7eb2e8f9f7 | 2051 | } |
<> | 144:ef7eb2e8f9f7 | 2052 | |
<> | 144:ef7eb2e8f9f7 | 2053 | /* Wait for conversion effectively stopped */ |
<> | 144:ef7eb2e8f9f7 | 2054 | /* Get tick count */ |
<> | 144:ef7eb2e8f9f7 | 2055 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 2056 | |
<> | 144:ef7eb2e8f9f7 | 2057 | while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET) |
<> | 144:ef7eb2e8f9f7 | 2058 | { |
<> | 144:ef7eb2e8f9f7 | 2059 | if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) |
<> | 144:ef7eb2e8f9f7 | 2060 | { |
<> | 144:ef7eb2e8f9f7 | 2061 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 2062 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 2063 | |
<> | 144:ef7eb2e8f9f7 | 2064 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 2065 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 2066 | |
<> | 144:ef7eb2e8f9f7 | 2067 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 2068 | } |
<> | 144:ef7eb2e8f9f7 | 2069 | } |
<> | 144:ef7eb2e8f9f7 | 2070 | |
<> | 144:ef7eb2e8f9f7 | 2071 | } |
<> | 144:ef7eb2e8f9f7 | 2072 | |
<> | 144:ef7eb2e8f9f7 | 2073 | /* Return HAL status */ |
<> | 144:ef7eb2e8f9f7 | 2074 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2075 | } |
<> | 144:ef7eb2e8f9f7 | 2076 | |
<> | 144:ef7eb2e8f9f7 | 2077 | |
<> | 144:ef7eb2e8f9f7 | 2078 | /** |
<> | 144:ef7eb2e8f9f7 | 2079 | * @brief DMA transfer complete callback. |
Anna Bridge |
180:96ed750bd169 | 2080 | * @param hdma pointer to DMA handle. |
<> | 144:ef7eb2e8f9f7 | 2081 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2082 | */ |
<> | 144:ef7eb2e8f9f7 | 2083 | static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2084 | { |
<> | 144:ef7eb2e8f9f7 | 2085 | /* Retrieve ADC handle corresponding to current DMA handle */ |
<> | 144:ef7eb2e8f9f7 | 2086 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 2087 | |
<> | 144:ef7eb2e8f9f7 | 2088 | /* Update state machine on conversion status if not in error state */ |
<> | 144:ef7eb2e8f9f7 | 2089 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) |
<> | 144:ef7eb2e8f9f7 | 2090 | { |
<> | 144:ef7eb2e8f9f7 | 2091 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 2092 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
<> | 144:ef7eb2e8f9f7 | 2093 | |
<> | 144:ef7eb2e8f9f7 | 2094 | /* Determine whether any further conversion upcoming on group regular */ |
<> | 144:ef7eb2e8f9f7 | 2095 | /* by external trigger, continuous mode or scan sequence on going. */ |
<> | 144:ef7eb2e8f9f7 | 2096 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
<> | 144:ef7eb2e8f9f7 | 2097 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
<> | 144:ef7eb2e8f9f7 | 2098 | { |
<> | 144:ef7eb2e8f9f7 | 2099 | /* If End of Sequence is reached, disable interrupts */ |
<> | 144:ef7eb2e8f9f7 | 2100 | if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) |
<> | 144:ef7eb2e8f9f7 | 2101 | { |
<> | 144:ef7eb2e8f9f7 | 2102 | /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ |
<> | 144:ef7eb2e8f9f7 | 2103 | /* ADSTART==0 (no conversion on going) */ |
<> | 144:ef7eb2e8f9f7 | 2104 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 2105 | { |
<> | 144:ef7eb2e8f9f7 | 2106 | /* Disable ADC end of single conversion interrupt on group regular */ |
<> | 144:ef7eb2e8f9f7 | 2107 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
<> | 144:ef7eb2e8f9f7 | 2108 | /* HAL_Start_IT(), but is not disabled here because can be used */ |
<> | 144:ef7eb2e8f9f7 | 2109 | /* by overrun IRQ process below. */ |
<> | 144:ef7eb2e8f9f7 | 2110 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); |
<> | 144:ef7eb2e8f9f7 | 2111 | |
<> | 144:ef7eb2e8f9f7 | 2112 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 2113 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 2114 | HAL_ADC_STATE_REG_BUSY, |
<> | 144:ef7eb2e8f9f7 | 2115 | HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 2116 | } |
<> | 144:ef7eb2e8f9f7 | 2117 | else |
<> | 144:ef7eb2e8f9f7 | 2118 | { |
<> | 144:ef7eb2e8f9f7 | 2119 | /* Change ADC state to error state */ |
<> | 144:ef7eb2e8f9f7 | 2120 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
<> | 144:ef7eb2e8f9f7 | 2121 | |
<> | 144:ef7eb2e8f9f7 | 2122 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 2123 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 2124 | } |
<> | 144:ef7eb2e8f9f7 | 2125 | } |
<> | 144:ef7eb2e8f9f7 | 2126 | } |
<> | 144:ef7eb2e8f9f7 | 2127 | |
<> | 144:ef7eb2e8f9f7 | 2128 | /* Conversion complete callback */ |
<> | 144:ef7eb2e8f9f7 | 2129 | HAL_ADC_ConvCpltCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 2130 | } |
<> | 144:ef7eb2e8f9f7 | 2131 | else |
<> | 144:ef7eb2e8f9f7 | 2132 | { |
<> | 144:ef7eb2e8f9f7 | 2133 | /* Call DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 2134 | hadc->DMA_Handle->XferErrorCallback(hdma); |
<> | 144:ef7eb2e8f9f7 | 2135 | } |
<> | 144:ef7eb2e8f9f7 | 2136 | |
<> | 144:ef7eb2e8f9f7 | 2137 | } |
<> | 144:ef7eb2e8f9f7 | 2138 | |
<> | 144:ef7eb2e8f9f7 | 2139 | /** |
<> | 144:ef7eb2e8f9f7 | 2140 | * @brief DMA half transfer complete callback. |
Anna Bridge |
180:96ed750bd169 | 2141 | * @param hdma pointer to DMA handle. |
<> | 144:ef7eb2e8f9f7 | 2142 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2143 | */ |
<> | 144:ef7eb2e8f9f7 | 2144 | static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2145 | { |
<> | 144:ef7eb2e8f9f7 | 2146 | /* Retrieve ADC handle corresponding to current DMA handle */ |
<> | 144:ef7eb2e8f9f7 | 2147 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 2148 | |
<> | 144:ef7eb2e8f9f7 | 2149 | /* Half conversion callback */ |
<> | 144:ef7eb2e8f9f7 | 2150 | HAL_ADC_ConvHalfCpltCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 2151 | } |
<> | 144:ef7eb2e8f9f7 | 2152 | |
<> | 144:ef7eb2e8f9f7 | 2153 | /** |
<> | 144:ef7eb2e8f9f7 | 2154 | * @brief DMA error callback |
Anna Bridge |
180:96ed750bd169 | 2155 | * @param hdma pointer to DMA handle. |
<> | 144:ef7eb2e8f9f7 | 2156 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2157 | */ |
<> | 144:ef7eb2e8f9f7 | 2158 | static void ADC_DMAError(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2159 | { |
<> | 144:ef7eb2e8f9f7 | 2160 | /* Retrieve ADC handle corresponding to current DMA handle */ |
<> | 144:ef7eb2e8f9f7 | 2161 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 2162 | |
<> | 144:ef7eb2e8f9f7 | 2163 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 2164 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); |
<> | 144:ef7eb2e8f9f7 | 2165 | |
<> | 144:ef7eb2e8f9f7 | 2166 | /* Set ADC error code to DMA error */ |
<> | 144:ef7eb2e8f9f7 | 2167 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); |
<> | 144:ef7eb2e8f9f7 | 2168 | |
<> | 144:ef7eb2e8f9f7 | 2169 | /* Error callback */ |
<> | 144:ef7eb2e8f9f7 | 2170 | HAL_ADC_ErrorCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 2171 | } |
<> | 144:ef7eb2e8f9f7 | 2172 | |
<> | 144:ef7eb2e8f9f7 | 2173 | /** |
<> | 144:ef7eb2e8f9f7 | 2174 | * @} |
<> | 144:ef7eb2e8f9f7 | 2175 | */ |
<> | 144:ef7eb2e8f9f7 | 2176 | |
<> | 144:ef7eb2e8f9f7 | 2177 | #endif /* HAL_ADC_MODULE_ENABLED */ |
<> | 144:ef7eb2e8f9f7 | 2178 | /** |
<> | 144:ef7eb2e8f9f7 | 2179 | * @} |
<> | 144:ef7eb2e8f9f7 | 2180 | */ |
<> | 144:ef7eb2e8f9f7 | 2181 | |
<> | 144:ef7eb2e8f9f7 | 2182 | /** |
<> | 144:ef7eb2e8f9f7 | 2183 | * @} |
<> | 144:ef7eb2e8f9f7 | 2184 | */ |
<> | 144:ef7eb2e8f9f7 | 2185 | |
<> | 144:ef7eb2e8f9f7 | 2186 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |