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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.c@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:: <>
Date:: Mon Jan 16 15:03:32 2017 +0000
Revision:: 156:95d6b41a828b
Parent:: 149:156823d33999
Child:: 180:96ed750bd169

This updates the lib to the mbed lib v134

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f0xx_hal_adc.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	156:95d6b41a828b	5	* @version V1.5.0
<>	156:95d6b41a828b	6	* @date 04-November-2016
<>	144:ef7eb2e8f9f7	7	* @brief This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	8	* functionalities of the Analog to Digital Convertor (ADC)
<>	144:ef7eb2e8f9f7	9	* peripheral:
<>	144:ef7eb2e8f9f7	10	* + Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	11	* ++ Initialization and Configuration of ADC
<>	144:ef7eb2e8f9f7	12	* + Operation functions
<>	144:ef7eb2e8f9f7	13	* ++ Start, stop, get result of conversions of regular
<>	144:ef7eb2e8f9f7	14	* group, using 3 possible modes: polling, interruption or DMA.
<>	144:ef7eb2e8f9f7	15	* + Control functions
<>	144:ef7eb2e8f9f7	16	* ++ Channels configuration on regular group
<>	144:ef7eb2e8f9f7	17	* ++ Analog Watchdog configuration
<>	144:ef7eb2e8f9f7	18	* + State functions
<>	144:ef7eb2e8f9f7	19	* ++ ADC state machine management
<>	144:ef7eb2e8f9f7	20	* ++ Interrupts and flags management
<>	144:ef7eb2e8f9f7	21	* Other functions (extended functions) are available in file
<>	144:ef7eb2e8f9f7	22	* "stm32f0xx_hal_adc_ex.c".
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	@verbatim
<>	144:ef7eb2e8f9f7	25	==============================================================================
<>	144:ef7eb2e8f9f7	26	##### ADC peripheral features #####
<>	144:ef7eb2e8f9f7	27	==============================================================================
<>	144:ef7eb2e8f9f7	28	[..]
<>	144:ef7eb2e8f9f7	29	(+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
<>	144:ef7eb2e8f9f7	30
<>	144:ef7eb2e8f9f7	31	(+) Interrupt generation at the end of regular conversion and in case of
<>	144:ef7eb2e8f9f7	32	analog watchdog or overrun events.
<>	144:ef7eb2e8f9f7	33
<>	144:ef7eb2e8f9f7	34	(+) Single and continuous conversion modes.
<>	144:ef7eb2e8f9f7	35
<>	144:ef7eb2e8f9f7	36	(+) Scan mode for conversion of several channels sequentially.
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	(+) Data alignment with in-built data coherency.
<>	144:ef7eb2e8f9f7	39
<>	144:ef7eb2e8f9f7	40	(+) Programmable sampling time (common for all channels)
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	(+) ADC conversion of regular group.
<>	144:ef7eb2e8f9f7	43
<>	144:ef7eb2e8f9f7	44	(+) External trigger (timer or EXTI) with configurable polarity
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	(+) DMA request generation for transfer of conversions data of regular group.
<>	144:ef7eb2e8f9f7	47
<>	144:ef7eb2e8f9f7	48	(+) ADC calibration
<>	144:ef7eb2e8f9f7	49
<>	144:ef7eb2e8f9f7	50	(+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
<>	144:ef7eb2e8f9f7	51	slower speed.
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	(+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
<>	144:ef7eb2e8f9f7	54	Vdda or to an external voltage reference).
<>	144:ef7eb2e8f9f7	55
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	58	==============================================================================
<>	144:ef7eb2e8f9f7	59	[..]
<>	144:ef7eb2e8f9f7	60
<>	144:ef7eb2e8f9f7	61	* Configuration of top level parameters related to ADC *
<>	144:ef7eb2e8f9f7	62	============================================================
<>	144:ef7eb2e8f9f7	63	[..]
<>	144:ef7eb2e8f9f7	64
<>	144:ef7eb2e8f9f7	65	(#) Enable the ADC interface
<>	144:ef7eb2e8f9f7	66	(++) As prerequisite, ADC clock must be configured at RCC top level.
<>	144:ef7eb2e8f9f7	67	Caution: On STM32F0, ADC clock frequency max is 14MHz (refer
<>	144:ef7eb2e8f9f7	68	to device datasheet).
<>	144:ef7eb2e8f9f7	69	Therefore, ADC clock prescaler must be configured in
<>	144:ef7eb2e8f9f7	70	function of ADC clock source frequency to remain below
<>	144:ef7eb2e8f9f7	71	this maximum frequency.
<>	144:ef7eb2e8f9f7	72
<>	144:ef7eb2e8f9f7	73	(++) Two clock settings are mandatory:
<>	144:ef7eb2e8f9f7	74	(+++) ADC clock (core clock, also possibly conversion clock).
<>	144:ef7eb2e8f9f7	75
<>	144:ef7eb2e8f9f7	76	(+++) ADC clock (conversions clock).
<>	144:ef7eb2e8f9f7	77	Two possible clock sources: synchronous clock derived from APB clock
<>	144:ef7eb2e8f9f7	78	or asynchronous clock derived from ADC dedicated HSI RC oscillator
<>	144:ef7eb2e8f9f7	79	14MHz.
<>	144:ef7eb2e8f9f7	80	If asynchronous clock is selected, parameter "HSI14State" must be set either:
<>	144:ef7eb2e8f9f7	81	- to "...HSI14State = RCC_HSI14_ADC_CONTROL" to let the ADC control
<>	144:ef7eb2e8f9f7	82	the HSI14 oscillator enable/disable (if not used to supply the main
<>	144:ef7eb2e8f9f7	83	system clock): feature used if ADC mode LowPowerAutoPowerOff is
<>	144:ef7eb2e8f9f7	84	enabled.
<>	144:ef7eb2e8f9f7	85	- to "...HSI14State = RCC_HSI14_ON" to maintain the HSI14 oscillator
<>	144:ef7eb2e8f9f7	86	always enabled: can be used to supply the main system clock.
<>	144:ef7eb2e8f9f7	87
<>	144:ef7eb2e8f9f7	88	(+++) Example:
<>	144:ef7eb2e8f9f7	89	Into HAL_ADC_MspInit() (recommended code location) or with
<>	144:ef7eb2e8f9f7	90	other device clock parameters configuration:
<>	144:ef7eb2e8f9f7	91	(+++) __HAL_RCC_ADC1_CLK_ENABLE(); (mandatory)
<>	144:ef7eb2e8f9f7	92
<>	144:ef7eb2e8f9f7	93	HI14 enable or let under control of ADC: (optional: if asynchronous clock selected)
<>	144:ef7eb2e8f9f7	94	(+++) RCC_OscInitTypeDef RCC_OscInitStructure;
<>	144:ef7eb2e8f9f7	95	(+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
<>	144:ef7eb2e8f9f7	96	(+++) RCC_OscInitStructure.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT;
<>	144:ef7eb2e8f9f7	97	(+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_ADC_CONTROL;
<>	144:ef7eb2e8f9f7	98	(+++) RCC_OscInitStructure.PLL... (optional if used for system clock)
<>	144:ef7eb2e8f9f7	99	(+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
<>	144:ef7eb2e8f9f7	100
<>	144:ef7eb2e8f9f7	101	(++) ADC clock source and clock prescaler are configured at ADC level with
<>	144:ef7eb2e8f9f7	102	parameter "ClockPrescaler" using function HAL_ADC_Init().
<>	144:ef7eb2e8f9f7	103
<>	144:ef7eb2e8f9f7	104	(#) ADC pins configuration
<>	144:ef7eb2e8f9f7	105	(++) Enable the clock for the ADC GPIOs
<>	144:ef7eb2e8f9f7	106	using macro __HAL_RCC_GPIOx_CLK_ENABLE()
<>	144:ef7eb2e8f9f7	107	(++) Configure these ADC pins in analog mode
<>	144:ef7eb2e8f9f7	108	using function HAL_GPIO_Init()
<>	144:ef7eb2e8f9f7	109
<>	144:ef7eb2e8f9f7	110	(#) Optionally, in case of usage of ADC with interruptions:
<>	144:ef7eb2e8f9f7	111	(++) Configure the NVIC for ADC
<>	144:ef7eb2e8f9f7	112	using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
<>	144:ef7eb2e8f9f7	113	(++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
<>	144:ef7eb2e8f9f7	114	into the function of corresponding ADC interruption vector
<>	144:ef7eb2e8f9f7	115	ADCx_IRQHandler().
<>	144:ef7eb2e8f9f7	116
<>	144:ef7eb2e8f9f7	117	(#) Optionally, in case of usage of DMA:
<>	144:ef7eb2e8f9f7	118	(++) Configure the DMA (DMA channel, mode normal or circular, ...)
<>	144:ef7eb2e8f9f7	119	using function HAL_DMA_Init().
<>	144:ef7eb2e8f9f7	120	(++) Configure the NVIC for DMA
<>	144:ef7eb2e8f9f7	121	using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
<>	144:ef7eb2e8f9f7	122	(++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
<>	144:ef7eb2e8f9f7	123	into the function of corresponding DMA interruption vector
<>	144:ef7eb2e8f9f7	124	DMAx_Channelx_IRQHandler().
<>	144:ef7eb2e8f9f7	125
<>	144:ef7eb2e8f9f7	126	* Configuration of ADC, group regular, channels parameters *
<>	144:ef7eb2e8f9f7	127	================================================================
<>	144:ef7eb2e8f9f7	128	[..]
<>	144:ef7eb2e8f9f7	129
<>	144:ef7eb2e8f9f7	130	(#) Configure the ADC parameters (resolution, data alignment, ...)
<>	144:ef7eb2e8f9f7	131	and regular group parameters (conversion trigger, sequencer, ...)
<>	144:ef7eb2e8f9f7	132	using function HAL_ADC_Init().
<>	144:ef7eb2e8f9f7	133
<>	144:ef7eb2e8f9f7	134	(#) Configure the channels for regular group parameters (channel number,
<>	144:ef7eb2e8f9f7	135	channel rank into sequencer, ..., into regular group)
<>	144:ef7eb2e8f9f7	136	using function HAL_ADC_ConfigChannel().
<>	144:ef7eb2e8f9f7	137
<>	144:ef7eb2e8f9f7	138	(#) Optionally, configure the analog watchdog parameters (channels
<>	144:ef7eb2e8f9f7	139	monitored, thresholds, ...)
<>	144:ef7eb2e8f9f7	140	using function HAL_ADC_AnalogWDGConfig().
<>	144:ef7eb2e8f9f7	141
<>	144:ef7eb2e8f9f7	142	* Execution of ADC conversions *
<>	144:ef7eb2e8f9f7	143	====================================
<>	144:ef7eb2e8f9f7	144	[..]
<>	144:ef7eb2e8f9f7	145
<>	144:ef7eb2e8f9f7	146	(#) Optionally, perform an automatic ADC calibration to improve the
<>	144:ef7eb2e8f9f7	147	conversion accuracy
<>	144:ef7eb2e8f9f7	148	using function HAL_ADCEx_Calibration_Start().
<>	144:ef7eb2e8f9f7	149
<>	144:ef7eb2e8f9f7	150	(#) ADC driver can be used among three modes: polling, interruption,
<>	144:ef7eb2e8f9f7	151	transfer by DMA.
<>	144:ef7eb2e8f9f7	152
<>	144:ef7eb2e8f9f7	153	(++) ADC conversion by polling:
<>	144:ef7eb2e8f9f7	154	(+++) Activate the ADC peripheral and start conversions
<>	144:ef7eb2e8f9f7	155	using function HAL_ADC_Start()
<>	144:ef7eb2e8f9f7	156	(+++) Wait for ADC conversion completion
<>	144:ef7eb2e8f9f7	157	using function HAL_ADC_PollForConversion()
<>	144:ef7eb2e8f9f7	158	(+++) Retrieve conversion results
<>	144:ef7eb2e8f9f7	159	using function HAL_ADC_GetValue()
<>	144:ef7eb2e8f9f7	160	(+++) Stop conversion and disable the ADC peripheral
<>	144:ef7eb2e8f9f7	161	using function HAL_ADC_Stop()
<>	144:ef7eb2e8f9f7	162
<>	144:ef7eb2e8f9f7	163	(++) ADC conversion by interruption:
<>	144:ef7eb2e8f9f7	164	(+++) Activate the ADC peripheral and start conversions
<>	144:ef7eb2e8f9f7	165	using function HAL_ADC_Start_IT()
<>	144:ef7eb2e8f9f7	166	(+++) Wait for ADC conversion completion by call of function
<>	144:ef7eb2e8f9f7	167	HAL_ADC_ConvCpltCallback()
<>	144:ef7eb2e8f9f7	168	(this function must be implemented in user program)
<>	144:ef7eb2e8f9f7	169	(+++) Retrieve conversion results
<>	144:ef7eb2e8f9f7	170	using function HAL_ADC_GetValue()
<>	144:ef7eb2e8f9f7	171	(+++) Stop conversion and disable the ADC peripheral
<>	144:ef7eb2e8f9f7	172	using function HAL_ADC_Stop_IT()
<>	144:ef7eb2e8f9f7	173
<>	144:ef7eb2e8f9f7	174	(++) ADC conversion with transfer by DMA:
<>	144:ef7eb2e8f9f7	175	(+++) Activate the ADC peripheral and start conversions
<>	144:ef7eb2e8f9f7	176	using function HAL_ADC_Start_DMA()
<>	144:ef7eb2e8f9f7	177	(+++) Wait for ADC conversion completion by call of function
<>	144:ef7eb2e8f9f7	178	HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
<>	144:ef7eb2e8f9f7	179	(these functions must be implemented in user program)
<>	144:ef7eb2e8f9f7	180	(+++) Conversion results are automatically transferred by DMA into
<>	144:ef7eb2e8f9f7	181	destination variable address.
<>	144:ef7eb2e8f9f7	182	(+++) Stop conversion and disable the ADC peripheral
<>	144:ef7eb2e8f9f7	183	using function HAL_ADC_Stop_DMA()
<>	144:ef7eb2e8f9f7	184
<>	144:ef7eb2e8f9f7	185	[..]
<>	144:ef7eb2e8f9f7	186
<>	144:ef7eb2e8f9f7	187	(@) Callback functions must be implemented in user program:
<>	144:ef7eb2e8f9f7	188	(+@) HAL_ADC_ErrorCallback()
<>	144:ef7eb2e8f9f7	189	(+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
<>	144:ef7eb2e8f9f7	190	(+@) HAL_ADC_ConvCpltCallback()
<>	144:ef7eb2e8f9f7	191	(+@) HAL_ADC_ConvHalfCpltCallback
<>	144:ef7eb2e8f9f7	192
<>	144:ef7eb2e8f9f7	193	* Deinitialization of ADC *
<>	144:ef7eb2e8f9f7	194	============================================================
<>	144:ef7eb2e8f9f7	195	[..]
<>	144:ef7eb2e8f9f7	196
<>	144:ef7eb2e8f9f7	197	(#) Disable the ADC interface
<>	144:ef7eb2e8f9f7	198	(++) ADC clock can be hard reset and disabled at RCC top level.
<>	144:ef7eb2e8f9f7	199	(++) Hard reset of ADC peripherals
<>	144:ef7eb2e8f9f7	200	using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
<>	144:ef7eb2e8f9f7	201	(++) ADC clock disable
<>	144:ef7eb2e8f9f7	202	using the equivalent macro/functions as configuration step.
<>	144:ef7eb2e8f9f7	203	(+++) Example:
<>	144:ef7eb2e8f9f7	204	Into HAL_ADC_MspDeInit() (recommended code location) or with
<>	144:ef7eb2e8f9f7	205	other device clock parameters configuration:
<>	144:ef7eb2e8f9f7	206	(+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
<>	144:ef7eb2e8f9f7	207	(+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
<>	144:ef7eb2e8f9f7	208	(+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
<>	144:ef7eb2e8f9f7	209
<>	144:ef7eb2e8f9f7	210	(#) ADC pins configuration
<>	144:ef7eb2e8f9f7	211	(++) Disable the clock for the ADC GPIOs
<>	144:ef7eb2e8f9f7	212	using macro __HAL_RCC_GPIOx_CLK_DISABLE()
<>	144:ef7eb2e8f9f7	213
<>	144:ef7eb2e8f9f7	214	(#) Optionally, in case of usage of ADC with interruptions:
<>	144:ef7eb2e8f9f7	215	(++) Disable the NVIC for ADC
<>	144:ef7eb2e8f9f7	216	using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
<>	144:ef7eb2e8f9f7	217
<>	144:ef7eb2e8f9f7	218	(#) Optionally, in case of usage of DMA:
<>	144:ef7eb2e8f9f7	219	(++) Deinitialize the DMA
<>	144:ef7eb2e8f9f7	220	using function HAL_DMA_Init().
<>	144:ef7eb2e8f9f7	221	(++) Disable the NVIC for DMA
<>	144:ef7eb2e8f9f7	222	using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
<>	144:ef7eb2e8f9f7	223
<>	144:ef7eb2e8f9f7	224	[..]
<>	144:ef7eb2e8f9f7	225
<>	144:ef7eb2e8f9f7	226	@endverbatim
<>	144:ef7eb2e8f9f7	227	******************************************************************************
<>	144:ef7eb2e8f9f7	228	* @attention
<>	144:ef7eb2e8f9f7	229	*
<>	144:ef7eb2e8f9f7	230	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	231	*
<>	144:ef7eb2e8f9f7	232	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	233	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	234	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	235	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	236	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	237	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	238	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	239	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	240	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	241	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	242	*
<>	144:ef7eb2e8f9f7	243	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	244	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	245	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	246	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	247	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	248	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	249	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	250	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	251	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	252	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	253	*
<>	144:ef7eb2e8f9f7	254	******************************************************************************
<>	144:ef7eb2e8f9f7	255	*/
<>	144:ef7eb2e8f9f7	256
<>	144:ef7eb2e8f9f7	257	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	258	#include "stm32f0xx_hal.h"
<>	144:ef7eb2e8f9f7	259
<>	144:ef7eb2e8f9f7	260	/** @addtogroup STM32F0xx_HAL_Driver
<>	144:ef7eb2e8f9f7	261	* @{
<>	144:ef7eb2e8f9f7	262	*/
<>	144:ef7eb2e8f9f7	263
<>	144:ef7eb2e8f9f7	264	/** @defgroup ADC ADC
<>	144:ef7eb2e8f9f7	265	* @brief ADC HAL module driver
<>	144:ef7eb2e8f9f7	266	* @{
<>	144:ef7eb2e8f9f7	267	*/
<>	144:ef7eb2e8f9f7	268
<>	144:ef7eb2e8f9f7	269	#ifdef HAL_ADC_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	270
<>	144:ef7eb2e8f9f7	271	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	272	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	273	/** @defgroup ADC_Private_Constants ADC Private Constants
<>	144:ef7eb2e8f9f7	274	* @{
<>	144:ef7eb2e8f9f7	275	*/
<>	144:ef7eb2e8f9f7	276
<>	144:ef7eb2e8f9f7	277	/* Fixed timeout values for ADC calibration, enable settling time, disable */
<>	144:ef7eb2e8f9f7	278	/* settling time. */
<>	144:ef7eb2e8f9f7	279	/* Values defined to be higher than worst cases: low clock frequency, */
<>	144:ef7eb2e8f9f7	280	/* maximum prescaler. */
<>	144:ef7eb2e8f9f7	281	/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
<>	144:ef7eb2e8f9f7	282	/* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */
<>	144:ef7eb2e8f9f7	283	/* Unit: ms */
<>	156:95d6b41a828b	284	#define ADC_ENABLE_TIMEOUT ( 2U)
<>	156:95d6b41a828b	285	#define ADC_DISABLE_TIMEOUT ( 2U)
<>	156:95d6b41a828b	286	#define ADC_STOP_CONVERSION_TIMEOUT ( 2U)
<>	144:ef7eb2e8f9f7	287
<>	144:ef7eb2e8f9f7	288	/* Delay for ADC stabilization time. */
<>	144:ef7eb2e8f9f7	289	/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
<>	144:ef7eb2e8f9f7	290	/* Unit: us */
<>	156:95d6b41a828b	291	#define ADC_STAB_DELAY_US ( 1U)
<>	144:ef7eb2e8f9f7	292
<>	144:ef7eb2e8f9f7	293	/* Delay for temperature sensor stabilization time. */
<>	144:ef7eb2e8f9f7	294	/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
<>	144:ef7eb2e8f9f7	295	/* Unit: us */
<>	156:95d6b41a828b	296	#define ADC_TEMPSENSOR_DELAY_US ( 10U)
<>	144:ef7eb2e8f9f7	297
<>	144:ef7eb2e8f9f7	298	/**
<>	144:ef7eb2e8f9f7	299	* @}
<>	144:ef7eb2e8f9f7	300	*/
<>	144:ef7eb2e8f9f7	301
<>	144:ef7eb2e8f9f7	302	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	303	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	304	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	305	/** @defgroup ADC_Private_Functions ADC Private Functions
<>	144:ef7eb2e8f9f7	306	* @{
<>	144:ef7eb2e8f9f7	307	*/
<>	144:ef7eb2e8f9f7	308	static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	309	static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	310	static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	311	static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	312	static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	313	static void ADC_DMAError(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	314	/**
<>	144:ef7eb2e8f9f7	315	* @}
<>	144:ef7eb2e8f9f7	316	*/
<>	144:ef7eb2e8f9f7	317
<>	144:ef7eb2e8f9f7	318	/* Exported functions ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	319
<>	144:ef7eb2e8f9f7	320	/** @defgroup ADC_Exported_Functions ADC Exported Functions
<>	144:ef7eb2e8f9f7	321	* @{
<>	144:ef7eb2e8f9f7	322	*/
<>	144:ef7eb2e8f9f7	323
<>	144:ef7eb2e8f9f7	324	/** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions
<>	144:ef7eb2e8f9f7	325	* @brief Initialization and Configuration functions
<>	144:ef7eb2e8f9f7	326	*
<>	144:ef7eb2e8f9f7	327	@verbatim
<>	144:ef7eb2e8f9f7	328	===============================================================================
<>	144:ef7eb2e8f9f7	329	##### Initialization and de-initialization functions #####
<>	144:ef7eb2e8f9f7	330	===============================================================================
<>	144:ef7eb2e8f9f7	331	[..] This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	332	(+) Initialize and configure the ADC.
<>	144:ef7eb2e8f9f7	333	(+) De-initialize the ADC
<>	144:ef7eb2e8f9f7	334	@endverbatim
<>	144:ef7eb2e8f9f7	335	* @{
<>	144:ef7eb2e8f9f7	336	*/
<>	144:ef7eb2e8f9f7	337
<>	144:ef7eb2e8f9f7	338	/**
<>	144:ef7eb2e8f9f7	339	* @brief Initializes the ADC peripheral and regular group according to
<>	144:ef7eb2e8f9f7	340	* parameters specified in structure "ADC_InitTypeDef".
<>	144:ef7eb2e8f9f7	341	* @note As prerequisite, ADC clock must be configured at RCC top level
<>	144:ef7eb2e8f9f7	342	* depending on both possible clock sources: APB clock of HSI clock.
<>	144:ef7eb2e8f9f7	343	* See commented example code below that can be copied and uncommented
<>	144:ef7eb2e8f9f7	344	* into HAL_ADC_MspInit().
<>	144:ef7eb2e8f9f7	345	* @note Possibility to update parameters on the fly:
<>	144:ef7eb2e8f9f7	346	* This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
<>	144:ef7eb2e8f9f7	347	* coming from ADC state reset. Following calls to this function can
<>	144:ef7eb2e8f9f7	348	* be used to reconfigure some parameters of ADC_InitTypeDef
<>	144:ef7eb2e8f9f7	349	* structure on the fly, without modifying MSP configuration. If ADC
<>	144:ef7eb2e8f9f7	350	* MSP has to be modified again, HAL_ADC_DeInit() must be called
<>	144:ef7eb2e8f9f7	351	* before HAL_ADC_Init().
<>	144:ef7eb2e8f9f7	352	* The setting of these parameters is conditioned to ADC state.
<>	144:ef7eb2e8f9f7	353	* For parameters constraints, see comments of structure
<>	144:ef7eb2e8f9f7	354	* "ADC_InitTypeDef".
<>	144:ef7eb2e8f9f7	355	* @note This function configures the ADC within 2 scopes: scope of entire
<>	144:ef7eb2e8f9f7	356	* ADC and scope of regular group. For parameters details, see comments
<>	144:ef7eb2e8f9f7	357	* of structure "ADC_InitTypeDef".
<>	144:ef7eb2e8f9f7	358	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	359	* @retval HAL status
<>	144:ef7eb2e8f9f7	360	*/
<>	144:ef7eb2e8f9f7	361	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	362	{
<>	144:ef7eb2e8f9f7	363	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<>	156:95d6b41a828b	364	uint32_t tmpCFGR1 = 0U;
<>	144:ef7eb2e8f9f7	365
<>	144:ef7eb2e8f9f7	366	/* Check ADC handle */
<>	144:ef7eb2e8f9f7	367	if(hadc == NULL)
<>	144:ef7eb2e8f9f7	368	{
<>	144:ef7eb2e8f9f7	369	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	370	}
<>	144:ef7eb2e8f9f7	371
<>	144:ef7eb2e8f9f7	372	/* Check the parameters */
<>	144:ef7eb2e8f9f7	373	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	374	assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
<>	144:ef7eb2e8f9f7	375	assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
<>	144:ef7eb2e8f9f7	376	assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
<>	144:ef7eb2e8f9f7	377	assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
<>	144:ef7eb2e8f9f7	378	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
<>	144:ef7eb2e8f9f7	379	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
<>	144:ef7eb2e8f9f7	380	assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
<>	144:ef7eb2e8f9f7	381	assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
<>	144:ef7eb2e8f9f7	382	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
<>	144:ef7eb2e8f9f7	383	assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
<>	144:ef7eb2e8f9f7	384	assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
<>	144:ef7eb2e8f9f7	385	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
<>	144:ef7eb2e8f9f7	386	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff));
<>	144:ef7eb2e8f9f7	387
<>	144:ef7eb2e8f9f7	388	/* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
<>	144:ef7eb2e8f9f7	389	/* at RCC top level depending on both possible clock sources: */
<>	144:ef7eb2e8f9f7	390	/* APB clock or HSI clock. */
<>	144:ef7eb2e8f9f7	391	/* Refer to header of this file for more details on clock enabling procedure*/
<>	144:ef7eb2e8f9f7	392
<>	144:ef7eb2e8f9f7	393	/* Actions performed only if ADC is coming from state reset: */
<>	144:ef7eb2e8f9f7	394	/* - Initialization of ADC MSP */
<>	144:ef7eb2e8f9f7	395	/* - ADC voltage regulator enable */
<>	144:ef7eb2e8f9f7	396	if (hadc->State == HAL_ADC_STATE_RESET)
<>	144:ef7eb2e8f9f7	397	{
<>	144:ef7eb2e8f9f7	398	/* Initialize ADC error code */
<>	144:ef7eb2e8f9f7	399	ADC_CLEAR_ERRORCODE(hadc);
<>	144:ef7eb2e8f9f7	400
<>	144:ef7eb2e8f9f7	401	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	402	hadc->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	403
<>	144:ef7eb2e8f9f7	404	/* Init the low level hardware */
<>	144:ef7eb2e8f9f7	405	HAL_ADC_MspInit(hadc);
<>	144:ef7eb2e8f9f7	406	}
<>	144:ef7eb2e8f9f7	407
<>	144:ef7eb2e8f9f7	408	/* Configuration of ADC parameters if previous preliminary actions are */
<>	144:ef7eb2e8f9f7	409	/* correctly completed. */
<>	144:ef7eb2e8f9f7	410	/* and if there is no conversion on going on regular group (ADC can be */
<>	144:ef7eb2e8f9f7	411	/* enabled anyway, in case of call of this function to update a parameter */
<>	144:ef7eb2e8f9f7	412	/* on the fly). */
<>	144:ef7eb2e8f9f7	413	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
<>	144:ef7eb2e8f9f7	414	(tmp_hal_status == HAL_OK) &&
<>	144:ef7eb2e8f9f7	415	(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
<>	144:ef7eb2e8f9f7	416	{
<>	144:ef7eb2e8f9f7	417	/* Set ADC state */
<>	144:ef7eb2e8f9f7	418	ADC_STATE_CLR_SET(hadc->State,
<>	144:ef7eb2e8f9f7	419	HAL_ADC_STATE_REG_BUSY,
<>	144:ef7eb2e8f9f7	420	HAL_ADC_STATE_BUSY_INTERNAL);
<>	144:ef7eb2e8f9f7	421
<>	144:ef7eb2e8f9f7	422	/* Parameters update conditioned to ADC state: */
<>	144:ef7eb2e8f9f7	423	/* Parameters that can be updated only when ADC is disabled: */
<>	144:ef7eb2e8f9f7	424	/* - ADC clock mode */
<>	144:ef7eb2e8f9f7	425	/* - ADC clock prescaler */
<>	144:ef7eb2e8f9f7	426	/* - ADC resolution */
<>	144:ef7eb2e8f9f7	427	if (ADC_IS_ENABLE(hadc) == RESET)
<>	144:ef7eb2e8f9f7	428	{
<>	144:ef7eb2e8f9f7	429	/* Some parameters of this register are not reset, since they are set */
<>	144:ef7eb2e8f9f7	430	/* by other functions and must be kept in case of usage of this */
<>	144:ef7eb2e8f9f7	431	/* function on the fly (update of a parameter of ADC_InitTypeDef */
<>	144:ef7eb2e8f9f7	432	/* without needing to reconfigure all other ADC groups/channels */
<>	144:ef7eb2e8f9f7	433	/* parameters): */
<>	144:ef7eb2e8f9f7	434	/* - internal measurement paths: Vbat, temperature sensor, Vref */
<>	144:ef7eb2e8f9f7	435	/* (set into HAL_ADC_ConfigChannel() ) */
<>	144:ef7eb2e8f9f7	436
<>	144:ef7eb2e8f9f7	437	/* Configuration of ADC resolution */
<>	144:ef7eb2e8f9f7	438	MODIFY_REG(hadc->Instance->CFGR1,
<>	144:ef7eb2e8f9f7	439	ADC_CFGR1_RES ,
<>	144:ef7eb2e8f9f7	440	hadc->Init.Resolution );
<>	144:ef7eb2e8f9f7	441
<>	144:ef7eb2e8f9f7	442	/* Configuration of ADC clock mode: clock source AHB or HSI with */
<>	144:ef7eb2e8f9f7	443	/* selectable prescaler */
<>	144:ef7eb2e8f9f7	444	MODIFY_REG(hadc->Instance->CFGR2 ,
<>	144:ef7eb2e8f9f7	445	ADC_CFGR2_CKMODE ,
<>	144:ef7eb2e8f9f7	446	hadc->Init.ClockPrescaler );
<>	144:ef7eb2e8f9f7	447	}
<>	144:ef7eb2e8f9f7	448
<>	144:ef7eb2e8f9f7	449	/* Configuration of ADC: */
<>	144:ef7eb2e8f9f7	450	/* - discontinuous mode */
<>	144:ef7eb2e8f9f7	451	/* - LowPowerAutoWait mode */
<>	144:ef7eb2e8f9f7	452	/* - LowPowerAutoPowerOff mode */
<>	144:ef7eb2e8f9f7	453	/* - continuous conversion mode */
<>	144:ef7eb2e8f9f7	454	/* - overrun */
<>	144:ef7eb2e8f9f7	455	/* - external trigger to start conversion */
<>	144:ef7eb2e8f9f7	456	/* - external trigger polarity */
<>	144:ef7eb2e8f9f7	457	/* - data alignment */
<>	144:ef7eb2e8f9f7	458	/* - resolution */
<>	144:ef7eb2e8f9f7	459	/* - scan direction */
<>	144:ef7eb2e8f9f7	460	/* - DMA continuous request */
<>	144:ef7eb2e8f9f7	461	hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN \|
<>	144:ef7eb2e8f9f7	462	ADC_CFGR1_AUTOFF \|
<>	144:ef7eb2e8f9f7	463	ADC_CFGR1_AUTDLY \|
<>	144:ef7eb2e8f9f7	464	ADC_CFGR1_CONT \|
<>	144:ef7eb2e8f9f7	465	ADC_CFGR1_OVRMOD \|
<>	144:ef7eb2e8f9f7	466	ADC_CFGR1_EXTSEL \|
<>	144:ef7eb2e8f9f7	467	ADC_CFGR1_EXTEN \|
<>	144:ef7eb2e8f9f7	468	ADC_CFGR1_ALIGN \|
<>	144:ef7eb2e8f9f7	469	ADC_CFGR1_SCANDIR \|
<>	144:ef7eb2e8f9f7	470	ADC_CFGR1_DMACFG );
<>	144:ef7eb2e8f9f7	471
<>	144:ef7eb2e8f9f7	472	tmpCFGR1 \|= (ADC_CFGR1_AUTOWAIT(hadc->Init.LowPowerAutoWait) \|
<>	144:ef7eb2e8f9f7	473	ADC_CFGR1_AUTOOFF(hadc->Init.LowPowerAutoPowerOff) \|
<>	144:ef7eb2e8f9f7	474	ADC_CFGR1_CONTINUOUS(hadc->Init.ContinuousConvMode) \|
<>	144:ef7eb2e8f9f7	475	ADC_CFGR1_OVERRUN(hadc->Init.Overrun) \|
<>	144:ef7eb2e8f9f7	476	hadc->Init.DataAlign \|
<>	144:ef7eb2e8f9f7	477	ADC_SCANDIR(hadc->Init.ScanConvMode) \|
<>	144:ef7eb2e8f9f7	478	ADC_CFGR1_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
<>	144:ef7eb2e8f9f7	479
<>	144:ef7eb2e8f9f7	480	/* Enable discontinuous mode only if continuous mode is disabled */
<>	144:ef7eb2e8f9f7	481	if (hadc->Init.DiscontinuousConvMode == ENABLE)
<>	144:ef7eb2e8f9f7	482	{
<>	144:ef7eb2e8f9f7	483	if (hadc->Init.ContinuousConvMode == DISABLE)
<>	144:ef7eb2e8f9f7	484	{
<>	144:ef7eb2e8f9f7	485	/* Enable the selected ADC group regular discontinuous mode */
<>	144:ef7eb2e8f9f7	486	tmpCFGR1 \|= ADC_CFGR1_DISCEN;
<>	144:ef7eb2e8f9f7	487	}
<>	144:ef7eb2e8f9f7	488	else
<>	144:ef7eb2e8f9f7	489	{
<>	144:ef7eb2e8f9f7	490	/* ADC regular group discontinuous was intended to be enabled, */
<>	144:ef7eb2e8f9f7	491	/* but ADC regular group modes continuous and sequencer discontinuous */
<>	144:ef7eb2e8f9f7	492	/* cannot be enabled simultaneously. */
<>	144:ef7eb2e8f9f7	493
<>	144:ef7eb2e8f9f7	494	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	495	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<>	144:ef7eb2e8f9f7	496
<>	144:ef7eb2e8f9f7	497	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	498	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	499	}
<>	144:ef7eb2e8f9f7	500	}
<>	144:ef7eb2e8f9f7	501
<>	144:ef7eb2e8f9f7	502	/* Enable external trigger if trigger selection is different of software */
<>	144:ef7eb2e8f9f7	503	/* start. */
<>	144:ef7eb2e8f9f7	504	/* Note: This configuration keeps the hardware feature of parameter */
<>	144:ef7eb2e8f9f7	505	/* ExternalTrigConvEdge "trigger edge none" equivalent to */
<>	144:ef7eb2e8f9f7	506	/* software start. */
<>	144:ef7eb2e8f9f7	507	if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
<>	144:ef7eb2e8f9f7	508	{
<>	144:ef7eb2e8f9f7	509	tmpCFGR1 \|= ( hadc->Init.ExternalTrigConv \|
<>	144:ef7eb2e8f9f7	510	hadc->Init.ExternalTrigConvEdge );
<>	144:ef7eb2e8f9f7	511	}
<>	144:ef7eb2e8f9f7	512
<>	144:ef7eb2e8f9f7	513	/* Update ADC configuration register with previous settings */
<>	144:ef7eb2e8f9f7	514	hadc->Instance->CFGR1 \|= tmpCFGR1;
<>	144:ef7eb2e8f9f7	515
<>	144:ef7eb2e8f9f7	516	/* Channel sampling time configuration */
<>	144:ef7eb2e8f9f7	517	/* Management of parameters "SamplingTimeCommon" and "SamplingTime" */
<>	144:ef7eb2e8f9f7	518	/* (obsolete): sampling time set in this function if parameter */
<>	144:ef7eb2e8f9f7	519	/* "SamplingTimeCommon" has been set to a valid sampling time. */
<>	144:ef7eb2e8f9f7	520	/* Otherwise, sampling time is set into ADC channel initialization */
<>	144:ef7eb2e8f9f7	521	/* structure with parameter "SamplingTime" (obsolete). */
<>	144:ef7eb2e8f9f7	522	if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
<>	144:ef7eb2e8f9f7	523	{
<>	144:ef7eb2e8f9f7	524	/* Channel sampling time configuration */
<>	144:ef7eb2e8f9f7	525	/* Clear the old sample time */
<>	144:ef7eb2e8f9f7	526	hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
<>	144:ef7eb2e8f9f7	527
<>	144:ef7eb2e8f9f7	528	/* Set the new sample time */
<>	144:ef7eb2e8f9f7	529	hadc->Instance->SMPR \|= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon);
<>	144:ef7eb2e8f9f7	530	}
<>	144:ef7eb2e8f9f7	531
<>	144:ef7eb2e8f9f7	532	/* Check back that ADC registers have effectively been configured to */
<>	144:ef7eb2e8f9f7	533	/* ensure of no potential problem of ADC core IP clocking. */
<>	144:ef7eb2e8f9f7	534	/* Check through register CFGR1 (excluding analog watchdog configuration: */
<>	144:ef7eb2e8f9f7	535	/* set into separate dedicated function, and bits of ADC resolution set */
<>	144:ef7eb2e8f9f7	536	/* out of temporary variable 'tmpCFGR1'). */
<>	144:ef7eb2e8f9f7	537	if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL \| ADC_CFGR1_RES))
<>	144:ef7eb2e8f9f7	538	== tmpCFGR1)
<>	144:ef7eb2e8f9f7	539	{
<>	144:ef7eb2e8f9f7	540	/* Set ADC error code to none */
<>	144:ef7eb2e8f9f7	541	ADC_CLEAR_ERRORCODE(hadc);
<>	144:ef7eb2e8f9f7	542
<>	144:ef7eb2e8f9f7	543	/* Set the ADC state */
<>	144:ef7eb2e8f9f7	544	ADC_STATE_CLR_SET(hadc->State,
<>	144:ef7eb2e8f9f7	545	HAL_ADC_STATE_BUSY_INTERNAL,
<>	144:ef7eb2e8f9f7	546	HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	547	}
<>	144:ef7eb2e8f9f7	548	else
<>	144:ef7eb2e8f9f7	549	{
<>	144:ef7eb2e8f9f7	550	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	551	ADC_STATE_CLR_SET(hadc->State,
<>	144:ef7eb2e8f9f7	552	HAL_ADC_STATE_BUSY_INTERNAL,
<>	144:ef7eb2e8f9f7	553	HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	554
<>	144:ef7eb2e8f9f7	555	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	556	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	557
<>	144:ef7eb2e8f9f7	558	tmp_hal_status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	559	}
<>	144:ef7eb2e8f9f7	560
<>	144:ef7eb2e8f9f7	561	}
<>	144:ef7eb2e8f9f7	562	else
<>	144:ef7eb2e8f9f7	563	{
<>	144:ef7eb2e8f9f7	564	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	565	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	566
<>	144:ef7eb2e8f9f7	567	tmp_hal_status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	568	}
<>	144:ef7eb2e8f9f7	569
<>	144:ef7eb2e8f9f7	570	/* Return function status */
<>	144:ef7eb2e8f9f7	571	return tmp_hal_status;
<>	144:ef7eb2e8f9f7	572	}
<>	144:ef7eb2e8f9f7	573
<>	144:ef7eb2e8f9f7	574
<>	144:ef7eb2e8f9f7	575	/**
<>	144:ef7eb2e8f9f7	576	* @brief Deinitialize the ADC peripheral registers to their default reset
<>	144:ef7eb2e8f9f7	577	* values, with deinitialization of the ADC MSP.
<>	144:ef7eb2e8f9f7	578	* @note For devices with several ADCs: reset of ADC common registers is done
<>	144:ef7eb2e8f9f7	579	* only if all ADCs sharing the same common group are disabled.
<>	144:ef7eb2e8f9f7	580	* If this is not the case, reset of these common parameters reset is
<>	144:ef7eb2e8f9f7	581	* bypassed without error reporting: it can be the intended behaviour in
<>	144:ef7eb2e8f9f7	582	* case of reset of a single ADC while the other ADCs sharing the same
<>	144:ef7eb2e8f9f7	583	* common group is still running.
<>	144:ef7eb2e8f9f7	584	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	585	* @retval HAL status
<>	144:ef7eb2e8f9f7	586	*/
<>	144:ef7eb2e8f9f7	587	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	588	{
<>	144:ef7eb2e8f9f7	589	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<>	144:ef7eb2e8f9f7	590
<>	144:ef7eb2e8f9f7	591	/* Check ADC handle */
<>	144:ef7eb2e8f9f7	592	if(hadc == NULL)
<>	144:ef7eb2e8f9f7	593	{
<>	144:ef7eb2e8f9f7	594	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	595	}
<>	144:ef7eb2e8f9f7	596
<>	144:ef7eb2e8f9f7	597	/* Check the parameters */
<>	144:ef7eb2e8f9f7	598	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	599
<>	144:ef7eb2e8f9f7	600	/* Set ADC state */
<>	144:ef7eb2e8f9f7	601	SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
<>	144:ef7eb2e8f9f7	602
<>	144:ef7eb2e8f9f7	603	/* Stop potential conversion on going, on regular group */
<>	144:ef7eb2e8f9f7	604	tmp_hal_status = ADC_ConversionStop(hadc);
<>	144:ef7eb2e8f9f7	605
<>	144:ef7eb2e8f9f7	606	/* Disable ADC peripheral if conversions are effectively stopped */
<>	144:ef7eb2e8f9f7	607	if (tmp_hal_status == HAL_OK)
<>	144:ef7eb2e8f9f7	608	{
<>	144:ef7eb2e8f9f7	609	/* Disable the ADC peripheral */
<>	144:ef7eb2e8f9f7	610	tmp_hal_status = ADC_Disable(hadc);
<>	144:ef7eb2e8f9f7	611
<>	144:ef7eb2e8f9f7	612	/* Check if ADC is effectively disabled */
<>	144:ef7eb2e8f9f7	613	if (tmp_hal_status != HAL_ERROR)
<>	144:ef7eb2e8f9f7	614	{
<>	144:ef7eb2e8f9f7	615	/* Change ADC state */
<>	144:ef7eb2e8f9f7	616	hadc->State = HAL_ADC_STATE_READY;
<>	144:ef7eb2e8f9f7	617	}
<>	144:ef7eb2e8f9f7	618	}
<>	144:ef7eb2e8f9f7	619
<>	144:ef7eb2e8f9f7	620
<>	144:ef7eb2e8f9f7	621	/* Configuration of ADC parameters if previous preliminary actions are */
<>	144:ef7eb2e8f9f7	622	/* correctly completed. */
<>	144:ef7eb2e8f9f7	623	if (tmp_hal_status != HAL_ERROR)
<>	144:ef7eb2e8f9f7	624	{
<>	144:ef7eb2e8f9f7	625
<>	144:ef7eb2e8f9f7	626	/* ========== Reset ADC registers ========== */
<>	144:ef7eb2e8f9f7	627	/* Reset register IER */
<>	144:ef7eb2e8f9f7	628	__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD \| ADC_IT_OVR \|
<>	144:ef7eb2e8f9f7	629	ADC_IT_EOS \| ADC_IT_EOC \|
<>	144:ef7eb2e8f9f7	630	ADC_IT_EOSMP \| ADC_IT_RDY ) );
<>	144:ef7eb2e8f9f7	631
<>	144:ef7eb2e8f9f7	632	/* Reset register ISR */
<>	144:ef7eb2e8f9f7	633	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD \| ADC_FLAG_OVR \|
<>	144:ef7eb2e8f9f7	634	ADC_FLAG_EOS \| ADC_FLAG_EOC \|
<>	144:ef7eb2e8f9f7	635	ADC_FLAG_EOSMP \| ADC_FLAG_RDY ) );
<>	144:ef7eb2e8f9f7	636
<>	144:ef7eb2e8f9f7	637	/* Reset register CR */
<>	144:ef7eb2e8f9f7	638	/* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
<>	144:ef7eb2e8f9f7	639	/* "read-set": no direct reset applicable. */
<>	144:ef7eb2e8f9f7	640
<>	144:ef7eb2e8f9f7	641	/* Reset register CFGR1 */
<>	144:ef7eb2e8f9f7	642	hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWDCH \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL \| ADC_CFGR1_DISCEN \|
<>	144:ef7eb2e8f9f7	643	ADC_CFGR1_AUTOFF \| ADC_CFGR1_WAIT \| ADC_CFGR1_CONT \| ADC_CFGR1_OVRMOD \|
<>	144:ef7eb2e8f9f7	644	ADC_CFGR1_EXTEN \| ADC_CFGR1_EXTSEL \| ADC_CFGR1_ALIGN \| ADC_CFGR1_RES \|
<>	144:ef7eb2e8f9f7	645	ADC_CFGR1_SCANDIR \| ADC_CFGR1_DMACFG \| ADC_CFGR1_DMAEN );
<>	144:ef7eb2e8f9f7	646
<>	144:ef7eb2e8f9f7	647	/* Reset register CFGR2 */
<>	144:ef7eb2e8f9f7	648	/* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
<>	144:ef7eb2e8f9f7	649	/* already done above. */
<>	144:ef7eb2e8f9f7	650	hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE;
<>	144:ef7eb2e8f9f7	651
<>	144:ef7eb2e8f9f7	652	/* Reset register SMPR */
<>	144:ef7eb2e8f9f7	653	hadc->Instance->SMPR &= ~ADC_SMPR_SMP;
<>	144:ef7eb2e8f9f7	654
<>	144:ef7eb2e8f9f7	655	/* Reset register TR1 */
<>	144:ef7eb2e8f9f7	656	hadc->Instance->TR &= ~(ADC_TR_HT \| ADC_TR_LT);
<>	144:ef7eb2e8f9f7	657
<>	144:ef7eb2e8f9f7	658	/* Reset register CHSELR */
<>	144:ef7eb2e8f9f7	659	hadc->Instance->CHSELR &= ~(ADC_CHSELR_CHSEL18 \| ADC_CHSELR_CHSEL17 \| ADC_CHSELR_CHSEL16 \|
<>	144:ef7eb2e8f9f7	660	ADC_CHSELR_CHSEL15 \| ADC_CHSELR_CHSEL14 \| ADC_CHSELR_CHSEL13 \| ADC_CHSELR_CHSEL12 \|
<>	144:ef7eb2e8f9f7	661	ADC_CHSELR_CHSEL11 \| ADC_CHSELR_CHSEL10 \| ADC_CHSELR_CHSEL9 \| ADC_CHSELR_CHSEL8 \|
<>	144:ef7eb2e8f9f7	662	ADC_CHSELR_CHSEL7 \| ADC_CHSELR_CHSEL6 \| ADC_CHSELR_CHSEL5 \| ADC_CHSELR_CHSEL4 \|
<>	144:ef7eb2e8f9f7	663	ADC_CHSELR_CHSEL3 \| ADC_CHSELR_CHSEL2 \| ADC_CHSELR_CHSEL1 \| ADC_CHSELR_CHSEL0 );
<>	144:ef7eb2e8f9f7	664
<>	144:ef7eb2e8f9f7	665	/* Reset register DR */
<>	144:ef7eb2e8f9f7	666	/* bits in access mode read only, no direct reset applicable*/
<>	144:ef7eb2e8f9f7	667
<>	144:ef7eb2e8f9f7	668	/* Reset register CCR */
<>	144:ef7eb2e8f9f7	669	ADC->CCR &= ~(ADC_CCR_ALL);
<>	144:ef7eb2e8f9f7	670
<>	144:ef7eb2e8f9f7	671	/* ========== Hard reset ADC peripheral ========== */
<>	144:ef7eb2e8f9f7	672	/* Performs a global reset of the entire ADC peripheral: ADC state is */
<>	144:ef7eb2e8f9f7	673	/* forced to a similar state after device power-on. */
<>	144:ef7eb2e8f9f7	674	/* If needed, copy-paste and uncomment the following reset code into */
<>	144:ef7eb2e8f9f7	675	/* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
<>	144:ef7eb2e8f9f7	676	/* */
<>	144:ef7eb2e8f9f7	677	/* __HAL_RCC_ADC1_FORCE_RESET() */
<>	144:ef7eb2e8f9f7	678	/* __HAL_RCC_ADC1_RELEASE_RESET() */
<>	144:ef7eb2e8f9f7	679
<>	144:ef7eb2e8f9f7	680	/* DeInit the low level hardware */
<>	144:ef7eb2e8f9f7	681	HAL_ADC_MspDeInit(hadc);
<>	144:ef7eb2e8f9f7	682
<>	144:ef7eb2e8f9f7	683	/* Set ADC error code to none */
<>	144:ef7eb2e8f9f7	684	ADC_CLEAR_ERRORCODE(hadc);
<>	144:ef7eb2e8f9f7	685
<>	144:ef7eb2e8f9f7	686	/* Set ADC state */
<>	144:ef7eb2e8f9f7	687	hadc->State = HAL_ADC_STATE_RESET;
<>	144:ef7eb2e8f9f7	688	}
<>	144:ef7eb2e8f9f7	689
<>	144:ef7eb2e8f9f7	690	/* Process unlocked */
<>	144:ef7eb2e8f9f7	691	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	692
<>	144:ef7eb2e8f9f7	693	/* Return function status */
<>	144:ef7eb2e8f9f7	694	return tmp_hal_status;
<>	144:ef7eb2e8f9f7	695	}
<>	144:ef7eb2e8f9f7	696
<>	144:ef7eb2e8f9f7	697
<>	144:ef7eb2e8f9f7	698	/**
<>	144:ef7eb2e8f9f7	699	* @brief Initializes the ADC MSP.
<>	144:ef7eb2e8f9f7	700	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	701	* @retval None
<>	144:ef7eb2e8f9f7	702	*/
<>	144:ef7eb2e8f9f7	703	__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	704	{
<>	144:ef7eb2e8f9f7	705	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	706	UNUSED(hadc);
<>	144:ef7eb2e8f9f7	707
<>	144:ef7eb2e8f9f7	708	/* NOTE : This function should not be modified. When the callback is needed,
<>	144:ef7eb2e8f9f7	709	function HAL_ADC_MspInit must be implemented in the user file.
<>	144:ef7eb2e8f9f7	710	*/
<>	144:ef7eb2e8f9f7	711	}
<>	144:ef7eb2e8f9f7	712
<>	144:ef7eb2e8f9f7	713	/**
<>	144:ef7eb2e8f9f7	714	* @brief DeInitializes the ADC MSP.
<>	144:ef7eb2e8f9f7	715	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	716	* @retval None
<>	144:ef7eb2e8f9f7	717	*/
<>	144:ef7eb2e8f9f7	718	__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	719	{
<>	144:ef7eb2e8f9f7	720	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	721	UNUSED(hadc);
<>	144:ef7eb2e8f9f7	722
<>	144:ef7eb2e8f9f7	723	/* NOTE : This function should not be modified. When the callback is needed,
<>	144:ef7eb2e8f9f7	724	function HAL_ADC_MspDeInit must be implemented in the user file.
<>	144:ef7eb2e8f9f7	725	*/
<>	144:ef7eb2e8f9f7	726	}
<>	144:ef7eb2e8f9f7	727
<>	144:ef7eb2e8f9f7	728	/**
<>	144:ef7eb2e8f9f7	729	* @}
<>	144:ef7eb2e8f9f7	730	*/
<>	144:ef7eb2e8f9f7	731
<>	144:ef7eb2e8f9f7	732	/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
<>	144:ef7eb2e8f9f7	733	* @brief IO operation functions
<>	144:ef7eb2e8f9f7	734	*
<>	144:ef7eb2e8f9f7	735	@verbatim
<>	144:ef7eb2e8f9f7	736	===============================================================================
<>	144:ef7eb2e8f9f7	737	##### IO operation functions #####
<>	144:ef7eb2e8f9f7	738	===============================================================================
<>	144:ef7eb2e8f9f7	739	[..] This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	740	(+) Start conversion of regular group.
<>	144:ef7eb2e8f9f7	741	(+) Stop conversion of regular group.
<>	144:ef7eb2e8f9f7	742	(+) Poll for conversion complete on regular group.
<>	144:ef7eb2e8f9f7	743	(+) Poll for conversion event.
<>	144:ef7eb2e8f9f7	744	(+) Get result of regular channel conversion.
<>	144:ef7eb2e8f9f7	745	(+) Start conversion of regular group and enable interruptions.
<>	144:ef7eb2e8f9f7	746	(+) Stop conversion of regular group and disable interruptions.
<>	144:ef7eb2e8f9f7	747	(+) Handle ADC interrupt request
<>	144:ef7eb2e8f9f7	748	(+) Start conversion of regular group and enable DMA transfer.
<>	144:ef7eb2e8f9f7	749	(+) Stop conversion of regular group and disable ADC DMA transfer.
<>	144:ef7eb2e8f9f7	750	@endverbatim
<>	144:ef7eb2e8f9f7	751	* @{
<>	144:ef7eb2e8f9f7	752	*/
<>	144:ef7eb2e8f9f7	753
<>	144:ef7eb2e8f9f7	754	/**
<>	144:ef7eb2e8f9f7	755	* @brief Enables ADC, starts conversion of regular group.
<>	144:ef7eb2e8f9f7	756	* Interruptions enabled in this function: None.
<>	144:ef7eb2e8f9f7	757	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	758	* @retval HAL status
<>	144:ef7eb2e8f9f7	759	*/
<>	144:ef7eb2e8f9f7	760	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	761	{
<>	144:ef7eb2e8f9f7	762	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<>	144:ef7eb2e8f9f7	763
<>	144:ef7eb2e8f9f7	764	/* Check the parameters */
<>	144:ef7eb2e8f9f7	765	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	766
<>	144:ef7eb2e8f9f7	767	/* Perform ADC enable and conversion start if no conversion is on going */
<>	144:ef7eb2e8f9f7	768	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<>	144:ef7eb2e8f9f7	769	{
<>	144:ef7eb2e8f9f7	770	/* Process locked */
<>	144:ef7eb2e8f9f7	771	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	772
<>	144:ef7eb2e8f9f7	773	/* Enable the ADC peripheral */
<>	144:ef7eb2e8f9f7	774	/* If low power mode AutoPowerOff is enabled, power-on/off phases are */
<>	144:ef7eb2e8f9f7	775	/* performed automatically by hardware. */
<>	144:ef7eb2e8f9f7	776	if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
<>	144:ef7eb2e8f9f7	777	{
<>	144:ef7eb2e8f9f7	778	tmp_hal_status = ADC_Enable(hadc);
<>	144:ef7eb2e8f9f7	779	}
<>	144:ef7eb2e8f9f7	780
<>	144:ef7eb2e8f9f7	781	/* Start conversion if ADC is effectively enabled */
<>	144:ef7eb2e8f9f7	782	if (tmp_hal_status == HAL_OK)
<>	144:ef7eb2e8f9f7	783	{
<>	144:ef7eb2e8f9f7	784	/* Set ADC state */
<>	144:ef7eb2e8f9f7	785	/* - Clear state bitfield related to regular group conversion results */
<>	144:ef7eb2e8f9f7	786	/* - Set state bitfield related to regular operation */
<>	144:ef7eb2e8f9f7	787	ADC_STATE_CLR_SET(hadc->State,
<>	144:ef7eb2e8f9f7	788	HAL_ADC_STATE_READY \| HAL_ADC_STATE_REG_EOC \| HAL_ADC_STATE_REG_OVR \| HAL_ADC_STATE_REG_EOSMP,
<>	144:ef7eb2e8f9f7	789	HAL_ADC_STATE_REG_BUSY);
<>	144:ef7eb2e8f9f7	790
<>	144:ef7eb2e8f9f7	791	/* Reset ADC all error code fields */
<>	144:ef7eb2e8f9f7	792	ADC_CLEAR_ERRORCODE(hadc);
<>	144:ef7eb2e8f9f7	793
<>	144:ef7eb2e8f9f7	794	/* Process unlocked */
<>	144:ef7eb2e8f9f7	795	/* Unlock before starting ADC conversions: in case of potential */
<>	144:ef7eb2e8f9f7	796	/* interruption, to let the process to ADC IRQ Handler. */
<>	144:ef7eb2e8f9f7	797	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	798
<>	144:ef7eb2e8f9f7	799	/* Clear regular group conversion flag and overrun flag */
<>	144:ef7eb2e8f9f7	800	/* (To ensure of no unknown state from potential previous ADC */
<>	144:ef7eb2e8f9f7	801	/* operations) */
<>	144:ef7eb2e8f9f7	802	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_OVR));
<>	144:ef7eb2e8f9f7	803
<>	144:ef7eb2e8f9f7	804	/* Enable conversion of regular group. */
<>	144:ef7eb2e8f9f7	805	/* If software start has been selected, conversion starts immediately. */
<>	144:ef7eb2e8f9f7	806	/* If external trigger has been selected, conversion will start at next */
<>	144:ef7eb2e8f9f7	807	/* trigger event. */
<>	144:ef7eb2e8f9f7	808	hadc->Instance->CR \|= ADC_CR_ADSTART;
<>	144:ef7eb2e8f9f7	809	}
<>	144:ef7eb2e8f9f7	810	}
<>	144:ef7eb2e8f9f7	811	else
<>	144:ef7eb2e8f9f7	812	{
<>	144:ef7eb2e8f9f7	813	tmp_hal_status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	814	}
<>	144:ef7eb2e8f9f7	815
<>	144:ef7eb2e8f9f7	816	/* Return function status */
<>	144:ef7eb2e8f9f7	817	return tmp_hal_status;
<>	144:ef7eb2e8f9f7	818	}
<>	144:ef7eb2e8f9f7	819
<>	144:ef7eb2e8f9f7	820	/**
<>	144:ef7eb2e8f9f7	821	* @brief Stop ADC conversion of regular group, disable ADC peripheral.
<>	144:ef7eb2e8f9f7	822	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	823	* @retval HAL status.
<>	144:ef7eb2e8f9f7	824	*/
<>	144:ef7eb2e8f9f7	825	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	826	{
<>	144:ef7eb2e8f9f7	827	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<>	144:ef7eb2e8f9f7	828
<>	144:ef7eb2e8f9f7	829	/* Check the parameters */
<>	144:ef7eb2e8f9f7	830	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	831
<>	144:ef7eb2e8f9f7	832	/* Process locked */
<>	144:ef7eb2e8f9f7	833	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	834
<>	144:ef7eb2e8f9f7	835	/* 1. Stop potential conversion on going, on regular group */
<>	144:ef7eb2e8f9f7	836	tmp_hal_status = ADC_ConversionStop(hadc);
<>	144:ef7eb2e8f9f7	837
<>	144:ef7eb2e8f9f7	838	/* Disable ADC peripheral if conversions are effectively stopped */
<>	144:ef7eb2e8f9f7	839	if (tmp_hal_status == HAL_OK)
<>	144:ef7eb2e8f9f7	840	{
<>	144:ef7eb2e8f9f7	841	/* 2. Disable the ADC peripheral */
<>	144:ef7eb2e8f9f7	842	tmp_hal_status = ADC_Disable(hadc);
<>	144:ef7eb2e8f9f7	843
<>	144:ef7eb2e8f9f7	844	/* Check if ADC is effectively disabled */
<>	144:ef7eb2e8f9f7	845	if (tmp_hal_status == HAL_OK)
<>	144:ef7eb2e8f9f7	846	{
<>	144:ef7eb2e8f9f7	847	/* Set ADC state */
<>	144:ef7eb2e8f9f7	848	ADC_STATE_CLR_SET(hadc->State,
<>	144:ef7eb2e8f9f7	849	HAL_ADC_STATE_REG_BUSY,
<>	144:ef7eb2e8f9f7	850	HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	851	}
<>	144:ef7eb2e8f9f7	852	}
<>	144:ef7eb2e8f9f7	853
<>	144:ef7eb2e8f9f7	854	/* Process unlocked */
<>	144:ef7eb2e8f9f7	855	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	856
<>	144:ef7eb2e8f9f7	857	/* Return function status */
<>	144:ef7eb2e8f9f7	858	return tmp_hal_status;
<>	144:ef7eb2e8f9f7	859	}
<>	144:ef7eb2e8f9f7	860
<>	144:ef7eb2e8f9f7	861	/**
<>	144:ef7eb2e8f9f7	862	* @brief Wait for regular group conversion to be completed.
<>	144:ef7eb2e8f9f7	863	* @note ADC conversion flags EOS (end of sequence) and EOC (end of
<>	144:ef7eb2e8f9f7	864	* conversion) are cleared by this function, with an exception:
<>	144:ef7eb2e8f9f7	865	* if low power feature "LowPowerAutoWait" is enabled, flags are
<>	144:ef7eb2e8f9f7	866	* not cleared to not interfere with this feature until data register
<>	144:ef7eb2e8f9f7	867	* is read using function HAL_ADC_GetValue().
<>	144:ef7eb2e8f9f7	868	* @note This function cannot be used in a particular setup: ADC configured
<>	144:ef7eb2e8f9f7	869	* in DMA mode and polling for end of each conversion (ADC init
<>	144:ef7eb2e8f9f7	870	* parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
<>	144:ef7eb2e8f9f7	871	* In this case, DMA resets the flag EOC and polling cannot be
<>	144:ef7eb2e8f9f7	872	* performed on each conversion. Nevertheless, polling can still
<>	144:ef7eb2e8f9f7	873	* be performed on the complete sequence (ADC init
<>	144:ef7eb2e8f9f7	874	* parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
<>	144:ef7eb2e8f9f7	875	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	876	* @param Timeout: Timeout value in millisecond.
<>	144:ef7eb2e8f9f7	877	* @retval HAL status
<>	144:ef7eb2e8f9f7	878	*/
<>	144:ef7eb2e8f9f7	879	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	880	{
<>	144:ef7eb2e8f9f7	881	uint32_t tickstart;
<>	144:ef7eb2e8f9f7	882	uint32_t tmp_Flag_EOC;
<>	144:ef7eb2e8f9f7	883
<>	144:ef7eb2e8f9f7	884	/* Check the parameters */
<>	144:ef7eb2e8f9f7	885	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	886
<>	144:ef7eb2e8f9f7	887	/* If end of conversion selected to end of sequence */
<>	144:ef7eb2e8f9f7	888	if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
<>	144:ef7eb2e8f9f7	889	{
<>	144:ef7eb2e8f9f7	890	tmp_Flag_EOC = ADC_FLAG_EOS;
<>	144:ef7eb2e8f9f7	891	}
<>	144:ef7eb2e8f9f7	892	/* If end of conversion selected to end of each conversion */
<>	144:ef7eb2e8f9f7	893	else /* ADC_EOC_SINGLE_CONV */
<>	144:ef7eb2e8f9f7	894	{
<>	144:ef7eb2e8f9f7	895	/* Verification that ADC configuration is compliant with polling for */
<>	144:ef7eb2e8f9f7	896	/* each conversion: */
<>	144:ef7eb2e8f9f7	897	/* Particular case is ADC configured in DMA mode and ADC sequencer with */
<>	144:ef7eb2e8f9f7	898	/* several ranks and polling for end of each conversion. */
<>	144:ef7eb2e8f9f7	899	/* For code simplicity sake, this particular case is generalized to */
<>	144:ef7eb2e8f9f7	900	/* ADC configured in DMA mode and and polling for end of each conversion. */
<>	144:ef7eb2e8f9f7	901	if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN))
<>	144:ef7eb2e8f9f7	902	{
<>	144:ef7eb2e8f9f7	903	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	904	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<>	144:ef7eb2e8f9f7	905
<>	144:ef7eb2e8f9f7	906	/* Process unlocked */
<>	144:ef7eb2e8f9f7	907	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	908
<>	144:ef7eb2e8f9f7	909	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	910	}
<>	144:ef7eb2e8f9f7	911	else
<>	144:ef7eb2e8f9f7	912	{
<>	144:ef7eb2e8f9f7	913	tmp_Flag_EOC = (ADC_FLAG_EOC \| ADC_FLAG_EOS);
<>	144:ef7eb2e8f9f7	914	}
<>	144:ef7eb2e8f9f7	915	}
<>	144:ef7eb2e8f9f7	916
<>	144:ef7eb2e8f9f7	917	/* Get tick count */
<>	144:ef7eb2e8f9f7	918	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	919
<>	144:ef7eb2e8f9f7	920	/* Wait until End of Conversion flag is raised */
<>	144:ef7eb2e8f9f7	921	while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
<>	144:ef7eb2e8f9f7	922	{
<>	144:ef7eb2e8f9f7	923	/* Check if timeout is disabled (set to infinite wait) */
<>	144:ef7eb2e8f9f7	924	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	925	{
<>	144:ef7eb2e8f9f7	926	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	927	{
<>	144:ef7eb2e8f9f7	928	/* Update ADC state machine to timeout */
<>	144:ef7eb2e8f9f7	929	SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<>	144:ef7eb2e8f9f7	930
<>	144:ef7eb2e8f9f7	931	/* Process unlocked */
<>	144:ef7eb2e8f9f7	932	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	933
<>	144:ef7eb2e8f9f7	934	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	935	}
<>	144:ef7eb2e8f9f7	936	}
<>	144:ef7eb2e8f9f7	937	}
<>	144:ef7eb2e8f9f7	938
<>	144:ef7eb2e8f9f7	939	/* Update ADC state machine */
<>	144:ef7eb2e8f9f7	940	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<>	144:ef7eb2e8f9f7	941
<>	144:ef7eb2e8f9f7	942	/* Determine whether any further conversion upcoming on group regular */
<>	144:ef7eb2e8f9f7	943	/* by external trigger, continuous mode or scan sequence on going. */
<>	144:ef7eb2e8f9f7	944	if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<>	144:ef7eb2e8f9f7	945	(hadc->Init.ContinuousConvMode == DISABLE) )
<>	144:ef7eb2e8f9f7	946	{
<>	144:ef7eb2e8f9f7	947	/* If End of Sequence is reached, disable interrupts */
<>	144:ef7eb2e8f9f7	948	if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
<>	144:ef7eb2e8f9f7	949	{
<>	144:ef7eb2e8f9f7	950	/* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
<>	144:ef7eb2e8f9f7	951	/* ADSTART==0 (no conversion on going) */
<>	144:ef7eb2e8f9f7	952	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<>	144:ef7eb2e8f9f7	953	{
<>	144:ef7eb2e8f9f7	954	/* Disable ADC end of single conversion interrupt on group regular */
<>	144:ef7eb2e8f9f7	955	/* Note: Overrun interrupt was enabled with EOC interrupt in */
<>	144:ef7eb2e8f9f7	956	/* HAL_Start_IT(), but is not disabled here because can be used */
<>	144:ef7eb2e8f9f7	957	/* by overrun IRQ process below. */
<>	144:ef7eb2e8f9f7	958	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC \| ADC_IT_EOS);
<>	144:ef7eb2e8f9f7	959
<>	144:ef7eb2e8f9f7	960	/* Set ADC state */
<>	144:ef7eb2e8f9f7	961	ADC_STATE_CLR_SET(hadc->State,
<>	144:ef7eb2e8f9f7	962	HAL_ADC_STATE_REG_BUSY,
<>	144:ef7eb2e8f9f7	963	HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	964	}
<>	144:ef7eb2e8f9f7	965	else
<>	144:ef7eb2e8f9f7	966	{
<>	144:ef7eb2e8f9f7	967	/* Change ADC state to error state */
<>	144:ef7eb2e8f9f7	968	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<>	144:ef7eb2e8f9f7	969
<>	144:ef7eb2e8f9f7	970	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	971	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	972	}
<>	144:ef7eb2e8f9f7	973	}
<>	144:ef7eb2e8f9f7	974	}
<>	144:ef7eb2e8f9f7	975
<>	144:ef7eb2e8f9f7	976	/* Clear end of conversion flag of regular group if low power feature */
<>	144:ef7eb2e8f9f7	977	/* "LowPowerAutoWait " is disabled, to not interfere with this feature */
<>	144:ef7eb2e8f9f7	978	/* until data register is read using function HAL_ADC_GetValue(). */
<>	144:ef7eb2e8f9f7	979	if (hadc->Init.LowPowerAutoWait == DISABLE)
<>	144:ef7eb2e8f9f7	980	{
<>	144:ef7eb2e8f9f7	981	/* Clear regular group conversion flag */
<>	144:ef7eb2e8f9f7	982	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS));
<>	144:ef7eb2e8f9f7	983	}
<>	144:ef7eb2e8f9f7	984
<>	144:ef7eb2e8f9f7	985	/* Return ADC state */
<>	144:ef7eb2e8f9f7	986	return HAL_OK;
<>	144:ef7eb2e8f9f7	987	}
<>	144:ef7eb2e8f9f7	988
<>	144:ef7eb2e8f9f7	989	/**
<>	144:ef7eb2e8f9f7	990	* @brief Poll for conversion event.
<>	144:ef7eb2e8f9f7	991	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	992	* @param EventType: the ADC event type.
<>	144:ef7eb2e8f9f7	993	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	994	* @arg ADC_AWD_EVENT: ADC Analog watchdog event
<>	144:ef7eb2e8f9f7	995	* @arg ADC_OVR_EVENT: ADC Overrun event
<>	144:ef7eb2e8f9f7	996	* @param Timeout: Timeout value in millisecond.
<>	144:ef7eb2e8f9f7	997	* @retval HAL status
<>	144:ef7eb2e8f9f7	998	*/
<>	144:ef7eb2e8f9f7	999	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1000	{
<>	144:ef7eb2e8f9f7	1001	uint32_t tickstart=0;
<>	144:ef7eb2e8f9f7	1002
<>	144:ef7eb2e8f9f7	1003	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1004	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1005	assert_param(IS_ADC_EVENT_TYPE(EventType));
<>	144:ef7eb2e8f9f7	1006
<>	144:ef7eb2e8f9f7	1007	/* Get tick count */
<>	144:ef7eb2e8f9f7	1008	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1009
<>	144:ef7eb2e8f9f7	1010	/* Check selected event flag */
<>	144:ef7eb2e8f9f7	1011	while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
<>	144:ef7eb2e8f9f7	1012	{
<>	144:ef7eb2e8f9f7	1013	/* Check if timeout is disabled (set to infinite wait) */
<>	144:ef7eb2e8f9f7	1014	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	1015	{
<>	156:95d6b41a828b	1016	if((Timeout == 0U) \|\| ((HAL_GetTick()-tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	1017	{
<>	144:ef7eb2e8f9f7	1018	/* Update ADC state machine to timeout */
<>	144:ef7eb2e8f9f7	1019	SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<>	144:ef7eb2e8f9f7	1020
<>	144:ef7eb2e8f9f7	1021	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1022	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1023
<>	144:ef7eb2e8f9f7	1024	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1025	}
<>	144:ef7eb2e8f9f7	1026	}
<>	144:ef7eb2e8f9f7	1027	}
<>	144:ef7eb2e8f9f7	1028
<>	144:ef7eb2e8f9f7	1029	switch(EventType)
<>	144:ef7eb2e8f9f7	1030	{
<>	144:ef7eb2e8f9f7	1031	/* Analog watchdog (level out of window) event */
<>	144:ef7eb2e8f9f7	1032	case ADC_AWD_EVENT:
<>	144:ef7eb2e8f9f7	1033	/* Set ADC state */
<>	144:ef7eb2e8f9f7	1034	SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
<>	144:ef7eb2e8f9f7	1035
<>	144:ef7eb2e8f9f7	1036	/* Clear ADC analog watchdog flag */
<>	144:ef7eb2e8f9f7	1037	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
<>	144:ef7eb2e8f9f7	1038	break;
<>	144:ef7eb2e8f9f7	1039
<>	144:ef7eb2e8f9f7	1040	/* Overrun event */
<>	144:ef7eb2e8f9f7	1041	default: /* Case ADC_OVR_EVENT */
<>	144:ef7eb2e8f9f7	1042	/* If overrun is set to overwrite previous data, overrun event is not */
<>	144:ef7eb2e8f9f7	1043	/* considered as an error. */
<>	144:ef7eb2e8f9f7	1044	/* (cf ref manual "Managing conversions without using the DMA and without */
<>	144:ef7eb2e8f9f7	1045	/* overrun ") */
<>	144:ef7eb2e8f9f7	1046	if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
<>	144:ef7eb2e8f9f7	1047	{
<>	144:ef7eb2e8f9f7	1048	/* Set ADC state */
<>	144:ef7eb2e8f9f7	1049	SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
<>	144:ef7eb2e8f9f7	1050
<>	144:ef7eb2e8f9f7	1051	/* Set ADC error code to overrun */
<>	144:ef7eb2e8f9f7	1052	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
<>	144:ef7eb2e8f9f7	1053	}
<>	144:ef7eb2e8f9f7	1054
<>	144:ef7eb2e8f9f7	1055	/* Clear ADC Overrun flag */
<>	144:ef7eb2e8f9f7	1056	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
<>	144:ef7eb2e8f9f7	1057	break;
<>	144:ef7eb2e8f9f7	1058	}
<>	144:ef7eb2e8f9f7	1059
<>	144:ef7eb2e8f9f7	1060	/* Return ADC state */
<>	144:ef7eb2e8f9f7	1061	return HAL_OK;
<>	144:ef7eb2e8f9f7	1062	}
<>	144:ef7eb2e8f9f7	1063
<>	144:ef7eb2e8f9f7	1064	/**
<>	144:ef7eb2e8f9f7	1065	* @brief Enables ADC, starts conversion of regular group with interruption.
<>	144:ef7eb2e8f9f7	1066	* Interruptions enabled in this function:
<>	144:ef7eb2e8f9f7	1067	* - EOC (end of conversion of regular group) or EOS (end of
<>	144:ef7eb2e8f9f7	1068	* sequence of regular group) depending on ADC initialization
<>	144:ef7eb2e8f9f7	1069	* parameter "EOCSelection"
<>	144:ef7eb2e8f9f7	1070	* - overrun (if available)
<>	144:ef7eb2e8f9f7	1071	* Each of these interruptions has its dedicated callback function.
<>	144:ef7eb2e8f9f7	1072	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1073	* @retval HAL status
<>	144:ef7eb2e8f9f7	1074	*/
<>	144:ef7eb2e8f9f7	1075	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	1076	{
<>	144:ef7eb2e8f9f7	1077	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<>	144:ef7eb2e8f9f7	1078
<>	144:ef7eb2e8f9f7	1079	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1080	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1081
<>	144:ef7eb2e8f9f7	1082	/* Perform ADC enable and conversion start if no conversion is on going */
<>	144:ef7eb2e8f9f7	1083	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<>	144:ef7eb2e8f9f7	1084	{
<>	144:ef7eb2e8f9f7	1085	/* Process locked */
<>	144:ef7eb2e8f9f7	1086	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	1087
<>	144:ef7eb2e8f9f7	1088	/* Enable the ADC peripheral */
<>	144:ef7eb2e8f9f7	1089	/* If low power mode AutoPowerOff is enabled, power-on/off phases are */
<>	144:ef7eb2e8f9f7	1090	/* performed automatically by hardware. */
<>	144:ef7eb2e8f9f7	1091	if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
<>	144:ef7eb2e8f9f7	1092	{
<>	144:ef7eb2e8f9f7	1093	tmp_hal_status = ADC_Enable(hadc);
<>	144:ef7eb2e8f9f7	1094	}
<>	144:ef7eb2e8f9f7	1095
<>	144:ef7eb2e8f9f7	1096	/* Start conversion if ADC is effectively enabled */
<>	144:ef7eb2e8f9f7	1097	if (tmp_hal_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1098	{
<>	144:ef7eb2e8f9f7	1099	/* Set ADC state */
<>	144:ef7eb2e8f9f7	1100	/* - Clear state bitfield related to regular group conversion results */
<>	144:ef7eb2e8f9f7	1101	/* - Set state bitfield related to regular operation */
<>	144:ef7eb2e8f9f7	1102	ADC_STATE_CLR_SET(hadc->State,
<>	144:ef7eb2e8f9f7	1103	HAL_ADC_STATE_READY \| HAL_ADC_STATE_REG_EOC \| HAL_ADC_STATE_REG_OVR \| HAL_ADC_STATE_REG_EOSMP,
<>	144:ef7eb2e8f9f7	1104	HAL_ADC_STATE_REG_BUSY);
<>	144:ef7eb2e8f9f7	1105
<>	144:ef7eb2e8f9f7	1106	/* Reset ADC all error code fields */
<>	144:ef7eb2e8f9f7	1107	ADC_CLEAR_ERRORCODE(hadc);
<>	144:ef7eb2e8f9f7	1108
<>	144:ef7eb2e8f9f7	1109	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1110	/* Unlock before starting ADC conversions: in case of potential */
<>	144:ef7eb2e8f9f7	1111	/* interruption, to let the process to ADC IRQ Handler. */
<>	144:ef7eb2e8f9f7	1112	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1113
<>	144:ef7eb2e8f9f7	1114	/* Clear regular group conversion flag and overrun flag */
<>	144:ef7eb2e8f9f7	1115	/* (To ensure of no unknown state from potential previous ADC */
<>	144:ef7eb2e8f9f7	1116	/* operations) */
<>	144:ef7eb2e8f9f7	1117	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_OVR));
<>	144:ef7eb2e8f9f7	1118
<>	144:ef7eb2e8f9f7	1119	/* Enable ADC end of conversion interrupt */
<>	144:ef7eb2e8f9f7	1120	/* Enable ADC overrun interrupt */
<>	144:ef7eb2e8f9f7	1121	switch(hadc->Init.EOCSelection)
<>	144:ef7eb2e8f9f7	1122	{
<>	144:ef7eb2e8f9f7	1123	case ADC_EOC_SEQ_CONV:
<>	144:ef7eb2e8f9f7	1124	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
<>	144:ef7eb2e8f9f7	1125	__HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS \| ADC_IT_OVR));
<>	144:ef7eb2e8f9f7	1126	break;
<>	144:ef7eb2e8f9f7	1127	/* case ADC_EOC_SINGLE_CONV */
<>	144:ef7eb2e8f9f7	1128	default:
<>	144:ef7eb2e8f9f7	1129	__HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC \| ADC_IT_EOS \| ADC_IT_OVR));
<>	144:ef7eb2e8f9f7	1130	break;
<>	144:ef7eb2e8f9f7	1131	}
<>	144:ef7eb2e8f9f7	1132
<>	144:ef7eb2e8f9f7	1133	/* Enable conversion of regular group. */
<>	144:ef7eb2e8f9f7	1134	/* If software start has been selected, conversion starts immediately. */
<>	144:ef7eb2e8f9f7	1135	/* If external trigger has been selected, conversion will start at next */
<>	144:ef7eb2e8f9f7	1136	/* trigger event. */
<>	144:ef7eb2e8f9f7	1137	hadc->Instance->CR \|= ADC_CR_ADSTART;
<>	144:ef7eb2e8f9f7	1138	}
<>	144:ef7eb2e8f9f7	1139	}
<>	144:ef7eb2e8f9f7	1140	else
<>	144:ef7eb2e8f9f7	1141	{
<>	144:ef7eb2e8f9f7	1142	tmp_hal_status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1143	}
<>	144:ef7eb2e8f9f7	1144
<>	144:ef7eb2e8f9f7	1145	/* Return function status */
<>	144:ef7eb2e8f9f7	1146	return tmp_hal_status;
<>	144:ef7eb2e8f9f7	1147	}
<>	144:ef7eb2e8f9f7	1148
<>	144:ef7eb2e8f9f7	1149
<>	144:ef7eb2e8f9f7	1150	/**
<>	144:ef7eb2e8f9f7	1151	* @brief Stop ADC conversion of regular group, disable interruption of
<>	144:ef7eb2e8f9f7	1152	* end-of-conversion, disable ADC peripheral.
<>	144:ef7eb2e8f9f7	1153	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1154	* @retval HAL status.
<>	144:ef7eb2e8f9f7	1155	*/
<>	144:ef7eb2e8f9f7	1156	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	1157	{
<>	144:ef7eb2e8f9f7	1158	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<>	144:ef7eb2e8f9f7	1159
<>	144:ef7eb2e8f9f7	1160	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1161	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1162
<>	144:ef7eb2e8f9f7	1163	/* Process locked */
<>	144:ef7eb2e8f9f7	1164	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	1165
<>	144:ef7eb2e8f9f7	1166	/* 1. Stop potential conversion on going, on regular group */
<>	144:ef7eb2e8f9f7	1167	tmp_hal_status = ADC_ConversionStop(hadc);
<>	144:ef7eb2e8f9f7	1168
<>	144:ef7eb2e8f9f7	1169	/* Disable ADC peripheral if conversions are effectively stopped */
<>	144:ef7eb2e8f9f7	1170	if (tmp_hal_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1171	{
<>	144:ef7eb2e8f9f7	1172	/* Disable ADC end of conversion interrupt for regular group */
<>	144:ef7eb2e8f9f7	1173	/* Disable ADC overrun interrupt */
<>	144:ef7eb2e8f9f7	1174	__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC \| ADC_IT_EOS \| ADC_IT_OVR));
<>	144:ef7eb2e8f9f7	1175
<>	144:ef7eb2e8f9f7	1176	/* 2. Disable the ADC peripheral */
<>	144:ef7eb2e8f9f7	1177	tmp_hal_status = ADC_Disable(hadc);
<>	144:ef7eb2e8f9f7	1178
<>	144:ef7eb2e8f9f7	1179	/* Check if ADC is effectively disabled */
<>	144:ef7eb2e8f9f7	1180	if (tmp_hal_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1181	{
<>	144:ef7eb2e8f9f7	1182	/* Set ADC state */
<>	144:ef7eb2e8f9f7	1183	ADC_STATE_CLR_SET(hadc->State,
<>	144:ef7eb2e8f9f7	1184	HAL_ADC_STATE_REG_BUSY,
<>	144:ef7eb2e8f9f7	1185	HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	1186	}
<>	144:ef7eb2e8f9f7	1187	}
<>	144:ef7eb2e8f9f7	1188
<>	144:ef7eb2e8f9f7	1189	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1190	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1191
<>	144:ef7eb2e8f9f7	1192	/* Return function status */
<>	144:ef7eb2e8f9f7	1193	return tmp_hal_status;
<>	144:ef7eb2e8f9f7	1194	}
<>	144:ef7eb2e8f9f7	1195
<>	144:ef7eb2e8f9f7	1196	/**
<>	144:ef7eb2e8f9f7	1197	* @brief Enables ADC, starts conversion of regular group and transfers result
<>	144:ef7eb2e8f9f7	1198	* through DMA.
<>	144:ef7eb2e8f9f7	1199	* Interruptions enabled in this function:
<>	144:ef7eb2e8f9f7	1200	* - DMA transfer complete
<>	144:ef7eb2e8f9f7	1201	* - DMA half transfer
<>	144:ef7eb2e8f9f7	1202	* - overrun
<>	144:ef7eb2e8f9f7	1203	* Each of these interruptions has its dedicated callback function.
<>	144:ef7eb2e8f9f7	1204	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1205	* @param pData: The destination Buffer address.
<>	144:ef7eb2e8f9f7	1206	* @param Length: The length of data to be transferred from ADC peripheral to memory.
<>	144:ef7eb2e8f9f7	1207	* @retval None
<>	144:ef7eb2e8f9f7	1208	*/
<>	144:ef7eb2e8f9f7	1209	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
<>	144:ef7eb2e8f9f7	1210	{
<>	144:ef7eb2e8f9f7	1211	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<>	144:ef7eb2e8f9f7	1212
<>	144:ef7eb2e8f9f7	1213	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1214	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1215
<>	144:ef7eb2e8f9f7	1216	/* Perform ADC enable and conversion start if no conversion is on going */
<>	144:ef7eb2e8f9f7	1217	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<>	144:ef7eb2e8f9f7	1218	{
<>	144:ef7eb2e8f9f7	1219	/* Process locked */
<>	144:ef7eb2e8f9f7	1220	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	1221
<>	144:ef7eb2e8f9f7	1222	/* Enable the ADC peripheral */
<>	144:ef7eb2e8f9f7	1223	/* If low power mode AutoPowerOff is enabled, power-on/off phases are */
<>	144:ef7eb2e8f9f7	1224	/* performed automatically by hardware. */
<>	144:ef7eb2e8f9f7	1225	if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
<>	144:ef7eb2e8f9f7	1226	{
<>	144:ef7eb2e8f9f7	1227	tmp_hal_status = ADC_Enable(hadc);
<>	144:ef7eb2e8f9f7	1228	}
<>	144:ef7eb2e8f9f7	1229
<>	144:ef7eb2e8f9f7	1230	/* Start conversion if ADC is effectively enabled */
<>	144:ef7eb2e8f9f7	1231	if (tmp_hal_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1232	{
<>	144:ef7eb2e8f9f7	1233	/* Set ADC state */
<>	144:ef7eb2e8f9f7	1234	/* - Clear state bitfield related to regular group conversion results */
<>	144:ef7eb2e8f9f7	1235	/* - Set state bitfield related to regular operation */
<>	144:ef7eb2e8f9f7	1236	ADC_STATE_CLR_SET(hadc->State,
<>	144:ef7eb2e8f9f7	1237	HAL_ADC_STATE_READY \| HAL_ADC_STATE_REG_EOC \| HAL_ADC_STATE_REG_OVR \| HAL_ADC_STATE_REG_EOSMP,
<>	144:ef7eb2e8f9f7	1238	HAL_ADC_STATE_REG_BUSY);
<>	144:ef7eb2e8f9f7	1239
<>	144:ef7eb2e8f9f7	1240	/* Reset ADC all error code fields */
<>	144:ef7eb2e8f9f7	1241	ADC_CLEAR_ERRORCODE(hadc);
<>	144:ef7eb2e8f9f7	1242
<>	144:ef7eb2e8f9f7	1243	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1244	/* Unlock before starting ADC conversions: in case of potential */
<>	144:ef7eb2e8f9f7	1245	/* interruption, to let the process to ADC IRQ Handler. */
<>	144:ef7eb2e8f9f7	1246	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1247
<>	144:ef7eb2e8f9f7	1248	/* Set the DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1249	hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
<>	144:ef7eb2e8f9f7	1250
<>	144:ef7eb2e8f9f7	1251	/* Set the DMA half transfer complete callback */
<>	144:ef7eb2e8f9f7	1252	hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
<>	144:ef7eb2e8f9f7	1253
<>	144:ef7eb2e8f9f7	1254	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1255	hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
<>	144:ef7eb2e8f9f7	1256
<>	144:ef7eb2e8f9f7	1257
<>	144:ef7eb2e8f9f7	1258	/* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
<>	144:ef7eb2e8f9f7	1259	/* start (in case of SW start): */
<>	144:ef7eb2e8f9f7	1260
<>	144:ef7eb2e8f9f7	1261	/* Clear regular group conversion flag and overrun flag */
<>	144:ef7eb2e8f9f7	1262	/* (To ensure of no unknown state from potential previous ADC */
<>	144:ef7eb2e8f9f7	1263	/* operations) */
<>	144:ef7eb2e8f9f7	1264	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_OVR));
<>	144:ef7eb2e8f9f7	1265
<>	144:ef7eb2e8f9f7	1266	/* Enable ADC overrun interrupt */
<>	144:ef7eb2e8f9f7	1267	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
<>	144:ef7eb2e8f9f7	1268
<>	144:ef7eb2e8f9f7	1269	/* Enable ADC DMA mode */
<>	144:ef7eb2e8f9f7	1270	hadc->Instance->CFGR1 \|= ADC_CFGR1_DMAEN;
<>	144:ef7eb2e8f9f7	1271
<>	144:ef7eb2e8f9f7	1272	/* Start the DMA channel */
<>	144:ef7eb2e8f9f7	1273	HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
<>	144:ef7eb2e8f9f7	1274
<>	144:ef7eb2e8f9f7	1275	/* Enable conversion of regular group. */
<>	144:ef7eb2e8f9f7	1276	/* If software start has been selected, conversion starts immediately. */
<>	144:ef7eb2e8f9f7	1277	/* If external trigger has been selected, conversion will start at next */
<>	144:ef7eb2e8f9f7	1278	/* trigger event. */
<>	144:ef7eb2e8f9f7	1279	hadc->Instance->CR \|= ADC_CR_ADSTART;
<>	144:ef7eb2e8f9f7	1280	}
<>	144:ef7eb2e8f9f7	1281	}
<>	144:ef7eb2e8f9f7	1282	else
<>	144:ef7eb2e8f9f7	1283	{
<>	144:ef7eb2e8f9f7	1284	tmp_hal_status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1285	}
<>	144:ef7eb2e8f9f7	1286
<>	144:ef7eb2e8f9f7	1287	/* Return function status */
<>	144:ef7eb2e8f9f7	1288	return tmp_hal_status;
<>	144:ef7eb2e8f9f7	1289	}
<>	144:ef7eb2e8f9f7	1290
<>	144:ef7eb2e8f9f7	1291	/**
<>	144:ef7eb2e8f9f7	1292	* @brief Stop ADC conversion of regular group, disable ADC DMA transfer, disable
<>	144:ef7eb2e8f9f7	1293	* ADC peripheral.
<>	144:ef7eb2e8f9f7	1294	* Each of these interruptions has its dedicated callback function.
<>	144:ef7eb2e8f9f7	1295	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1296	* @retval HAL status.
<>	144:ef7eb2e8f9f7	1297	*/
<>	144:ef7eb2e8f9f7	1298	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	1299	{
<>	144:ef7eb2e8f9f7	1300	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<>	144:ef7eb2e8f9f7	1301
<>	144:ef7eb2e8f9f7	1302	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1303	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1304
<>	144:ef7eb2e8f9f7	1305	/* Process locked */
<>	144:ef7eb2e8f9f7	1306	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	1307
<>	144:ef7eb2e8f9f7	1308	/* 1. Stop potential conversion on going, on regular group */
<>	144:ef7eb2e8f9f7	1309	tmp_hal_status = ADC_ConversionStop(hadc);
<>	144:ef7eb2e8f9f7	1310
<>	144:ef7eb2e8f9f7	1311	/* Disable ADC peripheral if conversions are effectively stopped */
<>	144:ef7eb2e8f9f7	1312	if (tmp_hal_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1313	{
<>	144:ef7eb2e8f9f7	1314	/* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
<>	144:ef7eb2e8f9f7	1315	hadc->Instance->CFGR1 &= ~ADC_CFGR1_DMAEN;
<>	144:ef7eb2e8f9f7	1316
<>	144:ef7eb2e8f9f7	1317	/* Disable the DMA channel (in case of DMA in circular mode or stop while */
<>	144:ef7eb2e8f9f7	1318	/* while DMA transfer is on going) */
<>	144:ef7eb2e8f9f7	1319	tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
<>	144:ef7eb2e8f9f7	1320
<>	144:ef7eb2e8f9f7	1321	/* Check if DMA channel effectively disabled */
<>	144:ef7eb2e8f9f7	1322	if (tmp_hal_status != HAL_OK)
<>	144:ef7eb2e8f9f7	1323	{
<>	144:ef7eb2e8f9f7	1324	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	1325	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<>	144:ef7eb2e8f9f7	1326	}
<>	144:ef7eb2e8f9f7	1327
<>	144:ef7eb2e8f9f7	1328	/* Disable ADC overrun interrupt */
<>	144:ef7eb2e8f9f7	1329	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
<>	144:ef7eb2e8f9f7	1330
<>	144:ef7eb2e8f9f7	1331	/* 2. Disable the ADC peripheral */
<>	144:ef7eb2e8f9f7	1332	/* Update "tmp_hal_status" only if DMA channel disabling passed, to keep */
<>	144:ef7eb2e8f9f7	1333	/* in memory a potential failing status. */
<>	144:ef7eb2e8f9f7	1334	if (tmp_hal_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1335	{
<>	144:ef7eb2e8f9f7	1336	tmp_hal_status = ADC_Disable(hadc);
<>	144:ef7eb2e8f9f7	1337	}
<>	144:ef7eb2e8f9f7	1338	else
<>	144:ef7eb2e8f9f7	1339	{
<>	144:ef7eb2e8f9f7	1340	ADC_Disable(hadc);
<>	144:ef7eb2e8f9f7	1341	}
<>	144:ef7eb2e8f9f7	1342
<>	144:ef7eb2e8f9f7	1343	/* Check if ADC is effectively disabled */
<>	144:ef7eb2e8f9f7	1344	if (tmp_hal_status == HAL_OK)
<>	144:ef7eb2e8f9f7	1345	{
<>	144:ef7eb2e8f9f7	1346	/* Set ADC state */
<>	144:ef7eb2e8f9f7	1347	ADC_STATE_CLR_SET(hadc->State,
<>	144:ef7eb2e8f9f7	1348	HAL_ADC_STATE_REG_BUSY,
<>	144:ef7eb2e8f9f7	1349	HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	1350	}
<>	144:ef7eb2e8f9f7	1351
<>	144:ef7eb2e8f9f7	1352	}
<>	144:ef7eb2e8f9f7	1353
<>	144:ef7eb2e8f9f7	1354	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1355	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1356
<>	144:ef7eb2e8f9f7	1357	/* Return function status */
<>	144:ef7eb2e8f9f7	1358	return tmp_hal_status;
<>	144:ef7eb2e8f9f7	1359	}
<>	144:ef7eb2e8f9f7	1360
<>	144:ef7eb2e8f9f7	1361	/**
<>	144:ef7eb2e8f9f7	1362	* @brief Get ADC regular group conversion result.
<>	144:ef7eb2e8f9f7	1363	* @note Reading register DR automatically clears ADC flag EOC
<>	144:ef7eb2e8f9f7	1364	* (ADC group regular end of unitary conversion).
<>	144:ef7eb2e8f9f7	1365	* @note This function does not clear ADC flag EOS
<>	144:ef7eb2e8f9f7	1366	* (ADC group regular end of sequence conversion).
<>	144:ef7eb2e8f9f7	1367	* Occurrence of flag EOS rising:
<>	144:ef7eb2e8f9f7	1368	* - If sequencer is composed of 1 rank, flag EOS is equivalent
<>	144:ef7eb2e8f9f7	1369	* to flag EOC.
<>	144:ef7eb2e8f9f7	1370	* - If sequencer is composed of several ranks, during the scan
<>	144:ef7eb2e8f9f7	1371	* sequence flag EOC only is raised, at the end of the scan sequence
<>	144:ef7eb2e8f9f7	1372	* both flags EOC and EOS are raised.
<>	144:ef7eb2e8f9f7	1373	* To clear this flag, either use function:
<>	144:ef7eb2e8f9f7	1374	* in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
<>	144:ef7eb2e8f9f7	1375	* model polling: @ref HAL_ADC_PollForConversion()
<>	144:ef7eb2e8f9f7	1376	* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
<>	144:ef7eb2e8f9f7	1377	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1378	* @retval ADC group regular conversion data
<>	144:ef7eb2e8f9f7	1379	*/
<>	144:ef7eb2e8f9f7	1380	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	1381	{
<>	144:ef7eb2e8f9f7	1382	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1383	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1384
<>	144:ef7eb2e8f9f7	1385	/* Note: EOC flag is not cleared here by software because automatically */
<>	144:ef7eb2e8f9f7	1386	/* cleared by hardware when reading register DR. */
<>	144:ef7eb2e8f9f7	1387
<>	144:ef7eb2e8f9f7	1388	/* Return ADC converted value */
<>	144:ef7eb2e8f9f7	1389	return hadc->Instance->DR;
<>	144:ef7eb2e8f9f7	1390	}
<>	144:ef7eb2e8f9f7	1391
<>	144:ef7eb2e8f9f7	1392	/**
<>	144:ef7eb2e8f9f7	1393	* @brief Handles ADC interrupt request.
<>	144:ef7eb2e8f9f7	1394	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1395	* @retval None
<>	144:ef7eb2e8f9f7	1396	*/
<>	144:ef7eb2e8f9f7	1397	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	1398	{
<>	144:ef7eb2e8f9f7	1399	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1400	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1401	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
<>	144:ef7eb2e8f9f7	1402	assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
<>	144:ef7eb2e8f9f7	1403
<>	144:ef7eb2e8f9f7	1404	/* ========== Check End of Conversion flag for regular group ========== */
<>	144:ef7eb2e8f9f7	1405	if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) \|\|
<>	144:ef7eb2e8f9f7	1406	(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) )
<>	144:ef7eb2e8f9f7	1407	{
<>	144:ef7eb2e8f9f7	1408	/* Update state machine on conversion status if not in error state */
<>	144:ef7eb2e8f9f7	1409	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
<>	144:ef7eb2e8f9f7	1410	{
<>	144:ef7eb2e8f9f7	1411	/* Set ADC state */
<>	144:ef7eb2e8f9f7	1412	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<>	144:ef7eb2e8f9f7	1413	}
<>	144:ef7eb2e8f9f7	1414
<>	144:ef7eb2e8f9f7	1415	/* Determine whether any further conversion upcoming on group regular */
<>	144:ef7eb2e8f9f7	1416	/* by external trigger, continuous mode or scan sequence on going. */
<>	144:ef7eb2e8f9f7	1417	if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<>	144:ef7eb2e8f9f7	1418	(hadc->Init.ContinuousConvMode == DISABLE) )
<>	144:ef7eb2e8f9f7	1419	{
<>	144:ef7eb2e8f9f7	1420	/* If End of Sequence is reached, disable interrupts */
<>	144:ef7eb2e8f9f7	1421	if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
<>	144:ef7eb2e8f9f7	1422	{
<>	144:ef7eb2e8f9f7	1423	/* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
<>	144:ef7eb2e8f9f7	1424	/* ADSTART==0 (no conversion on going) */
<>	144:ef7eb2e8f9f7	1425	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<>	144:ef7eb2e8f9f7	1426	{
<>	144:ef7eb2e8f9f7	1427	/* Disable ADC end of single conversion interrupt on group regular */
<>	144:ef7eb2e8f9f7	1428	/* Note: Overrun interrupt was enabled with EOC interrupt in */
<>	144:ef7eb2e8f9f7	1429	/* HAL_Start_IT(), but is not disabled here because can be used */
<>	144:ef7eb2e8f9f7	1430	/* by overrun IRQ process below. */
<>	144:ef7eb2e8f9f7	1431	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC \| ADC_IT_EOS);
<>	144:ef7eb2e8f9f7	1432
<>	144:ef7eb2e8f9f7	1433	/* Set ADC state */
<>	144:ef7eb2e8f9f7	1434	ADC_STATE_CLR_SET(hadc->State,
<>	144:ef7eb2e8f9f7	1435	HAL_ADC_STATE_REG_BUSY,
<>	144:ef7eb2e8f9f7	1436	HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	1437	}
<>	144:ef7eb2e8f9f7	1438	else
<>	144:ef7eb2e8f9f7	1439	{
<>	144:ef7eb2e8f9f7	1440	/* Change ADC state to error state */
<>	144:ef7eb2e8f9f7	1441	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<>	144:ef7eb2e8f9f7	1442
<>	144:ef7eb2e8f9f7	1443	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	1444	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	1445	}
<>	144:ef7eb2e8f9f7	1446	}
<>	144:ef7eb2e8f9f7	1447	}
<>	144:ef7eb2e8f9f7	1448
<>	144:ef7eb2e8f9f7	1449	/* Conversion complete callback */
<>	144:ef7eb2e8f9f7	1450	/* Note: into callback, to determine if conversion has been triggered */
<>	144:ef7eb2e8f9f7	1451	/* from EOC or EOS, possibility to use: */
<>	144:ef7eb2e8f9f7	1452	/* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
<>	144:ef7eb2e8f9f7	1453	HAL_ADC_ConvCpltCallback(hadc);
<>	144:ef7eb2e8f9f7	1454
<>	144:ef7eb2e8f9f7	1455
<>	144:ef7eb2e8f9f7	1456	/* Clear regular group conversion flag */
<>	144:ef7eb2e8f9f7	1457	/* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
<>	144:ef7eb2e8f9f7	1458	/* conversion flags clear induces the release of the preserved data.*/
<>	144:ef7eb2e8f9f7	1459	/* Therefore, if the preserved data value is needed, it must be */
<>	144:ef7eb2e8f9f7	1460	/* read preliminarily into HAL_ADC_ConvCpltCallback(). */
<>	144:ef7eb2e8f9f7	1461	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC \| ADC_FLAG_EOS) );
<>	144:ef7eb2e8f9f7	1462	}
<>	144:ef7eb2e8f9f7	1463
<>	144:ef7eb2e8f9f7	1464	/* ========== Check Analog watchdog flags ========== */
<>	144:ef7eb2e8f9f7	1465	if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
<>	144:ef7eb2e8f9f7	1466	{
<>	144:ef7eb2e8f9f7	1467	/* Set ADC state */
<>	144:ef7eb2e8f9f7	1468	SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
<>	144:ef7eb2e8f9f7	1469
<>	144:ef7eb2e8f9f7	1470	/* Level out of window callback */
<>	144:ef7eb2e8f9f7	1471	HAL_ADC_LevelOutOfWindowCallback(hadc);
<>	144:ef7eb2e8f9f7	1472
<>	144:ef7eb2e8f9f7	1473	/* Clear ADC Analog watchdog flag */
<>	144:ef7eb2e8f9f7	1474	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
<>	144:ef7eb2e8f9f7	1475
<>	144:ef7eb2e8f9f7	1476	}
<>	144:ef7eb2e8f9f7	1477
<>	144:ef7eb2e8f9f7	1478
<>	144:ef7eb2e8f9f7	1479	/* ========== Check Overrun flag ========== */
<>	144:ef7eb2e8f9f7	1480	if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
<>	144:ef7eb2e8f9f7	1481	{
<>	144:ef7eb2e8f9f7	1482	/* If overrun is set to overwrite previous data (default setting), */
<>	144:ef7eb2e8f9f7	1483	/* overrun event is not considered as an error. */
<>	144:ef7eb2e8f9f7	1484	/* (cf ref manual "Managing conversions without using the DMA and without */
<>	144:ef7eb2e8f9f7	1485	/* overrun ") */
<>	144:ef7eb2e8f9f7	1486	/* Exception for usage with DMA overrun event always considered as an */
<>	144:ef7eb2e8f9f7	1487	/* error. */
<>	144:ef7eb2e8f9f7	1488	if ((hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) \|\|
<>	144:ef7eb2e8f9f7	1489	HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) )
<>	144:ef7eb2e8f9f7	1490	{
<>	144:ef7eb2e8f9f7	1491	/* Set ADC error code to overrun */
<>	144:ef7eb2e8f9f7	1492	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
<>	144:ef7eb2e8f9f7	1493
<>	144:ef7eb2e8f9f7	1494	/* Clear ADC overrun flag */
<>	144:ef7eb2e8f9f7	1495	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
<>	144:ef7eb2e8f9f7	1496
<>	144:ef7eb2e8f9f7	1497	/* Error callback */
<>	144:ef7eb2e8f9f7	1498	HAL_ADC_ErrorCallback(hadc);
<>	144:ef7eb2e8f9f7	1499	}
<>	144:ef7eb2e8f9f7	1500
<>	144:ef7eb2e8f9f7	1501	/* Clear the Overrun flag */
<>	144:ef7eb2e8f9f7	1502	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
<>	144:ef7eb2e8f9f7	1503	}
<>	144:ef7eb2e8f9f7	1504
<>	144:ef7eb2e8f9f7	1505	}
<>	144:ef7eb2e8f9f7	1506
<>	144:ef7eb2e8f9f7	1507
<>	144:ef7eb2e8f9f7	1508	/**
<>	144:ef7eb2e8f9f7	1509	* @brief Conversion complete callback in non blocking mode
<>	144:ef7eb2e8f9f7	1510	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1511	* @retval None
<>	144:ef7eb2e8f9f7	1512	*/
<>	144:ef7eb2e8f9f7	1513	__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	1514	{
<>	144:ef7eb2e8f9f7	1515	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1516	UNUSED(hadc);
<>	144:ef7eb2e8f9f7	1517
<>	144:ef7eb2e8f9f7	1518	/* NOTE : This function should not be modified. When the callback is needed,
<>	144:ef7eb2e8f9f7	1519	function HAL_ADC_ConvCpltCallback must be implemented in the user file.
<>	144:ef7eb2e8f9f7	1520	*/
<>	144:ef7eb2e8f9f7	1521	}
<>	144:ef7eb2e8f9f7	1522
<>	144:ef7eb2e8f9f7	1523	/**
<>	144:ef7eb2e8f9f7	1524	* @brief Conversion DMA half-transfer callback in non blocking mode
<>	144:ef7eb2e8f9f7	1525	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1526	* @retval None
<>	144:ef7eb2e8f9f7	1527	*/
<>	144:ef7eb2e8f9f7	1528	__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	1529	{
<>	144:ef7eb2e8f9f7	1530	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1531	UNUSED(hadc);
<>	144:ef7eb2e8f9f7	1532
<>	144:ef7eb2e8f9f7	1533	/* NOTE : This function should not be modified. When the callback is needed,
<>	144:ef7eb2e8f9f7	1534	function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
<>	144:ef7eb2e8f9f7	1535	*/
<>	144:ef7eb2e8f9f7	1536	}
<>	144:ef7eb2e8f9f7	1537
<>	144:ef7eb2e8f9f7	1538	/**
<>	144:ef7eb2e8f9f7	1539	* @brief Analog watchdog callback in non blocking mode.
<>	144:ef7eb2e8f9f7	1540	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1541	* @retval None
<>	144:ef7eb2e8f9f7	1542	*/
<>	144:ef7eb2e8f9f7	1543	__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	1544	{
<>	144:ef7eb2e8f9f7	1545	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1546	UNUSED(hadc);
<>	144:ef7eb2e8f9f7	1547
<>	144:ef7eb2e8f9f7	1548	/* NOTE : This function should not be modified. When the callback is needed,
<>	144:ef7eb2e8f9f7	1549	function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file.
<>	144:ef7eb2e8f9f7	1550	*/
<>	144:ef7eb2e8f9f7	1551	}
<>	144:ef7eb2e8f9f7	1552
<>	144:ef7eb2e8f9f7	1553	/**
<>	144:ef7eb2e8f9f7	1554	* @brief ADC error callback in non blocking mode
<>	144:ef7eb2e8f9f7	1555	* (ADC conversion with interruption or transfer by DMA)
<>	144:ef7eb2e8f9f7	1556	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1557	* @retval None
<>	144:ef7eb2e8f9f7	1558	*/
<>	144:ef7eb2e8f9f7	1559	__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
<>	144:ef7eb2e8f9f7	1560	{
<>	144:ef7eb2e8f9f7	1561	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1562	UNUSED(hadc);
<>	144:ef7eb2e8f9f7	1563
<>	144:ef7eb2e8f9f7	1564	/* NOTE : This function should not be modified. When the callback is needed,
<>	144:ef7eb2e8f9f7	1565	function HAL_ADC_ErrorCallback must be implemented in the user file.
<>	144:ef7eb2e8f9f7	1566	*/
<>	144:ef7eb2e8f9f7	1567	}
<>	144:ef7eb2e8f9f7	1568
<>	144:ef7eb2e8f9f7	1569
<>	144:ef7eb2e8f9f7	1570	/**
<>	144:ef7eb2e8f9f7	1571	* @}
<>	144:ef7eb2e8f9f7	1572	*/
<>	144:ef7eb2e8f9f7	1573
<>	144:ef7eb2e8f9f7	1574	/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
<>	144:ef7eb2e8f9f7	1575	* @brief Peripheral Control functions
<>	144:ef7eb2e8f9f7	1576	*
<>	144:ef7eb2e8f9f7	1577	@verbatim
<>	144:ef7eb2e8f9f7	1578	===============================================================================
<>	144:ef7eb2e8f9f7	1579	##### Peripheral Control functions #####
<>	144:ef7eb2e8f9f7	1580	===============================================================================
<>	144:ef7eb2e8f9f7	1581	[..] This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	1582	(+) Configure channels on regular group
<>	144:ef7eb2e8f9f7	1583	(+) Configure the analog watchdog
<>	144:ef7eb2e8f9f7	1584
<>	144:ef7eb2e8f9f7	1585	@endverbatim
<>	144:ef7eb2e8f9f7	1586	* @{
<>	144:ef7eb2e8f9f7	1587	*/
<>	144:ef7eb2e8f9f7	1588
<>	144:ef7eb2e8f9f7	1589	/**
<>	144:ef7eb2e8f9f7	1590	* @brief Configures the the selected channel to be linked to the regular
<>	144:ef7eb2e8f9f7	1591	* group.
<>	144:ef7eb2e8f9f7	1592	* @note In case of usage of internal measurement channels:
<>	144:ef7eb2e8f9f7	1593	* VrefInt/Vbat/TempSensor.
<>	144:ef7eb2e8f9f7	1594	* Sampling time constraints must be respected (sampling time can be
<>	144:ef7eb2e8f9f7	1595	* adjusted in function of ADC clock frequency and sampling time
<>	144:ef7eb2e8f9f7	1596	* setting).
<>	144:ef7eb2e8f9f7	1597	* Refer to device datasheet for timings values, parameters TS_vrefint,
<>	144:ef7eb2e8f9f7	1598	* TS_vbat, TS_temp (values rough order: 5us to 17us).
<>	144:ef7eb2e8f9f7	1599	* These internal paths can be be disabled using function
<>	144:ef7eb2e8f9f7	1600	* HAL_ADC_DeInit().
<>	144:ef7eb2e8f9f7	1601	* @note Possibility to update parameters on the fly:
<>	144:ef7eb2e8f9f7	1602	* This function initializes channel into regular group, following
<>	144:ef7eb2e8f9f7	1603	* calls to this function can be used to reconfigure some parameters
<>	144:ef7eb2e8f9f7	1604	* of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
<>	144:ef7eb2e8f9f7	1605	* the ADC.
<>	144:ef7eb2e8f9f7	1606	* The setting of these parameters is conditioned to ADC state.
<>	144:ef7eb2e8f9f7	1607	* For parameters constraints, see comments of structure
<>	144:ef7eb2e8f9f7	1608	* "ADC_ChannelConfTypeDef".
<>	144:ef7eb2e8f9f7	1609	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1610	* @param sConfig: Structure of ADC channel for regular group.
<>	144:ef7eb2e8f9f7	1611	* @retval HAL status
<>	144:ef7eb2e8f9f7	1612	*/
<>	144:ef7eb2e8f9f7	1613	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
<>	144:ef7eb2e8f9f7	1614	{
<>	144:ef7eb2e8f9f7	1615	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<>	156:95d6b41a828b	1616	__IO uint32_t wait_loop_index = 0U;
<>	144:ef7eb2e8f9f7	1617
<>	144:ef7eb2e8f9f7	1618	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1619	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1620	assert_param(IS_ADC_CHANNEL(sConfig->Channel));
<>	144:ef7eb2e8f9f7	1621	assert_param(IS_ADC_RANK(sConfig->Rank));
<>	144:ef7eb2e8f9f7	1622
<>	144:ef7eb2e8f9f7	1623	if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
<>	144:ef7eb2e8f9f7	1624	{
<>	144:ef7eb2e8f9f7	1625	assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
<>	144:ef7eb2e8f9f7	1626	}
<>	144:ef7eb2e8f9f7	1627
<>	144:ef7eb2e8f9f7	1628	/* Process locked */
<>	144:ef7eb2e8f9f7	1629	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	1630
<>	144:ef7eb2e8f9f7	1631	/* Parameters update conditioned to ADC state: */
<>	144:ef7eb2e8f9f7	1632	/* Parameters that can be updated when ADC is disabled or enabled without */
<>	144:ef7eb2e8f9f7	1633	/* conversion on going on regular group: */
<>	144:ef7eb2e8f9f7	1634	/* - Channel number */
<>	144:ef7eb2e8f9f7	1635	/* - Channel sampling time */
<>	144:ef7eb2e8f9f7	1636	/* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */
<>	144:ef7eb2e8f9f7	1637	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<>	144:ef7eb2e8f9f7	1638	{
<>	144:ef7eb2e8f9f7	1639	/* Configure channel: depending on rank setting, add it or remove it from */
<>	144:ef7eb2e8f9f7	1640	/* ADC conversion sequencer. */
<>	144:ef7eb2e8f9f7	1641	if (sConfig->Rank != ADC_RANK_NONE)
<>	144:ef7eb2e8f9f7	1642	{
<>	144:ef7eb2e8f9f7	1643	/* Regular sequence configuration */
<>	144:ef7eb2e8f9f7	1644	/* Set the channel selection register from the selected channel */
<>	144:ef7eb2e8f9f7	1645	hadc->Instance->CHSELR \|= ADC_CHSELR_CHANNEL(sConfig->Channel);
<>	144:ef7eb2e8f9f7	1646
<>	144:ef7eb2e8f9f7	1647	/* Channel sampling time configuration */
<>	144:ef7eb2e8f9f7	1648	/* Management of parameters "SamplingTimeCommon" and "SamplingTime" */
<>	144:ef7eb2e8f9f7	1649	/* (obsolete): sampling time set in this function with */
<>	144:ef7eb2e8f9f7	1650	/* parameter "SamplingTime" (obsolete) only if not already set into */
<>	144:ef7eb2e8f9f7	1651	/* ADC initialization structure with parameter "SamplingTimeCommon". */
<>	144:ef7eb2e8f9f7	1652	if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
<>	144:ef7eb2e8f9f7	1653	{
<>	144:ef7eb2e8f9f7	1654	/* Modify sampling time if needed (not needed in case of reoccurrence */
<>	144:ef7eb2e8f9f7	1655	/* for several channels programmed consecutively into the sequencer) */
<>	144:ef7eb2e8f9f7	1656	if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc))
<>	144:ef7eb2e8f9f7	1657	{
<>	144:ef7eb2e8f9f7	1658	/* Channel sampling time configuration */
<>	144:ef7eb2e8f9f7	1659	/* Clear the old sample time */
<>	144:ef7eb2e8f9f7	1660	hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
<>	144:ef7eb2e8f9f7	1661
<>	144:ef7eb2e8f9f7	1662	/* Set the new sample time */
<>	144:ef7eb2e8f9f7	1663	hadc->Instance->SMPR \|= ADC_SMPR_SET(sConfig->SamplingTime);
<>	144:ef7eb2e8f9f7	1664	}
<>	144:ef7eb2e8f9f7	1665	}
<>	144:ef7eb2e8f9f7	1666
<>	144:ef7eb2e8f9f7	1667	/* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
<>	144:ef7eb2e8f9f7	1668	/* internal measurement paths enable: If internal channel selected, */
<>	144:ef7eb2e8f9f7	1669	/* enable dedicated internal buffers and path. */
<>	144:ef7eb2e8f9f7	1670	/* Note: these internal measurement paths can be disabled using */
<>	144:ef7eb2e8f9f7	1671	/* HAL_ADC_DeInit() or removing the channel from sequencer with */
<>	144:ef7eb2e8f9f7	1672	/* channel configuration parameter "Rank". */
<>	144:ef7eb2e8f9f7	1673	if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
<>	144:ef7eb2e8f9f7	1674	{
<>	144:ef7eb2e8f9f7	1675	/* If Channel_16 is selected, enable Temp. sensor measurement path. */
<>	144:ef7eb2e8f9f7	1676	/* If Channel_17 is selected, enable VREFINT measurement path. */
<>	144:ef7eb2e8f9f7	1677	/* If Channel_18 is selected, enable VBAT measurement path. */
<>	144:ef7eb2e8f9f7	1678	ADC->CCR \|= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel);
<>	144:ef7eb2e8f9f7	1679
<>	144:ef7eb2e8f9f7	1680	/* If Temp. sensor is selected, wait for stabilization delay */
<>	144:ef7eb2e8f9f7	1681	if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
<>	144:ef7eb2e8f9f7	1682	{
<>	144:ef7eb2e8f9f7	1683	/* Delay for temperature sensor stabilization time */
<>	144:ef7eb2e8f9f7	1684	/* Compute number of CPU cycles to wait for */
<>	156:95d6b41a828b	1685	wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
<>	156:95d6b41a828b	1686	while(wait_loop_index != 0U)
<>	144:ef7eb2e8f9f7	1687	{
<>	144:ef7eb2e8f9f7	1688	wait_loop_index--;
<>	144:ef7eb2e8f9f7	1689	}
<>	144:ef7eb2e8f9f7	1690	}
<>	144:ef7eb2e8f9f7	1691	}
<>	144:ef7eb2e8f9f7	1692	}
<>	144:ef7eb2e8f9f7	1693	else
<>	144:ef7eb2e8f9f7	1694	{
<>	144:ef7eb2e8f9f7	1695	/* Regular sequence configuration */
<>	144:ef7eb2e8f9f7	1696	/* Reset the channel selection register from the selected channel */
<>	144:ef7eb2e8f9f7	1697	hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel);
<>	144:ef7eb2e8f9f7	1698
<>	144:ef7eb2e8f9f7	1699	/* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
<>	144:ef7eb2e8f9f7	1700	/* internal measurement paths disable: If internal channel selected, */
<>	144:ef7eb2e8f9f7	1701	/* disable dedicated internal buffers and path. */
<>	144:ef7eb2e8f9f7	1702	if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
<>	144:ef7eb2e8f9f7	1703	{
<>	144:ef7eb2e8f9f7	1704	/* If Channel_16 is selected, disable Temp. sensor measurement path. */
<>	144:ef7eb2e8f9f7	1705	/* If Channel_17 is selected, disable VREFINT measurement path. */
<>	144:ef7eb2e8f9f7	1706	/* If Channel_18 is selected, disable VBAT measurement path. */
<>	144:ef7eb2e8f9f7	1707	ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel);
<>	144:ef7eb2e8f9f7	1708	}
<>	144:ef7eb2e8f9f7	1709	}
<>	144:ef7eb2e8f9f7	1710
<>	144:ef7eb2e8f9f7	1711	}
<>	144:ef7eb2e8f9f7	1712
<>	144:ef7eb2e8f9f7	1713	/* If a conversion is on going on regular group, no update on regular */
<>	144:ef7eb2e8f9f7	1714	/* channel could be done on neither of the channel configuration structure */
<>	144:ef7eb2e8f9f7	1715	/* parameters. */
<>	144:ef7eb2e8f9f7	1716	else
<>	144:ef7eb2e8f9f7	1717	{
<>	144:ef7eb2e8f9f7	1718	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	1719	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<>	144:ef7eb2e8f9f7	1720
<>	144:ef7eb2e8f9f7	1721	tmp_hal_status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1722	}
<>	144:ef7eb2e8f9f7	1723
<>	144:ef7eb2e8f9f7	1724	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1725	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1726
<>	144:ef7eb2e8f9f7	1727	/* Return function status */
<>	144:ef7eb2e8f9f7	1728	return tmp_hal_status;
<>	144:ef7eb2e8f9f7	1729	}
<>	144:ef7eb2e8f9f7	1730
<>	144:ef7eb2e8f9f7	1731
<>	144:ef7eb2e8f9f7	1732	/**
<>	144:ef7eb2e8f9f7	1733	* @brief Configures the analog watchdog.
<>	144:ef7eb2e8f9f7	1734	* @note Possibility to update parameters on the fly:
<>	144:ef7eb2e8f9f7	1735	* This function initializes the selected analog watchdog, following
<>	144:ef7eb2e8f9f7	1736	* calls to this function can be used to reconfigure some parameters
<>	144:ef7eb2e8f9f7	1737	* of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
<>	144:ef7eb2e8f9f7	1738	* the ADC.
<>	144:ef7eb2e8f9f7	1739	* The setting of these parameters is conditioned to ADC state.
<>	144:ef7eb2e8f9f7	1740	* For parameters constraints, see comments of structure
<>	144:ef7eb2e8f9f7	1741	* "ADC_AnalogWDGConfTypeDef".
<>	144:ef7eb2e8f9f7	1742	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1743	* @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
<>	144:ef7eb2e8f9f7	1744	* @retval HAL status
<>	144:ef7eb2e8f9f7	1745	*/
<>	144:ef7eb2e8f9f7	1746	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
<>	144:ef7eb2e8f9f7	1747	{
<>	144:ef7eb2e8f9f7	1748	HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<>	144:ef7eb2e8f9f7	1749
<>	144:ef7eb2e8f9f7	1750	uint32_t tmpAWDHighThresholdShifted;
<>	144:ef7eb2e8f9f7	1751	uint32_t tmpAWDLowThresholdShifted;
<>	144:ef7eb2e8f9f7	1752
<>	144:ef7eb2e8f9f7	1753	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1754	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1755	assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
<>	144:ef7eb2e8f9f7	1756	assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
<>	144:ef7eb2e8f9f7	1757
<>	144:ef7eb2e8f9f7	1758	/* Verify if threshold is within the selected ADC resolution */
<>	144:ef7eb2e8f9f7	1759	assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
<>	144:ef7eb2e8f9f7	1760	assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
<>	144:ef7eb2e8f9f7	1761
<>	144:ef7eb2e8f9f7	1762	if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)
<>	144:ef7eb2e8f9f7	1763	{
<>	144:ef7eb2e8f9f7	1764	assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
<>	144:ef7eb2e8f9f7	1765	}
<>	144:ef7eb2e8f9f7	1766
<>	144:ef7eb2e8f9f7	1767	/* Process locked */
<>	144:ef7eb2e8f9f7	1768	__HAL_LOCK(hadc);
<>	144:ef7eb2e8f9f7	1769
<>	144:ef7eb2e8f9f7	1770	/* Parameters update conditioned to ADC state: */
<>	144:ef7eb2e8f9f7	1771	/* Parameters that can be updated when ADC is disabled or enabled without */
<>	144:ef7eb2e8f9f7	1772	/* conversion on going on regular group: */
<>	144:ef7eb2e8f9f7	1773	/* - Analog watchdog channels */
<>	144:ef7eb2e8f9f7	1774	/* - Analog watchdog thresholds */
<>	144:ef7eb2e8f9f7	1775	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<>	144:ef7eb2e8f9f7	1776	{
<>	144:ef7eb2e8f9f7	1777	/* Configuration of analog watchdog: */
<>	144:ef7eb2e8f9f7	1778	/* - Set the analog watchdog enable mode: one or overall group of */
<>	144:ef7eb2e8f9f7	1779	/* channels. */
<>	144:ef7eb2e8f9f7	1780	/* - Set the Analog watchdog channel (is not used if watchdog */
<>	144:ef7eb2e8f9f7	1781	/* mode "all channels": ADC_CFGR_AWD1SGL=0). */
<>	144:ef7eb2e8f9f7	1782	hadc->Instance->CFGR1 &= ~( ADC_CFGR1_AWDSGL \|
<>	144:ef7eb2e8f9f7	1783	ADC_CFGR1_AWDEN \|
<>	144:ef7eb2e8f9f7	1784	ADC_CFGR1_AWDCH );
<>	144:ef7eb2e8f9f7	1785
<>	144:ef7eb2e8f9f7	1786	hadc->Instance->CFGR1 \|= ( AnalogWDGConfig->WatchdogMode \|
<>	144:ef7eb2e8f9f7	1787	ADC_CFGR_AWDCH(AnalogWDGConfig->Channel) );
<>	144:ef7eb2e8f9f7	1788
<>	144:ef7eb2e8f9f7	1789	/* Shift the offset in function of the selected ADC resolution: Thresholds*/
<>	144:ef7eb2e8f9f7	1790	/* have to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
<>	144:ef7eb2e8f9f7	1791	tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
<>	144:ef7eb2e8f9f7	1792	tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
<>	144:ef7eb2e8f9f7	1793
<>	144:ef7eb2e8f9f7	1794	/* Set the high and low thresholds */
<>	144:ef7eb2e8f9f7	1795	hadc->Instance->TR &= ~(ADC_TR_HT \| ADC_TR_LT);
<>	144:ef7eb2e8f9f7	1796	hadc->Instance->TR \|= ( ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) \|
<>	144:ef7eb2e8f9f7	1797	tmpAWDLowThresholdShifted );
<>	144:ef7eb2e8f9f7	1798
<>	144:ef7eb2e8f9f7	1799	/* Clear the ADC Analog watchdog flag (in case of left enabled by */
<>	144:ef7eb2e8f9f7	1800	/* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
<>	144:ef7eb2e8f9f7	1801	/* or HAL_ADC_PollForEvent(). */
<>	144:ef7eb2e8f9f7	1802	__HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD);
<>	144:ef7eb2e8f9f7	1803
<>	144:ef7eb2e8f9f7	1804	/* Configure ADC Analog watchdog interrupt */
<>	144:ef7eb2e8f9f7	1805	if(AnalogWDGConfig->ITMode == ENABLE)
<>	144:ef7eb2e8f9f7	1806	{
<>	144:ef7eb2e8f9f7	1807	/* Enable the ADC Analog watchdog interrupt */
<>	144:ef7eb2e8f9f7	1808	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
<>	144:ef7eb2e8f9f7	1809	}
<>	144:ef7eb2e8f9f7	1810	else
<>	144:ef7eb2e8f9f7	1811	{
<>	144:ef7eb2e8f9f7	1812	/* Disable the ADC Analog watchdog interrupt */
<>	144:ef7eb2e8f9f7	1813	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
<>	144:ef7eb2e8f9f7	1814	}
<>	144:ef7eb2e8f9f7	1815
<>	144:ef7eb2e8f9f7	1816	}
<>	144:ef7eb2e8f9f7	1817	/* If a conversion is on going on regular group, no update could be done */
<>	144:ef7eb2e8f9f7	1818	/* on neither of the AWD configuration structure parameters. */
<>	144:ef7eb2e8f9f7	1819	else
<>	144:ef7eb2e8f9f7	1820	{
<>	144:ef7eb2e8f9f7	1821	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	1822	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<>	144:ef7eb2e8f9f7	1823
<>	144:ef7eb2e8f9f7	1824	tmp_hal_status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1825	}
<>	144:ef7eb2e8f9f7	1826
<>	144:ef7eb2e8f9f7	1827
<>	144:ef7eb2e8f9f7	1828	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1829	__HAL_UNLOCK(hadc);
<>	144:ef7eb2e8f9f7	1830
<>	144:ef7eb2e8f9f7	1831	/* Return function status */
<>	144:ef7eb2e8f9f7	1832	return tmp_hal_status;
<>	144:ef7eb2e8f9f7	1833	}
<>	144:ef7eb2e8f9f7	1834
<>	144:ef7eb2e8f9f7	1835
<>	144:ef7eb2e8f9f7	1836	/**
<>	144:ef7eb2e8f9f7	1837	* @}
<>	144:ef7eb2e8f9f7	1838	*/
<>	144:ef7eb2e8f9f7	1839
<>	144:ef7eb2e8f9f7	1840
<>	144:ef7eb2e8f9f7	1841	/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
<>	144:ef7eb2e8f9f7	1842	* @brief Peripheral State functions
<>	144:ef7eb2e8f9f7	1843	*
<>	144:ef7eb2e8f9f7	1844	@verbatim
<>	144:ef7eb2e8f9f7	1845	===============================================================================
<>	144:ef7eb2e8f9f7	1846	##### Peripheral State and Errors functions #####
<>	144:ef7eb2e8f9f7	1847	===============================================================================
<>	144:ef7eb2e8f9f7	1848	[..]
<>	144:ef7eb2e8f9f7	1849	This subsection provides functions to get in run-time the status of the
<>	144:ef7eb2e8f9f7	1850	peripheral.
<>	144:ef7eb2e8f9f7	1851	(+) Check the ADC state
<>	144:ef7eb2e8f9f7	1852	(+) Check the ADC error code
<>	144:ef7eb2e8f9f7	1853
<>	144:ef7eb2e8f9f7	1854	@endverbatim
<>	144:ef7eb2e8f9f7	1855	* @{
<>	144:ef7eb2e8f9f7	1856	*/
<>	144:ef7eb2e8f9f7	1857
<>	144:ef7eb2e8f9f7	1858	/**
<>	144:ef7eb2e8f9f7	1859	* @brief Return the ADC state
<>	144:ef7eb2e8f9f7	1860	* @note ADC state machine is managed by bitfields, ADC status must be
<>	144:ef7eb2e8f9f7	1861	* compared with states bits.
<>	144:ef7eb2e8f9f7	1862	* For example:
<>	144:ef7eb2e8f9f7	1863	* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
<>	144:ef7eb2e8f9f7	1864	* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
<>	144:ef7eb2e8f9f7	1865	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1866	* @retval HAL state
<>	144:ef7eb2e8f9f7	1867	*/
<>	144:ef7eb2e8f9f7	1868	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	1869	{
<>	144:ef7eb2e8f9f7	1870	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1871	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	1872
<>	144:ef7eb2e8f9f7	1873	/* Return ADC state */
<>	144:ef7eb2e8f9f7	1874	return hadc->State;
<>	144:ef7eb2e8f9f7	1875	}
<>	144:ef7eb2e8f9f7	1876
<>	144:ef7eb2e8f9f7	1877	/**
<>	144:ef7eb2e8f9f7	1878	* @brief Return the ADC error code
<>	144:ef7eb2e8f9f7	1879	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1880	* @retval ADC Error Code
<>	144:ef7eb2e8f9f7	1881	*/
<>	144:ef7eb2e8f9f7	1882	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
<>	144:ef7eb2e8f9f7	1883	{
<>	144:ef7eb2e8f9f7	1884	return hadc->ErrorCode;
<>	144:ef7eb2e8f9f7	1885	}
<>	144:ef7eb2e8f9f7	1886
<>	144:ef7eb2e8f9f7	1887	/**
<>	144:ef7eb2e8f9f7	1888	* @}
<>	144:ef7eb2e8f9f7	1889	*/
<>	144:ef7eb2e8f9f7	1890
<>	144:ef7eb2e8f9f7	1891	/**
<>	144:ef7eb2e8f9f7	1892	* @}
<>	144:ef7eb2e8f9f7	1893	*/
<>	144:ef7eb2e8f9f7	1894
<>	144:ef7eb2e8f9f7	1895	/** @defgroup ADC_Private_Functions ADC Private Functions
<>	144:ef7eb2e8f9f7	1896	* @{
<>	144:ef7eb2e8f9f7	1897	*/
<>	144:ef7eb2e8f9f7	1898
<>	144:ef7eb2e8f9f7	1899	/**
<>	144:ef7eb2e8f9f7	1900	* @brief Enable the selected ADC.
<>	144:ef7eb2e8f9f7	1901	* @note Prerequisite condition to use this function: ADC must be disabled
<>	144:ef7eb2e8f9f7	1902	* and voltage regulator must be enabled (done into HAL_ADC_Init()).
<>	144:ef7eb2e8f9f7	1903	* @note If low power mode AutoPowerOff is enabled, power-on/off phases are
<>	144:ef7eb2e8f9f7	1904	* performed automatically by hardware.
<>	144:ef7eb2e8f9f7	1905	* In this mode, this function is useless and must not be called because
<>	144:ef7eb2e8f9f7	1906	* flag ADC_FLAG_RDY is not usable.
<>	144:ef7eb2e8f9f7	1907	* Therefore, this function must be called under condition of
<>	144:ef7eb2e8f9f7	1908	* "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)".
<>	144:ef7eb2e8f9f7	1909	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1910	* @retval HAL status.
<>	144:ef7eb2e8f9f7	1911	*/
<>	144:ef7eb2e8f9f7	1912	static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	1913	{
<>	156:95d6b41a828b	1914	uint32_t tickstart = 0U;
<>	156:95d6b41a828b	1915	__IO uint32_t wait_loop_index = 0U;
<>	144:ef7eb2e8f9f7	1916
<>	144:ef7eb2e8f9f7	1917	/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
<>	144:ef7eb2e8f9f7	1918	/* enabling phase not yet completed: flag ADC ready not yet set). */
<>	144:ef7eb2e8f9f7	1919	/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
<>	144:ef7eb2e8f9f7	1920	/* causes: ADC clock not running, ...). */
<>	144:ef7eb2e8f9f7	1921	if (ADC_IS_ENABLE(hadc) == RESET)
<>	144:ef7eb2e8f9f7	1922	{
<>	144:ef7eb2e8f9f7	1923	/* Check if conditions to enable the ADC are fulfilled */
<>	144:ef7eb2e8f9f7	1924	if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
<>	144:ef7eb2e8f9f7	1925	{
<>	144:ef7eb2e8f9f7	1926	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	1927	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	1928
<>	144:ef7eb2e8f9f7	1929	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	1930	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	1931
<>	144:ef7eb2e8f9f7	1932	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1933	}
<>	144:ef7eb2e8f9f7	1934
<>	144:ef7eb2e8f9f7	1935	/* Enable the ADC peripheral */
<>	144:ef7eb2e8f9f7	1936	__HAL_ADC_ENABLE(hadc);
<>	144:ef7eb2e8f9f7	1937
<>	144:ef7eb2e8f9f7	1938	/* Delay for ADC stabilization time */
<>	144:ef7eb2e8f9f7	1939	/* Compute number of CPU cycles to wait for */
<>	156:95d6b41a828b	1940	wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
<>	156:95d6b41a828b	1941	while(wait_loop_index != 0U)
<>	144:ef7eb2e8f9f7	1942	{
<>	144:ef7eb2e8f9f7	1943	wait_loop_index--;
<>	144:ef7eb2e8f9f7	1944	}
<>	144:ef7eb2e8f9f7	1945
<>	144:ef7eb2e8f9f7	1946	/* Get tick count */
<>	144:ef7eb2e8f9f7	1947	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1948
<>	144:ef7eb2e8f9f7	1949	/* Wait for ADC effectively enabled */
<>	144:ef7eb2e8f9f7	1950	while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
<>	144:ef7eb2e8f9f7	1951	{
<>	144:ef7eb2e8f9f7	1952	if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
<>	144:ef7eb2e8f9f7	1953	{
<>	144:ef7eb2e8f9f7	1954	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	1955	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	1956
<>	144:ef7eb2e8f9f7	1957	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	1958	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	1959
<>	144:ef7eb2e8f9f7	1960	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1961	}
<>	144:ef7eb2e8f9f7	1962	}
<>	144:ef7eb2e8f9f7	1963
<>	144:ef7eb2e8f9f7	1964	}
<>	144:ef7eb2e8f9f7	1965
<>	144:ef7eb2e8f9f7	1966	/* Return HAL status */
<>	144:ef7eb2e8f9f7	1967	return HAL_OK;
<>	144:ef7eb2e8f9f7	1968	}
<>	144:ef7eb2e8f9f7	1969
<>	144:ef7eb2e8f9f7	1970	/**
<>	144:ef7eb2e8f9f7	1971	* @brief Disable the selected ADC.
<>	144:ef7eb2e8f9f7	1972	* @note Prerequisite condition to use this function: ADC conversions must be
<>	144:ef7eb2e8f9f7	1973	* stopped.
<>	144:ef7eb2e8f9f7	1974	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	1975	* @retval HAL status.
<>	144:ef7eb2e8f9f7	1976	*/
<>	144:ef7eb2e8f9f7	1977	static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	1978	{
<>	156:95d6b41a828b	1979	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	1980
<>	144:ef7eb2e8f9f7	1981	/* Verification if ADC is not already disabled: */
<>	144:ef7eb2e8f9f7	1982	/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
<>	144:ef7eb2e8f9f7	1983	/* disabled. */
<>	144:ef7eb2e8f9f7	1984	if (ADC_IS_ENABLE(hadc) != RESET)
<>	144:ef7eb2e8f9f7	1985	{
<>	144:ef7eb2e8f9f7	1986	/* Check if conditions to disable the ADC are fulfilled */
<>	144:ef7eb2e8f9f7	1987	if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
<>	144:ef7eb2e8f9f7	1988	{
<>	144:ef7eb2e8f9f7	1989	/* Disable the ADC peripheral */
<>	144:ef7eb2e8f9f7	1990	__HAL_ADC_DISABLE(hadc);
<>	144:ef7eb2e8f9f7	1991	}
<>	144:ef7eb2e8f9f7	1992	else
<>	144:ef7eb2e8f9f7	1993	{
<>	144:ef7eb2e8f9f7	1994	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	1995	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	1996
<>	144:ef7eb2e8f9f7	1997	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	1998	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	1999
<>	144:ef7eb2e8f9f7	2000	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2001	}
<>	144:ef7eb2e8f9f7	2002
<>	144:ef7eb2e8f9f7	2003	/* Wait for ADC effectively disabled */
<>	144:ef7eb2e8f9f7	2004	/* Get tick count */
<>	144:ef7eb2e8f9f7	2005	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2006
<>	144:ef7eb2e8f9f7	2007	while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
<>	144:ef7eb2e8f9f7	2008	{
<>	144:ef7eb2e8f9f7	2009	if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
<>	144:ef7eb2e8f9f7	2010	{
<>	144:ef7eb2e8f9f7	2011	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	2012	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2013
<>	144:ef7eb2e8f9f7	2014	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	2015	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2016
<>	144:ef7eb2e8f9f7	2017	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2018	}
<>	144:ef7eb2e8f9f7	2019	}
<>	144:ef7eb2e8f9f7	2020	}
<>	144:ef7eb2e8f9f7	2021
<>	144:ef7eb2e8f9f7	2022	/* Return HAL status */
<>	144:ef7eb2e8f9f7	2023	return HAL_OK;
<>	144:ef7eb2e8f9f7	2024	}
<>	144:ef7eb2e8f9f7	2025
<>	144:ef7eb2e8f9f7	2026
<>	144:ef7eb2e8f9f7	2027	/**
<>	144:ef7eb2e8f9f7	2028	* @brief Stop ADC conversion.
<>	144:ef7eb2e8f9f7	2029	* @note Prerequisite condition to use this function: ADC conversions must be
<>	144:ef7eb2e8f9f7	2030	* stopped to disable the ADC.
<>	144:ef7eb2e8f9f7	2031	* @param hadc: ADC handle
<>	144:ef7eb2e8f9f7	2032	* @retval HAL status.
<>	144:ef7eb2e8f9f7	2033	*/
<>	144:ef7eb2e8f9f7	2034	static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc)
<>	144:ef7eb2e8f9f7	2035	{
<>	156:95d6b41a828b	2036	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	2037
<>	144:ef7eb2e8f9f7	2038	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2039	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<>	144:ef7eb2e8f9f7	2040
<>	144:ef7eb2e8f9f7	2041	/* Verification if ADC is not already stopped on regular group to bypass */
<>	144:ef7eb2e8f9f7	2042	/* this function if not needed. */
<>	144:ef7eb2e8f9f7	2043	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
<>	144:ef7eb2e8f9f7	2044	{
<>	144:ef7eb2e8f9f7	2045
<>	144:ef7eb2e8f9f7	2046	/* Stop potential conversion on going on regular group */
<>	144:ef7eb2e8f9f7	2047	/* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
<>	144:ef7eb2e8f9f7	2048	if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
<>	144:ef7eb2e8f9f7	2049	HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
<>	144:ef7eb2e8f9f7	2050	{
<>	144:ef7eb2e8f9f7	2051	/* Stop conversions on regular group */
<>	144:ef7eb2e8f9f7	2052	hadc->Instance->CR \|= ADC_CR_ADSTP;
<>	144:ef7eb2e8f9f7	2053	}
<>	144:ef7eb2e8f9f7	2054
<>	144:ef7eb2e8f9f7	2055	/* Wait for conversion effectively stopped */
<>	144:ef7eb2e8f9f7	2056	/* Get tick count */
<>	144:ef7eb2e8f9f7	2057	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2058
<>	144:ef7eb2e8f9f7	2059	while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET)
<>	144:ef7eb2e8f9f7	2060	{
<>	144:ef7eb2e8f9f7	2061	if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
<>	144:ef7eb2e8f9f7	2062	{
<>	144:ef7eb2e8f9f7	2063	/* Update ADC state machine to error */
<>	144:ef7eb2e8f9f7	2064	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2065
<>	144:ef7eb2e8f9f7	2066	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	2067	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2068
<>	144:ef7eb2e8f9f7	2069	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2070	}
<>	144:ef7eb2e8f9f7	2071	}
<>	144:ef7eb2e8f9f7	2072
<>	144:ef7eb2e8f9f7	2073	}
<>	144:ef7eb2e8f9f7	2074
<>	144:ef7eb2e8f9f7	2075	/* Return HAL status */
<>	144:ef7eb2e8f9f7	2076	return HAL_OK;
<>	144:ef7eb2e8f9f7	2077	}
<>	144:ef7eb2e8f9f7	2078
<>	144:ef7eb2e8f9f7	2079
<>	144:ef7eb2e8f9f7	2080	/**
<>	144:ef7eb2e8f9f7	2081	* @brief DMA transfer complete callback.
<>	144:ef7eb2e8f9f7	2082	* @param hdma: pointer to DMA handle.
<>	144:ef7eb2e8f9f7	2083	* @retval None
<>	144:ef7eb2e8f9f7	2084	*/
<>	144:ef7eb2e8f9f7	2085	static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2086	{
<>	144:ef7eb2e8f9f7	2087	/* Retrieve ADC handle corresponding to current DMA handle */
<>	144:ef7eb2e8f9f7	2088	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2089
<>	144:ef7eb2e8f9f7	2090	/* Update state machine on conversion status if not in error state */
<>	144:ef7eb2e8f9f7	2091	if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL \| HAL_ADC_STATE_ERROR_DMA))
<>	144:ef7eb2e8f9f7	2092	{
<>	144:ef7eb2e8f9f7	2093	/* Set ADC state */
<>	144:ef7eb2e8f9f7	2094	SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<>	144:ef7eb2e8f9f7	2095
<>	144:ef7eb2e8f9f7	2096	/* Determine whether any further conversion upcoming on group regular */
<>	144:ef7eb2e8f9f7	2097	/* by external trigger, continuous mode or scan sequence on going. */
<>	144:ef7eb2e8f9f7	2098	if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<>	144:ef7eb2e8f9f7	2099	(hadc->Init.ContinuousConvMode == DISABLE) )
<>	144:ef7eb2e8f9f7	2100	{
<>	144:ef7eb2e8f9f7	2101	/* If End of Sequence is reached, disable interrupts */
<>	144:ef7eb2e8f9f7	2102	if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
<>	144:ef7eb2e8f9f7	2103	{
<>	144:ef7eb2e8f9f7	2104	/* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
<>	144:ef7eb2e8f9f7	2105	/* ADSTART==0 (no conversion on going) */
<>	144:ef7eb2e8f9f7	2106	if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
<>	144:ef7eb2e8f9f7	2107	{
<>	144:ef7eb2e8f9f7	2108	/* Disable ADC end of single conversion interrupt on group regular */
<>	144:ef7eb2e8f9f7	2109	/* Note: Overrun interrupt was enabled with EOC interrupt in */
<>	144:ef7eb2e8f9f7	2110	/* HAL_Start_IT(), but is not disabled here because can be used */
<>	144:ef7eb2e8f9f7	2111	/* by overrun IRQ process below. */
<>	144:ef7eb2e8f9f7	2112	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC \| ADC_IT_EOS);
<>	144:ef7eb2e8f9f7	2113
<>	144:ef7eb2e8f9f7	2114	/* Set ADC state */
<>	144:ef7eb2e8f9f7	2115	ADC_STATE_CLR_SET(hadc->State,
<>	144:ef7eb2e8f9f7	2116	HAL_ADC_STATE_REG_BUSY,
<>	144:ef7eb2e8f9f7	2117	HAL_ADC_STATE_READY);
<>	144:ef7eb2e8f9f7	2118	}
<>	144:ef7eb2e8f9f7	2119	else
<>	144:ef7eb2e8f9f7	2120	{
<>	144:ef7eb2e8f9f7	2121	/* Change ADC state to error state */
<>	144:ef7eb2e8f9f7	2122	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<>	144:ef7eb2e8f9f7	2123
<>	144:ef7eb2e8f9f7	2124	/* Set ADC error code to ADC IP internal error */
<>	144:ef7eb2e8f9f7	2125	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<>	144:ef7eb2e8f9f7	2126	}
<>	144:ef7eb2e8f9f7	2127	}
<>	144:ef7eb2e8f9f7	2128	}
<>	144:ef7eb2e8f9f7	2129
<>	144:ef7eb2e8f9f7	2130	/* Conversion complete callback */
<>	144:ef7eb2e8f9f7	2131	HAL_ADC_ConvCpltCallback(hadc);
<>	144:ef7eb2e8f9f7	2132	}
<>	144:ef7eb2e8f9f7	2133	else
<>	144:ef7eb2e8f9f7	2134	{
<>	144:ef7eb2e8f9f7	2135	/* Call DMA error callback */
<>	144:ef7eb2e8f9f7	2136	hadc->DMA_Handle->XferErrorCallback(hdma);
<>	144:ef7eb2e8f9f7	2137	}
<>	144:ef7eb2e8f9f7	2138
<>	144:ef7eb2e8f9f7	2139	}
<>	144:ef7eb2e8f9f7	2140
<>	144:ef7eb2e8f9f7	2141	/**
<>	144:ef7eb2e8f9f7	2142	* @brief DMA half transfer complete callback.
<>	144:ef7eb2e8f9f7	2143	* @param hdma: pointer to DMA handle.
<>	144:ef7eb2e8f9f7	2144	* @retval None
<>	144:ef7eb2e8f9f7	2145	*/
<>	144:ef7eb2e8f9f7	2146	static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2147	{
<>	144:ef7eb2e8f9f7	2148	/* Retrieve ADC handle corresponding to current DMA handle */
<>	144:ef7eb2e8f9f7	2149	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2150
<>	144:ef7eb2e8f9f7	2151	/* Half conversion callback */
<>	144:ef7eb2e8f9f7	2152	HAL_ADC_ConvHalfCpltCallback(hadc);
<>	144:ef7eb2e8f9f7	2153	}
<>	144:ef7eb2e8f9f7	2154
<>	144:ef7eb2e8f9f7	2155	/**
<>	144:ef7eb2e8f9f7	2156	* @brief DMA error callback
<>	144:ef7eb2e8f9f7	2157	* @param hdma: pointer to DMA handle.
<>	144:ef7eb2e8f9f7	2158	* @retval None
<>	144:ef7eb2e8f9f7	2159	*/
<>	144:ef7eb2e8f9f7	2160	static void ADC_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2161	{
<>	144:ef7eb2e8f9f7	2162	/* Retrieve ADC handle corresponding to current DMA handle */
<>	144:ef7eb2e8f9f7	2163	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2164
<>	144:ef7eb2e8f9f7	2165	/* Set ADC state */
<>	144:ef7eb2e8f9f7	2166	SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<>	144:ef7eb2e8f9f7	2167
<>	144:ef7eb2e8f9f7	2168	/* Set ADC error code to DMA error */
<>	144:ef7eb2e8f9f7	2169	SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
<>	144:ef7eb2e8f9f7	2170
<>	144:ef7eb2e8f9f7	2171	/* Error callback */
<>	144:ef7eb2e8f9f7	2172	HAL_ADC_ErrorCallback(hadc);
<>	144:ef7eb2e8f9f7	2173	}
<>	144:ef7eb2e8f9f7	2174
<>	144:ef7eb2e8f9f7	2175	/**
<>	144:ef7eb2e8f9f7	2176	* @}
<>	144:ef7eb2e8f9f7	2177	*/
<>	144:ef7eb2e8f9f7	2178
<>	144:ef7eb2e8f9f7	2179	#endif /* HAL_ADC_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	2180	/**
<>	144:ef7eb2e8f9f7	2181	* @}
<>	144:ef7eb2e8f9f7	2182	*/
<>	144:ef7eb2e8f9f7	2183
<>	144:ef7eb2e8f9f7	2184	/**
<>	144:ef7eb2e8f9f7	2185	* @}
<>	144:ef7eb2e8f9f7	2186	*/
<>	144:ef7eb2e8f9f7	2187
<>	144:ef7eb2e8f9f7	2188	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/