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cmsis/BUILD/mbed/TARGET_EFM32ZG_STK3200/TOOLCHAIN_IAR/em_qspi.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /***************************************************************************//**
AnnaBridge 189:f392fc9709a3 2 * @file em_qspi.h
AnnaBridge 189:f392fc9709a3 3 * @brief QSPI Octal-SPI Flash Controller API
AnnaBridge 189:f392fc9709a3 4 * @version 5.3.3
AnnaBridge 189:f392fc9709a3 5 *******************************************************************************
AnnaBridge 189:f392fc9709a3 6 * # License
AnnaBridge 189:f392fc9709a3 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 189:f392fc9709a3 8 *******************************************************************************
AnnaBridge 189:f392fc9709a3 9 *
AnnaBridge 189:f392fc9709a3 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 189:f392fc9709a3 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 189:f392fc9709a3 12 * freely, subject to the following restrictions:
AnnaBridge 189:f392fc9709a3 13 *
AnnaBridge 189:f392fc9709a3 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 189:f392fc9709a3 15 * claim that you wrote the original software.
AnnaBridge 189:f392fc9709a3 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 189:f392fc9709a3 17 * misrepresented as being the original software.
AnnaBridge 189:f392fc9709a3 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 189:f392fc9709a3 19 *
AnnaBridge 189:f392fc9709a3 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
AnnaBridge 189:f392fc9709a3 21 * obligation to support this Software. Silicon Labs is providing the
AnnaBridge 189:f392fc9709a3 22 * Software "AS IS", with no express or implied warranties of any kind,
AnnaBridge 189:f392fc9709a3 23 * including, but not limited to, any implied warranties of merchantability
AnnaBridge 189:f392fc9709a3 24 * or fitness for any particular purpose or warranties against infringement
AnnaBridge 189:f392fc9709a3 25 * of any proprietary rights of a third party.
AnnaBridge 189:f392fc9709a3 26 *
AnnaBridge 189:f392fc9709a3 27 * Silicon Labs will not be liable for any consequential, incidental, or
AnnaBridge 189:f392fc9709a3 28 * special damages, or any other relief, or for any claim by any third party,
AnnaBridge 189:f392fc9709a3 29 * arising from your use of this Software.
AnnaBridge 189:f392fc9709a3 30 *
AnnaBridge 189:f392fc9709a3 31 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 32
AnnaBridge 189:f392fc9709a3 33 #ifndef EM_QSPI_H
AnnaBridge 189:f392fc9709a3 34 #define EM_QSPI_H
AnnaBridge 189:f392fc9709a3 35
AnnaBridge 189:f392fc9709a3 36 #include "em_device.h"
AnnaBridge 189:f392fc9709a3 37 #if defined(QSPI_COUNT) && (QSPI_COUNT > 0)
AnnaBridge 189:f392fc9709a3 38
AnnaBridge 189:f392fc9709a3 39 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 40 extern "C" {
AnnaBridge 189:f392fc9709a3 41 #endif
AnnaBridge 189:f392fc9709a3 42
AnnaBridge 189:f392fc9709a3 43 #include "em_bus.h"
AnnaBridge 189:f392fc9709a3 44 #include <stdbool.h>
AnnaBridge 189:f392fc9709a3 45
AnnaBridge 189:f392fc9709a3 46 /***************************************************************************//**
AnnaBridge 189:f392fc9709a3 47 * @addtogroup emlib
AnnaBridge 189:f392fc9709a3 48 * @{
AnnaBridge 189:f392fc9709a3 49 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 50
AnnaBridge 189:f392fc9709a3 51 /***************************************************************************//**
AnnaBridge 189:f392fc9709a3 52 * @addtogroup QSPI
AnnaBridge 189:f392fc9709a3 53 * @{
AnnaBridge 189:f392fc9709a3 54 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 55
AnnaBridge 189:f392fc9709a3 56 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 57 ******************************* DEFINES ***********************************
AnnaBridge 189:f392fc9709a3 58 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 59
AnnaBridge 189:f392fc9709a3 60 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 61 ******************************** ENUMS ************************************
AnnaBridge 189:f392fc9709a3 62 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 63
AnnaBridge 189:f392fc9709a3 64 /** Transfer type. */
AnnaBridge 189:f392fc9709a3 65 typedef enum {
AnnaBridge 189:f392fc9709a3 66 /** Single IO mode. DQ0 used for output and DQ1 as input. */
AnnaBridge 189:f392fc9709a3 67 qspiTransferSingle = 0,
AnnaBridge 189:f392fc9709a3 68
AnnaBridge 189:f392fc9709a3 69 /** Dual I/O transfer. DQ0 and DQ1 are used as both inputs and outputs. */
AnnaBridge 189:f392fc9709a3 70 qspiTransferDual = 1,
AnnaBridge 189:f392fc9709a3 71
AnnaBridge 189:f392fc9709a3 72 /** Quad I/O transfer. DQ0, DQ1, DQ2 and DQ3 are used as both inputs and outputs. */
AnnaBridge 189:f392fc9709a3 73 qspiTransferQuad = 2,
AnnaBridge 189:f392fc9709a3 74
AnnaBridge 189:f392fc9709a3 75 /** Octal I/O transfer. DQ[7:0] are used as both inputs and outputs. */
AnnaBridge 189:f392fc9709a3 76 qspiTransferOctal = 3
AnnaBridge 189:f392fc9709a3 77 } QSPI_TransferType_TypeDef;
AnnaBridge 189:f392fc9709a3 78
AnnaBridge 189:f392fc9709a3 79 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 80 ******************************* STRUCTS ***********************************
AnnaBridge 189:f392fc9709a3 81 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 82
AnnaBridge 189:f392fc9709a3 83 /** QSPI Device Read Instruction Configuration structure. */
AnnaBridge 189:f392fc9709a3 84 typedef struct {
AnnaBridge 189:f392fc9709a3 85 /** Read opcode in non-xip mode. */
AnnaBridge 189:f392fc9709a3 86 uint8_t opCode;
AnnaBridge 189:f392fc9709a3 87
AnnaBridge 189:f392fc9709a3 88 /** Number of dummy read clock cycles. */
AnnaBridge 189:f392fc9709a3 89 uint8_t dummyCycles;
AnnaBridge 189:f392fc9709a3 90
AnnaBridge 189:f392fc9709a3 91 /** Transfer type used for address. */
AnnaBridge 189:f392fc9709a3 92 QSPI_TransferType_TypeDef addrTransfer;
AnnaBridge 189:f392fc9709a3 93
AnnaBridge 189:f392fc9709a3 94 /** Transfer type used for data. */
AnnaBridge 189:f392fc9709a3 95 QSPI_TransferType_TypeDef dataTransfer;
AnnaBridge 189:f392fc9709a3 96
AnnaBridge 189:f392fc9709a3 97 /** Transfer type used for instruction. */
AnnaBridge 189:f392fc9709a3 98 QSPI_TransferType_TypeDef instTransfer;
AnnaBridge 189:f392fc9709a3 99 } QSPI_ReadConfig_TypeDef;
AnnaBridge 189:f392fc9709a3 100
AnnaBridge 189:f392fc9709a3 101 /** Default read configuration structure. */
AnnaBridge 189:f392fc9709a3 102 #define QSPI_READCONFIG_DEFAULT \
AnnaBridge 189:f392fc9709a3 103 { \
AnnaBridge 189:f392fc9709a3 104 0x03, /* 0x03 is the standard read opcode. */ \
AnnaBridge 189:f392fc9709a3 105 0, /* 0 dummy cycles. */ \
AnnaBridge 189:f392fc9709a3 106 qspiTransferSingle, /* Single I/O mode. */ \
AnnaBridge 189:f392fc9709a3 107 qspiTransferSingle, /* Single I/O mode. */ \
AnnaBridge 189:f392fc9709a3 108 qspiTransferSingle, /* Single I/O mode. */ \
AnnaBridge 189:f392fc9709a3 109 }
AnnaBridge 189:f392fc9709a3 110
AnnaBridge 189:f392fc9709a3 111 /** QSPI Device Write Instruction Configuration structure. */
AnnaBridge 189:f392fc9709a3 112 typedef struct {
AnnaBridge 189:f392fc9709a3 113 /** Write opcode. */
AnnaBridge 189:f392fc9709a3 114 uint8_t opCode;
AnnaBridge 189:f392fc9709a3 115
AnnaBridge 189:f392fc9709a3 116 /** Number of dummy read clock cycles. */
AnnaBridge 189:f392fc9709a3 117 uint8_t dummyCycles;
AnnaBridge 189:f392fc9709a3 118
AnnaBridge 189:f392fc9709a3 119 /** Transfer type used for address. */
AnnaBridge 189:f392fc9709a3 120 QSPI_TransferType_TypeDef addrTransfer;
AnnaBridge 189:f392fc9709a3 121
AnnaBridge 189:f392fc9709a3 122 /** Transfer type used for data. */
AnnaBridge 189:f392fc9709a3 123 QSPI_TransferType_TypeDef dataTransfer;
AnnaBridge 189:f392fc9709a3 124
AnnaBridge 189:f392fc9709a3 125 /**
AnnaBridge 189:f392fc9709a3 126 * @brief
AnnaBridge 189:f392fc9709a3 127 * Enable/disable automatic issuing of WEL (Write Enable Latch)
AnnaBridge 189:f392fc9709a3 128 * command before a write operation.
AnnaBridge 189:f392fc9709a3 129 *
AnnaBridge 189:f392fc9709a3 130 * @details
AnnaBridge 189:f392fc9709a3 131 * When writing to a flash device the write enable latch (WEL)
AnnaBridge 189:f392fc9709a3 132 * within the flash device itself must be high before a write sequence can be
AnnaBridge 189:f392fc9709a3 133 * issued. The QSPI peripheral can automatically issue the write enable latch
AnnaBridge 189:f392fc9709a3 134 * command before triggering a write sequence. The command used for enabling
AnnaBridge 189:f392fc9709a3 135 * the write enable latch is WREN (0x06) and is common between devices. */
AnnaBridge 189:f392fc9709a3 136 bool autoWEL;
AnnaBridge 189:f392fc9709a3 137 } QSPI_WriteConfig_TypeDef;
AnnaBridge 189:f392fc9709a3 138
AnnaBridge 189:f392fc9709a3 139 /** Default write configuration structure. */
AnnaBridge 189:f392fc9709a3 140 #define QSPI_WRITECONFIG_DEFAULT \
AnnaBridge 189:f392fc9709a3 141 { \
AnnaBridge 189:f392fc9709a3 142 0x02, /* 0x02 is the standard write opcode. */ \
AnnaBridge 189:f392fc9709a3 143 0, /* 0 dummy cycles. */ \
AnnaBridge 189:f392fc9709a3 144 qspiTransferSingle, /* Single I/O mode. */ \
AnnaBridge 189:f392fc9709a3 145 qspiTransferSingle, /* Single I/O mode. */ \
AnnaBridge 189:f392fc9709a3 146 true, /* Send WEL command automatically. */ \
AnnaBridge 189:f392fc9709a3 147 }
AnnaBridge 189:f392fc9709a3 148
AnnaBridge 189:f392fc9709a3 149 /** QSPI Device Delay Configuration structure. */
AnnaBridge 189:f392fc9709a3 150 typedef struct {
AnnaBridge 189:f392fc9709a3 151 /** The minimal delay to keep the chip select line de-asserted between
AnnaBridge 189:f392fc9709a3 152 * two transactions. */
AnnaBridge 189:f392fc9709a3 153 uint8_t deassert;
AnnaBridge 189:f392fc9709a3 154
AnnaBridge 189:f392fc9709a3 155 /** Delay between one chip select being de-activated and the
AnnaBridge 189:f392fc9709a3 156 * activation of another. */
AnnaBridge 189:f392fc9709a3 157 uint8_t deviceSwitch;
AnnaBridge 189:f392fc9709a3 158
AnnaBridge 189:f392fc9709a3 159 /** Delay between last bit and chip select de-assert. */
AnnaBridge 189:f392fc9709a3 160 uint8_t lastBit;
AnnaBridge 189:f392fc9709a3 161
AnnaBridge 189:f392fc9709a3 162 /** Delay chip select assert and first bit in a transaction. */
AnnaBridge 189:f392fc9709a3 163 uint8_t firstBit;
AnnaBridge 189:f392fc9709a3 164 } QSPI_DelayConfig_TypeDef;
AnnaBridge 189:f392fc9709a3 165
AnnaBridge 189:f392fc9709a3 166 /** Defines command to be executed using STIG mechanism. */
AnnaBridge 189:f392fc9709a3 167 typedef struct {
AnnaBridge 189:f392fc9709a3 168 /** command op-code */
AnnaBridge 189:f392fc9709a3 169 uint8_t cmdOpcode;
AnnaBridge 189:f392fc9709a3 170 /** Number of Read Data Bytes */
AnnaBridge 189:f392fc9709a3 171 uint16_t readDataSize;
AnnaBridge 189:f392fc9709a3 172 /** Number of Address Bytes */
AnnaBridge 189:f392fc9709a3 173 uint8_t addrSize;
AnnaBridge 189:f392fc9709a3 174 /** Number of Write Data Bytes */
AnnaBridge 189:f392fc9709a3 175 uint8_t writeDataSize;
AnnaBridge 189:f392fc9709a3 176 /** Number of dummy cycles */
AnnaBridge 189:f392fc9709a3 177 uint8_t dummyCycles;
AnnaBridge 189:f392fc9709a3 178 /** Mode Bit Configuration register are sent following the address bytes. */
AnnaBridge 189:f392fc9709a3 179 bool modeBitEnable;
AnnaBridge 189:f392fc9709a3 180 /** flash command address */
AnnaBridge 189:f392fc9709a3 181 uint32_t address;
AnnaBridge 189:f392fc9709a3 182 /** buffer for read data */
AnnaBridge 189:f392fc9709a3 183 void * readBuffer;
AnnaBridge 189:f392fc9709a3 184 /** buffer with data to write */
AnnaBridge 189:f392fc9709a3 185 void * writeBuffer;
AnnaBridge 189:f392fc9709a3 186 } QSPI_StigCmd_TypeDef;
AnnaBridge 189:f392fc9709a3 187
AnnaBridge 189:f392fc9709a3 188 /** QSPI initialization structure. */
AnnaBridge 189:f392fc9709a3 189 typedef struct {
AnnaBridge 189:f392fc9709a3 190 /** Enable/disable Quad SPI when initialization is completed. */
AnnaBridge 189:f392fc9709a3 191 bool enable;
AnnaBridge 189:f392fc9709a3 192
AnnaBridge 189:f392fc9709a3 193 /**
AnnaBridge 189:f392fc9709a3 194 * Master mode baude rate divisor. Values can be even numbers in the range
AnnaBridge 189:f392fc9709a3 195 * [2-32] inclusive. */
AnnaBridge 189:f392fc9709a3 196 uint8_t divisor;
AnnaBridge 189:f392fc9709a3 197 } QSPI_Init_TypeDef;
AnnaBridge 189:f392fc9709a3 198
AnnaBridge 189:f392fc9709a3 199 /** Default configuration for QSPI_Init_TypeDef structure. */
AnnaBridge 189:f392fc9709a3 200 #define QSPI_INIT_DEFAULT \
AnnaBridge 189:f392fc9709a3 201 { \
AnnaBridge 189:f392fc9709a3 202 true, /* Enable Quad SPI. */ \
AnnaBridge 189:f392fc9709a3 203 32, /* Divide QSPI clock by 32. */ \
AnnaBridge 189:f392fc9709a3 204 }
AnnaBridge 189:f392fc9709a3 205
AnnaBridge 189:f392fc9709a3 206 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 207 ****************************** PROTOTYPES *********************************
AnnaBridge 189:f392fc9709a3 208 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 209
AnnaBridge 189:f392fc9709a3 210 void QSPI_Init(QSPI_TypeDef * qspi, const QSPI_Init_TypeDef * init);
AnnaBridge 189:f392fc9709a3 211 void QSPI_ReadConfig(QSPI_TypeDef * qspi, const QSPI_ReadConfig_TypeDef * config);
AnnaBridge 189:f392fc9709a3 212 void QSPI_WriteConfig(QSPI_TypeDef * qspi, const QSPI_WriteConfig_TypeDef * config);
AnnaBridge 189:f392fc9709a3 213 void QSPI_ExecStigCmd(QSPI_TypeDef * qspi, const QSPI_StigCmd_TypeDef * stigCmd);
AnnaBridge 189:f392fc9709a3 214
AnnaBridge 189:f392fc9709a3 215 /***************************************************************************//**
AnnaBridge 189:f392fc9709a3 216 * @brief
AnnaBridge 189:f392fc9709a3 217 * Wait for the QSPI to go into idle state.
AnnaBridge 189:f392fc9709a3 218 *
AnnaBridge 189:f392fc9709a3 219 * @param[in] qspi
AnnaBridge 189:f392fc9709a3 220 * Pointer to QSPI peripheral register block.
AnnaBridge 189:f392fc9709a3 221 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 222 __STATIC_INLINE void QSPI_WaitForIdle(QSPI_TypeDef * qspi)
AnnaBridge 189:f392fc9709a3 223 {
AnnaBridge 189:f392fc9709a3 224 while ((qspi->CONFIG & _QSPI_CONFIG_IDLE_MASK) == 0)
AnnaBridge 189:f392fc9709a3 225 ;
AnnaBridge 189:f392fc9709a3 226 }
AnnaBridge 189:f392fc9709a3 227
AnnaBridge 189:f392fc9709a3 228 /***************************************************************************//**
AnnaBridge 189:f392fc9709a3 229 * @brief
AnnaBridge 189:f392fc9709a3 230 * Get the fill level of the write partition of the QSPI internal SRAM.
AnnaBridge 189:f392fc9709a3 231 *
AnnaBridge 189:f392fc9709a3 232 * @param[in] qspi
AnnaBridge 189:f392fc9709a3 233 * Pointer to QSPI peripheral register block.
AnnaBridge 189:f392fc9709a3 234 *
AnnaBridge 189:f392fc9709a3 235 * @return
AnnaBridge 189:f392fc9709a3 236 * SRAM fill level of the write partition. The value is the number of 4 byte
AnnaBridge 189:f392fc9709a3 237 * words in the write partition.
AnnaBridge 189:f392fc9709a3 238 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 239 __STATIC_INLINE uint16_t QSPI_GetWriteLevel(QSPI_TypeDef * qspi)
AnnaBridge 189:f392fc9709a3 240 {
AnnaBridge 189:f392fc9709a3 241 return (qspi->SRAMFILL & _QSPI_SRAMFILL_SRAMFILLINDACWRITE_MASK)
AnnaBridge 189:f392fc9709a3 242 >> _QSPI_SRAMFILL_SRAMFILLINDACWRITE_SHIFT;
AnnaBridge 189:f392fc9709a3 243 }
AnnaBridge 189:f392fc9709a3 244
AnnaBridge 189:f392fc9709a3 245 /***************************************************************************//**
AnnaBridge 189:f392fc9709a3 246 * @brief
AnnaBridge 189:f392fc9709a3 247 * Get the fill level of the read partition of the QSPI internal SRAM.
AnnaBridge 189:f392fc9709a3 248 *
AnnaBridge 189:f392fc9709a3 249 * @param[in] qspi
AnnaBridge 189:f392fc9709a3 250 * Pointer to QSPI peripheral register block.
AnnaBridge 189:f392fc9709a3 251 *
AnnaBridge 189:f392fc9709a3 252 * @return
AnnaBridge 189:f392fc9709a3 253 * SRAM fill level of the read partition. The value is the number of 4 byte
AnnaBridge 189:f392fc9709a3 254 * words in the read partition.
AnnaBridge 189:f392fc9709a3 255 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 256 __STATIC_INLINE uint16_t QSPI_GetReadLevel(QSPI_TypeDef * qspi)
AnnaBridge 189:f392fc9709a3 257 {
AnnaBridge 189:f392fc9709a3 258 return (qspi->SRAMFILL & _QSPI_SRAMFILL_SRAMFILLINDACREAD_MASK)
AnnaBridge 189:f392fc9709a3 259 >> _QSPI_SRAMFILL_SRAMFILLINDACREAD_SHIFT;
AnnaBridge 189:f392fc9709a3 260 }
AnnaBridge 189:f392fc9709a3 261
AnnaBridge 189:f392fc9709a3 262 /***************************************************************************//**
AnnaBridge 189:f392fc9709a3 263 * @brief
AnnaBridge 189:f392fc9709a3 264 * Enable/disable Quad SPI.
AnnaBridge 189:f392fc9709a3 265 *
AnnaBridge 189:f392fc9709a3 266 * @param[in] qspi
AnnaBridge 189:f392fc9709a3 267 * Pointer to QSPI peripheral register block.
AnnaBridge 189:f392fc9709a3 268 *
AnnaBridge 189:f392fc9709a3 269 * @param[in] enable
AnnaBridge 189:f392fc9709a3 270 * true to enable quad spi, false to disable quad spi.
AnnaBridge 189:f392fc9709a3 271 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 272 __STATIC_INLINE void QSPI_Enable(QSPI_TypeDef * qspi, bool enable)
AnnaBridge 189:f392fc9709a3 273 {
AnnaBridge 189:f392fc9709a3 274 BUS_RegBitWrite(&qspi->CONFIG, _QSPI_CONFIG_ENBSPI_SHIFT, enable ? 1 : 0);
AnnaBridge 189:f392fc9709a3 275 }
AnnaBridge 189:f392fc9709a3 276
AnnaBridge 189:f392fc9709a3 277 /***************************************************************************//**
AnnaBridge 189:f392fc9709a3 278 * @brief
AnnaBridge 189:f392fc9709a3 279 * Get the current interrupt flags.
AnnaBridge 189:f392fc9709a3 280 *
AnnaBridge 189:f392fc9709a3 281 * @param[in] qspi
AnnaBridge 189:f392fc9709a3 282 * Pointer to QSPI peripheral register block.
AnnaBridge 189:f392fc9709a3 283 *
AnnaBridge 189:f392fc9709a3 284 * @return
AnnaBridge 189:f392fc9709a3 285 * This functions returns the current interrupt flags that are set.
AnnaBridge 189:f392fc9709a3 286 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 287 __STATIC_INLINE uint32_t QSPI_IntGet(QSPI_TypeDef * qspi)
AnnaBridge 189:f392fc9709a3 288 {
AnnaBridge 189:f392fc9709a3 289 return qspi->IRQSTATUS;
AnnaBridge 189:f392fc9709a3 290 }
AnnaBridge 189:f392fc9709a3 291
AnnaBridge 189:f392fc9709a3 292 /***************************************************************************//**
AnnaBridge 189:f392fc9709a3 293 * @brief
AnnaBridge 189:f392fc9709a3 294 * Clear interrupt flags
AnnaBridge 189:f392fc9709a3 295 *
AnnaBridge 189:f392fc9709a3 296 * @param[in] qspi
AnnaBridge 189:f392fc9709a3 297 * Pointer to QSPI peripheral register block.
AnnaBridge 189:f392fc9709a3 298 *
AnnaBridge 189:f392fc9709a3 299 * @param[in] flags
AnnaBridge 189:f392fc9709a3 300 * The interrupt flags to clear.
AnnaBridge 189:f392fc9709a3 301 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 302 __STATIC_INLINE void QSPI_IntClear(QSPI_TypeDef * qspi, uint32_t flags)
AnnaBridge 189:f392fc9709a3 303 {
AnnaBridge 189:f392fc9709a3 304 qspi->IRQSTATUS = flags;
AnnaBridge 189:f392fc9709a3 305 }
AnnaBridge 189:f392fc9709a3 306
AnnaBridge 189:f392fc9709a3 307 /***************************************************************************//**
AnnaBridge 189:f392fc9709a3 308 * @brief
AnnaBridge 189:f392fc9709a3 309 * Enable interrupts.
AnnaBridge 189:f392fc9709a3 310 *
AnnaBridge 189:f392fc9709a3 311 * @param[in] qspi
AnnaBridge 189:f392fc9709a3 312 * Pointer to QSPI peripheral register block.
AnnaBridge 189:f392fc9709a3 313 *
AnnaBridge 189:f392fc9709a3 314 * @param[in] flags
AnnaBridge 189:f392fc9709a3 315 * The interrupt flags to enable.
AnnaBridge 189:f392fc9709a3 316 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 317 __STATIC_INLINE void QSPI_IntEnable(QSPI_TypeDef * qspi, uint32_t flags)
AnnaBridge 189:f392fc9709a3 318 {
AnnaBridge 189:f392fc9709a3 319 qspi->IRQMASK = flags & (~_QSPI_IRQMASK_MASK);
AnnaBridge 189:f392fc9709a3 320 }
AnnaBridge 189:f392fc9709a3 321
AnnaBridge 189:f392fc9709a3 322 /***************************************************************************//**
AnnaBridge 189:f392fc9709a3 323 * @brief
AnnaBridge 189:f392fc9709a3 324 * Disable interrupts.
AnnaBridge 189:f392fc9709a3 325 *
AnnaBridge 189:f392fc9709a3 326 * @param[in] qspi
AnnaBridge 189:f392fc9709a3 327 * Pointer to QSPI peripheral register block.
AnnaBridge 189:f392fc9709a3 328 *
AnnaBridge 189:f392fc9709a3 329 * @param[in] flags
AnnaBridge 189:f392fc9709a3 330 * The interrupt flags to disable.
AnnaBridge 189:f392fc9709a3 331 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 332 __STATIC_INLINE void QSPI_IntDisable(QSPI_TypeDef * qspi, uint32_t flags)
AnnaBridge 189:f392fc9709a3 333 {
AnnaBridge 189:f392fc9709a3 334 qspi->IRQMASK = ~flags & (~_QSPI_IRQMASK_MASK);
AnnaBridge 189:f392fc9709a3 335 }
AnnaBridge 189:f392fc9709a3 336
AnnaBridge 189:f392fc9709a3 337 /** @} (end addtogroup QSPI) */
AnnaBridge 189:f392fc9709a3 338 /** @} (end addtogroup emlib) */
AnnaBridge 189:f392fc9709a3 339
AnnaBridge 189:f392fc9709a3 340 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 341 }
AnnaBridge 189:f392fc9709a3 342 #endif
AnnaBridge 189:f392fc9709a3 343
AnnaBridge 189:f392fc9709a3 344 #endif /* defined(QSPI_COUNT) && (QSPI_COUNT > 0) */
AnnaBridge 189:f392fc9709a3 345 #endif /* EM_QSPI_H */