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targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_IAR/startup_efm32zg.S@182:a56a73fd2a6f, 2018-03-20 (annotated)

Committer:
AnnaBridge
Date:
Tue Mar 20 16:56:18 2018 +0000
Revision:
182:a56a73fd2a6f
Parent:
targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_IAR/startup_efm32zg.s@150:02e0a0aed4ec 
mbed-dev library. Release version 160

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 ;/**************************************************************************//**
<> 150:02e0a0aed4ec 2 ; * @file startup_efm32zg.s
<> 150:02e0a0aed4ec 3 ; * @brief CMSIS Core Device Startup File
<> 150:02e0a0aed4ec 4 ; * Silicon Labs EFM32ZG Device Series
<> 150:02e0a0aed4ec 5 ; * @version 5.0.0
<> 150:02e0a0aed4ec 6 ; * @date 30. January 2012
<> 150:02e0a0aed4ec 7 ; *
<> 150:02e0a0aed4ec 8 ; * @note
<> 150:02e0a0aed4ec 9 ; * Copyright (C) 2012 ARM Limited. All rights reserved.
<> 150:02e0a0aed4ec 10 ; *
<> 150:02e0a0aed4ec 11 ; * @par
<> 150:02e0a0aed4ec 12 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M
<> 150:02e0a0aed4ec 13 ; * processor based microcontrollers. This file can be freely distributed
<> 150:02e0a0aed4ec 14 ; * within development tools that are supporting such ARM based processors.
<> 150:02e0a0aed4ec 15 ; *
<> 150:02e0a0aed4ec 16 ; * @par
<> 150:02e0a0aed4ec 17 ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 150:02e0a0aed4ec 18 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 150:02e0a0aed4ec 19 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 150:02e0a0aed4ec 20 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
<> 150:02e0a0aed4ec 21 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 150:02e0a0aed4ec 22 ; *
<> 150:02e0a0aed4ec 23 ; ******************************************************************************/
<> 150:02e0a0aed4ec 24
<> 150:02e0a0aed4ec 25 ;
<> 150:02e0a0aed4ec 26 ; The modules in this file are included in the libraries, and may be replaced
<> 150:02e0a0aed4ec 27 ; by any user-defined modules that define the PUBLIC symbol _program_start or
<> 150:02e0a0aed4ec 28 ; a user defined start symbol.
<> 150:02e0a0aed4ec 29 ; To override the cstartup defined in the library, simply add your modified
<> 150:02e0a0aed4ec 30 ; version to the workbench project.
<> 150:02e0a0aed4ec 31 ;
<> 150:02e0a0aed4ec 32 ; The vector table is normally located at address 0.
<> 150:02e0a0aed4ec 33 ;
<> 150:02e0a0aed4ec 34 ; When debugging in RAM, it can be located in RAM with at least a 128 byte
<> 150:02e0a0aed4ec 35 ; alignment, 256 byte alignment is requied if all interrupt vectors are in use.
<> 150:02e0a0aed4ec 36 ;
<> 150:02e0a0aed4ec 37 ; The name "__vector_table" has special meaning for C-SPY:
<> 150:02e0a0aed4ec 38 ; it is where the SP start value is found, and the NVIC vector
<> 150:02e0a0aed4ec 39 ; table register (VTOR) is initialized to this address if != 0.
<> 150:02e0a0aed4ec 40 ;
<> 150:02e0a0aed4ec 41 ; Cortex-M version
<> 150:02e0a0aed4ec 42 ;
<> 150:02e0a0aed4ec 43 MODULE ?cstartup
<> 150:02e0a0aed4ec 44
<> 150:02e0a0aed4ec 45 ;; Forward declaration of sections.
<> 150:02e0a0aed4ec 46 SECTION CSTACK:DATA:NOROOT(3)
<> 150:02e0a0aed4ec 47
<> 150:02e0a0aed4ec 48 SECTION .intvec:CODE:NOROOT(8)
<> 150:02e0a0aed4ec 49
<> 150:02e0a0aed4ec 50 EXTERN __iar_program_start
<> 150:02e0a0aed4ec 51 EXTERN SystemInit
<> 150:02e0a0aed4ec 52 PUBLIC __vector_table
<> 150:02e0a0aed4ec 53 PUBLIC __vector_table_0x1c
<> 150:02e0a0aed4ec 54 PUBLIC __Vectors
<> 150:02e0a0aed4ec 55 PUBLIC __Vectors_End
<> 150:02e0a0aed4ec 56 PUBLIC __Vectors_Size
<> 150:02e0a0aed4ec 57
<> 150:02e0a0aed4ec 58 DATA
<> 150:02e0a0aed4ec 59
<> 150:02e0a0aed4ec 60 __vector_table
<> 150:02e0a0aed4ec 61 DCD sfe(CSTACK)
<> 150:02e0a0aed4ec 62 DCD Reset_Handler
<> 150:02e0a0aed4ec 63
<> 150:02e0a0aed4ec 64 DCD NMI_Handler
<> 150:02e0a0aed4ec 65 DCD HardFault_Handler
<> 150:02e0a0aed4ec 66 DCD 0
<> 150:02e0a0aed4ec 67 DCD 0
<> 150:02e0a0aed4ec 68 DCD 0
<> 150:02e0a0aed4ec 69 __vector_table_0x1c
<> 150:02e0a0aed4ec 70 DCD 0
<> 150:02e0a0aed4ec 71 DCD 0
<> 150:02e0a0aed4ec 72 DCD 0
<> 150:02e0a0aed4ec 73 DCD 0
<> 150:02e0a0aed4ec 74 DCD SVC_Handler
<> 150:02e0a0aed4ec 75 DCD 0
<> 150:02e0a0aed4ec 76 DCD 0
<> 150:02e0a0aed4ec 77 DCD PendSV_Handler
<> 150:02e0a0aed4ec 78 DCD SysTick_Handler
<> 150:02e0a0aed4ec 79
<> 150:02e0a0aed4ec 80 ; External Interrupts
<> 150:02e0a0aed4ec 81
<> 150:02e0a0aed4ec 82 DCD DMA_IRQHandler ; 0: DMA Interrupt
<> 150:02e0a0aed4ec 83 DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt
<> 150:02e0a0aed4ec 84 DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt
<> 150:02e0a0aed4ec 85 DCD ACMP0_IRQHandler ; 3: ACMP0 Interrupt
<> 150:02e0a0aed4ec 86 DCD ADC0_IRQHandler ; 4: ADC0 Interrupt
<> 150:02e0a0aed4ec 87 DCD I2C0_IRQHandler ; 5: I2C0 Interrupt
<> 150:02e0a0aed4ec 88 DCD GPIO_ODD_IRQHandler ; 6: GPIO_ODD Interrupt
<> 150:02e0a0aed4ec 89 DCD TIMER1_IRQHandler ; 7: TIMER1 Interrupt
<> 150:02e0a0aed4ec 90 DCD USART1_RX_IRQHandler ; 8: USART1_RX Interrupt
<> 150:02e0a0aed4ec 91 DCD USART1_TX_IRQHandler ; 9: USART1_TX Interrupt
<> 150:02e0a0aed4ec 92 DCD LEUART0_IRQHandler ; 10: LEUART0 Interrupt
<> 150:02e0a0aed4ec 93 DCD PCNT0_IRQHandler ; 11: PCNT0 Interrupt
<> 150:02e0a0aed4ec 94 DCD RTC_IRQHandler ; 12: RTC Interrupt
<> 150:02e0a0aed4ec 95 DCD CMU_IRQHandler ; 13: CMU Interrupt
<> 150:02e0a0aed4ec 96 DCD VCMP_IRQHandler ; 14: VCMP Interrupt
<> 150:02e0a0aed4ec 97 DCD MSC_IRQHandler ; 15: MSC Interrupt
<> 150:02e0a0aed4ec 98 DCD AES_IRQHandler ; 16: AES Interrupt
<> 150:02e0a0aed4ec 99 DCD 0 ; 17: Reserved Interrupt
<> 150:02e0a0aed4ec 100 DCD 0 ; 18: Reserved Interrupt
<> 150:02e0a0aed4ec 101
<> 150:02e0a0aed4ec 102
<> 150:02e0a0aed4ec 103 __Vectors_End
<> 150:02e0a0aed4ec 104 __Vectors EQU __vector_table
<> 150:02e0a0aed4ec 105 __Vectors_Size EQU __Vectors_End - __Vectors
<> 150:02e0a0aed4ec 106
<> 150:02e0a0aed4ec 107
<> 150:02e0a0aed4ec 108 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
<> 150:02e0a0aed4ec 109 ;;
<> 150:02e0a0aed4ec 110 ;; Default interrupt handlers.
<> 150:02e0a0aed4ec 111 ;;
<> 150:02e0a0aed4ec 112 THUMB
<> 150:02e0a0aed4ec 113
<> 150:02e0a0aed4ec 114 PUBWEAK Reset_Handler
<> 150:02e0a0aed4ec 115 SECTION .text:CODE:REORDER:NOROOT(2)
<> 150:02e0a0aed4ec 116 Reset_Handler
<> 150:02e0a0aed4ec 117 LDR R0, =SystemInit
<> 150:02e0a0aed4ec 118 BLX R0
<> 150:02e0a0aed4ec 119 LDR R0, =__iar_program_start
<> 150:02e0a0aed4ec 120 BX R0
<> 150:02e0a0aed4ec 121
<> 150:02e0a0aed4ec 122 PUBWEAK NMI_Handler
<> 150:02e0a0aed4ec 123 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 124 NMI_Handler
<> 150:02e0a0aed4ec 125 B NMI_Handler
<> 150:02e0a0aed4ec 126
<> 150:02e0a0aed4ec 127 PUBWEAK HardFault_Handler
<> 150:02e0a0aed4ec 128 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 129 HardFault_Handler
<> 150:02e0a0aed4ec 130 B HardFault_Handler
<> 150:02e0a0aed4ec 131
<> 150:02e0a0aed4ec 132 PUBWEAK SVC_Handler
<> 150:02e0a0aed4ec 133 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 134 SVC_Handler
<> 150:02e0a0aed4ec 135 B SVC_Handler
<> 150:02e0a0aed4ec 136
<> 150:02e0a0aed4ec 137 PUBWEAK PendSV_Handler
<> 150:02e0a0aed4ec 138 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 139 PendSV_Handler
<> 150:02e0a0aed4ec 140 B PendSV_Handler
<> 150:02e0a0aed4ec 141
<> 150:02e0a0aed4ec 142 PUBWEAK SysTick_Handler
<> 150:02e0a0aed4ec 143 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 144 SysTick_Handler
<> 150:02e0a0aed4ec 145 B SysTick_Handler
<> 150:02e0a0aed4ec 146
<> 150:02e0a0aed4ec 147 ; Device specific interrupt handlers
<> 150:02e0a0aed4ec 148
<> 150:02e0a0aed4ec 149 PUBWEAK DMA_IRQHandler
<> 150:02e0a0aed4ec 150 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 151 DMA_IRQHandler
<> 150:02e0a0aed4ec 152 B DMA_IRQHandler
<> 150:02e0a0aed4ec 153
<> 150:02e0a0aed4ec 154 PUBWEAK GPIO_EVEN_IRQHandler
<> 150:02e0a0aed4ec 155 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 156 GPIO_EVEN_IRQHandler
<> 150:02e0a0aed4ec 157 B GPIO_EVEN_IRQHandler
<> 150:02e0a0aed4ec 158
<> 150:02e0a0aed4ec 159 PUBWEAK TIMER0_IRQHandler
<> 150:02e0a0aed4ec 160 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 161 TIMER0_IRQHandler
<> 150:02e0a0aed4ec 162 B TIMER0_IRQHandler
<> 150:02e0a0aed4ec 163
<> 150:02e0a0aed4ec 164 PUBWEAK ACMP0_IRQHandler
<> 150:02e0a0aed4ec 165 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 166 ACMP0_IRQHandler
<> 150:02e0a0aed4ec 167 B ACMP0_IRQHandler
<> 150:02e0a0aed4ec 168
<> 150:02e0a0aed4ec 169 PUBWEAK ADC0_IRQHandler
<> 150:02e0a0aed4ec 170 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 171 ADC0_IRQHandler
<> 150:02e0a0aed4ec 172 B ADC0_IRQHandler
<> 150:02e0a0aed4ec 173
<> 150:02e0a0aed4ec 174 PUBWEAK I2C0_IRQHandler
<> 150:02e0a0aed4ec 175 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 176 I2C0_IRQHandler
<> 150:02e0a0aed4ec 177 B I2C0_IRQHandler
<> 150:02e0a0aed4ec 178
<> 150:02e0a0aed4ec 179 PUBWEAK GPIO_ODD_IRQHandler
<> 150:02e0a0aed4ec 180 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 181 GPIO_ODD_IRQHandler
<> 150:02e0a0aed4ec 182 B GPIO_ODD_IRQHandler
<> 150:02e0a0aed4ec 183
<> 150:02e0a0aed4ec 184 PUBWEAK TIMER1_IRQHandler
<> 150:02e0a0aed4ec 185 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 186 TIMER1_IRQHandler
<> 150:02e0a0aed4ec 187 B TIMER1_IRQHandler
<> 150:02e0a0aed4ec 188
<> 150:02e0a0aed4ec 189 PUBWEAK USART1_RX_IRQHandler
<> 150:02e0a0aed4ec 190 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 191 USART1_RX_IRQHandler
<> 150:02e0a0aed4ec 192 B USART1_RX_IRQHandler
<> 150:02e0a0aed4ec 193
<> 150:02e0a0aed4ec 194 PUBWEAK USART1_TX_IRQHandler
<> 150:02e0a0aed4ec 195 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 196 USART1_TX_IRQHandler
<> 150:02e0a0aed4ec 197 B USART1_TX_IRQHandler
<> 150:02e0a0aed4ec 198
<> 150:02e0a0aed4ec 199 PUBWEAK LEUART0_IRQHandler
<> 150:02e0a0aed4ec 200 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 201 LEUART0_IRQHandler
<> 150:02e0a0aed4ec 202 B LEUART0_IRQHandler
<> 150:02e0a0aed4ec 203
<> 150:02e0a0aed4ec 204 PUBWEAK PCNT0_IRQHandler
<> 150:02e0a0aed4ec 205 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 206 PCNT0_IRQHandler
<> 150:02e0a0aed4ec 207 B PCNT0_IRQHandler
<> 150:02e0a0aed4ec 208
<> 150:02e0a0aed4ec 209 PUBWEAK RTC_IRQHandler
<> 150:02e0a0aed4ec 210 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 211 RTC_IRQHandler
<> 150:02e0a0aed4ec 212 B RTC_IRQHandler
<> 150:02e0a0aed4ec 213
<> 150:02e0a0aed4ec 214 PUBWEAK CMU_IRQHandler
<> 150:02e0a0aed4ec 215 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 216 CMU_IRQHandler
<> 150:02e0a0aed4ec 217 B CMU_IRQHandler
<> 150:02e0a0aed4ec 218
<> 150:02e0a0aed4ec 219 PUBWEAK VCMP_IRQHandler
<> 150:02e0a0aed4ec 220 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 221 VCMP_IRQHandler
<> 150:02e0a0aed4ec 222 B VCMP_IRQHandler
<> 150:02e0a0aed4ec 223
<> 150:02e0a0aed4ec 224 PUBWEAK MSC_IRQHandler
<> 150:02e0a0aed4ec 225 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 226 MSC_IRQHandler
<> 150:02e0a0aed4ec 227 B MSC_IRQHandler
<> 150:02e0a0aed4ec 228
<> 150:02e0a0aed4ec 229 PUBWEAK AES_IRQHandler
<> 150:02e0a0aed4ec 230 SECTION .text:CODE:REORDER:NOROOT(1)
<> 150:02e0a0aed4ec 231 AES_IRQHandler
<> 150:02e0a0aed4ec 232 B AES_IRQHandler
<> 150:02e0a0aed4ec 233
<> 150:02e0a0aed4ec 234
<> 150:02e0a0aed4ec 235 END