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targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_GCC_ARM/startup_stm32f401xe.S@182:a56a73fd2a6f, 2018-03-20 (annotated)

Committer:
AnnaBridge
Date:
Tue Mar 20 16:56:18 2018 +0000
Revision:
182:a56a73fd2a6f
Parent:
158:b23ee177fd68 
mbed-dev library. Release version 160

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file startup_stm32f401xe.s
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 182:a56a73fd2a6f 5 * @brief STM32F401xExx Devices vector table for GCC based toolchains.
<> 144:ef7eb2e8f9f7 6 * This module performs:
<> 144:ef7eb2e8f9f7 7 * - Set the initial SP
<> 144:ef7eb2e8f9f7 8 * - Set the initial PC == Reset_Handler,
<> 144:ef7eb2e8f9f7 9 * - Set the vector table entries with the exceptions ISR address
<> 144:ef7eb2e8f9f7 10 * - Branches to main in the C library (which eventually
<> 144:ef7eb2e8f9f7 11 * calls main()).
<> 144:ef7eb2e8f9f7 12 * After Reset the Cortex-M4 processor is in Thread mode,
<> 144:ef7eb2e8f9f7 13 * priority is Privileged, and the Stack is set to Main.
<> 144:ef7eb2e8f9f7 14 ******************************************************************************
<> 144:ef7eb2e8f9f7 15 * @attention
<> 144:ef7eb2e8f9f7 16 *
AnnaBridge 182:a56a73fd2a6f 17 * <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 20 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 21 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 22 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 24 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 25 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 27 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 28 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 29 *
<> 144:ef7eb2e8f9f7 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 40 *
<> 144:ef7eb2e8f9f7 41 ******************************************************************************
<> 144:ef7eb2e8f9f7 42 */
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 .syntax unified
<> 144:ef7eb2e8f9f7 45 .cpu cortex-m4
<> 144:ef7eb2e8f9f7 46 .fpu softvfp
<> 144:ef7eb2e8f9f7 47 .thumb
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 .global g_pfnVectors
<> 144:ef7eb2e8f9f7 50 .global Default_Handler
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /* start address for the initialization values of the .data section.
<> 144:ef7eb2e8f9f7 53 defined in linker script */
<> 144:ef7eb2e8f9f7 54 .word _sidata
<> 144:ef7eb2e8f9f7 55 /* start address for the .data section. defined in linker script */
<> 144:ef7eb2e8f9f7 56 .word _sdata
<> 144:ef7eb2e8f9f7 57 /* end address for the .data section. defined in linker script */
<> 144:ef7eb2e8f9f7 58 .word _edata
AnnaBridge 182:a56a73fd2a6f 59 /* start address for the .bss section. defined in linker script */
AnnaBridge 182:a56a73fd2a6f 60 .word _sbss
AnnaBridge 182:a56a73fd2a6f 61 /* end address for the .bss section. defined in linker script */
AnnaBridge 182:a56a73fd2a6f 62 .word _ebss
<> 144:ef7eb2e8f9f7 63 /* stack used for SystemInit_ExtMemCtl; always internal RAM used */
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /**
<> 144:ef7eb2e8f9f7 66 * @brief This is the code that gets called when the processor first
<> 144:ef7eb2e8f9f7 67 * starts execution following a reset event. Only the absolutely
<> 144:ef7eb2e8f9f7 68 * necessary set is performed, after which the application
<> 144:ef7eb2e8f9f7 69 * supplied main() routine is called.
<> 144:ef7eb2e8f9f7 70 * @param None
<> 144:ef7eb2e8f9f7 71 * @retval : None
<> 144:ef7eb2e8f9f7 72 */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 .section .text.Reset_Handler
<> 144:ef7eb2e8f9f7 75 .weak Reset_Handler
<> 144:ef7eb2e8f9f7 76 .type Reset_Handler, %function
<> 144:ef7eb2e8f9f7 77 Reset_Handler:
<> 144:ef7eb2e8f9f7 78 ldr sp, =_estack /* set stack pointer */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /* Copy the data segment initializers from flash to SRAM */
<> 144:ef7eb2e8f9f7 81 movs r1, #0
<> 144:ef7eb2e8f9f7 82 b LoopCopyDataInit
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 CopyDataInit:
<> 144:ef7eb2e8f9f7 85 ldr r3, =_sidata
<> 144:ef7eb2e8f9f7 86 ldr r3, [r3, r1]
<> 144:ef7eb2e8f9f7 87 str r3, [r0, r1]
<> 144:ef7eb2e8f9f7 88 adds r1, r1, #4
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 LoopCopyDataInit:
<> 144:ef7eb2e8f9f7 91 ldr r0, =_sdata
<> 144:ef7eb2e8f9f7 92 ldr r3, =_edata
<> 144:ef7eb2e8f9f7 93 adds r2, r0, r1
<> 144:ef7eb2e8f9f7 94 cmp r2, r3
<> 144:ef7eb2e8f9f7 95 bcc CopyDataInit
AnnaBridge 182:a56a73fd2a6f 96 ldr r2, =_sbss
AnnaBridge 182:a56a73fd2a6f 97 b LoopFillZerobss
AnnaBridge 182:a56a73fd2a6f 98 /* Zero fill the bss segment. */
AnnaBridge 182:a56a73fd2a6f 99 FillZerobss:
AnnaBridge 182:a56a73fd2a6f 100 movs r3, #0
AnnaBridge 182:a56a73fd2a6f 101 str r3, [r2], #4
AnnaBridge 182:a56a73fd2a6f 102
AnnaBridge 182:a56a73fd2a6f 103 LoopFillZerobss:
AnnaBridge 182:a56a73fd2a6f 104 ldr r3, = _ebss
AnnaBridge 182:a56a73fd2a6f 105 cmp r2, r3
AnnaBridge 182:a56a73fd2a6f 106 bcc FillZerobss
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /* Call the clock system intitialization function.*/
<> 144:ef7eb2e8f9f7 109 bl SystemInit
<> 144:ef7eb2e8f9f7 110 /* Call static constructors */
<> 144:ef7eb2e8f9f7 111 //bl __libc_init_array
<> 144:ef7eb2e8f9f7 112 /* Call the application's entry point.*/
<> 144:ef7eb2e8f9f7 113 //bl main
<> 144:ef7eb2e8f9f7 114 // Calling the crt0 'cold-start' entry point. There __libc_init_array is called
<> 144:ef7eb2e8f9f7 115 // and when existing hardware_init_hook() and software_init_hook() before
<> 144:ef7eb2e8f9f7 116 // starting main(). software_init_hook() is available and has to be called due
<> 144:ef7eb2e8f9f7 117 // to initializsation when using rtos.
<> 144:ef7eb2e8f9f7 118 bl _start
<> 144:ef7eb2e8f9f7 119 bx lr
<> 144:ef7eb2e8f9f7 120 .size Reset_Handler, .-Reset_Handler
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /**
<> 144:ef7eb2e8f9f7 123 * @brief This is the code that gets called when the processor receives an
<> 144:ef7eb2e8f9f7 124 * unexpected interrupt. This simply enters an infinite loop, preserving
<> 144:ef7eb2e8f9f7 125 * the system state for examination by a debugger.
<> 144:ef7eb2e8f9f7 126 * @param None
<> 144:ef7eb2e8f9f7 127 * @retval None
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129 .section .text.Default_Handler,"ax",%progbits
<> 144:ef7eb2e8f9f7 130 Default_Handler:
<> 144:ef7eb2e8f9f7 131 Infinite_Loop:
<> 144:ef7eb2e8f9f7 132 b Infinite_Loop
<> 144:ef7eb2e8f9f7 133 .size Default_Handler, .-Default_Handler
<> 144:ef7eb2e8f9f7 134 /******************************************************************************
<> 144:ef7eb2e8f9f7 135 *
<> 144:ef7eb2e8f9f7 136 * The minimal vector table for a Cortex M3. Note that the proper constructs
<> 144:ef7eb2e8f9f7 137 * must be placed on this to ensure that it ends up at physical address
<> 144:ef7eb2e8f9f7 138 * 0x0000.0000.
<> 144:ef7eb2e8f9f7 139 *
<> 144:ef7eb2e8f9f7 140 *******************************************************************************/
<> 144:ef7eb2e8f9f7 141 .section .isr_vector,"a",%progbits
<> 144:ef7eb2e8f9f7 142 .type g_pfnVectors, %object
<> 144:ef7eb2e8f9f7 143 .size g_pfnVectors, .-g_pfnVectors
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 g_pfnVectors:
<> 144:ef7eb2e8f9f7 146 .word _estack
<> 144:ef7eb2e8f9f7 147 .word Reset_Handler
<> 144:ef7eb2e8f9f7 148 .word NMI_Handler
<> 144:ef7eb2e8f9f7 149 .word HardFault_Handler
<> 144:ef7eb2e8f9f7 150 .word MemManage_Handler
<> 144:ef7eb2e8f9f7 151 .word BusFault_Handler
<> 144:ef7eb2e8f9f7 152 .word UsageFault_Handler
<> 144:ef7eb2e8f9f7 153 .word 0
<> 144:ef7eb2e8f9f7 154 .word 0
<> 144:ef7eb2e8f9f7 155 .word 0
<> 144:ef7eb2e8f9f7 156 .word 0
<> 144:ef7eb2e8f9f7 157 .word SVC_Handler
<> 144:ef7eb2e8f9f7 158 .word DebugMon_Handler
<> 144:ef7eb2e8f9f7 159 .word 0
<> 144:ef7eb2e8f9f7 160 .word PendSV_Handler
<> 144:ef7eb2e8f9f7 161 .word SysTick_Handler
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /* External Interrupts */
<> 144:ef7eb2e8f9f7 164 .word WWDG_IRQHandler /* Window WatchDog */
<> 144:ef7eb2e8f9f7 165 .word PVD_IRQHandler /* PVD through EXTI Line detection */
<> 144:ef7eb2e8f9f7 166 .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
<> 144:ef7eb2e8f9f7 167 .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
<> 144:ef7eb2e8f9f7 168 .word FLASH_IRQHandler /* FLASH */
<> 144:ef7eb2e8f9f7 169 .word RCC_IRQHandler /* RCC */
<> 144:ef7eb2e8f9f7 170 .word EXTI0_IRQHandler /* EXTI Line0 */
<> 144:ef7eb2e8f9f7 171 .word EXTI1_IRQHandler /* EXTI Line1 */
<> 144:ef7eb2e8f9f7 172 .word EXTI2_IRQHandler /* EXTI Line2 */
<> 144:ef7eb2e8f9f7 173 .word EXTI3_IRQHandler /* EXTI Line3 */
<> 144:ef7eb2e8f9f7 174 .word EXTI4_IRQHandler /* EXTI Line4 */
<> 144:ef7eb2e8f9f7 175 .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
<> 144:ef7eb2e8f9f7 176 .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
<> 144:ef7eb2e8f9f7 177 .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
<> 144:ef7eb2e8f9f7 178 .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
<> 144:ef7eb2e8f9f7 179 .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
<> 144:ef7eb2e8f9f7 180 .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
<> 144:ef7eb2e8f9f7 181 .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
<> 144:ef7eb2e8f9f7 182 .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
<> 144:ef7eb2e8f9f7 183 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 184 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 185 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 186 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 187 .word EXTI9_5_IRQHandler /* External Line[9:5]s */
<> 144:ef7eb2e8f9f7 188 .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
<> 144:ef7eb2e8f9f7 189 .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
<> 144:ef7eb2e8f9f7 190 .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
<> 144:ef7eb2e8f9f7 191 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
<> 144:ef7eb2e8f9f7 192 .word TIM2_IRQHandler /* TIM2 */
<> 144:ef7eb2e8f9f7 193 .word TIM3_IRQHandler /* TIM3 */
<> 144:ef7eb2e8f9f7 194 .word TIM4_IRQHandler /* TIM4 */
<> 144:ef7eb2e8f9f7 195 .word I2C1_EV_IRQHandler /* I2C1 Event */
<> 144:ef7eb2e8f9f7 196 .word I2C1_ER_IRQHandler /* I2C1 Error */
<> 144:ef7eb2e8f9f7 197 .word I2C2_EV_IRQHandler /* I2C2 Event */
<> 144:ef7eb2e8f9f7 198 .word I2C2_ER_IRQHandler /* I2C2 Error */
<> 144:ef7eb2e8f9f7 199 .word SPI1_IRQHandler /* SPI1 */
<> 144:ef7eb2e8f9f7 200 .word SPI2_IRQHandler /* SPI2 */
<> 144:ef7eb2e8f9f7 201 .word USART1_IRQHandler /* USART1 */
<> 144:ef7eb2e8f9f7 202 .word USART2_IRQHandler /* USART2 */
<> 144:ef7eb2e8f9f7 203 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 204 .word EXTI15_10_IRQHandler /* External Line[15:10]s */
<> 144:ef7eb2e8f9f7 205 .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
<> 144:ef7eb2e8f9f7 206 .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
<> 144:ef7eb2e8f9f7 207 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 208 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 209 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 210 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 211 .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
<> 144:ef7eb2e8f9f7 212 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 213 .word SDIO_IRQHandler /* SDIO */
<> 144:ef7eb2e8f9f7 214 .word TIM5_IRQHandler /* TIM5 */
<> 144:ef7eb2e8f9f7 215 .word SPI3_IRQHandler /* SPI3 */
<> 144:ef7eb2e8f9f7 216 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 217 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 218 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 219 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 220 .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
<> 144:ef7eb2e8f9f7 221 .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
<> 144:ef7eb2e8f9f7 222 .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
<> 144:ef7eb2e8f9f7 223 .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
<> 144:ef7eb2e8f9f7 224 .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
<> 144:ef7eb2e8f9f7 225 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 226 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 227 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 228 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 229 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 230 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 231 .word OTG_FS_IRQHandler /* USB OTG FS */
<> 144:ef7eb2e8f9f7 232 .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
<> 144:ef7eb2e8f9f7 233 .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
<> 144:ef7eb2e8f9f7 234 .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
<> 144:ef7eb2e8f9f7 235 .word USART6_IRQHandler /* USART6 */
<> 144:ef7eb2e8f9f7 236 .word I2C3_EV_IRQHandler /* I2C3 event */
<> 144:ef7eb2e8f9f7 237 .word I2C3_ER_IRQHandler /* I2C3 error */
<> 144:ef7eb2e8f9f7 238 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 239 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 240 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 241 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 242 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 243 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 244 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 245 .word FPU_IRQHandler /* FPU */
<> 144:ef7eb2e8f9f7 246 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 247 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 248 .word SPI4_IRQHandler /* SPI4 */
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /*******************************************************************************
<> 144:ef7eb2e8f9f7 251 *
<> 144:ef7eb2e8f9f7 252 * Provide weak aliases for each Exception handler to the Default_Handler.
<> 144:ef7eb2e8f9f7 253 * As they are weak aliases, any function with the same name will override
<> 144:ef7eb2e8f9f7 254 * this definition.
<> 144:ef7eb2e8f9f7 255 *
<> 144:ef7eb2e8f9f7 256 *******************************************************************************/
<> 144:ef7eb2e8f9f7 257 .weak NMI_Handler
<> 144:ef7eb2e8f9f7 258 .thumb_set NMI_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 .weak HardFault_Handler
<> 144:ef7eb2e8f9f7 261 .thumb_set HardFault_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 .weak MemManage_Handler
<> 144:ef7eb2e8f9f7 264 .thumb_set MemManage_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 .weak BusFault_Handler
<> 144:ef7eb2e8f9f7 267 .thumb_set BusFault_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 .weak UsageFault_Handler
<> 144:ef7eb2e8f9f7 270 .thumb_set UsageFault_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 .weak SVC_Handler
<> 144:ef7eb2e8f9f7 273 .thumb_set SVC_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 .weak DebugMon_Handler
<> 144:ef7eb2e8f9f7 276 .thumb_set DebugMon_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 .weak PendSV_Handler
<> 144:ef7eb2e8f9f7 279 .thumb_set PendSV_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 .weak SysTick_Handler
<> 144:ef7eb2e8f9f7 282 .thumb_set SysTick_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 .weak WWDG_IRQHandler
<> 144:ef7eb2e8f9f7 285 .thumb_set WWDG_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 .weak PVD_IRQHandler
<> 144:ef7eb2e8f9f7 288 .thumb_set PVD_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 .weak TAMP_STAMP_IRQHandler
<> 144:ef7eb2e8f9f7 291 .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 .weak RTC_WKUP_IRQHandler
<> 144:ef7eb2e8f9f7 294 .thumb_set RTC_WKUP_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 .weak FLASH_IRQHandler
<> 144:ef7eb2e8f9f7 297 .thumb_set FLASH_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 .weak RCC_IRQHandler
<> 144:ef7eb2e8f9f7 300 .thumb_set RCC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 .weak EXTI0_IRQHandler
<> 144:ef7eb2e8f9f7 303 .thumb_set EXTI0_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 .weak EXTI1_IRQHandler
<> 144:ef7eb2e8f9f7 306 .thumb_set EXTI1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 .weak EXTI2_IRQHandler
<> 144:ef7eb2e8f9f7 309 .thumb_set EXTI2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 .weak EXTI3_IRQHandler
<> 144:ef7eb2e8f9f7 312 .thumb_set EXTI3_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 .weak EXTI4_IRQHandler
<> 144:ef7eb2e8f9f7 315 .thumb_set EXTI4_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 .weak DMA1_Stream0_IRQHandler
<> 144:ef7eb2e8f9f7 318 .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 .weak DMA1_Stream1_IRQHandler
<> 144:ef7eb2e8f9f7 321 .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 .weak DMA1_Stream2_IRQHandler
<> 144:ef7eb2e8f9f7 324 .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 .weak DMA1_Stream3_IRQHandler
<> 144:ef7eb2e8f9f7 327 .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 .weak DMA1_Stream4_IRQHandler
<> 144:ef7eb2e8f9f7 330 .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 .weak DMA1_Stream5_IRQHandler
<> 144:ef7eb2e8f9f7 333 .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 .weak DMA1_Stream6_IRQHandler
<> 144:ef7eb2e8f9f7 336 .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 .weak ADC_IRQHandler
<> 144:ef7eb2e8f9f7 339 .thumb_set ADC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 .weak EXTI9_5_IRQHandler
<> 144:ef7eb2e8f9f7 342 .thumb_set EXTI9_5_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 .weak TIM1_BRK_TIM9_IRQHandler
<> 144:ef7eb2e8f9f7 345 .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 .weak TIM1_UP_TIM10_IRQHandler
<> 144:ef7eb2e8f9f7 348 .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 .weak TIM1_TRG_COM_TIM11_IRQHandler
<> 144:ef7eb2e8f9f7 351 .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 .weak TIM1_CC_IRQHandler
<> 144:ef7eb2e8f9f7 354 .thumb_set TIM1_CC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 .weak TIM2_IRQHandler
<> 144:ef7eb2e8f9f7 357 .thumb_set TIM2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 .weak TIM3_IRQHandler
<> 144:ef7eb2e8f9f7 360 .thumb_set TIM3_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 .weak TIM4_IRQHandler
<> 144:ef7eb2e8f9f7 363 .thumb_set TIM4_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 .weak I2C1_EV_IRQHandler
<> 144:ef7eb2e8f9f7 366 .thumb_set I2C1_EV_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 .weak I2C1_ER_IRQHandler
<> 144:ef7eb2e8f9f7 369 .thumb_set I2C1_ER_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 .weak I2C2_EV_IRQHandler
<> 144:ef7eb2e8f9f7 372 .thumb_set I2C2_EV_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 .weak I2C2_ER_IRQHandler
<> 144:ef7eb2e8f9f7 375 .thumb_set I2C2_ER_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 .weak SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 378 .thumb_set SPI1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 .weak SPI2_IRQHandler
<> 144:ef7eb2e8f9f7 381 .thumb_set SPI2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 .weak USART1_IRQHandler
<> 144:ef7eb2e8f9f7 384 .thumb_set USART1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 .weak USART2_IRQHandler
<> 144:ef7eb2e8f9f7 387 .thumb_set USART2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 .weak EXTI15_10_IRQHandler
<> 144:ef7eb2e8f9f7 390 .thumb_set EXTI15_10_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 .weak RTC_Alarm_IRQHandler
<> 144:ef7eb2e8f9f7 393 .thumb_set RTC_Alarm_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 .weak OTG_FS_WKUP_IRQHandler
<> 144:ef7eb2e8f9f7 396 .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 .weak DMA1_Stream7_IRQHandler
<> 144:ef7eb2e8f9f7 399 .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 .weak SDIO_IRQHandler
<> 144:ef7eb2e8f9f7 402 .thumb_set SDIO_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 .weak TIM5_IRQHandler
<> 144:ef7eb2e8f9f7 405 .thumb_set TIM5_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 .weak SPI3_IRQHandler
<> 144:ef7eb2e8f9f7 408 .thumb_set SPI3_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 .weak DMA2_Stream0_IRQHandler
<> 144:ef7eb2e8f9f7 411 .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 .weak DMA2_Stream1_IRQHandler
<> 144:ef7eb2e8f9f7 414 .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 .weak DMA2_Stream2_IRQHandler
<> 144:ef7eb2e8f9f7 417 .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 .weak DMA2_Stream3_IRQHandler
<> 144:ef7eb2e8f9f7 420 .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 .weak DMA2_Stream4_IRQHandler
<> 144:ef7eb2e8f9f7 423 .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 .weak OTG_FS_IRQHandler
<> 144:ef7eb2e8f9f7 426 .thumb_set OTG_FS_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 .weak DMA2_Stream5_IRQHandler
<> 144:ef7eb2e8f9f7 429 .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 .weak DMA2_Stream6_IRQHandler
<> 144:ef7eb2e8f9f7 432 .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 .weak DMA2_Stream7_IRQHandler
<> 144:ef7eb2e8f9f7 435 .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 .weak USART6_IRQHandler
<> 144:ef7eb2e8f9f7 438 .thumb_set USART6_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 .weak I2C3_EV_IRQHandler
<> 144:ef7eb2e8f9f7 441 .thumb_set I2C3_EV_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 .weak I2C3_ER_IRQHandler
<> 144:ef7eb2e8f9f7 444 .thumb_set I2C3_ER_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 .weak FPU_IRQHandler
<> 144:ef7eb2e8f9f7 447 .thumb_set FPU_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 .weak SPI4_IRQHandler
<> 144:ef7eb2e8f9f7 450 .thumb_set SPI4_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 453