mbed official / mbed-dev

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/startup_stm32f031x6.S@182:a56a73fd2a6f, 2018-03-20 (annotated)

Committer:
AnnaBridge
Date:
Tue Mar 20 16:56:18 2018 +0000
Revision:
182:a56a73fd2a6f
Parent:
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/startup_stm32f031x6.s@180:96ed750bd169 
mbed-dev library. Release version 160

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
<> 144:ef7eb2e8f9f7 2 ;* File Name : startup_stm32f031x6.s
<> 144:ef7eb2e8f9f7 3 ;* Author : MCD Application Team
<> 144:ef7eb2e8f9f7 4 ;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain.
<> 144:ef7eb2e8f9f7 5 ;* This module performs:
<> 144:ef7eb2e8f9f7 6 ;* - Set the initial SP
<> 144:ef7eb2e8f9f7 7 ;* - Set the initial PC == Reset_Handler
<> 144:ef7eb2e8f9f7 8 ;* - Set the vector table entries with the exceptions ISR address
<> 144:ef7eb2e8f9f7 9 ;* - Branches to __main in the C library (which eventually
<> 144:ef7eb2e8f9f7 10 ;* calls main()).
<> 144:ef7eb2e8f9f7 11 ;* After Reset the CortexM0 processor is in Thread mode,
<> 144:ef7eb2e8f9f7 12 ;* priority is Privileged, and the Stack is set to Main.
<> 144:ef7eb2e8f9f7 13 ;* <<< Use Configuration Wizard in Context Menu >>>
<> 144:ef7eb2e8f9f7 14 ;*******************************************************************************
<> 144:ef7eb2e8f9f7 15 ;
<> 144:ef7eb2e8f9f7 16 ;* Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 17 ;* are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 18 ;* 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 19 ;* this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 20 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 21 ;* this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 22 ;* and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 23 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 24 ;* may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 25 ;* without specific prior written permission.
<> 144:ef7eb2e8f9f7 26 ;*
<> 144:ef7eb2e8f9f7 27 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 28 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 29 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 30 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 31 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 32 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 33 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 34 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 35 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 36 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 37 ;
<> 144:ef7eb2e8f9f7 38 ;*******************************************************************************
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 __initial_sp EQU 0x20001000 ; Top of RAM
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 PRESERVE8
<> 144:ef7eb2e8f9f7 43 THUMB
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 ; Vector Table Mapped to Address 0 at Reset
<> 144:ef7eb2e8f9f7 47 AREA RESET, DATA, READONLY
<> 144:ef7eb2e8f9f7 48 EXPORT __Vectors
<> 144:ef7eb2e8f9f7 49 EXPORT __Vectors_End
<> 144:ef7eb2e8f9f7 50 EXPORT __Vectors_Size
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 __Vectors DCD __initial_sp ; Top of Stack
<> 144:ef7eb2e8f9f7 53 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 54 DCD NMI_Handler ; NMI Handler
<> 144:ef7eb2e8f9f7 55 DCD HardFault_Handler ; Hard Fault Handler
<> 144:ef7eb2e8f9f7 56 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 57 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 58 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 59 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 60 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 61 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 62 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 63 DCD SVC_Handler ; SVCall Handler
<> 144:ef7eb2e8f9f7 64 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 65 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 66 DCD PendSV_Handler ; PendSV Handler
<> 144:ef7eb2e8f9f7 67 DCD SysTick_Handler ; SysTick Handler
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 ; External Interrupts
<> 144:ef7eb2e8f9f7 70 DCD WWDG_IRQHandler ; Window Watchdog
<> 144:ef7eb2e8f9f7 71 DCD PVD_IRQHandler ; PVD through EXTI Line detect
<> 144:ef7eb2e8f9f7 72 DCD RTC_IRQHandler ; RTC through EXTI Line
<> 144:ef7eb2e8f9f7 73 DCD FLASH_IRQHandler ; FLASH
<> 144:ef7eb2e8f9f7 74 DCD RCC_IRQHandler ; RCC
<> 144:ef7eb2e8f9f7 75 DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
<> 144:ef7eb2e8f9f7 76 DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
<> 144:ef7eb2e8f9f7 77 DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
<> 144:ef7eb2e8f9f7 78 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 79 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
<> 144:ef7eb2e8f9f7 80 DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
<> 144:ef7eb2e8f9f7 81 DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
<> 144:ef7eb2e8f9f7 82 DCD ADC1_IRQHandler ; ADC1
<> 144:ef7eb2e8f9f7 83 DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
<> 144:ef7eb2e8f9f7 84 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
<> 144:ef7eb2e8f9f7 85 DCD TIM2_IRQHandler ; TIM2
<> 144:ef7eb2e8f9f7 86 DCD TIM3_IRQHandler ; TIM3
<> 144:ef7eb2e8f9f7 87 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 88 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 89 DCD TIM14_IRQHandler ; TIM14
<> 144:ef7eb2e8f9f7 90 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 91 DCD TIM16_IRQHandler ; TIM16
<> 144:ef7eb2e8f9f7 92 DCD TIM17_IRQHandler ; TIM17
<> 144:ef7eb2e8f9f7 93 DCD I2C1_IRQHandler ; I2C1
<> 144:ef7eb2e8f9f7 94 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 95 DCD SPI1_IRQHandler ; SPI1
<> 144:ef7eb2e8f9f7 96 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 97 DCD USART1_IRQHandler ; USART1
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 __Vectors_End
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 __Vectors_Size EQU __Vectors_End - __Vectors
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 AREA |.text|, CODE, READONLY
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 ; Reset handler routine
<> 144:ef7eb2e8f9f7 107 Reset_Handler PROC
<> 144:ef7eb2e8f9f7 108 EXPORT Reset_Handler [WEAK]
<> 144:ef7eb2e8f9f7 109 IMPORT __main
<> 144:ef7eb2e8f9f7 110 IMPORT SystemInit
<> 144:ef7eb2e8f9f7 111 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 112 BLX R0
<> 144:ef7eb2e8f9f7 113 LDR R0, =__main
<> 144:ef7eb2e8f9f7 114 BX R0
<> 144:ef7eb2e8f9f7 115 ENDP
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 NMI_Handler PROC
<> 144:ef7eb2e8f9f7 120 EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 121 B .
<> 144:ef7eb2e8f9f7 122 ENDP
<> 144:ef7eb2e8f9f7 123 HardFault_Handler\
<> 144:ef7eb2e8f9f7 124 PROC
<> 144:ef7eb2e8f9f7 125 EXPORT HardFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 126 B .
<> 144:ef7eb2e8f9f7 127 ENDP
<> 144:ef7eb2e8f9f7 128 SVC_Handler PROC
<> 144:ef7eb2e8f9f7 129 EXPORT SVC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 130 B .
<> 144:ef7eb2e8f9f7 131 ENDP
<> 144:ef7eb2e8f9f7 132 PendSV_Handler PROC
<> 144:ef7eb2e8f9f7 133 EXPORT PendSV_Handler [WEAK]
<> 144:ef7eb2e8f9f7 134 B .
<> 144:ef7eb2e8f9f7 135 ENDP
<> 144:ef7eb2e8f9f7 136 SysTick_Handler PROC
<> 144:ef7eb2e8f9f7 137 EXPORT SysTick_Handler [WEAK]
<> 144:ef7eb2e8f9f7 138 B .
<> 144:ef7eb2e8f9f7 139 ENDP
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 Default_Handler PROC
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 EXPORT WWDG_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 144 EXPORT PVD_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 145 EXPORT RTC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 146 EXPORT FLASH_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 147 EXPORT RCC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 148 EXPORT EXTI0_1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 149 EXPORT EXTI2_3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 150 EXPORT EXTI4_15_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 151 EXPORT DMA1_Channel1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 152 EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 153 EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 154 EXPORT ADC1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 155 EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 156 EXPORT TIM1_CC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 157 EXPORT TIM2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 158 EXPORT TIM3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 159 EXPORT TIM14_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 160 EXPORT TIM16_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 161 EXPORT TIM17_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 162 EXPORT I2C1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 163 EXPORT SPI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 164 EXPORT USART1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 WWDG_IRQHandler
<> 144:ef7eb2e8f9f7 168 PVD_IRQHandler
<> 144:ef7eb2e8f9f7 169 RTC_IRQHandler
<> 144:ef7eb2e8f9f7 170 FLASH_IRQHandler
<> 144:ef7eb2e8f9f7 171 RCC_IRQHandler
<> 144:ef7eb2e8f9f7 172 EXTI0_1_IRQHandler
<> 144:ef7eb2e8f9f7 173 EXTI2_3_IRQHandler
<> 144:ef7eb2e8f9f7 174 EXTI4_15_IRQHandler
<> 144:ef7eb2e8f9f7 175 DMA1_Channel1_IRQHandler
<> 144:ef7eb2e8f9f7 176 DMA1_Channel2_3_IRQHandler
<> 144:ef7eb2e8f9f7 177 DMA1_Channel4_5_IRQHandler
<> 144:ef7eb2e8f9f7 178 ADC1_IRQHandler
<> 144:ef7eb2e8f9f7 179 TIM1_BRK_UP_TRG_COM_IRQHandler
<> 144:ef7eb2e8f9f7 180 TIM1_CC_IRQHandler
<> 144:ef7eb2e8f9f7 181 TIM2_IRQHandler
<> 144:ef7eb2e8f9f7 182 TIM3_IRQHandler
<> 144:ef7eb2e8f9f7 183 TIM14_IRQHandler
<> 144:ef7eb2e8f9f7 184 TIM16_IRQHandler
<> 144:ef7eb2e8f9f7 185 TIM17_IRQHandler
<> 144:ef7eb2e8f9f7 186 I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 187 SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 188 USART1_IRQHandler
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 B .
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 ENDP
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 ALIGN
<> 144:ef7eb2e8f9f7 195 END
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****