mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c@180:96ed750bd169, 2018-01-17 (annotated)
- Committer:
- Anna Bridge
- Date:
- Wed Jan 17 15:23:54 2018 +0000
- Revision:
- 180:96ed750bd169
- Parent:
- 179:b0033dcd6934
- Child:
- 184:08ed48f1de7f
mbed-dev libray. Release version 158
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 2 | * @file spi_api.c |
<> | 144:ef7eb2e8f9f7 | 3 | ******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 4 | * @section License |
<> | 144:ef7eb2e8f9f7 | 5 | * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b> |
<> | 144:ef7eb2e8f9f7 | 6 | ******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * SPDX-License-Identifier: Apache-2.0 |
<> | 144:ef7eb2e8f9f7 | 9 | * |
<> | 144:ef7eb2e8f9f7 | 10 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
<> | 144:ef7eb2e8f9f7 | 11 | * not use this file except in compliance with the License. |
<> | 144:ef7eb2e8f9f7 | 12 | * You may obtain a copy of the License at |
<> | 144:ef7eb2e8f9f7 | 13 | * |
<> | 144:ef7eb2e8f9f7 | 14 | * http://www.apache.org/licenses/LICENSE-2.0 |
<> | 144:ef7eb2e8f9f7 | 15 | * |
<> | 144:ef7eb2e8f9f7 | 16 | * Unless required by applicable law or agreed to in writing, software |
<> | 144:ef7eb2e8f9f7 | 17 | * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
<> | 144:ef7eb2e8f9f7 | 18 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
<> | 144:ef7eb2e8f9f7 | 19 | * See the License for the specific language governing permissions and |
<> | 144:ef7eb2e8f9f7 | 20 | * limitations under the License. |
<> | 144:ef7eb2e8f9f7 | 21 | * |
<> | 144:ef7eb2e8f9f7 | 22 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 23 | |
<> | 144:ef7eb2e8f9f7 | 24 | #include "device.h" |
<> | 144:ef7eb2e8f9f7 | 25 | #include "clocking.h" |
<> | 144:ef7eb2e8f9f7 | 26 | #if DEVICE_SPI |
<> | 144:ef7eb2e8f9f7 | 27 | |
<> | 144:ef7eb2e8f9f7 | 28 | #include "mbed_assert.h" |
Anna Bridge |
180:96ed750bd169 | 29 | #include "mbed_sleep.h" |
<> | 144:ef7eb2e8f9f7 | 30 | #include "PeripheralPins.h" |
<> | 144:ef7eb2e8f9f7 | 31 | #include "pinmap.h" |
<> | 144:ef7eb2e8f9f7 | 32 | #include "pinmap_function.h" |
<> | 150:02e0a0aed4ec | 33 | #include "mbed_error.h" |
<> | 144:ef7eb2e8f9f7 | 34 | |
<> | 144:ef7eb2e8f9f7 | 35 | #include "dma_api.h" |
<> | 144:ef7eb2e8f9f7 | 36 | #include "dma_api_HAL.h" |
<> | 144:ef7eb2e8f9f7 | 37 | #include "serial_api_HAL.h" |
<> | 144:ef7eb2e8f9f7 | 38 | #include "spi_api.h" |
<> | 144:ef7eb2e8f9f7 | 39 | #include "em_usart.h" |
<> | 144:ef7eb2e8f9f7 | 40 | #include "em_cmu.h" |
<> | 144:ef7eb2e8f9f7 | 41 | #include "em_dma.h" |
<> | 144:ef7eb2e8f9f7 | 42 | #include "sleep_api.h" |
<> | 144:ef7eb2e8f9f7 | 43 | |
<> | 144:ef7eb2e8f9f7 | 44 | static uint16_t fill_word = SPI_FILL_WORD; |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | static inline CMU_Clock_TypeDef spi_get_clock_tree(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 47 | { |
<> | 144:ef7eb2e8f9f7 | 48 | switch ((int)obj->spi.spi) { |
<> | 144:ef7eb2e8f9f7 | 49 | #ifdef USART0 |
<> | 144:ef7eb2e8f9f7 | 50 | case SPI_0: |
<> | 144:ef7eb2e8f9f7 | 51 | return cmuClock_USART0; |
<> | 144:ef7eb2e8f9f7 | 52 | #endif |
<> | 144:ef7eb2e8f9f7 | 53 | #ifdef USART1 |
<> | 144:ef7eb2e8f9f7 | 54 | case SPI_1: |
<> | 144:ef7eb2e8f9f7 | 55 | return cmuClock_USART1; |
<> | 144:ef7eb2e8f9f7 | 56 | #endif |
<> | 144:ef7eb2e8f9f7 | 57 | #ifdef USART2 |
<> | 144:ef7eb2e8f9f7 | 58 | case SPI_2: |
<> | 144:ef7eb2e8f9f7 | 59 | return cmuClock_USART2; |
<> | 144:ef7eb2e8f9f7 | 60 | #endif |
AnnaBridge | 179:b0033dcd6934 | 61 | #ifdef USART3 |
AnnaBridge | 179:b0033dcd6934 | 62 | case SPI_3: |
AnnaBridge | 179:b0033dcd6934 | 63 | return cmuClock_USART3; |
AnnaBridge | 179:b0033dcd6934 | 64 | #endif |
AnnaBridge | 179:b0033dcd6934 | 65 | #ifdef USART4 |
AnnaBridge | 179:b0033dcd6934 | 66 | case SPI_4: |
AnnaBridge | 179:b0033dcd6934 | 67 | return cmuClock_USART4; |
AnnaBridge | 179:b0033dcd6934 | 68 | #endif |
AnnaBridge | 179:b0033dcd6934 | 69 | #ifdef USART5 |
AnnaBridge | 179:b0033dcd6934 | 70 | case SPI_5: |
AnnaBridge | 179:b0033dcd6934 | 71 | return cmuClock_USART5; |
AnnaBridge | 179:b0033dcd6934 | 72 | #endif |
<> | 144:ef7eb2e8f9f7 | 73 | default: |
<> | 144:ef7eb2e8f9f7 | 74 | error("Spi module not available.. Out of bound access."); |
<> | 144:ef7eb2e8f9f7 | 75 | return cmuClock_HFPER; |
<> | 144:ef7eb2e8f9f7 | 76 | } |
<> | 144:ef7eb2e8f9f7 | 77 | } |
<> | 144:ef7eb2e8f9f7 | 78 | |
<> | 144:ef7eb2e8f9f7 | 79 | static inline uint8_t spi_get_index(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 80 | { |
<> | 144:ef7eb2e8f9f7 | 81 | uint8_t index = 0; |
<> | 144:ef7eb2e8f9f7 | 82 | switch ((int)obj->spi.spi) { |
<> | 144:ef7eb2e8f9f7 | 83 | #ifdef USART0 |
<> | 144:ef7eb2e8f9f7 | 84 | case SPI_0: |
<> | 144:ef7eb2e8f9f7 | 85 | index = 0; |
<> | 144:ef7eb2e8f9f7 | 86 | break; |
<> | 144:ef7eb2e8f9f7 | 87 | #endif |
<> | 144:ef7eb2e8f9f7 | 88 | #ifdef USART1 |
<> | 144:ef7eb2e8f9f7 | 89 | case SPI_1: |
<> | 144:ef7eb2e8f9f7 | 90 | index = 1; |
<> | 144:ef7eb2e8f9f7 | 91 | break; |
<> | 144:ef7eb2e8f9f7 | 92 | #endif |
<> | 144:ef7eb2e8f9f7 | 93 | #ifdef USART2 |
<> | 144:ef7eb2e8f9f7 | 94 | case SPI_2: |
<> | 144:ef7eb2e8f9f7 | 95 | index = 2; |
<> | 144:ef7eb2e8f9f7 | 96 | break; |
<> | 144:ef7eb2e8f9f7 | 97 | #endif |
AnnaBridge | 179:b0033dcd6934 | 98 | #ifdef USART3 |
AnnaBridge | 179:b0033dcd6934 | 99 | case SPI_3: |
AnnaBridge | 179:b0033dcd6934 | 100 | index = 3; |
AnnaBridge | 179:b0033dcd6934 | 101 | break; |
AnnaBridge | 179:b0033dcd6934 | 102 | #endif |
AnnaBridge | 179:b0033dcd6934 | 103 | #ifdef USART4 |
AnnaBridge | 179:b0033dcd6934 | 104 | case SPI_4: |
AnnaBridge | 179:b0033dcd6934 | 105 | index = 4; |
AnnaBridge | 179:b0033dcd6934 | 106 | break; |
AnnaBridge | 179:b0033dcd6934 | 107 | #endif |
AnnaBridge | 179:b0033dcd6934 | 108 | #ifdef USART5 |
AnnaBridge | 179:b0033dcd6934 | 109 | case SPI_5: |
AnnaBridge | 179:b0033dcd6934 | 110 | index = 5; |
AnnaBridge | 179:b0033dcd6934 | 111 | break; |
AnnaBridge | 179:b0033dcd6934 | 112 | #endif |
<> | 144:ef7eb2e8f9f7 | 113 | default: |
<> | 144:ef7eb2e8f9f7 | 114 | error("Spi module not available.. Out of bound access."); |
<> | 144:ef7eb2e8f9f7 | 115 | break; |
<> | 144:ef7eb2e8f9f7 | 116 | } |
<> | 144:ef7eb2e8f9f7 | 117 | return index; |
<> | 144:ef7eb2e8f9f7 | 118 | } |
<> | 144:ef7eb2e8f9f7 | 119 | |
<> | 144:ef7eb2e8f9f7 | 120 | uint8_t spi_get_module(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 121 | { |
<> | 144:ef7eb2e8f9f7 | 122 | return spi_get_index(obj); |
<> | 144:ef7eb2e8f9f7 | 123 | } |
<> | 144:ef7eb2e8f9f7 | 124 | |
<> | 144:ef7eb2e8f9f7 | 125 | static void usart_init(spi_t *obj, uint32_t baudrate, USART_Databits_TypeDef databits, bool master, USART_ClockMode_TypeDef clockMode ) |
<> | 144:ef7eb2e8f9f7 | 126 | { |
<> | 144:ef7eb2e8f9f7 | 127 | USART_InitSync_TypeDef init = USART_INITSYNC_DEFAULT; |
<> | 144:ef7eb2e8f9f7 | 128 | init.enable = usartDisable; |
<> | 144:ef7eb2e8f9f7 | 129 | init.baudrate = baudrate; |
<> | 144:ef7eb2e8f9f7 | 130 | init.databits = databits; |
<> | 144:ef7eb2e8f9f7 | 131 | init.master = master; |
<> | 144:ef7eb2e8f9f7 | 132 | init.msbf = 1; |
<> | 144:ef7eb2e8f9f7 | 133 | init.clockMode = clockMode; |
<> | 144:ef7eb2e8f9f7 | 134 | |
<> | 144:ef7eb2e8f9f7 | 135 | /* Determine the reference clock, because the correct clock may not be set up at init time (e.g. before main()) */ |
<> | 144:ef7eb2e8f9f7 | 136 | init.refFreq = REFERENCE_FREQUENCY; |
<> | 144:ef7eb2e8f9f7 | 137 | |
<> | 144:ef7eb2e8f9f7 | 138 | USART_InitSync(obj->spi.spi, &init); |
<> | 144:ef7eb2e8f9f7 | 139 | } |
<> | 144:ef7eb2e8f9f7 | 140 | |
<> | 144:ef7eb2e8f9f7 | 141 | void spi_preinit(spi_t *obj, PinName mosi, PinName miso, PinName clk, PinName cs) |
<> | 144:ef7eb2e8f9f7 | 142 | { |
<> | 144:ef7eb2e8f9f7 | 143 | SPIName spi_mosi = (SPIName) pinmap_peripheral(mosi, PinMap_SPI_MOSI); |
<> | 144:ef7eb2e8f9f7 | 144 | SPIName spi_miso = (SPIName) pinmap_peripheral(miso, PinMap_SPI_MISO); |
<> | 144:ef7eb2e8f9f7 | 145 | SPIName spi_clk = (SPIName) pinmap_peripheral(clk, PinMap_SPI_CLK); |
<> | 144:ef7eb2e8f9f7 | 146 | SPIName spi_cs = (SPIName) pinmap_peripheral(cs, PinMap_SPI_CS); |
<> | 144:ef7eb2e8f9f7 | 147 | SPIName spi_data = (SPIName) pinmap_merge(spi_mosi, spi_miso); |
<> | 144:ef7eb2e8f9f7 | 148 | SPIName spi_ctrl = (SPIName) pinmap_merge(spi_clk, spi_cs); |
<> | 144:ef7eb2e8f9f7 | 149 | |
<> | 144:ef7eb2e8f9f7 | 150 | obj->spi.spi = (USART_TypeDef *) pinmap_merge(spi_data, spi_ctrl); |
AnnaBridge | 179:b0033dcd6934 | 151 | MBED_ASSERT((unsigned int) obj->spi.spi != NC); |
<> | 144:ef7eb2e8f9f7 | 152 | |
<> | 144:ef7eb2e8f9f7 | 153 | if (cs != NC) { /* Slave mode */ |
<> | 144:ef7eb2e8f9f7 | 154 | obj->spi.master = false; |
<> | 144:ef7eb2e8f9f7 | 155 | } else { |
<> | 144:ef7eb2e8f9f7 | 156 | obj->spi.master = true; |
<> | 144:ef7eb2e8f9f7 | 157 | } |
<> | 144:ef7eb2e8f9f7 | 158 | |
<> | 144:ef7eb2e8f9f7 | 159 | #if defined(_SILICON_LABS_32B_PLATFORM_1) |
<> | 144:ef7eb2e8f9f7 | 160 | // On P1, we need to ensure all pins are on same location |
<> | 144:ef7eb2e8f9f7 | 161 | uint32_t loc_mosi = pin_location(mosi, PinMap_SPI_MOSI); |
<> | 144:ef7eb2e8f9f7 | 162 | uint32_t loc_miso = pin_location(miso, PinMap_SPI_MISO); |
<> | 144:ef7eb2e8f9f7 | 163 | uint32_t loc_clk = pin_location(clk, PinMap_SPI_CLK); |
<> | 144:ef7eb2e8f9f7 | 164 | uint32_t loc_cs = pin_location(cs, PinMap_SPI_CS); |
<> | 144:ef7eb2e8f9f7 | 165 | uint32_t loc_data = pinmap_merge(loc_mosi, loc_miso); |
<> | 144:ef7eb2e8f9f7 | 166 | uint32_t loc_ctrl = pinmap_merge(loc_clk, loc_cs); |
<> | 144:ef7eb2e8f9f7 | 167 | obj->spi.location = pinmap_merge(loc_data, loc_ctrl); |
<> | 144:ef7eb2e8f9f7 | 168 | MBED_ASSERT(obj->spi.location != NC); |
<> | 144:ef7eb2e8f9f7 | 169 | #endif |
<> | 144:ef7eb2e8f9f7 | 170 | |
<> | 144:ef7eb2e8f9f7 | 171 | obj->spi.dmaOptionsTX.dmaUsageState = DMA_USAGE_OPPORTUNISTIC; |
<> | 144:ef7eb2e8f9f7 | 172 | } |
<> | 144:ef7eb2e8f9f7 | 173 | |
<> | 144:ef7eb2e8f9f7 | 174 | void spi_enable_pins(spi_t *obj, uint8_t enable, PinName mosi, PinName miso, PinName clk, PinName cs) |
<> | 144:ef7eb2e8f9f7 | 175 | { |
<> | 144:ef7eb2e8f9f7 | 176 | if (enable) { |
<> | 144:ef7eb2e8f9f7 | 177 | if (obj->spi.master) { /* Master mode */ |
<> | 144:ef7eb2e8f9f7 | 178 | /* Either mosi or miso can be NC */ |
<> | 144:ef7eb2e8f9f7 | 179 | if (mosi != NC) { |
<> | 144:ef7eb2e8f9f7 | 180 | pin_mode(mosi, PushPull); |
<> | 144:ef7eb2e8f9f7 | 181 | } |
<> | 144:ef7eb2e8f9f7 | 182 | if (miso != NC) { |
<> | 144:ef7eb2e8f9f7 | 183 | pin_mode(miso, Input); |
<> | 144:ef7eb2e8f9f7 | 184 | } |
<> | 144:ef7eb2e8f9f7 | 185 | pin_mode(clk, PushPull); |
<> | 144:ef7eb2e8f9f7 | 186 | /* Don't set cs pin, since we toggle it manually */ |
<> | 144:ef7eb2e8f9f7 | 187 | } else { /* Slave mode */ |
<> | 144:ef7eb2e8f9f7 | 188 | if (mosi != NC) { |
<> | 144:ef7eb2e8f9f7 | 189 | pin_mode(mosi, Input); |
<> | 144:ef7eb2e8f9f7 | 190 | } |
<> | 144:ef7eb2e8f9f7 | 191 | if (miso != NC) { |
<> | 144:ef7eb2e8f9f7 | 192 | pin_mode(miso, PushPull); |
<> | 144:ef7eb2e8f9f7 | 193 | } |
<> | 144:ef7eb2e8f9f7 | 194 | pin_mode(clk, Input); |
<> | 144:ef7eb2e8f9f7 | 195 | pin_mode(cs, Input); |
<> | 144:ef7eb2e8f9f7 | 196 | } |
<> | 144:ef7eb2e8f9f7 | 197 | } else { |
<> | 144:ef7eb2e8f9f7 | 198 | // TODO_LP return PinMode to the previous state |
<> | 144:ef7eb2e8f9f7 | 199 | if (obj->spi.master) { /* Master mode */ |
<> | 144:ef7eb2e8f9f7 | 200 | /* Either mosi or miso can be NC */ |
<> | 144:ef7eb2e8f9f7 | 201 | if (mosi != NC) { |
<> | 144:ef7eb2e8f9f7 | 202 | pin_mode(mosi, Disabled); |
<> | 144:ef7eb2e8f9f7 | 203 | } |
<> | 144:ef7eb2e8f9f7 | 204 | if (miso != NC) { |
<> | 144:ef7eb2e8f9f7 | 205 | pin_mode(miso, Disabled); |
<> | 144:ef7eb2e8f9f7 | 206 | } |
<> | 144:ef7eb2e8f9f7 | 207 | pin_mode(clk, Disabled); |
<> | 144:ef7eb2e8f9f7 | 208 | /* Don't set cs pin, since we toggle it manually */ |
<> | 144:ef7eb2e8f9f7 | 209 | } else { /* Slave mode */ |
<> | 144:ef7eb2e8f9f7 | 210 | if (mosi != NC) { |
<> | 144:ef7eb2e8f9f7 | 211 | pin_mode(mosi, Disabled); |
<> | 144:ef7eb2e8f9f7 | 212 | } |
<> | 144:ef7eb2e8f9f7 | 213 | if (miso != NC) { |
<> | 144:ef7eb2e8f9f7 | 214 | pin_mode(miso, Disabled); |
<> | 144:ef7eb2e8f9f7 | 215 | } |
<> | 144:ef7eb2e8f9f7 | 216 | pin_mode(clk, Disabled); |
<> | 144:ef7eb2e8f9f7 | 217 | pin_mode(cs, Disabled); |
<> | 144:ef7eb2e8f9f7 | 218 | } |
<> | 144:ef7eb2e8f9f7 | 219 | } |
<> | 144:ef7eb2e8f9f7 | 220 | |
<> | 144:ef7eb2e8f9f7 | 221 | /* Enabling pins and setting location */ |
<> | 144:ef7eb2e8f9f7 | 222 | #ifdef _USART_ROUTEPEN_RESETVALUE |
<> | 144:ef7eb2e8f9f7 | 223 | uint32_t route = USART_ROUTEPEN_CLKPEN; |
AnnaBridge | 167:e84263d55307 | 224 | |
<> | 144:ef7eb2e8f9f7 | 225 | obj->spi.spi->ROUTELOC0 &= ~_USART_ROUTELOC0_CLKLOC_MASK; |
<> | 144:ef7eb2e8f9f7 | 226 | obj->spi.spi->ROUTELOC0 |= pin_location(clk, PinMap_SPI_CLK)<<_USART_ROUTELOC0_CLKLOC_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 227 | if (mosi != NC) { |
<> | 144:ef7eb2e8f9f7 | 228 | route |= USART_ROUTEPEN_TXPEN; |
<> | 144:ef7eb2e8f9f7 | 229 | obj->spi.spi->ROUTELOC0 &= ~_USART_ROUTELOC0_TXLOC_MASK; |
<> | 144:ef7eb2e8f9f7 | 230 | obj->spi.spi->ROUTELOC0 |= pin_location(mosi, PinMap_SPI_MOSI)<<_USART_ROUTELOC0_TXLOC_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 231 | } |
<> | 144:ef7eb2e8f9f7 | 232 | if (miso != NC) { |
<> | 144:ef7eb2e8f9f7 | 233 | route |= USART_ROUTEPEN_RXPEN; |
<> | 144:ef7eb2e8f9f7 | 234 | obj->spi.spi->ROUTELOC0 &= ~_USART_ROUTELOC0_RXLOC_MASK; |
AnnaBridge | 167:e84263d55307 | 235 | obj->spi.spi->ROUTELOC0 |= pin_location(miso, PinMap_SPI_MISO)<<_USART_ROUTELOC0_RXLOC_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 236 | } |
<> | 144:ef7eb2e8f9f7 | 237 | if (!obj->spi.master) { |
<> | 144:ef7eb2e8f9f7 | 238 | route |= USART_ROUTEPEN_CSPEN; |
<> | 144:ef7eb2e8f9f7 | 239 | obj->spi.spi->ROUTELOC0 &= ~_USART_ROUTELOC0_CSLOC_MASK; |
AnnaBridge | 167:e84263d55307 | 240 | obj->spi.spi->ROUTELOC0 |= pin_location(cs, PinMap_SPI_CS)<<_USART_ROUTELOC0_CSLOC_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 241 | } |
Anna Bridge |
163:74e0ce7f98e8 | 242 | obj->spi.location = obj->spi.spi->ROUTELOC0; |
Anna Bridge |
163:74e0ce7f98e8 | 243 | obj->spi.route = route; |
<> | 144:ef7eb2e8f9f7 | 244 | obj->spi.spi->ROUTEPEN = route; |
<> | 144:ef7eb2e8f9f7 | 245 | } |
<> | 144:ef7eb2e8f9f7 | 246 | #else |
Anna Bridge |
163:74e0ce7f98e8 | 247 | uint32_t route = USART_ROUTE_CLKPEN; |
<> | 144:ef7eb2e8f9f7 | 248 | |
<> | 144:ef7eb2e8f9f7 | 249 | if (mosi != NC) { |
<> | 144:ef7eb2e8f9f7 | 250 | route |= USART_ROUTE_TXPEN; |
<> | 144:ef7eb2e8f9f7 | 251 | } |
<> | 144:ef7eb2e8f9f7 | 252 | if (miso != NC) { |
<> | 144:ef7eb2e8f9f7 | 253 | route |= USART_ROUTE_RXPEN; |
<> | 144:ef7eb2e8f9f7 | 254 | } |
<> | 144:ef7eb2e8f9f7 | 255 | if (!obj->spi.master) { |
<> | 144:ef7eb2e8f9f7 | 256 | route |= USART_ROUTE_CSPEN; |
<> | 144:ef7eb2e8f9f7 | 257 | } |
Anna Bridge |
163:74e0ce7f98e8 | 258 | route |= obj->spi.location << _USART_ROUTE_LOCATION_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 259 | obj->spi.spi->ROUTE = route; |
Anna Bridge |
163:74e0ce7f98e8 | 260 | obj->spi.route = route; |
<> | 144:ef7eb2e8f9f7 | 261 | } |
<> | 144:ef7eb2e8f9f7 | 262 | #endif |
<> | 144:ef7eb2e8f9f7 | 263 | void spi_enable(spi_t *obj, uint8_t enable) |
<> | 144:ef7eb2e8f9f7 | 264 | { |
<> | 144:ef7eb2e8f9f7 | 265 | USART_Enable(obj->spi.spi, (enable ? usartEnable : usartDisable)); |
<> | 144:ef7eb2e8f9f7 | 266 | } |
<> | 144:ef7eb2e8f9f7 | 267 | |
<> | 144:ef7eb2e8f9f7 | 268 | void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName clk, PinName cs) |
<> | 144:ef7eb2e8f9f7 | 269 | { |
<> | 144:ef7eb2e8f9f7 | 270 | CMU_ClockEnable(cmuClock_HFPER, true); |
<> | 144:ef7eb2e8f9f7 | 271 | spi_preinit(obj, mosi, miso, clk, cs); |
<> | 144:ef7eb2e8f9f7 | 272 | CMU_ClockEnable(spi_get_clock_tree(obj), true); |
<> | 144:ef7eb2e8f9f7 | 273 | usart_init(obj, 100000, usartDatabits8, true, usartClockMode0); |
<> | 144:ef7eb2e8f9f7 | 274 | |
<> | 144:ef7eb2e8f9f7 | 275 | spi_enable_pins(obj, true, mosi, miso, clk, cs); |
<> | 144:ef7eb2e8f9f7 | 276 | spi_enable(obj, true); |
<> | 144:ef7eb2e8f9f7 | 277 | } |
<> | 144:ef7eb2e8f9f7 | 278 | |
<> | 144:ef7eb2e8f9f7 | 279 | void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable) |
<> | 144:ef7eb2e8f9f7 | 280 | { |
<> | 144:ef7eb2e8f9f7 | 281 | if(enable) obj->spi.event |= event; |
<> | 144:ef7eb2e8f9f7 | 282 | else obj->spi.event &= ~event; |
<> | 144:ef7eb2e8f9f7 | 283 | } |
<> | 144:ef7eb2e8f9f7 | 284 | |
<> | 144:ef7eb2e8f9f7 | 285 | /**************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 286 | * void spi_enable_interrupt(spi_t *obj, uint32_t handler, uint8_t enable) |
<> | 144:ef7eb2e8f9f7 | 287 | * |
<> | 144:ef7eb2e8f9f7 | 288 | * This will enable the interrupt in NVIC for the associated USART RX channel |
<> | 144:ef7eb2e8f9f7 | 289 | * |
<> | 144:ef7eb2e8f9f7 | 290 | * * obj: pointer to spi object |
<> | 144:ef7eb2e8f9f7 | 291 | * * handler: pointer to interrupt handler for this channel |
<> | 144:ef7eb2e8f9f7 | 292 | * * enable: Whether to enable (true) or disable (false) the interrupt |
<> | 144:ef7eb2e8f9f7 | 293 | * |
<> | 144:ef7eb2e8f9f7 | 294 | ****************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 295 | void spi_enable_interrupt(spi_t *obj, uint32_t handler, uint8_t enable) |
<> | 144:ef7eb2e8f9f7 | 296 | { |
<> | 144:ef7eb2e8f9f7 | 297 | IRQn_Type IRQvector; |
<> | 144:ef7eb2e8f9f7 | 298 | |
<> | 144:ef7eb2e8f9f7 | 299 | switch ((uint32_t)obj->spi.spi) { |
<> | 144:ef7eb2e8f9f7 | 300 | #ifdef USART0 |
<> | 144:ef7eb2e8f9f7 | 301 | case USART_0: |
<> | 144:ef7eb2e8f9f7 | 302 | IRQvector = USART0_RX_IRQn; |
<> | 144:ef7eb2e8f9f7 | 303 | break; |
<> | 144:ef7eb2e8f9f7 | 304 | #endif |
<> | 144:ef7eb2e8f9f7 | 305 | #ifdef USART1 |
<> | 144:ef7eb2e8f9f7 | 306 | case USART_1: |
<> | 144:ef7eb2e8f9f7 | 307 | IRQvector = USART1_RX_IRQn; |
<> | 144:ef7eb2e8f9f7 | 308 | break; |
<> | 144:ef7eb2e8f9f7 | 309 | #endif |
<> | 144:ef7eb2e8f9f7 | 310 | #ifdef USART2 |
<> | 144:ef7eb2e8f9f7 | 311 | case USART_2: |
<> | 144:ef7eb2e8f9f7 | 312 | IRQvector = USART2_RX_IRQn; |
<> | 144:ef7eb2e8f9f7 | 313 | break; |
<> | 144:ef7eb2e8f9f7 | 314 | #endif |
AnnaBridge | 179:b0033dcd6934 | 315 | #ifdef USART3 |
AnnaBridge | 179:b0033dcd6934 | 316 | case USART_3: |
AnnaBridge | 179:b0033dcd6934 | 317 | IRQvector = USART3_RX_IRQn; |
AnnaBridge | 179:b0033dcd6934 | 318 | break; |
AnnaBridge | 179:b0033dcd6934 | 319 | #endif |
AnnaBridge | 179:b0033dcd6934 | 320 | #ifdef USART4 |
AnnaBridge | 179:b0033dcd6934 | 321 | case USART_4: |
AnnaBridge | 179:b0033dcd6934 | 322 | IRQvector = USART4_RX_IRQn; |
AnnaBridge | 179:b0033dcd6934 | 323 | break; |
AnnaBridge | 179:b0033dcd6934 | 324 | #endif |
AnnaBridge | 179:b0033dcd6934 | 325 | #ifdef USART5 |
AnnaBridge | 179:b0033dcd6934 | 326 | case USART_5: |
AnnaBridge | 179:b0033dcd6934 | 327 | IRQvector = USART5_RX_IRQn; |
AnnaBridge | 179:b0033dcd6934 | 328 | break; |
AnnaBridge | 179:b0033dcd6934 | 329 | #endif |
<> | 144:ef7eb2e8f9f7 | 330 | default: |
<> | 144:ef7eb2e8f9f7 | 331 | error("Undefined SPI peripheral"); |
<> | 144:ef7eb2e8f9f7 | 332 | return; |
<> | 144:ef7eb2e8f9f7 | 333 | } |
<> | 144:ef7eb2e8f9f7 | 334 | |
<> | 144:ef7eb2e8f9f7 | 335 | if (enable == true) { |
<> | 144:ef7eb2e8f9f7 | 336 | NVIC_SetVector(IRQvector, handler); |
<> | 144:ef7eb2e8f9f7 | 337 | USART_IntEnable(obj->spi.spi, USART_IEN_RXDATAV); |
<> | 144:ef7eb2e8f9f7 | 338 | NVIC_EnableIRQ(IRQvector); |
<> | 144:ef7eb2e8f9f7 | 339 | } else { |
<> | 144:ef7eb2e8f9f7 | 340 | NVIC_SetVector(IRQvector, handler); |
<> | 144:ef7eb2e8f9f7 | 341 | USART_IntDisable(obj->spi.spi, USART_IEN_RXDATAV); |
<> | 144:ef7eb2e8f9f7 | 342 | NVIC_DisableIRQ(IRQvector); |
<> | 144:ef7eb2e8f9f7 | 343 | } |
<> | 144:ef7eb2e8f9f7 | 344 | } |
<> | 144:ef7eb2e8f9f7 | 345 | |
<> | 144:ef7eb2e8f9f7 | 346 | void spi_format(spi_t *obj, int bits, int mode, int slave) |
<> | 144:ef7eb2e8f9f7 | 347 | { |
<> | 144:ef7eb2e8f9f7 | 348 | /* Bits: values between 4 and 16 are valid */ |
<> | 144:ef7eb2e8f9f7 | 349 | MBED_ASSERT(bits >= 4 && bits <= 16); |
<> | 144:ef7eb2e8f9f7 | 350 | obj->spi.bits = bits; |
<> | 144:ef7eb2e8f9f7 | 351 | /* 0x01 = usartDatabits4, etc, up to 0x0D = usartDatabits16 */ |
<> | 144:ef7eb2e8f9f7 | 352 | USART_Databits_TypeDef databits = (USART_Databits_TypeDef) (bits - 3); |
<> | 144:ef7eb2e8f9f7 | 353 | |
<> | 144:ef7eb2e8f9f7 | 354 | USART_ClockMode_TypeDef clockMode; |
<> | 144:ef7eb2e8f9f7 | 355 | MBED_ASSERT(mode >= 0 && mode <= 3); |
<> | 144:ef7eb2e8f9f7 | 356 | switch (mode) { |
<> | 144:ef7eb2e8f9f7 | 357 | case 0: |
<> | 144:ef7eb2e8f9f7 | 358 | clockMode = usartClockMode0; |
<> | 144:ef7eb2e8f9f7 | 359 | break; |
<> | 144:ef7eb2e8f9f7 | 360 | case 1: |
<> | 144:ef7eb2e8f9f7 | 361 | clockMode = usartClockMode1; |
<> | 144:ef7eb2e8f9f7 | 362 | break; |
<> | 144:ef7eb2e8f9f7 | 363 | case 2: |
<> | 144:ef7eb2e8f9f7 | 364 | clockMode = usartClockMode2; |
<> | 144:ef7eb2e8f9f7 | 365 | break; |
<> | 144:ef7eb2e8f9f7 | 366 | case 3: |
<> | 144:ef7eb2e8f9f7 | 367 | clockMode = usartClockMode3; |
<> | 144:ef7eb2e8f9f7 | 368 | break; |
<> | 144:ef7eb2e8f9f7 | 369 | default: |
<> | 144:ef7eb2e8f9f7 | 370 | clockMode = usartClockMode0; |
<> | 144:ef7eb2e8f9f7 | 371 | } |
<> | 144:ef7eb2e8f9f7 | 372 | uint32_t iflags = obj->spi.spi->IEN; |
<> | 144:ef7eb2e8f9f7 | 373 | bool enabled = (obj->spi.spi->STATUS & (USART_STATUS_RXENS | USART_STATUS_TXENS)) != 0; |
<> | 144:ef7eb2e8f9f7 | 374 | |
<> | 144:ef7eb2e8f9f7 | 375 | usart_init(obj, 100000, databits, (slave ? false : true), clockMode); |
<> | 144:ef7eb2e8f9f7 | 376 | |
<> | 144:ef7eb2e8f9f7 | 377 | //restore state |
<> | 144:ef7eb2e8f9f7 | 378 | #ifdef _USART_ROUTEPEN_RESETVALUE |
Anna Bridge |
163:74e0ce7f98e8 | 379 | obj->spi.spi->ROUTEPEN = obj->spi.route; |
Anna Bridge |
163:74e0ce7f98e8 | 380 | obj->spi.spi->ROUTELOC0 = obj->spi.location; |
<> | 144:ef7eb2e8f9f7 | 381 | #else |
Anna Bridge |
163:74e0ce7f98e8 | 382 | obj->spi.spi->ROUTE = obj->spi.route; |
<> | 144:ef7eb2e8f9f7 | 383 | #endif |
<> | 144:ef7eb2e8f9f7 | 384 | obj->spi.spi->IEN = iflags; |
<> | 144:ef7eb2e8f9f7 | 385 | |
<> | 144:ef7eb2e8f9f7 | 386 | if(enabled) spi_enable(obj, enabled); |
<> | 144:ef7eb2e8f9f7 | 387 | } |
<> | 144:ef7eb2e8f9f7 | 388 | |
<> | 144:ef7eb2e8f9f7 | 389 | void spi_frequency(spi_t *obj, int hz) |
<> | 144:ef7eb2e8f9f7 | 390 | { |
<> | 144:ef7eb2e8f9f7 | 391 | USART_BaudrateSyncSet(obj->spi.spi, REFERENCE_FREQUENCY, hz); |
<> | 144:ef7eb2e8f9f7 | 392 | } |
<> | 144:ef7eb2e8f9f7 | 393 | |
<> | 144:ef7eb2e8f9f7 | 394 | /* Read/Write */ |
<> | 144:ef7eb2e8f9f7 | 395 | |
<> | 144:ef7eb2e8f9f7 | 396 | void spi_write(spi_t *obj, int value) |
<> | 144:ef7eb2e8f9f7 | 397 | { |
<> | 144:ef7eb2e8f9f7 | 398 | if (obj->spi.bits <= 8) { |
<> | 144:ef7eb2e8f9f7 | 399 | USART_Tx(obj->spi.spi, (uint8_t) value); |
<> | 144:ef7eb2e8f9f7 | 400 | } else if (obj->spi.bits == 9) { |
<> | 144:ef7eb2e8f9f7 | 401 | USART_TxExt(obj->spi.spi, (uint16_t) value & 0x1FF); |
<> | 144:ef7eb2e8f9f7 | 402 | } else { |
<> | 144:ef7eb2e8f9f7 | 403 | USART_TxDouble(obj->spi.spi, (uint16_t) value); |
<> | 144:ef7eb2e8f9f7 | 404 | } |
<> | 144:ef7eb2e8f9f7 | 405 | } |
<> | 144:ef7eb2e8f9f7 | 406 | |
<> | 144:ef7eb2e8f9f7 | 407 | int spi_read(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 408 | { |
<> | 144:ef7eb2e8f9f7 | 409 | if (obj->spi.bits <= 8) { |
<> | 144:ef7eb2e8f9f7 | 410 | return (int) obj->spi.spi->RXDATA; |
<> | 144:ef7eb2e8f9f7 | 411 | } else if (obj->spi.bits == 9) { |
<> | 144:ef7eb2e8f9f7 | 412 | return (int) obj->spi.spi->RXDATAX & 0x1FF; |
<> | 144:ef7eb2e8f9f7 | 413 | } else { |
<> | 144:ef7eb2e8f9f7 | 414 | return (int) obj->spi.spi->RXDOUBLE; |
<> | 144:ef7eb2e8f9f7 | 415 | } |
<> | 144:ef7eb2e8f9f7 | 416 | } |
<> | 144:ef7eb2e8f9f7 | 417 | |
<> | 144:ef7eb2e8f9f7 | 418 | int spi_read_asynch(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 419 | { |
<> | 144:ef7eb2e8f9f7 | 420 | return spi_read(obj); |
<> | 144:ef7eb2e8f9f7 | 421 | } |
<> | 144:ef7eb2e8f9f7 | 422 | |
<> | 144:ef7eb2e8f9f7 | 423 | int spi_master_write(spi_t *obj, int value) |
<> | 144:ef7eb2e8f9f7 | 424 | { |
<> | 144:ef7eb2e8f9f7 | 425 | spi_write(obj, value); |
<> | 144:ef7eb2e8f9f7 | 426 | |
<> | 144:ef7eb2e8f9f7 | 427 | /* Wait for transmission of last byte */ |
<> | 144:ef7eb2e8f9f7 | 428 | while (!(obj->spi.spi->STATUS & USART_STATUS_TXC)) { |
<> | 144:ef7eb2e8f9f7 | 429 | } |
<> | 144:ef7eb2e8f9f7 | 430 | |
<> | 144:ef7eb2e8f9f7 | 431 | return spi_read(obj); |
<> | 144:ef7eb2e8f9f7 | 432 | } |
<> | 144:ef7eb2e8f9f7 | 433 | |
Kojto | 170:19eb464bc2be | 434 | int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, |
Kojto | 170:19eb464bc2be | 435 | char *rx_buffer, int rx_length, char write_fill) { |
AnnaBridge | 167:e84263d55307 | 436 | int total = (tx_length > rx_length) ? tx_length : rx_length; |
AnnaBridge | 167:e84263d55307 | 437 | |
AnnaBridge | 167:e84263d55307 | 438 | for (int i = 0; i < total; i++) { |
Kojto | 170:19eb464bc2be | 439 | char out = (i < tx_length) ? tx_buffer[i] : write_fill; |
AnnaBridge | 167:e84263d55307 | 440 | char in = spi_master_write(obj, out); |
AnnaBridge | 167:e84263d55307 | 441 | if (i < rx_length) { |
AnnaBridge | 167:e84263d55307 | 442 | rx_buffer[i] = in; |
AnnaBridge | 167:e84263d55307 | 443 | } |
AnnaBridge | 167:e84263d55307 | 444 | } |
AnnaBridge | 167:e84263d55307 | 445 | |
AnnaBridge | 167:e84263d55307 | 446 | return total; |
AnnaBridge | 167:e84263d55307 | 447 | } |
AnnaBridge | 167:e84263d55307 | 448 | |
<> | 144:ef7eb2e8f9f7 | 449 | inline uint8_t spi_master_tx_ready(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 450 | { |
<> | 144:ef7eb2e8f9f7 | 451 | return (obj->spi.spi->STATUS & USART_STATUS_TXBL) ? true : false; |
<> | 144:ef7eb2e8f9f7 | 452 | } |
<> | 144:ef7eb2e8f9f7 | 453 | |
<> | 144:ef7eb2e8f9f7 | 454 | uint8_t spi_master_rx_ready(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 455 | { |
<> | 144:ef7eb2e8f9f7 | 456 | return (obj->spi.spi->STATUS & USART_STATUS_RXDATAV) ? true : false; |
<> | 144:ef7eb2e8f9f7 | 457 | } |
<> | 144:ef7eb2e8f9f7 | 458 | |
<> | 144:ef7eb2e8f9f7 | 459 | uint8_t spi_master_tx_int_flag(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 460 | { |
<> | 144:ef7eb2e8f9f7 | 461 | return (obj->spi.spi->IF & USART_IF_TXBL) ? true : false; |
<> | 144:ef7eb2e8f9f7 | 462 | } |
<> | 144:ef7eb2e8f9f7 | 463 | |
<> | 144:ef7eb2e8f9f7 | 464 | uint8_t spi_master_rx_int_flag(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 465 | { |
<> | 144:ef7eb2e8f9f7 | 466 | return (obj->spi.spi->IF & (USART_IF_RXDATAV | USART_IF_RXFULL)) ? true : false; |
<> | 144:ef7eb2e8f9f7 | 467 | } |
<> | 144:ef7eb2e8f9f7 | 468 | |
<> | 144:ef7eb2e8f9f7 | 469 | void spi_master_read_asynch_complete(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 470 | { |
<> | 144:ef7eb2e8f9f7 | 471 | obj->spi.spi->IFC = USART_IFC_RXFULL; // in case it got full |
<> | 144:ef7eb2e8f9f7 | 472 | } |
<> | 144:ef7eb2e8f9f7 | 473 | |
<> | 144:ef7eb2e8f9f7 | 474 | void spi_master_write_asynch_complete(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 475 | { |
<> | 144:ef7eb2e8f9f7 | 476 | obj->spi.spi->IFC = USART_IFC_TXC; |
<> | 144:ef7eb2e8f9f7 | 477 | } |
<> | 144:ef7eb2e8f9f7 | 478 | |
<> | 144:ef7eb2e8f9f7 | 479 | void spi_irq_handler(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 480 | { |
<> | 144:ef7eb2e8f9f7 | 481 | spi_read(obj); //TODO_LP store data to the object? |
<> | 144:ef7eb2e8f9f7 | 482 | } |
<> | 144:ef7eb2e8f9f7 | 483 | |
<> | 144:ef7eb2e8f9f7 | 484 | uint8_t spi_active(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 485 | { |
<> | 144:ef7eb2e8f9f7 | 486 | switch(obj->spi.dmaOptionsTX.dmaUsageState) { |
<> | 144:ef7eb2e8f9f7 | 487 | case DMA_USAGE_TEMPORARY_ALLOCATED: |
<> | 144:ef7eb2e8f9f7 | 488 | return true; |
<> | 144:ef7eb2e8f9f7 | 489 | case DMA_USAGE_ALLOCATED: |
<> | 144:ef7eb2e8f9f7 | 490 | /* Check whether the allocated DMA channel is active */ |
<> | 144:ef7eb2e8f9f7 | 491 | #ifdef LDMA_PRESENT |
<> | 144:ef7eb2e8f9f7 | 492 | return(LDMAx_ChannelEnabled(obj->spi.dmaOptionsTX.dmaChannel) || LDMAx_ChannelEnabled(obj->spi.dmaOptionsRX.dmaChannel)); |
<> | 144:ef7eb2e8f9f7 | 493 | #else |
<> | 144:ef7eb2e8f9f7 | 494 | return(DMA_ChannelEnabled(obj->spi.dmaOptionsTX.dmaChannel) || DMA_ChannelEnabled(obj->spi.dmaOptionsRX.dmaChannel)); |
<> | 144:ef7eb2e8f9f7 | 495 | #endif |
<> | 144:ef7eb2e8f9f7 | 496 | default: |
<> | 144:ef7eb2e8f9f7 | 497 | /* Check whether interrupt for spi is enabled */ |
<> | 144:ef7eb2e8f9f7 | 498 | return (obj->spi.spi->IEN & (USART_IEN_RXDATAV | USART_IEN_TXBL)) ? true : false; |
<> | 144:ef7eb2e8f9f7 | 499 | } |
<> | 144:ef7eb2e8f9f7 | 500 | } |
<> | 144:ef7eb2e8f9f7 | 501 | |
<> | 144:ef7eb2e8f9f7 | 502 | void spi_buffer_set(spi_t *obj, const void *tx, uint32_t tx_length, void *rx, uint32_t rx_length, uint8_t bit_width) |
<> | 144:ef7eb2e8f9f7 | 503 | { |
<> | 144:ef7eb2e8f9f7 | 504 | uint32_t i; |
<> | 144:ef7eb2e8f9f7 | 505 | uint16_t *tx_ptr = (uint16_t *) tx; |
<> | 144:ef7eb2e8f9f7 | 506 | |
<> | 144:ef7eb2e8f9f7 | 507 | obj->tx_buff.buffer = (void *)tx; |
<> | 144:ef7eb2e8f9f7 | 508 | obj->rx_buff.buffer = rx; |
<> | 144:ef7eb2e8f9f7 | 509 | obj->tx_buff.length = tx_length; |
<> | 144:ef7eb2e8f9f7 | 510 | obj->rx_buff.length = rx_length; |
<> | 144:ef7eb2e8f9f7 | 511 | obj->tx_buff.pos = 0; |
<> | 144:ef7eb2e8f9f7 | 512 | obj->rx_buff.pos = 0; |
<> | 144:ef7eb2e8f9f7 | 513 | obj->tx_buff.width = bit_width; |
<> | 144:ef7eb2e8f9f7 | 514 | obj->rx_buff.width = bit_width; |
<> | 144:ef7eb2e8f9f7 | 515 | |
<> | 144:ef7eb2e8f9f7 | 516 | if((obj->spi.bits == 9) && (tx != 0)) { |
<> | 144:ef7eb2e8f9f7 | 517 | // Make sure we don't have inadvertent non-zero bits outside 9-bit frames which could trigger unwanted operation |
<> | 144:ef7eb2e8f9f7 | 518 | for(i = 0; i < (tx_length / 2); i++) { |
<> | 144:ef7eb2e8f9f7 | 519 | tx_ptr[i] &= 0x1FF; |
<> | 144:ef7eb2e8f9f7 | 520 | } |
<> | 144:ef7eb2e8f9f7 | 521 | } |
<> | 144:ef7eb2e8f9f7 | 522 | } |
<> | 144:ef7eb2e8f9f7 | 523 | |
<> | 144:ef7eb2e8f9f7 | 524 | static void spi_buffer_tx_write(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 525 | { |
<> | 144:ef7eb2e8f9f7 | 526 | uint32_t data = 0; |
<> | 144:ef7eb2e8f9f7 | 527 | |
<> | 144:ef7eb2e8f9f7 | 528 | // Interpret buffer according to declared width |
<> | 144:ef7eb2e8f9f7 | 529 | if (!obj->tx_buff.buffer) { |
<> | 144:ef7eb2e8f9f7 | 530 | data = SPI_FILL_WORD; |
<> | 144:ef7eb2e8f9f7 | 531 | } else if (obj->tx_buff.width == 32) { |
<> | 144:ef7eb2e8f9f7 | 532 | uint32_t * tx = (uint32_t *)obj->tx_buff.buffer; |
<> | 144:ef7eb2e8f9f7 | 533 | data = tx[obj->tx_buff.pos]; |
<> | 144:ef7eb2e8f9f7 | 534 | } else if (obj->tx_buff.width == 16) { |
<> | 144:ef7eb2e8f9f7 | 535 | uint16_t * tx = (uint16_t *)obj->tx_buff.buffer; |
<> | 144:ef7eb2e8f9f7 | 536 | data = tx[obj->tx_buff.pos]; |
<> | 144:ef7eb2e8f9f7 | 537 | } else { |
<> | 144:ef7eb2e8f9f7 | 538 | uint8_t * tx = (uint8_t *)obj->tx_buff.buffer; |
<> | 144:ef7eb2e8f9f7 | 539 | data = tx[obj->tx_buff.pos]; |
<> | 144:ef7eb2e8f9f7 | 540 | } |
<> | 144:ef7eb2e8f9f7 | 541 | obj->tx_buff.pos++; |
<> | 144:ef7eb2e8f9f7 | 542 | |
<> | 144:ef7eb2e8f9f7 | 543 | // Send buffer |
<> | 144:ef7eb2e8f9f7 | 544 | if (obj->spi.bits > 9) { |
<> | 144:ef7eb2e8f9f7 | 545 | obj->spi.spi->TXDOUBLE = data; |
<> | 144:ef7eb2e8f9f7 | 546 | } else if (obj->spi.bits == 9) { |
<> | 144:ef7eb2e8f9f7 | 547 | obj->spi.spi->TXDATAX = data; |
<> | 144:ef7eb2e8f9f7 | 548 | } else { |
<> | 144:ef7eb2e8f9f7 | 549 | obj->spi.spi->TXDATA = data; |
<> | 144:ef7eb2e8f9f7 | 550 | } |
<> | 144:ef7eb2e8f9f7 | 551 | } |
<> | 144:ef7eb2e8f9f7 | 552 | |
<> | 144:ef7eb2e8f9f7 | 553 | static void spi_buffer_rx_read(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 554 | { |
<> | 144:ef7eb2e8f9f7 | 555 | uint32_t data; |
<> | 144:ef7eb2e8f9f7 | 556 | |
<> | 144:ef7eb2e8f9f7 | 557 | if (obj->spi.spi->STATUS & USART_STATUS_RXDATAV) { |
<> | 144:ef7eb2e8f9f7 | 558 | // Read from the FIFO |
<> | 144:ef7eb2e8f9f7 | 559 | if (obj->spi.bits > 9) { |
<> | 144:ef7eb2e8f9f7 | 560 | data = obj->spi.spi->RXDOUBLE; |
<> | 144:ef7eb2e8f9f7 | 561 | } else if (obj->spi.bits == 9) { |
<> | 144:ef7eb2e8f9f7 | 562 | data = obj->spi.spi->RXDATAX; |
<> | 144:ef7eb2e8f9f7 | 563 | } else { |
<> | 144:ef7eb2e8f9f7 | 564 | data = obj->spi.spi->RXDATA; |
<> | 144:ef7eb2e8f9f7 | 565 | } |
<> | 144:ef7eb2e8f9f7 | 566 | |
<> | 144:ef7eb2e8f9f7 | 567 | // If there is room in the buffer, store the data |
<> | 144:ef7eb2e8f9f7 | 568 | if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) { |
<> | 144:ef7eb2e8f9f7 | 569 | if (obj->rx_buff.width == 32) { |
<> | 144:ef7eb2e8f9f7 | 570 | uint32_t * rx = (uint32_t *)(obj->rx_buff.buffer); |
<> | 144:ef7eb2e8f9f7 | 571 | rx[obj->rx_buff.pos] = data; |
<> | 144:ef7eb2e8f9f7 | 572 | } else if (obj->rx_buff.width == 16) { |
<> | 144:ef7eb2e8f9f7 | 573 | uint16_t * rx = (uint16_t *)(obj->rx_buff.buffer); |
<> | 144:ef7eb2e8f9f7 | 574 | rx[obj->rx_buff.pos] = data; |
<> | 144:ef7eb2e8f9f7 | 575 | } else { |
<> | 144:ef7eb2e8f9f7 | 576 | uint8_t * rx = (uint8_t *)(obj->rx_buff.buffer); |
<> | 144:ef7eb2e8f9f7 | 577 | rx[obj->rx_buff.pos] = data; |
<> | 144:ef7eb2e8f9f7 | 578 | } |
<> | 144:ef7eb2e8f9f7 | 579 | obj->rx_buff.pos++; |
<> | 144:ef7eb2e8f9f7 | 580 | } |
<> | 144:ef7eb2e8f9f7 | 581 | } |
<> | 144:ef7eb2e8f9f7 | 582 | } |
<> | 144:ef7eb2e8f9f7 | 583 | |
<> | 144:ef7eb2e8f9f7 | 584 | int spi_master_write_asynch(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 585 | { |
<> | 144:ef7eb2e8f9f7 | 586 | int ndata = 0; |
<> | 144:ef7eb2e8f9f7 | 587 | while ((obj->tx_buff.pos < obj->tx_buff.length) && (obj->spi.spi->STATUS & USART_STATUS_TXBL)) { |
<> | 144:ef7eb2e8f9f7 | 588 | spi_buffer_tx_write(obj); |
<> | 144:ef7eb2e8f9f7 | 589 | ndata++; |
<> | 144:ef7eb2e8f9f7 | 590 | } |
<> | 144:ef7eb2e8f9f7 | 591 | return ndata; |
<> | 144:ef7eb2e8f9f7 | 592 | } |
<> | 144:ef7eb2e8f9f7 | 593 | |
<> | 144:ef7eb2e8f9f7 | 594 | int spi_master_read_asynch(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 595 | { |
<> | 144:ef7eb2e8f9f7 | 596 | int ndata = 0; |
<> | 144:ef7eb2e8f9f7 | 597 | while ((obj->rx_buff.pos < obj->rx_buff.length) && (obj->spi.spi->STATUS & (USART_STATUS_RXDATAV | USART_STATUS_RXFULL))) { |
<> | 144:ef7eb2e8f9f7 | 598 | spi_buffer_rx_read(obj); |
<> | 144:ef7eb2e8f9f7 | 599 | ndata++; |
<> | 144:ef7eb2e8f9f7 | 600 | } |
<> | 144:ef7eb2e8f9f7 | 601 | // all sent but still more to receive? need to align tx buffer |
<> | 144:ef7eb2e8f9f7 | 602 | if ((obj->tx_buff.pos >= obj->tx_buff.length) && (obj->rx_buff.pos < obj->rx_buff.length)) { |
<> | 144:ef7eb2e8f9f7 | 603 | obj->tx_buff.buffer = (void *)0; |
<> | 144:ef7eb2e8f9f7 | 604 | obj->tx_buff.length = obj->rx_buff.length; |
<> | 144:ef7eb2e8f9f7 | 605 | } |
<> | 144:ef7eb2e8f9f7 | 606 | |
<> | 144:ef7eb2e8f9f7 | 607 | return ndata; |
<> | 144:ef7eb2e8f9f7 | 608 | } |
<> | 144:ef7eb2e8f9f7 | 609 | |
<> | 144:ef7eb2e8f9f7 | 610 | uint8_t spi_buffer_rx_empty(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 611 | { |
<> | 144:ef7eb2e8f9f7 | 612 | return (obj->rx_buff.pos >= obj->rx_buff.length ? true : false ); |
<> | 144:ef7eb2e8f9f7 | 613 | } |
<> | 144:ef7eb2e8f9f7 | 614 | |
<> | 144:ef7eb2e8f9f7 | 615 | uint8_t spi_buffer_tx_empty(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 616 | { |
<> | 144:ef7eb2e8f9f7 | 617 | return (obj->tx_buff.pos >= obj->tx_buff.length ? true : false ); |
<> | 144:ef7eb2e8f9f7 | 618 | } |
<> | 144:ef7eb2e8f9f7 | 619 | |
<> | 144:ef7eb2e8f9f7 | 620 | //TODO_LP implement slave |
<> | 144:ef7eb2e8f9f7 | 621 | |
<> | 144:ef7eb2e8f9f7 | 622 | int spi_slave_receive(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 623 | { |
<> | 144:ef7eb2e8f9f7 | 624 | if (obj->spi.bits <= 9) { |
<> | 144:ef7eb2e8f9f7 | 625 | return (obj->spi.spi->STATUS & USART_STATUS_RXDATAV) ? 1 : 0; |
<> | 144:ef7eb2e8f9f7 | 626 | } else { |
<> | 144:ef7eb2e8f9f7 | 627 | return (obj->spi.spi->STATUS & USART_STATUS_RXFULL) ? 1 : 0; |
<> | 144:ef7eb2e8f9f7 | 628 | } |
<> | 144:ef7eb2e8f9f7 | 629 | } |
<> | 144:ef7eb2e8f9f7 | 630 | |
<> | 144:ef7eb2e8f9f7 | 631 | int spi_slave_read(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 632 | { |
<> | 144:ef7eb2e8f9f7 | 633 | return spi_read(obj); |
<> | 144:ef7eb2e8f9f7 | 634 | } |
<> | 144:ef7eb2e8f9f7 | 635 | |
<> | 144:ef7eb2e8f9f7 | 636 | void spi_slave_write(spi_t *obj, int value) |
<> | 144:ef7eb2e8f9f7 | 637 | { |
<> | 144:ef7eb2e8f9f7 | 638 | spi_write(obj, value); |
<> | 144:ef7eb2e8f9f7 | 639 | } |
<> | 144:ef7eb2e8f9f7 | 640 | |
<> | 144:ef7eb2e8f9f7 | 641 | uint32_t spi_event_check(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 642 | { |
<> | 144:ef7eb2e8f9f7 | 643 | uint32_t requestedEvent = obj->spi.event; |
<> | 144:ef7eb2e8f9f7 | 644 | uint32_t event = 0; |
<> | 144:ef7eb2e8f9f7 | 645 | uint8_t quit = spi_buffer_rx_empty(obj) & spi_buffer_tx_empty(obj); |
<> | 144:ef7eb2e8f9f7 | 646 | if (((requestedEvent & SPI_EVENT_COMPLETE) != 0) && (quit == true)) { |
<> | 144:ef7eb2e8f9f7 | 647 | event |= SPI_EVENT_COMPLETE; |
<> | 144:ef7eb2e8f9f7 | 648 | } |
<> | 144:ef7eb2e8f9f7 | 649 | |
<> | 144:ef7eb2e8f9f7 | 650 | if(quit == true) { |
<> | 144:ef7eb2e8f9f7 | 651 | event |= SPI_EVENT_INTERNAL_TRANSFER_COMPLETE; |
<> | 144:ef7eb2e8f9f7 | 652 | } |
<> | 144:ef7eb2e8f9f7 | 653 | |
<> | 144:ef7eb2e8f9f7 | 654 | return event; |
<> | 144:ef7eb2e8f9f7 | 655 | } |
<> | 144:ef7eb2e8f9f7 | 656 | /****************************************** |
<> | 144:ef7eb2e8f9f7 | 657 | * void transferComplete(uint channel, bool primary, void* user) |
<> | 144:ef7eb2e8f9f7 | 658 | * |
<> | 144:ef7eb2e8f9f7 | 659 | * Callback function which gets called upon DMA transfer completion |
<> | 144:ef7eb2e8f9f7 | 660 | * the user-defined pointer is pointing to the CPP-land thunk |
<> | 144:ef7eb2e8f9f7 | 661 | ******************************************/ |
<> | 144:ef7eb2e8f9f7 | 662 | void transferComplete(unsigned int channel, bool primary, void *user) |
<> | 144:ef7eb2e8f9f7 | 663 | { |
<> | 144:ef7eb2e8f9f7 | 664 | (void) channel; |
<> | 144:ef7eb2e8f9f7 | 665 | (void) primary; |
<> | 144:ef7eb2e8f9f7 | 666 | |
<> | 144:ef7eb2e8f9f7 | 667 | /* User pointer should be a thunk to CPP land */ |
<> | 144:ef7eb2e8f9f7 | 668 | if (user != NULL) { |
<> | 144:ef7eb2e8f9f7 | 669 | ((DMACallback)user)(); |
<> | 144:ef7eb2e8f9f7 | 670 | } |
<> | 144:ef7eb2e8f9f7 | 671 | } |
<> | 144:ef7eb2e8f9f7 | 672 | |
<> | 144:ef7eb2e8f9f7 | 673 | /****************************************** |
<> | 144:ef7eb2e8f9f7 | 674 | * bool spi_allocate_dma(spi_t *obj); |
<> | 144:ef7eb2e8f9f7 | 675 | * (helper function for spi_enable_dma) |
<> | 144:ef7eb2e8f9f7 | 676 | * |
<> | 144:ef7eb2e8f9f7 | 677 | * This function will request two DMA channels from the DMA API if needed |
<> | 144:ef7eb2e8f9f7 | 678 | * by the hint provided. They will be allocated to the SPI object pointed to. |
<> | 144:ef7eb2e8f9f7 | 679 | * |
<> | 144:ef7eb2e8f9f7 | 680 | * return value: whether the channels were acquired successfully (true) or not. |
<> | 144:ef7eb2e8f9f7 | 681 | ******************************************/ |
<> | 144:ef7eb2e8f9f7 | 682 | bool spi_allocate_dma(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 683 | { |
<> | 144:ef7eb2e8f9f7 | 684 | int dmaChannelIn, dmaChannelOut; |
<> | 144:ef7eb2e8f9f7 | 685 | dmaChannelIn = dma_channel_allocate(DMA_CAP_NONE); |
<> | 144:ef7eb2e8f9f7 | 686 | if (dmaChannelIn == DMA_ERROR_OUT_OF_CHANNELS) { |
<> | 144:ef7eb2e8f9f7 | 687 | return false; |
<> | 144:ef7eb2e8f9f7 | 688 | } |
<> | 144:ef7eb2e8f9f7 | 689 | dmaChannelOut = dma_channel_allocate(DMA_CAP_NONE); |
<> | 144:ef7eb2e8f9f7 | 690 | if (dmaChannelOut == DMA_ERROR_OUT_OF_CHANNELS) { |
<> | 144:ef7eb2e8f9f7 | 691 | dma_channel_free(dmaChannelIn); |
<> | 144:ef7eb2e8f9f7 | 692 | return false; |
<> | 144:ef7eb2e8f9f7 | 693 | } |
<> | 144:ef7eb2e8f9f7 | 694 | |
<> | 144:ef7eb2e8f9f7 | 695 | obj->spi.dmaOptionsTX.dmaChannel = dmaChannelOut; |
<> | 144:ef7eb2e8f9f7 | 696 | obj->spi.dmaOptionsRX.dmaChannel = dmaChannelIn; |
<> | 144:ef7eb2e8f9f7 | 697 | return true; |
<> | 144:ef7eb2e8f9f7 | 698 | } |
<> | 144:ef7eb2e8f9f7 | 699 | |
<> | 144:ef7eb2e8f9f7 | 700 | /****************************************** |
<> | 144:ef7eb2e8f9f7 | 701 | * void spi_enable_dma(spi_t *obj, DMAUsage state) |
<> | 144:ef7eb2e8f9f7 | 702 | * |
<> | 144:ef7eb2e8f9f7 | 703 | * This function tries to allocate DMA as indicated by the hint (state). |
<> | 144:ef7eb2e8f9f7 | 704 | * There are three possibilities: |
<> | 144:ef7eb2e8f9f7 | 705 | * * state = NEVER: |
<> | 144:ef7eb2e8f9f7 | 706 | * if there were channels allocated by state = ALWAYS, they will be released |
<> | 144:ef7eb2e8f9f7 | 707 | * * state = OPPORTUNITIC: |
<> | 144:ef7eb2e8f9f7 | 708 | * if there are channels available, they will get used, but freed upon transfer completion |
<> | 144:ef7eb2e8f9f7 | 709 | * * state = ALWAYS |
<> | 144:ef7eb2e8f9f7 | 710 | * if there are channels available, they will get allocated and not be freed until state changes |
<> | 144:ef7eb2e8f9f7 | 711 | ******************************************/ |
<> | 144:ef7eb2e8f9f7 | 712 | void spi_enable_dma(spi_t *obj, DMAUsage state) |
<> | 144:ef7eb2e8f9f7 | 713 | { |
<> | 144:ef7eb2e8f9f7 | 714 | if (state == DMA_USAGE_ALWAYS && obj->spi.dmaOptionsTX.dmaUsageState != DMA_USAGE_ALLOCATED) { |
<> | 144:ef7eb2e8f9f7 | 715 | /* Try to allocate channels */ |
<> | 144:ef7eb2e8f9f7 | 716 | if (spi_allocate_dma(obj)) { |
<> | 144:ef7eb2e8f9f7 | 717 | obj->spi.dmaOptionsTX.dmaUsageState = DMA_USAGE_ALLOCATED; |
<> | 144:ef7eb2e8f9f7 | 718 | } else { |
<> | 144:ef7eb2e8f9f7 | 719 | obj->spi.dmaOptionsTX.dmaUsageState = state; |
<> | 144:ef7eb2e8f9f7 | 720 | } |
<> | 144:ef7eb2e8f9f7 | 721 | } else if (state == DMA_USAGE_OPPORTUNISTIC) { |
<> | 144:ef7eb2e8f9f7 | 722 | if (obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_ALLOCATED) { |
<> | 144:ef7eb2e8f9f7 | 723 | /* Channels have already been allocated previously by an ALWAYS state, so after this transfer, we will release them */ |
<> | 144:ef7eb2e8f9f7 | 724 | obj->spi.dmaOptionsTX.dmaUsageState = DMA_USAGE_TEMPORARY_ALLOCATED; |
<> | 144:ef7eb2e8f9f7 | 725 | } else { |
<> | 144:ef7eb2e8f9f7 | 726 | /* Try to allocate channels */ |
<> | 144:ef7eb2e8f9f7 | 727 | if (spi_allocate_dma(obj)) { |
<> | 144:ef7eb2e8f9f7 | 728 | obj->spi.dmaOptionsTX.dmaUsageState = DMA_USAGE_TEMPORARY_ALLOCATED; |
<> | 144:ef7eb2e8f9f7 | 729 | } else { |
<> | 144:ef7eb2e8f9f7 | 730 | obj->spi.dmaOptionsTX.dmaUsageState = state; |
<> | 144:ef7eb2e8f9f7 | 731 | } |
<> | 144:ef7eb2e8f9f7 | 732 | } |
<> | 144:ef7eb2e8f9f7 | 733 | } else if (state == DMA_USAGE_NEVER) { |
<> | 144:ef7eb2e8f9f7 | 734 | /* If channels are allocated, get rid of them */ |
<> | 144:ef7eb2e8f9f7 | 735 | if (obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_ALLOCATED) { |
<> | 144:ef7eb2e8f9f7 | 736 | dma_channel_free(obj->spi.dmaOptionsTX.dmaChannel); |
<> | 144:ef7eb2e8f9f7 | 737 | dma_channel_free(obj->spi.dmaOptionsRX.dmaChannel); |
<> | 144:ef7eb2e8f9f7 | 738 | } |
<> | 144:ef7eb2e8f9f7 | 739 | obj->spi.dmaOptionsTX.dmaUsageState = DMA_USAGE_NEVER; |
<> | 144:ef7eb2e8f9f7 | 740 | } |
<> | 144:ef7eb2e8f9f7 | 741 | } |
<> | 144:ef7eb2e8f9f7 | 742 | |
<> | 144:ef7eb2e8f9f7 | 743 | #ifdef LDMA_PRESENT |
<> | 144:ef7eb2e8f9f7 | 744 | /************************************************************************************ |
<> | 144:ef7eb2e8f9f7 | 745 | * DMA helper functions * |
<> | 144:ef7eb2e8f9f7 | 746 | ************************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 747 | /****************************************** |
<> | 144:ef7eb2e8f9f7 | 748 | * static void serial_dmaTransferComplete(uint channel, bool primary, void* user) |
<> | 144:ef7eb2e8f9f7 | 749 | * |
<> | 144:ef7eb2e8f9f7 | 750 | * Callback function which gets called upon DMA transfer completion |
<> | 144:ef7eb2e8f9f7 | 751 | * the user-defined pointer is pointing to the CPP-land thunk |
<> | 144:ef7eb2e8f9f7 | 752 | ******************************************/ |
<> | 144:ef7eb2e8f9f7 | 753 | static void serial_dmaTransferComplete(unsigned int channel, bool primary, void *user) |
<> | 144:ef7eb2e8f9f7 | 754 | { |
<> | 144:ef7eb2e8f9f7 | 755 | |
<> | 144:ef7eb2e8f9f7 | 756 | /* User pointer should be a thunk to CPP land */ |
<> | 144:ef7eb2e8f9f7 | 757 | if (user != NULL) { |
<> | 144:ef7eb2e8f9f7 | 758 | ((DMACallback)user)(); |
<> | 144:ef7eb2e8f9f7 | 759 | } |
<> | 144:ef7eb2e8f9f7 | 760 | } |
<> | 144:ef7eb2e8f9f7 | 761 | static void spi_master_dma_channel_setup(spi_t *obj, void* callback) |
<> | 144:ef7eb2e8f9f7 | 762 | { |
<> | 144:ef7eb2e8f9f7 | 763 | obj->spi.dmaOptionsRX.dmaCallback.userPtr = callback; |
<> | 144:ef7eb2e8f9f7 | 764 | } |
<> | 144:ef7eb2e8f9f7 | 765 | #else |
<> | 144:ef7eb2e8f9f7 | 766 | /****************************************** |
<> | 144:ef7eb2e8f9f7 | 767 | * void spi_master_dma_channel_setup(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 768 | * |
<> | 144:ef7eb2e8f9f7 | 769 | * This function will setup the DMA configuration for SPI transfers |
<> | 144:ef7eb2e8f9f7 | 770 | * |
<> | 144:ef7eb2e8f9f7 | 771 | * The channel numbers are fetched from the SPI instance, so this function |
<> | 144:ef7eb2e8f9f7 | 772 | * should only be called when those channels have actually been allocated. |
<> | 144:ef7eb2e8f9f7 | 773 | ******************************************/ |
<> | 144:ef7eb2e8f9f7 | 774 | static void spi_master_dma_channel_setup(spi_t *obj, void* callback) |
<> | 144:ef7eb2e8f9f7 | 775 | { |
<> | 144:ef7eb2e8f9f7 | 776 | DMA_CfgChannel_TypeDef rxChnlCfg; |
<> | 144:ef7eb2e8f9f7 | 777 | DMA_CfgChannel_TypeDef txChnlCfg; |
<> | 144:ef7eb2e8f9f7 | 778 | |
<> | 144:ef7eb2e8f9f7 | 779 | /* Setting up channel for rx. */ |
<> | 144:ef7eb2e8f9f7 | 780 | obj->spi.dmaOptionsRX.dmaCallback.cbFunc = transferComplete; |
<> | 144:ef7eb2e8f9f7 | 781 | obj->spi.dmaOptionsRX.dmaCallback.userPtr = callback; |
<> | 144:ef7eb2e8f9f7 | 782 | |
<> | 144:ef7eb2e8f9f7 | 783 | rxChnlCfg.highPri = false; |
<> | 144:ef7eb2e8f9f7 | 784 | rxChnlCfg.enableInt = true; |
<> | 144:ef7eb2e8f9f7 | 785 | rxChnlCfg.cb = &(obj->spi.dmaOptionsRX.dmaCallback); |
<> | 144:ef7eb2e8f9f7 | 786 | |
<> | 144:ef7eb2e8f9f7 | 787 | /* Setting up channel for tx. */ |
<> | 144:ef7eb2e8f9f7 | 788 | obj->spi.dmaOptionsTX.dmaCallback.cbFunc = transferComplete; |
<> | 144:ef7eb2e8f9f7 | 789 | obj->spi.dmaOptionsTX.dmaCallback.userPtr = callback; |
<> | 144:ef7eb2e8f9f7 | 790 | |
<> | 144:ef7eb2e8f9f7 | 791 | txChnlCfg.highPri = false; |
<> | 144:ef7eb2e8f9f7 | 792 | txChnlCfg.enableInt = true; |
<> | 144:ef7eb2e8f9f7 | 793 | txChnlCfg.cb = &(obj->spi.dmaOptionsTX.dmaCallback); |
<> | 144:ef7eb2e8f9f7 | 794 | |
<> | 144:ef7eb2e8f9f7 | 795 | switch ((int)obj->spi.spi) { |
<> | 144:ef7eb2e8f9f7 | 796 | #ifdef USART0 |
<> | 144:ef7eb2e8f9f7 | 797 | case SPI_0: |
<> | 144:ef7eb2e8f9f7 | 798 | rxChnlCfg.select = DMAREQ_USART0_RXDATAV; |
<> | 144:ef7eb2e8f9f7 | 799 | txChnlCfg.select = DMAREQ_USART0_TXEMPTY; |
<> | 144:ef7eb2e8f9f7 | 800 | break; |
<> | 144:ef7eb2e8f9f7 | 801 | #endif |
<> | 144:ef7eb2e8f9f7 | 802 | #ifdef USART1 |
<> | 144:ef7eb2e8f9f7 | 803 | case SPI_1: |
<> | 144:ef7eb2e8f9f7 | 804 | rxChnlCfg.select = DMAREQ_USART1_RXDATAV; |
<> | 144:ef7eb2e8f9f7 | 805 | txChnlCfg.select = DMAREQ_USART1_TXEMPTY; |
<> | 144:ef7eb2e8f9f7 | 806 | break; |
<> | 144:ef7eb2e8f9f7 | 807 | #endif |
<> | 144:ef7eb2e8f9f7 | 808 | #ifdef USART2 |
<> | 144:ef7eb2e8f9f7 | 809 | case SPI_2: |
<> | 144:ef7eb2e8f9f7 | 810 | rxChnlCfg.select = DMAREQ_USART2_RXDATAV; |
<> | 144:ef7eb2e8f9f7 | 811 | txChnlCfg.select = DMAREQ_USART2_TXEMPTY; |
<> | 144:ef7eb2e8f9f7 | 812 | break; |
<> | 144:ef7eb2e8f9f7 | 813 | #endif |
AnnaBridge | 179:b0033dcd6934 | 814 | #ifdef USART3 |
AnnaBridge | 179:b0033dcd6934 | 815 | case SPI_3: |
AnnaBridge | 179:b0033dcd6934 | 816 | rxChnlCfg.select = DMAREQ_USART3_RXDATAV; |
AnnaBridge | 179:b0033dcd6934 | 817 | txChnlCfg.select = DMAREQ_USART3_TXEMPTY; |
AnnaBridge | 179:b0033dcd6934 | 818 | break; |
AnnaBridge | 179:b0033dcd6934 | 819 | #endif |
AnnaBridge | 179:b0033dcd6934 | 820 | #ifdef USART4 |
AnnaBridge | 179:b0033dcd6934 | 821 | case SPI_4: |
AnnaBridge | 179:b0033dcd6934 | 822 | rxChnlCfg.select = DMAREQ_USART4_RXDATAV; |
AnnaBridge | 179:b0033dcd6934 | 823 | txChnlCfg.select = DMAREQ_USART4_TXEMPTY; |
AnnaBridge | 179:b0033dcd6934 | 824 | break; |
AnnaBridge | 179:b0033dcd6934 | 825 | #endif |
AnnaBridge | 179:b0033dcd6934 | 826 | #ifdef USART5 |
AnnaBridge | 179:b0033dcd6934 | 827 | case SPI_5: |
AnnaBridge | 179:b0033dcd6934 | 828 | rxChnlCfg.select = DMAREQ_USART5_RXDATAV; |
AnnaBridge | 179:b0033dcd6934 | 829 | txChnlCfg.select = DMAREQ_USART5_TXEMPTY; |
AnnaBridge | 179:b0033dcd6934 | 830 | break; |
AnnaBridge | 179:b0033dcd6934 | 831 | #endif |
<> | 144:ef7eb2e8f9f7 | 832 | default: |
<> | 144:ef7eb2e8f9f7 | 833 | error("Spi module not available.. Out of bound access."); |
<> | 144:ef7eb2e8f9f7 | 834 | break; |
<> | 144:ef7eb2e8f9f7 | 835 | } |
<> | 144:ef7eb2e8f9f7 | 836 | DMA_CfgChannel(obj->spi.dmaOptionsRX.dmaChannel, &rxChnlCfg); |
<> | 144:ef7eb2e8f9f7 | 837 | DMA_CfgChannel(obj->spi.dmaOptionsTX.dmaChannel, &txChnlCfg); |
<> | 144:ef7eb2e8f9f7 | 838 | } |
<> | 144:ef7eb2e8f9f7 | 839 | #endif // LDMA_PRESENT |
<> | 144:ef7eb2e8f9f7 | 840 | /****************************************** |
<> | 144:ef7eb2e8f9f7 | 841 | * void spi_activate_dma(spi_t *obj, void* rxdata, void* txdata, int length) |
<> | 144:ef7eb2e8f9f7 | 842 | * |
<> | 144:ef7eb2e8f9f7 | 843 | * This function will start the DMA engine for SPI transfers |
<> | 144:ef7eb2e8f9f7 | 844 | * |
<> | 144:ef7eb2e8f9f7 | 845 | * * rxdata: pointer to RX buffer, if needed. |
<> | 144:ef7eb2e8f9f7 | 846 | * * txdata: pointer to TX buffer, if needed. Else FF's. |
<> | 144:ef7eb2e8f9f7 | 847 | * * tx_length: how many bytes will get sent. |
<> | 144:ef7eb2e8f9f7 | 848 | * * rx_length: how many bytes will get received. If > tx_length, TX will get padded with n lower bits of SPI_FILL_WORD. |
<> | 144:ef7eb2e8f9f7 | 849 | ******************************************/ |
<> | 144:ef7eb2e8f9f7 | 850 | #ifdef LDMA_PRESENT |
<> | 144:ef7eb2e8f9f7 | 851 | static void spi_activate_dma(spi_t *obj, void* rxdata, const void* txdata, int tx_length, int rx_length) |
<> | 144:ef7eb2e8f9f7 | 852 | { |
<> | 144:ef7eb2e8f9f7 | 853 | LDMA_PeripheralSignal_t dma_periph; |
<> | 144:ef7eb2e8f9f7 | 854 | |
<> | 144:ef7eb2e8f9f7 | 855 | if(rxdata) { |
<> | 144:ef7eb2e8f9f7 | 856 | volatile const void *source_addr; |
<> | 144:ef7eb2e8f9f7 | 857 | /* Select RX source address. 9 bit frame length requires to use extended register. |
<> | 144:ef7eb2e8f9f7 | 858 | 10 bit and larger frame requires to use RXDOUBLE register. */ |
<> | 144:ef7eb2e8f9f7 | 859 | switch((int)obj->spi.spi) { |
AnnaBridge | 179:b0033dcd6934 | 860 | #ifdef USART0 |
<> | 144:ef7eb2e8f9f7 | 861 | case USART_0: |
<> | 144:ef7eb2e8f9f7 | 862 | dma_periph = ldmaPeripheralSignal_USART0_RXDATAV; |
<> | 144:ef7eb2e8f9f7 | 863 | break; |
AnnaBridge | 179:b0033dcd6934 | 864 | #endif |
AnnaBridge | 179:b0033dcd6934 | 865 | #ifdef USART1 |
<> | 144:ef7eb2e8f9f7 | 866 | case USART_1: |
<> | 144:ef7eb2e8f9f7 | 867 | dma_periph = ldmaPeripheralSignal_USART1_RXDATAV; |
<> | 144:ef7eb2e8f9f7 | 868 | break; |
AnnaBridge | 179:b0033dcd6934 | 869 | #endif |
AnnaBridge | 179:b0033dcd6934 | 870 | #ifdef USART2 |
AnnaBridge | 179:b0033dcd6934 | 871 | case USART_2: |
AnnaBridge | 179:b0033dcd6934 | 872 | dma_periph = ldmaPeripheralSignal_USART2_RXDATAV; |
AnnaBridge | 179:b0033dcd6934 | 873 | break; |
AnnaBridge | 179:b0033dcd6934 | 874 | #endif |
AnnaBridge | 179:b0033dcd6934 | 875 | #ifdef USART3 |
AnnaBridge | 179:b0033dcd6934 | 876 | case USART_3: |
AnnaBridge | 179:b0033dcd6934 | 877 | dma_periph = ldmaPeripheralSignal_USART3_RXDATAV; |
AnnaBridge | 179:b0033dcd6934 | 878 | break; |
AnnaBridge | 179:b0033dcd6934 | 879 | #endif |
AnnaBridge | 179:b0033dcd6934 | 880 | #ifdef USART4 |
AnnaBridge | 179:b0033dcd6934 | 881 | case USART_4: |
AnnaBridge | 179:b0033dcd6934 | 882 | dma_periph = ldmaPeripheralSignal_USART4_RXDATAV; |
AnnaBridge | 179:b0033dcd6934 | 883 | break; |
AnnaBridge | 179:b0033dcd6934 | 884 | #endif |
AnnaBridge | 179:b0033dcd6934 | 885 | #ifdef USART5 |
AnnaBridge | 179:b0033dcd6934 | 886 | case USART_5: |
AnnaBridge | 179:b0033dcd6934 | 887 | dma_periph = ldmaPeripheralSignal_USART5_RXDATAV; |
AnnaBridge | 179:b0033dcd6934 | 888 | break; |
AnnaBridge | 179:b0033dcd6934 | 889 | #endif |
<> | 144:ef7eb2e8f9f7 | 890 | default: |
<> | 144:ef7eb2e8f9f7 | 891 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 892 | while(1); |
<> | 144:ef7eb2e8f9f7 | 893 | break; |
<> | 144:ef7eb2e8f9f7 | 894 | } |
<> | 144:ef7eb2e8f9f7 | 895 | |
<> | 144:ef7eb2e8f9f7 | 896 | if (obj->spi.bits <= 8) { |
<> | 144:ef7eb2e8f9f7 | 897 | source_addr = &obj->spi.spi->RXDATA; |
<> | 144:ef7eb2e8f9f7 | 898 | } else if (obj->spi.bits == 9) { |
<> | 144:ef7eb2e8f9f7 | 899 | source_addr = &obj->spi.spi->RXDATAX; |
<> | 144:ef7eb2e8f9f7 | 900 | } else { |
<> | 144:ef7eb2e8f9f7 | 901 | source_addr = &obj->spi.spi->RXDOUBLE; |
<> | 144:ef7eb2e8f9f7 | 902 | } |
<> | 144:ef7eb2e8f9f7 | 903 | |
<> | 144:ef7eb2e8f9f7 | 904 | LDMA_TransferCfg_t xferConf = LDMA_TRANSFER_CFG_PERIPHERAL(dma_periph); |
<> | 144:ef7eb2e8f9f7 | 905 | LDMA_Descriptor_t desc = LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(source_addr, rxdata, rx_length); |
<> | 144:ef7eb2e8f9f7 | 906 | |
<> | 144:ef7eb2e8f9f7 | 907 | if(obj->spi.bits >= 9){ |
<> | 144:ef7eb2e8f9f7 | 908 | desc.xfer.size = ldmaCtrlSizeHalf; |
<> | 144:ef7eb2e8f9f7 | 909 | } |
<> | 144:ef7eb2e8f9f7 | 910 | |
<> | 144:ef7eb2e8f9f7 | 911 | if (obj->tx_buff.width == 32) { |
<> | 144:ef7eb2e8f9f7 | 912 | if (obj->spi.bits >= 9) { |
<> | 144:ef7eb2e8f9f7 | 913 | desc.xfer.dstInc = ldmaCtrlDstIncTwo; |
<> | 144:ef7eb2e8f9f7 | 914 | } else { |
<> | 144:ef7eb2e8f9f7 | 915 | desc.xfer.dstInc = ldmaCtrlDstIncFour; |
<> | 144:ef7eb2e8f9f7 | 916 | } |
<> | 144:ef7eb2e8f9f7 | 917 | } else if (obj->tx_buff.width == 16) { |
<> | 144:ef7eb2e8f9f7 | 918 | if (obj->spi.bits >= 9) { |
<> | 144:ef7eb2e8f9f7 | 919 | desc.xfer.dstInc = ldmaCtrlDstIncOne; |
<> | 144:ef7eb2e8f9f7 | 920 | } else { |
<> | 144:ef7eb2e8f9f7 | 921 | desc.xfer.dstInc = ldmaCtrlDstIncTwo; |
<> | 144:ef7eb2e8f9f7 | 922 | } |
<> | 144:ef7eb2e8f9f7 | 923 | } else { |
<> | 144:ef7eb2e8f9f7 | 924 | desc.xfer.dstInc = ldmaCtrlDstIncOne; |
<> | 144:ef7eb2e8f9f7 | 925 | } |
<> | 144:ef7eb2e8f9f7 | 926 | |
<> | 144:ef7eb2e8f9f7 | 927 | LDMAx_StartTransfer(obj->spi.dmaOptionsRX.dmaChannel, &xferConf, &desc, serial_dmaTransferComplete,obj->spi.dmaOptionsRX.dmaCallback.userPtr); |
<> | 144:ef7eb2e8f9f7 | 928 | } |
<> | 144:ef7eb2e8f9f7 | 929 | |
<> | 144:ef7eb2e8f9f7 | 930 | volatile void *target_addr; |
<> | 144:ef7eb2e8f9f7 | 931 | |
<> | 144:ef7eb2e8f9f7 | 932 | /* Select TX target address. 9 bit frame length requires to use extended register. |
<> | 144:ef7eb2e8f9f7 | 933 | 10 bit and larger frame requires to use TXDOUBLE register. */ |
<> | 144:ef7eb2e8f9f7 | 934 | switch ((int)obj->spi.spi) { |
<> | 144:ef7eb2e8f9f7 | 935 | case USART_0: |
<> | 144:ef7eb2e8f9f7 | 936 | dma_periph = ldmaPeripheralSignal_USART0_TXBL; |
<> | 144:ef7eb2e8f9f7 | 937 | break; |
<> | 144:ef7eb2e8f9f7 | 938 | case USART_1: |
<> | 144:ef7eb2e8f9f7 | 939 | dma_periph = ldmaPeripheralSignal_USART1_TXBL; |
<> | 144:ef7eb2e8f9f7 | 940 | break; |
<> | 144:ef7eb2e8f9f7 | 941 | default: |
<> | 144:ef7eb2e8f9f7 | 942 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 943 | while(1); |
<> | 144:ef7eb2e8f9f7 | 944 | break; |
<> | 144:ef7eb2e8f9f7 | 945 | } |
<> | 144:ef7eb2e8f9f7 | 946 | |
<> | 144:ef7eb2e8f9f7 | 947 | if (obj->spi.bits <= 8) { |
<> | 144:ef7eb2e8f9f7 | 948 | target_addr = &obj->spi.spi->TXDATA; |
<> | 144:ef7eb2e8f9f7 | 949 | } else if (obj->spi.bits == 9) { |
<> | 144:ef7eb2e8f9f7 | 950 | target_addr = &obj->spi.spi->TXDATAX; |
<> | 144:ef7eb2e8f9f7 | 951 | } else { |
<> | 144:ef7eb2e8f9f7 | 952 | target_addr = &obj->spi.spi->TXDOUBLE; |
<> | 144:ef7eb2e8f9f7 | 953 | } |
<> | 144:ef7eb2e8f9f7 | 954 | |
<> | 144:ef7eb2e8f9f7 | 955 | /* Check the transmit length, and split long transfers to smaller ones */ |
<> | 144:ef7eb2e8f9f7 | 956 | int max_length = 1024; |
<> | 144:ef7eb2e8f9f7 | 957 | #ifdef _LDMA_CH_CTRL_XFERCNT_MASK |
<> | 144:ef7eb2e8f9f7 | 958 | max_length = (_LDMA_CH_CTRL_XFERCNT_MASK>>_LDMA_CH_CTRL_XFERCNT_SHIFT)+1; |
<> | 144:ef7eb2e8f9f7 | 959 | #endif |
<> | 144:ef7eb2e8f9f7 | 960 | if (tx_length > max_length) { |
<> | 144:ef7eb2e8f9f7 | 961 | tx_length = max_length; |
<> | 144:ef7eb2e8f9f7 | 962 | } |
<> | 144:ef7eb2e8f9f7 | 963 | |
<> | 144:ef7eb2e8f9f7 | 964 | /* Save amount of TX done by DMA */ |
<> | 144:ef7eb2e8f9f7 | 965 | obj->tx_buff.pos += tx_length; |
<> | 144:ef7eb2e8f9f7 | 966 | |
<> | 144:ef7eb2e8f9f7 | 967 | LDMA_TransferCfg_t xferConf = LDMA_TRANSFER_CFG_PERIPHERAL(dma_periph); |
<> | 144:ef7eb2e8f9f7 | 968 | LDMA_Descriptor_t desc = LDMA_DESCRIPTOR_SINGLE_M2P_BYTE((txdata ? txdata : &fill_word), target_addr, tx_length); |
<> | 144:ef7eb2e8f9f7 | 969 | |
<> | 144:ef7eb2e8f9f7 | 970 | if (obj->spi.bits >= 9) { |
<> | 144:ef7eb2e8f9f7 | 971 | desc.xfer.size = ldmaCtrlSizeHalf; |
<> | 144:ef7eb2e8f9f7 | 972 | } |
<> | 144:ef7eb2e8f9f7 | 973 | |
<> | 144:ef7eb2e8f9f7 | 974 | if (!txdata) { |
<> | 144:ef7eb2e8f9f7 | 975 | desc.xfer.srcInc = ldmaCtrlSrcIncNone; |
<> | 144:ef7eb2e8f9f7 | 976 | } else if (obj->tx_buff.width == 32) { |
<> | 144:ef7eb2e8f9f7 | 977 | if (obj->spi.bits >= 9) { |
<> | 144:ef7eb2e8f9f7 | 978 | desc.xfer.srcInc = ldmaCtrlSrcIncTwo; |
<> | 144:ef7eb2e8f9f7 | 979 | } else { |
<> | 144:ef7eb2e8f9f7 | 980 | desc.xfer.srcInc = ldmaCtrlSrcIncFour; |
<> | 144:ef7eb2e8f9f7 | 981 | } |
<> | 144:ef7eb2e8f9f7 | 982 | } else if (obj->tx_buff.width == 16) { |
<> | 144:ef7eb2e8f9f7 | 983 | if (obj->spi.bits >= 9) { |
<> | 144:ef7eb2e8f9f7 | 984 | desc.xfer.srcInc = ldmaCtrlSrcIncOne; |
<> | 144:ef7eb2e8f9f7 | 985 | } else { |
<> | 144:ef7eb2e8f9f7 | 986 | desc.xfer.srcInc = ldmaCtrlSrcIncTwo; |
<> | 144:ef7eb2e8f9f7 | 987 | } |
<> | 144:ef7eb2e8f9f7 | 988 | } else { |
<> | 144:ef7eb2e8f9f7 | 989 | desc.xfer.srcInc = ldmaCtrlSrcIncOne; |
<> | 144:ef7eb2e8f9f7 | 990 | } |
<> | 144:ef7eb2e8f9f7 | 991 | |
<> | 144:ef7eb2e8f9f7 | 992 | // Kick off DMA TX |
<> | 144:ef7eb2e8f9f7 | 993 | LDMAx_StartTransfer(obj->spi.dmaOptionsTX.dmaChannel, &xferConf, &desc, serial_dmaTransferComplete,obj->spi.dmaOptionsTX.dmaCallback.userPtr); |
<> | 144:ef7eb2e8f9f7 | 994 | } |
<> | 144:ef7eb2e8f9f7 | 995 | |
<> | 144:ef7eb2e8f9f7 | 996 | #else |
<> | 144:ef7eb2e8f9f7 | 997 | /****************************************** |
<> | 144:ef7eb2e8f9f7 | 998 | * void spi_activate_dma(spi_t *obj, void* rxdata, void* txdata, int length) |
<> | 144:ef7eb2e8f9f7 | 999 | * |
<> | 144:ef7eb2e8f9f7 | 1000 | * This function will start the DMA engine for SPI transfers |
<> | 144:ef7eb2e8f9f7 | 1001 | * |
<> | 144:ef7eb2e8f9f7 | 1002 | * * rxdata: pointer to RX buffer, if needed. |
<> | 144:ef7eb2e8f9f7 | 1003 | * * txdata: pointer to TX buffer, if needed. Else FF's. |
<> | 144:ef7eb2e8f9f7 | 1004 | * * tx_length: how many bytes will get sent. |
<> | 144:ef7eb2e8f9f7 | 1005 | * * rx_length: how many bytes will get received. If > tx_length, TX will get padded with n lower bits of SPI_FILL_WORD. |
<> | 144:ef7eb2e8f9f7 | 1006 | ******************************************/ |
<> | 144:ef7eb2e8f9f7 | 1007 | static void spi_activate_dma(spi_t *obj, void* rxdata, const void* txdata, int tx_length, int rx_length) |
<> | 144:ef7eb2e8f9f7 | 1008 | { |
<> | 144:ef7eb2e8f9f7 | 1009 | /* DMA descriptors */ |
<> | 144:ef7eb2e8f9f7 | 1010 | DMA_CfgDescr_TypeDef rxDescrCfg; |
<> | 144:ef7eb2e8f9f7 | 1011 | DMA_CfgDescr_TypeDef txDescrCfg; |
<> | 144:ef7eb2e8f9f7 | 1012 | |
<> | 144:ef7eb2e8f9f7 | 1013 | /* Split up transfers if the length is larger than what the DMA supports. */ |
<> | 144:ef7eb2e8f9f7 | 1014 | const int DMA_MAX_TRANSFER = (_DMA_CTRL_N_MINUS_1_MASK >> _DMA_CTRL_N_MINUS_1_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1015 | |
<> | 144:ef7eb2e8f9f7 | 1016 | if (tx_length > DMA_MAX_TRANSFER) { |
<> | 144:ef7eb2e8f9f7 | 1017 | tx_length = DMA_MAX_TRANSFER; |
<> | 144:ef7eb2e8f9f7 | 1018 | } |
<> | 144:ef7eb2e8f9f7 | 1019 | if (rx_length > DMA_MAX_TRANSFER) { |
<> | 144:ef7eb2e8f9f7 | 1020 | rx_length = DMA_MAX_TRANSFER; |
<> | 144:ef7eb2e8f9f7 | 1021 | } |
<> | 144:ef7eb2e8f9f7 | 1022 | |
<> | 144:ef7eb2e8f9f7 | 1023 | /* Save amount of TX done by DMA */ |
<> | 144:ef7eb2e8f9f7 | 1024 | obj->tx_buff.pos += tx_length; |
<> | 144:ef7eb2e8f9f7 | 1025 | obj->rx_buff.pos += rx_length; |
<> | 144:ef7eb2e8f9f7 | 1026 | |
<> | 144:ef7eb2e8f9f7 | 1027 | /* Only activate RX DMA if a receive buffer is specified */ |
<> | 144:ef7eb2e8f9f7 | 1028 | if (rxdata != NULL) { |
<> | 144:ef7eb2e8f9f7 | 1029 | // Setting up channel descriptor |
<> | 144:ef7eb2e8f9f7 | 1030 | if (obj->rx_buff.width == 32) { |
<> | 144:ef7eb2e8f9f7 | 1031 | rxDescrCfg.dstInc = dmaDataInc4; |
<> | 144:ef7eb2e8f9f7 | 1032 | } else if (obj->rx_buff.width == 16) { |
<> | 144:ef7eb2e8f9f7 | 1033 | rxDescrCfg.dstInc = dmaDataInc2; |
<> | 144:ef7eb2e8f9f7 | 1034 | } else { |
<> | 144:ef7eb2e8f9f7 | 1035 | rxDescrCfg.dstInc = dmaDataInc1; |
<> | 144:ef7eb2e8f9f7 | 1036 | } |
<> | 144:ef7eb2e8f9f7 | 1037 | rxDescrCfg.srcInc = dmaDataIncNone; |
<> | 144:ef7eb2e8f9f7 | 1038 | rxDescrCfg.size = (obj->spi.bits <= 8 ? dmaDataSize1 : dmaDataSize2); //When frame size >= 9, use RXDOUBLE |
<> | 144:ef7eb2e8f9f7 | 1039 | rxDescrCfg.arbRate = dmaArbitrate1; |
<> | 144:ef7eb2e8f9f7 | 1040 | rxDescrCfg.hprot = 0; |
<> | 144:ef7eb2e8f9f7 | 1041 | DMA_CfgDescr(obj->spi.dmaOptionsRX.dmaChannel, true, &rxDescrCfg); |
<> | 144:ef7eb2e8f9f7 | 1042 | |
<> | 144:ef7eb2e8f9f7 | 1043 | void * rx_reg; |
<> | 144:ef7eb2e8f9f7 | 1044 | if (obj->spi.bits > 9) { |
<> | 144:ef7eb2e8f9f7 | 1045 | rx_reg = (void *)&obj->spi.spi->RXDOUBLE; |
<> | 144:ef7eb2e8f9f7 | 1046 | } else if (obj->spi.bits == 9) { |
<> | 144:ef7eb2e8f9f7 | 1047 | rx_reg = (void *)&obj->spi.spi->RXDATAX; |
<> | 144:ef7eb2e8f9f7 | 1048 | } else { |
<> | 144:ef7eb2e8f9f7 | 1049 | rx_reg = (void *)&obj->spi.spi->RXDATA; |
<> | 144:ef7eb2e8f9f7 | 1050 | } |
<> | 144:ef7eb2e8f9f7 | 1051 | |
<> | 144:ef7eb2e8f9f7 | 1052 | /* Activate RX channel */ |
<> | 144:ef7eb2e8f9f7 | 1053 | DMA_ActivateBasic(obj->spi.dmaOptionsRX.dmaChannel, |
<> | 144:ef7eb2e8f9f7 | 1054 | true, |
<> | 144:ef7eb2e8f9f7 | 1055 | false, |
<> | 144:ef7eb2e8f9f7 | 1056 | rxdata, |
<> | 144:ef7eb2e8f9f7 | 1057 | rx_reg, |
<> | 144:ef7eb2e8f9f7 | 1058 | rx_length - 1); |
<> | 144:ef7eb2e8f9f7 | 1059 | } |
<> | 144:ef7eb2e8f9f7 | 1060 | |
<> | 144:ef7eb2e8f9f7 | 1061 | // buffer with all FFs. |
<> | 144:ef7eb2e8f9f7 | 1062 | /* Setting up channel descriptor */ |
<> | 144:ef7eb2e8f9f7 | 1063 | txDescrCfg.dstInc = dmaDataIncNone; |
<> | 144:ef7eb2e8f9f7 | 1064 | if (txdata == 0) { |
<> | 144:ef7eb2e8f9f7 | 1065 | // Don't increment source when there is no transmit buffer |
<> | 144:ef7eb2e8f9f7 | 1066 | txDescrCfg.srcInc = dmaDataIncNone; |
<> | 144:ef7eb2e8f9f7 | 1067 | } else { |
<> | 144:ef7eb2e8f9f7 | 1068 | if (obj->tx_buff.width == 32) { |
<> | 144:ef7eb2e8f9f7 | 1069 | txDescrCfg.srcInc = dmaDataInc4; |
<> | 144:ef7eb2e8f9f7 | 1070 | } else if (obj->tx_buff.width == 16) { |
<> | 144:ef7eb2e8f9f7 | 1071 | txDescrCfg.srcInc = dmaDataInc2; |
<> | 144:ef7eb2e8f9f7 | 1072 | } else { |
<> | 144:ef7eb2e8f9f7 | 1073 | txDescrCfg.srcInc = dmaDataInc1; |
<> | 144:ef7eb2e8f9f7 | 1074 | } |
<> | 144:ef7eb2e8f9f7 | 1075 | } |
<> | 144:ef7eb2e8f9f7 | 1076 | txDescrCfg.size = (obj->spi.bits <= 8 ? dmaDataSize1 : dmaDataSize2); //When frame size >= 9, use TXDOUBLE |
<> | 144:ef7eb2e8f9f7 | 1077 | txDescrCfg.arbRate = dmaArbitrate1; |
<> | 144:ef7eb2e8f9f7 | 1078 | txDescrCfg.hprot = 0; |
<> | 144:ef7eb2e8f9f7 | 1079 | DMA_CfgDescr(obj->spi.dmaOptionsTX.dmaChannel, true, &txDescrCfg); |
<> | 144:ef7eb2e8f9f7 | 1080 | |
<> | 144:ef7eb2e8f9f7 | 1081 | void * tx_reg; |
<> | 144:ef7eb2e8f9f7 | 1082 | if (obj->spi.bits > 9) { |
<> | 144:ef7eb2e8f9f7 | 1083 | tx_reg = (void *)&obj->spi.spi->TXDOUBLE; |
<> | 144:ef7eb2e8f9f7 | 1084 | } else if (obj->spi.bits == 9) { |
<> | 144:ef7eb2e8f9f7 | 1085 | tx_reg = (void *)&obj->spi.spi->TXDATAX; |
<> | 144:ef7eb2e8f9f7 | 1086 | } else { |
<> | 144:ef7eb2e8f9f7 | 1087 | tx_reg = (void *)&obj->spi.spi->TXDATA; |
<> | 144:ef7eb2e8f9f7 | 1088 | } |
<> | 144:ef7eb2e8f9f7 | 1089 | |
<> | 144:ef7eb2e8f9f7 | 1090 | /* Activate TX channel */ |
<> | 144:ef7eb2e8f9f7 | 1091 | DMA_ActivateBasic(obj->spi.dmaOptionsTX.dmaChannel, |
<> | 144:ef7eb2e8f9f7 | 1092 | true, |
<> | 144:ef7eb2e8f9f7 | 1093 | false, |
<> | 144:ef7eb2e8f9f7 | 1094 | tx_reg, |
<> | 144:ef7eb2e8f9f7 | 1095 | (txdata == 0 ? &fill_word : (void *)txdata), // When there is nothing to transmit, point to static fill word |
<> | 144:ef7eb2e8f9f7 | 1096 | (tx_length - 1)); |
<> | 144:ef7eb2e8f9f7 | 1097 | } |
<> | 144:ef7eb2e8f9f7 | 1098 | #endif //LDMA_PRESENT |
<> | 144:ef7eb2e8f9f7 | 1099 | /******************************************************************** |
<> | 144:ef7eb2e8f9f7 | 1100 | * spi_master_transfer_dma(spi_t *obj, void *rxdata, void *txdata, int length, DMACallback cb, DMAUsage hint) |
<> | 144:ef7eb2e8f9f7 | 1101 | * |
<> | 144:ef7eb2e8f9f7 | 1102 | * Start an SPI transfer by using DMA and the supplied hint for DMA useage |
<> | 144:ef7eb2e8f9f7 | 1103 | * |
<> | 144:ef7eb2e8f9f7 | 1104 | * * obj: pointer to specific SPI instance |
<> | 144:ef7eb2e8f9f7 | 1105 | * * rxdata: pointer to rx buffer. If null, we will assume only TX is relevant, and RX will be ignored. |
<> | 144:ef7eb2e8f9f7 | 1106 | * * txdata: pointer to TX buffer. If null, we will assume only the read is relevant, and will send FF's for reading back. |
<> | 144:ef7eb2e8f9f7 | 1107 | * * length: How many bytes should be written/read. |
<> | 144:ef7eb2e8f9f7 | 1108 | * * cb: thunk pointer into CPP-land to get the spi object |
<> | 144:ef7eb2e8f9f7 | 1109 | * * hint: hint for the requested DMA useage. |
<> | 144:ef7eb2e8f9f7 | 1110 | * * NEVER: do not use DMA, but use IRQ instead |
<> | 144:ef7eb2e8f9f7 | 1111 | * * OPPORTUNISTIC: use DMA if there are channels available, but return them after the transfer. |
<> | 144:ef7eb2e8f9f7 | 1112 | * * ALWAYS: use DMA if channels are available, and hold on to the channels after the transfer. |
<> | 144:ef7eb2e8f9f7 | 1113 | * If the previous transfer has kept the channel, that channel will continue to get used. |
<> | 144:ef7eb2e8f9f7 | 1114 | * |
<> | 144:ef7eb2e8f9f7 | 1115 | ********************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 1116 | void spi_master_transfer_dma(spi_t *obj, const void *txdata, void *rxdata, int tx_length, int rx_length, void* cb, DMAUsage hint) |
<> | 144:ef7eb2e8f9f7 | 1117 | { |
<> | 144:ef7eb2e8f9f7 | 1118 | /* Init DMA here to include it in the power figure */ |
<> | 144:ef7eb2e8f9f7 | 1119 | dma_init(); |
<> | 144:ef7eb2e8f9f7 | 1120 | /* Clear TX and RX registers */ |
<> | 144:ef7eb2e8f9f7 | 1121 | obj->spi.spi->CMD = USART_CMD_CLEARTX; |
<> | 144:ef7eb2e8f9f7 | 1122 | obj->spi.spi->CMD = USART_CMD_CLEARRX; |
<> | 144:ef7eb2e8f9f7 | 1123 | /* If the DMA channels are already allocated, we can assume they have been setup already */ |
<> | 144:ef7eb2e8f9f7 | 1124 | if (hint != DMA_USAGE_NEVER && obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_ALLOCATED) { |
<> | 144:ef7eb2e8f9f7 | 1125 | /* setup has already been done, so just activate the transfer */ |
<> | 144:ef7eb2e8f9f7 | 1126 | spi_activate_dma(obj, rxdata, txdata, tx_length, rx_length); |
<> | 144:ef7eb2e8f9f7 | 1127 | } else if (hint == DMA_USAGE_NEVER) { |
<> | 144:ef7eb2e8f9f7 | 1128 | /* use IRQ */ |
<> | 144:ef7eb2e8f9f7 | 1129 | obj->spi.spi->IFC = 0xFFFFFFFF; |
<> | 144:ef7eb2e8f9f7 | 1130 | spi_master_write_asynch(obj); |
<> | 144:ef7eb2e8f9f7 | 1131 | spi_enable_interrupt(obj, (uint32_t)cb, true); |
<> | 144:ef7eb2e8f9f7 | 1132 | } else { |
<> | 144:ef7eb2e8f9f7 | 1133 | /* try to acquire channels */ |
<> | 144:ef7eb2e8f9f7 | 1134 | dma_init(); |
<> | 144:ef7eb2e8f9f7 | 1135 | spi_enable_dma(obj, hint); |
<> | 144:ef7eb2e8f9f7 | 1136 | |
<> | 144:ef7eb2e8f9f7 | 1137 | /* decide between DMA and IRQ */ |
<> | 144:ef7eb2e8f9f7 | 1138 | if (obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_ALLOCATED || obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { |
<> | 144:ef7eb2e8f9f7 | 1139 | /* disable the interrupts that may have been left open previously */ |
<> | 144:ef7eb2e8f9f7 | 1140 | spi_enable_interrupt(obj, (uint32_t)cb, false); |
<> | 144:ef7eb2e8f9f7 | 1141 | |
<> | 144:ef7eb2e8f9f7 | 1142 | /* DMA channels are allocated, so do their setup */ |
<> | 144:ef7eb2e8f9f7 | 1143 | spi_master_dma_channel_setup(obj, cb); |
<> | 144:ef7eb2e8f9f7 | 1144 | /* and activate the transfer */ |
<> | 144:ef7eb2e8f9f7 | 1145 | spi_activate_dma(obj, rxdata, txdata, tx_length, rx_length); |
<> | 144:ef7eb2e8f9f7 | 1146 | } else { |
<> | 144:ef7eb2e8f9f7 | 1147 | /* DMA is unavailable, so fall back to IRQ */ |
<> | 144:ef7eb2e8f9f7 | 1148 | obj->spi.spi->IFC = 0xFFFFFFFF; |
<> | 144:ef7eb2e8f9f7 | 1149 | spi_master_write_asynch(obj); |
<> | 144:ef7eb2e8f9f7 | 1150 | spi_enable_interrupt(obj, (uint32_t)cb, true); |
<> | 144:ef7eb2e8f9f7 | 1151 | } |
<> | 144:ef7eb2e8f9f7 | 1152 | } |
<> | 144:ef7eb2e8f9f7 | 1153 | } |
<> | 144:ef7eb2e8f9f7 | 1154 | |
<> | 144:ef7eb2e8f9f7 | 1155 | /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff |
<> | 144:ef7eb2e8f9f7 | 1156 | * |
<> | 144:ef7eb2e8f9f7 | 1157 | * @param[in] obj The SPI object which holds the transfer information |
<> | 144:ef7eb2e8f9f7 | 1158 | * @param[in] tx The buffer to send |
<> | 144:ef7eb2e8f9f7 | 1159 | * @param[in] tx_length The number of words to transmit |
<> | 144:ef7eb2e8f9f7 | 1160 | * @param[in] rx The buffer to receive |
<> | 144:ef7eb2e8f9f7 | 1161 | * @param[in] rx_length The number of words to receive |
<> | 144:ef7eb2e8f9f7 | 1162 | * @param[in] bit_width The bit width of buffer words |
<> | 144:ef7eb2e8f9f7 | 1163 | * @param[in] event The logical OR of events to be registered |
<> | 144:ef7eb2e8f9f7 | 1164 | * @param[in] handler SPI interrupt handler |
<> | 144:ef7eb2e8f9f7 | 1165 | * @param[in] hint A suggestion for how to use DMA with this transfer |
<> | 144:ef7eb2e8f9f7 | 1166 | */ |
<> | 144:ef7eb2e8f9f7 | 1167 | void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint) |
<> | 144:ef7eb2e8f9f7 | 1168 | { |
<> | 144:ef7eb2e8f9f7 | 1169 | if( spi_active(obj) ) return; |
<> | 144:ef7eb2e8f9f7 | 1170 | |
<> | 144:ef7eb2e8f9f7 | 1171 | /* update fill word if on 9-bit frame size */ |
<> | 144:ef7eb2e8f9f7 | 1172 | if(obj->spi.bits == 9) fill_word = SPI_FILL_WORD & 0x1FF; |
<> | 144:ef7eb2e8f9f7 | 1173 | else fill_word = SPI_FILL_WORD; |
<> | 144:ef7eb2e8f9f7 | 1174 | |
<> | 144:ef7eb2e8f9f7 | 1175 | /* check corner case */ |
<> | 144:ef7eb2e8f9f7 | 1176 | if(tx_length == 0) { |
<> | 144:ef7eb2e8f9f7 | 1177 | tx_length = rx_length; |
<> | 144:ef7eb2e8f9f7 | 1178 | tx = (void*) 0; |
<> | 144:ef7eb2e8f9f7 | 1179 | } |
<> | 144:ef7eb2e8f9f7 | 1180 | |
<> | 144:ef7eb2e8f9f7 | 1181 | /* First, set the buffer */ |
<> | 144:ef7eb2e8f9f7 | 1182 | spi_buffer_set(obj, tx, tx_length, rx, rx_length, bit_width); |
<> | 144:ef7eb2e8f9f7 | 1183 | |
<> | 144:ef7eb2e8f9f7 | 1184 | /* Then, enable the events */ |
<> | 144:ef7eb2e8f9f7 | 1185 | spi_enable_event(obj, SPI_EVENT_ALL, false); |
<> | 144:ef7eb2e8f9f7 | 1186 | spi_enable_event(obj, event, true); |
<> | 144:ef7eb2e8f9f7 | 1187 | |
<> | 144:ef7eb2e8f9f7 | 1188 | // Set the sleep mode |
Anna Bridge |
180:96ed750bd169 | 1189 | sleep_manager_lock_deep_sleep(); |
<> | 144:ef7eb2e8f9f7 | 1190 | |
<> | 144:ef7eb2e8f9f7 | 1191 | /* And kick off the transfer */ |
<> | 144:ef7eb2e8f9f7 | 1192 | spi_master_transfer_dma(obj, tx, rx, tx_length, rx_length, (void*)handler, hint); |
<> | 144:ef7eb2e8f9f7 | 1193 | } |
<> | 144:ef7eb2e8f9f7 | 1194 | |
<> | 144:ef7eb2e8f9f7 | 1195 | |
<> | 144:ef7eb2e8f9f7 | 1196 | /******************************************************************** |
<> | 144:ef7eb2e8f9f7 | 1197 | * uint32_t spi_irq_handler_generic(spi_t* obj) |
<> | 144:ef7eb2e8f9f7 | 1198 | * |
<> | 144:ef7eb2e8f9f7 | 1199 | * handler which should get called by CPP-land when either a DMA or SPI IRQ gets fired for a SPI transaction. |
<> | 144:ef7eb2e8f9f7 | 1200 | * |
<> | 144:ef7eb2e8f9f7 | 1201 | * * obj: pointer to the specific SPI instance |
<> | 144:ef7eb2e8f9f7 | 1202 | * |
<> | 144:ef7eb2e8f9f7 | 1203 | * return: event mask. Currently only 0 or SPI_EVENT_COMPLETE upon transfer completion. |
<> | 144:ef7eb2e8f9f7 | 1204 | * |
<> | 144:ef7eb2e8f9f7 | 1205 | ********************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 1206 | #ifdef LDMA_PRESENT |
<> | 144:ef7eb2e8f9f7 | 1207 | uint32_t spi_irq_handler_asynch(spi_t* obj) |
<> | 144:ef7eb2e8f9f7 | 1208 | { |
<> | 144:ef7eb2e8f9f7 | 1209 | if (obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_ALLOCATED || obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { |
<> | 144:ef7eb2e8f9f7 | 1210 | /* DMA implementation */ |
<> | 144:ef7eb2e8f9f7 | 1211 | /* If there is still data in the TX buffer, setup a new transfer. */ |
<> | 144:ef7eb2e8f9f7 | 1212 | if (obj->tx_buff.pos < obj->tx_buff.length) { |
<> | 144:ef7eb2e8f9f7 | 1213 | /* Find position and remaining length without modifying tx_buff. */ |
<> | 144:ef7eb2e8f9f7 | 1214 | void* tx_pointer = (char*)obj->tx_buff.buffer + obj->tx_buff.pos; |
<> | 144:ef7eb2e8f9f7 | 1215 | uint32_t tx_length = obj->tx_buff.length - obj->tx_buff.pos; |
<> | 144:ef7eb2e8f9f7 | 1216 | |
<> | 144:ef7eb2e8f9f7 | 1217 | /* Begin transfer. Rely on spi_activate_dma to split up the transfer further. */ |
<> | 144:ef7eb2e8f9f7 | 1218 | spi_activate_dma(obj, obj->rx_buff.buffer, tx_pointer, tx_length, obj->rx_buff.length); |
<> | 144:ef7eb2e8f9f7 | 1219 | |
<> | 144:ef7eb2e8f9f7 | 1220 | return 0; |
<> | 144:ef7eb2e8f9f7 | 1221 | } |
<> | 144:ef7eb2e8f9f7 | 1222 | /* If there is an RX transfer ongoing, wait for it to finish */ |
<> | 144:ef7eb2e8f9f7 | 1223 | if (LDMAx_ChannelEnabled(obj->spi.dmaOptionsRX.dmaChannel)) { |
<> | 144:ef7eb2e8f9f7 | 1224 | /* Check if we need to kick off TX transfer again to force more incoming data. */ |
<> | 144:ef7eb2e8f9f7 | 1225 | if (LDMA_TransferDone(obj->spi.dmaOptionsTX.dmaChannel) && (obj->tx_buff.pos < obj->rx_buff.length)) { |
<> | 144:ef7eb2e8f9f7 | 1226 | void* tx_pointer = (char*)obj->tx_buff.buffer + obj->tx_buff.pos; |
<> | 144:ef7eb2e8f9f7 | 1227 | uint32_t tx_length = obj->tx_buff.length - obj->tx_buff.pos; |
<> | 144:ef7eb2e8f9f7 | 1228 | /* Begin transfer. Rely on spi_activate_dma to split up the transfer further. */ |
<> | 144:ef7eb2e8f9f7 | 1229 | spi_activate_dma(obj, obj->rx_buff.buffer, tx_pointer, tx_length, obj->rx_buff.length); |
<> | 144:ef7eb2e8f9f7 | 1230 | } else return 0; |
<> | 144:ef7eb2e8f9f7 | 1231 | } |
<> | 144:ef7eb2e8f9f7 | 1232 | /* If there is still a TX transfer ongoing (tx_length > rx_length), wait for it to finish */ |
<> | 144:ef7eb2e8f9f7 | 1233 | if (!LDMA_TransferDone(obj->spi.dmaOptionsTX.dmaChannel)) { |
<> | 144:ef7eb2e8f9f7 | 1234 | return 0; |
<> | 144:ef7eb2e8f9f7 | 1235 | } |
<> | 144:ef7eb2e8f9f7 | 1236 | /* Release the dma channels if they were opportunistically allocated */ |
<> | 144:ef7eb2e8f9f7 | 1237 | if (obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { |
<> | 144:ef7eb2e8f9f7 | 1238 | dma_channel_free(obj->spi.dmaOptionsTX.dmaChannel); |
<> | 144:ef7eb2e8f9f7 | 1239 | dma_channel_free(obj->spi.dmaOptionsRX.dmaChannel); |
<> | 144:ef7eb2e8f9f7 | 1240 | obj->spi.dmaOptionsTX.dmaUsageState = DMA_USAGE_OPPORTUNISTIC; |
<> | 144:ef7eb2e8f9f7 | 1241 | } |
<> | 144:ef7eb2e8f9f7 | 1242 | |
<> | 144:ef7eb2e8f9f7 | 1243 | /* Wait transmit to complete, before user code is indicated*/ |
<> | 144:ef7eb2e8f9f7 | 1244 | while(!(obj->spi.spi->STATUS & USART_STATUS_TXC)); |
Anna Bridge |
180:96ed750bd169 | 1245 | sleep_manager_unlock_deep_sleep(); |
<> | 144:ef7eb2e8f9f7 | 1246 | /* return to CPP land to say we're finished */ |
<> | 144:ef7eb2e8f9f7 | 1247 | return SPI_EVENT_COMPLETE; |
<> | 144:ef7eb2e8f9f7 | 1248 | } else { |
<> | 144:ef7eb2e8f9f7 | 1249 | /* IRQ implementation */ |
<> | 144:ef7eb2e8f9f7 | 1250 | if (spi_master_rx_int_flag(obj)) { |
<> | 144:ef7eb2e8f9f7 | 1251 | spi_master_read_asynch(obj); |
<> | 144:ef7eb2e8f9f7 | 1252 | } |
<> | 144:ef7eb2e8f9f7 | 1253 | |
<> | 144:ef7eb2e8f9f7 | 1254 | if (spi_master_tx_int_flag(obj)) { |
<> | 144:ef7eb2e8f9f7 | 1255 | spi_master_write_asynch(obj); |
<> | 144:ef7eb2e8f9f7 | 1256 | } |
<> | 144:ef7eb2e8f9f7 | 1257 | |
<> | 144:ef7eb2e8f9f7 | 1258 | uint32_t event = spi_event_check(obj); |
<> | 144:ef7eb2e8f9f7 | 1259 | if (event & SPI_EVENT_INTERNAL_TRANSFER_COMPLETE) { |
<> | 144:ef7eb2e8f9f7 | 1260 | /* disable interrupts */ |
<> | 144:ef7eb2e8f9f7 | 1261 | spi_enable_interrupt(obj, (uint32_t)NULL, false); |
<> | 144:ef7eb2e8f9f7 | 1262 | |
Anna Bridge |
180:96ed750bd169 | 1263 | sleep_manager_unlock_deep_sleep(); |
<> | 144:ef7eb2e8f9f7 | 1264 | /* Return the event back to userland */ |
<> | 144:ef7eb2e8f9f7 | 1265 | return event; |
<> | 144:ef7eb2e8f9f7 | 1266 | } |
<> | 144:ef7eb2e8f9f7 | 1267 | |
<> | 144:ef7eb2e8f9f7 | 1268 | return 0; |
<> | 144:ef7eb2e8f9f7 | 1269 | } |
<> | 144:ef7eb2e8f9f7 | 1270 | } |
<> | 144:ef7eb2e8f9f7 | 1271 | #else |
<> | 144:ef7eb2e8f9f7 | 1272 | uint32_t spi_irq_handler_asynch(spi_t* obj) |
<> | 144:ef7eb2e8f9f7 | 1273 | { |
<> | 144:ef7eb2e8f9f7 | 1274 | |
<> | 144:ef7eb2e8f9f7 | 1275 | /* Determine whether the current scenario is DMA or IRQ, and act accordingly */ |
<> | 144:ef7eb2e8f9f7 | 1276 | |
<> | 144:ef7eb2e8f9f7 | 1277 | if (obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_ALLOCATED || obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { |
<> | 144:ef7eb2e8f9f7 | 1278 | /* DMA implementation */ |
<> | 144:ef7eb2e8f9f7 | 1279 | |
<> | 144:ef7eb2e8f9f7 | 1280 | /* If there is still data in the TX buffer, setup a new transfer. */ |
<> | 144:ef7eb2e8f9f7 | 1281 | if (obj->tx_buff.pos < obj->tx_buff.length) { |
<> | 144:ef7eb2e8f9f7 | 1282 | /* If there is still a TX transfer ongoing, let it finish |
<> | 144:ef7eb2e8f9f7 | 1283 | * before (if necessary) kicking off a new transfer */ |
<> | 144:ef7eb2e8f9f7 | 1284 | if (DMA_ChannelEnabled(obj->spi.dmaOptionsTX.dmaChannel)) { |
<> | 144:ef7eb2e8f9f7 | 1285 | return 0; |
<> | 144:ef7eb2e8f9f7 | 1286 | } |
<> | 144:ef7eb2e8f9f7 | 1287 | /* Find position and remaining length without modifying tx_buff. */ |
<> | 144:ef7eb2e8f9f7 | 1288 | void * tx_pointer; |
<> | 144:ef7eb2e8f9f7 | 1289 | if (obj->tx_buff.width == 32) { |
<> | 144:ef7eb2e8f9f7 | 1290 | tx_pointer = ((uint32_t *)obj->tx_buff.buffer) + obj->tx_buff.pos; |
<> | 144:ef7eb2e8f9f7 | 1291 | } else if (obj->tx_buff.width == 16) { |
<> | 144:ef7eb2e8f9f7 | 1292 | tx_pointer = ((uint16_t *)obj->tx_buff.buffer) + obj->tx_buff.pos; |
<> | 144:ef7eb2e8f9f7 | 1293 | } else { |
<> | 144:ef7eb2e8f9f7 | 1294 | tx_pointer = ((uint8_t *)obj->tx_buff.buffer) + obj->tx_buff.pos; |
<> | 144:ef7eb2e8f9f7 | 1295 | } |
<> | 144:ef7eb2e8f9f7 | 1296 | uint32_t tx_length = obj->tx_buff.length - obj->tx_buff.pos; |
<> | 144:ef7eb2e8f9f7 | 1297 | |
<> | 144:ef7eb2e8f9f7 | 1298 | /* Refresh RX transfer too if it exists */ |
<> | 144:ef7eb2e8f9f7 | 1299 | void * rx_pointer = NULL; |
<> | 144:ef7eb2e8f9f7 | 1300 | if (obj->rx_buff.pos < obj->rx_buff.length) { |
<> | 144:ef7eb2e8f9f7 | 1301 | if (obj->rx_buff.width == 32) { |
<> | 144:ef7eb2e8f9f7 | 1302 | rx_pointer = ((uint32_t *)obj->rx_buff.buffer) + obj->rx_buff.pos; |
<> | 144:ef7eb2e8f9f7 | 1303 | } else if (obj->rx_buff.width == 16) { |
<> | 144:ef7eb2e8f9f7 | 1304 | rx_pointer = ((uint16_t *)obj->rx_buff.buffer) + obj->rx_buff.pos; |
<> | 144:ef7eb2e8f9f7 | 1305 | } else { |
<> | 144:ef7eb2e8f9f7 | 1306 | rx_pointer = ((uint8_t *)obj->rx_buff.buffer) + obj->rx_buff.pos; |
AnnaBridge | 179:b0033dcd6934 | 1307 | } |
<> | 144:ef7eb2e8f9f7 | 1308 | } |
<> | 144:ef7eb2e8f9f7 | 1309 | uint32_t rx_length = obj->rx_buff.length - obj->rx_buff.pos; |
<> | 144:ef7eb2e8f9f7 | 1310 | |
<> | 144:ef7eb2e8f9f7 | 1311 | /* Wait for the previous transfer to complete. */ |
<> | 144:ef7eb2e8f9f7 | 1312 | while(!(obj->spi.spi->STATUS & USART_STATUS_TXC)); |
<> | 144:ef7eb2e8f9f7 | 1313 | |
<> | 144:ef7eb2e8f9f7 | 1314 | /* Begin transfer. Rely on spi_activate_dma to split up the transfer further. */ |
<> | 144:ef7eb2e8f9f7 | 1315 | spi_activate_dma(obj, rx_pointer, tx_pointer, tx_length, rx_length); |
<> | 144:ef7eb2e8f9f7 | 1316 | |
<> | 144:ef7eb2e8f9f7 | 1317 | return 0; |
<> | 144:ef7eb2e8f9f7 | 1318 | } |
<> | 144:ef7eb2e8f9f7 | 1319 | |
<> | 144:ef7eb2e8f9f7 | 1320 | /* If an RX transfer is ongoing, continue processing RX data */ |
<> | 144:ef7eb2e8f9f7 | 1321 | if (DMA_ChannelEnabled(obj->spi.dmaOptionsRX.dmaChannel)) { |
<> | 144:ef7eb2e8f9f7 | 1322 | /* Check if we need to kick off TX transfer again to force more incoming data. */ |
<> | 144:ef7eb2e8f9f7 | 1323 | if (!DMA_ChannelEnabled(obj->spi.dmaOptionsTX.dmaChannel) && (obj->rx_buff.pos < obj->rx_buff.length)) { |
<> | 144:ef7eb2e8f9f7 | 1324 | //Save state of TX transfer amount |
<> | 144:ef7eb2e8f9f7 | 1325 | int length_diff = obj->rx_buff.length - obj->rx_buff.pos; |
<> | 144:ef7eb2e8f9f7 | 1326 | obj->tx_buff.pos = obj->rx_buff.length; |
<> | 144:ef7eb2e8f9f7 | 1327 | |
<> | 144:ef7eb2e8f9f7 | 1328 | //Kick off a new DMA transfer |
<> | 144:ef7eb2e8f9f7 | 1329 | DMA_CfgDescr_TypeDef txDescrCfg; |
<> | 144:ef7eb2e8f9f7 | 1330 | |
<> | 144:ef7eb2e8f9f7 | 1331 | fill_word = SPI_FILL_WORD; |
<> | 144:ef7eb2e8f9f7 | 1332 | /* Setting up channel descriptor */ |
<> | 144:ef7eb2e8f9f7 | 1333 | txDescrCfg.dstInc = dmaDataIncNone; |
<> | 144:ef7eb2e8f9f7 | 1334 | txDescrCfg.srcInc = dmaDataIncNone; //Do not increment source pointer when there is no transmit buffer |
<> | 144:ef7eb2e8f9f7 | 1335 | txDescrCfg.size = (obj->spi.bits <= 8 ? dmaDataSize1 : dmaDataSize2); //When frame size > 9, we can use TXDOUBLE to save bandwidth |
<> | 144:ef7eb2e8f9f7 | 1336 | txDescrCfg.arbRate = dmaArbitrate1; |
<> | 144:ef7eb2e8f9f7 | 1337 | txDescrCfg.hprot = 0; |
<> | 144:ef7eb2e8f9f7 | 1338 | DMA_CfgDescr(obj->spi.dmaOptionsTX.dmaChannel, true, &txDescrCfg); |
<> | 144:ef7eb2e8f9f7 | 1339 | |
<> | 144:ef7eb2e8f9f7 | 1340 | void * tx_reg; |
<> | 144:ef7eb2e8f9f7 | 1341 | if (obj->spi.bits > 9) { |
<> | 144:ef7eb2e8f9f7 | 1342 | tx_reg = (void *)&obj->spi.spi->TXDOUBLE; |
<> | 144:ef7eb2e8f9f7 | 1343 | } else if (obj->spi.bits == 9) { |
<> | 144:ef7eb2e8f9f7 | 1344 | tx_reg = (void *)&obj->spi.spi->TXDATAX; |
<> | 144:ef7eb2e8f9f7 | 1345 | } else { |
<> | 144:ef7eb2e8f9f7 | 1346 | tx_reg = (void *)&obj->spi.spi->TXDATA; |
<> | 144:ef7eb2e8f9f7 | 1347 | } |
<> | 144:ef7eb2e8f9f7 | 1348 | |
<> | 144:ef7eb2e8f9f7 | 1349 | /* Activate TX channel */ |
<> | 144:ef7eb2e8f9f7 | 1350 | DMA_ActivateBasic(obj->spi.dmaOptionsTX.dmaChannel, |
<> | 144:ef7eb2e8f9f7 | 1351 | true, |
<> | 144:ef7eb2e8f9f7 | 1352 | false, |
<> | 144:ef7eb2e8f9f7 | 1353 | tx_reg, //When frame size > 9, point to TXDOUBLE |
<> | 144:ef7eb2e8f9f7 | 1354 | &fill_word, // When there is nothing to transmit, point to static fill word |
<> | 144:ef7eb2e8f9f7 | 1355 | length_diff - 1); |
<> | 144:ef7eb2e8f9f7 | 1356 | } else { |
<> | 144:ef7eb2e8f9f7 | 1357 | /* Nothing to do */ |
<> | 144:ef7eb2e8f9f7 | 1358 | return 0; |
<> | 144:ef7eb2e8f9f7 | 1359 | } |
<> | 144:ef7eb2e8f9f7 | 1360 | } |
<> | 144:ef7eb2e8f9f7 | 1361 | |
<> | 144:ef7eb2e8f9f7 | 1362 | /* Release the dma channels if they were opportunistically allocated */ |
<> | 144:ef7eb2e8f9f7 | 1363 | if (obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { |
<> | 144:ef7eb2e8f9f7 | 1364 | dma_channel_free(obj->spi.dmaOptionsTX.dmaChannel); |
<> | 144:ef7eb2e8f9f7 | 1365 | dma_channel_free(obj->spi.dmaOptionsRX.dmaChannel); |
<> | 144:ef7eb2e8f9f7 | 1366 | obj->spi.dmaOptionsTX.dmaUsageState = DMA_USAGE_OPPORTUNISTIC; |
<> | 144:ef7eb2e8f9f7 | 1367 | } |
<> | 144:ef7eb2e8f9f7 | 1368 | |
<> | 144:ef7eb2e8f9f7 | 1369 | /* Wait for transmit to complete, before user code is indicated */ |
<> | 144:ef7eb2e8f9f7 | 1370 | while(!(obj->spi.spi->STATUS & USART_STATUS_TXC)); |
Anna Bridge |
180:96ed750bd169 | 1371 | sleep_manager_unlock_deep_sleep(); |
<> | 144:ef7eb2e8f9f7 | 1372 | |
<> | 144:ef7eb2e8f9f7 | 1373 | /* return to CPP land to say we're finished */ |
<> | 144:ef7eb2e8f9f7 | 1374 | return SPI_EVENT_COMPLETE; |
<> | 144:ef7eb2e8f9f7 | 1375 | } else { |
<> | 144:ef7eb2e8f9f7 | 1376 | /* IRQ implementation */ |
<> | 144:ef7eb2e8f9f7 | 1377 | if (spi_master_rx_int_flag(obj)) { |
<> | 144:ef7eb2e8f9f7 | 1378 | spi_master_read_asynch(obj); |
<> | 144:ef7eb2e8f9f7 | 1379 | } |
<> | 144:ef7eb2e8f9f7 | 1380 | |
<> | 144:ef7eb2e8f9f7 | 1381 | if (spi_master_tx_int_flag(obj)) { |
<> | 144:ef7eb2e8f9f7 | 1382 | spi_master_write_asynch(obj); |
<> | 144:ef7eb2e8f9f7 | 1383 | } |
<> | 144:ef7eb2e8f9f7 | 1384 | |
<> | 144:ef7eb2e8f9f7 | 1385 | uint32_t event = spi_event_check(obj); |
<> | 144:ef7eb2e8f9f7 | 1386 | if (event & SPI_EVENT_INTERNAL_TRANSFER_COMPLETE) { |
<> | 144:ef7eb2e8f9f7 | 1387 | /* disable interrupts */ |
<> | 144:ef7eb2e8f9f7 | 1388 | spi_enable_interrupt(obj, (uint32_t)NULL, false); |
<> | 144:ef7eb2e8f9f7 | 1389 | |
<> | 144:ef7eb2e8f9f7 | 1390 | /* Wait for transmit to complete, before user code is indicated */ |
<> | 144:ef7eb2e8f9f7 | 1391 | while(!(obj->spi.spi->STATUS & USART_STATUS_TXC)); |
Anna Bridge |
180:96ed750bd169 | 1392 | sleep_manager_unlock_deep_sleep(); |
<> | 144:ef7eb2e8f9f7 | 1393 | |
<> | 144:ef7eb2e8f9f7 | 1394 | /* Return the event back to userland */ |
<> | 144:ef7eb2e8f9f7 | 1395 | return event; |
<> | 144:ef7eb2e8f9f7 | 1396 | } |
<> | 144:ef7eb2e8f9f7 | 1397 | |
<> | 144:ef7eb2e8f9f7 | 1398 | return 0; |
<> | 144:ef7eb2e8f9f7 | 1399 | } |
<> | 144:ef7eb2e8f9f7 | 1400 | } |
<> | 144:ef7eb2e8f9f7 | 1401 | #endif // LDMA_PRESENT |
<> | 144:ef7eb2e8f9f7 | 1402 | /** Abort an SPI transfer |
<> | 144:ef7eb2e8f9f7 | 1403 | * |
<> | 144:ef7eb2e8f9f7 | 1404 | * @param obj The SPI peripheral to stop |
<> | 144:ef7eb2e8f9f7 | 1405 | */ |
<> | 144:ef7eb2e8f9f7 | 1406 | void spi_abort_asynch(spi_t *obj) |
<> | 144:ef7eb2e8f9f7 | 1407 | { |
<> | 144:ef7eb2e8f9f7 | 1408 | // If we're not currently transferring, then there's nothing to do here |
<> | 144:ef7eb2e8f9f7 | 1409 | if(spi_active(obj) != 0) return; |
<> | 144:ef7eb2e8f9f7 | 1410 | |
<> | 144:ef7eb2e8f9f7 | 1411 | // Determine whether we're running DMA or interrupt |
<> | 144:ef7eb2e8f9f7 | 1412 | if (obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_ALLOCATED || obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { |
<> | 144:ef7eb2e8f9f7 | 1413 | // Cancel the DMA transfers |
<> | 144:ef7eb2e8f9f7 | 1414 | #ifdef LDMA_PRESENT |
<> | 144:ef7eb2e8f9f7 | 1415 | LDMA_StopTransfer(obj->spi.dmaOptionsTX.dmaChannel); |
<> | 144:ef7eb2e8f9f7 | 1416 | LDMA_StopTransfer(obj->spi.dmaOptionsRX.dmaChannel); |
<> | 144:ef7eb2e8f9f7 | 1417 | #else |
<> | 144:ef7eb2e8f9f7 | 1418 | DMA_ChannelEnable(obj->spi.dmaOptionsTX.dmaChannel, false); |
<> | 144:ef7eb2e8f9f7 | 1419 | DMA_ChannelEnable(obj->spi.dmaOptionsRX.dmaChannel, false); |
<> | 144:ef7eb2e8f9f7 | 1420 | #endif |
<> | 144:ef7eb2e8f9f7 | 1421 | /* Release the dma channels if they were opportunistically allocated */ |
<> | 144:ef7eb2e8f9f7 | 1422 | if (obj->spi.dmaOptionsTX.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { |
<> | 144:ef7eb2e8f9f7 | 1423 | dma_channel_free(obj->spi.dmaOptionsTX.dmaChannel); |
<> | 144:ef7eb2e8f9f7 | 1424 | dma_channel_free(obj->spi.dmaOptionsRX.dmaChannel); |
<> | 144:ef7eb2e8f9f7 | 1425 | obj->spi.dmaOptionsTX.dmaUsageState = DMA_USAGE_OPPORTUNISTIC; |
<> | 144:ef7eb2e8f9f7 | 1426 | } |
<> | 144:ef7eb2e8f9f7 | 1427 | |
<> | 144:ef7eb2e8f9f7 | 1428 | } else { |
<> | 144:ef7eb2e8f9f7 | 1429 | // Interrupt implementation: switch off interrupts |
<> | 144:ef7eb2e8f9f7 | 1430 | spi_enable_interrupt(obj, (uint32_t)NULL, false); |
<> | 144:ef7eb2e8f9f7 | 1431 | } |
<> | 144:ef7eb2e8f9f7 | 1432 | |
<> | 144:ef7eb2e8f9f7 | 1433 | // Release sleep mode block |
Anna Bridge |
180:96ed750bd169 | 1434 | sleep_manager_unlock_deep_sleep(); |
<> | 144:ef7eb2e8f9f7 | 1435 | } |
<> | 144:ef7eb2e8f9f7 | 1436 | |
<> | 144:ef7eb2e8f9f7 | 1437 | #endif |