Diff: targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.c

Revision:

167:e84263d55307

Parent:

149:156823d33999

Child:

182:a56a73fd2a6f

--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.c	Thu Jun 08 15:02:37 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.c	Wed Jun 21 17:46:44 2017 +0100
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_tim_ex.c
   * @author  MCD Application Team
-  * @version V1.5.0
-  * @date    06-May-2016
+  * @version V1.7.1
+  * @date    14-April-2017
   * @brief   TIM HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Timer extension peripheral:
@@ -69,7 +69,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -394,7 +394,7 @@
   }
   else if((htim->State == HAL_TIM_STATE_READY))
   {
-    if(((uint32_t)pData == 0U) && (Length > 0U)) 
+    if(((uint32_t)pData == 0U) && (Length > 0)) 
     {
       return HAL_ERROR;                                    
     }
@@ -701,7 +701,7 @@
   }
   else if((htim->State == HAL_TIM_STATE_READY))
   {
-    if(((uint32_t)pData == 0U) && (Length > 0U)) 
+    if(((uint32_t)pData == 0U) && (Length > 0)) 
     {
       return HAL_ERROR;                                    
     }
@@ -1119,7 +1119,7 @@
   }
   else if((htim->State == HAL_TIM_STATE_READY))
   {
-    if(((uint32_t)pData == 0U) && (Length > 0U)) 
+    if(((uint32_t)pData == 0U) && (Length > 0)) 
     {
       return HAL_ERROR;                                    
     }
@@ -1655,39 +1655,42 @@
   *         contains the BDTR Register configuration  information for the TIM peripheral. 
   * @retval HAL status
   */    
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, 
-                                              TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
 {
+  uint32_t tmpbdtr = 0U;
+  
   /* Check the parameters */
-  assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
   assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
   assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
   assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
   assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
   assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
-  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
   
-  /* Process Locked */
+  /* Check input state */
   __HAL_LOCK(htim);
   
-  htim->State = HAL_TIM_STATE_BUSY;
-
   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
-     the OSSI State, the dead time value and the Automatic Output Enable Bit */
-  htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode  | 
-                                   sBreakDeadTimeConfig->OffStateIDLEMode |
-                                   sBreakDeadTimeConfig->LockLevel        |
-                                   sBreakDeadTimeConfig->DeadTime         |
-                                   sBreakDeadTimeConfig->BreakState       |
-                                   sBreakDeadTimeConfig->BreakPolarity    |
-                                   sBreakDeadTimeConfig->AutomaticOutput;
+  the OSSI State, the dead time value and the Automatic Output Enable Bit */
   
-                                   
-  htim->State = HAL_TIM_STATE_READY;                                 
+  /* Set the BDTR bits */
+  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
+  
+  /* Set TIMx_BDTR */
+  htim->Instance->BDTR = tmpbdtr;
   
   __HAL_UNLOCK(htim);
-  
+
   return HAL_OK;
 }
 
@@ -1708,6 +1711,12 @@
   *            @arg TIM_TIM11_GPIO:     TIM11 CH4 input is connected to dedicated Timer pin(default) 
   *            @arg TIM_TIM11_HSE:      TIM11 CH4 input is connected to HSE_RTC clock
   *                                     (HSE divided by a programmable prescaler)  
+  *            @arg TIM_TIM9_TIM3_TRGO: TIM9 ITR1 input is connected to TIM3 Trigger output(default)
+  *            @arg TIM_TIM9_LPTIM:     TIM9 ITR1 input is connected to LPTIM.
+  *            @arg TIM_TIM5_TIM3_TRGO: TIM5 ITR1 input is connected to TIM3 Trigger output(default)
+  *            @arg TIM_TIM5_LPTIM:     TIM5 ITR1 input is connected to LPTIM.
+  *            @arg TIM_TIM1_TIM3_TRGO: TIM1 ITR2 input is connected to TIM3 Trigger output(default)
+  *            @arg TIM_TIM1_LPTIM:     TIM1 ITR2 input is connected to LPTIM.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
@@ -1717,10 +1726,24 @@
   /* Check parameters */
   assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
   assert_param(IS_TIM_REMAP(Remap));
-  
+
+#if defined(LPTIM_OR_TIM1_ITR2_RMP)
+  if ((Remap == TIM_TIM9_TIM3_TRGO)|| (Remap == TIM_TIM9_LPTIM)||(Remap ==TIM_TIM5_TIM3_TRGO)||\
+     (Remap == TIM_TIM5_LPTIM)||(Remap == TIM_TIM1_TIM3_TRGO)|| (Remap == TIM_TIM1_LPTIM))
+  {
+    __HAL_RCC_LPTIM1_CLK_ENABLE();
+
+    LPTIM1->OR = (Remap& 0xEFFFFFFFU);
+  }
+  else
+  {
+    /* Set the Timer remapping configuration */
+    htim->Instance->OR = Remap;
+  }
+#else
   /* Set the Timer remapping configuration */
   htim->Instance->OR = Remap;
-  
+#endif
   htim->State = HAL_TIM_STATE_READY;
   
   __HAL_UNLOCK(htim);