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Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
Diff: targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_clock.c
- Revision:
- 188:bcfe06ba3d64
- Parent:
- 154:37f96f9d4de2
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_clock.c Thu Sep 06 13:40:20 2018 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_clock.c Thu Nov 08 11:46:34 2018 +0000
@@ -67,30 +67,30 @@
#define MCG_S_CLKST_VAL ((MCG->S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT)
#define MCG_S_IREFST_VAL ((MCG->S & MCG_S_IREFST_MASK) >> MCG_S_IREFST_SHIFT)
#define MCG_S_PLLST_VAL ((MCG->S & MCG_S_PLLST_MASK) >> MCG_S_PLLST_SHIFT)
-#define MCG_C1_FRDIV_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C1) & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
-#define MCG_C2_LP_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C2) & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
-#define MCG_C2_RANGE_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C2) & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
-#define MCG_SC_FCRDIV_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->SC) & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
+#define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
+#define MCG_C2_LP_VAL ((MCG->C2 & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
+#define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
+#define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
#define MCG_S2_PLLCST_VAL ((MCG->S2 & MCG_S2_PLLCST_MASK) >> MCG_S2_PLLCST_SHIFT)
-#define MCG_C7_OSCSEL_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C7) & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT)
+#define MCG_C7_OSCSEL_VAL ((MCG->C7 & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT)
#define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
#define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
-#define MCG_C7_PLL32KREFSEL_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C7) & MCG_C7_PLL32KREFSEL_MASK) >> MCG_C7_PLL32KREFSEL_SHIFT)
-#define MCG_C5_PLLREFSEL0_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C5) & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
+#define MCG_C7_PLL32KREFSEL_VAL ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) >> MCG_C7_PLL32KREFSEL_SHIFT)
+#define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
#define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT)
#define MCG_C11_PRDIV1_VAL ((MCG->C11 & MCG_C11_PRDIV1_MASK) >> MCG_C11_PRDIV1_SHIFT)
#define MCG_C12_VDIV1_VAL ((MCG->C12 & MCG_C12_VDIV1_MASK) >> MCG_C12_VDIV1_SHIFT)
-#define MCG_C5_PRDIV0_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C5) & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
-#define MCG_C6_VDIV0_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C6) & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
+#define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
+#define MCG_C6_VDIV0_VAL ((MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
#define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
-#define SIM_CLKDIV1_OUTDIV1_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->CLKDIV1) & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)
-#define SIM_CLKDIV1_OUTDIV2_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->CLKDIV1) & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT)
-#define SIM_CLKDIV1_OUTDIV3_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->CLKDIV1) & SIM_CLKDIV1_OUTDIV3_MASK) >> SIM_CLKDIV1_OUTDIV3_SHIFT)
-#define SIM_CLKDIV1_OUTDIV4_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->CLKDIV1) & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT)
-#define SIM_SOPT1_OSC32KSEL_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->SOPT1) & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT)
-#define SIM_SOPT2_PLLFLLSEL_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->SOPT2) & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT)
+#define SIM_CLKDIV1_OUTDIV1_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)
+#define SIM_CLKDIV1_OUTDIV2_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT)
+#define SIM_CLKDIV1_OUTDIV3_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV3_MASK) >> SIM_CLKDIV1_OUTDIV3_SHIFT)
+#define SIM_CLKDIV1_OUTDIV4_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT)
+#define SIM_SOPT1_OSC32KSEL_VAL ((SIM->SOPT1 & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT)
+#define SIM_SOPT2_PLLFLLSEL_VAL ((SIM->SOPT2 & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT)
/* MCG_S_CLKST definition. */
enum _mcg_clkout_stat
@@ -491,8 +491,7 @@
void CLOCK_SetSimConfig(sim_clock_config_t const *config)
{
- __FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV1, config->clkdiv1);
-
+ SIM->CLKDIV1 = config->clkdiv1;
CLOCK_SetPllFllSelClock(config->pllFllSel);
CLOCK_SetEr32kClock(config->er32kSrc);
}
@@ -505,30 +504,30 @@
if (kCLOCK_UsbSrcExt == src)
{
- __FSL_CLOCK_SECURE_BITS_CLEAR(&SIM->SOPT2, SIM_SOPT2_USBSRC_MASK);
+ SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK;
}
else
{
switch (freq)
{
case 120000000U:
- __FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV2, SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1));
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
break;
case 96000000U:
- __FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV2, SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0));
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
break;
case 72000000U:
- __FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV2, SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1));
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
break;
case 48000000U:
- __FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV2, SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0));
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
break;
default:
ret = false;
break;
}
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK, (uint32_t)src);
+ SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src);
}
CLOCK_EnableClock(kCLOCK_Usbfs0);
@@ -575,7 +574,7 @@
uint32_t freq;
/* If FLL is not enabled currently, then return 0U. */
- if ((__FSL_CLOCK_SECURE_READ(&MCG->C2) & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK))
+ if ((MCG->C2 & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK))
{
return 0U;
}
@@ -596,7 +595,7 @@
uint32_t CLOCK_GetInternalRefClkFreq(void)
{
/* If MCGIRCLK is gated. */
- if (!(__FSL_CLOCK_SECURE_READ(&MCG->C1) & MCG_C1_IRCLKEN_MASK))
+ if (!(MCG->C1 & MCG_C1_IRCLKEN_MASK))
{
return 0U;
}
@@ -666,10 +665,10 @@
needDelay = false;
}
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C7, MCG_C7_OSCSEL_MASK, MCG_C7_OSCSEL(oscsel));
+ MCG->C7 = (MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel);
if (kMCG_OscselOsc == oscsel)
{
- if (__FSL_CLOCK_SECURE_READ(&MCG->C2) & MCG_C2_EREFS_MASK)
+ if (MCG->C2 & MCG_C2_EREFS_MASK)
{
while (!(MCG->S & MCG_S_OSCINIT0_MASK))
{
@@ -712,20 +711,20 @@
if (fcrdiv != curFcrdiv)
{
/* If fast IRC is in use currently, change to slow IRC. */
- if ((kMCG_IrcFast == curIrcs) && ((mcgOutClkState == kMCG_ClkOutStatInt) || (__FSL_CLOCK_SECURE_READ(&MCG->C1) & MCG_C1_IRCLKEN_MASK)))
+ if ((kMCG_IrcFast == curIrcs) && ((mcgOutClkState == kMCG_ClkOutStatInt) || (MCG->C1 & MCG_C1_IRCLKEN_MASK)))
{
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C2, MCG_C2_IRCS_MASK, MCG_C2_IRCS(kMCG_IrcSlow));
+ MCG->C2 = ((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow)));
while (MCG_S_IRCST_VAL != kMCG_IrcSlow)
{
}
}
/* Update FCRDIV. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->SC, MCG_SC_FCRDIV_MASK | MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK, MCG_SC_FCRDIV(fcrdiv));
+ MCG->SC = (MCG->SC & ~(MCG_SC_FCRDIV_MASK | MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK)) | MCG_SC_FCRDIV(fcrdiv);
}
/* Set internal reference clock selection. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C2, MCG_C2_IRCS_MASK, MCG_C2_IRCS(ircs));
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK, (uint8_t)enableMode);
+ MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs));
+ MCG->C1 = (MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode;
/* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */
if ((mcgOutClkState == kMCG_ClkOutStatInt) || (enableMode & kMCG_IrclkEnable))
@@ -842,12 +841,12 @@
uint8_t mcg_c5 = 0U;
mcg_c5 |= MCG_C5_PRDIV0(config->prdiv);
- __FSL_CLOCK_SECURE_WRITE(&MCG->C5, mcg_c5); /* Disable the PLL first. */
+ MCG->C5 = mcg_c5; /* Disable the PLL first. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C6, MCG_C6_VDIV0_MASK, MCG_C6_VDIV0(config->vdiv));
+ MCG->C6 = (MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv);
/* Set enable mode. */
- __FSL_CLOCK_SECURE_BITS_SET(&MCG->C5, ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode));
+ MCG->C5 |= ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode);
/* Wait for PLL lock. */
while (!(MCG->S & MCG_S_LOCK0_MASK))
@@ -862,25 +861,25 @@
if (kMCG_MonitorNone == mode)
{
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C6, MCG_C6_CME0_MASK);
+ MCG->C6 &= ~MCG_C6_CME0_MASK;
}
else
{
if (kMCG_MonitorInt == mode)
{
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LOCRE0_MASK);
+ MCG->C2 &= ~MCG_C2_LOCRE0_MASK;
}
else
{
- __FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LOCRE0_MASK);
+ MCG->C2 |= MCG_C2_LOCRE0_MASK;
}
- __FSL_CLOCK_SECURE_BITS_SET(&MCG->C6, MCG_C6_CME0_MASK);
+ MCG->C6 |= MCG_C6_CME0_MASK;
}
}
void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
{
- uint8_t mcg_c8 = __FSL_CLOCK_SECURE_READ(&MCG->C8);
+ uint8_t mcg_c8 = MCG->C8;
mcg_c8 &= ~(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK);
@@ -892,7 +891,7 @@
}
mcg_c8 |= MCG_C8_CME1_MASK;
}
- __FSL_CLOCK_SECURE_WRITE(&MCG->C8, mcg_c8);
+ MCG->C8 = mcg_c8;
}
void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
@@ -904,11 +903,11 @@
if (kMCG_MonitorNone == mode)
{
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C6, MCG_C6_LOLIE0_MASK);
+ MCG->C6 &= ~MCG_C6_LOLIE0_MASK;
}
else
{
- mcg_c8 = __FSL_CLOCK_SECURE_READ(&MCG->C8);
+ mcg_c8 = MCG->C8;
mcg_c8 &= ~MCG_C8_LOCS1_MASK;
@@ -920,8 +919,8 @@
{
mcg_c8 |= MCG_C8_LOLRE_MASK;
}
- __FSL_CLOCK_SECURE_WRITE(&MCG->C8, mcg_c8);
- __FSL_CLOCK_SECURE_BITS_SET(&MCG->C6, MCG_C6_LOLIE0_MASK);
+ MCG->C8 = mcg_c8;
+ MCG->C6 |= MCG_C6_LOLIE0_MASK;
}
}
@@ -930,7 +929,7 @@
uint32_t ret = 0U;
uint8_t mcg_s = MCG->S;
- if (__FSL_CLOCK_SECURE_READ(&MCG->SC) & MCG_SC_LOCS0_MASK)
+ if (MCG->SC & MCG_SC_LOCS0_MASK)
{
ret |= kMCG_Osc0LostFlag;
}
@@ -938,7 +937,7 @@
{
ret |= kMCG_Osc0InitFlag;
}
- if (__FSL_CLOCK_SECURE_READ(&MCG->C8) & MCG_C8_LOCS1_MASK)
+ if (MCG->C8 & MCG_C8_LOCS1_MASK)
{
ret |= kMCG_RtcOscLostFlag;
}
@@ -963,8 +962,8 @@
}
if (mask & kMCG_RtcOscLostFlag)
{
- reg = __FSL_CLOCK_SECURE_READ(&MCG->C8);
- __FSL_CLOCK_SECURE_WRITE(&MCG->C8, reg);
+ reg = MCG->C8;
+ MCG->C8 = reg;
}
if (mask & kMCG_Pll0LostFlag)
{
@@ -979,7 +978,7 @@
OSC_SetCapLoad(OSC0, config->capLoad);
OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig);
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C2, OSC_MODE_MASK, MCG_C2_RANGE(range) | (uint8_t)config->workMode);
+ MCG->C2 = ((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode);
if ((kOSC_ModeExt != config->workMode) && (OSC0->CR & OSC_CR_ERCLKEN_MASK))
{
@@ -993,7 +992,7 @@
void CLOCK_DeinitOsc0(void)
{
OSC0->CR = 0U;
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, OSC_MODE_MASK);
+ MCG->C2 &= ~OSC_MODE_MASK;
}
status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
@@ -1040,21 +1039,21 @@
MCG->ATCVL = (uint8_t)actv;
MCG->ATCVH = (uint8_t)(actv >> 8U);
- mcg_sc = __FSL_CLOCK_SECURE_READ(&MCG->SC);
+ mcg_sc = MCG->SC;
mcg_sc &= ~(MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK);
mcg_sc |= (MCG_SC_ATMF_MASK | MCG_SC_ATMS(atms));
- __FSL_CLOCK_SECURE_WRITE(&MCG->SC, (mcg_sc | MCG_SC_ATME_MASK));
+ MCG->SC = (mcg_sc | MCG_SC_ATME_MASK);
/* Wait for finished. */
- while (__FSL_CLOCK_SECURE_READ(&MCG->SC) & MCG_SC_ATME_MASK)
+ while (MCG->SC & MCG_SC_ATME_MASK)
{
}
/* Error occurs? */
- if (__FSL_CLOCK_SECURE_READ(&MCG->SC) & MCG_SC_ATMF_MASK)
+ if (MCG->SC & MCG_SC_ATMF_MASK)
{
/* Clear the failed flag. */
- __FSL_CLOCK_SECURE_WRITE(&MCG->SC, mcg_sc);
+ MCG->SC = mcg_sc;
return kStatus_MCG_AtmHardwareFail;
}
@@ -1201,7 +1200,7 @@
/* Set CLKS and IREFS. */
MCG->C1 =
- ((__FSL_CLOCK_SECURE_READ(&MCG->C1) & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */
+ ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */
| MCG_C1_IREFS(kMCG_FllSrcInternal)); /* IREFS = 1 */
/* Wait and check status. */
@@ -1260,7 +1259,7 @@
}
/* Set CLKS and IREFS. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK,
+ MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) |
(MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */
| MCG_C1_FRDIV(frdiv) /* FRDIV */
| MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
@@ -1317,7 +1316,7 @@
mcg_c4 = MCG->C4;
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK); /* Disable lowpower. */
+ MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
/*
Errata: ERR007993
@@ -1333,8 +1332,8 @@
}
/* Set CLKS and IREFS. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK,
- (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */
+ MCG->C1 =
+ ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */
| MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
/* Wait and check status. */
@@ -1378,13 +1377,13 @@
#endif
/* Change to FLL mode. */
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C6, MCG_C6_PLLS_MASK);
+ MCG->C6 &= ~MCG_C6_PLLS_MASK;
while (MCG->S & MCG_S_PLLST_MASK)
{
}
/* Set LP bit to enable the FLL */
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK);
+ MCG->C2 &= ~MCG_C2_LP_MASK;
mcg_c4 = MCG->C4;
@@ -1402,7 +1401,7 @@
}
/* Set CLKS and IREFS. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK,
+ MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) |
(MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */
| MCG_C1_FRDIV(frdiv) /* FRDIV = frdiv */
| MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
@@ -1445,7 +1444,7 @@
#endif /* MCG_CONFIG_CHECK_PARAM */
/* Set LP. */
- __FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LP_MASK);
+ MCG->C2 |= MCG_C2_LP_MASK;
return kStatus_Success;
}
@@ -1460,7 +1459,7 @@
#endif
/* Set LP bit to enter BLPE mode. */
- __FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LP_MASK);
+ MCG->C2 |= MCG_C2_LP_MASK;
return kStatus_Success;
}
@@ -1473,10 +1472,10 @@
This function is designed to change MCG to PBE mode from PEE/BLPE/FBE,
but with this workflow, the source mode could be all modes except PEI/PBI.
*/
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK); /* Disable lowpower. */
+ MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
/* Change to use external clock first. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
+ MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
/* Wait for CLKST clock status bits to show clock source is ext ref clk */
while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
@@ -1485,7 +1484,7 @@
}
/* Disable PLL first, then configure PLL. */
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C6, MCG_C6_PLLS_MASK);
+ MCG->C6 &= ~MCG_C6_PLLS_MASK;
while (MCG->S & MCG_S_PLLST_MASK)
{
}
@@ -1496,7 +1495,7 @@
}
/* Change to PLL mode. */
- __FSL_CLOCK_SECURE_BITS_SET(&MCG->C6, MCG_C6_PLLS_MASK);
+ MCG->C6 |= MCG_C6_PLLS_MASK;
/* Wait for PLL mode changed. */
while (!(MCG->S & MCG_S_PLLST_MASK))
@@ -1517,7 +1516,7 @@
#endif
/* Change to use PLL/FLL output clock first. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcOut));
+ MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut);
/* Wait for clock status bits to update */
while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll)
@@ -1537,15 +1536,15 @@
#endif /* MCG_CONFIG_CHECK_PARAM */
/* Disable low power */
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK);
+ MCG->C2 &= ~MCG_C2_LP_MASK;
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
+ MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt)
{
}
/* Disable PLL. */
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C6, MCG_C6_PLLS_MASK);
+ MCG->C6 &= ~MCG_C6_PLLS_MASK;
while (MCG->S & MCG_S_PLLST_MASK)
{
}
@@ -1563,9 +1562,9 @@
#endif
/* Disable low power */
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK);
+ MCG->C2 &= ~MCG_C2_LP_MASK;
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
+ MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt)
{
}
@@ -1592,13 +1591,13 @@
CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv);
/* If reset mode is not BLPI, first enter FBI mode. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
+ MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal);
while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt)
{
}
/* Enter BLPI mode. */
- __FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LP_MASK);
+ MCG->C2 |= MCG_C2_LP_MASK;
return kStatus_Success;
}
@@ -1608,8 +1607,8 @@
CLOCK_SetExternalRefClkConfig(oscsel);
/* Set to FBE mode. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK,
- (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */
+ MCG->C1 =
+ ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */
| MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
/* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */
@@ -1619,7 +1618,7 @@
}
/* In FBE now, start to enter BLPE. */
- __FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LP_MASK);
+ MCG->C2 |= MCG_C2_LP_MASK;
return kStatus_Success;
}
@@ -1633,7 +1632,7 @@
CLOCK_SetPbeMode(pllcs, config);
/* Change to use PLL output clock. */
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcOut));
+ MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut);
while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll)
{
}
@@ -1693,7 +1692,7 @@
/* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */
if (MCG_S_CLKST_VAL == kMCG_ClkOutStatInt)
{
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK); /* Disable lowpower. */
+ MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
{
CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
@@ -1739,7 +1738,7 @@
}
else
{
- __FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
+ MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt)
{
}
@@ -1763,7 +1762,7 @@
}
else
{
- __FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C5, (uint32_t)kMCG_PllEnableIndependent);
+ MCG->C5 &= ~(uint32_t)kMCG_PllEnableIndependent;
}
return kStatus_Success;
}
