Diff: targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h

Revision:

178:79309dc6340a

Parent:

159:612c381a210f

--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h	Wed Nov 08 13:50:44 2017 +0000
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h	Thu Nov 23 11:57:25 2017 +0000
@@ -48,7 +48,6 @@
 #define I2C_SPEED_400K_AT_8MHZ     (uint8_t)0x03
 #define I2C_SPEED_400K_AT_16MHZ    (uint8_t)0x08
 
-
 /* I2C commands */
 #define I2C_CMD_NULL          0x00
 #define I2C_CMD_WDAT0         0x10
@@ -93,7 +92,10 @@
 #define I2C_API_STATUS_SUCCESS    0
 #define PAD_REG_ADRS_BYTE_SIZE    4
 
-#define SEND_COMMAND(cmd)  while(!I2C_FIFO_EMPTY); wait_us(1); obj->membase->CMD_REG = cmd;
+// The wait_us(0) command is needed so the I2C state machines have enough
+// time for data to settle across all clock domain crossings in their
+// synchronizers, both directions.
+#define SEND_COMMAND(cmd) wait_us(0); obj->membase->CMD_REG = cmd; wait_us(0);
 
 /** Init I2C device.
  * @details
@@ -158,4 +160,4 @@
  */
 extern int32_t fI2cWriteB(i2c_t *d, const char *buf, int len);
 
-#endif /* I2C_H_ */
\ No newline at end of file
+#endif /* I2C_H_ */